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i387: Uninline the generic FP helpers that we expose to kernel modules
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
313a3dc7 30
18068523 31#include <linux/clocksource.h>
4d5c5d0f 32#include <linux/interrupt.h>
313a3dc7
CO		 33#include <linux/kvm.h>
34#include <linux/fs.h>
35#include <linux/vmalloc.h>
5fb76f9b 36#include <linux/module.h>
0de10343 37#include <linux/mman.h>
2bacc55c 38#include <linux/highmem.h>
19de40a8 39#include <linux/iommu.h>
62c476c7 40#include <linux/intel-iommu.h>
c8076604 41#include <linux/cpufreq.h>
18863bdd 42#include <linux/user-return-notifier.h>
a983fb23 43#include <linux/srcu.h>
5a0e3ad6 44#include <linux/slab.h>
ff9d07a0 45#include <linux/perf_event.h>
7bee342a 46#include <linux/uaccess.h>
af585b92 47#include <linux/hash.h>
a1b60c1c 48#include <linux/pci.h>
aec51dc4 49#include <trace/events/kvm.h>
2ed152af 50
229456fc
MT		 51#define CREATE_TRACE_POINTS
52#include "trace.h"
043405e1 53
24f1e32c 54#include <asm/debugreg.h>
d825ed0a 55#include <asm/msr.h>
a5f61300 56#include <asm/desc.h>
0bed3b56 57#include <asm/mtrr.h>
890ca9ae 58#include <asm/mce.h>
7cf30855 59#include <asm/i387.h>
98918833 60#include <asm/xcr.h>
1d5f066e 61#include <asm/pvclock.h>
217fc9cf 62#include <asm/div64.h>
043405e1 63
313a3dc7 64#define MAX_IO_MSRS 256
890ca9ae 65#define KVM_MAX_MCE_BANKS 32
5854dbca 66#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 67
0f65dd70
AK		 68#define emul_to_vcpu(ctxt) \
69 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
70
50a37eb4
JR		 71/* EFER defaults:
72 * - enable syscall per default because its emulated by KVM
73 * - enable LME and LMA per default on 64 bit KVM
74 */
75#ifdef CONFIG_X86_64
1260edbe
LJ		 76static
77u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 78#else
1260edbe 79static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 80#endif
313a3dc7 81
ba1389b7
AK		 82#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
83#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 84
cb142eb7 85static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 86static void process_nmi(struct kvm_vcpu *vcpu);
674eea0f 87
97896d04 88struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 89EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 90
476bc001
RR		 91static bool ignore_msrs = 0;
92module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 93
92a1f12d
JR		 94bool kvm_has_tsc_control;
95EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
96u32 kvm_max_guest_tsc_khz;
97EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
98
18863bdd
AK		 99#define KVM_NR_SHARED_MSRS 16
100
101struct kvm_shared_msrs_global {
102 int nr;
2bf78fa7 103 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 104};
105
106struct kvm_shared_msrs {
107 struct user_return_notifier urn;
108 bool registered;
2bf78fa7
SY		 109 struct kvm_shared_msr_values {
110 u64 host;
111 u64 curr;
112 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 113};
114
115static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
116static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
117
417bc304 118struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 119 { "pf_fixed", VCPU_STAT(pf_fixed) },
120 { "pf_guest", VCPU_STAT(pf_guest) },
121 { "tlb_flush", VCPU_STAT(tlb_flush) },
122 { "invlpg", VCPU_STAT(invlpg) },
123 { "exits", VCPU_STAT(exits) },
124 { "io_exits", VCPU_STAT(io_exits) },
125 { "mmio_exits", VCPU_STAT(mmio_exits) },
126 { "signal_exits", VCPU_STAT(signal_exits) },
127 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 128 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 129 { "halt_exits", VCPU_STAT(halt_exits) },
130 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 131 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 132 { "request_irq", VCPU_STAT(request_irq_exits) },
133 { "irq_exits", VCPU_STAT(irq_exits) },
134 { "host_state_reload", VCPU_STAT(host_state_reload) },
135 { "efer_reload", VCPU_STAT(efer_reload) },
136 { "fpu_reload", VCPU_STAT(fpu_reload) },
137 { "insn_emulation", VCPU_STAT(insn_emulation) },
138 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 139 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 140 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 141 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
142 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
143 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
144 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
145 { "mmu_flooded", VM_STAT(mmu_flooded) },
146 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 147 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 148 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 149 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 150 { "largepages", VM_STAT(lpages) },
417bc304
HB		 151 { NULL }
152};
153
2acf923e
DC		 154u64 __read_mostly host_xcr0;
155
d6aa1000
AK		 156int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
157
af585b92
GN		 158static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
159{
160 int i;
161 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
162 vcpu->arch.apf.gfns[i] = ~0;
163}
164
18863bdd
AK		 165static void kvm_on_user_return(struct user_return_notifier *urn)
166{
167 unsigned slot;
18863bdd
AK		 168 struct kvm_shared_msrs *locals
169 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 170 struct kvm_shared_msr_values *values;
18863bdd
AK		 171
172 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 173 values = &locals->values[slot];
174 if (values->host != values->curr) {
175 wrmsrl(shared_msrs_global.msrs[slot], values->host);
176 values->curr = values->host;
18863bdd
AK		 177 }
178 }
179 locals->registered = false;
180 user_return_notifier_unregister(urn);
181}
182
2bf78fa7 183static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 184{
2bf78fa7 185 struct kvm_shared_msrs *smsr;
18863bdd
AK		 186 u64 value;
187
2bf78fa7
SY		 188 smsr = &__get_cpu_var(shared_msrs);
189 /* only read, and nobody should modify it at this time,
190 * so don't need lock */
191 if (slot >= shared_msrs_global.nr) {
192 printk(KERN_ERR "kvm: invalid MSR slot!");
193 return;
194 }
195 rdmsrl_safe(msr, &value);
196 smsr->values[slot].host = value;
197 smsr->values[slot].curr = value;
198}
199
200void kvm_define_shared_msr(unsigned slot, u32 msr)
201{
18863bdd
AK		 202 if (slot >= shared_msrs_global.nr)
203 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 204 shared_msrs_global.msrs[slot] = msr;
205 /* we need ensured the shared_msr_global have been updated */
206 smp_wmb();
18863bdd
AK		 207}
208EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
209
210static void kvm_shared_msr_cpu_online(void)
211{
212 unsigned i;
18863bdd
AK		 213
214 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 215 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 216}
217
d5696725 218void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 219{
220 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
221
2bf78fa7 222 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 223 return;
2bf78fa7
SY		 224 smsr->values[slot].curr = value;
225 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 226 if (!smsr->registered) {
227 smsr->urn.on_user_return = kvm_on_user_return;
228 user_return_notifier_register(&smsr->urn);
229 smsr->registered = true;
230 }
231}
232EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
233
3548bab5
AK		 234static void drop_user_return_notifiers(void *ignore)
235{
236 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
237
238 if (smsr->registered)
239 kvm_on_user_return(&smsr->urn);
240}
241
6866b83e
CO		 242u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
243{
244 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 245 return vcpu->arch.apic_base;
6866b83e 246 else
ad312c7c 247 return vcpu->arch.apic_base;
6866b83e
CO		 248}
249EXPORT_SYMBOL_GPL(kvm_get_apic_base);
250
251void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
252{
253 /* TODO: reserve bits check */
254 if (irqchip_in_kernel(vcpu->kvm))
255 kvm_lapic_set_base(vcpu, data);
256 else
ad312c7c 257 vcpu->arch.apic_base = data;
6866b83e
CO		 258}
259EXPORT_SYMBOL_GPL(kvm_set_apic_base);
260
3fd28fce
ED		 261#define EXCPT_BENIGN 0
262#define EXCPT_CONTRIBUTORY 1
263#define EXCPT_PF 2
264
265static int exception_class(int vector)
266{
267 switch (vector) {
268 case PF_VECTOR:
269 return EXCPT_PF;
270 case DE_VECTOR:
271 case TS_VECTOR:
272 case NP_VECTOR:
273 case SS_VECTOR:
274 case GP_VECTOR:
275 return EXCPT_CONTRIBUTORY;
276 default:
277 break;
278 }
279 return EXCPT_BENIGN;
280}
281
282static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 283 unsigned nr, bool has_error, u32 error_code,
284 bool reinject)
3fd28fce
ED		 285{
286 u32 prev_nr;
287 int class1, class2;
288
3842d135
AK		 289 kvm_make_request(KVM_REQ_EVENT, vcpu);
290
3fd28fce
ED		 291 if (!vcpu->arch.exception.pending) {
292 queue:
293 vcpu->arch.exception.pending = true;
294 vcpu->arch.exception.has_error_code = has_error;
295 vcpu->arch.exception.nr = nr;
296 vcpu->arch.exception.error_code = error_code;
3f0fd292 297 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 298 return;
299 }
300
301 /* to check exception */
302 prev_nr = vcpu->arch.exception.nr;
303 if (prev_nr == DF_VECTOR) {
304 /* triple fault -> shutdown */
a8eeb04a 305 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 306 return;
307 }
308 class1 = exception_class(prev_nr);
309 class2 = exception_class(nr);
310 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
311 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
312 /* generate double fault per SDM Table 5-5 */
313 vcpu->arch.exception.pending = true;
314 vcpu->arch.exception.has_error_code = true;
315 vcpu->arch.exception.nr = DF_VECTOR;
316 vcpu->arch.exception.error_code = 0;
317 } else
318 /* replace previous exception with a new one in a hope
319 that instruction re-execution will regenerate lost
320 exception */
321 goto queue;
322}
323
298101da
AK		 324void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
325{
ce7ddec4 326 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 327}
328EXPORT_SYMBOL_GPL(kvm_queue_exception);
329
ce7ddec4
JR		 330void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
331{
332 kvm_multiple_exception(vcpu, nr, false, 0, true);
333}
334EXPORT_SYMBOL_GPL(kvm_requeue_exception);
335
db8fcefa 336void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 337{
db8fcefa
AP		 338 if (err)
339 kvm_inject_gp(vcpu, 0);
340 else
341 kvm_x86_ops->skip_emulated_instruction(vcpu);
342}
343EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 344
6389ee94 345void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 346{
347 ++vcpu->stat.pf_guest;
6389ee94
AK		 348 vcpu->arch.cr2 = fault->address;
349 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 350}
27d6c865 351EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 352
6389ee94 353void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 354{
6389ee94
AK		 355 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
356 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 357 else
6389ee94 358 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
d4f8cf66
JR		 359}
360
3419ffc8
SY		 361void kvm_inject_nmi(struct kvm_vcpu *vcpu)
362{
7460fb4a
AK		 363 atomic_inc(&vcpu->arch.nmi_queued);
364 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 365}
366EXPORT_SYMBOL_GPL(kvm_inject_nmi);
367
298101da
AK		 368void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
369{
ce7ddec4 370 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 371}
372EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
373
ce7ddec4
JR		 374void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
375{
376 kvm_multiple_exception(vcpu, nr, true, error_code, true);
377}
378EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
379
0a79b009
AK		 380/*
381 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
382 * a #GP and return false.
383 */
384bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 385{
0a79b009
AK		 386 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
387 return true;
388 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
389 return false;
298101da 390}
0a79b009 391EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 392
ec92fe44
JR		 393/*
394 * This function will be used to read from the physical memory of the currently
395 * running guest. The difference to kvm_read_guest_page is that this function
396 * can read from guest physical or from the guest's guest physical memory.
397 */
398int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
399 gfn_t ngfn, void *data, int offset, int len,
400 u32 access)
401{
402 gfn_t real_gfn;
403 gpa_t ngpa;
404
405 ngpa = gfn_to_gpa(ngfn);
406 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
407 if (real_gfn == UNMAPPED_GVA)
408 return -EFAULT;
409
410 real_gfn = gpa_to_gfn(real_gfn);
411
412 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
413}
414EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
415
3d06b8bf
JR		 416int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
417 void *data, int offset, int len, u32 access)
418{
419 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
420 data, offset, len, access);
421}
422
a03490ed
CO		 423/*
424 * Load the pae pdptrs. Return true is they are all valid.
425 */
ff03a073 426int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 427{
428 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
429 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
430 int i;
431 int ret;
ff03a073 432 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 433
ff03a073
JR		 434 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
435 offset * sizeof(u64), sizeof(pdpte),
436 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 437 if (ret < 0) {
438 ret = 0;
439 goto out;
440 }
441 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 442 if (is_present_gpte(pdpte[i]) &&
20c466b5 443 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 444 ret = 0;
445 goto out;
446 }
447 }
448 ret = 1;
449
ff03a073 450 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 451 __set_bit(VCPU_EXREG_PDPTR,
452 (unsigned long *)&vcpu->arch.regs_avail);
453 __set_bit(VCPU_EXREG_PDPTR,
454 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 455out:
a03490ed
CO		 456
457 return ret;
458}
cc4b6871 459EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 460
d835dfec
AK		 461static bool pdptrs_changed(struct kvm_vcpu *vcpu)
462{
ff03a073 463 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 464 bool changed = true;
3d06b8bf
JR		 465 int offset;
466 gfn_t gfn;
d835dfec
AK		 467 int r;
468
469 if (is_long_mode(vcpu) || !is_pae(vcpu))
470 return false;
471
6de4f3ad
AK		 472 if (!test_bit(VCPU_EXREG_PDPTR,
473 (unsigned long *)&vcpu->arch.regs_avail))
474 return true;
475
9f8fe504
AK		 476 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
477 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 478 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
479 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 480 if (r < 0)
481 goto out;
ff03a073 482 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 483out:
d835dfec
AK		 484
485 return changed;
486}
487
49a9b07e 488int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 489{
aad82703
SY		 490 unsigned long old_cr0 = kvm_read_cr0(vcpu);
491 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
492 X86_CR0_CD | X86_CR0_NW;
493
f9a48e6a
AK		 494 cr0 |= X86_CR0_ET;
495
ab344828 496#ifdef CONFIG_X86_64
0f12244f
GN		 497 if (cr0 & 0xffffffff00000000UL)
498 return 1;
ab344828
GN		 499#endif
500
501 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 502
0f12244f
GN		 503 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
504 return 1;
a03490ed 505
0f12244f
GN		 506 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
507 return 1;
a03490ed
CO		 508
509 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
510#ifdef CONFIG_X86_64
f6801dff 511 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 512 int cs_db, cs_l;
513
0f12244f
GN		 514 if (!is_pae(vcpu))
515 return 1;
a03490ed 516 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 517 if (cs_l)
518 return 1;
a03490ed
CO		 519 } else
520#endif
ff03a073 521 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 522 kvm_read_cr3(vcpu)))
0f12244f 523 return 1;
a03490ed
CO		 524 }
525
526 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 527
d170c419 528 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 529 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 530 kvm_async_pf_hash_reset(vcpu);
531 }
e5f3f027 532
aad82703
SY		 533 if ((cr0 ^ old_cr0) & update_bits)
534 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 535 return 0;
536}
2d3ad1f4 537EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 538
2d3ad1f4 539void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 540{
49a9b07e 541 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 542}
2d3ad1f4 543EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 544
2acf923e
DC		 545int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
546{
547 u64 xcr0;
548
549 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
550 if (index != XCR_XFEATURE_ENABLED_MASK)
551 return 1;
552 xcr0 = xcr;
553 if (kvm_x86_ops->get_cpl(vcpu) != 0)
554 return 1;
555 if (!(xcr0 & XSTATE_FP))
556 return 1;
557 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
558 return 1;
559 if (xcr0 & ~host_xcr0)
560 return 1;
561 vcpu->arch.xcr0 = xcr0;
562 vcpu->guest_xcr0_loaded = 0;
563 return 0;
564}
565
566int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
567{
568 if (__kvm_set_xcr(vcpu, index, xcr)) {
569 kvm_inject_gp(vcpu, 0);
570 return 1;
571 }
572 return 0;
573}
574EXPORT_SYMBOL_GPL(kvm_set_xcr);
575
a83b29c6 576int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 577{
fc78f519 578 unsigned long old_cr4 = kvm_read_cr4(vcpu);
c68b734f
YW		 579 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
580 X86_CR4_PAE | X86_CR4_SMEP;
0f12244f
GN		 581 if (cr4 & CR4_RESERVED_BITS)
582 return 1;
a03490ed 583
2acf923e
DC		 584 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
585 return 1;
586
c68b734f
YW		 587 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
588 return 1;
589
74dc2b4f
YW		 590 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_RDWRGSFS))
591 return 1;
592
a03490ed 593 if (is_long_mode(vcpu)) {
0f12244f
GN		 594 if (!(cr4 & X86_CR4_PAE))
595 return 1;
a2edf57f
AK		 596 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
597 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 598 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
599 kvm_read_cr3(vcpu)))
0f12244f
GN		 600 return 1;
601
5e1746d6 602 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 603 return 1;
a03490ed 604
aad82703
SY		 605 if ((cr4 ^ old_cr4) & pdptr_bits)
606 kvm_mmu_reset_context(vcpu);
0f12244f 607
2acf923e 608 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 609 kvm_update_cpuid(vcpu);
2acf923e 610
0f12244f
GN		 611 return 0;
612}
2d3ad1f4 613EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 614
2390218b 615int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 616{
9f8fe504 617 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 618 kvm_mmu_sync_roots(vcpu);
d835dfec 619 kvm_mmu_flush_tlb(vcpu);
0f12244f 620 return 0;
d835dfec
AK		 621 }
622
a03490ed 623 if (is_long_mode(vcpu)) {
0f12244f
GN		 624 if (cr3 & CR3_L_MODE_RESERVED_BITS)
625 return 1;
a03490ed
CO		 626 } else {
627 if (is_pae(vcpu)) {
0f12244f
GN		 628 if (cr3 & CR3_PAE_RESERVED_BITS)
629 return 1;
ff03a073
JR		 630 if (is_paging(vcpu) &&
631 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
0f12244f 632 return 1;
a03490ed
CO		 633 }
634 /*
635 * We don't check reserved bits in nonpae mode, because
636 * this isn't enforced, and VMware depends on this.
637 */
638 }
639
a03490ed
CO		 640 /*
641 * Does the new cr3 value map to physical memory? (Note, we
642 * catch an invalid cr3 even in real-mode, because it would
643 * cause trouble later on when we turn on paging anyway.)
644 *
645 * A real CPU would silently accept an invalid cr3 and would
646 * attempt to use it - with largely undefined (and often hard
647 * to debug) behavior on the guest side.
648 */
649 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
0f12244f
GN		 650 return 1;
651 vcpu->arch.cr3 = cr3;
aff48baa 652 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
0f12244f
GN		 653 vcpu->arch.mmu.new_cr3(vcpu);
654 return 0;
655}
2d3ad1f4 656EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 657
eea1cff9 658int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 659{
0f12244f
GN		 660 if (cr8 & CR8_RESERVED_BITS)
661 return 1;
a03490ed
CO		 662 if (irqchip_in_kernel(vcpu->kvm))
663 kvm_lapic_set_tpr(vcpu, cr8);
664 else
ad312c7c 665 vcpu->arch.cr8 = cr8;
0f12244f
GN		 666 return 0;
667}
2d3ad1f4 668EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 669
2d3ad1f4 670unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 671{
672 if (irqchip_in_kernel(vcpu->kvm))
673 return kvm_lapic_get_cr8(vcpu);
674 else
ad312c7c 675 return vcpu->arch.cr8;
a03490ed 676}
2d3ad1f4 677EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 678
338dbc97 679static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 680{
681 switch (dr) {
682 case 0 ... 3:
683 vcpu->arch.db[dr] = val;
684 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
685 vcpu->arch.eff_db[dr] = val;
686 break;
687 case 4:
338dbc97
GN		 688 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
689 return 1; /* #UD */
020df079
GN		 690 /* fall through */
691 case 6:
338dbc97
GN		 692 if (val & 0xffffffff00000000ULL)
693 return -1; /* #GP */
020df079
GN		 694 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
695 break;
696 case 5:
338dbc97
GN		 697 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
698 return 1; /* #UD */
020df079
GN		 699 /* fall through */
700 default: /* 7 */
338dbc97
GN		 701 if (val & 0xffffffff00000000ULL)
702 return -1; /* #GP */
020df079
GN		 703 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
704 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
705 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
706 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
707 }
708 break;
709 }
710
711 return 0;
712}
338dbc97
GN		 713
714int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
715{
716 int res;
717
718 res = __kvm_set_dr(vcpu, dr, val);
719 if (res > 0)
720 kvm_queue_exception(vcpu, UD_VECTOR);
721 else if (res < 0)
722 kvm_inject_gp(vcpu, 0);
723
724 return res;
725}
020df079
GN		 726EXPORT_SYMBOL_GPL(kvm_set_dr);
727
338dbc97 728static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 729{
730 switch (dr) {
731 case 0 ... 3:
732 *val = vcpu->arch.db[dr];
733 break;
734 case 4:
338dbc97 735 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 736 return 1;
020df079
GN		 737 /* fall through */
738 case 6:
739 *val = vcpu->arch.dr6;
740 break;
741 case 5:
338dbc97 742 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 743 return 1;
020df079
GN		 744 /* fall through */
745 default: /* 7 */
746 *val = vcpu->arch.dr7;
747 break;
748 }
749
750 return 0;
751}
338dbc97
GN		 752
753int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
754{
755 if (_kvm_get_dr(vcpu, dr, val)) {
756 kvm_queue_exception(vcpu, UD_VECTOR);
757 return 1;
758 }
759 return 0;
760}
020df079
GN		 761EXPORT_SYMBOL_GPL(kvm_get_dr);
762
022cd0e8
AK		 763bool kvm_rdpmc(struct kvm_vcpu *vcpu)
764{
765 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
766 u64 data;
767 int err;
768
769 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
770 if (err)
771 return err;
772 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
773 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
774 return err;
775}
776EXPORT_SYMBOL_GPL(kvm_rdpmc);
777
043405e1
CO		 778/*
779 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
780 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
781 *
782 * This list is modified at module load time to reflect the
e3267cbb
GC		 783 * capabilities of the host cpu. This capabilities test skips MSRs that are
784 * kvm-specific. Those are put in the beginning of the list.
043405e1 785 */
e3267cbb 786
c9aaa895 787#define KVM_SAVE_MSRS_BEGIN 9
043405e1 788static u32 msrs_to_save[] = {
e3267cbb 789 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 790 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 791 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
c9aaa895 792 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
043405e1 793 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 794 MSR_STAR,
043405e1
CO		 795#ifdef CONFIG_X86_64
796 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
797#endif
e90aa41e 798 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 799};
800
801static unsigned num_msrs_to_save;
802
803static u32 emulated_msrs[] = {
a3e06bbe 804 MSR_IA32_TSCDEADLINE,
043405e1 805 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 806 MSR_IA32_MCG_STATUS,
807 MSR_IA32_MCG_CTL,
043405e1
CO		 808};
809
b69e8cae 810static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 811{
aad82703
SY		 812 u64 old_efer = vcpu->arch.efer;
813
b69e8cae
RJ		 814 if (efer & efer_reserved_bits)
815 return 1;
15c4a640
CO		 816
817 if (is_paging(vcpu)
b69e8cae
RJ		 818 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
819 return 1;
15c4a640 820
1b2fd70c
AG		 821 if (efer & EFER_FFXSR) {
822 struct kvm_cpuid_entry2 *feat;
823
824 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 825 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
826 return 1;
1b2fd70c
AG		 827 }
828
d8017474
AG		 829 if (efer & EFER_SVME) {
830 struct kvm_cpuid_entry2 *feat;
831
832 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 833 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
834 return 1;
d8017474
AG		 835 }
836
15c4a640 837 efer &= ~EFER_LMA;
f6801dff 838 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 839
a3d204e2
SY		 840 kvm_x86_ops->set_efer(vcpu, efer);
841
9645bb56 842 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
b69e8cae 843
aad82703
SY		 844 /* Update reserved bits */
845 if ((efer ^ old_efer) & EFER_NX)
846 kvm_mmu_reset_context(vcpu);
847
b69e8cae 848 return 0;
15c4a640
CO		 849}
850
f2b4b7dd
JR		 851void kvm_enable_efer_bits(u64 mask)
852{
853 efer_reserved_bits &= ~mask;
854}
855EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
856
857
15c4a640
CO		 858/*
859 * Writes msr value into into the appropriate "register".
860 * Returns 0 on success, non-0 otherwise.
861 * Assumes vcpu_load() was already called.
862 */
863int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
864{
865 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
866}
867
313a3dc7
CO		 868/*
869 * Adapt set_msr() to msr_io()'s calling convention
870 */
871static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
872{
873 return kvm_set_msr(vcpu, index, *data);
874}
875
18068523
GOC		 876static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
877{
9ed3c444
AK		 878 int version;
879 int r;
50d0a0f9 880 struct pvclock_wall_clock wc;
923de3cf 881 struct timespec boot;
18068523
GOC		 882
883 if (!wall_clock)
884 return;
885
9ed3c444
AK		 886 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
887 if (r)
888 return;
889
890 if (version & 1)
891 ++version; /* first time write, random junk */
892
893 ++version;
18068523 894
18068523
GOC		 895 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
896
50d0a0f9
GH		 897 /*
898 * The guest calculates current wall clock time by adding
34c238a1 899 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 900 * wall clock specified here. guest system time equals host
901 * system time for us, thus we must fill in host boot time here.
902 */
923de3cf 903 getboottime(&boot);
50d0a0f9
GH		 904
905 wc.sec = boot.tv_sec;
906 wc.nsec = boot.tv_nsec;
907 wc.version = version;
18068523
GOC		 908
909 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
910
911 version++;
912 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 913}
914
50d0a0f9
GH		 915static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
916{
917 uint32_t quotient, remainder;
918
919 /* Don't try to replace with do_div(), this one calculates
920 * "(dividend << 32) / divisor" */
921 __asm__ ( "divl %4"
922 : "=a" (quotient), "=d" (remainder)
923 : "0" (0), "1" (dividend), "r" (divisor) );
924 return quotient;
925}
926
5f4e3f88
ZA		 927static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
928 s8 *pshift, u32 *pmultiplier)
50d0a0f9 929{
5f4e3f88 930 uint64_t scaled64;
50d0a0f9
GH		 931 int32_t shift = 0;
932 uint64_t tps64;
933 uint32_t tps32;
934
5f4e3f88
ZA		 935 tps64 = base_khz * 1000LL;
936 scaled64 = scaled_khz * 1000LL;
50933623 937 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 938 tps64 >>= 1;
939 shift--;
940 }
941
942 tps32 = (uint32_t)tps64;
50933623
JK		 943 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
944 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 945 scaled64 >>= 1;
946 else
947 tps32 <<= 1;
50d0a0f9
GH		 948 shift++;
949 }
950
5f4e3f88
ZA		 951 *pshift = shift;
952 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 953
5f4e3f88
ZA		 954 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
955 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 956}
957
759379dd
ZA		 958static inline u64 get_kernel_ns(void)
959{
960 struct timespec ts;
961
962 WARN_ON(preemptible());
963 ktime_get_ts(&ts);
964 monotonic_to_bootbased(&ts);
965 return timespec_to_ns(&ts);
50d0a0f9
GH		 966}
967
c8076604 968static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 969unsigned long max_tsc_khz;
c8076604 970
8cfdc000
ZA		 971static inline int kvm_tsc_changes_freq(void)
972{
973 int cpu = get_cpu();
974 int ret = !boot_cpu_has(X86_FEATURE_CONSTANT_TSC) &&
975 cpufreq_quick_get(cpu) != 0;
976 put_cpu();
977 return ret;
978}
979
a3e06bbe 980u64 vcpu_tsc_khz(struct kvm_vcpu *vcpu)
1e993611
JR		 981{
982 if (vcpu->arch.virtual_tsc_khz)
983 return vcpu->arch.virtual_tsc_khz;
984 else
985 return __this_cpu_read(cpu_tsc_khz);
986}
987
857e4099 988static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
759379dd 989{
217fc9cf
AK		 990 u64 ret;
991
759379dd
ZA		 992 WARN_ON(preemptible());
993 if (kvm_tsc_changes_freq())
994 printk_once(KERN_WARNING
995 "kvm: unreliable cycle conversion on adjustable rate TSC\n");
857e4099 996 ret = nsec * vcpu_tsc_khz(vcpu);
217fc9cf
AK		 997 do_div(ret, USEC_PER_SEC);
998 return ret;
759379dd
ZA		 999}
1000
1e993611 1001static void kvm_init_tsc_catchup(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
c285545f
ZA		 1002{
1003 /* Compute a scale to convert nanoseconds in TSC cycles */
1004 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
1e993611
JR		 1005 &vcpu->arch.tsc_catchup_shift,
1006 &vcpu->arch.tsc_catchup_mult);
c285545f
ZA		 1007}
1008
1009static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1010{
1011 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.last_tsc_nsec,
1e993611
JR		 1012 vcpu->arch.tsc_catchup_mult,
1013 vcpu->arch.tsc_catchup_shift);
c285545f
ZA		 1014 tsc += vcpu->arch.last_tsc_write;
1015 return tsc;
1016}
1017
99e3e30a
ZA		 1018void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
1019{
1020 struct kvm *kvm = vcpu->kvm;
f38e098f 1021 u64 offset, ns, elapsed;
99e3e30a 1022 unsigned long flags;
46543ba4 1023 s64 sdiff;
99e3e30a 1024
038f8c11 1025 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1026 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1027 ns = get_kernel_ns();
f38e098f 1028 elapsed = ns - kvm->arch.last_tsc_nsec;
46543ba4
ZA		 1029 sdiff = data - kvm->arch.last_tsc_write;
1030 if (sdiff < 0)
1031 sdiff = -sdiff;
f38e098f
ZA		 1032
1033 /*
46543ba4 1034 * Special case: close write to TSC within 5 seconds of
f38e098f 1035 * another CPU is interpreted as an attempt to synchronize
0d2eb44f 1036 * The 5 seconds is to accommodate host load / swapping as
46543ba4 1037 * well as any reset of TSC during the boot process.
f38e098f
ZA		 1038 *
1039 * In that case, for a reliable TSC, we can match TSC offsets,
46543ba4 1040 * or make a best guest using elapsed value.
f38e098f 1041 */
857e4099 1042 if (sdiff < nsec_to_cycles(vcpu, 5ULL * NSEC_PER_SEC) &&
46543ba4 1043 elapsed < 5ULL * NSEC_PER_SEC) {
f38e098f
ZA		 1044 if (!check_tsc_unstable()) {
1045 offset = kvm->arch.last_tsc_offset;
1046 pr_debug("kvm: matched tsc offset for %llu\n", data);
1047 } else {
857e4099 1048 u64 delta = nsec_to_cycles(vcpu, elapsed);
759379dd
ZA		 1049 offset += delta;
1050 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f
ZA		 1051 }
1052 ns = kvm->arch.last_tsc_nsec;
1053 }
1054 kvm->arch.last_tsc_nsec = ns;
1055 kvm->arch.last_tsc_write = data;
1056 kvm->arch.last_tsc_offset = offset;
99e3e30a 1057 kvm_x86_ops->write_tsc_offset(vcpu, offset);
038f8c11 1058 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
99e3e30a
ZA		 1059
1060 /* Reset of TSC must disable overshoot protection below */
1061 vcpu->arch.hv_clock.tsc_timestamp = 0;
c285545f
ZA		 1062 vcpu->arch.last_tsc_write = data;
1063 vcpu->arch.last_tsc_nsec = ns;
99e3e30a
ZA		 1064}
1065EXPORT_SYMBOL_GPL(kvm_write_tsc);
1066
34c238a1 1067static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1068{
18068523
GOC		 1069 unsigned long flags;
1070 struct kvm_vcpu_arch *vcpu = &v->arch;
1071 void *shared_kaddr;
463656c0 1072 unsigned long this_tsc_khz;
1d5f066e
ZA		 1073 s64 kernel_ns, max_kernel_ns;
1074 u64 tsc_timestamp;
18068523 1075
18068523
GOC		 1076 /* Keep irq disabled to prevent changes to the clock */
1077 local_irq_save(flags);
d5c1785d 1078 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v);
759379dd 1079 kernel_ns = get_kernel_ns();
1e993611 1080 this_tsc_khz = vcpu_tsc_khz(v);
8cfdc000 1081 if (unlikely(this_tsc_khz == 0)) {
c285545f 1082 local_irq_restore(flags);
34c238a1 1083 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
8cfdc000
ZA		 1084 return 1;
1085 }
18068523 1086
c285545f
ZA		 1087 /*
1088 * We may have to catch up the TSC to match elapsed wall clock
1089 * time for two reasons, even if kvmclock is used.
1090 * 1) CPU could have been running below the maximum TSC rate
1091 * 2) Broken TSC compensation resets the base at each VCPU
1092 * entry to avoid unknown leaps of TSC even when running
1093 * again on the same CPU. This may cause apparent elapsed
1094 * time to disappear, and the guest to stand still or run
1095 * very slowly.
1096 */
1097 if (vcpu->tsc_catchup) {
1098 u64 tsc = compute_guest_tsc(v, kernel_ns);
1099 if (tsc > tsc_timestamp) {
1100 kvm_x86_ops->adjust_tsc_offset(v, tsc - tsc_timestamp);
1101 tsc_timestamp = tsc;
1102 }
50d0a0f9
GH		 1103 }
1104
18068523
GOC		 1105 local_irq_restore(flags);
1106
c285545f
ZA		 1107 if (!vcpu->time_page)
1108 return 0;
18068523 1109
1d5f066e
ZA		 1110 /*
1111 * Time as measured by the TSC may go backwards when resetting the base
1112 * tsc_timestamp. The reason for this is that the TSC resolution is
1113 * higher than the resolution of the other clock scales. Thus, many
1114 * possible measurments of the TSC correspond to one measurement of any
1115 * other clock, and so a spread of values is possible. This is not a
1116 * problem for the computation of the nanosecond clock; with TSC rates
1117 * around 1GHZ, there can only be a few cycles which correspond to one
1118 * nanosecond value, and any path through this code will inevitably
1119 * take longer than that. However, with the kernel_ns value itself,
1120 * the precision may be much lower, down to HZ granularity. If the
1121 * first sampling of TSC against kernel_ns ends in the low part of the
1122 * range, and the second in the high end of the range, we can get:
1123 *
1124 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1125 *
1126 * As the sampling errors potentially range in the thousands of cycles,
1127 * it is possible such a time value has already been observed by the
1128 * guest. To protect against this, we must compute the system time as
1129 * observed by the guest and ensure the new system time is greater.
1130 */
1131 max_kernel_ns = 0;
1132 if (vcpu->hv_clock.tsc_timestamp && vcpu->last_guest_tsc) {
1133 max_kernel_ns = vcpu->last_guest_tsc -
1134 vcpu->hv_clock.tsc_timestamp;
1135 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1136 vcpu->hv_clock.tsc_to_system_mul,
1137 vcpu->hv_clock.tsc_shift);
1138 max_kernel_ns += vcpu->last_kernel_ns;
1139 }
afbcf7ab 1140
e48672fa 1141 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1142 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1143 &vcpu->hv_clock.tsc_shift,
1144 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1145 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1146 }
1147
1d5f066e
ZA		 1148 if (max_kernel_ns > kernel_ns)
1149 kernel_ns = max_kernel_ns;
1150
8cfdc000 1151 /* With all the info we got, fill in the values */
1d5f066e 1152 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1153 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1d5f066e 1154 vcpu->last_kernel_ns = kernel_ns;
28e4639a 1155 vcpu->last_guest_tsc = tsc_timestamp;
371bcf64
GC		 1156 vcpu->hv_clock.flags = 0;
1157
18068523
GOC		 1158 /*
1159 * The interface expects us to write an even number signaling that the
1160 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1161 * state, we just increase by 2 at the end.
18068523 1162 */
50d0a0f9 1163 vcpu->hv_clock.version += 2;
18068523
GOC		 1164
1165 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
1166
1167 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 1168 sizeof(vcpu->hv_clock));
18068523
GOC		 1169
1170 kunmap_atomic(shared_kaddr, KM_USER0);
1171
1172 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
8cfdc000 1173 return 0;
c8076604
GH		 1174}
1175
9ba075a6
AK		 1176static bool msr_mtrr_valid(unsigned msr)
1177{
1178 switch (msr) {
1179 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1180 case MSR_MTRRfix64K_00000:
1181 case MSR_MTRRfix16K_80000:
1182 case MSR_MTRRfix16K_A0000:
1183 case MSR_MTRRfix4K_C0000:
1184 case MSR_MTRRfix4K_C8000:
1185 case MSR_MTRRfix4K_D0000:
1186 case MSR_MTRRfix4K_D8000:
1187 case MSR_MTRRfix4K_E0000:
1188 case MSR_MTRRfix4K_E8000:
1189 case MSR_MTRRfix4K_F0000:
1190 case MSR_MTRRfix4K_F8000:
1191 case MSR_MTRRdefType:
1192 case MSR_IA32_CR_PAT:
1193 return true;
1194 case 0x2f8:
1195 return true;
1196 }
1197 return false;
1198}
1199
d6289b93
MT		 1200static bool valid_pat_type(unsigned t)
1201{
1202 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1203}
1204
1205static bool valid_mtrr_type(unsigned t)
1206{
1207 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1208}
1209
1210static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1211{
1212 int i;
1213
1214 if (!msr_mtrr_valid(msr))
1215 return false;
1216
1217 if (msr == MSR_IA32_CR_PAT) {
1218 for (i = 0; i < 8; i++)
1219 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1220 return false;
1221 return true;
1222 } else if (msr == MSR_MTRRdefType) {
1223 if (data & ~0xcff)
1224 return false;
1225 return valid_mtrr_type(data & 0xff);
1226 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1227 for (i = 0; i < 8 ; i++)
1228 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1229 return false;
1230 return true;
1231 }
1232
1233 /* variable MTRRs */
1234 return valid_mtrr_type(data & 0xff);
1235}
1236
9ba075a6
AK		 1237static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1238{
0bed3b56
SY		 1239 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1240
d6289b93 1241 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1242 return 1;
1243
0bed3b56
SY		 1244 if (msr == MSR_MTRRdefType) {
1245 vcpu->arch.mtrr_state.def_type = data;
1246 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1247 } else if (msr == MSR_MTRRfix64K_00000)
1248 p[0] = data;
1249 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1250 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1251 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1252 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1253 else if (msr == MSR_IA32_CR_PAT)
1254 vcpu->arch.pat = data;
1255 else { /* Variable MTRRs */
1256 int idx, is_mtrr_mask;
1257 u64 *pt;
1258
1259 idx = (msr - 0x200) / 2;
1260 is_mtrr_mask = msr - 0x200 - 2 * idx;
1261 if (!is_mtrr_mask)
1262 pt =
1263 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1264 else
1265 pt =
1266 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1267 *pt = data;
1268 }
1269
1270 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1271 return 0;
1272}
15c4a640 1273
890ca9ae 1274static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1275{
890ca9ae
HY		 1276 u64 mcg_cap = vcpu->arch.mcg_cap;
1277 unsigned bank_num = mcg_cap & 0xff;
1278
15c4a640 1279 switch (msr) {
15c4a640 1280 case MSR_IA32_MCG_STATUS:
890ca9ae 1281 vcpu->arch.mcg_status = data;
15c4a640 1282 break;
c7ac679c 1283 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1284 if (!(mcg_cap & MCG_CTL_P))
1285 return 1;
1286 if (data != 0 && data != ~(u64)0)
1287 return -1;
1288 vcpu->arch.mcg_ctl = data;
1289 break;
1290 default:
1291 if (msr >= MSR_IA32_MC0_CTL &&
1292 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1293 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1294 /* only 0 or all 1s can be written to IA32_MCi_CTL
1295 * some Linux kernels though clear bit 10 in bank 4 to
1296 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1297 * this to avoid an uncatched #GP in the guest
1298 */
890ca9ae 1299 if ((offset & 0x3) == 0 &&
114be429 1300 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1301 return -1;
1302 vcpu->arch.mce_banks[offset] = data;
1303 break;
1304 }
1305 return 1;
1306 }
1307 return 0;
1308}
1309
ffde22ac
ES		 1310static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1311{
1312 struct kvm *kvm = vcpu->kvm;
1313 int lm = is_long_mode(vcpu);
1314 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1315 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1316 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1317 : kvm->arch.xen_hvm_config.blob_size_32;
1318 u32 page_num = data & ~PAGE_MASK;
1319 u64 page_addr = data & PAGE_MASK;
1320 u8 *page;
1321 int r;
1322
1323 r = -E2BIG;
1324 if (page_num >= blob_size)
1325 goto out;
1326 r = -ENOMEM;
ff5c2c03
SL		 1327 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1328 if (IS_ERR(page)) {
1329 r = PTR_ERR(page);
ffde22ac 1330 goto out;
ff5c2c03 1331 }
ffde22ac
ES		 1332 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1333 goto out_free;
1334 r = 0;
1335out_free:
1336 kfree(page);
1337out:
1338 return r;
1339}
1340
55cd8e5a
GN		 1341static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1342{
1343 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1344}
1345
1346static bool kvm_hv_msr_partition_wide(u32 msr)
1347{
1348 bool r = false;
1349 switch (msr) {
1350 case HV_X64_MSR_GUEST_OS_ID:
1351 case HV_X64_MSR_HYPERCALL:
1352 r = true;
1353 break;
1354 }
1355
1356 return r;
1357}
1358
1359static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1360{
1361 struct kvm *kvm = vcpu->kvm;
1362
1363 switch (msr) {
1364 case HV_X64_MSR_GUEST_OS_ID:
1365 kvm->arch.hv_guest_os_id = data;
1366 /* setting guest os id to zero disables hypercall page */
1367 if (!kvm->arch.hv_guest_os_id)
1368 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1369 break;
1370 case HV_X64_MSR_HYPERCALL: {
1371 u64 gfn;
1372 unsigned long addr;
1373 u8 instructions[4];
1374
1375 /* if guest os id is not set hypercall should remain disabled */
1376 if (!kvm->arch.hv_guest_os_id)
1377 break;
1378 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1379 kvm->arch.hv_hypercall = data;
1380 break;
1381 }
1382 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1383 addr = gfn_to_hva(kvm, gfn);
1384 if (kvm_is_error_hva(addr))
1385 return 1;
1386 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1387 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1388 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1389 return 1;
1390 kvm->arch.hv_hypercall = data;
1391 break;
1392 }
1393 default:
1394 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1395 "data 0x%llx\n", msr, data);
1396 return 1;
1397 }
1398 return 0;
1399}
1400
1401static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1402{
10388a07
GN		 1403 switch (msr) {
1404 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1405 unsigned long addr;
55cd8e5a 1406
10388a07
GN		 1407 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1408 vcpu->arch.hv_vapic = data;
1409 break;
1410 }
1411 addr = gfn_to_hva(vcpu->kvm, data >>
1412 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1413 if (kvm_is_error_hva(addr))
1414 return 1;
8b0cedff 1415 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 1416 return 1;
1417 vcpu->arch.hv_vapic = data;
1418 break;
1419 }
1420 case HV_X64_MSR_EOI:
1421 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1422 case HV_X64_MSR_ICR:
1423 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1424 case HV_X64_MSR_TPR:
1425 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1426 default:
1427 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1428 "data 0x%llx\n", msr, data);
1429 return 1;
1430 }
1431
1432 return 0;
55cd8e5a
GN		 1433}
1434
344d9588
GN		 1435static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1436{
1437 gpa_t gpa = data & ~0x3f;
1438
6adba527
GN		 1439 /* Bits 2:5 are resrved, Should be zero */
1440 if (data & 0x3c)
344d9588
GN		 1441 return 1;
1442
1443 vcpu->arch.apf.msr_val = data;
1444
1445 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1446 kvm_clear_async_pf_completion_queue(vcpu);
1447 kvm_async_pf_hash_reset(vcpu);
1448 return 0;
1449 }
1450
1451 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa))
1452 return 1;
1453
6adba527 1454 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1455 kvm_async_pf_wakeup_all(vcpu);
1456 return 0;
1457}
1458
12f9a48f
GC		 1459static void kvmclock_reset(struct kvm_vcpu *vcpu)
1460{
1461 if (vcpu->arch.time_page) {
1462 kvm_release_page_dirty(vcpu->arch.time_page);
1463 vcpu->arch.time_page = NULL;
1464 }
1465}
1466
c9aaa895
GC		 1467static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1468{
1469 u64 delta;
1470
1471 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1472 return;
1473
1474 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1475 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1476 vcpu->arch.st.accum_steal = delta;
1477}
1478
1479static void record_steal_time(struct kvm_vcpu *vcpu)
1480{
1481 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1482 return;
1483
1484 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1485 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1486 return;
1487
1488 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1489 vcpu->arch.st.steal.version += 2;
1490 vcpu->arch.st.accum_steal = 0;
1491
1492 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1493 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1494}
1495
15c4a640
CO		 1496int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1497{
5753785f
GN		 1498 bool pr = false;
1499
15c4a640 1500 switch (msr) {
15c4a640 1501 case MSR_EFER:
b69e8cae 1502 return set_efer(vcpu, data);
8f1589d9
AP		 1503 case MSR_K7_HWCR:
1504 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1505 data &= ~(u64)0x100; /* ignore ignne emulation enable */
8f1589d9
AP		 1506 if (data != 0) {
1507 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1508 data);
1509 return 1;
1510 }
15c4a640 1511 break;
f7c6d140
AP		 1512 case MSR_FAM10H_MMIO_CONF_BASE:
1513 if (data != 0) {
1514 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1515 "0x%llx\n", data);
1516 return 1;
1517 }
15c4a640 1518 break;
c323c0e5 1519 case MSR_AMD64_NB_CFG:
c7ac679c 1520 break;
b5e2fec0
AG		 1521 case MSR_IA32_DEBUGCTLMSR:
1522 if (!data) {
1523 /* We support the non-activated case already */
1524 break;
1525 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1526 /* Values other than LBR and BTF are vendor-specific,
1527 thus reserved and should throw a #GP */
1528 return 1;
1529 }
1530 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1531 __func__, data);
1532 break;
15c4a640
CO		 1533 case MSR_IA32_UCODE_REV:
1534 case MSR_IA32_UCODE_WRITE:
61a6bd67 1535 case MSR_VM_HSAVE_PA:
6098ca93 1536 case MSR_AMD64_PATCH_LOADER:
15c4a640 1537 break;
9ba075a6
AK		 1538 case 0x200 ... 0x2ff:
1539 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1540 case MSR_IA32_APICBASE:
1541 kvm_set_apic_base(vcpu, data);
1542 break;
0105d1a5
GN		 1543 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1544 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 1545 case MSR_IA32_TSCDEADLINE:
1546 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1547 break;
15c4a640 1548 case MSR_IA32_MISC_ENABLE:
ad312c7c 1549 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1550 break;
11c6bffa 1551 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1552 case MSR_KVM_WALL_CLOCK:
1553 vcpu->kvm->arch.wall_clock = data;
1554 kvm_write_wall_clock(vcpu->kvm, data);
1555 break;
11c6bffa 1556 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 1557 case MSR_KVM_SYSTEM_TIME: {
12f9a48f 1558 kvmclock_reset(vcpu);
18068523
GOC		 1559
1560 vcpu->arch.time = data;
c285545f 1561 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
18068523
GOC		 1562
1563 /* we verify if the enable bit is set... */
1564 if (!(data & 1))
1565 break;
1566
1567 /* ...but clean it before doing the actual write */
1568 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1569
18068523
GOC		 1570 vcpu->arch.time_page =
1571 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1572
1573 if (is_error_page(vcpu->arch.time_page)) {
1574 kvm_release_page_clean(vcpu->arch.time_page);
1575 vcpu->arch.time_page = NULL;
1576 }
18068523
GOC		 1577 break;
1578 }
344d9588
GN		 1579 case MSR_KVM_ASYNC_PF_EN:
1580 if (kvm_pv_enable_async_pf(vcpu, data))
1581 return 1;
1582 break;
c9aaa895
GC		 1583 case MSR_KVM_STEAL_TIME:
1584
1585 if (unlikely(!sched_info_on()))
1586 return 1;
1587
1588 if (data & KVM_STEAL_RESERVED_MASK)
1589 return 1;
1590
1591 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
1592 data & KVM_STEAL_VALID_BITS))
1593 return 1;
1594
1595 vcpu->arch.st.msr_val = data;
1596
1597 if (!(data & KVM_MSR_ENABLED))
1598 break;
1599
1600 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1601
1602 preempt_disable();
1603 accumulate_steal_time(vcpu);
1604 preempt_enable();
1605
1606 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
1607
1608 break;
1609
890ca9ae
HY		 1610 case MSR_IA32_MCG_CTL:
1611 case MSR_IA32_MCG_STATUS:
1612 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1613 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1614
1615 /* Performance counters are not protected by a CPUID bit,
1616 * so we should check all of them in the generic path for the sake of
1617 * cross vendor migration.
1618 * Writing a zero into the event select MSRs disables them,
1619 * which we perfectly emulate ;-). Any other value should be at least
1620 * reported, some guests depend on them.
1621 */
71db6023
AP		 1622 case MSR_K7_EVNTSEL0:
1623 case MSR_K7_EVNTSEL1:
1624 case MSR_K7_EVNTSEL2:
1625 case MSR_K7_EVNTSEL3:
1626 if (data != 0)
1627 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1628 "0x%x data 0x%llx\n", msr, data);
1629 break;
1630 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1631 * so we ignore writes to make it happy.
1632 */
71db6023
AP		 1633 case MSR_K7_PERFCTR0:
1634 case MSR_K7_PERFCTR1:
1635 case MSR_K7_PERFCTR2:
1636 case MSR_K7_PERFCTR3:
1637 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1638 "0x%x data 0x%llx\n", msr, data);
1639 break;
5753785f
GN		 1640 case MSR_P6_PERFCTR0:
1641 case MSR_P6_PERFCTR1:
1642 pr = true;
1643 case MSR_P6_EVNTSEL0:
1644 case MSR_P6_EVNTSEL1:
1645 if (kvm_pmu_msr(vcpu, msr))
1646 return kvm_pmu_set_msr(vcpu, msr, data);
1647
1648 if (pr || data != 0)
1649 pr_unimpl(vcpu, "disabled perfctr wrmsr: "
1650 "0x%x data 0x%llx\n", msr, data);
1651 break;
84e0cefa
JS		 1652 case MSR_K7_CLK_CTL:
1653 /*
1654 * Ignore all writes to this no longer documented MSR.
1655 * Writes are only relevant for old K7 processors,
1656 * all pre-dating SVM, but a recommended workaround from
1657 * AMD for these chips. It is possible to speicify the
1658 * affected processor models on the command line, hence
1659 * the need to ignore the workaround.
1660 */
1661 break;
55cd8e5a
GN		 1662 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1663 if (kvm_hv_msr_partition_wide(msr)) {
1664 int r;
1665 mutex_lock(&vcpu->kvm->lock);
1666 r = set_msr_hyperv_pw(vcpu, msr, data);
1667 mutex_unlock(&vcpu->kvm->lock);
1668 return r;
1669 } else
1670 return set_msr_hyperv(vcpu, msr, data);
1671 break;
91c9c3ed 1672 case MSR_IA32_BBL_CR_CTL3:
1673 /* Drop writes to this legacy MSR -- see rdmsr
1674 * counterpart for further detail.
1675 */
1676 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
1677 break;
15c4a640 1678 default:
ffde22ac
ES		 1679 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1680 return xen_hvm_config(vcpu, data);
f5132b01
GN		 1681 if (kvm_pmu_msr(vcpu, msr))
1682 return kvm_pmu_set_msr(vcpu, msr, data);
ed85c068
AP		 1683 if (!ignore_msrs) {
1684 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1685 msr, data);
1686 return 1;
1687 } else {
1688 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1689 msr, data);
1690 break;
1691 }
15c4a640
CO		 1692 }
1693 return 0;
1694}
1695EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1696
1697
1698/*
1699 * Reads an msr value (of 'msr_index') into 'pdata'.
1700 * Returns 0 on success, non-0 otherwise.
1701 * Assumes vcpu_load() was already called.
1702 */
1703int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1704{
1705 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1706}
1707
9ba075a6
AK		 1708static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1709{
0bed3b56
SY		 1710 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1711
9ba075a6
AK		 1712 if (!msr_mtrr_valid(msr))
1713 return 1;
1714
0bed3b56
SY		 1715 if (msr == MSR_MTRRdefType)
1716 *pdata = vcpu->arch.mtrr_state.def_type +
1717 (vcpu->arch.mtrr_state.enabled << 10);
1718 else if (msr == MSR_MTRRfix64K_00000)
1719 *pdata = p[0];
1720 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1721 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1722 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1723 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1724 else if (msr == MSR_IA32_CR_PAT)
1725 *pdata = vcpu->arch.pat;
1726 else { /* Variable MTRRs */
1727 int idx, is_mtrr_mask;
1728 u64 *pt;
1729
1730 idx = (msr - 0x200) / 2;
1731 is_mtrr_mask = msr - 0x200 - 2 * idx;
1732 if (!is_mtrr_mask)
1733 pt =
1734 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1735 else
1736 pt =
1737 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1738 *pdata = *pt;
1739 }
1740
9ba075a6
AK		 1741 return 0;
1742}
1743
890ca9ae 1744static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1745{
1746 u64 data;
890ca9ae
HY		 1747 u64 mcg_cap = vcpu->arch.mcg_cap;
1748 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1749
1750 switch (msr) {
15c4a640
CO		 1751 case MSR_IA32_P5_MC_ADDR:
1752 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1753 data = 0;
1754 break;
15c4a640 1755 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1756 data = vcpu->arch.mcg_cap;
1757 break;
c7ac679c 1758 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1759 if (!(mcg_cap & MCG_CTL_P))
1760 return 1;
1761 data = vcpu->arch.mcg_ctl;
1762 break;
1763 case MSR_IA32_MCG_STATUS:
1764 data = vcpu->arch.mcg_status;
1765 break;
1766 default:
1767 if (msr >= MSR_IA32_MC0_CTL &&
1768 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1769 u32 offset = msr - MSR_IA32_MC0_CTL;
1770 data = vcpu->arch.mce_banks[offset];
1771 break;
1772 }
1773 return 1;
1774 }
1775 *pdata = data;
1776 return 0;
1777}
1778
55cd8e5a
GN		 1779static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1780{
1781 u64 data = 0;
1782 struct kvm *kvm = vcpu->kvm;
1783
1784 switch (msr) {
1785 case HV_X64_MSR_GUEST_OS_ID:
1786 data = kvm->arch.hv_guest_os_id;
1787 break;
1788 case HV_X64_MSR_HYPERCALL:
1789 data = kvm->arch.hv_hypercall;
1790 break;
1791 default:
1792 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1793 return 1;
1794 }
1795
1796 *pdata = data;
1797 return 0;
1798}
1799
1800static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1801{
1802 u64 data = 0;
1803
1804 switch (msr) {
1805 case HV_X64_MSR_VP_INDEX: {
1806 int r;
1807 struct kvm_vcpu *v;
1808 kvm_for_each_vcpu(r, v, vcpu->kvm)
1809 if (v == vcpu)
1810 data = r;
1811 break;
1812 }
10388a07
GN		 1813 case HV_X64_MSR_EOI:
1814 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1815 case HV_X64_MSR_ICR:
1816 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1817 case HV_X64_MSR_TPR:
1818 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 1819 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 1820 data = vcpu->arch.hv_vapic;
1821 break;
55cd8e5a
GN		 1822 default:
1823 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1824 return 1;
1825 }
1826 *pdata = data;
1827 return 0;
1828}
1829
890ca9ae
HY		 1830int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1831{
1832 u64 data;
1833
1834 switch (msr) {
890ca9ae 1835 case MSR_IA32_PLATFORM_ID:
15c4a640 1836 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1837 case MSR_IA32_DEBUGCTLMSR:
1838 case MSR_IA32_LASTBRANCHFROMIP:
1839 case MSR_IA32_LASTBRANCHTOIP:
1840 case MSR_IA32_LASTINTFROMIP:
1841 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1842 case MSR_K8_SYSCFG:
1843 case MSR_K7_HWCR:
61a6bd67 1844 case MSR_VM_HSAVE_PA:
9e699624 1845 case MSR_K7_EVNTSEL0:
1f3ee616 1846 case MSR_K7_PERFCTR0:
1fdbd48c 1847 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1848 case MSR_AMD64_NB_CFG:
f7c6d140 1849 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1850 data = 0;
1851 break;
5753785f
GN		 1852 case MSR_P6_PERFCTR0:
1853 case MSR_P6_PERFCTR1:
1854 case MSR_P6_EVNTSEL0:
1855 case MSR_P6_EVNTSEL1:
1856 if (kvm_pmu_msr(vcpu, msr))
1857 return kvm_pmu_get_msr(vcpu, msr, pdata);
1858 data = 0;
1859 break;
742bc670
MT		 1860 case MSR_IA32_UCODE_REV:
1861 data = 0x100000000ULL;
1862 break;
9ba075a6
AK		 1863 case MSR_MTRRcap:
1864 data = 0x500 | KVM_NR_VAR_MTRR;
1865 break;
1866 case 0x200 ... 0x2ff:
1867 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1868 case 0xcd: /* fsb frequency */
1869 data = 3;
1870 break;
7b914098
JS		 1871 /*
1872 * MSR_EBC_FREQUENCY_ID
1873 * Conservative value valid for even the basic CPU models.
1874 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
1875 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
1876 * and 266MHz for model 3, or 4. Set Core Clock
1877 * Frequency to System Bus Frequency Ratio to 1 (bits
1878 * 31:24) even though these are only valid for CPU
1879 * models > 2, however guests may end up dividing or
1880 * multiplying by zero otherwise.
1881 */
1882 case MSR_EBC_FREQUENCY_ID:
1883 data = 1 << 24;
1884 break;
15c4a640
CO		 1885 case MSR_IA32_APICBASE:
1886 data = kvm_get_apic_base(vcpu);
1887 break;
0105d1a5
GN		 1888 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1889 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1890 break;
a3e06bbe
LJ		 1891 case MSR_IA32_TSCDEADLINE:
1892 data = kvm_get_lapic_tscdeadline_msr(vcpu);
1893 break;
15c4a640 1894 case MSR_IA32_MISC_ENABLE:
ad312c7c 1895 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1896 break;
847f0ad8
AG		 1897 case MSR_IA32_PERF_STATUS:
1898 /* TSC increment by tick */
1899 data = 1000ULL;
1900 /* CPU multiplier */
1901 data |= (((uint64_t)4ULL) << 40);
1902 break;
15c4a640 1903 case MSR_EFER:
f6801dff 1904 data = vcpu->arch.efer;
15c4a640 1905 break;
18068523 1906 case MSR_KVM_WALL_CLOCK:
11c6bffa 1907 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1908 data = vcpu->kvm->arch.wall_clock;
1909 break;
1910 case MSR_KVM_SYSTEM_TIME:
11c6bffa 1911 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1912 data = vcpu->arch.time;
1913 break;
344d9588
GN		 1914 case MSR_KVM_ASYNC_PF_EN:
1915 data = vcpu->arch.apf.msr_val;
1916 break;
c9aaa895
GC		 1917 case MSR_KVM_STEAL_TIME:
1918 data = vcpu->arch.st.msr_val;
1919 break;
890ca9ae
HY		 1920 case MSR_IA32_P5_MC_ADDR:
1921 case MSR_IA32_P5_MC_TYPE:
1922 case MSR_IA32_MCG_CAP:
1923 case MSR_IA32_MCG_CTL:
1924 case MSR_IA32_MCG_STATUS:
1925 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1926 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 1927 case MSR_K7_CLK_CTL:
1928 /*
1929 * Provide expected ramp-up count for K7. All other
1930 * are set to zero, indicating minimum divisors for
1931 * every field.
1932 *
1933 * This prevents guest kernels on AMD host with CPU
1934 * type 6, model 8 and higher from exploding due to
1935 * the rdmsr failing.
1936 */
1937 data = 0x20000000;
1938 break;
55cd8e5a
GN		 1939 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1940 if (kvm_hv_msr_partition_wide(msr)) {
1941 int r;
1942 mutex_lock(&vcpu->kvm->lock);
1943 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1944 mutex_unlock(&vcpu->kvm->lock);
1945 return r;
1946 } else
1947 return get_msr_hyperv(vcpu, msr, pdata);
1948 break;
91c9c3ed 1949 case MSR_IA32_BBL_CR_CTL3:
1950 /* This legacy MSR exists but isn't fully documented in current
1951 * silicon. It is however accessed by winxp in very narrow
1952 * scenarios where it sets bit #19, itself documented as
1953 * a "reserved" bit. Best effort attempt to source coherent
1954 * read data here should the balance of the register be
1955 * interpreted by the guest:
1956 *
1957 * L2 cache control register 3: 64GB range, 256KB size,
1958 * enabled, latency 0x1, configured
1959 */
1960 data = 0xbe702111;
1961 break;
15c4a640 1962 default:
f5132b01
GN		 1963 if (kvm_pmu_msr(vcpu, msr))
1964 return kvm_pmu_get_msr(vcpu, msr, pdata);
ed85c068
AP		 1965 if (!ignore_msrs) {
1966 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1967 return 1;
1968 } else {
1969 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1970 data = 0;
1971 }
1972 break;
15c4a640
CO		 1973 }
1974 *pdata = data;
1975 return 0;
1976}
1977EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1978
313a3dc7
CO		 1979/*
1980 * Read or write a bunch of msrs. All parameters are kernel addresses.
1981 *
1982 * @return number of msrs set successfully.
1983 */
1984static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1985 struct kvm_msr_entry *entries,
1986 int (*do_msr)(struct kvm_vcpu *vcpu,
1987 unsigned index, u64 *data))
1988{
f656ce01 1989 int i, idx;
313a3dc7 1990
f656ce01 1991 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 1992 for (i = 0; i < msrs->nmsrs; ++i)
1993 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1994 break;
f656ce01 1995 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 1996
313a3dc7
CO		 1997 return i;
1998}
1999
2000/*
2001 * Read or write a bunch of msrs. Parameters are user addresses.
2002 *
2003 * @return number of msrs set successfully.
2004 */
2005static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2006 int (*do_msr)(struct kvm_vcpu *vcpu,
2007 unsigned index, u64 *data),
2008 int writeback)
2009{
2010 struct kvm_msrs msrs;
2011 struct kvm_msr_entry *entries;
2012 int r, n;
2013 unsigned size;
2014
2015 r = -EFAULT;
2016 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2017 goto out;
2018
2019 r = -E2BIG;
2020 if (msrs.nmsrs >= MAX_IO_MSRS)
2021 goto out;
2022
313a3dc7 2023 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2024 entries = memdup_user(user_msrs->entries, size);
2025 if (IS_ERR(entries)) {
2026 r = PTR_ERR(entries);
313a3dc7 2027 goto out;
ff5c2c03 2028 }
313a3dc7
CO		 2029
2030 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2031 if (r < 0)
2032 goto out_free;
2033
2034 r = -EFAULT;
2035 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2036 goto out_free;
2037
2038 r = n;
2039
2040out_free:
7a73c028 2041 kfree(entries);
313a3dc7
CO		 2042out:
2043 return r;
2044}
2045
018d00d2
ZX		 2046int kvm_dev_ioctl_check_extension(long ext)
2047{
2048 int r;
2049
2050 switch (ext) {
2051 case KVM_CAP_IRQCHIP:
2052 case KVM_CAP_HLT:
2053 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2054 case KVM_CAP_SET_TSS_ADDR:
07716717 2055 case KVM_CAP_EXT_CPUID:
c8076604 2056 case KVM_CAP_CLOCKSOURCE:
7837699f 2057 case KVM_CAP_PIT:
a28e4f5a 2058 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2059 case KVM_CAP_MP_STATE:
ed848624 2060 case KVM_CAP_SYNC_MMU:
a355c85c 2061 case KVM_CAP_USER_NMI:
52d939a0 2062 case KVM_CAP_REINJECT_CONTROL:
4925663a 2063 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 2064 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 2065 case KVM_CAP_IRQFD:
d34e6b17 2066 case KVM_CAP_IOEVENTFD:
c5ff41ce 2067 case KVM_CAP_PIT2:
e9f42757 2068 case KVM_CAP_PIT_STATE2:
b927a3ce 2069 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2070 case KVM_CAP_XEN_HVM:
afbcf7ab 2071 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2072 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2073 case KVM_CAP_HYPERV:
10388a07 2074 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2075 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2076 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2077 case KVM_CAP_DEBUGREGS:
d2be1651 2078 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2079 case KVM_CAP_XSAVE:
344d9588 2080 case KVM_CAP_ASYNC_PF:
92a1f12d 2081 case KVM_CAP_GET_TSC_KHZ:
018d00d2
ZX		 2082 r = 1;
2083 break;
542472b5
LV		 2084 case KVM_CAP_COALESCED_MMIO:
2085 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2086 break;
774ead3a
AK		 2087 case KVM_CAP_VAPIC:
2088 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2089 break;
f725230a 2090 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2091 r = KVM_SOFT_MAX_VCPUS;
2092 break;
2093 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2094 r = KVM_MAX_VCPUS;
2095 break;
a988b910
AK		 2096 case KVM_CAP_NR_MEMSLOTS:
2097 r = KVM_MEMORY_SLOTS;
2098 break;
a68a6a72
MT		 2099 case KVM_CAP_PV_MMU: /* obsolete */
2100 r = 0;
2f333bcb 2101 break;
62c476c7 2102 case KVM_CAP_IOMMU:
a1b60c1c 2103 r = iommu_present(&pci_bus_type);
62c476c7 2104 break;
890ca9ae
HY		 2105 case KVM_CAP_MCE:
2106 r = KVM_MAX_MCE_BANKS;
2107 break;
2d5b5a66
SY		 2108 case KVM_CAP_XCRS:
2109 r = cpu_has_xsave;
2110 break;
92a1f12d
JR		 2111 case KVM_CAP_TSC_CONTROL:
2112 r = kvm_has_tsc_control;
2113 break;
4d25a066
JK		 2114 case KVM_CAP_TSC_DEADLINE_TIMER:
2115 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2116 break;
018d00d2
ZX		 2117 default:
2118 r = 0;
2119 break;
2120 }
2121 return r;
2122
2123}
2124
043405e1
CO		 2125long kvm_arch_dev_ioctl(struct file *filp,
2126 unsigned int ioctl, unsigned long arg)
2127{
2128 void __user *argp = (void __user *)arg;
2129 long r;
2130
2131 switch (ioctl) {
2132 case KVM_GET_MSR_INDEX_LIST: {
2133 struct kvm_msr_list __user *user_msr_list = argp;
2134 struct kvm_msr_list msr_list;
2135 unsigned n;
2136
2137 r = -EFAULT;
2138 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2139 goto out;
2140 n = msr_list.nmsrs;
2141 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2142 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2143 goto out;
2144 r = -E2BIG;
e125e7b6 2145 if (n < msr_list.nmsrs)
043405e1
CO		 2146 goto out;
2147 r = -EFAULT;
2148 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2149 num_msrs_to_save * sizeof(u32)))
2150 goto out;
e125e7b6 2151 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2152 &emulated_msrs,
2153 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2154 goto out;
2155 r = 0;
2156 break;
2157 }
674eea0f
AK		 2158 case KVM_GET_SUPPORTED_CPUID: {
2159 struct kvm_cpuid2 __user *cpuid_arg = argp;
2160 struct kvm_cpuid2 cpuid;
2161
2162 r = -EFAULT;
2163 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2164 goto out;
2165 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 2166 cpuid_arg->entries);
674eea0f
AK		 2167 if (r)
2168 goto out;
2169
2170 r = -EFAULT;
2171 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2172 goto out;
2173 r = 0;
2174 break;
2175 }
890ca9ae
HY		 2176 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2177 u64 mce_cap;
2178
2179 mce_cap = KVM_MCE_CAP_SUPPORTED;
2180 r = -EFAULT;
2181 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2182 goto out;
2183 r = 0;
2184 break;
2185 }
043405e1
CO		 2186 default:
2187 r = -EINVAL;
2188 }
2189out:
2190 return r;
2191}
2192
f5f48ee1
SY		 2193static void wbinvd_ipi(void *garbage)
2194{
2195 wbinvd();
2196}
2197
2198static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2199{
2200 return vcpu->kvm->arch.iommu_domain &&
2201 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2202}
2203
313a3dc7
CO		 2204void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2205{
f5f48ee1
SY		 2206 /* Address WBINVD may be executed by guest */
2207 if (need_emulate_wbinvd(vcpu)) {
2208 if (kvm_x86_ops->has_wbinvd_exit())
2209 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2210 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2211 smp_call_function_single(vcpu->cpu,
2212 wbinvd_ipi, NULL, 1);
2213 }
2214
313a3dc7 2215 kvm_x86_ops->vcpu_load(vcpu, cpu);
48434c20 2216 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
e48672fa 2217 /* Make sure TSC doesn't go backwards */
8f6055cb
JR		 2218 s64 tsc_delta;
2219 u64 tsc;
2220
d5c1785d 2221 tsc = kvm_x86_ops->read_l1_tsc(vcpu);
8f6055cb
JR		 2222 tsc_delta = !vcpu->arch.last_guest_tsc ? 0 :
2223 tsc - vcpu->arch.last_guest_tsc;
2224
e48672fa
ZA		 2225 if (tsc_delta < 0)
2226 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2227 if (check_tsc_unstable()) {
e48672fa 2228 kvm_x86_ops->adjust_tsc_offset(vcpu, -tsc_delta);
c285545f 2229 vcpu->arch.tsc_catchup = 1;
c285545f 2230 }
1aa8ceef 2231 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2232 if (vcpu->cpu != cpu)
2233 kvm_migrate_timers(vcpu);
e48672fa 2234 vcpu->cpu = cpu;
6b7d7e76 2235 }
c9aaa895
GC		 2236
2237 accumulate_steal_time(vcpu);
2238 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2239}
2240
2241void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2242{
02daab21 2243 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2244 kvm_put_guest_fpu(vcpu);
d5c1785d 2245 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu);
313a3dc7
CO		 2246}
2247
313a3dc7
CO		 2248static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2249 struct kvm_lapic_state *s)
2250{
ad312c7c 2251 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2252
2253 return 0;
2254}
2255
2256static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2257 struct kvm_lapic_state *s)
2258{
ad312c7c 2259 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 2260 kvm_apic_post_state_restore(vcpu);
cb142eb7 2261 update_cr8_intercept(vcpu);
313a3dc7
CO		 2262
2263 return 0;
2264}
2265
f77bc6a4
ZX		 2266static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2267 struct kvm_interrupt *irq)
2268{
2269 if (irq->irq < 0 || irq->irq >= 256)
2270 return -EINVAL;
2271 if (irqchip_in_kernel(vcpu->kvm))
2272 return -ENXIO;
f77bc6a4 2273
66fd3f7f 2274 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2275 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2276
f77bc6a4
ZX		 2277 return 0;
2278}
2279
c4abb7c9
JK		 2280static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2281{
c4abb7c9 2282 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2283
2284 return 0;
2285}
2286
b209749f
AK		 2287static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2288 struct kvm_tpr_access_ctl *tac)
2289{
2290 if (tac->flags)
2291 return -EINVAL;
2292 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2293 return 0;
2294}
2295
890ca9ae
HY		 2296static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2297 u64 mcg_cap)
2298{
2299 int r;
2300 unsigned bank_num = mcg_cap & 0xff, bank;
2301
2302 r = -EINVAL;
a9e38c3e 2303 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2304 goto out;
2305 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2306 goto out;
2307 r = 0;
2308 vcpu->arch.mcg_cap = mcg_cap;
2309 /* Init IA32_MCG_CTL to all 1s */
2310 if (mcg_cap & MCG_CTL_P)
2311 vcpu->arch.mcg_ctl = ~(u64)0;
2312 /* Init IA32_MCi_CTL to all 1s */
2313 for (bank = 0; bank < bank_num; bank++)
2314 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2315out:
2316 return r;
2317}
2318
2319static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2320 struct kvm_x86_mce *mce)
2321{
2322 u64 mcg_cap = vcpu->arch.mcg_cap;
2323 unsigned bank_num = mcg_cap & 0xff;
2324 u64 *banks = vcpu->arch.mce_banks;
2325
2326 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2327 return -EINVAL;
2328 /*
2329 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2330 * reporting is disabled
2331 */
2332 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2333 vcpu->arch.mcg_ctl != ~(u64)0)
2334 return 0;
2335 banks += 4 * mce->bank;
2336 /*
2337 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2338 * reporting is disabled for the bank
2339 */
2340 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2341 return 0;
2342 if (mce->status & MCI_STATUS_UC) {
2343 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2344 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2345 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2346 return 0;
2347 }
2348 if (banks[1] & MCI_STATUS_VAL)
2349 mce->status |= MCI_STATUS_OVER;
2350 banks[2] = mce->addr;
2351 banks[3] = mce->misc;
2352 vcpu->arch.mcg_status = mce->mcg_status;
2353 banks[1] = mce->status;
2354 kvm_queue_exception(vcpu, MC_VECTOR);
2355 } else if (!(banks[1] & MCI_STATUS_VAL)
2356 || !(banks[1] & MCI_STATUS_UC)) {
2357 if (banks[1] & MCI_STATUS_VAL)
2358 mce->status |= MCI_STATUS_OVER;
2359 banks[2] = mce->addr;
2360 banks[3] = mce->misc;
2361 banks[1] = mce->status;
2362 } else
2363 banks[1] |= MCI_STATUS_OVER;
2364 return 0;
2365}
2366
3cfc3092
JK		 2367static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2368 struct kvm_vcpu_events *events)
2369{
7460fb4a 2370 process_nmi(vcpu);
03b82a30
JK		 2371 events->exception.injected =
2372 vcpu->arch.exception.pending &&
2373 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2374 events->exception.nr = vcpu->arch.exception.nr;
2375 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2376 events->exception.pad = 0;
3cfc3092
JK		 2377 events->exception.error_code = vcpu->arch.exception.error_code;
2378
03b82a30
JK		 2379 events->interrupt.injected =
2380 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2381 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2382 events->interrupt.soft = 0;
48005f64
JK		 2383 events->interrupt.shadow =
2384 kvm_x86_ops->get_interrupt_shadow(vcpu,
2385 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2386
2387 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2388 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2389 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2390 events->nmi.pad = 0;
3cfc3092
JK		 2391
2392 events->sipi_vector = vcpu->arch.sipi_vector;
2393
dab4b911 2394 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2395 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2396 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 2397 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2398}
2399
2400static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2401 struct kvm_vcpu_events *events)
2402{
dab4b911 2403 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2404 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2405 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2406 return -EINVAL;
2407
7460fb4a 2408 process_nmi(vcpu);
3cfc3092
JK		 2409 vcpu->arch.exception.pending = events->exception.injected;
2410 vcpu->arch.exception.nr = events->exception.nr;
2411 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2412 vcpu->arch.exception.error_code = events->exception.error_code;
2413
2414 vcpu->arch.interrupt.pending = events->interrupt.injected;
2415 vcpu->arch.interrupt.nr = events->interrupt.nr;
2416 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2417 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2418 kvm_x86_ops->set_interrupt_shadow(vcpu,
2419 events->interrupt.shadow);
3cfc3092
JK		 2420
2421 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2422 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2423 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2424 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2425
dab4b911
JK		 2426 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2427 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092 2428
3842d135
AK		 2429 kvm_make_request(KVM_REQ_EVENT, vcpu);
2430
3cfc3092
JK		 2431 return 0;
2432}
2433
a1efbe77
JK		 2434static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2435 struct kvm_debugregs *dbgregs)
2436{
a1efbe77
JK		 2437 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2438 dbgregs->dr6 = vcpu->arch.dr6;
2439 dbgregs->dr7 = vcpu->arch.dr7;
2440 dbgregs->flags = 0;
97e69aa6 2441 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 2442}
2443
2444static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2445 struct kvm_debugregs *dbgregs)
2446{
2447 if (dbgregs->flags)
2448 return -EINVAL;
2449
a1efbe77
JK		 2450 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2451 vcpu->arch.dr6 = dbgregs->dr6;
2452 vcpu->arch.dr7 = dbgregs->dr7;
2453
a1efbe77
JK		 2454 return 0;
2455}
2456
2d5b5a66
SY		 2457static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2458 struct kvm_xsave *guest_xsave)
2459{
2460 if (cpu_has_xsave)
2461 memcpy(guest_xsave->region,
2462 &vcpu->arch.guest_fpu.state->xsave,
f45755b8 2463 xstate_size);
2d5b5a66
SY		 2464 else {
2465 memcpy(guest_xsave->region,
2466 &vcpu->arch.guest_fpu.state->fxsave,
2467 sizeof(struct i387_fxsave_struct));
2468 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2469 XSTATE_FPSSE;
2470 }
2471}
2472
2473static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2474 struct kvm_xsave *guest_xsave)
2475{
2476 u64 xstate_bv =
2477 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2478
2479 if (cpu_has_xsave)
2480 memcpy(&vcpu->arch.guest_fpu.state->xsave,
f45755b8 2481 guest_xsave->region, xstate_size);
2d5b5a66
SY		 2482 else {
2483 if (xstate_bv & ~XSTATE_FPSSE)
2484 return -EINVAL;
2485 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2486 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2487 }
2488 return 0;
2489}
2490
2491static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2492 struct kvm_xcrs *guest_xcrs)
2493{
2494 if (!cpu_has_xsave) {
2495 guest_xcrs->nr_xcrs = 0;
2496 return;
2497 }
2498
2499 guest_xcrs->nr_xcrs = 1;
2500 guest_xcrs->flags = 0;
2501 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2502 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2503}
2504
2505static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2506 struct kvm_xcrs *guest_xcrs)
2507{
2508 int i, r = 0;
2509
2510 if (!cpu_has_xsave)
2511 return -EINVAL;
2512
2513 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2514 return -EINVAL;
2515
2516 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2517 /* Only support XCR0 currently */
2518 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2519 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2520 guest_xcrs->xcrs[0].value);
2521 break;
2522 }
2523 if (r)
2524 r = -EINVAL;
2525 return r;
2526}
2527
313a3dc7
CO		 2528long kvm_arch_vcpu_ioctl(struct file *filp,
2529 unsigned int ioctl, unsigned long arg)
2530{
2531 struct kvm_vcpu *vcpu = filp->private_data;
2532 void __user *argp = (void __user *)arg;
2533 int r;
d1ac91d8
AK		 2534 union {
2535 struct kvm_lapic_state *lapic;
2536 struct kvm_xsave *xsave;
2537 struct kvm_xcrs *xcrs;
2538 void *buffer;
2539 } u;
2540
2541 u.buffer = NULL;
313a3dc7
CO		 2542 switch (ioctl) {
2543 case KVM_GET_LAPIC: {
2204ae3c
MT		 2544 r = -EINVAL;
2545 if (!vcpu->arch.apic)
2546 goto out;
d1ac91d8 2547 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2548
b772ff36 2549 r = -ENOMEM;
d1ac91d8 2550 if (!u.lapic)
b772ff36 2551 goto out;
d1ac91d8 2552 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 2553 if (r)
2554 goto out;
2555 r = -EFAULT;
d1ac91d8 2556 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2557 goto out;
2558 r = 0;
2559 break;
2560 }
2561 case KVM_SET_LAPIC: {
2204ae3c
MT		 2562 r = -EINVAL;
2563 if (!vcpu->arch.apic)
2564 goto out;
ff5c2c03
SL		 2565 u.lapic = memdup_user(argp, sizeof(*u.lapic));
2566 if (IS_ERR(u.lapic)) {
2567 r = PTR_ERR(u.lapic);
313a3dc7 2568 goto out;
ff5c2c03
SL		 2569 }
2570
d1ac91d8 2571 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 2572 if (r)
2573 goto out;
2574 r = 0;
2575 break;
2576 }
f77bc6a4
ZX		 2577 case KVM_INTERRUPT: {
2578 struct kvm_interrupt irq;
2579
2580 r = -EFAULT;
2581 if (copy_from_user(&irq, argp, sizeof irq))
2582 goto out;
2583 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2584 if (r)
2585 goto out;
2586 r = 0;
2587 break;
2588 }
c4abb7c9
JK		 2589 case KVM_NMI: {
2590 r = kvm_vcpu_ioctl_nmi(vcpu);
2591 if (r)
2592 goto out;
2593 r = 0;
2594 break;
2595 }
313a3dc7
CO		 2596 case KVM_SET_CPUID: {
2597 struct kvm_cpuid __user *cpuid_arg = argp;
2598 struct kvm_cpuid cpuid;
2599
2600 r = -EFAULT;
2601 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2602 goto out;
2603 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2604 if (r)
2605 goto out;
2606 break;
2607 }
07716717
DK		 2608 case KVM_SET_CPUID2: {
2609 struct kvm_cpuid2 __user *cpuid_arg = argp;
2610 struct kvm_cpuid2 cpuid;
2611
2612 r = -EFAULT;
2613 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2614 goto out;
2615 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2616 cpuid_arg->entries);
07716717
DK		 2617 if (r)
2618 goto out;
2619 break;
2620 }
2621 case KVM_GET_CPUID2: {
2622 struct kvm_cpuid2 __user *cpuid_arg = argp;
2623 struct kvm_cpuid2 cpuid;
2624
2625 r = -EFAULT;
2626 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2627 goto out;
2628 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2629 cpuid_arg->entries);
07716717
DK		 2630 if (r)
2631 goto out;
2632 r = -EFAULT;
2633 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2634 goto out;
2635 r = 0;
2636 break;
2637 }
313a3dc7
CO		 2638 case KVM_GET_MSRS:
2639 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2640 break;
2641 case KVM_SET_MSRS:
2642 r = msr_io(vcpu, argp, do_set_msr, 0);
2643 break;
b209749f
AK		 2644 case KVM_TPR_ACCESS_REPORTING: {
2645 struct kvm_tpr_access_ctl tac;
2646
2647 r = -EFAULT;
2648 if (copy_from_user(&tac, argp, sizeof tac))
2649 goto out;
2650 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2651 if (r)
2652 goto out;
2653 r = -EFAULT;
2654 if (copy_to_user(argp, &tac, sizeof tac))
2655 goto out;
2656 r = 0;
2657 break;
2658 };
b93463aa
AK		 2659 case KVM_SET_VAPIC_ADDR: {
2660 struct kvm_vapic_addr va;
2661
2662 r = -EINVAL;
2663 if (!irqchip_in_kernel(vcpu->kvm))
2664 goto out;
2665 r = -EFAULT;
2666 if (copy_from_user(&va, argp, sizeof va))
2667 goto out;
2668 r = 0;
2669 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2670 break;
2671 }
890ca9ae
HY		 2672 case KVM_X86_SETUP_MCE: {
2673 u64 mcg_cap;
2674
2675 r = -EFAULT;
2676 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2677 goto out;
2678 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2679 break;
2680 }
2681 case KVM_X86_SET_MCE: {
2682 struct kvm_x86_mce mce;
2683
2684 r = -EFAULT;
2685 if (copy_from_user(&mce, argp, sizeof mce))
2686 goto out;
2687 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2688 break;
2689 }
3cfc3092
JK		 2690 case KVM_GET_VCPU_EVENTS: {
2691 struct kvm_vcpu_events events;
2692
2693 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2694
2695 r = -EFAULT;
2696 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2697 break;
2698 r = 0;
2699 break;
2700 }
2701 case KVM_SET_VCPU_EVENTS: {
2702 struct kvm_vcpu_events events;
2703
2704 r = -EFAULT;
2705 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2706 break;
2707
2708 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2709 break;
2710 }
a1efbe77
JK		 2711 case KVM_GET_DEBUGREGS: {
2712 struct kvm_debugregs dbgregs;
2713
2714 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2715
2716 r = -EFAULT;
2717 if (copy_to_user(argp, &dbgregs,
2718 sizeof(struct kvm_debugregs)))
2719 break;
2720 r = 0;
2721 break;
2722 }
2723 case KVM_SET_DEBUGREGS: {
2724 struct kvm_debugregs dbgregs;
2725
2726 r = -EFAULT;
2727 if (copy_from_user(&dbgregs, argp,
2728 sizeof(struct kvm_debugregs)))
2729 break;
2730
2731 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2732 break;
2733 }
2d5b5a66 2734 case KVM_GET_XSAVE: {
d1ac91d8 2735 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 2736 r = -ENOMEM;
d1ac91d8 2737 if (!u.xsave)
2d5b5a66
SY		 2738 break;
2739
d1ac91d8 2740 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2741
2742 r = -EFAULT;
d1ac91d8 2743 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 2744 break;
2745 r = 0;
2746 break;
2747 }
2748 case KVM_SET_XSAVE: {
ff5c2c03
SL		 2749 u.xsave = memdup_user(argp, sizeof(*u.xsave));
2750 if (IS_ERR(u.xsave)) {
2751 r = PTR_ERR(u.xsave);
2752 goto out;
2753 }
2d5b5a66 2754
d1ac91d8 2755 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2756 break;
2757 }
2758 case KVM_GET_XCRS: {
d1ac91d8 2759 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 2760 r = -ENOMEM;
d1ac91d8 2761 if (!u.xcrs)
2d5b5a66
SY		 2762 break;
2763
d1ac91d8 2764 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 2765
2766 r = -EFAULT;
d1ac91d8 2767 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 2768 sizeof(struct kvm_xcrs)))
2769 break;
2770 r = 0;
2771 break;
2772 }
2773 case KVM_SET_XCRS: {
ff5c2c03
SL		 2774 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
2775 if (IS_ERR(u.xcrs)) {
2776 r = PTR_ERR(u.xcrs);
2777 goto out;
2778 }
2d5b5a66 2779
d1ac91d8 2780 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 2781 break;
2782 }
92a1f12d
JR		 2783 case KVM_SET_TSC_KHZ: {
2784 u32 user_tsc_khz;
2785
2786 r = -EINVAL;
2787 if (!kvm_has_tsc_control)
2788 break;
2789
2790 user_tsc_khz = (u32)arg;
2791
2792 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
2793 goto out;
2794
2795 kvm_x86_ops->set_tsc_khz(vcpu, user_tsc_khz);
2796
2797 r = 0;
2798 goto out;
2799 }
2800 case KVM_GET_TSC_KHZ: {
2801 r = -EIO;
2802 if (check_tsc_unstable())
2803 goto out;
2804
2805 r = vcpu_tsc_khz(vcpu);
2806
2807 goto out;
2808 }
313a3dc7
CO		 2809 default:
2810 r = -EINVAL;
2811 }
2812out:
d1ac91d8 2813 kfree(u.buffer);
313a3dc7
CO		 2814 return r;
2815}
2816
1fe779f8
CO		 2817static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2818{
2819 int ret;
2820
2821 if (addr > (unsigned int)(-3 * PAGE_SIZE))
2822 return -1;
2823 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2824 return ret;
2825}
2826
b927a3ce
SY		 2827static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2828 u64 ident_addr)
2829{
2830 kvm->arch.ept_identity_map_addr = ident_addr;
2831 return 0;
2832}
2833
1fe779f8
CO		 2834static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
2835 u32 kvm_nr_mmu_pages)
2836{
2837 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
2838 return -EINVAL;
2839
79fac95e 2840 mutex_lock(&kvm->slots_lock);
7c8a83b7 2841 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 2842
2843 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 2844 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 2845
7c8a83b7 2846 spin_unlock(&kvm->mmu_lock);
79fac95e 2847 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2848 return 0;
2849}
2850
2851static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2852{
39de71ec 2853 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 2854}
2855
1fe779f8
CO		 2856static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2857{
2858 int r;
2859
2860 r = 0;
2861 switch (chip->chip_id) {
2862 case KVM_IRQCHIP_PIC_MASTER:
2863 memcpy(&chip->chip.pic,
2864 &pic_irqchip(kvm)->pics[0],
2865 sizeof(struct kvm_pic_state));
2866 break;
2867 case KVM_IRQCHIP_PIC_SLAVE:
2868 memcpy(&chip->chip.pic,
2869 &pic_irqchip(kvm)->pics[1],
2870 sizeof(struct kvm_pic_state));
2871 break;
2872 case KVM_IRQCHIP_IOAPIC:
eba0226b 2873 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2874 break;
2875 default:
2876 r = -EINVAL;
2877 break;
2878 }
2879 return r;
2880}
2881
2882static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2883{
2884 int r;
2885
2886 r = 0;
2887 switch (chip->chip_id) {
2888 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 2889 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2890 memcpy(&pic_irqchip(kvm)->pics[0],
2891 &chip->chip.pic,
2892 sizeof(struct kvm_pic_state));
f4f51050 2893 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2894 break;
2895 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 2896 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2897 memcpy(&pic_irqchip(kvm)->pics[1],
2898 &chip->chip.pic,
2899 sizeof(struct kvm_pic_state));
f4f51050 2900 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2901 break;
2902 case KVM_IRQCHIP_IOAPIC:
eba0226b 2903 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2904 break;
2905 default:
2906 r = -EINVAL;
2907 break;
2908 }
2909 kvm_pic_update_irq(pic_irqchip(kvm));
2910 return r;
2911}
2912
e0f63cb9
SY		 2913static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2914{
2915 int r = 0;
2916
894a9c55 2917 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2918 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 2919 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2920 return r;
2921}
2922
2923static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2924{
2925 int r = 0;
2926
894a9c55 2927 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2928 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 2929 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
2930 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2931 return r;
2932}
2933
2934static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2935{
2936 int r = 0;
2937
2938 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2939 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
2940 sizeof(ps->channels));
2941 ps->flags = kvm->arch.vpit->pit_state.flags;
2942 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 2943 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 2944 return r;
2945}
2946
2947static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
2948{
2949 int r = 0, start = 0;
2950 u32 prev_legacy, cur_legacy;
2951 mutex_lock(&kvm->arch.vpit->pit_state.lock);
2952 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
2953 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
2954 if (!prev_legacy && cur_legacy)
2955 start = 1;
2956 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
2957 sizeof(kvm->arch.vpit->pit_state.channels));
2958 kvm->arch.vpit->pit_state.flags = ps->flags;
2959 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 2960 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2961 return r;
2962}
2963
52d939a0
MT		 2964static int kvm_vm_ioctl_reinject(struct kvm *kvm,
2965 struct kvm_reinject_control *control)
2966{
2967 if (!kvm->arch.vpit)
2968 return -ENXIO;
894a9c55 2969 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 2970 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 2971 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 2972 return 0;
2973}
2974
95d4c16c
TY		 2975/**
2976 * write_protect_slot - write protect a slot for dirty logging
2977 * @kvm: the kvm instance
2978 * @memslot: the slot we protect
2979 * @dirty_bitmap: the bitmap indicating which pages are dirty
2980 * @nr_dirty_pages: the number of dirty pages
2981 *
2982 * We have two ways to find all sptes to protect:
2983 * 1. Use kvm_mmu_slot_remove_write_access() which walks all shadow pages and
2984 * checks ones that have a spte mapping a page in the slot.
2985 * 2. Use kvm_mmu_rmap_write_protect() for each gfn found in the bitmap.
2986 *
2987 * Generally speaking, if there are not so many dirty pages compared to the
2988 * number of shadow pages, we should use the latter.
2989 *
2990 * Note that letting others write into a page marked dirty in the old bitmap
2991 * by using the remaining tlb entry is not a problem. That page will become
2992 * write protected again when we flush the tlb and then be reported dirty to
2993 * the user space by copying the old bitmap.
2994 */
2995static void write_protect_slot(struct kvm *kvm,
2996 struct kvm_memory_slot *memslot,
2997 unsigned long *dirty_bitmap,
2998 unsigned long nr_dirty_pages)
2999{
3000 /* Not many dirty pages compared to # of shadow pages. */
3001 if (nr_dirty_pages < kvm->arch.n_used_mmu_pages) {
3002 unsigned long gfn_offset;
3003
3004 for_each_set_bit(gfn_offset, dirty_bitmap, memslot->npages) {
3005 unsigned long gfn = memslot->base_gfn + gfn_offset;
3006
3007 spin_lock(&kvm->mmu_lock);
3008 kvm_mmu_rmap_write_protect(kvm, gfn, memslot);
3009 spin_unlock(&kvm->mmu_lock);
3010 }
3011 kvm_flush_remote_tlbs(kvm);
3012 } else {
3013 spin_lock(&kvm->mmu_lock);
3014 kvm_mmu_slot_remove_write_access(kvm, memslot->id);
3015 spin_unlock(&kvm->mmu_lock);
3016 }
3017}
3018
5bb064dc
ZX		 3019/*
3020 * Get (and clear) the dirty memory log for a memory slot.
3021 */
3022int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
3023 struct kvm_dirty_log *log)
3024{
7850ac54 3025 int r;
5bb064dc 3026 struct kvm_memory_slot *memslot;
95d4c16c 3027 unsigned long n, nr_dirty_pages;
5bb064dc 3028
79fac95e 3029 mutex_lock(&kvm->slots_lock);
5bb064dc 3030
b050b015
MT		 3031 r = -EINVAL;
3032 if (log->slot >= KVM_MEMORY_SLOTS)
3033 goto out;
3034
28a37544 3035 memslot = id_to_memslot(kvm->memslots, log->slot);
b050b015
MT		 3036 r = -ENOENT;
3037 if (!memslot->dirty_bitmap)
3038 goto out;
3039
87bf6e7d 3040 n = kvm_dirty_bitmap_bytes(memslot);
95d4c16c 3041 nr_dirty_pages = memslot->nr_dirty_pages;
b050b015 3042
5bb064dc 3043 /* If nothing is dirty, don't bother messing with page tables. */
95d4c16c 3044 if (nr_dirty_pages) {
b050b015 3045 struct kvm_memslots *slots, *old_slots;
28a37544 3046 unsigned long *dirty_bitmap, *dirty_bitmap_head;
b050b015 3047
28a37544
XG		 3048 dirty_bitmap = memslot->dirty_bitmap;
3049 dirty_bitmap_head = memslot->dirty_bitmap_head;
3050 if (dirty_bitmap == dirty_bitmap_head)
3051 dirty_bitmap_head += n / sizeof(long);
3052 memset(dirty_bitmap_head, 0, n);
b050b015 3053
914ebccd 3054 r = -ENOMEM;
cdfca7b3 3055 slots = kmemdup(kvm->memslots, sizeof(*kvm->memslots), GFP_KERNEL);
515a0127 3056 if (!slots)
914ebccd 3057 goto out;
cdfca7b3 3058
28a37544 3059 memslot = id_to_memslot(slots, log->slot);
95d4c16c 3060 memslot->nr_dirty_pages = 0;
28a37544 3061 memslot->dirty_bitmap = dirty_bitmap_head;
be593d62 3062 update_memslots(slots, NULL);
b050b015
MT		 3063
3064 old_slots = kvm->memslots;
3065 rcu_assign_pointer(kvm->memslots, slots);
3066 synchronize_srcu_expedited(&kvm->srcu);
b050b015 3067 kfree(old_slots);
914ebccd 3068
95d4c16c 3069 write_protect_slot(kvm, memslot, dirty_bitmap, nr_dirty_pages);
edde99ce 3070
914ebccd 3071 r = -EFAULT;
515a0127 3072 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n))
914ebccd 3073 goto out;
914ebccd
TY		 3074 } else {
3075 r = -EFAULT;
3076 if (clear_user(log->dirty_bitmap, n))
3077 goto out;
5bb064dc 3078 }
b050b015 3079
5bb064dc
ZX		 3080 r = 0;
3081out:
79fac95e 3082 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3083 return r;
3084}
3085
1fe779f8
CO		 3086long kvm_arch_vm_ioctl(struct file *filp,
3087 unsigned int ioctl, unsigned long arg)
3088{
3089 struct kvm *kvm = filp->private_data;
3090 void __user *argp = (void __user *)arg;
367e1319 3091 int r = -ENOTTY;
f0d66275
DH		 3092 /*
3093 * This union makes it completely explicit to gcc-3.x
3094 * that these two variables' stack usage should be
3095 * combined, not added together.
3096 */
3097 union {
3098 struct kvm_pit_state ps;
e9f42757 3099 struct kvm_pit_state2 ps2;
c5ff41ce 3100 struct kvm_pit_config pit_config;
f0d66275 3101 } u;
1fe779f8
CO		 3102
3103 switch (ioctl) {
3104 case KVM_SET_TSS_ADDR:
3105 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3106 if (r < 0)
3107 goto out;
3108 break;
b927a3ce
SY		 3109 case KVM_SET_IDENTITY_MAP_ADDR: {
3110 u64 ident_addr;
3111
3112 r = -EFAULT;
3113 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3114 goto out;
3115 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3116 if (r < 0)
3117 goto out;
3118 break;
3119 }
1fe779f8
CO		 3120 case KVM_SET_NR_MMU_PAGES:
3121 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3122 if (r)
3123 goto out;
3124 break;
3125 case KVM_GET_NR_MMU_PAGES:
3126 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3127 break;
3ddea128
MT		 3128 case KVM_CREATE_IRQCHIP: {
3129 struct kvm_pic *vpic;
3130
3131 mutex_lock(&kvm->lock);
3132 r = -EEXIST;
3133 if (kvm->arch.vpic)
3134 goto create_irqchip_unlock;
1fe779f8 3135 r = -ENOMEM;
3ddea128
MT		 3136 vpic = kvm_create_pic(kvm);
3137 if (vpic) {
1fe779f8
CO		 3138 r = kvm_ioapic_init(kvm);
3139 if (r) {
175504cd 3140 mutex_lock(&kvm->slots_lock);
72bb2fcd 3141 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3142 &vpic->dev_master);
3143 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3144 &vpic->dev_slave);
3145 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3146 &vpic->dev_eclr);
175504cd 3147 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3148 kfree(vpic);
3149 goto create_irqchip_unlock;
1fe779f8
CO		 3150 }
3151 } else
3ddea128
MT		 3152 goto create_irqchip_unlock;
3153 smp_wmb();
3154 kvm->arch.vpic = vpic;
3155 smp_wmb();
399ec807
AK		 3156 r = kvm_setup_default_irq_routing(kvm);
3157 if (r) {
175504cd 3158 mutex_lock(&kvm->slots_lock);
3ddea128 3159 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3160 kvm_ioapic_destroy(kvm);
3161 kvm_destroy_pic(kvm);
3ddea128 3162 mutex_unlock(&kvm->irq_lock);
175504cd 3163 mutex_unlock(&kvm->slots_lock);
399ec807 3164 }
3ddea128
MT		 3165 create_irqchip_unlock:
3166 mutex_unlock(&kvm->lock);
1fe779f8 3167 break;
3ddea128 3168 }
7837699f 3169 case KVM_CREATE_PIT:
c5ff41ce
JK		 3170 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3171 goto create_pit;
3172 case KVM_CREATE_PIT2:
3173 r = -EFAULT;
3174 if (copy_from_user(&u.pit_config, argp,
3175 sizeof(struct kvm_pit_config)))
3176 goto out;
3177 create_pit:
79fac95e 3178 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3179 r = -EEXIST;
3180 if (kvm->arch.vpit)
3181 goto create_pit_unlock;
7837699f 3182 r = -ENOMEM;
c5ff41ce 3183 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3184 if (kvm->arch.vpit)
3185 r = 0;
269e05e4 3186 create_pit_unlock:
79fac95e 3187 mutex_unlock(&kvm->slots_lock);
7837699f 3188 break;
4925663a 3189 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 3190 case KVM_IRQ_LINE: {
3191 struct kvm_irq_level irq_event;
3192
3193 r = -EFAULT;
3194 if (copy_from_user(&irq_event, argp, sizeof irq_event))
3195 goto out;
160d2f6c 3196 r = -ENXIO;
1fe779f8 3197 if (irqchip_in_kernel(kvm)) {
4925663a 3198 __s32 status;
4925663a
GN		 3199 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3200 irq_event.irq, irq_event.level);
4925663a 3201 if (ioctl == KVM_IRQ_LINE_STATUS) {
160d2f6c 3202 r = -EFAULT;
4925663a
GN		 3203 irq_event.status = status;
3204 if (copy_to_user(argp, &irq_event,
3205 sizeof irq_event))
3206 goto out;
3207 }
1fe779f8
CO		 3208 r = 0;
3209 }
3210 break;
3211 }
3212 case KVM_GET_IRQCHIP: {
3213 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3214 struct kvm_irqchip *chip;
1fe779f8 3215
ff5c2c03
SL		 3216 chip = memdup_user(argp, sizeof(*chip));
3217 if (IS_ERR(chip)) {
3218 r = PTR_ERR(chip);
1fe779f8 3219 goto out;
ff5c2c03
SL		 3220 }
3221
1fe779f8
CO		 3222 r = -ENXIO;
3223 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3224 goto get_irqchip_out;
3225 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3226 if (r)
f0d66275 3227 goto get_irqchip_out;
1fe779f8 3228 r = -EFAULT;
f0d66275
DH		 3229 if (copy_to_user(argp, chip, sizeof *chip))
3230 goto get_irqchip_out;
1fe779f8 3231 r = 0;
f0d66275
DH		 3232 get_irqchip_out:
3233 kfree(chip);
3234 if (r)
3235 goto out;
1fe779f8
CO		 3236 break;
3237 }
3238 case KVM_SET_IRQCHIP: {
3239 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3240 struct kvm_irqchip *chip;
1fe779f8 3241
ff5c2c03
SL		 3242 chip = memdup_user(argp, sizeof(*chip));
3243 if (IS_ERR(chip)) {
3244 r = PTR_ERR(chip);
1fe779f8 3245 goto out;
ff5c2c03
SL		 3246 }
3247
1fe779f8
CO		 3248 r = -ENXIO;
3249 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3250 goto set_irqchip_out;
3251 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3252 if (r)
f0d66275 3253 goto set_irqchip_out;
1fe779f8 3254 r = 0;
f0d66275
DH		 3255 set_irqchip_out:
3256 kfree(chip);
3257 if (r)
3258 goto out;
1fe779f8
CO		 3259 break;
3260 }
e0f63cb9 3261 case KVM_GET_PIT: {
e0f63cb9 3262 r = -EFAULT;
f0d66275 3263 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3264 goto out;
3265 r = -ENXIO;
3266 if (!kvm->arch.vpit)
3267 goto out;
f0d66275 3268 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3269 if (r)
3270 goto out;
3271 r = -EFAULT;
f0d66275 3272 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3273 goto out;
3274 r = 0;
3275 break;
3276 }
3277 case KVM_SET_PIT: {
e0f63cb9 3278 r = -EFAULT;
f0d66275 3279 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3280 goto out;
3281 r = -ENXIO;
3282 if (!kvm->arch.vpit)
3283 goto out;
f0d66275 3284 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3285 if (r)
3286 goto out;
3287 r = 0;
3288 break;
3289 }
e9f42757
BK		 3290 case KVM_GET_PIT2: {
3291 r = -ENXIO;
3292 if (!kvm->arch.vpit)
3293 goto out;
3294 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3295 if (r)
3296 goto out;
3297 r = -EFAULT;
3298 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3299 goto out;
3300 r = 0;
3301 break;
3302 }
3303 case KVM_SET_PIT2: {
3304 r = -EFAULT;
3305 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3306 goto out;
3307 r = -ENXIO;
3308 if (!kvm->arch.vpit)
3309 goto out;
3310 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3311 if (r)
3312 goto out;
3313 r = 0;
3314 break;
3315 }
52d939a0
MT		 3316 case KVM_REINJECT_CONTROL: {
3317 struct kvm_reinject_control control;
3318 r = -EFAULT;
3319 if (copy_from_user(&control, argp, sizeof(control)))
3320 goto out;
3321 r = kvm_vm_ioctl_reinject(kvm, &control);
3322 if (r)
3323 goto out;
3324 r = 0;
3325 break;
3326 }
ffde22ac
ES		 3327 case KVM_XEN_HVM_CONFIG: {
3328 r = -EFAULT;
3329 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3330 sizeof(struct kvm_xen_hvm_config)))
3331 goto out;
3332 r = -EINVAL;
3333 if (kvm->arch.xen_hvm_config.flags)
3334 goto out;
3335 r = 0;
3336 break;
3337 }
afbcf7ab 3338 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3339 struct kvm_clock_data user_ns;
3340 u64 now_ns;
3341 s64 delta;
3342
3343 r = -EFAULT;
3344 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3345 goto out;
3346
3347 r = -EINVAL;
3348 if (user_ns.flags)
3349 goto out;
3350
3351 r = 0;
395c6b0a 3352 local_irq_disable();
759379dd 3353 now_ns = get_kernel_ns();
afbcf7ab 3354 delta = user_ns.clock - now_ns;
395c6b0a 3355 local_irq_enable();
afbcf7ab
GC		 3356 kvm->arch.kvmclock_offset = delta;
3357 break;
3358 }
3359 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3360 struct kvm_clock_data user_ns;
3361 u64 now_ns;
3362
395c6b0a 3363 local_irq_disable();
759379dd 3364 now_ns = get_kernel_ns();
afbcf7ab 3365 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3366 local_irq_enable();
afbcf7ab 3367 user_ns.flags = 0;
97e69aa6 3368 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3369
3370 r = -EFAULT;
3371 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3372 goto out;
3373 r = 0;
3374 break;
3375 }
3376
1fe779f8
CO		 3377 default:
3378 ;
3379 }
3380out:
3381 return r;
3382}
3383
a16b043c 3384static void kvm_init_msr_list(void)
043405e1
CO		 3385{
3386 u32 dummy[2];
3387 unsigned i, j;
3388
e3267cbb
GC		 3389 /* skip the first msrs in the list. KVM-specific */
3390 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3391 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3392 continue;
3393 if (j < i)
3394 msrs_to_save[j] = msrs_to_save[i];
3395 j++;
3396 }
3397 num_msrs_to_save = j;
3398}
3399
bda9020e
MT		 3400static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3401 const void *v)
bbd9b64e 3402{
70252a10
AK		 3403 int handled = 0;
3404 int n;
3405
3406 do {
3407 n = min(len, 8);
3408 if (!(vcpu->arch.apic &&
3409 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3410 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3411 break;
3412 handled += n;
3413 addr += n;
3414 len -= n;
3415 v += n;
3416 } while (len);
bbd9b64e 3417
70252a10 3418 return handled;
bbd9b64e
CO		 3419}
3420
bda9020e 3421static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3422{
70252a10
AK		 3423 int handled = 0;
3424 int n;
3425
3426 do {
3427 n = min(len, 8);
3428 if (!(vcpu->arch.apic &&
3429 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3430 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3431 break;
3432 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3433 handled += n;
3434 addr += n;
3435 len -= n;
3436 v += n;
3437 } while (len);
bbd9b64e 3438
70252a10 3439 return handled;
bbd9b64e
CO		 3440}
3441
2dafc6c2
GN		 3442static void kvm_set_segment(struct kvm_vcpu *vcpu,
3443 struct kvm_segment *var, int seg)
3444{
3445 kvm_x86_ops->set_segment(vcpu, var, seg);
3446}
3447
3448void kvm_get_segment(struct kvm_vcpu *vcpu,
3449 struct kvm_segment *var, int seg)
3450{
3451 kvm_x86_ops->get_segment(vcpu, var, seg);
3452}
3453
e459e322 3454gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
02f59dc9
JR		 3455{
3456 gpa_t t_gpa;
ab9ae313 3457 struct x86_exception exception;
02f59dc9
JR		 3458
3459 BUG_ON(!mmu_is_nested(vcpu));
3460
3461 /* NPT walks are always user-walks */
3462 access |= PFERR_USER_MASK;
ab9ae313 3463 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
02f59dc9
JR		 3464
3465 return t_gpa;
3466}
3467
ab9ae313
AK		 3468gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3469 struct x86_exception *exception)
1871c602
GN		 3470{
3471 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 3472 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3473}
3474
ab9ae313
AK		 3475 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3476 struct x86_exception *exception)
1871c602
GN		 3477{
3478 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3479 access |= PFERR_FETCH_MASK;
ab9ae313 3480 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3481}
3482
ab9ae313
AK		 3483gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3484 struct x86_exception *exception)
1871c602
GN		 3485{
3486 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3487 access |= PFERR_WRITE_MASK;
ab9ae313 3488 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3489}
3490
3491/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 3492gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3493 struct x86_exception *exception)
1871c602 3494{
ab9ae313 3495 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 3496}
3497
3498static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3499 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 3500 struct x86_exception *exception)
bbd9b64e
CO		 3501{
3502 void *data = val;
10589a46 3503 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3504
3505 while (bytes) {
14dfe855 3506 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 3507 exception);
bbd9b64e 3508 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3509 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3510 int ret;
3511
bcc55cba 3512 if (gpa == UNMAPPED_GVA)
ab9ae313 3513 return X86EMUL_PROPAGATE_FAULT;
77c2002e 3514 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3515 if (ret < 0) {
c3cd7ffa 3516 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3517 goto out;
3518 }
bbd9b64e 3519
77c2002e
IE		 3520 bytes -= toread;
3521 data += toread;
3522 addr += toread;
bbd9b64e 3523 }
10589a46 3524out:
10589a46 3525 return r;
bbd9b64e 3526}
77c2002e 3527
1871c602 3528/* used for instruction fetching */
0f65dd70
AK		 3529static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
3530 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3531 struct x86_exception *exception)
1871c602 3532{
0f65dd70 3533 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3534 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3535
1871c602 3536 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
bcc55cba
AK		 3537 access | PFERR_FETCH_MASK,
3538 exception);
1871c602
GN		 3539}
3540
064aea77 3541int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 3542 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3543 struct x86_exception *exception)
1871c602 3544{
0f65dd70 3545 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3546 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3547
1871c602 3548 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 3549 exception);
1871c602 3550}
064aea77 3551EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 3552
0f65dd70
AK		 3553static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3554 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3555 struct x86_exception *exception)
1871c602 3556{
0f65dd70 3557 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 3558 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 3559}
3560
6a4d7550 3561int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 3562 gva_t addr, void *val,
2dafc6c2 3563 unsigned int bytes,
bcc55cba 3564 struct x86_exception *exception)
77c2002e 3565{
0f65dd70 3566 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 3567 void *data = val;
3568 int r = X86EMUL_CONTINUE;
3569
3570 while (bytes) {
14dfe855
JR		 3571 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3572 PFERR_WRITE_MASK,
ab9ae313 3573 exception);
77c2002e
IE		 3574 unsigned offset = addr & (PAGE_SIZE-1);
3575 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3576 int ret;
3577
bcc55cba 3578 if (gpa == UNMAPPED_GVA)
ab9ae313 3579 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 3580 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3581 if (ret < 0) {
c3cd7ffa 3582 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 3583 goto out;
3584 }
3585
3586 bytes -= towrite;
3587 data += towrite;
3588 addr += towrite;
3589 }
3590out:
3591 return r;
3592}
6a4d7550 3593EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 3594
af7cc7d1
XG		 3595static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
3596 gpa_t *gpa, struct x86_exception *exception,
3597 bool write)
3598{
3599 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3600
bebb106a
XG		 3601 if (vcpu_match_mmio_gva(vcpu, gva) &&
3602 check_write_user_access(vcpu, write, access,
3603 vcpu->arch.access)) {
3604 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
3605 (gva & (PAGE_SIZE - 1));
4f022648 3606 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 3607 return 1;
3608 }
3609
af7cc7d1
XG		 3610 if (write)
3611 access |= PFERR_WRITE_MASK;
3612
3613 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3614
3615 if (*gpa == UNMAPPED_GVA)
3616 return -1;
3617
3618 /* For APIC access vmexit */
3619 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3620 return 1;
3621
4f022648
XG		 3622 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
3623 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 3624 return 1;
4f022648 3625 }
bebb106a 3626
af7cc7d1
XG		 3627 return 0;
3628}
3629
3200f405 3630int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 3631 const void *val, int bytes)
bbd9b64e
CO		 3632{
3633 int ret;
3634
3635 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3636 if (ret < 0)
bbd9b64e 3637 return 0;
f57f2ef5 3638 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 3639 return 1;
3640}
3641
77d197b2
XG		 3642struct read_write_emulator_ops {
3643 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
3644 int bytes);
3645 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
3646 void *val, int bytes);
3647 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
3648 int bytes, void *val);
3649 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
3650 void *val, int bytes);
3651 bool write;
3652};
3653
3654static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
3655{
3656 if (vcpu->mmio_read_completed) {
3657 memcpy(val, vcpu->mmio_data, bytes);
3658 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3659 vcpu->mmio_phys_addr, *(u64 *)val);
3660 vcpu->mmio_read_completed = 0;
3661 return 1;
3662 }
3663
3664 return 0;
3665}
3666
3667static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
3668 void *val, int bytes)
3669{
3670 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
3671}
3672
3673static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
3674 void *val, int bytes)
3675{
3676 return emulator_write_phys(vcpu, gpa, val, bytes);
3677}
3678
3679static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
3680{
3681 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
3682 return vcpu_mmio_write(vcpu, gpa, bytes, val);
3683}
3684
3685static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
3686 void *val, int bytes)
3687{
3688 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
3689 return X86EMUL_IO_NEEDED;
3690}
3691
3692static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
3693 void *val, int bytes)
3694{
3695 memcpy(vcpu->mmio_data, val, bytes);
3696 memcpy(vcpu->run->mmio.data, vcpu->mmio_data, 8);
3697 return X86EMUL_CONTINUE;
3698}
3699
3700static struct read_write_emulator_ops read_emultor = {
3701 .read_write_prepare = read_prepare,
3702 .read_write_emulate = read_emulate,
3703 .read_write_mmio = vcpu_mmio_read,
3704 .read_write_exit_mmio = read_exit_mmio,
3705};
3706
3707static struct read_write_emulator_ops write_emultor = {
3708 .read_write_emulate = write_emulate,
3709 .read_write_mmio = write_mmio,
3710 .read_write_exit_mmio = write_exit_mmio,
3711 .write = true,
3712};
3713
22388a3c
XG		 3714static int emulator_read_write_onepage(unsigned long addr, void *val,
3715 unsigned int bytes,
3716 struct x86_exception *exception,
3717 struct kvm_vcpu *vcpu,
3718 struct read_write_emulator_ops *ops)
bbd9b64e 3719{
af7cc7d1
XG		 3720 gpa_t gpa;
3721 int handled, ret;
22388a3c
XG		 3722 bool write = ops->write;
3723
3724 if (ops->read_write_prepare &&
3725 ops->read_write_prepare(vcpu, val, bytes))
3726 return X86EMUL_CONTINUE;
10589a46 3727
22388a3c 3728 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 3729
af7cc7d1 3730 if (ret < 0)
bbd9b64e 3731 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3732
3733 /* For APIC access vmexit */
af7cc7d1 3734 if (ret)
bbd9b64e
CO		 3735 goto mmio;
3736
22388a3c 3737 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 3738 return X86EMUL_CONTINUE;
3739
3740mmio:
3741 /*
3742 * Is this MMIO handled locally?
3743 */
22388a3c 3744 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 3745 if (handled == bytes)
bbd9b64e 3746 return X86EMUL_CONTINUE;
bbd9b64e 3747
70252a10
AK		 3748 gpa += handled;
3749 bytes -= handled;
3750 val += handled;
3751
bbd9b64e 3752 vcpu->mmio_needed = 1;
411c35b7
GN		 3753 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3754 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
cef4dea0
AK		 3755 vcpu->mmio_size = bytes;
3756 vcpu->run->mmio.len = min(vcpu->mmio_size, 8);
22388a3c 3757 vcpu->run->mmio.is_write = vcpu->mmio_is_write = write;
cef4dea0 3758 vcpu->mmio_index = 0;
bbd9b64e 3759
22388a3c 3760 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
bbd9b64e
CO		 3761}
3762
22388a3c
XG		 3763int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
3764 void *val, unsigned int bytes,
3765 struct x86_exception *exception,
3766 struct read_write_emulator_ops *ops)
bbd9b64e 3767{
0f65dd70
AK		 3768 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3769
bbd9b64e
CO		 3770 /* Crossing a page boundary? */
3771 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3772 int rc, now;
3773
3774 now = -addr & ~PAGE_MASK;
22388a3c
XG		 3775 rc = emulator_read_write_onepage(addr, val, now, exception,
3776 vcpu, ops);
3777
bbd9b64e
CO		 3778 if (rc != X86EMUL_CONTINUE)
3779 return rc;
3780 addr += now;
3781 val += now;
3782 bytes -= now;
3783 }
22388a3c
XG		 3784
3785 return emulator_read_write_onepage(addr, val, bytes, exception,
3786 vcpu, ops);
3787}
3788
3789static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
3790 unsigned long addr,
3791 void *val,
3792 unsigned int bytes,
3793 struct x86_exception *exception)
3794{
3795 return emulator_read_write(ctxt, addr, val, bytes,
3796 exception, &read_emultor);
3797}
3798
3799int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
3800 unsigned long addr,
3801 const void *val,
3802 unsigned int bytes,
3803 struct x86_exception *exception)
3804{
3805 return emulator_read_write(ctxt, addr, (void *)val, bytes,
3806 exception, &write_emultor);
bbd9b64e 3807}
bbd9b64e 3808
daea3e73
AK		 3809#define CMPXCHG_TYPE(t, ptr, old, new) \
3810 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
3811
3812#ifdef CONFIG_X86_64
3813# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
3814#else
3815# define CMPXCHG64(ptr, old, new) \
9749a6c0 3816 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 3817#endif
3818
0f65dd70
AK		 3819static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
3820 unsigned long addr,
bbd9b64e
CO		 3821 const void *old,
3822 const void *new,
3823 unsigned int bytes,
0f65dd70 3824 struct x86_exception *exception)
bbd9b64e 3825{
0f65dd70 3826 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 3827 gpa_t gpa;
3828 struct page *page;
3829 char *kaddr;
3830 bool exchanged;
2bacc55c 3831
daea3e73
AK		 3832 /* guests cmpxchg8b have to be emulated atomically */
3833 if (bytes > 8 || (bytes & (bytes - 1)))
3834 goto emul_write;
10589a46 3835
daea3e73 3836 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 3837
daea3e73
AK		 3838 if (gpa == UNMAPPED_GVA ||
3839 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3840 goto emul_write;
2bacc55c 3841
daea3e73
AK		 3842 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3843 goto emul_write;
72dc67a6 3844
daea3e73 3845 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
c19b8bd6
WY		 3846 if (is_error_page(page)) {
3847 kvm_release_page_clean(page);
3848 goto emul_write;
3849 }
72dc67a6 3850
daea3e73
AK		 3851 kaddr = kmap_atomic(page, KM_USER0);
3852 kaddr += offset_in_page(gpa);
3853 switch (bytes) {
3854 case 1:
3855 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
3856 break;
3857 case 2:
3858 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
3859 break;
3860 case 4:
3861 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
3862 break;
3863 case 8:
3864 exchanged = CMPXCHG64(kaddr, old, new);
3865 break;
3866 default:
3867 BUG();
2bacc55c 3868 }
daea3e73
AK		 3869 kunmap_atomic(kaddr, KM_USER0);
3870 kvm_release_page_dirty(page);
3871
3872 if (!exchanged)
3873 return X86EMUL_CMPXCHG_FAILED;
3874
f57f2ef5 3875 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 3876
3877 return X86EMUL_CONTINUE;
4a5f48f6 3878
3200f405 3879emul_write:
daea3e73 3880 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 3881
0f65dd70 3882 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 3883}
3884
cf8f70bf
GN		 3885static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
3886{
3887 /* TODO: String I/O for in kernel device */
3888 int r;
3889
3890 if (vcpu->arch.pio.in)
3891 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
3892 vcpu->arch.pio.size, pd);
3893 else
3894 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3895 vcpu->arch.pio.port, vcpu->arch.pio.size,
3896 pd);
3897 return r;
3898}
3899
6f6fbe98
XG		 3900static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
3901 unsigned short port, void *val,
3902 unsigned int count, bool in)
cf8f70bf 3903{
6f6fbe98 3904 trace_kvm_pio(!in, port, size, count);
cf8f70bf
GN		 3905
3906 vcpu->arch.pio.port = port;
6f6fbe98 3907 vcpu->arch.pio.in = in;
7972995b 3908 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3909 vcpu->arch.pio.size = size;
3910
3911 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 3912 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3913 return 1;
3914 }
3915
3916 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 3917 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 3918 vcpu->run->io.size = size;
3919 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3920 vcpu->run->io.count = count;
3921 vcpu->run->io.port = port;
3922
3923 return 0;
3924}
3925
6f6fbe98
XG		 3926static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
3927 int size, unsigned short port, void *val,
3928 unsigned int count)
cf8f70bf 3929{
ca1d4a9e 3930 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 3931 int ret;
ca1d4a9e 3932
6f6fbe98
XG		 3933 if (vcpu->arch.pio.count)
3934 goto data_avail;
cf8f70bf 3935
6f6fbe98
XG		 3936 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
3937 if (ret) {
3938data_avail:
3939 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 3940 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3941 return 1;
3942 }
3943
cf8f70bf
GN		 3944 return 0;
3945}
3946
6f6fbe98
XG		 3947static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
3948 int size, unsigned short port,
3949 const void *val, unsigned int count)
3950{
3951 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3952
3953 memcpy(vcpu->arch.pio_data, val, size * count);
3954 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
3955}
3956
bbd9b64e
CO		 3957static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
3958{
3959 return kvm_x86_ops->get_segment_base(vcpu, seg);
3960}
3961
3cb16fe7 3962static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 3963{
3cb16fe7 3964 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 3965}
3966
f5f48ee1
SY		 3967int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
3968{
3969 if (!need_emulate_wbinvd(vcpu))
3970 return X86EMUL_CONTINUE;
3971
3972 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 3973 int cpu = get_cpu();
3974
3975 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 3976 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
3977 wbinvd_ipi, NULL, 1);
2eec7343 3978 put_cpu();
f5f48ee1 3979 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 3980 } else
3981 wbinvd();
f5f48ee1
SY		 3982 return X86EMUL_CONTINUE;
3983}
3984EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
3985
bcaf5cc5
AK		 3986static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
3987{
3988 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
3989}
3990
717746e3 3991int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
bbd9b64e 3992{
717746e3 3993 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 3994}
3995
717746e3 3996int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
bbd9b64e 3997{
338dbc97 3998
717746e3 3999 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4000}
4001
52a46617 4002static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4003{
52a46617 4004 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4005}
4006
717746e3 4007static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4008{
717746e3 4009 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4010 unsigned long value;
4011
4012 switch (cr) {
4013 case 0:
4014 value = kvm_read_cr0(vcpu);
4015 break;
4016 case 2:
4017 value = vcpu->arch.cr2;
4018 break;
4019 case 3:
9f8fe504 4020 value = kvm_read_cr3(vcpu);
52a46617
GN		 4021 break;
4022 case 4:
4023 value = kvm_read_cr4(vcpu);
4024 break;
4025 case 8:
4026 value = kvm_get_cr8(vcpu);
4027 break;
4028 default:
4029 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
4030 return 0;
4031 }
4032
4033 return value;
4034}
4035
717746e3 4036static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4037{
717746e3 4038 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4039 int res = 0;
4040
52a46617
GN		 4041 switch (cr) {
4042 case 0:
49a9b07e 4043 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4044 break;
4045 case 2:
4046 vcpu->arch.cr2 = val;
4047 break;
4048 case 3:
2390218b 4049 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4050 break;
4051 case 4:
a83b29c6 4052 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4053 break;
4054 case 8:
eea1cff9 4055 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4056 break;
4057 default:
4058 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
0f12244f 4059 res = -1;
52a46617 4060 }
0f12244f
GN		 4061
4062 return res;
52a46617
GN		 4063}
4064
717746e3 4065static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4066{
717746e3 4067 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4068}
4069
4bff1e86 4070static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4071{
4bff1e86 4072 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4073}
4074
4bff1e86 4075static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4076{
4bff1e86 4077 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4078}
4079
1ac9d0cf
AK		 4080static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4081{
4082 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4083}
4084
4085static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4086{
4087 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4088}
4089
4bff1e86
AK		 4090static unsigned long emulator_get_cached_segment_base(
4091 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4092{
4bff1e86 4093 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4094}
4095
1aa36616
AK		 4096static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4097 struct desc_struct *desc, u32 *base3,
4098 int seg)
2dafc6c2
GN		 4099{
4100 struct kvm_segment var;
4101
4bff1e86 4102 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4103 *selector = var.selector;
2dafc6c2
GN		 4104
4105 if (var.unusable)
4106 return false;
4107
4108 if (var.g)
4109 var.limit >>= 12;
4110 set_desc_limit(desc, var.limit);
4111 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4112#ifdef CONFIG_X86_64
4113 if (base3)
4114 *base3 = var.base >> 32;
4115#endif
2dafc6c2
GN		 4116 desc->type = var.type;
4117 desc->s = var.s;
4118 desc->dpl = var.dpl;
4119 desc->p = var.present;
4120 desc->avl = var.avl;
4121 desc->l = var.l;
4122 desc->d = var.db;
4123 desc->g = var.g;
4124
4125 return true;
4126}
4127
1aa36616
AK		 4128static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4129 struct desc_struct *desc, u32 base3,
4130 int seg)
2dafc6c2 4131{
4bff1e86 4132 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4133 struct kvm_segment var;
4134
1aa36616 4135 var.selector = selector;
2dafc6c2 4136 var.base = get_desc_base(desc);
5601d05b
GN		 4137#ifdef CONFIG_X86_64
4138 var.base |= ((u64)base3) << 32;
4139#endif
2dafc6c2
GN		 4140 var.limit = get_desc_limit(desc);
4141 if (desc->g)
4142 var.limit = (var.limit << 12) | 0xfff;
4143 var.type = desc->type;
4144 var.present = desc->p;
4145 var.dpl = desc->dpl;
4146 var.db = desc->d;
4147 var.s = desc->s;
4148 var.l = desc->l;
4149 var.g = desc->g;
4150 var.avl = desc->avl;
4151 var.present = desc->p;
4152 var.unusable = !var.present;
4153 var.padding = 0;
4154
4155 kvm_set_segment(vcpu, &var, seg);
4156 return;
4157}
4158
717746e3
AK		 4159static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4160 u32 msr_index, u64 *pdata)
4161{
4162 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4163}
4164
4165static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4166 u32 msr_index, u64 data)
4167{
4168 return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
4169}
4170
222d21aa
AK		 4171static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4172 u32 pmc, u64 *pdata)
4173{
4174 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4175}
4176
6c3287f7
AK		 4177static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4178{
4179 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4180}
4181
5037f6f3
AK		 4182static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4183{
4184 preempt_disable();
5197b808 4185 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4186 /*
4187 * CR0.TS may reference the host fpu state, not the guest fpu state,
4188 * so it may be clear at this point.
4189 */
4190 clts();
4191}
4192
4193static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4194{
4195 preempt_enable();
4196}
4197
2953538e 4198static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4199 struct x86_instruction_info *info,
c4f035c6
AK		 4200 enum x86_intercept_stage stage)
4201{
2953538e 4202 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4203}
4204
bdb42f5a
SB		 4205static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
4206 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4207{
4208 struct kvm_cpuid_entry2 *cpuid = NULL;
4209
4210 if (eax && ecx)
4211 cpuid = kvm_find_cpuid_entry(emul_to_vcpu(ctxt),
4212 *eax, *ecx);
4213
4214 if (cpuid) {
4215 *eax = cpuid->eax;
4216 *ecx = cpuid->ecx;
4217 if (ebx)
4218 *ebx = cpuid->ebx;
4219 if (edx)
4220 *edx = cpuid->edx;
4221 return true;
4222 }
4223
4224 return false;
4225}
4226
14af3f3c 4227static struct x86_emulate_ops emulate_ops = {
1871c602 4228 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4229 .write_std = kvm_write_guest_virt_system,
1871c602 4230 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4231 .read_emulated = emulator_read_emulated,
4232 .write_emulated = emulator_write_emulated,
4233 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4234 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4235 .pio_in_emulated = emulator_pio_in_emulated,
4236 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4237 .get_segment = emulator_get_segment,
4238 .set_segment = emulator_set_segment,
5951c442 4239 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4240 .get_gdt = emulator_get_gdt,
160ce1f1 4241 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4242 .set_gdt = emulator_set_gdt,
4243 .set_idt = emulator_set_idt,
52a46617
GN		 4244 .get_cr = emulator_get_cr,
4245 .set_cr = emulator_set_cr,
9c537244 4246 .cpl = emulator_get_cpl,
35aa5375
GN		 4247 .get_dr = emulator_get_dr,
4248 .set_dr = emulator_set_dr,
717746e3
AK		 4249 .set_msr = emulator_set_msr,
4250 .get_msr = emulator_get_msr,
222d21aa 4251 .read_pmc = emulator_read_pmc,
6c3287f7 4252 .halt = emulator_halt,
bcaf5cc5 4253 .wbinvd = emulator_wbinvd,
d6aa1000 4254 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4255 .get_fpu = emulator_get_fpu,
4256 .put_fpu = emulator_put_fpu,
c4f035c6 4257 .intercept = emulator_intercept,
bdb42f5a 4258 .get_cpuid = emulator_get_cpuid,
bbd9b64e
CO		 4259};
4260
5fdbf976
MT		 4261static void cache_all_regs(struct kvm_vcpu *vcpu)
4262{
4263 kvm_register_read(vcpu, VCPU_REGS_RAX);
4264 kvm_register_read(vcpu, VCPU_REGS_RSP);
4265 kvm_register_read(vcpu, VCPU_REGS_RIP);
4266 vcpu->arch.regs_dirty = ~0;
4267}
4268
95cb2295
GN		 4269static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4270{
4271 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4272 /*
4273 * an sti; sti; sequence only disable interrupts for the first
4274 * instruction. So, if the last instruction, be it emulated or
4275 * not, left the system with the INT_STI flag enabled, it
4276 * means that the last instruction is an sti. We should not
4277 * leave the flag on in this case. The same goes for mov ss
4278 */
4279 if (!(int_shadow & mask))
4280 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4281}
4282
54b8486f
GN		 4283static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4284{
4285 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4286 if (ctxt->exception.vector == PF_VECTOR)
6389ee94 4287 kvm_propagate_fault(vcpu, &ctxt->exception);
da9cb575
AK		 4288 else if (ctxt->exception.error_code_valid)
4289 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4290 ctxt->exception.error_code);
54b8486f 4291 else
da9cb575 4292 kvm_queue_exception(vcpu, ctxt->exception.vector);
54b8486f
GN		 4293}
4294
9dac77fa 4295static void init_decode_cache(struct x86_emulate_ctxt *ctxt,
b5c9ff73
TY		 4296 const unsigned long *regs)
4297{
9dac77fa
AK		 4298 memset(&ctxt->twobyte, 0,
4299 (void *)&ctxt->regs - (void *)&ctxt->twobyte);
4300 memcpy(ctxt->regs, regs, sizeof(ctxt->regs));
b5c9ff73 4301
9dac77fa
AK		 4302 ctxt->fetch.start = 0;
4303 ctxt->fetch.end = 0;
4304 ctxt->io_read.pos = 0;
4305 ctxt->io_read.end = 0;
4306 ctxt->mem_read.pos = 0;
4307 ctxt->mem_read.end = 0;
b5c9ff73
TY		 4308}
4309
8ec4722d
MG		 4310static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4311{
adf52235 4312 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4313 int cs_db, cs_l;
4314
2aab2c5b
GN		 4315 /*
4316 * TODO: fix emulate.c to use guest_read/write_register
4317 * instead of direct ->regs accesses, can save hundred cycles
4318 * on Intel for instructions that don't read/change RSP, for
4319 * for example.
4320 */
8ec4722d
MG		 4321 cache_all_regs(vcpu);
4322
4323 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4324
adf52235
TY		 4325 ctxt->eflags = kvm_get_rflags(vcpu);
4326 ctxt->eip = kvm_rip_read(vcpu);
4327 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4328 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4329 cs_l ? X86EMUL_MODE_PROT64 :
4330 cs_db ? X86EMUL_MODE_PROT32 :
4331 X86EMUL_MODE_PROT16;
4332 ctxt->guest_mode = is_guest_mode(vcpu);
4333
9dac77fa 4334 init_decode_cache(ctxt, vcpu->arch.regs);
7ae441ea 4335 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4336}
4337
71f9833b 4338int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 4339{
9d74191a 4340 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 4341 int ret;
4342
4343 init_emulate_ctxt(vcpu);
4344
9dac77fa
AK		 4345 ctxt->op_bytes = 2;
4346 ctxt->ad_bytes = 2;
4347 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 4348 ret = emulate_int_real(ctxt, irq);
63995653
MG		 4349
4350 if (ret != X86EMUL_CONTINUE)
4351 return EMULATE_FAIL;
4352
9dac77fa
AK		 4353 ctxt->eip = ctxt->_eip;
4354 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
9d74191a
TY		 4355 kvm_rip_write(vcpu, ctxt->eip);
4356 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 4357
4358 if (irq == NMI_VECTOR)
7460fb4a 4359 vcpu->arch.nmi_pending = 0;
63995653
MG		 4360 else
4361 vcpu->arch.interrupt.pending = false;
4362
4363 return EMULATE_DONE;
4364}
4365EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4366
6d77dbfc
GN		 4367static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4368{
fc3a9157
JR		 4369 int r = EMULATE_DONE;
4370
6d77dbfc
GN		 4371 ++vcpu->stat.insn_emulation_fail;
4372 trace_kvm_emulate_insn_failed(vcpu);
fc3a9157
JR		 4373 if (!is_guest_mode(vcpu)) {
4374 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4375 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4376 vcpu->run->internal.ndata = 0;
4377 r = EMULATE_FAIL;
4378 }
6d77dbfc 4379 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4380
4381 return r;
6d77dbfc
GN		 4382}
4383
a6f177ef
GN		 4384static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
4385{
4386 gpa_t gpa;
4387
68be0803
GN		 4388 if (tdp_enabled)
4389 return false;
4390
a6f177ef
GN		 4391 /*
4392 * if emulation was due to access to shadowed page table
4393 * and it failed try to unshadow page and re-entetr the
4394 * guest to let CPU execute the instruction.
4395 */
4396 if (kvm_mmu_unprotect_page_virt(vcpu, gva))
4397 return true;
4398
4399 gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
4400
4401 if (gpa == UNMAPPED_GVA)
4402 return true; /* let cpu generate fault */
4403
4404 if (!kvm_is_error_hva(gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT)))
4405 return true;
4406
4407 return false;
4408}
4409
1cb3f3ae
XG		 4410static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
4411 unsigned long cr2, int emulation_type)
4412{
4413 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4414 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
4415
4416 last_retry_eip = vcpu->arch.last_retry_eip;
4417 last_retry_addr = vcpu->arch.last_retry_addr;
4418
4419 /*
4420 * If the emulation is caused by #PF and it is non-page_table
4421 * writing instruction, it means the VM-EXIT is caused by shadow
4422 * page protected, we can zap the shadow page and retry this
4423 * instruction directly.
4424 *
4425 * Note: if the guest uses a non-page-table modifying instruction
4426 * on the PDE that points to the instruction, then we will unmap
4427 * the instruction and go to an infinite loop. So, we cache the
4428 * last retried eip and the last fault address, if we meet the eip
4429 * and the address again, we can break out of the potential infinite
4430 * loop.
4431 */
4432 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
4433
4434 if (!(emulation_type & EMULTYPE_RETRY))
4435 return false;
4436
4437 if (x86_page_table_writing_insn(ctxt))
4438 return false;
4439
4440 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
4441 return false;
4442
4443 vcpu->arch.last_retry_eip = ctxt->eip;
4444 vcpu->arch.last_retry_addr = cr2;
4445
4446 if (!vcpu->arch.mmu.direct_map)
4447 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4448
4449 kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4450
4451 return true;
4452}
4453
51d8b661
AP		 4454int x86_emulate_instruction(struct kvm_vcpu *vcpu,
4455 unsigned long cr2,
dc25e89e
AP		 4456 int emulation_type,
4457 void *insn,
4458 int insn_len)
bbd9b64e 4459{
95cb2295 4460 int r;
9d74191a 4461 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 4462 bool writeback = true;
bbd9b64e 4463
26eef70c 4464 kvm_clear_exception_queue(vcpu);
8d7d8102 4465
571008da 4466 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 4467 init_emulate_ctxt(vcpu);
9d74191a
TY		 4468 ctxt->interruptibility = 0;
4469 ctxt->have_exception = false;
4470 ctxt->perm_ok = false;
bbd9b64e 4471
9d74191a 4472 ctxt->only_vendor_specific_insn
4005996e
AK		 4473 = emulation_type & EMULTYPE_TRAP_UD;
4474
9d74191a 4475 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 4476
e46479f8 4477 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 4478 ++vcpu->stat.insn_emulation;
1d2887e2 4479 if (r != EMULATION_OK) {
4005996e
AK		 4480 if (emulation_type & EMULTYPE_TRAP_UD)
4481 return EMULATE_FAIL;
a6f177ef 4482 if (reexecute_instruction(vcpu, cr2))
bbd9b64e 4483 return EMULATE_DONE;
6d77dbfc
GN		 4484 if (emulation_type & EMULTYPE_SKIP)
4485 return EMULATE_FAIL;
4486 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4487 }
4488 }
4489
ba8afb6b 4490 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 4491 kvm_rip_write(vcpu, ctxt->_eip);
ba8afb6b
GN		 4492 return EMULATE_DONE;
4493 }
4494
1cb3f3ae
XG		 4495 if (retry_instruction(ctxt, cr2, emulation_type))
4496 return EMULATE_DONE;
4497
7ae441ea 4498 /* this is needed for vmware backdoor interface to work since it
4d2179e1 4499 changes registers values during IO operation */
7ae441ea
GN		 4500 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
4501 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
9dac77fa 4502 memcpy(ctxt->regs, vcpu->arch.regs, sizeof ctxt->regs);
7ae441ea 4503 }
4d2179e1 4504
5cd21917 4505restart:
9d74191a 4506 r = x86_emulate_insn(ctxt);
bbd9b64e 4507
775fde86
JR		 4508 if (r == EMULATION_INTERCEPTED)
4509 return EMULATE_DONE;
4510
d2ddd1c4 4511 if (r == EMULATION_FAILED) {
a6f177ef 4512 if (reexecute_instruction(vcpu, cr2))
c3cd7ffa
GN		 4513 return EMULATE_DONE;
4514
6d77dbfc 4515 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4516 }
4517
9d74191a 4518 if (ctxt->have_exception) {
54b8486f 4519 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 4520 r = EMULATE_DONE;
4521 } else if (vcpu->arch.pio.count) {
3457e419
GN		 4522 if (!vcpu->arch.pio.in)
4523 vcpu->arch.pio.count = 0;
7ae441ea
GN		 4524 else
4525 writeback = false;
e85d28f8 4526 r = EMULATE_DO_MMIO;
7ae441ea
GN		 4527 } else if (vcpu->mmio_needed) {
4528 if (!vcpu->mmio_is_write)
4529 writeback = false;
e85d28f8 4530 r = EMULATE_DO_MMIO;
7ae441ea 4531 } else if (r == EMULATION_RESTART)
5cd21917 4532 goto restart;
d2ddd1c4
GN		 4533 else
4534 r = EMULATE_DONE;
f850e2e6 4535
7ae441ea 4536 if (writeback) {
9d74191a
TY		 4537 toggle_interruptibility(vcpu, ctxt->interruptibility);
4538 kvm_set_rflags(vcpu, ctxt->eflags);
7ae441ea 4539 kvm_make_request(KVM_REQ_EVENT, vcpu);
9dac77fa 4540 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
7ae441ea 4541 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 4542 kvm_rip_write(vcpu, ctxt->eip);
7ae441ea
GN		 4543 } else
4544 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 4545
4546 return r;
de7d789a 4547}
51d8b661 4548EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 4549
cf8f70bf 4550int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 4551{
cf8f70bf 4552 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 4553 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
4554 size, port, &val, 1);
cf8f70bf 4555 /* do not return to emulator after return from userspace */
7972995b 4556 vcpu->arch.pio.count = 0;
de7d789a
CO		 4557 return ret;
4558}
cf8f70bf 4559EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 4560
8cfdc000
ZA		 4561static void tsc_bad(void *info)
4562{
0a3aee0d 4563 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 4564}
4565
4566static void tsc_khz_changed(void *data)
c8076604 4567{
8cfdc000
ZA		 4568 struct cpufreq_freqs *freq = data;
4569 unsigned long khz = 0;
4570
4571 if (data)
4572 khz = freq->new;
4573 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4574 khz = cpufreq_quick_get(raw_smp_processor_id());
4575 if (!khz)
4576 khz = tsc_khz;
0a3aee0d 4577 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 4578}
4579
c8076604
GH		 4580static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4581 void *data)
4582{
4583 struct cpufreq_freqs *freq = data;
4584 struct kvm *kvm;
4585 struct kvm_vcpu *vcpu;
4586 int i, send_ipi = 0;
4587
8cfdc000
ZA		 4588 /*
4589 * We allow guests to temporarily run on slowing clocks,
4590 * provided we notify them after, or to run on accelerating
4591 * clocks, provided we notify them before. Thus time never
4592 * goes backwards.
4593 *
4594 * However, we have a problem. We can't atomically update
4595 * the frequency of a given CPU from this function; it is
4596 * merely a notifier, which can be called from any CPU.
4597 * Changing the TSC frequency at arbitrary points in time
4598 * requires a recomputation of local variables related to
4599 * the TSC for each VCPU. We must flag these local variables
4600 * to be updated and be sure the update takes place with the
4601 * new frequency before any guests proceed.
4602 *
4603 * Unfortunately, the combination of hotplug CPU and frequency
4604 * change creates an intractable locking scenario; the order
4605 * of when these callouts happen is undefined with respect to
4606 * CPU hotplug, and they can race with each other. As such,
4607 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
4608 * undefined; you can actually have a CPU frequency change take
4609 * place in between the computation of X and the setting of the
4610 * variable. To protect against this problem, all updates of
4611 * the per_cpu tsc_khz variable are done in an interrupt
4612 * protected IPI, and all callers wishing to update the value
4613 * must wait for a synchronous IPI to complete (which is trivial
4614 * if the caller is on the CPU already). This establishes the
4615 * necessary total order on variable updates.
4616 *
4617 * Note that because a guest time update may take place
4618 * anytime after the setting of the VCPU's request bit, the
4619 * correct TSC value must be set before the request. However,
4620 * to ensure the update actually makes it to any guest which
4621 * starts running in hardware virtualization between the set
4622 * and the acquisition of the spinlock, we must also ping the
4623 * CPU after setting the request bit.
4624 *
4625 */
4626
c8076604
GH		 4627 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
4628 return 0;
4629 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
4630 return 0;
8cfdc000
ZA		 4631
4632 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 4633
e935b837 4634 raw_spin_lock(&kvm_lock);
c8076604 4635 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 4636 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 4637 if (vcpu->cpu != freq->cpu)
4638 continue;
c285545f 4639 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 4640 if (vcpu->cpu != smp_processor_id())
8cfdc000 4641 send_ipi = 1;
c8076604
GH		 4642 }
4643 }
e935b837 4644 raw_spin_unlock(&kvm_lock);
c8076604
GH		 4645
4646 if (freq->old < freq->new && send_ipi) {
4647 /*
4648 * We upscale the frequency. Must make the guest
4649 * doesn't see old kvmclock values while running with
4650 * the new frequency, otherwise we risk the guest sees
4651 * time go backwards.
4652 *
4653 * In case we update the frequency for another cpu
4654 * (which might be in guest context) send an interrupt
4655 * to kick the cpu out of guest context. Next time
4656 * guest context is entered kvmclock will be updated,
4657 * so the guest will not see stale values.
4658 */
8cfdc000 4659 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 4660 }
4661 return 0;
4662}
4663
4664static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 4665 .notifier_call = kvmclock_cpufreq_notifier
4666};
4667
4668static int kvmclock_cpu_notifier(struct notifier_block *nfb,
4669 unsigned long action, void *hcpu)
4670{
4671 unsigned int cpu = (unsigned long)hcpu;
4672
4673 switch (action) {
4674 case CPU_ONLINE:
4675 case CPU_DOWN_FAILED:
4676 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4677 break;
4678 case CPU_DOWN_PREPARE:
4679 smp_call_function_single(cpu, tsc_bad, NULL, 1);
4680 break;
4681 }
4682 return NOTIFY_OK;
4683}
4684
4685static struct notifier_block kvmclock_cpu_notifier_block = {
4686 .notifier_call = kvmclock_cpu_notifier,
4687 .priority = -INT_MAX
c8076604
GH		 4688};
4689
b820cc0c
ZA		 4690static void kvm_timer_init(void)
4691{
4692 int cpu;
4693
c285545f 4694 max_tsc_khz = tsc_khz;
8cfdc000 4695 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 4696 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 4697#ifdef CONFIG_CPU_FREQ
4698 struct cpufreq_policy policy;
4699 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 4700 cpu = get_cpu();
4701 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 4702 if (policy.cpuinfo.max_freq)
4703 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 4704 put_cpu();
c285545f 4705#endif
b820cc0c
ZA		 4706 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4707 CPUFREQ_TRANSITION_NOTIFIER);
4708 }
c285545f 4709 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 4710 for_each_online_cpu(cpu)
4711 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 4712}
4713
ff9d07a0
ZY		 4714static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
4715
f5132b01 4716int kvm_is_in_guest(void)
ff9d07a0 4717{
086c9855 4718 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 4719}
4720
4721static int kvm_is_user_mode(void)
4722{
4723 int user_mode = 3;
dcf46b94 4724
086c9855
AS		 4725 if (__this_cpu_read(current_vcpu))
4726 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 4727
ff9d07a0
ZY		 4728 return user_mode != 0;
4729}
4730
4731static unsigned long kvm_get_guest_ip(void)
4732{
4733 unsigned long ip = 0;
dcf46b94 4734
086c9855
AS		 4735 if (__this_cpu_read(current_vcpu))
4736 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 4737
ff9d07a0
ZY		 4738 return ip;
4739}
4740
4741static struct perf_guest_info_callbacks kvm_guest_cbs = {
4742 .is_in_guest = kvm_is_in_guest,
4743 .is_user_mode = kvm_is_user_mode,
4744 .get_guest_ip = kvm_get_guest_ip,
4745};
4746
4747void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4748{
086c9855 4749 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 4750}
4751EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4752
4753void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4754{
086c9855 4755 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 4756}
4757EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4758
ce88decf
XG		 4759static void kvm_set_mmio_spte_mask(void)
4760{
4761 u64 mask;
4762 int maxphyaddr = boot_cpu_data.x86_phys_bits;
4763
4764 /*
4765 * Set the reserved bits and the present bit of an paging-structure
4766 * entry to generate page fault with PFER.RSV = 1.
4767 */
4768 mask = ((1ull << (62 - maxphyaddr + 1)) - 1) << maxphyaddr;
4769 mask |= 1ull;
4770
4771#ifdef CONFIG_X86_64
4772 /*
4773 * If reserved bit is not supported, clear the present bit to disable
4774 * mmio page fault.
4775 */
4776 if (maxphyaddr == 52)
4777 mask &= ~1ull;
4778#endif
4779
4780 kvm_mmu_set_mmio_spte_mask(mask);
4781}
4782
f8c16bba 4783int kvm_arch_init(void *opaque)
043405e1 4784{
b820cc0c 4785 int r;
f8c16bba
ZX		 4786 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4787
f8c16bba
ZX		 4788 if (kvm_x86_ops) {
4789 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 4790 r = -EEXIST;
4791 goto out;
f8c16bba
ZX		 4792 }
4793
4794 if (!ops->cpu_has_kvm_support()) {
4795 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 4796 r = -EOPNOTSUPP;
4797 goto out;
f8c16bba
ZX		 4798 }
4799 if (ops->disabled_by_bios()) {
4800 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 4801 r = -EOPNOTSUPP;
4802 goto out;
f8c16bba
ZX		 4803 }
4804
97db56ce
AK		 4805 r = kvm_mmu_module_init();
4806 if (r)
4807 goto out;
4808
ce88decf 4809 kvm_set_mmio_spte_mask();
97db56ce
AK		 4810 kvm_init_msr_list();
4811
f8c16bba 4812 kvm_x86_ops = ops;
7b52345e 4813 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 4814 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 4815
b820cc0c 4816 kvm_timer_init();
c8076604 4817
ff9d07a0
ZY		 4818 perf_register_guest_info_callbacks(&kvm_guest_cbs);
4819
2acf923e
DC		 4820 if (cpu_has_xsave)
4821 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
4822
f8c16bba 4823 return 0;
56c6d28a
ZX		 4824
4825out:
56c6d28a 4826 return r;
043405e1 4827}
8776e519 4828
f8c16bba
ZX		 4829void kvm_arch_exit(void)
4830{
ff9d07a0
ZY		 4831 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4832
888d256e
JK		 4833 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4834 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4835 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 4836 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
f8c16bba 4837 kvm_x86_ops = NULL;
56c6d28a
ZX		 4838 kvm_mmu_module_exit();
4839}
f8c16bba 4840
8776e519
HB		 4841int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4842{
4843 ++vcpu->stat.halt_exits;
4844 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 4845 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 4846 return 1;
4847 } else {
4848 vcpu->run->exit_reason = KVM_EXIT_HLT;
4849 return 0;
4850 }
4851}
4852EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4853
55cd8e5a
GN		 4854int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
4855{
4856 u64 param, ingpa, outgpa, ret;
4857 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
4858 bool fast, longmode;
4859 int cs_db, cs_l;
4860
4861 /*
4862 * hypercall generates UD from non zero cpl and real mode
4863 * per HYPER-V spec
4864 */
3eeb3288 4865 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 4866 kvm_queue_exception(vcpu, UD_VECTOR);
4867 return 0;
4868 }
4869
4870 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4871 longmode = is_long_mode(vcpu) && cs_l == 1;
4872
4873 if (!longmode) {
ccd46936
GN		 4874 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
4875 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
4876 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
4877 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
4878 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
4879 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 4880 }
4881#ifdef CONFIG_X86_64
4882 else {
4883 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
4884 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
4885 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
4886 }
4887#endif
4888
4889 code = param & 0xffff;
4890 fast = (param >> 16) & 0x1;
4891 rep_cnt = (param >> 32) & 0xfff;
4892 rep_idx = (param >> 48) & 0xfff;
4893
4894 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
4895
c25bc163
GN		 4896 switch (code) {
4897 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
4898 kvm_vcpu_on_spin(vcpu);
4899 break;
4900 default:
4901 res = HV_STATUS_INVALID_HYPERCALL_CODE;
4902 break;
4903 }
55cd8e5a
GN		 4904
4905 ret = res | (((u64)rep_done & 0xfff) << 32);
4906 if (longmode) {
4907 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
4908 } else {
4909 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
4910 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
4911 }
4912
4913 return 1;
4914}
4915
8776e519
HB		 4916int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
4917{
4918 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 4919 int r = 1;
8776e519 4920
55cd8e5a
GN		 4921 if (kvm_hv_hypercall_enabled(vcpu->kvm))
4922 return kvm_hv_hypercall(vcpu);
4923
5fdbf976
MT		 4924 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
4925 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
4926 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
4927 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
4928 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 4929
229456fc 4930 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 4931
8776e519
HB		 4932 if (!is_long_mode(vcpu)) {
4933 nr &= 0xFFFFFFFF;
4934 a0 &= 0xFFFFFFFF;
4935 a1 &= 0xFFFFFFFF;
4936 a2 &= 0xFFFFFFFF;
4937 a3 &= 0xFFFFFFFF;
4938 }
4939
07708c4a
JK		 4940 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
4941 ret = -KVM_EPERM;
4942 goto out;
4943 }
4944
8776e519 4945 switch (nr) {
b93463aa
AK		 4946 case KVM_HC_VAPIC_POLL_IRQ:
4947 ret = 0;
4948 break;
8776e519
HB		 4949 default:
4950 ret = -KVM_ENOSYS;
4951 break;
4952 }
07708c4a 4953out:
5fdbf976 4954 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 4955 ++vcpu->stat.hypercalls;
2f333bcb 4956 return r;
8776e519
HB		 4957}
4958EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
4959
d6aa1000 4960int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 4961{
d6aa1000 4962 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 4963 char instruction[3];
5fdbf976 4964 unsigned long rip = kvm_rip_read(vcpu);
8776e519 4965
8776e519
HB		 4966 /*
4967 * Blow out the MMU to ensure that no other VCPU has an active mapping
4968 * to ensure that the updated hypercall appears atomically across all
4969 * VCPUs.
4970 */
4971 kvm_mmu_zap_all(vcpu->kvm);
4972
8776e519 4973 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 4974
9d74191a 4975 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 4976}
4977
b6c7a5dc
HB		 4978/*
4979 * Check if userspace requested an interrupt window, and that the
4980 * interrupt window is open.
4981 *
4982 * No need to exit to userspace if we already have an interrupt queued.
4983 */
851ba692 4984static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 4985{
8061823a 4986 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 4987 vcpu->run->request_interrupt_window &&
5df56646 4988 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 4989}
4990
851ba692 4991static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 4992{
851ba692
AK		 4993 struct kvm_run *kvm_run = vcpu->run;
4994
91586a3b 4995 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 4996 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 4997 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 4998 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 4999 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5000 else
b6c7a5dc 5001 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5002 kvm_arch_interrupt_allowed(vcpu) &&
5003 !kvm_cpu_has_interrupt(vcpu) &&
5004 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5005}
5006
b93463aa
AK		 5007static void vapic_enter(struct kvm_vcpu *vcpu)
5008{
5009 struct kvm_lapic *apic = vcpu->arch.apic;
5010 struct page *page;
5011
5012 if (!apic || !apic->vapic_addr)
5013 return;
5014
5015 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 5016
5017 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 5018}
5019
5020static void vapic_exit(struct kvm_vcpu *vcpu)
5021{
5022 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 5023 int idx;
b93463aa
AK		 5024
5025 if (!apic || !apic->vapic_addr)
5026 return;
5027
f656ce01 5028 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 5029 kvm_release_page_dirty(apic->vapic_page);
5030 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 5031 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 5032}
5033
95ba8273
GN		 5034static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5035{
5036 int max_irr, tpr;
5037
5038 if (!kvm_x86_ops->update_cr8_intercept)
5039 return;
5040
88c808fd
AK		 5041 if (!vcpu->arch.apic)
5042 return;
5043
8db3baa2
GN		 5044 if (!vcpu->arch.apic->vapic_addr)
5045 max_irr = kvm_lapic_find_highest_irr(vcpu);
5046 else
5047 max_irr = -1;
95ba8273
GN		 5048
5049 if (max_irr != -1)
5050 max_irr >>= 4;
5051
5052 tpr = kvm_lapic_get_cr8(vcpu);
5053
5054 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5055}
5056
851ba692 5057static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 5058{
5059 /* try to reinject previous events if any */
b59bb7bd 5060 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5061 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5062 vcpu->arch.exception.has_error_code,
5063 vcpu->arch.exception.error_code);
b59bb7bd
GN		 5064 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5065 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5066 vcpu->arch.exception.error_code,
5067 vcpu->arch.exception.reinject);
b59bb7bd
GN		 5068 return;
5069 }
5070
95ba8273
GN		 5071 if (vcpu->arch.nmi_injected) {
5072 kvm_x86_ops->set_nmi(vcpu);
5073 return;
5074 }
5075
5076 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5077 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5078 return;
5079 }
5080
5081 /* try to inject new event if pending */
5082 if (vcpu->arch.nmi_pending) {
5083 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 5084 --vcpu->arch.nmi_pending;
95ba8273
GN		 5085 vcpu->arch.nmi_injected = true;
5086 kvm_x86_ops->set_nmi(vcpu);
5087 }
5088 } else if (kvm_cpu_has_interrupt(vcpu)) {
5089 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5090 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5091 false);
5092 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5093 }
5094 }
5095}
5096
2acf923e
DC		 5097static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
5098{
5099 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
5100 !vcpu->guest_xcr0_loaded) {
5101 /* kvm_set_xcr() also depends on this */
5102 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
5103 vcpu->guest_xcr0_loaded = 1;
5104 }
5105}
5106
5107static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
5108{
5109 if (vcpu->guest_xcr0_loaded) {
5110 if (vcpu->arch.xcr0 != host_xcr0)
5111 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
5112 vcpu->guest_xcr0_loaded = 0;
5113 }
5114}
5115
7460fb4a
AK		 5116static void process_nmi(struct kvm_vcpu *vcpu)
5117{
5118 unsigned limit = 2;
5119
5120 /*
5121 * x86 is limited to one NMI running, and one NMI pending after it.
5122 * If an NMI is already in progress, limit further NMIs to just one.
5123 * Otherwise, allow two (and we'll inject the first one immediately).
5124 */
5125 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5126 limit = 1;
5127
5128 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5129 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5130 kvm_make_request(KVM_REQ_EVENT, vcpu);
5131}
5132
851ba692 5133static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5134{
5135 int r;
6a8b1d13 5136 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5137 vcpu->run->request_interrupt_window;
d6185f20 5138 bool req_immediate_exit = 0;
b6c7a5dc 5139
3e007509 5140 if (vcpu->requests) {
a8eeb04a 5141 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5142 kvm_mmu_unload(vcpu);
a8eeb04a 5143 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5144 __kvm_migrate_timers(vcpu);
34c238a1
ZA		 5145 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5146 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 5147 if (unlikely(r))
5148 goto out;
5149 }
a8eeb04a 5150 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5151 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5152 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5153 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5154 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5155 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5156 r = 0;
5157 goto out;
5158 }
a8eeb04a 5159 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5160 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5161 r = 0;
5162 goto out;
5163 }
a8eeb04a 5164 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5165 vcpu->fpu_active = 0;
5166 kvm_x86_ops->fpu_deactivate(vcpu);
5167 }
af585b92
GN		 5168 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5169 /* Page is swapped out. Do synthetic halt */
5170 vcpu->arch.apf.halted = true;
5171 r = 1;
5172 goto out;
5173 }
c9aaa895
GC		 5174 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5175 record_steal_time(vcpu);
7460fb4a
AK		 5176 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5177 process_nmi(vcpu);
d6185f20
NHE		 5178 req_immediate_exit =
5179 kvm_check_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
f5132b01
GN		 5180 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5181 kvm_handle_pmu_event(vcpu);
5182 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5183 kvm_deliver_pmi(vcpu);
2f52d58c 5184 }
b93463aa 5185
3e007509
AK		 5186 r = kvm_mmu_reload(vcpu);
5187 if (unlikely(r))
5188 goto out;
5189
b463a6f7
AK		 5190 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5191 inject_pending_event(vcpu);
5192
5193 /* enable NMI/IRQ window open exits if needed */
7460fb4a 5194 if (vcpu->arch.nmi_pending)
b463a6f7
AK		 5195 kvm_x86_ops->enable_nmi_window(vcpu);
5196 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
5197 kvm_x86_ops->enable_irq_window(vcpu);
5198
5199 if (kvm_lapic_enabled(vcpu)) {
5200 update_cr8_intercept(vcpu);
5201 kvm_lapic_sync_to_vapic(vcpu);
5202 }
5203 }
5204
b6c7a5dc
HB		 5205 preempt_disable();
5206
5207 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 5208 if (vcpu->fpu_active)
5209 kvm_load_guest_fpu(vcpu);
2acf923e 5210 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 5211
6b7e2d09
XG		 5212 vcpu->mode = IN_GUEST_MODE;
5213
5214 /* We should set ->mode before check ->requests,
5215 * see the comment in make_all_cpus_request.
5216 */
5217 smp_mb();
b6c7a5dc 5218
d94e1dc9 5219 local_irq_disable();
32f88400 5220
6b7e2d09 5221 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 5222 || need_resched() || signal_pending(current)) {
6b7e2d09 5223 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5224 smp_wmb();
6c142801
AK		 5225 local_irq_enable();
5226 preempt_enable();
b463a6f7 5227 kvm_x86_ops->cancel_injection(vcpu);
6c142801
AK		 5228 r = 1;
5229 goto out;
5230 }
5231
f656ce01 5232 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 5233
d6185f20
NHE		 5234 if (req_immediate_exit)
5235 smp_send_reschedule(vcpu->cpu);
5236
b6c7a5dc
HB		 5237 kvm_guest_enter();
5238
42dbaa5a 5239 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 5240 set_debugreg(0, 7);
5241 set_debugreg(vcpu->arch.eff_db[0], 0);
5242 set_debugreg(vcpu->arch.eff_db[1], 1);
5243 set_debugreg(vcpu->arch.eff_db[2], 2);
5244 set_debugreg(vcpu->arch.eff_db[3], 3);
5245 }
b6c7a5dc 5246
229456fc 5247 trace_kvm_entry(vcpu->vcpu_id);
851ba692 5248 kvm_x86_ops->run(vcpu);
b6c7a5dc 5249
24f1e32c
FW		 5250 /*
5251 * If the guest has used debug registers, at least dr7
5252 * will be disabled while returning to the host.
5253 * If we don't have active breakpoints in the host, we don't
5254 * care about the messed up debug address registers. But if
5255 * we have some of them active, restore the old state.
5256 */
59d8eb53 5257 if (hw_breakpoint_active())
24f1e32c 5258 hw_breakpoint_restore();
42dbaa5a 5259
d5c1785d 5260 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu);
1d5f066e 5261
6b7e2d09 5262 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5263 smp_wmb();
b6c7a5dc
HB		 5264 local_irq_enable();
5265
5266 ++vcpu->stat.exits;
5267
5268 /*
5269 * We must have an instruction between local_irq_enable() and
5270 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5271 * the interrupt shadow. The stat.exits increment will do nicely.
5272 * But we need to prevent reordering, hence this barrier():
5273 */
5274 barrier();
5275
5276 kvm_guest_exit();
5277
5278 preempt_enable();
5279
f656ce01 5280 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 5281
b6c7a5dc
HB		 5282 /*
5283 * Profile KVM exit RIPs:
5284 */
5285 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 5286 unsigned long rip = kvm_rip_read(vcpu);
5287 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 5288 }
5289
298101da 5290
b93463aa
AK		 5291 kvm_lapic_sync_from_vapic(vcpu);
5292
851ba692 5293 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 5294out:
5295 return r;
5296}
b6c7a5dc 5297
09cec754 5298
851ba692 5299static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 5300{
5301 int r;
f656ce01 5302 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 5303
5304 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 5305 pr_debug("vcpu %d received sipi with vector # %x\n",
5306 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 5307 kvm_lapic_reset(vcpu);
5f179287 5308 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 5309 if (r)
5310 return r;
5311 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 5312 }
5313
f656ce01 5314 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 5315 vapic_enter(vcpu);
5316
5317 r = 1;
5318 while (r > 0) {
af585b92
GN		 5319 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
5320 !vcpu->arch.apf.halted)
851ba692 5321 r = vcpu_enter_guest(vcpu);
d7690175 5322 else {
f656ce01 5323 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 5324 kvm_vcpu_block(vcpu);
f656ce01 5325 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
a8eeb04a 5326 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
09cec754
GN		 5327 {
5328 switch(vcpu->arch.mp_state) {
5329 case KVM_MP_STATE_HALTED:
d7690175 5330 vcpu->arch.mp_state =
09cec754
GN		 5331 KVM_MP_STATE_RUNNABLE;
5332 case KVM_MP_STATE_RUNNABLE:
af585b92 5333 vcpu->arch.apf.halted = false;
09cec754
GN		 5334 break;
5335 case KVM_MP_STATE_SIPI_RECEIVED:
5336 default:
5337 r = -EINTR;
5338 break;
5339 }
5340 }
d7690175
MT		 5341 }
5342
09cec754
GN		 5343 if (r <= 0)
5344 break;
5345
5346 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5347 if (kvm_cpu_has_pending_timer(vcpu))
5348 kvm_inject_pending_timer_irqs(vcpu);
5349
851ba692 5350 if (dm_request_for_irq_injection(vcpu)) {
09cec754 5351 r = -EINTR;
851ba692 5352 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5353 ++vcpu->stat.request_irq_exits;
5354 }
af585b92
GN		 5355
5356 kvm_check_async_pf_completion(vcpu);
5357
09cec754
GN		 5358 if (signal_pending(current)) {
5359 r = -EINTR;
851ba692 5360 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5361 ++vcpu->stat.signal_exits;
5362 }
5363 if (need_resched()) {
f656ce01 5364 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 5365 kvm_resched(vcpu);
f656ce01 5366 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 5367 }
b6c7a5dc
HB		 5368 }
5369
f656ce01 5370 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 5371
b93463aa
AK		 5372 vapic_exit(vcpu);
5373
b6c7a5dc
HB		 5374 return r;
5375}
5376
5287f194
AK		 5377static int complete_mmio(struct kvm_vcpu *vcpu)
5378{
5379 struct kvm_run *run = vcpu->run;
5380 int r;
5381
5382 if (!(vcpu->arch.pio.count || vcpu->mmio_needed))
5383 return 1;
5384
5385 if (vcpu->mmio_needed) {
5287f194 5386 vcpu->mmio_needed = 0;
cef4dea0 5387 if (!vcpu->mmio_is_write)
0004c7c2
GN		 5388 memcpy(vcpu->mmio_data + vcpu->mmio_index,
5389 run->mmio.data, 8);
cef4dea0
AK		 5390 vcpu->mmio_index += 8;
5391 if (vcpu->mmio_index < vcpu->mmio_size) {
5392 run->exit_reason = KVM_EXIT_MMIO;
5393 run->mmio.phys_addr = vcpu->mmio_phys_addr + vcpu->mmio_index;
5394 memcpy(run->mmio.data, vcpu->mmio_data + vcpu->mmio_index, 8);
5395 run->mmio.len = min(vcpu->mmio_size - vcpu->mmio_index, 8);
5396 run->mmio.is_write = vcpu->mmio_is_write;
5397 vcpu->mmio_needed = 1;
5398 return 0;
5399 }
5400 if (vcpu->mmio_is_write)
5401 return 1;
5402 vcpu->mmio_read_completed = 1;
5287f194
AK		 5403 }
5404 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5405 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
5406 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5407 if (r != EMULATE_DONE)
5408 return 0;
5409 return 1;
5410}
5411
b6c7a5dc
HB		 5412int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
5413{
5414 int r;
5415 sigset_t sigsaved;
5416
e5c30142
AK		 5417 if (!tsk_used_math(current) && init_fpu(current))
5418 return -ENOMEM;
5419
ac9f6dc0
AK		 5420 if (vcpu->sigset_active)
5421 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
5422
a4535290 5423 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 5424 kvm_vcpu_block(vcpu);
d7690175 5425 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 5426 r = -EAGAIN;
5427 goto out;
b6c7a5dc
HB		 5428 }
5429
b6c7a5dc 5430 /* re-sync apic's tpr */
eea1cff9
AP		 5431 if (!irqchip_in_kernel(vcpu->kvm)) {
5432 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
5433 r = -EINVAL;
5434 goto out;
5435 }
5436 }
b6c7a5dc 5437
5287f194
AK		 5438 r = complete_mmio(vcpu);
5439 if (r <= 0)
5440 goto out;
5441
851ba692 5442 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 5443
5444out:
f1d86e46 5445 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 5446 if (vcpu->sigset_active)
5447 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
5448
b6c7a5dc
HB		 5449 return r;
5450}
5451
5452int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5453{
7ae441ea
GN		 5454 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
5455 /*
5456 * We are here if userspace calls get_regs() in the middle of
5457 * instruction emulation. Registers state needs to be copied
5458 * back from emulation context to vcpu. Usrapace shouldn't do
5459 * that usually, but some bad designed PV devices (vmware
5460 * backdoor interface) need this to work
5461 */
9dac77fa
AK		 5462 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5463 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
7ae441ea
GN		 5464 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5465 }
5fdbf976
MT		 5466 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5467 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5468 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5469 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5470 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
5471 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
5472 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5473 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 5474#ifdef CONFIG_X86_64
5fdbf976
MT		 5475 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
5476 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
5477 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
5478 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
5479 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
5480 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
5481 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
5482 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 5483#endif
5484
5fdbf976 5485 regs->rip = kvm_rip_read(vcpu);
91586a3b 5486 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 5487
b6c7a5dc
HB		 5488 return 0;
5489}
5490
5491int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5492{
7ae441ea
GN		 5493 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
5494 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5495
5fdbf976
MT		 5496 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
5497 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
5498 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
5499 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
5500 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
5501 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
5502 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
5503 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 5504#ifdef CONFIG_X86_64
5fdbf976
MT		 5505 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
5506 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
5507 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
5508 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
5509 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
5510 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
5511 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
5512 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 5513#endif
5514
5fdbf976 5515 kvm_rip_write(vcpu, regs->rip);
91586a3b 5516 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 5517
b4f14abd
JK		 5518 vcpu->arch.exception.pending = false;
5519
3842d135
AK		 5520 kvm_make_request(KVM_REQ_EVENT, vcpu);
5521
b6c7a5dc
HB		 5522 return 0;
5523}
5524
b6c7a5dc
HB		 5525void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5526{
5527 struct kvm_segment cs;
5528
3e6e0aab 5529 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 5530 *db = cs.db;
5531 *l = cs.l;
5532}
5533EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
5534
5535int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
5536 struct kvm_sregs *sregs)
5537{
89a27f4d 5538 struct desc_ptr dt;
b6c7a5dc 5539
3e6e0aab
GT		 5540 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5541 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5542 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5543 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5544 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5545 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5546
3e6e0aab
GT		 5547 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5548 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 5549
5550 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 5551 sregs->idt.limit = dt.size;
5552 sregs->idt.base = dt.address;
b6c7a5dc 5553 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 5554 sregs->gdt.limit = dt.size;
5555 sregs->gdt.base = dt.address;
b6c7a5dc 5556
4d4ec087 5557 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 5558 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 5559 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 5560 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 5561 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 5562 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 5563 sregs->apic_base = kvm_get_apic_base(vcpu);
5564
923c61bb 5565 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 5566
36752c9b 5567 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 5568 set_bit(vcpu->arch.interrupt.nr,
5569 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 5570
b6c7a5dc
HB		 5571 return 0;
5572}
5573
62d9f0db
MT		 5574int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
5575 struct kvm_mp_state *mp_state)
5576{
62d9f0db 5577 mp_state->mp_state = vcpu->arch.mp_state;
62d9f0db
MT		 5578 return 0;
5579}
5580
5581int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
5582 struct kvm_mp_state *mp_state)
5583{
62d9f0db 5584 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 5585 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 5586 return 0;
5587}
5588
e269fb21
JK		 5589int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason,
5590 bool has_error_code, u32 error_code)
b6c7a5dc 5591{
9d74191a 5592 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 5593 int ret;
e01c2426 5594
8ec4722d 5595 init_emulate_ctxt(vcpu);
c697518a 5596
9d74191a
TY		 5597 ret = emulator_task_switch(ctxt, tss_selector, reason,
5598 has_error_code, error_code);
c697518a 5599
c697518a 5600 if (ret)
19d04437 5601 return EMULATE_FAIL;
37817f29 5602
9dac77fa 5603 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
9d74191a
TY		 5604 kvm_rip_write(vcpu, ctxt->eip);
5605 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 5606 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 5607 return EMULATE_DONE;
37817f29
IE		 5608}
5609EXPORT_SYMBOL_GPL(kvm_task_switch);
5610
b6c7a5dc
HB		 5611int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5612 struct kvm_sregs *sregs)
5613{
5614 int mmu_reset_needed = 0;
63f42e02 5615 int pending_vec, max_bits, idx;
89a27f4d 5616 struct desc_ptr dt;
b6c7a5dc 5617
89a27f4d
GN		 5618 dt.size = sregs->idt.limit;
5619 dt.address = sregs->idt.base;
b6c7a5dc 5620 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 5621 dt.size = sregs->gdt.limit;
5622 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 5623 kvm_x86_ops->set_gdt(vcpu, &dt);
5624
ad312c7c 5625 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 5626 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 5627 vcpu->arch.cr3 = sregs->cr3;
aff48baa 5628 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 5629
2d3ad1f4 5630 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 5631
f6801dff 5632 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 5633 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 5634 kvm_set_apic_base(vcpu, sregs->apic_base);
5635
4d4ec087 5636 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 5637 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 5638 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 5639
fc78f519 5640 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 5641 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 5642 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 5643 kvm_update_cpuid(vcpu);
63f42e02
XG		 5644
5645 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 5646 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 5647 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 5648 mmu_reset_needed = 1;
5649 }
63f42e02 5650 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 5651
5652 if (mmu_reset_needed)
5653 kvm_mmu_reset_context(vcpu);
5654
923c61bb
GN		 5655 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5656 pending_vec = find_first_bit(
5657 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5658 if (pending_vec < max_bits) {
66fd3f7f 5659 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 5660 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 5661 }
5662
3e6e0aab
GT		 5663 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5664 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5665 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5666 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5667 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5668 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5669
3e6e0aab
GT		 5670 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5671 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 5672
5f0269f5
ME		 5673 update_cr8_intercept(vcpu);
5674
9c3e4aab 5675 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 5676 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 5677 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 5678 !is_protmode(vcpu))
9c3e4aab
MT		 5679 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5680
3842d135
AK		 5681 kvm_make_request(KVM_REQ_EVENT, vcpu);
5682
b6c7a5dc
HB		 5683 return 0;
5684}
5685
d0bfb940
JK		 5686int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5687 struct kvm_guest_debug *dbg)
b6c7a5dc 5688{
355be0b9 5689 unsigned long rflags;
ae675ef0 5690 int i, r;
b6c7a5dc 5691
4f926bf2
JK		 5692 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5693 r = -EBUSY;
5694 if (vcpu->arch.exception.pending)
2122ff5e 5695 goto out;
4f926bf2
JK		 5696 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5697 kvm_queue_exception(vcpu, DB_VECTOR);
5698 else
5699 kvm_queue_exception(vcpu, BP_VECTOR);
5700 }
5701
91586a3b
JK		 5702 /*
5703 * Read rflags as long as potentially injected trace flags are still
5704 * filtered out.
5705 */
5706 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 5707
5708 vcpu->guest_debug = dbg->control;
5709 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5710 vcpu->guest_debug = 0;
5711
5712 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 5713 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5714 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5715 vcpu->arch.switch_db_regs =
5716 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5717 } else {
5718 for (i = 0; i < KVM_NR_DB_REGS; i++)
5719 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5720 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5721 }
5722
f92653ee
JK		 5723 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5724 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5725 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 5726
91586a3b
JK		 5727 /*
5728 * Trigger an rflags update that will inject or remove the trace
5729 * flags.
5730 */
5731 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 5732
355be0b9 5733 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 5734
4f926bf2 5735 r = 0;
d0bfb940 5736
2122ff5e 5737out:
b6c7a5dc
HB		 5738
5739 return r;
5740}
5741
8b006791
ZX		 5742/*
5743 * Translate a guest virtual address to a guest physical address.
5744 */
5745int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5746 struct kvm_translation *tr)
5747{
5748 unsigned long vaddr = tr->linear_address;
5749 gpa_t gpa;
f656ce01 5750 int idx;
8b006791 5751
f656ce01 5752 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 5753 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 5754 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 5755 tr->physical_address = gpa;
5756 tr->valid = gpa != UNMAPPED_GVA;
5757 tr->writeable = 1;
5758 tr->usermode = 0;
8b006791
ZX		 5759
5760 return 0;
5761}
5762
d0752060
HB		 5763int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5764{
98918833
SY		 5765 struct i387_fxsave_struct *fxsave =
5766 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5767
d0752060
HB		 5768 memcpy(fpu->fpr, fxsave->st_space, 128);
5769 fpu->fcw = fxsave->cwd;
5770 fpu->fsw = fxsave->swd;
5771 fpu->ftwx = fxsave->twd;
5772 fpu->last_opcode = fxsave->fop;
5773 fpu->last_ip = fxsave->rip;
5774 fpu->last_dp = fxsave->rdp;
5775 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5776
d0752060
HB		 5777 return 0;
5778}
5779
5780int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5781{
98918833
SY		 5782 struct i387_fxsave_struct *fxsave =
5783 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5784
d0752060
HB		 5785 memcpy(fxsave->st_space, fpu->fpr, 128);
5786 fxsave->cwd = fpu->fcw;
5787 fxsave->swd = fpu->fsw;
5788 fxsave->twd = fpu->ftwx;
5789 fxsave->fop = fpu->last_opcode;
5790 fxsave->rip = fpu->last_ip;
5791 fxsave->rdp = fpu->last_dp;
5792 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5793
d0752060
HB		 5794 return 0;
5795}
5796
10ab25cd 5797int fx_init(struct kvm_vcpu *vcpu)
d0752060 5798{
10ab25cd
JK		 5799 int err;
5800
5801 err = fpu_alloc(&vcpu->arch.guest_fpu);
5802 if (err)
5803 return err;
5804
98918833 5805 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 5806
2acf923e
DC		 5807 /*
5808 * Ensure guest xcr0 is valid for loading
5809 */
5810 vcpu->arch.xcr0 = XSTATE_FP;
5811
ad312c7c 5812 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 5813
5814 return 0;
d0752060
HB		 5815}
5816EXPORT_SYMBOL_GPL(fx_init);
5817
98918833
SY		 5818static void fx_free(struct kvm_vcpu *vcpu)
5819{
5820 fpu_free(&vcpu->arch.guest_fpu);
5821}
5822
d0752060
HB		 5823void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5824{
2608d7a1 5825 if (vcpu->guest_fpu_loaded)
d0752060
HB		 5826 return;
5827
2acf923e
DC		 5828 /*
5829 * Restore all possible states in the guest,
5830 * and assume host would use all available bits.
5831 * Guest xcr0 would be loaded later.
5832 */
5833 kvm_put_guest_xcr0(vcpu);
d0752060 5834 vcpu->guest_fpu_loaded = 1;
7cf30855 5835 unlazy_fpu(current);
98918833 5836 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 5837 trace_kvm_fpu(1);
d0752060 5838}
d0752060
HB		 5839
5840void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5841{
2acf923e
DC		 5842 kvm_put_guest_xcr0(vcpu);
5843
d0752060
HB		 5844 if (!vcpu->guest_fpu_loaded)
5845 return;
5846
5847 vcpu->guest_fpu_loaded = 0;
98918833 5848 fpu_save_init(&vcpu->arch.guest_fpu);
f096ed85 5849 ++vcpu->stat.fpu_reload;
a8eeb04a 5850 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 5851 trace_kvm_fpu(0);
d0752060 5852}
e9b11c17
ZX		 5853
5854void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5855{
12f9a48f 5856 kvmclock_reset(vcpu);
7f1ea208 5857
f5f48ee1 5858 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 5859 fx_free(vcpu);
e9b11c17
ZX		 5860 kvm_x86_ops->vcpu_free(vcpu);
5861}
5862
5863struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5864 unsigned int id)
5865{
6755bae8
ZA		 5866 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
5867 printk_once(KERN_WARNING
5868 "kvm: SMP vm created on host with unstable TSC; "
5869 "guest TSC will not be reliable\n");
26e5215f
AK		 5870 return kvm_x86_ops->vcpu_create(kvm, id);
5871}
e9b11c17 5872
26e5215f
AK		 5873int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5874{
5875 int r;
e9b11c17 5876
0bed3b56 5877 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 5878 vcpu_load(vcpu);
5879 r = kvm_arch_vcpu_reset(vcpu);
5880 if (r == 0)
5881 r = kvm_mmu_setup(vcpu);
5882 vcpu_put(vcpu);
e9b11c17 5883
26e5215f 5884 return r;
e9b11c17
ZX		 5885}
5886
d40ccc62 5887void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 5888{
344d9588
GN		 5889 vcpu->arch.apf.msr_val = 0;
5890
e9b11c17
ZX		 5891 vcpu_load(vcpu);
5892 kvm_mmu_unload(vcpu);
5893 vcpu_put(vcpu);
5894
98918833 5895 fx_free(vcpu);
e9b11c17
ZX		 5896 kvm_x86_ops->vcpu_free(vcpu);
5897}
5898
5899int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
5900{
7460fb4a
AK		 5901 atomic_set(&vcpu->arch.nmi_queued, 0);
5902 vcpu->arch.nmi_pending = 0;
448fa4a9
JK		 5903 vcpu->arch.nmi_injected = false;
5904
42dbaa5a
JK		 5905 vcpu->arch.switch_db_regs = 0;
5906 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
5907 vcpu->arch.dr6 = DR6_FIXED_1;
5908 vcpu->arch.dr7 = DR7_FIXED_1;
5909
3842d135 5910 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 5911 vcpu->arch.apf.msr_val = 0;
c9aaa895 5912 vcpu->arch.st.msr_val = 0;
3842d135 5913
12f9a48f
GC		 5914 kvmclock_reset(vcpu);
5915
af585b92
GN		 5916 kvm_clear_async_pf_completion_queue(vcpu);
5917 kvm_async_pf_hash_reset(vcpu);
5918 vcpu->arch.apf.halted = false;
3842d135 5919
f5132b01
GN		 5920 kvm_pmu_reset(vcpu);
5921
e9b11c17
ZX		 5922 return kvm_x86_ops->vcpu_reset(vcpu);
5923}
5924
10474ae8 5925int kvm_arch_hardware_enable(void *garbage)
e9b11c17 5926{
ca84d1a2
ZA		 5927 struct kvm *kvm;
5928 struct kvm_vcpu *vcpu;
5929 int i;
18863bdd
AK		 5930
5931 kvm_shared_msr_cpu_online();
ca84d1a2
ZA		 5932 list_for_each_entry(kvm, &vm_list, vm_list)
5933 kvm_for_each_vcpu(i, vcpu, kvm)
5934 if (vcpu->cpu == smp_processor_id())
c285545f 5935 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
10474ae8 5936 return kvm_x86_ops->hardware_enable(garbage);
e9b11c17
ZX		 5937}
5938
5939void kvm_arch_hardware_disable(void *garbage)
5940{
5941 kvm_x86_ops->hardware_disable(garbage);
3548bab5 5942 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 5943}
5944
5945int kvm_arch_hardware_setup(void)
5946{
5947 return kvm_x86_ops->hardware_setup();
5948}
5949
5950void kvm_arch_hardware_unsetup(void)
5951{
5952 kvm_x86_ops->hardware_unsetup();
5953}
5954
5955void kvm_arch_check_processor_compat(void *rtn)
5956{
5957 kvm_x86_ops->check_processor_compatibility(rtn);
5958}
5959
5960int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
5961{
5962 struct page *page;
5963 struct kvm *kvm;
5964 int r;
5965
5966 BUG_ON(vcpu->kvm == NULL);
5967 kvm = vcpu->kvm;
5968
9aabc88f 5969 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
c5af89b6 5970 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 5971 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 5972 else
a4535290 5973 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 5974
5975 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
5976 if (!page) {
5977 r = -ENOMEM;
5978 goto fail;
5979 }
ad312c7c 5980 vcpu->arch.pio_data = page_address(page);
e9b11c17 5981
1e993611 5982 kvm_init_tsc_catchup(vcpu, max_tsc_khz);
c285545f 5983
e9b11c17
ZX		 5984 r = kvm_mmu_create(vcpu);
5985 if (r < 0)
5986 goto fail_free_pio_data;
5987
5988 if (irqchip_in_kernel(kvm)) {
5989 r = kvm_create_lapic(vcpu);
5990 if (r < 0)
5991 goto fail_mmu_destroy;
5992 }
5993
890ca9ae
HY		 5994 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
5995 GFP_KERNEL);
5996 if (!vcpu->arch.mce_banks) {
5997 r = -ENOMEM;
443c39bc 5998 goto fail_free_lapic;
890ca9ae
HY		 5999 }
6000 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6001
f5f48ee1
SY		 6002 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
6003 goto fail_free_mce_banks;
6004
af585b92 6005 kvm_async_pf_hash_reset(vcpu);
f5132b01 6006 kvm_pmu_init(vcpu);
af585b92 6007
e9b11c17 6008 return 0;
f5f48ee1
SY		 6009fail_free_mce_banks:
6010 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 6011fail_free_lapic:
6012 kvm_free_lapic(vcpu);
e9b11c17
ZX		 6013fail_mmu_destroy:
6014 kvm_mmu_destroy(vcpu);
6015fail_free_pio_data:
ad312c7c 6016 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 6017fail:
6018 return r;
6019}
6020
6021void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6022{
f656ce01
MT		 6023 int idx;
6024
f5132b01 6025 kvm_pmu_destroy(vcpu);
36cb93fd 6026 kfree(vcpu->arch.mce_banks);
e9b11c17 6027 kvm_free_lapic(vcpu);
f656ce01 6028 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 6029 kvm_mmu_destroy(vcpu);
f656ce01 6030 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 6031 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 6032}
d19a9cd2 6033
d89f5eff 6034int kvm_arch_init_vm(struct kvm *kvm)
d19a9cd2 6035{
f05e70ac 6036 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 6037 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 6038
5550af4d
SY		 6039 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
6040 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
6041
038f8c11 6042 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
53f658b3 6043
d89f5eff 6044 return 0;
d19a9cd2
ZX		 6045}
6046
6047static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
6048{
6049 vcpu_load(vcpu);
6050 kvm_mmu_unload(vcpu);
6051 vcpu_put(vcpu);
6052}
6053
6054static void kvm_free_vcpus(struct kvm *kvm)
6055{
6056 unsigned int i;
988a2cae 6057 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 6058
6059 /*
6060 * Unpin any mmu pages first.
6061 */
af585b92
GN		 6062 kvm_for_each_vcpu(i, vcpu, kvm) {
6063 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 6064 kvm_unload_vcpu_mmu(vcpu);
af585b92 6065 }
988a2cae
GN		 6066 kvm_for_each_vcpu(i, vcpu, kvm)
6067 kvm_arch_vcpu_free(vcpu);
6068
6069 mutex_lock(&kvm->lock);
6070 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
6071 kvm->vcpus[i] = NULL;
d19a9cd2 6072
988a2cae
GN		 6073 atomic_set(&kvm->online_vcpus, 0);
6074 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 6075}
6076
ad8ba2cd
SY		 6077void kvm_arch_sync_events(struct kvm *kvm)
6078{
ba4cef31 6079 kvm_free_all_assigned_devices(kvm);
aea924f6 6080 kvm_free_pit(kvm);
ad8ba2cd
SY		 6081}
6082
d19a9cd2
ZX		 6083void kvm_arch_destroy_vm(struct kvm *kvm)
6084{
6eb55818 6085 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 6086 kfree(kvm->arch.vpic);
6087 kfree(kvm->arch.vioapic);
d19a9cd2 6088 kvm_free_vcpus(kvm);
3d45830c
AK		 6089 if (kvm->arch.apic_access_page)
6090 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 6091 if (kvm->arch.ept_identity_pagetable)
6092 put_page(kvm->arch.ept_identity_pagetable);
d19a9cd2 6093}
0de10343 6094
f7784b8e
MT		 6095int kvm_arch_prepare_memory_region(struct kvm *kvm,
6096 struct kvm_memory_slot *memslot,
0de10343 6097 struct kvm_memory_slot old,
f7784b8e 6098 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 6099 int user_alloc)
6100{
f7784b8e 6101 int npages = memslot->npages;
7ac77099
AK		 6102 int map_flags = MAP_PRIVATE | MAP_ANONYMOUS;
6103
6104 /* Prevent internal slot pages from being moved by fork()/COW. */
6105 if (memslot->id >= KVM_MEMORY_SLOTS)
6106 map_flags = MAP_SHARED | MAP_ANONYMOUS;
0de10343
ZX		 6107
6108 /*To keep backward compatibility with older userspace,
6109 *x86 needs to hanlde !user_alloc case.
6110 */
6111 if (!user_alloc) {
6112 if (npages && !old.rmap) {
604b38ac
AA		 6113 unsigned long userspace_addr;
6114
72dc67a6 6115 down_write(&current->mm->mmap_sem);
604b38ac
AA		 6116 userspace_addr = do_mmap(NULL, 0,
6117 npages * PAGE_SIZE,
6118 PROT_READ | PROT_WRITE,
7ac77099 6119 map_flags,
604b38ac 6120 0);
72dc67a6 6121 up_write(&current->mm->mmap_sem);
0de10343 6122
604b38ac
AA		 6123 if (IS_ERR((void *)userspace_addr))
6124 return PTR_ERR((void *)userspace_addr);
6125
604b38ac 6126 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 6127 }
6128 }
6129
f7784b8e
MT		 6130
6131 return 0;
6132}
6133
6134void kvm_arch_commit_memory_region(struct kvm *kvm,
6135 struct kvm_userspace_memory_region *mem,
6136 struct kvm_memory_slot old,
6137 int user_alloc)
6138{
6139
48c0e4e9 6140 int nr_mmu_pages = 0, npages = mem->memory_size >> PAGE_SHIFT;
f7784b8e
MT		 6141
6142 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
6143 int ret;
6144
6145 down_write(&current->mm->mmap_sem);
6146 ret = do_munmap(current->mm, old.userspace_addr,
6147 old.npages * PAGE_SIZE);
6148 up_write(&current->mm->mmap_sem);
6149 if (ret < 0)
6150 printk(KERN_WARNING
6151 "kvm_vm_ioctl_set_memory_region: "
6152 "failed to munmap memory\n");
6153 }
6154
48c0e4e9
XG		 6155 if (!kvm->arch.n_requested_mmu_pages)
6156 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
6157
7c8a83b7 6158 spin_lock(&kvm->mmu_lock);
48c0e4e9 6159 if (nr_mmu_pages)
0de10343 6160 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
0de10343 6161 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 6162 spin_unlock(&kvm->mmu_lock);
0de10343 6163}
1d737c8a 6164
34d4cb8f
MT		 6165void kvm_arch_flush_shadow(struct kvm *kvm)
6166{
6167 kvm_mmu_zap_all(kvm);
8986ecc0 6168 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 6169}
6170
1d737c8a
ZX		 6171int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
6172{
af585b92
GN		 6173 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6174 !vcpu->arch.apf.halted)
6175 || !list_empty_careful(&vcpu->async_pf.done)
a1b37100 6176 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
7460fb4a 6177 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 6178 (kvm_arch_interrupt_allowed(vcpu) &&
6179 kvm_cpu_has_interrupt(vcpu));
1d737c8a 6180}
5736199a 6181
5736199a
ZX		 6182void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
6183{
32f88400
MT		 6184 int me;
6185 int cpu = vcpu->cpu;
5736199a
ZX		 6186
6187 if (waitqueue_active(&vcpu->wq)) {
6188 wake_up_interruptible(&vcpu->wq);
6189 ++vcpu->stat.halt_wakeup;
6190 }
32f88400
MT		 6191
6192 me = get_cpu();
6193 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
6b7e2d09 6194 if (kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE)
32f88400 6195 smp_send_reschedule(cpu);
e9571ed5 6196 put_cpu();
5736199a 6197}
78646121
GN		 6198
6199int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
6200{
6201 return kvm_x86_ops->interrupt_allowed(vcpu);
6202}
229456fc 6203
f92653ee
JK		 6204bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
6205{
6206 unsigned long current_rip = kvm_rip_read(vcpu) +
6207 get_segment_base(vcpu, VCPU_SREG_CS);
6208
6209 return current_rip == linear_rip;
6210}
6211EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
6212
94fe45da
JK		 6213unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
6214{
6215 unsigned long rflags;
6216
6217 rflags = kvm_x86_ops->get_rflags(vcpu);
6218 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 6219 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 6220 return rflags;
6221}
6222EXPORT_SYMBOL_GPL(kvm_get_rflags);
6223
6224void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
6225{
6226 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 6227 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 6228 rflags |= X86_EFLAGS_TF;
94fe45da 6229 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 6230 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 6231}
6232EXPORT_SYMBOL_GPL(kvm_set_rflags);
6233
56028d08
GN		 6234void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
6235{
6236 int r;
6237
fb67e14f 6238 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
c4806acd 6239 is_error_page(work->page))
56028d08
GN		 6240 return;
6241
6242 r = kvm_mmu_reload(vcpu);
6243 if (unlikely(r))
6244 return;
6245
fb67e14f
XG		 6246 if (!vcpu->arch.mmu.direct_map &&
6247 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
6248 return;
6249
56028d08
GN		 6250 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
6251}
6252
af585b92
GN		 6253static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
6254{
6255 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
6256}
6257
6258static inline u32 kvm_async_pf_next_probe(u32 key)
6259{
6260 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
6261}
6262
6263static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6264{
6265 u32 key = kvm_async_pf_hash_fn(gfn);
6266
6267 while (vcpu->arch.apf.gfns[key] != ~0)
6268 key = kvm_async_pf_next_probe(key);
6269
6270 vcpu->arch.apf.gfns[key] = gfn;
6271}
6272
6273static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
6274{
6275 int i;
6276 u32 key = kvm_async_pf_hash_fn(gfn);
6277
6278 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 6279 (vcpu->arch.apf.gfns[key] != gfn &&
6280 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 6281 key = kvm_async_pf_next_probe(key);
6282
6283 return key;
6284}
6285
6286bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6287{
6288 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
6289}
6290
6291static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6292{
6293 u32 i, j, k;
6294
6295 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
6296 while (true) {
6297 vcpu->arch.apf.gfns[i] = ~0;
6298 do {
6299 j = kvm_async_pf_next_probe(j);
6300 if (vcpu->arch.apf.gfns[j] == ~0)
6301 return;
6302 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
6303 /*
6304 * k lies cyclically in ]i,j]
6305 * | i.k.j |
6306 * |....j i.k.| or |.k..j i...|
6307 */
6308 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
6309 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
6310 i = j;
6311 }
6312}
6313
7c90705b
GN		 6314static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
6315{
6316
6317 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
6318 sizeof(val));
6319}
6320
af585b92
GN		 6321void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
6322 struct kvm_async_pf *work)
6323{
6389ee94
AK		 6324 struct x86_exception fault;
6325
7c90705b 6326 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 6327 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 6328
6329 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 6330 (vcpu->arch.apf.send_user_only &&
6331 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 6332 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
6333 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 6334 fault.vector = PF_VECTOR;
6335 fault.error_code_valid = true;
6336 fault.error_code = 0;
6337 fault.nested_page_fault = false;
6338 fault.address = work->arch.token;
6339 kvm_inject_page_fault(vcpu, &fault);
7c90705b 6340 }
af585b92
GN		 6341}
6342
6343void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
6344 struct kvm_async_pf *work)
6345{
6389ee94
AK		 6346 struct x86_exception fault;
6347
7c90705b
GN		 6348 trace_kvm_async_pf_ready(work->arch.token, work->gva);
6349 if (is_error_page(work->page))
6350 work->arch.token = ~0; /* broadcast wakeup */
6351 else
6352 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
6353
6354 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
6355 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 6356 fault.vector = PF_VECTOR;
6357 fault.error_code_valid = true;
6358 fault.error_code = 0;
6359 fault.nested_page_fault = false;
6360 fault.address = work->arch.token;
6361 kvm_inject_page_fault(vcpu, &fault);
7c90705b 6362 }
e6d53e3b 6363 vcpu->arch.apf.halted = false;
7c90705b
GN		 6364}
6365
6366bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
6367{
6368 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
6369 return true;
6370 else
6371 return !kvm_event_needs_reinjection(vcpu) &&
6372 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 6373}
6374
229456fc
MT		 6375EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
6376EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
6377EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
6378EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
6379EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 6380EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 6381EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 6382EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 6383EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 6384EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 6385EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 6386EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
kernel source for telekom puls (alcatel/mediatek)