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KVM: SVM: Implement infrastructure for TSC_RATE_MSR
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
313a3dc7 29
18068523 30#include <linux/clocksource.h>
4d5c5d0f 31#include <linux/interrupt.h>
313a3dc7
CO		 32#include <linux/kvm.h>
33#include <linux/fs.h>
34#include <linux/vmalloc.h>
5fb76f9b 35#include <linux/module.h>
0de10343 36#include <linux/mman.h>
2bacc55c 37#include <linux/highmem.h>
19de40a8 38#include <linux/iommu.h>
62c476c7 39#include <linux/intel-iommu.h>
c8076604 40#include <linux/cpufreq.h>
18863bdd 41#include <linux/user-return-notifier.h>
a983fb23 42#include <linux/srcu.h>
5a0e3ad6 43#include <linux/slab.h>
ff9d07a0 44#include <linux/perf_event.h>
7bee342a 45#include <linux/uaccess.h>
af585b92 46#include <linux/hash.h>
aec51dc4 47#include <trace/events/kvm.h>
2ed152af 48
229456fc
MT		 49#define CREATE_TRACE_POINTS
50#include "trace.h"
043405e1 51
24f1e32c 52#include <asm/debugreg.h>
d825ed0a 53#include <asm/msr.h>
a5f61300 54#include <asm/desc.h>
0bed3b56 55#include <asm/mtrr.h>
890ca9ae 56#include <asm/mce.h>
7cf30855 57#include <asm/i387.h>
98918833 58#include <asm/xcr.h>
1d5f066e 59#include <asm/pvclock.h>
217fc9cf 60#include <asm/div64.h>
043405e1 61
313a3dc7 62#define MAX_IO_MSRS 256
890ca9ae 63#define KVM_MAX_MCE_BANKS 32
5854dbca 64#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 65
50a37eb4
JR		 66/* EFER defaults:
67 * - enable syscall per default because its emulated by KVM
68 * - enable LME and LMA per default on 64 bit KVM
69 */
70#ifdef CONFIG_X86_64
1260edbe
LJ		 71static
72u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 73#else
1260edbe 74static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 75#endif
313a3dc7 76
ba1389b7
AK		 77#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
78#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 79
cb142eb7 80static void update_cr8_intercept(struct kvm_vcpu *vcpu);
674eea0f
AK		 81static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
82 struct kvm_cpuid_entry2 __user *entries);
83
97896d04 84struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 85EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 86
ed85c068
AP		 87int ignore_msrs = 0;
88module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
89
18863bdd
AK		 90#define KVM_NR_SHARED_MSRS 16
91
92struct kvm_shared_msrs_global {
93 int nr;
2bf78fa7 94 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 95};
96
97struct kvm_shared_msrs {
98 struct user_return_notifier urn;
99 bool registered;
2bf78fa7
SY		 100 struct kvm_shared_msr_values {
101 u64 host;
102 u64 curr;
103 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 104};
105
106static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
107static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
108
417bc304 109struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 110 { "pf_fixed", VCPU_STAT(pf_fixed) },
111 { "pf_guest", VCPU_STAT(pf_guest) },
112 { "tlb_flush", VCPU_STAT(tlb_flush) },
113 { "invlpg", VCPU_STAT(invlpg) },
114 { "exits", VCPU_STAT(exits) },
115 { "io_exits", VCPU_STAT(io_exits) },
116 { "mmio_exits", VCPU_STAT(mmio_exits) },
117 { "signal_exits", VCPU_STAT(signal_exits) },
118 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 119 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 120 { "halt_exits", VCPU_STAT(halt_exits) },
121 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 122 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 123 { "request_irq", VCPU_STAT(request_irq_exits) },
124 { "irq_exits", VCPU_STAT(irq_exits) },
125 { "host_state_reload", VCPU_STAT(host_state_reload) },
126 { "efer_reload", VCPU_STAT(efer_reload) },
127 { "fpu_reload", VCPU_STAT(fpu_reload) },
128 { "insn_emulation", VCPU_STAT(insn_emulation) },
129 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 130 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 131 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 132 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
133 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
134 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
135 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
136 { "mmu_flooded", VM_STAT(mmu_flooded) },
137 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 138 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 139 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 140 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 141 { "largepages", VM_STAT(lpages) },
417bc304
HB		 142 { NULL }
143};
144
2acf923e
DC		 145u64 __read_mostly host_xcr0;
146
af585b92
GN		 147static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
148{
149 int i;
150 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
151 vcpu->arch.apf.gfns[i] = ~0;
152}
153
18863bdd
AK		 154static void kvm_on_user_return(struct user_return_notifier *urn)
155{
156 unsigned slot;
18863bdd
AK		 157 struct kvm_shared_msrs *locals
158 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 159 struct kvm_shared_msr_values *values;
18863bdd
AK		 160
161 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 162 values = &locals->values[slot];
163 if (values->host != values->curr) {
164 wrmsrl(shared_msrs_global.msrs[slot], values->host);
165 values->curr = values->host;
18863bdd
AK		 166 }
167 }
168 locals->registered = false;
169 user_return_notifier_unregister(urn);
170}
171
2bf78fa7 172static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 173{
2bf78fa7 174 struct kvm_shared_msrs *smsr;
18863bdd
AK		 175 u64 value;
176
2bf78fa7
SY		 177 smsr = &__get_cpu_var(shared_msrs);
178 /* only read, and nobody should modify it at this time,
179 * so don't need lock */
180 if (slot >= shared_msrs_global.nr) {
181 printk(KERN_ERR "kvm: invalid MSR slot!");
182 return;
183 }
184 rdmsrl_safe(msr, &value);
185 smsr->values[slot].host = value;
186 smsr->values[slot].curr = value;
187}
188
189void kvm_define_shared_msr(unsigned slot, u32 msr)
190{
18863bdd
AK		 191 if (slot >= shared_msrs_global.nr)
192 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 193 shared_msrs_global.msrs[slot] = msr;
194 /* we need ensured the shared_msr_global have been updated */
195 smp_wmb();
18863bdd
AK		 196}
197EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
198
199static void kvm_shared_msr_cpu_online(void)
200{
201 unsigned i;
18863bdd
AK		 202
203 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 204 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 205}
206
d5696725 207void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 208{
209 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
210
2bf78fa7 211 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 212 return;
2bf78fa7
SY		 213 smsr->values[slot].curr = value;
214 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 215 if (!smsr->registered) {
216 smsr->urn.on_user_return = kvm_on_user_return;
217 user_return_notifier_register(&smsr->urn);
218 smsr->registered = true;
219 }
220}
221EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
222
3548bab5
AK		 223static void drop_user_return_notifiers(void *ignore)
224{
225 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
226
227 if (smsr->registered)
228 kvm_on_user_return(&smsr->urn);
229}
230
6866b83e
CO		 231u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
232{
233 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 234 return vcpu->arch.apic_base;
6866b83e 235 else
ad312c7c 236 return vcpu->arch.apic_base;
6866b83e
CO		 237}
238EXPORT_SYMBOL_GPL(kvm_get_apic_base);
239
240void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
241{
242 /* TODO: reserve bits check */
243 if (irqchip_in_kernel(vcpu->kvm))
244 kvm_lapic_set_base(vcpu, data);
245 else
ad312c7c 246 vcpu->arch.apic_base = data;
6866b83e
CO		 247}
248EXPORT_SYMBOL_GPL(kvm_set_apic_base);
249
3fd28fce
ED		 250#define EXCPT_BENIGN 0
251#define EXCPT_CONTRIBUTORY 1
252#define EXCPT_PF 2
253
254static int exception_class(int vector)
255{
256 switch (vector) {
257 case PF_VECTOR:
258 return EXCPT_PF;
259 case DE_VECTOR:
260 case TS_VECTOR:
261 case NP_VECTOR:
262 case SS_VECTOR:
263 case GP_VECTOR:
264 return EXCPT_CONTRIBUTORY;
265 default:
266 break;
267 }
268 return EXCPT_BENIGN;
269}
270
271static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 272 unsigned nr, bool has_error, u32 error_code,
273 bool reinject)
3fd28fce
ED		 274{
275 u32 prev_nr;
276 int class1, class2;
277
3842d135
AK		 278 kvm_make_request(KVM_REQ_EVENT, vcpu);
279
3fd28fce
ED		 280 if (!vcpu->arch.exception.pending) {
281 queue:
282 vcpu->arch.exception.pending = true;
283 vcpu->arch.exception.has_error_code = has_error;
284 vcpu->arch.exception.nr = nr;
285 vcpu->arch.exception.error_code = error_code;
3f0fd292 286 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 287 return;
288 }
289
290 /* to check exception */
291 prev_nr = vcpu->arch.exception.nr;
292 if (prev_nr == DF_VECTOR) {
293 /* triple fault -> shutdown */
a8eeb04a 294 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 295 return;
296 }
297 class1 = exception_class(prev_nr);
298 class2 = exception_class(nr);
299 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
300 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
301 /* generate double fault per SDM Table 5-5 */
302 vcpu->arch.exception.pending = true;
303 vcpu->arch.exception.has_error_code = true;
304 vcpu->arch.exception.nr = DF_VECTOR;
305 vcpu->arch.exception.error_code = 0;
306 } else
307 /* replace previous exception with a new one in a hope
308 that instruction re-execution will regenerate lost
309 exception */
310 goto queue;
311}
312
298101da
AK		 313void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
314{
ce7ddec4 315 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 316}
317EXPORT_SYMBOL_GPL(kvm_queue_exception);
318
ce7ddec4
JR		 319void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
320{
321 kvm_multiple_exception(vcpu, nr, false, 0, true);
322}
323EXPORT_SYMBOL_GPL(kvm_requeue_exception);
324
db8fcefa 325void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 326{
db8fcefa
AP		 327 if (err)
328 kvm_inject_gp(vcpu, 0);
329 else
330 kvm_x86_ops->skip_emulated_instruction(vcpu);
331}
332EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 333
6389ee94 334void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 335{
336 ++vcpu->stat.pf_guest;
6389ee94
AK		 337 vcpu->arch.cr2 = fault->address;
338 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee
AK		 339}
340
6389ee94 341void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 342{
6389ee94
AK		 343 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
344 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 345 else
6389ee94 346 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
d4f8cf66
JR		 347}
348
3419ffc8
SY		 349void kvm_inject_nmi(struct kvm_vcpu *vcpu)
350{
3842d135 351 kvm_make_request(KVM_REQ_EVENT, vcpu);
c761e586 352 vcpu->arch.nmi_pending = 1;
3419ffc8
SY		 353}
354EXPORT_SYMBOL_GPL(kvm_inject_nmi);
355
298101da
AK		 356void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
357{
ce7ddec4 358 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 359}
360EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
361
ce7ddec4
JR		 362void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
363{
364 kvm_multiple_exception(vcpu, nr, true, error_code, true);
365}
366EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
367
0a79b009
AK		 368/*
369 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
370 * a #GP and return false.
371 */
372bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 373{
0a79b009
AK		 374 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
375 return true;
376 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
377 return false;
298101da 378}
0a79b009 379EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 380
ec92fe44
JR		 381/*
382 * This function will be used to read from the physical memory of the currently
383 * running guest. The difference to kvm_read_guest_page is that this function
384 * can read from guest physical or from the guest's guest physical memory.
385 */
386int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
387 gfn_t ngfn, void *data, int offset, int len,
388 u32 access)
389{
390 gfn_t real_gfn;
391 gpa_t ngpa;
392
393 ngpa = gfn_to_gpa(ngfn);
394 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
395 if (real_gfn == UNMAPPED_GVA)
396 return -EFAULT;
397
398 real_gfn = gpa_to_gfn(real_gfn);
399
400 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
401}
402EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
403
3d06b8bf
JR		 404int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
405 void *data, int offset, int len, u32 access)
406{
407 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
408 data, offset, len, access);
409}
410
a03490ed
CO		 411/*
412 * Load the pae pdptrs. Return true is they are all valid.
413 */
ff03a073 414int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 415{
416 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
417 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
418 int i;
419 int ret;
ff03a073 420 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 421
ff03a073
JR		 422 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
423 offset * sizeof(u64), sizeof(pdpte),
424 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 425 if (ret < 0) {
426 ret = 0;
427 goto out;
428 }
429 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 430 if (is_present_gpte(pdpte[i]) &&
20c466b5 431 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 432 ret = 0;
433 goto out;
434 }
435 }
436 ret = 1;
437
ff03a073 438 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 439 __set_bit(VCPU_EXREG_PDPTR,
440 (unsigned long *)&vcpu->arch.regs_avail);
441 __set_bit(VCPU_EXREG_PDPTR,
442 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 443out:
a03490ed
CO		 444
445 return ret;
446}
cc4b6871 447EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 448
d835dfec
AK		 449static bool pdptrs_changed(struct kvm_vcpu *vcpu)
450{
ff03a073 451 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 452 bool changed = true;
3d06b8bf
JR		 453 int offset;
454 gfn_t gfn;
d835dfec
AK		 455 int r;
456
457 if (is_long_mode(vcpu) || !is_pae(vcpu))
458 return false;
459
6de4f3ad
AK		 460 if (!test_bit(VCPU_EXREG_PDPTR,
461 (unsigned long *)&vcpu->arch.regs_avail))
462 return true;
463
9f8fe504
AK		 464 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
465 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 466 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
467 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 468 if (r < 0)
469 goto out;
ff03a073 470 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 471out:
d835dfec
AK		 472
473 return changed;
474}
475
49a9b07e 476int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 477{
aad82703
SY		 478 unsigned long old_cr0 = kvm_read_cr0(vcpu);
479 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
480 X86_CR0_CD | X86_CR0_NW;
481
f9a48e6a
AK		 482 cr0 |= X86_CR0_ET;
483
ab344828 484#ifdef CONFIG_X86_64
0f12244f
GN		 485 if (cr0 & 0xffffffff00000000UL)
486 return 1;
ab344828
GN		 487#endif
488
489 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 490
0f12244f
GN		 491 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
492 return 1;
a03490ed 493
0f12244f
GN		 494 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
495 return 1;
a03490ed
CO		 496
497 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
498#ifdef CONFIG_X86_64
f6801dff 499 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 500 int cs_db, cs_l;
501
0f12244f
GN		 502 if (!is_pae(vcpu))
503 return 1;
a03490ed 504 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 505 if (cs_l)
506 return 1;
a03490ed
CO		 507 } else
508#endif
ff03a073 509 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 510 kvm_read_cr3(vcpu)))
0f12244f 511 return 1;
a03490ed
CO		 512 }
513
514 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 515
d170c419 516 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 517 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 518 kvm_async_pf_hash_reset(vcpu);
519 }
e5f3f027 520
aad82703
SY		 521 if ((cr0 ^ old_cr0) & update_bits)
522 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 523 return 0;
524}
2d3ad1f4 525EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 526
2d3ad1f4 527void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 528{
49a9b07e 529 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 530}
2d3ad1f4 531EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 532
2acf923e
DC		 533int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
534{
535 u64 xcr0;
536
537 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
538 if (index != XCR_XFEATURE_ENABLED_MASK)
539 return 1;
540 xcr0 = xcr;
541 if (kvm_x86_ops->get_cpl(vcpu) != 0)
542 return 1;
543 if (!(xcr0 & XSTATE_FP))
544 return 1;
545 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
546 return 1;
547 if (xcr0 & ~host_xcr0)
548 return 1;
549 vcpu->arch.xcr0 = xcr0;
550 vcpu->guest_xcr0_loaded = 0;
551 return 0;
552}
553
554int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
555{
556 if (__kvm_set_xcr(vcpu, index, xcr)) {
557 kvm_inject_gp(vcpu, 0);
558 return 1;
559 }
560 return 0;
561}
562EXPORT_SYMBOL_GPL(kvm_set_xcr);
563
564static bool guest_cpuid_has_xsave(struct kvm_vcpu *vcpu)
565{
566 struct kvm_cpuid_entry2 *best;
567
568 best = kvm_find_cpuid_entry(vcpu, 1, 0);
569 return best && (best->ecx & bit(X86_FEATURE_XSAVE));
570}
571
572static void update_cpuid(struct kvm_vcpu *vcpu)
573{
574 struct kvm_cpuid_entry2 *best;
575
576 best = kvm_find_cpuid_entry(vcpu, 1, 0);
577 if (!best)
578 return;
579
580 /* Update OSXSAVE bit */
581 if (cpu_has_xsave && best->function == 0x1) {
582 best->ecx &= ~(bit(X86_FEATURE_OSXSAVE));
583 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE))
584 best->ecx |= bit(X86_FEATURE_OSXSAVE);
585 }
586}
587
a83b29c6 588int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 589{
fc78f519 590 unsigned long old_cr4 = kvm_read_cr4(vcpu);
a2edf57f
AK		 591 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
592
0f12244f
GN		 593 if (cr4 & CR4_RESERVED_BITS)
594 return 1;
a03490ed 595
2acf923e
DC		 596 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
597 return 1;
598
a03490ed 599 if (is_long_mode(vcpu)) {
0f12244f
GN		 600 if (!(cr4 & X86_CR4_PAE))
601 return 1;
a2edf57f
AK		 602 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
603 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 604 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
605 kvm_read_cr3(vcpu)))
0f12244f
GN		 606 return 1;
607
608 if (cr4 & X86_CR4_VMXE)
609 return 1;
a03490ed 610
a03490ed 611 kvm_x86_ops->set_cr4(vcpu, cr4);
62ad0755 612
aad82703
SY		 613 if ((cr4 ^ old_cr4) & pdptr_bits)
614 kvm_mmu_reset_context(vcpu);
0f12244f 615
2acf923e
DC		 616 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
617 update_cpuid(vcpu);
618
0f12244f
GN		 619 return 0;
620}
2d3ad1f4 621EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 622
2390218b 623int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 624{
9f8fe504 625 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 626 kvm_mmu_sync_roots(vcpu);
d835dfec 627 kvm_mmu_flush_tlb(vcpu);
0f12244f 628 return 0;
d835dfec
AK		 629 }
630
a03490ed 631 if (is_long_mode(vcpu)) {
0f12244f
GN		 632 if (cr3 & CR3_L_MODE_RESERVED_BITS)
633 return 1;
a03490ed
CO		 634 } else {
635 if (is_pae(vcpu)) {
0f12244f
GN		 636 if (cr3 & CR3_PAE_RESERVED_BITS)
637 return 1;
ff03a073
JR		 638 if (is_paging(vcpu) &&
639 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
0f12244f 640 return 1;
a03490ed
CO		 641 }
642 /*
643 * We don't check reserved bits in nonpae mode, because
644 * this isn't enforced, and VMware depends on this.
645 */
646 }
647
a03490ed
CO		 648 /*
649 * Does the new cr3 value map to physical memory? (Note, we
650 * catch an invalid cr3 even in real-mode, because it would
651 * cause trouble later on when we turn on paging anyway.)
652 *
653 * A real CPU would silently accept an invalid cr3 and would
654 * attempt to use it - with largely undefined (and often hard
655 * to debug) behavior on the guest side.
656 */
657 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
0f12244f
GN		 658 return 1;
659 vcpu->arch.cr3 = cr3;
aff48baa 660 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
0f12244f
GN		 661 vcpu->arch.mmu.new_cr3(vcpu);
662 return 0;
663}
2d3ad1f4 664EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 665
eea1cff9 666int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 667{
0f12244f
GN		 668 if (cr8 & CR8_RESERVED_BITS)
669 return 1;
a03490ed
CO		 670 if (irqchip_in_kernel(vcpu->kvm))
671 kvm_lapic_set_tpr(vcpu, cr8);
672 else
ad312c7c 673 vcpu->arch.cr8 = cr8;
0f12244f
GN		 674 return 0;
675}
2d3ad1f4 676EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 677
2d3ad1f4 678unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 679{
680 if (irqchip_in_kernel(vcpu->kvm))
681 return kvm_lapic_get_cr8(vcpu);
682 else
ad312c7c 683 return vcpu->arch.cr8;
a03490ed 684}
2d3ad1f4 685EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 686
338dbc97 687static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 688{
689 switch (dr) {
690 case 0 ... 3:
691 vcpu->arch.db[dr] = val;
692 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
693 vcpu->arch.eff_db[dr] = val;
694 break;
695 case 4:
338dbc97
GN		 696 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
697 return 1; /* #UD */
020df079
GN		 698 /* fall through */
699 case 6:
338dbc97
GN		 700 if (val & 0xffffffff00000000ULL)
701 return -1; /* #GP */
020df079
GN		 702 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
703 break;
704 case 5:
338dbc97
GN		 705 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
706 return 1; /* #UD */
020df079
GN		 707 /* fall through */
708 default: /* 7 */
338dbc97
GN		 709 if (val & 0xffffffff00000000ULL)
710 return -1; /* #GP */
020df079
GN		 711 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
712 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
713 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
714 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
715 }
716 break;
717 }
718
719 return 0;
720}
338dbc97
GN		 721
722int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
723{
724 int res;
725
726 res = __kvm_set_dr(vcpu, dr, val);
727 if (res > 0)
728 kvm_queue_exception(vcpu, UD_VECTOR);
729 else if (res < 0)
730 kvm_inject_gp(vcpu, 0);
731
732 return res;
733}
020df079
GN		 734EXPORT_SYMBOL_GPL(kvm_set_dr);
735
338dbc97 736static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 737{
738 switch (dr) {
739 case 0 ... 3:
740 *val = vcpu->arch.db[dr];
741 break;
742 case 4:
338dbc97 743 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 744 return 1;
020df079
GN		 745 /* fall through */
746 case 6:
747 *val = vcpu->arch.dr6;
748 break;
749 case 5:
338dbc97 750 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 751 return 1;
020df079
GN		 752 /* fall through */
753 default: /* 7 */
754 *val = vcpu->arch.dr7;
755 break;
756 }
757
758 return 0;
759}
338dbc97
GN		 760
761int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
762{
763 if (_kvm_get_dr(vcpu, dr, val)) {
764 kvm_queue_exception(vcpu, UD_VECTOR);
765 return 1;
766 }
767 return 0;
768}
020df079
GN		 769EXPORT_SYMBOL_GPL(kvm_get_dr);
770
043405e1
CO		 771/*
772 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
773 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
774 *
775 * This list is modified at module load time to reflect the
e3267cbb
GC		 776 * capabilities of the host cpu. This capabilities test skips MSRs that are
777 * kvm-specific. Those are put in the beginning of the list.
043405e1 778 */
e3267cbb 779
344d9588 780#define KVM_SAVE_MSRS_BEGIN 8
043405e1 781static u32 msrs_to_save[] = {
e3267cbb 782 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 783 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 784 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
344d9588 785 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN,
043405e1 786 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 787 MSR_STAR,
043405e1
CO		 788#ifdef CONFIG_X86_64
789 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
790#endif
e90aa41e 791 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 792};
793
794static unsigned num_msrs_to_save;
795
796static u32 emulated_msrs[] = {
797 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 798 MSR_IA32_MCG_STATUS,
799 MSR_IA32_MCG_CTL,
043405e1
CO		 800};
801
b69e8cae 802static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 803{
aad82703
SY		 804 u64 old_efer = vcpu->arch.efer;
805
b69e8cae
RJ		 806 if (efer & efer_reserved_bits)
807 return 1;
15c4a640
CO		 808
809 if (is_paging(vcpu)
b69e8cae
RJ		 810 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
811 return 1;
15c4a640 812
1b2fd70c
AG		 813 if (efer & EFER_FFXSR) {
814 struct kvm_cpuid_entry2 *feat;
815
816 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 817 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
818 return 1;
1b2fd70c
AG		 819 }
820
d8017474
AG		 821 if (efer & EFER_SVME) {
822 struct kvm_cpuid_entry2 *feat;
823
824 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 825 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
826 return 1;
d8017474
AG		 827 }
828
15c4a640 829 efer &= ~EFER_LMA;
f6801dff 830 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 831
a3d204e2
SY		 832 kvm_x86_ops->set_efer(vcpu, efer);
833
9645bb56 834 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
b69e8cae 835
aad82703
SY		 836 /* Update reserved bits */
837 if ((efer ^ old_efer) & EFER_NX)
838 kvm_mmu_reset_context(vcpu);
839
b69e8cae 840 return 0;
15c4a640
CO		 841}
842
f2b4b7dd
JR		 843void kvm_enable_efer_bits(u64 mask)
844{
845 efer_reserved_bits &= ~mask;
846}
847EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
848
849
15c4a640
CO		 850/*
851 * Writes msr value into into the appropriate "register".
852 * Returns 0 on success, non-0 otherwise.
853 * Assumes vcpu_load() was already called.
854 */
855int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
856{
857 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
858}
859
313a3dc7
CO		 860/*
861 * Adapt set_msr() to msr_io()'s calling convention
862 */
863static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
864{
865 return kvm_set_msr(vcpu, index, *data);
866}
867
18068523
GOC		 868static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
869{
9ed3c444
AK		 870 int version;
871 int r;
50d0a0f9 872 struct pvclock_wall_clock wc;
923de3cf 873 struct timespec boot;
18068523
GOC		 874
875 if (!wall_clock)
876 return;
877
9ed3c444
AK		 878 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
879 if (r)
880 return;
881
882 if (version & 1)
883 ++version; /* first time write, random junk */
884
885 ++version;
18068523 886
18068523
GOC		 887 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
888
50d0a0f9
GH		 889 /*
890 * The guest calculates current wall clock time by adding
34c238a1 891 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 892 * wall clock specified here. guest system time equals host
893 * system time for us, thus we must fill in host boot time here.
894 */
923de3cf 895 getboottime(&boot);
50d0a0f9
GH		 896
897 wc.sec = boot.tv_sec;
898 wc.nsec = boot.tv_nsec;
899 wc.version = version;
18068523
GOC		 900
901 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
902
903 version++;
904 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 905}
906
50d0a0f9
GH		 907static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
908{
909 uint32_t quotient, remainder;
910
911 /* Don't try to replace with do_div(), this one calculates
912 * "(dividend << 32) / divisor" */
913 __asm__ ( "divl %4"
914 : "=a" (quotient), "=d" (remainder)
915 : "0" (0), "1" (dividend), "r" (divisor) );
916 return quotient;
917}
918
5f4e3f88
ZA		 919static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
920 s8 *pshift, u32 *pmultiplier)
50d0a0f9 921{
5f4e3f88 922 uint64_t scaled64;
50d0a0f9
GH		 923 int32_t shift = 0;
924 uint64_t tps64;
925 uint32_t tps32;
926
5f4e3f88
ZA		 927 tps64 = base_khz * 1000LL;
928 scaled64 = scaled_khz * 1000LL;
50933623 929 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 930 tps64 >>= 1;
931 shift--;
932 }
933
934 tps32 = (uint32_t)tps64;
50933623
JK		 935 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
936 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 937 scaled64 >>= 1;
938 else
939 tps32 <<= 1;
50d0a0f9
GH		 940 shift++;
941 }
942
5f4e3f88
ZA		 943 *pshift = shift;
944 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 945
5f4e3f88
ZA		 946 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
947 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 948}
949
759379dd
ZA		 950static inline u64 get_kernel_ns(void)
951{
952 struct timespec ts;
953
954 WARN_ON(preemptible());
955 ktime_get_ts(&ts);
956 monotonic_to_bootbased(&ts);
957 return timespec_to_ns(&ts);
50d0a0f9
GH		 958}
959
c8076604 960static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 961unsigned long max_tsc_khz;
c8076604 962
8cfdc000
ZA		 963static inline int kvm_tsc_changes_freq(void)
964{
965 int cpu = get_cpu();
966 int ret = !boot_cpu_has(X86_FEATURE_CONSTANT_TSC) &&
967 cpufreq_quick_get(cpu) != 0;
968 put_cpu();
969 return ret;
970}
971
759379dd
ZA		 972static inline u64 nsec_to_cycles(u64 nsec)
973{
217fc9cf
AK		 974 u64 ret;
975
759379dd
ZA		 976 WARN_ON(preemptible());
977 if (kvm_tsc_changes_freq())
978 printk_once(KERN_WARNING
979 "kvm: unreliable cycle conversion on adjustable rate TSC\n");
0a3aee0d 980 ret = nsec * __this_cpu_read(cpu_tsc_khz);
217fc9cf
AK		 981 do_div(ret, USEC_PER_SEC);
982 return ret;
759379dd
ZA		 983}
984
c285545f
ZA		 985static void kvm_arch_set_tsc_khz(struct kvm *kvm, u32 this_tsc_khz)
986{
987 /* Compute a scale to convert nanoseconds in TSC cycles */
988 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
989 &kvm->arch.virtual_tsc_shift,
990 &kvm->arch.virtual_tsc_mult);
991 kvm->arch.virtual_tsc_khz = this_tsc_khz;
992}
993
994static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
995{
996 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.last_tsc_nsec,
997 vcpu->kvm->arch.virtual_tsc_mult,
998 vcpu->kvm->arch.virtual_tsc_shift);
999 tsc += vcpu->arch.last_tsc_write;
1000 return tsc;
1001}
1002
99e3e30a
ZA		 1003void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
1004{
1005 struct kvm *kvm = vcpu->kvm;
f38e098f 1006 u64 offset, ns, elapsed;
99e3e30a 1007 unsigned long flags;
46543ba4 1008 s64 sdiff;
99e3e30a 1009
038f8c11 1010 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
99e3e30a 1011 offset = data - native_read_tsc();
759379dd 1012 ns = get_kernel_ns();
f38e098f 1013 elapsed = ns - kvm->arch.last_tsc_nsec;
46543ba4
ZA		 1014 sdiff = data - kvm->arch.last_tsc_write;
1015 if (sdiff < 0)
1016 sdiff = -sdiff;
f38e098f
ZA		 1017
1018 /*
46543ba4 1019 * Special case: close write to TSC within 5 seconds of
f38e098f 1020 * another CPU is interpreted as an attempt to synchronize
0d2eb44f 1021 * The 5 seconds is to accommodate host load / swapping as
46543ba4 1022 * well as any reset of TSC during the boot process.
f38e098f
ZA		 1023 *
1024 * In that case, for a reliable TSC, we can match TSC offsets,
46543ba4 1025 * or make a best guest using elapsed value.
f38e098f 1026 */
46543ba4
ZA		 1027 if (sdiff < nsec_to_cycles(5ULL * NSEC_PER_SEC) &&
1028 elapsed < 5ULL * NSEC_PER_SEC) {
f38e098f
ZA		 1029 if (!check_tsc_unstable()) {
1030 offset = kvm->arch.last_tsc_offset;
1031 pr_debug("kvm: matched tsc offset for %llu\n", data);
1032 } else {
759379dd
ZA		 1033 u64 delta = nsec_to_cycles(elapsed);
1034 offset += delta;
1035 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f
ZA		 1036 }
1037 ns = kvm->arch.last_tsc_nsec;
1038 }
1039 kvm->arch.last_tsc_nsec = ns;
1040 kvm->arch.last_tsc_write = data;
1041 kvm->arch.last_tsc_offset = offset;
99e3e30a 1042 kvm_x86_ops->write_tsc_offset(vcpu, offset);
038f8c11 1043 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
99e3e30a
ZA		 1044
1045 /* Reset of TSC must disable overshoot protection below */
1046 vcpu->arch.hv_clock.tsc_timestamp = 0;
c285545f
ZA		 1047 vcpu->arch.last_tsc_write = data;
1048 vcpu->arch.last_tsc_nsec = ns;
99e3e30a
ZA		 1049}
1050EXPORT_SYMBOL_GPL(kvm_write_tsc);
1051
34c238a1 1052static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1053{
18068523
GOC		 1054 unsigned long flags;
1055 struct kvm_vcpu_arch *vcpu = &v->arch;
1056 void *shared_kaddr;
463656c0 1057 unsigned long this_tsc_khz;
1d5f066e
ZA		 1058 s64 kernel_ns, max_kernel_ns;
1059 u64 tsc_timestamp;
18068523 1060
18068523
GOC		 1061 /* Keep irq disabled to prevent changes to the clock */
1062 local_irq_save(flags);
1d5f066e 1063 kvm_get_msr(v, MSR_IA32_TSC, &tsc_timestamp);
759379dd 1064 kernel_ns = get_kernel_ns();
0a3aee0d 1065 this_tsc_khz = __this_cpu_read(cpu_tsc_khz);
18068523 1066
8cfdc000 1067 if (unlikely(this_tsc_khz == 0)) {
c285545f 1068 local_irq_restore(flags);
34c238a1 1069 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
8cfdc000
ZA		 1070 return 1;
1071 }
18068523 1072
c285545f
ZA		 1073 /*
1074 * We may have to catch up the TSC to match elapsed wall clock
1075 * time for two reasons, even if kvmclock is used.
1076 * 1) CPU could have been running below the maximum TSC rate
1077 * 2) Broken TSC compensation resets the base at each VCPU
1078 * entry to avoid unknown leaps of TSC even when running
1079 * again on the same CPU. This may cause apparent elapsed
1080 * time to disappear, and the guest to stand still or run
1081 * very slowly.
1082 */
1083 if (vcpu->tsc_catchup) {
1084 u64 tsc = compute_guest_tsc(v, kernel_ns);
1085 if (tsc > tsc_timestamp) {
1086 kvm_x86_ops->adjust_tsc_offset(v, tsc - tsc_timestamp);
1087 tsc_timestamp = tsc;
1088 }
50d0a0f9
GH		 1089 }
1090
18068523
GOC		 1091 local_irq_restore(flags);
1092
c285545f
ZA		 1093 if (!vcpu->time_page)
1094 return 0;
18068523 1095
1d5f066e
ZA		 1096 /*
1097 * Time as measured by the TSC may go backwards when resetting the base
1098 * tsc_timestamp. The reason for this is that the TSC resolution is
1099 * higher than the resolution of the other clock scales. Thus, many
1100 * possible measurments of the TSC correspond to one measurement of any
1101 * other clock, and so a spread of values is possible. This is not a
1102 * problem for the computation of the nanosecond clock; with TSC rates
1103 * around 1GHZ, there can only be a few cycles which correspond to one
1104 * nanosecond value, and any path through this code will inevitably
1105 * take longer than that. However, with the kernel_ns value itself,
1106 * the precision may be much lower, down to HZ granularity. If the
1107 * first sampling of TSC against kernel_ns ends in the low part of the
1108 * range, and the second in the high end of the range, we can get:
1109 *
1110 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1111 *
1112 * As the sampling errors potentially range in the thousands of cycles,
1113 * it is possible such a time value has already been observed by the
1114 * guest. To protect against this, we must compute the system time as
1115 * observed by the guest and ensure the new system time is greater.
1116 */
1117 max_kernel_ns = 0;
1118 if (vcpu->hv_clock.tsc_timestamp && vcpu->last_guest_tsc) {
1119 max_kernel_ns = vcpu->last_guest_tsc -
1120 vcpu->hv_clock.tsc_timestamp;
1121 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1122 vcpu->hv_clock.tsc_to_system_mul,
1123 vcpu->hv_clock.tsc_shift);
1124 max_kernel_ns += vcpu->last_kernel_ns;
1125 }
afbcf7ab 1126
e48672fa 1127 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1128 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1129 &vcpu->hv_clock.tsc_shift,
1130 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1131 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1132 }
1133
1d5f066e
ZA		 1134 if (max_kernel_ns > kernel_ns)
1135 kernel_ns = max_kernel_ns;
1136
8cfdc000 1137 /* With all the info we got, fill in the values */
1d5f066e 1138 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1139 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1d5f066e 1140 vcpu->last_kernel_ns = kernel_ns;
28e4639a 1141 vcpu->last_guest_tsc = tsc_timestamp;
371bcf64
GC		 1142 vcpu->hv_clock.flags = 0;
1143
18068523
GOC		 1144 /*
1145 * The interface expects us to write an even number signaling that the
1146 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1147 * state, we just increase by 2 at the end.
18068523 1148 */
50d0a0f9 1149 vcpu->hv_clock.version += 2;
18068523
GOC		 1150
1151 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
1152
1153 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 1154 sizeof(vcpu->hv_clock));
18068523
GOC		 1155
1156 kunmap_atomic(shared_kaddr, KM_USER0);
1157
1158 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
8cfdc000 1159 return 0;
c8076604
GH		 1160}
1161
9ba075a6
AK		 1162static bool msr_mtrr_valid(unsigned msr)
1163{
1164 switch (msr) {
1165 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1166 case MSR_MTRRfix64K_00000:
1167 case MSR_MTRRfix16K_80000:
1168 case MSR_MTRRfix16K_A0000:
1169 case MSR_MTRRfix4K_C0000:
1170 case MSR_MTRRfix4K_C8000:
1171 case MSR_MTRRfix4K_D0000:
1172 case MSR_MTRRfix4K_D8000:
1173 case MSR_MTRRfix4K_E0000:
1174 case MSR_MTRRfix4K_E8000:
1175 case MSR_MTRRfix4K_F0000:
1176 case MSR_MTRRfix4K_F8000:
1177 case MSR_MTRRdefType:
1178 case MSR_IA32_CR_PAT:
1179 return true;
1180 case 0x2f8:
1181 return true;
1182 }
1183 return false;
1184}
1185
d6289b93
MT		 1186static bool valid_pat_type(unsigned t)
1187{
1188 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1189}
1190
1191static bool valid_mtrr_type(unsigned t)
1192{
1193 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1194}
1195
1196static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1197{
1198 int i;
1199
1200 if (!msr_mtrr_valid(msr))
1201 return false;
1202
1203 if (msr == MSR_IA32_CR_PAT) {
1204 for (i = 0; i < 8; i++)
1205 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1206 return false;
1207 return true;
1208 } else if (msr == MSR_MTRRdefType) {
1209 if (data & ~0xcff)
1210 return false;
1211 return valid_mtrr_type(data & 0xff);
1212 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1213 for (i = 0; i < 8 ; i++)
1214 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1215 return false;
1216 return true;
1217 }
1218
1219 /* variable MTRRs */
1220 return valid_mtrr_type(data & 0xff);
1221}
1222
9ba075a6
AK		 1223static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1224{
0bed3b56
SY		 1225 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1226
d6289b93 1227 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1228 return 1;
1229
0bed3b56
SY		 1230 if (msr == MSR_MTRRdefType) {
1231 vcpu->arch.mtrr_state.def_type = data;
1232 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1233 } else if (msr == MSR_MTRRfix64K_00000)
1234 p[0] = data;
1235 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1236 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1237 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1238 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1239 else if (msr == MSR_IA32_CR_PAT)
1240 vcpu->arch.pat = data;
1241 else { /* Variable MTRRs */
1242 int idx, is_mtrr_mask;
1243 u64 *pt;
1244
1245 idx = (msr - 0x200) / 2;
1246 is_mtrr_mask = msr - 0x200 - 2 * idx;
1247 if (!is_mtrr_mask)
1248 pt =
1249 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1250 else
1251 pt =
1252 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1253 *pt = data;
1254 }
1255
1256 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1257 return 0;
1258}
15c4a640 1259
890ca9ae 1260static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1261{
890ca9ae
HY		 1262 u64 mcg_cap = vcpu->arch.mcg_cap;
1263 unsigned bank_num = mcg_cap & 0xff;
1264
15c4a640 1265 switch (msr) {
15c4a640 1266 case MSR_IA32_MCG_STATUS:
890ca9ae 1267 vcpu->arch.mcg_status = data;
15c4a640 1268 break;
c7ac679c 1269 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1270 if (!(mcg_cap & MCG_CTL_P))
1271 return 1;
1272 if (data != 0 && data != ~(u64)0)
1273 return -1;
1274 vcpu->arch.mcg_ctl = data;
1275 break;
1276 default:
1277 if (msr >= MSR_IA32_MC0_CTL &&
1278 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1279 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1280 /* only 0 or all 1s can be written to IA32_MCi_CTL
1281 * some Linux kernels though clear bit 10 in bank 4 to
1282 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1283 * this to avoid an uncatched #GP in the guest
1284 */
890ca9ae 1285 if ((offset & 0x3) == 0 &&
114be429 1286 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1287 return -1;
1288 vcpu->arch.mce_banks[offset] = data;
1289 break;
1290 }
1291 return 1;
1292 }
1293 return 0;
1294}
1295
ffde22ac
ES		 1296static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1297{
1298 struct kvm *kvm = vcpu->kvm;
1299 int lm = is_long_mode(vcpu);
1300 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1301 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1302 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1303 : kvm->arch.xen_hvm_config.blob_size_32;
1304 u32 page_num = data & ~PAGE_MASK;
1305 u64 page_addr = data & PAGE_MASK;
1306 u8 *page;
1307 int r;
1308
1309 r = -E2BIG;
1310 if (page_num >= blob_size)
1311 goto out;
1312 r = -ENOMEM;
1313 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
1314 if (!page)
1315 goto out;
1316 r = -EFAULT;
1317 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
1318 goto out_free;
1319 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1320 goto out_free;
1321 r = 0;
1322out_free:
1323 kfree(page);
1324out:
1325 return r;
1326}
1327
55cd8e5a
GN		 1328static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1329{
1330 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1331}
1332
1333static bool kvm_hv_msr_partition_wide(u32 msr)
1334{
1335 bool r = false;
1336 switch (msr) {
1337 case HV_X64_MSR_GUEST_OS_ID:
1338 case HV_X64_MSR_HYPERCALL:
1339 r = true;
1340 break;
1341 }
1342
1343 return r;
1344}
1345
1346static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1347{
1348 struct kvm *kvm = vcpu->kvm;
1349
1350 switch (msr) {
1351 case HV_X64_MSR_GUEST_OS_ID:
1352 kvm->arch.hv_guest_os_id = data;
1353 /* setting guest os id to zero disables hypercall page */
1354 if (!kvm->arch.hv_guest_os_id)
1355 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1356 break;
1357 case HV_X64_MSR_HYPERCALL: {
1358 u64 gfn;
1359 unsigned long addr;
1360 u8 instructions[4];
1361
1362 /* if guest os id is not set hypercall should remain disabled */
1363 if (!kvm->arch.hv_guest_os_id)
1364 break;
1365 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1366 kvm->arch.hv_hypercall = data;
1367 break;
1368 }
1369 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1370 addr = gfn_to_hva(kvm, gfn);
1371 if (kvm_is_error_hva(addr))
1372 return 1;
1373 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1374 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1375 if (copy_to_user((void __user *)addr, instructions, 4))
1376 return 1;
1377 kvm->arch.hv_hypercall = data;
1378 break;
1379 }
1380 default:
1381 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1382 "data 0x%llx\n", msr, data);
1383 return 1;
1384 }
1385 return 0;
1386}
1387
1388static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1389{
10388a07
GN		 1390 switch (msr) {
1391 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1392 unsigned long addr;
55cd8e5a 1393
10388a07
GN		 1394 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1395 vcpu->arch.hv_vapic = data;
1396 break;
1397 }
1398 addr = gfn_to_hva(vcpu->kvm, data >>
1399 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1400 if (kvm_is_error_hva(addr))
1401 return 1;
1402 if (clear_user((void __user *)addr, PAGE_SIZE))
1403 return 1;
1404 vcpu->arch.hv_vapic = data;
1405 break;
1406 }
1407 case HV_X64_MSR_EOI:
1408 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1409 case HV_X64_MSR_ICR:
1410 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1411 case HV_X64_MSR_TPR:
1412 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1413 default:
1414 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1415 "data 0x%llx\n", msr, data);
1416 return 1;
1417 }
1418
1419 return 0;
55cd8e5a
GN		 1420}
1421
344d9588
GN		 1422static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1423{
1424 gpa_t gpa = data & ~0x3f;
1425
6adba527
GN		 1426 /* Bits 2:5 are resrved, Should be zero */
1427 if (data & 0x3c)
344d9588
GN		 1428 return 1;
1429
1430 vcpu->arch.apf.msr_val = data;
1431
1432 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1433 kvm_clear_async_pf_completion_queue(vcpu);
1434 kvm_async_pf_hash_reset(vcpu);
1435 return 0;
1436 }
1437
1438 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa))
1439 return 1;
1440
6adba527 1441 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1442 kvm_async_pf_wakeup_all(vcpu);
1443 return 0;
1444}
1445
12f9a48f
GC		 1446static void kvmclock_reset(struct kvm_vcpu *vcpu)
1447{
1448 if (vcpu->arch.time_page) {
1449 kvm_release_page_dirty(vcpu->arch.time_page);
1450 vcpu->arch.time_page = NULL;
1451 }
1452}
1453
15c4a640
CO		 1454int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1455{
1456 switch (msr) {
15c4a640 1457 case MSR_EFER:
b69e8cae 1458 return set_efer(vcpu, data);
8f1589d9
AP		 1459 case MSR_K7_HWCR:
1460 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1461 data &= ~(u64)0x100; /* ignore ignne emulation enable */
8f1589d9
AP		 1462 if (data != 0) {
1463 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1464 data);
1465 return 1;
1466 }
15c4a640 1467 break;
f7c6d140
AP		 1468 case MSR_FAM10H_MMIO_CONF_BASE:
1469 if (data != 0) {
1470 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1471 "0x%llx\n", data);
1472 return 1;
1473 }
15c4a640 1474 break;
c323c0e5 1475 case MSR_AMD64_NB_CFG:
c7ac679c 1476 break;
b5e2fec0
AG		 1477 case MSR_IA32_DEBUGCTLMSR:
1478 if (!data) {
1479 /* We support the non-activated case already */
1480 break;
1481 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1482 /* Values other than LBR and BTF are vendor-specific,
1483 thus reserved and should throw a #GP */
1484 return 1;
1485 }
1486 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1487 __func__, data);
1488 break;
15c4a640
CO		 1489 case MSR_IA32_UCODE_REV:
1490 case MSR_IA32_UCODE_WRITE:
61a6bd67 1491 case MSR_VM_HSAVE_PA:
6098ca93 1492 case MSR_AMD64_PATCH_LOADER:
15c4a640 1493 break;
9ba075a6
AK		 1494 case 0x200 ... 0x2ff:
1495 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1496 case MSR_IA32_APICBASE:
1497 kvm_set_apic_base(vcpu, data);
1498 break;
0105d1a5
GN		 1499 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1500 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 1501 case MSR_IA32_MISC_ENABLE:
ad312c7c 1502 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1503 break;
11c6bffa 1504 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1505 case MSR_KVM_WALL_CLOCK:
1506 vcpu->kvm->arch.wall_clock = data;
1507 kvm_write_wall_clock(vcpu->kvm, data);
1508 break;
11c6bffa 1509 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 1510 case MSR_KVM_SYSTEM_TIME: {
12f9a48f 1511 kvmclock_reset(vcpu);
18068523
GOC		 1512
1513 vcpu->arch.time = data;
c285545f 1514 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
18068523
GOC		 1515
1516 /* we verify if the enable bit is set... */
1517 if (!(data & 1))
1518 break;
1519
1520 /* ...but clean it before doing the actual write */
1521 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1522
18068523
GOC		 1523 vcpu->arch.time_page =
1524 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1525
1526 if (is_error_page(vcpu->arch.time_page)) {
1527 kvm_release_page_clean(vcpu->arch.time_page);
1528 vcpu->arch.time_page = NULL;
1529 }
18068523
GOC		 1530 break;
1531 }
344d9588
GN		 1532 case MSR_KVM_ASYNC_PF_EN:
1533 if (kvm_pv_enable_async_pf(vcpu, data))
1534 return 1;
1535 break;
890ca9ae
HY		 1536 case MSR_IA32_MCG_CTL:
1537 case MSR_IA32_MCG_STATUS:
1538 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1539 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1540
1541 /* Performance counters are not protected by a CPUID bit,
1542 * so we should check all of them in the generic path for the sake of
1543 * cross vendor migration.
1544 * Writing a zero into the event select MSRs disables them,
1545 * which we perfectly emulate ;-). Any other value should be at least
1546 * reported, some guests depend on them.
1547 */
1548 case MSR_P6_EVNTSEL0:
1549 case MSR_P6_EVNTSEL1:
1550 case MSR_K7_EVNTSEL0:
1551 case MSR_K7_EVNTSEL1:
1552 case MSR_K7_EVNTSEL2:
1553 case MSR_K7_EVNTSEL3:
1554 if (data != 0)
1555 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1556 "0x%x data 0x%llx\n", msr, data);
1557 break;
1558 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1559 * so we ignore writes to make it happy.
1560 */
1561 case MSR_P6_PERFCTR0:
1562 case MSR_P6_PERFCTR1:
1563 case MSR_K7_PERFCTR0:
1564 case MSR_K7_PERFCTR1:
1565 case MSR_K7_PERFCTR2:
1566 case MSR_K7_PERFCTR3:
1567 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1568 "0x%x data 0x%llx\n", msr, data);
1569 break;
84e0cefa
JS		 1570 case MSR_K7_CLK_CTL:
1571 /*
1572 * Ignore all writes to this no longer documented MSR.
1573 * Writes are only relevant for old K7 processors,
1574 * all pre-dating SVM, but a recommended workaround from
1575 * AMD for these chips. It is possible to speicify the
1576 * affected processor models on the command line, hence
1577 * the need to ignore the workaround.
1578 */
1579 break;
55cd8e5a
GN		 1580 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1581 if (kvm_hv_msr_partition_wide(msr)) {
1582 int r;
1583 mutex_lock(&vcpu->kvm->lock);
1584 r = set_msr_hyperv_pw(vcpu, msr, data);
1585 mutex_unlock(&vcpu->kvm->lock);
1586 return r;
1587 } else
1588 return set_msr_hyperv(vcpu, msr, data);
1589 break;
91c9c3ed 1590 case MSR_IA32_BBL_CR_CTL3:
1591 /* Drop writes to this legacy MSR -- see rdmsr
1592 * counterpart for further detail.
1593 */
1594 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
1595 break;
15c4a640 1596 default:
ffde22ac
ES		 1597 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1598 return xen_hvm_config(vcpu, data);
ed85c068
AP		 1599 if (!ignore_msrs) {
1600 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1601 msr, data);
1602 return 1;
1603 } else {
1604 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1605 msr, data);
1606 break;
1607 }
15c4a640
CO		 1608 }
1609 return 0;
1610}
1611EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1612
1613
1614/*
1615 * Reads an msr value (of 'msr_index') into 'pdata'.
1616 * Returns 0 on success, non-0 otherwise.
1617 * Assumes vcpu_load() was already called.
1618 */
1619int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1620{
1621 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1622}
1623
9ba075a6
AK		 1624static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1625{
0bed3b56
SY		 1626 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1627
9ba075a6
AK		 1628 if (!msr_mtrr_valid(msr))
1629 return 1;
1630
0bed3b56
SY		 1631 if (msr == MSR_MTRRdefType)
1632 *pdata = vcpu->arch.mtrr_state.def_type +
1633 (vcpu->arch.mtrr_state.enabled << 10);
1634 else if (msr == MSR_MTRRfix64K_00000)
1635 *pdata = p[0];
1636 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1637 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1638 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1639 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1640 else if (msr == MSR_IA32_CR_PAT)
1641 *pdata = vcpu->arch.pat;
1642 else { /* Variable MTRRs */
1643 int idx, is_mtrr_mask;
1644 u64 *pt;
1645
1646 idx = (msr - 0x200) / 2;
1647 is_mtrr_mask = msr - 0x200 - 2 * idx;
1648 if (!is_mtrr_mask)
1649 pt =
1650 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1651 else
1652 pt =
1653 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1654 *pdata = *pt;
1655 }
1656
9ba075a6
AK		 1657 return 0;
1658}
1659
890ca9ae 1660static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1661{
1662 u64 data;
890ca9ae
HY		 1663 u64 mcg_cap = vcpu->arch.mcg_cap;
1664 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1665
1666 switch (msr) {
15c4a640
CO		 1667 case MSR_IA32_P5_MC_ADDR:
1668 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1669 data = 0;
1670 break;
15c4a640 1671 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1672 data = vcpu->arch.mcg_cap;
1673 break;
c7ac679c 1674 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1675 if (!(mcg_cap & MCG_CTL_P))
1676 return 1;
1677 data = vcpu->arch.mcg_ctl;
1678 break;
1679 case MSR_IA32_MCG_STATUS:
1680 data = vcpu->arch.mcg_status;
1681 break;
1682 default:
1683 if (msr >= MSR_IA32_MC0_CTL &&
1684 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1685 u32 offset = msr - MSR_IA32_MC0_CTL;
1686 data = vcpu->arch.mce_banks[offset];
1687 break;
1688 }
1689 return 1;
1690 }
1691 *pdata = data;
1692 return 0;
1693}
1694
55cd8e5a
GN		 1695static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1696{
1697 u64 data = 0;
1698 struct kvm *kvm = vcpu->kvm;
1699
1700 switch (msr) {
1701 case HV_X64_MSR_GUEST_OS_ID:
1702 data = kvm->arch.hv_guest_os_id;
1703 break;
1704 case HV_X64_MSR_HYPERCALL:
1705 data = kvm->arch.hv_hypercall;
1706 break;
1707 default:
1708 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1709 return 1;
1710 }
1711
1712 *pdata = data;
1713 return 0;
1714}
1715
1716static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1717{
1718 u64 data = 0;
1719
1720 switch (msr) {
1721 case HV_X64_MSR_VP_INDEX: {
1722 int r;
1723 struct kvm_vcpu *v;
1724 kvm_for_each_vcpu(r, v, vcpu->kvm)
1725 if (v == vcpu)
1726 data = r;
1727 break;
1728 }
10388a07
GN		 1729 case HV_X64_MSR_EOI:
1730 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1731 case HV_X64_MSR_ICR:
1732 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1733 case HV_X64_MSR_TPR:
1734 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
55cd8e5a
GN		 1735 default:
1736 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1737 return 1;
1738 }
1739 *pdata = data;
1740 return 0;
1741}
1742
890ca9ae
HY		 1743int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1744{
1745 u64 data;
1746
1747 switch (msr) {
890ca9ae 1748 case MSR_IA32_PLATFORM_ID:
15c4a640 1749 case MSR_IA32_UCODE_REV:
15c4a640 1750 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1751 case MSR_IA32_DEBUGCTLMSR:
1752 case MSR_IA32_LASTBRANCHFROMIP:
1753 case MSR_IA32_LASTBRANCHTOIP:
1754 case MSR_IA32_LASTINTFROMIP:
1755 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1756 case MSR_K8_SYSCFG:
1757 case MSR_K7_HWCR:
61a6bd67 1758 case MSR_VM_HSAVE_PA:
1f3ee616
AS		 1759 case MSR_P6_PERFCTR0:
1760 case MSR_P6_PERFCTR1:
7fe29e0f
AS		 1761 case MSR_P6_EVNTSEL0:
1762 case MSR_P6_EVNTSEL1:
9e699624 1763 case MSR_K7_EVNTSEL0:
1f3ee616 1764 case MSR_K7_PERFCTR0:
1fdbd48c 1765 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1766 case MSR_AMD64_NB_CFG:
f7c6d140 1767 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1768 data = 0;
1769 break;
9ba075a6
AK		 1770 case MSR_MTRRcap:
1771 data = 0x500 | KVM_NR_VAR_MTRR;
1772 break;
1773 case 0x200 ... 0x2ff:
1774 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1775 case 0xcd: /* fsb frequency */
1776 data = 3;
1777 break;
7b914098
JS		 1778 /*
1779 * MSR_EBC_FREQUENCY_ID
1780 * Conservative value valid for even the basic CPU models.
1781 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
1782 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
1783 * and 266MHz for model 3, or 4. Set Core Clock
1784 * Frequency to System Bus Frequency Ratio to 1 (bits
1785 * 31:24) even though these are only valid for CPU
1786 * models > 2, however guests may end up dividing or
1787 * multiplying by zero otherwise.
1788 */
1789 case MSR_EBC_FREQUENCY_ID:
1790 data = 1 << 24;
1791 break;
15c4a640
CO		 1792 case MSR_IA32_APICBASE:
1793 data = kvm_get_apic_base(vcpu);
1794 break;
0105d1a5
GN		 1795 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1796 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1797 break;
15c4a640 1798 case MSR_IA32_MISC_ENABLE:
ad312c7c 1799 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1800 break;
847f0ad8
AG		 1801 case MSR_IA32_PERF_STATUS:
1802 /* TSC increment by tick */
1803 data = 1000ULL;
1804 /* CPU multiplier */
1805 data |= (((uint64_t)4ULL) << 40);
1806 break;
15c4a640 1807 case MSR_EFER:
f6801dff 1808 data = vcpu->arch.efer;
15c4a640 1809 break;
18068523 1810 case MSR_KVM_WALL_CLOCK:
11c6bffa 1811 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1812 data = vcpu->kvm->arch.wall_clock;
1813 break;
1814 case MSR_KVM_SYSTEM_TIME:
11c6bffa 1815 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1816 data = vcpu->arch.time;
1817 break;
344d9588
GN		 1818 case MSR_KVM_ASYNC_PF_EN:
1819 data = vcpu->arch.apf.msr_val;
1820 break;
890ca9ae
HY		 1821 case MSR_IA32_P5_MC_ADDR:
1822 case MSR_IA32_P5_MC_TYPE:
1823 case MSR_IA32_MCG_CAP:
1824 case MSR_IA32_MCG_CTL:
1825 case MSR_IA32_MCG_STATUS:
1826 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1827 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 1828 case MSR_K7_CLK_CTL:
1829 /*
1830 * Provide expected ramp-up count for K7. All other
1831 * are set to zero, indicating minimum divisors for
1832 * every field.
1833 *
1834 * This prevents guest kernels on AMD host with CPU
1835 * type 6, model 8 and higher from exploding due to
1836 * the rdmsr failing.
1837 */
1838 data = 0x20000000;
1839 break;
55cd8e5a
GN		 1840 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1841 if (kvm_hv_msr_partition_wide(msr)) {
1842 int r;
1843 mutex_lock(&vcpu->kvm->lock);
1844 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1845 mutex_unlock(&vcpu->kvm->lock);
1846 return r;
1847 } else
1848 return get_msr_hyperv(vcpu, msr, pdata);
1849 break;
91c9c3ed 1850 case MSR_IA32_BBL_CR_CTL3:
1851 /* This legacy MSR exists but isn't fully documented in current
1852 * silicon. It is however accessed by winxp in very narrow
1853 * scenarios where it sets bit #19, itself documented as
1854 * a "reserved" bit. Best effort attempt to source coherent
1855 * read data here should the balance of the register be
1856 * interpreted by the guest:
1857 *
1858 * L2 cache control register 3: 64GB range, 256KB size,
1859 * enabled, latency 0x1, configured
1860 */
1861 data = 0xbe702111;
1862 break;
15c4a640 1863 default:
ed85c068
AP		 1864 if (!ignore_msrs) {
1865 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1866 return 1;
1867 } else {
1868 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1869 data = 0;
1870 }
1871 break;
15c4a640
CO		 1872 }
1873 *pdata = data;
1874 return 0;
1875}
1876EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1877
313a3dc7
CO		 1878/*
1879 * Read or write a bunch of msrs. All parameters are kernel addresses.
1880 *
1881 * @return number of msrs set successfully.
1882 */
1883static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1884 struct kvm_msr_entry *entries,
1885 int (*do_msr)(struct kvm_vcpu *vcpu,
1886 unsigned index, u64 *data))
1887{
f656ce01 1888 int i, idx;
313a3dc7 1889
f656ce01 1890 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 1891 for (i = 0; i < msrs->nmsrs; ++i)
1892 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1893 break;
f656ce01 1894 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 1895
313a3dc7
CO		 1896 return i;
1897}
1898
1899/*
1900 * Read or write a bunch of msrs. Parameters are user addresses.
1901 *
1902 * @return number of msrs set successfully.
1903 */
1904static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1905 int (*do_msr)(struct kvm_vcpu *vcpu,
1906 unsigned index, u64 *data),
1907 int writeback)
1908{
1909 struct kvm_msrs msrs;
1910 struct kvm_msr_entry *entries;
1911 int r, n;
1912 unsigned size;
1913
1914 r = -EFAULT;
1915 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1916 goto out;
1917
1918 r = -E2BIG;
1919 if (msrs.nmsrs >= MAX_IO_MSRS)
1920 goto out;
1921
1922 r = -ENOMEM;
1923 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
7a73c028 1924 entries = kmalloc(size, GFP_KERNEL);
313a3dc7
CO		 1925 if (!entries)
1926 goto out;
1927
1928 r = -EFAULT;
1929 if (copy_from_user(entries, user_msrs->entries, size))
1930 goto out_free;
1931
1932 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1933 if (r < 0)
1934 goto out_free;
1935
1936 r = -EFAULT;
1937 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1938 goto out_free;
1939
1940 r = n;
1941
1942out_free:
7a73c028 1943 kfree(entries);
313a3dc7
CO		 1944out:
1945 return r;
1946}
1947
018d00d2
ZX		 1948int kvm_dev_ioctl_check_extension(long ext)
1949{
1950 int r;
1951
1952 switch (ext) {
1953 case KVM_CAP_IRQCHIP:
1954 case KVM_CAP_HLT:
1955 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1956 case KVM_CAP_SET_TSS_ADDR:
07716717 1957 case KVM_CAP_EXT_CPUID:
c8076604 1958 case KVM_CAP_CLOCKSOURCE:
7837699f 1959 case KVM_CAP_PIT:
a28e4f5a 1960 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1961 case KVM_CAP_MP_STATE:
ed848624 1962 case KVM_CAP_SYNC_MMU:
a355c85c 1963 case KVM_CAP_USER_NMI:
52d939a0 1964 case KVM_CAP_REINJECT_CONTROL:
4925663a 1965 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1966 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1967 case KVM_CAP_IRQFD:
d34e6b17 1968 case KVM_CAP_IOEVENTFD:
c5ff41ce 1969 case KVM_CAP_PIT2:
e9f42757 1970 case KVM_CAP_PIT_STATE2:
b927a3ce 1971 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 1972 case KVM_CAP_XEN_HVM:
afbcf7ab 1973 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 1974 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 1975 case KVM_CAP_HYPERV:
10388a07 1976 case KVM_CAP_HYPERV_VAPIC:
c25bc163 1977 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 1978 case KVM_CAP_PCI_SEGMENT:
a1efbe77 1979 case KVM_CAP_DEBUGREGS:
d2be1651 1980 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 1981 case KVM_CAP_XSAVE:
344d9588 1982 case KVM_CAP_ASYNC_PF:
018d00d2
ZX		 1983 r = 1;
1984 break;
542472b5
LV		 1985 case KVM_CAP_COALESCED_MMIO:
1986 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1987 break;
774ead3a
AK		 1988 case KVM_CAP_VAPIC:
1989 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1990 break;
f725230a
AK		 1991 case KVM_CAP_NR_VCPUS:
1992 r = KVM_MAX_VCPUS;
1993 break;
a988b910
AK		 1994 case KVM_CAP_NR_MEMSLOTS:
1995 r = KVM_MEMORY_SLOTS;
1996 break;
a68a6a72
MT		 1997 case KVM_CAP_PV_MMU: /* obsolete */
1998 r = 0;
2f333bcb 1999 break;
62c476c7 2000 case KVM_CAP_IOMMU:
19de40a8 2001 r = iommu_found();
62c476c7 2002 break;
890ca9ae
HY		 2003 case KVM_CAP_MCE:
2004 r = KVM_MAX_MCE_BANKS;
2005 break;
2d5b5a66
SY		 2006 case KVM_CAP_XCRS:
2007 r = cpu_has_xsave;
2008 break;
018d00d2
ZX		 2009 default:
2010 r = 0;
2011 break;
2012 }
2013 return r;
2014
2015}
2016
043405e1
CO		 2017long kvm_arch_dev_ioctl(struct file *filp,
2018 unsigned int ioctl, unsigned long arg)
2019{
2020 void __user *argp = (void __user *)arg;
2021 long r;
2022
2023 switch (ioctl) {
2024 case KVM_GET_MSR_INDEX_LIST: {
2025 struct kvm_msr_list __user *user_msr_list = argp;
2026 struct kvm_msr_list msr_list;
2027 unsigned n;
2028
2029 r = -EFAULT;
2030 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2031 goto out;
2032 n = msr_list.nmsrs;
2033 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2034 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2035 goto out;
2036 r = -E2BIG;
e125e7b6 2037 if (n < msr_list.nmsrs)
043405e1
CO		 2038 goto out;
2039 r = -EFAULT;
2040 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2041 num_msrs_to_save * sizeof(u32)))
2042 goto out;
e125e7b6 2043 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2044 &emulated_msrs,
2045 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2046 goto out;
2047 r = 0;
2048 break;
2049 }
674eea0f
AK		 2050 case KVM_GET_SUPPORTED_CPUID: {
2051 struct kvm_cpuid2 __user *cpuid_arg = argp;
2052 struct kvm_cpuid2 cpuid;
2053
2054 r = -EFAULT;
2055 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2056 goto out;
2057 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 2058 cpuid_arg->entries);
674eea0f
AK		 2059 if (r)
2060 goto out;
2061
2062 r = -EFAULT;
2063 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2064 goto out;
2065 r = 0;
2066 break;
2067 }
890ca9ae
HY		 2068 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2069 u64 mce_cap;
2070
2071 mce_cap = KVM_MCE_CAP_SUPPORTED;
2072 r = -EFAULT;
2073 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2074 goto out;
2075 r = 0;
2076 break;
2077 }
043405e1
CO		 2078 default:
2079 r = -EINVAL;
2080 }
2081out:
2082 return r;
2083}
2084
f5f48ee1
SY		 2085static void wbinvd_ipi(void *garbage)
2086{
2087 wbinvd();
2088}
2089
2090static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2091{
2092 return vcpu->kvm->arch.iommu_domain &&
2093 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2094}
2095
313a3dc7
CO		 2096void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2097{
f5f48ee1
SY		 2098 /* Address WBINVD may be executed by guest */
2099 if (need_emulate_wbinvd(vcpu)) {
2100 if (kvm_x86_ops->has_wbinvd_exit())
2101 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2102 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2103 smp_call_function_single(vcpu->cpu,
2104 wbinvd_ipi, NULL, 1);
2105 }
2106
313a3dc7 2107 kvm_x86_ops->vcpu_load(vcpu, cpu);
48434c20 2108 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
e48672fa
ZA		 2109 /* Make sure TSC doesn't go backwards */
2110 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2111 native_read_tsc() - vcpu->arch.last_host_tsc;
2112 if (tsc_delta < 0)
2113 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2114 if (check_tsc_unstable()) {
e48672fa 2115 kvm_x86_ops->adjust_tsc_offset(vcpu, -tsc_delta);
c285545f 2116 vcpu->arch.tsc_catchup = 1;
c285545f 2117 }
1aa8ceef 2118 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2119 if (vcpu->cpu != cpu)
2120 kvm_migrate_timers(vcpu);
e48672fa 2121 vcpu->cpu = cpu;
6b7d7e76 2122 }
313a3dc7
CO		 2123}
2124
2125void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2126{
02daab21 2127 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2128 kvm_put_guest_fpu(vcpu);
e48672fa 2129 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2130}
2131
07716717 2132static int is_efer_nx(void)
313a3dc7 2133{
e286e86e 2134 unsigned long long efer = 0;
313a3dc7 2135
e286e86e 2136 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 2137 return efer & EFER_NX;
2138}
2139
2140static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
2141{
2142 int i;
2143 struct kvm_cpuid_entry2 *e, *entry;
2144
313a3dc7 2145 entry = NULL;
ad312c7c
ZX		 2146 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
2147 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 2148 if (e->function == 0x80000001) {
2149 entry = e;
2150 break;
2151 }
2152 }
07716717 2153 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 2154 entry->edx &= ~(1 << 20);
2155 printk(KERN_INFO "kvm: guest NX capability removed\n");
2156 }
2157}
2158
07716717 2159/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 2160static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
2161 struct kvm_cpuid *cpuid,
2162 struct kvm_cpuid_entry __user *entries)
07716717
DK		 2163{
2164 int r, i;
2165 struct kvm_cpuid_entry *cpuid_entries;
2166
2167 r = -E2BIG;
2168 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2169 goto out;
2170 r = -ENOMEM;
2171 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
2172 if (!cpuid_entries)
2173 goto out;
2174 r = -EFAULT;
2175 if (copy_from_user(cpuid_entries, entries,
2176 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
2177 goto out_free;
2178 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 2179 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
2180 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
2181 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
2182 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
2183 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
2184 vcpu->arch.cpuid_entries[i].index = 0;
2185 vcpu->arch.cpuid_entries[i].flags = 0;
2186 vcpu->arch.cpuid_entries[i].padding[0] = 0;
2187 vcpu->arch.cpuid_entries[i].padding[1] = 0;
2188 vcpu->arch.cpuid_entries[i].padding[2] = 0;
2189 }
2190 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 2191 cpuid_fix_nx_cap(vcpu);
2192 r = 0;
fc61b800 2193 kvm_apic_set_version(vcpu);
0e851880 2194 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 2195 update_cpuid(vcpu);
07716717
DK		 2196
2197out_free:
2198 vfree(cpuid_entries);
2199out:
2200 return r;
2201}
2202
2203static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 2204 struct kvm_cpuid2 *cpuid,
2205 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 2206{
2207 int r;
2208
2209 r = -E2BIG;
2210 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2211 goto out;
2212 r = -EFAULT;
ad312c7c 2213 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 2214 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 2215 goto out;
ad312c7c 2216 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 2217 kvm_apic_set_version(vcpu);
0e851880 2218 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 2219 update_cpuid(vcpu);
313a3dc7
CO		 2220 return 0;
2221
2222out:
2223 return r;
2224}
2225
07716717 2226static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 2227 struct kvm_cpuid2 *cpuid,
2228 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2229{
2230 int r;
2231
2232 r = -E2BIG;
ad312c7c 2233 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 2234 goto out;
2235 r = -EFAULT;
ad312c7c 2236 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 2237 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2238 goto out;
2239 return 0;
2240
2241out:
ad312c7c 2242 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 2243 return r;
2244}
2245
945ee35e
AK		 2246static void cpuid_mask(u32 *word, int wordnum)
2247{
2248 *word &= boot_cpu_data.x86_capability[wordnum];
2249}
2250
07716717 2251static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 2252 u32 index)
07716717
DK		 2253{
2254 entry->function = function;
2255 entry->index = index;
2256 cpuid_count(entry->function, entry->index,
19355475 2257 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 2258 entry->flags = 0;
2259}
2260
7faa4ee1
AK		 2261#define F(x) bit(X86_FEATURE_##x)
2262
07716717
DK		 2263static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
2264 u32 index, int *nent, int maxnent)
2265{
7faa4ee1 2266 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 2267#ifdef CONFIG_X86_64
17cc3935
SY		 2268 unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
2269 ? F(GBPAGES) : 0;
7faa4ee1
AK		 2270 unsigned f_lm = F(LM);
2271#else
17cc3935 2272 unsigned f_gbpages = 0;
7faa4ee1 2273 unsigned f_lm = 0;
07716717 2274#endif
4e47c7a6 2275 unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
7faa4ee1
AK		 2276
2277 /* cpuid 1.edx */
2278 const u32 kvm_supported_word0_x86_features =
2279 F(FPU) | F(VME) | F(DE) | F(PSE) |
2280 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2281 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
2282 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2283 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
2284 0 /* Reserved, DS, ACPI */ | F(MMX) |
2285 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
2286 0 /* HTT, TM, Reserved, PBE */;
2287 /* cpuid 0x80000001.edx */
2288 const u32 kvm_supported_word1_x86_features =
2289 F(FPU) | F(VME) | F(DE) | F(PSE) |
2290 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2291 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
2292 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2293 F(PAT) | F(PSE36) | 0 /* Reserved */ |
2294 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
4e47c7a6 2295 F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
7faa4ee1
AK		 2296 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
2297 /* cpuid 1.ecx */
2298 const u32 kvm_supported_word4_x86_features =
6c3f6041 2299 F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ |
d149c731
AK		 2300 0 /* DS-CPL, VMX, SMX, EST */ |
2301 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
2302 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
2303 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 2304 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
6d886fd0
AP		 2305 0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) |
2306 F(F16C);
7faa4ee1 2307 /* cpuid 0x80000001.ecx */
07716717 2308 const u32 kvm_supported_word6_x86_features =
4c62a2dc 2309 F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ |
7faa4ee1 2310 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
7ef8aa72 2311 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(XOP) |
6d886fd0 2312 0 /* SKINIT, WDT, LWP */ | F(FMA4) | F(TBM);
07716717 2313
19355475 2314 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 2315 get_cpu();
2316 do_cpuid_1_ent(entry, function, index);
2317 ++*nent;
2318
2319 switch (function) {
2320 case 0:
2acf923e 2321 entry->eax = min(entry->eax, (u32)0xd);
07716717
DK		 2322 break;
2323 case 1:
2324 entry->edx &= kvm_supported_word0_x86_features;
945ee35e 2325 cpuid_mask(&entry->edx, 0);
7faa4ee1 2326 entry->ecx &= kvm_supported_word4_x86_features;
945ee35e 2327 cpuid_mask(&entry->ecx, 4);
0d1de2d9
GN		 2328 /* we support x2apic emulation even if host does not support
2329 * it since we emulate x2apic in software */
2330 entry->ecx |= F(X2APIC);
07716717
DK		 2331 break;
2332 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
2333 * may return different values. This forces us to get_cpu() before
2334 * issuing the first command, and also to emulate this annoying behavior
2335 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
2336 case 2: {
2337 int t, times = entry->eax & 0xff;
2338
2339 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 2340 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 2341 for (t = 1; t < times && *nent < maxnent; ++t) {
2342 do_cpuid_1_ent(&entry[t], function, 0);
2343 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
2344 ++*nent;
2345 }
2346 break;
2347 }
2348 /* function 4 and 0xb have additional index. */
2349 case 4: {
14af3f3c 2350 int i, cache_type;
07716717
DK		 2351
2352 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2353 /* read more entries until cache_type is zero */
14af3f3c
HH		 2354 for (i = 1; *nent < maxnent; ++i) {
2355 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 2356 if (!cache_type)
2357 break;
14af3f3c
HH		 2358 do_cpuid_1_ent(&entry[i], function, i);
2359 entry[i].flags |=
07716717
DK		 2360 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2361 ++*nent;
2362 }
2363 break;
2364 }
2365 case 0xb: {
14af3f3c 2366 int i, level_type;
07716717
DK		 2367
2368 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2369 /* read more entries until level_type is zero */
14af3f3c 2370 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 2371 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 2372 if (!level_type)
2373 break;
14af3f3c
HH		 2374 do_cpuid_1_ent(&entry[i], function, i);
2375 entry[i].flags |=
07716717
DK		 2376 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2377 ++*nent;
2378 }
2379 break;
2380 }
2acf923e
DC		 2381 case 0xd: {
2382 int i;
2383
2384 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
20800bc9
AP		 2385 for (i = 1; *nent < maxnent && i < 64; ++i) {
2386 if (entry[i].eax == 0)
2387 continue;
2acf923e
DC		 2388 do_cpuid_1_ent(&entry[i], function, i);
2389 entry[i].flags |=
2390 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2391 ++*nent;
2392 }
2393 break;
2394 }
84478c82
GC		 2395 case KVM_CPUID_SIGNATURE: {
2396 char signature[12] = "KVMKVMKVM\0\0";
2397 u32 *sigptr = (u32 *)signature;
2398 entry->eax = 0;
2399 entry->ebx = sigptr[0];
2400 entry->ecx = sigptr[1];
2401 entry->edx = sigptr[2];
2402 break;
2403 }
2404 case KVM_CPUID_FEATURES:
2405 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) |
2406 (1 << KVM_FEATURE_NOP_IO_DELAY) |
371bcf64 2407 (1 << KVM_FEATURE_CLOCKSOURCE2) |
32918924 2408 (1 << KVM_FEATURE_ASYNC_PF) |
371bcf64 2409 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
84478c82
GC		 2410 entry->ebx = 0;
2411 entry->ecx = 0;
2412 entry->edx = 0;
2413 break;
07716717
DK		 2414 case 0x80000000:
2415 entry->eax = min(entry->eax, 0x8000001a);
2416 break;
2417 case 0x80000001:
2418 entry->edx &= kvm_supported_word1_x86_features;
945ee35e 2419 cpuid_mask(&entry->edx, 1);
07716717 2420 entry->ecx &= kvm_supported_word6_x86_features;
945ee35e 2421 cpuid_mask(&entry->ecx, 6);
07716717
DK		 2422 break;
2423 }
d4330ef2
JR		 2424
2425 kvm_x86_ops->set_supported_cpuid(function, entry);
2426
07716717
DK		 2427 put_cpu();
2428}
2429
7faa4ee1
AK		 2430#undef F
2431
674eea0f 2432static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 2433 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2434{
2435 struct kvm_cpuid_entry2 *cpuid_entries;
2436 int limit, nent = 0, r = -E2BIG;
2437 u32 func;
2438
2439 if (cpuid->nent < 1)
2440 goto out;
6a544355
AK		 2441 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2442 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
07716717
DK		 2443 r = -ENOMEM;
2444 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
2445 if (!cpuid_entries)
2446 goto out;
2447
2448 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
2449 limit = cpuid_entries[0].eax;
2450 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
2451 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2452 &nent, cpuid->nent);
07716717
DK		 2453 r = -E2BIG;
2454 if (nent >= cpuid->nent)
2455 goto out_free;
2456
2457 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
2458 limit = cpuid_entries[nent - 1].eax;
2459 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
2460 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2461 &nent, cpuid->nent);
84478c82
GC		 2462
2463
2464
2465 r = -E2BIG;
2466 if (nent >= cpuid->nent)
2467 goto out_free;
2468
2469 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_SIGNATURE, 0, &nent,
2470 cpuid->nent);
2471
2472 r = -E2BIG;
2473 if (nent >= cpuid->nent)
2474 goto out_free;
2475
2476 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_FEATURES, 0, &nent,
2477 cpuid->nent);
2478
cb007648
MM		 2479 r = -E2BIG;
2480 if (nent >= cpuid->nent)
2481 goto out_free;
2482
07716717
DK		 2483 r = -EFAULT;
2484 if (copy_to_user(entries, cpuid_entries,
19355475 2485 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2486 goto out_free;
2487 cpuid->nent = nent;
2488 r = 0;
2489
2490out_free:
2491 vfree(cpuid_entries);
2492out:
2493 return r;
2494}
2495
313a3dc7
CO		 2496static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2497 struct kvm_lapic_state *s)
2498{
ad312c7c 2499 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2500
2501 return 0;
2502}
2503
2504static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2505 struct kvm_lapic_state *s)
2506{
ad312c7c 2507 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 2508 kvm_apic_post_state_restore(vcpu);
cb142eb7 2509 update_cr8_intercept(vcpu);
313a3dc7
CO		 2510
2511 return 0;
2512}
2513
f77bc6a4
ZX		 2514static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2515 struct kvm_interrupt *irq)
2516{
2517 if (irq->irq < 0 || irq->irq >= 256)
2518 return -EINVAL;
2519 if (irqchip_in_kernel(vcpu->kvm))
2520 return -ENXIO;
f77bc6a4 2521
66fd3f7f 2522 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2523 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2524
f77bc6a4
ZX		 2525 return 0;
2526}
2527
c4abb7c9
JK		 2528static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2529{
c4abb7c9 2530 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2531
2532 return 0;
2533}
2534
b209749f
AK		 2535static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2536 struct kvm_tpr_access_ctl *tac)
2537{
2538 if (tac->flags)
2539 return -EINVAL;
2540 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2541 return 0;
2542}
2543
890ca9ae
HY		 2544static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2545 u64 mcg_cap)
2546{
2547 int r;
2548 unsigned bank_num = mcg_cap & 0xff, bank;
2549
2550 r = -EINVAL;
a9e38c3e 2551 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2552 goto out;
2553 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2554 goto out;
2555 r = 0;
2556 vcpu->arch.mcg_cap = mcg_cap;
2557 /* Init IA32_MCG_CTL to all 1s */
2558 if (mcg_cap & MCG_CTL_P)
2559 vcpu->arch.mcg_ctl = ~(u64)0;
2560 /* Init IA32_MCi_CTL to all 1s */
2561 for (bank = 0; bank < bank_num; bank++)
2562 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2563out:
2564 return r;
2565}
2566
2567static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2568 struct kvm_x86_mce *mce)
2569{
2570 u64 mcg_cap = vcpu->arch.mcg_cap;
2571 unsigned bank_num = mcg_cap & 0xff;
2572 u64 *banks = vcpu->arch.mce_banks;
2573
2574 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2575 return -EINVAL;
2576 /*
2577 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2578 * reporting is disabled
2579 */
2580 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2581 vcpu->arch.mcg_ctl != ~(u64)0)
2582 return 0;
2583 banks += 4 * mce->bank;
2584 /*
2585 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2586 * reporting is disabled for the bank
2587 */
2588 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2589 return 0;
2590 if (mce->status & MCI_STATUS_UC) {
2591 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2592 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2593 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2594 return 0;
2595 }
2596 if (banks[1] & MCI_STATUS_VAL)
2597 mce->status |= MCI_STATUS_OVER;
2598 banks[2] = mce->addr;
2599 banks[3] = mce->misc;
2600 vcpu->arch.mcg_status = mce->mcg_status;
2601 banks[1] = mce->status;
2602 kvm_queue_exception(vcpu, MC_VECTOR);
2603 } else if (!(banks[1] & MCI_STATUS_VAL)
2604 || !(banks[1] & MCI_STATUS_UC)) {
2605 if (banks[1] & MCI_STATUS_VAL)
2606 mce->status |= MCI_STATUS_OVER;
2607 banks[2] = mce->addr;
2608 banks[3] = mce->misc;
2609 banks[1] = mce->status;
2610 } else
2611 banks[1] |= MCI_STATUS_OVER;
2612 return 0;
2613}
2614
3cfc3092
JK		 2615static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2616 struct kvm_vcpu_events *events)
2617{
03b82a30
JK		 2618 events->exception.injected =
2619 vcpu->arch.exception.pending &&
2620 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2621 events->exception.nr = vcpu->arch.exception.nr;
2622 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2623 events->exception.pad = 0;
3cfc3092
JK		 2624 events->exception.error_code = vcpu->arch.exception.error_code;
2625
03b82a30
JK		 2626 events->interrupt.injected =
2627 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2628 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2629 events->interrupt.soft = 0;
48005f64
JK		 2630 events->interrupt.shadow =
2631 kvm_x86_ops->get_interrupt_shadow(vcpu,
2632 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2633
2634 events->nmi.injected = vcpu->arch.nmi_injected;
2635 events->nmi.pending = vcpu->arch.nmi_pending;
2636 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2637 events->nmi.pad = 0;
3cfc3092
JK		 2638
2639 events->sipi_vector = vcpu->arch.sipi_vector;
2640
dab4b911 2641 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2642 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2643 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 2644 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2645}
2646
2647static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2648 struct kvm_vcpu_events *events)
2649{
dab4b911 2650 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2651 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2652 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2653 return -EINVAL;
2654
3cfc3092
JK		 2655 vcpu->arch.exception.pending = events->exception.injected;
2656 vcpu->arch.exception.nr = events->exception.nr;
2657 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2658 vcpu->arch.exception.error_code = events->exception.error_code;
2659
2660 vcpu->arch.interrupt.pending = events->interrupt.injected;
2661 vcpu->arch.interrupt.nr = events->interrupt.nr;
2662 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2663 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2664 kvm_x86_ops->set_interrupt_shadow(vcpu,
2665 events->interrupt.shadow);
3cfc3092
JK		 2666
2667 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2668 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2669 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2670 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2671
dab4b911
JK		 2672 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2673 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092 2674
3842d135
AK		 2675 kvm_make_request(KVM_REQ_EVENT, vcpu);
2676
3cfc3092
JK		 2677 return 0;
2678}
2679
a1efbe77
JK		 2680static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2681 struct kvm_debugregs *dbgregs)
2682{
a1efbe77
JK		 2683 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2684 dbgregs->dr6 = vcpu->arch.dr6;
2685 dbgregs->dr7 = vcpu->arch.dr7;
2686 dbgregs->flags = 0;
97e69aa6 2687 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 2688}
2689
2690static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2691 struct kvm_debugregs *dbgregs)
2692{
2693 if (dbgregs->flags)
2694 return -EINVAL;
2695
a1efbe77
JK		 2696 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2697 vcpu->arch.dr6 = dbgregs->dr6;
2698 vcpu->arch.dr7 = dbgregs->dr7;
2699
a1efbe77
JK		 2700 return 0;
2701}
2702
2d5b5a66
SY		 2703static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2704 struct kvm_xsave *guest_xsave)
2705{
2706 if (cpu_has_xsave)
2707 memcpy(guest_xsave->region,
2708 &vcpu->arch.guest_fpu.state->xsave,
f45755b8 2709 xstate_size);
2d5b5a66
SY		 2710 else {
2711 memcpy(guest_xsave->region,
2712 &vcpu->arch.guest_fpu.state->fxsave,
2713 sizeof(struct i387_fxsave_struct));
2714 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2715 XSTATE_FPSSE;
2716 }
2717}
2718
2719static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2720 struct kvm_xsave *guest_xsave)
2721{
2722 u64 xstate_bv =
2723 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2724
2725 if (cpu_has_xsave)
2726 memcpy(&vcpu->arch.guest_fpu.state->xsave,
f45755b8 2727 guest_xsave->region, xstate_size);
2d5b5a66
SY		 2728 else {
2729 if (xstate_bv & ~XSTATE_FPSSE)
2730 return -EINVAL;
2731 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2732 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2733 }
2734 return 0;
2735}
2736
2737static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2738 struct kvm_xcrs *guest_xcrs)
2739{
2740 if (!cpu_has_xsave) {
2741 guest_xcrs->nr_xcrs = 0;
2742 return;
2743 }
2744
2745 guest_xcrs->nr_xcrs = 1;
2746 guest_xcrs->flags = 0;
2747 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2748 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2749}
2750
2751static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2752 struct kvm_xcrs *guest_xcrs)
2753{
2754 int i, r = 0;
2755
2756 if (!cpu_has_xsave)
2757 return -EINVAL;
2758
2759 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2760 return -EINVAL;
2761
2762 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2763 /* Only support XCR0 currently */
2764 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2765 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2766 guest_xcrs->xcrs[0].value);
2767 break;
2768 }
2769 if (r)
2770 r = -EINVAL;
2771 return r;
2772}
2773
313a3dc7
CO		 2774long kvm_arch_vcpu_ioctl(struct file *filp,
2775 unsigned int ioctl, unsigned long arg)
2776{
2777 struct kvm_vcpu *vcpu = filp->private_data;
2778 void __user *argp = (void __user *)arg;
2779 int r;
d1ac91d8
AK		 2780 union {
2781 struct kvm_lapic_state *lapic;
2782 struct kvm_xsave *xsave;
2783 struct kvm_xcrs *xcrs;
2784 void *buffer;
2785 } u;
2786
2787 u.buffer = NULL;
313a3dc7
CO		 2788 switch (ioctl) {
2789 case KVM_GET_LAPIC: {
2204ae3c
MT		 2790 r = -EINVAL;
2791 if (!vcpu->arch.apic)
2792 goto out;
d1ac91d8 2793 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2794
b772ff36 2795 r = -ENOMEM;
d1ac91d8 2796 if (!u.lapic)
b772ff36 2797 goto out;
d1ac91d8 2798 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 2799 if (r)
2800 goto out;
2801 r = -EFAULT;
d1ac91d8 2802 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2803 goto out;
2804 r = 0;
2805 break;
2806 }
2807 case KVM_SET_LAPIC: {
2204ae3c
MT		 2808 r = -EINVAL;
2809 if (!vcpu->arch.apic)
2810 goto out;
d1ac91d8 2811 u.lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
b772ff36 2812 r = -ENOMEM;
d1ac91d8 2813 if (!u.lapic)
b772ff36 2814 goto out;
313a3dc7 2815 r = -EFAULT;
d1ac91d8 2816 if (copy_from_user(u.lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 2817 goto out;
d1ac91d8 2818 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 2819 if (r)
2820 goto out;
2821 r = 0;
2822 break;
2823 }
f77bc6a4
ZX		 2824 case KVM_INTERRUPT: {
2825 struct kvm_interrupt irq;
2826
2827 r = -EFAULT;
2828 if (copy_from_user(&irq, argp, sizeof irq))
2829 goto out;
2830 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2831 if (r)
2832 goto out;
2833 r = 0;
2834 break;
2835 }
c4abb7c9
JK		 2836 case KVM_NMI: {
2837 r = kvm_vcpu_ioctl_nmi(vcpu);
2838 if (r)
2839 goto out;
2840 r = 0;
2841 break;
2842 }
313a3dc7
CO		 2843 case KVM_SET_CPUID: {
2844 struct kvm_cpuid __user *cpuid_arg = argp;
2845 struct kvm_cpuid cpuid;
2846
2847 r = -EFAULT;
2848 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2849 goto out;
2850 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2851 if (r)
2852 goto out;
2853 break;
2854 }
07716717
DK		 2855 case KVM_SET_CPUID2: {
2856 struct kvm_cpuid2 __user *cpuid_arg = argp;
2857 struct kvm_cpuid2 cpuid;
2858
2859 r = -EFAULT;
2860 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2861 goto out;
2862 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2863 cpuid_arg->entries);
07716717
DK		 2864 if (r)
2865 goto out;
2866 break;
2867 }
2868 case KVM_GET_CPUID2: {
2869 struct kvm_cpuid2 __user *cpuid_arg = argp;
2870 struct kvm_cpuid2 cpuid;
2871
2872 r = -EFAULT;
2873 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2874 goto out;
2875 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2876 cpuid_arg->entries);
07716717
DK		 2877 if (r)
2878 goto out;
2879 r = -EFAULT;
2880 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2881 goto out;
2882 r = 0;
2883 break;
2884 }
313a3dc7
CO		 2885 case KVM_GET_MSRS:
2886 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2887 break;
2888 case KVM_SET_MSRS:
2889 r = msr_io(vcpu, argp, do_set_msr, 0);
2890 break;
b209749f
AK		 2891 case KVM_TPR_ACCESS_REPORTING: {
2892 struct kvm_tpr_access_ctl tac;
2893
2894 r = -EFAULT;
2895 if (copy_from_user(&tac, argp, sizeof tac))
2896 goto out;
2897 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2898 if (r)
2899 goto out;
2900 r = -EFAULT;
2901 if (copy_to_user(argp, &tac, sizeof tac))
2902 goto out;
2903 r = 0;
2904 break;
2905 };
b93463aa
AK		 2906 case KVM_SET_VAPIC_ADDR: {
2907 struct kvm_vapic_addr va;
2908
2909 r = -EINVAL;
2910 if (!irqchip_in_kernel(vcpu->kvm))
2911 goto out;
2912 r = -EFAULT;
2913 if (copy_from_user(&va, argp, sizeof va))
2914 goto out;
2915 r = 0;
2916 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2917 break;
2918 }
890ca9ae
HY		 2919 case KVM_X86_SETUP_MCE: {
2920 u64 mcg_cap;
2921
2922 r = -EFAULT;
2923 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2924 goto out;
2925 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2926 break;
2927 }
2928 case KVM_X86_SET_MCE: {
2929 struct kvm_x86_mce mce;
2930
2931 r = -EFAULT;
2932 if (copy_from_user(&mce, argp, sizeof mce))
2933 goto out;
2934 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2935 break;
2936 }
3cfc3092
JK		 2937 case KVM_GET_VCPU_EVENTS: {
2938 struct kvm_vcpu_events events;
2939
2940 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2941
2942 r = -EFAULT;
2943 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2944 break;
2945 r = 0;
2946 break;
2947 }
2948 case KVM_SET_VCPU_EVENTS: {
2949 struct kvm_vcpu_events events;
2950
2951 r = -EFAULT;
2952 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2953 break;
2954
2955 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2956 break;
2957 }
a1efbe77
JK		 2958 case KVM_GET_DEBUGREGS: {
2959 struct kvm_debugregs dbgregs;
2960
2961 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2962
2963 r = -EFAULT;
2964 if (copy_to_user(argp, &dbgregs,
2965 sizeof(struct kvm_debugregs)))
2966 break;
2967 r = 0;
2968 break;
2969 }
2970 case KVM_SET_DEBUGREGS: {
2971 struct kvm_debugregs dbgregs;
2972
2973 r = -EFAULT;
2974 if (copy_from_user(&dbgregs, argp,
2975 sizeof(struct kvm_debugregs)))
2976 break;
2977
2978 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2979 break;
2980 }
2d5b5a66 2981 case KVM_GET_XSAVE: {
d1ac91d8 2982 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 2983 r = -ENOMEM;
d1ac91d8 2984 if (!u.xsave)
2d5b5a66
SY		 2985 break;
2986
d1ac91d8 2987 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2988
2989 r = -EFAULT;
d1ac91d8 2990 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 2991 break;
2992 r = 0;
2993 break;
2994 }
2995 case KVM_SET_XSAVE: {
d1ac91d8 2996 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 2997 r = -ENOMEM;
d1ac91d8 2998 if (!u.xsave)
2d5b5a66
SY		 2999 break;
3000
3001 r = -EFAULT;
d1ac91d8 3002 if (copy_from_user(u.xsave, argp, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3003 break;
3004
d1ac91d8 3005 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3006 break;
3007 }
3008 case KVM_GET_XCRS: {
d1ac91d8 3009 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3010 r = -ENOMEM;
d1ac91d8 3011 if (!u.xcrs)
2d5b5a66
SY		 3012 break;
3013
d1ac91d8 3014 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3015
3016 r = -EFAULT;
d1ac91d8 3017 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3018 sizeof(struct kvm_xcrs)))
3019 break;
3020 r = 0;
3021 break;
3022 }
3023 case KVM_SET_XCRS: {
d1ac91d8 3024 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3025 r = -ENOMEM;
d1ac91d8 3026 if (!u.xcrs)
2d5b5a66
SY		 3027 break;
3028
3029 r = -EFAULT;
d1ac91d8 3030 if (copy_from_user(u.xcrs, argp,
2d5b5a66
SY		 3031 sizeof(struct kvm_xcrs)))
3032 break;
3033
d1ac91d8 3034 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3035 break;
3036 }
313a3dc7
CO		 3037 default:
3038 r = -EINVAL;
3039 }
3040out:
d1ac91d8 3041 kfree(u.buffer);
313a3dc7
CO		 3042 return r;
3043}
3044
1fe779f8
CO		 3045static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3046{
3047 int ret;
3048
3049 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3050 return -1;
3051 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3052 return ret;
3053}
3054
b927a3ce
SY		 3055static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3056 u64 ident_addr)
3057{
3058 kvm->arch.ept_identity_map_addr = ident_addr;
3059 return 0;
3060}
3061
1fe779f8
CO		 3062static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3063 u32 kvm_nr_mmu_pages)
3064{
3065 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3066 return -EINVAL;
3067
79fac95e 3068 mutex_lock(&kvm->slots_lock);
7c8a83b7 3069 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 3070
3071 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3072 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3073
7c8a83b7 3074 spin_unlock(&kvm->mmu_lock);
79fac95e 3075 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3076 return 0;
3077}
3078
3079static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3080{
39de71ec 3081 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3082}
3083
1fe779f8
CO		 3084static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3085{
3086 int r;
3087
3088 r = 0;
3089 switch (chip->chip_id) {
3090 case KVM_IRQCHIP_PIC_MASTER:
3091 memcpy(&chip->chip.pic,
3092 &pic_irqchip(kvm)->pics[0],
3093 sizeof(struct kvm_pic_state));
3094 break;
3095 case KVM_IRQCHIP_PIC_SLAVE:
3096 memcpy(&chip->chip.pic,
3097 &pic_irqchip(kvm)->pics[1],
3098 sizeof(struct kvm_pic_state));
3099 break;
3100 case KVM_IRQCHIP_IOAPIC:
eba0226b 3101 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3102 break;
3103 default:
3104 r = -EINVAL;
3105 break;
3106 }
3107 return r;
3108}
3109
3110static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3111{
3112 int r;
3113
3114 r = 0;
3115 switch (chip->chip_id) {
3116 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3117 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3118 memcpy(&pic_irqchip(kvm)->pics[0],
3119 &chip->chip.pic,
3120 sizeof(struct kvm_pic_state));
f4f51050 3121 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3122 break;
3123 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3124 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3125 memcpy(&pic_irqchip(kvm)->pics[1],
3126 &chip->chip.pic,
3127 sizeof(struct kvm_pic_state));
f4f51050 3128 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3129 break;
3130 case KVM_IRQCHIP_IOAPIC:
eba0226b 3131 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3132 break;
3133 default:
3134 r = -EINVAL;
3135 break;
3136 }
3137 kvm_pic_update_irq(pic_irqchip(kvm));
3138 return r;
3139}
3140
e0f63cb9
SY		 3141static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3142{
3143 int r = 0;
3144
894a9c55 3145 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3146 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3147 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3148 return r;
3149}
3150
3151static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3152{
3153 int r = 0;
3154
894a9c55 3155 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3156 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3157 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3158 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3159 return r;
3160}
3161
3162static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3163{
3164 int r = 0;
3165
3166 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3167 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3168 sizeof(ps->channels));
3169 ps->flags = kvm->arch.vpit->pit_state.flags;
3170 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3171 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3172 return r;
3173}
3174
3175static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3176{
3177 int r = 0, start = 0;
3178 u32 prev_legacy, cur_legacy;
3179 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3180 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3181 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3182 if (!prev_legacy && cur_legacy)
3183 start = 1;
3184 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3185 sizeof(kvm->arch.vpit->pit_state.channels));
3186 kvm->arch.vpit->pit_state.flags = ps->flags;
3187 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3188 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3189 return r;
3190}
3191
52d939a0
MT		 3192static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3193 struct kvm_reinject_control *control)
3194{
3195 if (!kvm->arch.vpit)
3196 return -ENXIO;
894a9c55 3197 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 3198 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 3199 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3200 return 0;
3201}
3202
5bb064dc
ZX		 3203/*
3204 * Get (and clear) the dirty memory log for a memory slot.
3205 */
3206int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
3207 struct kvm_dirty_log *log)
3208{
87bf6e7d 3209 int r, i;
5bb064dc 3210 struct kvm_memory_slot *memslot;
87bf6e7d 3211 unsigned long n;
b050b015 3212 unsigned long is_dirty = 0;
5bb064dc 3213
79fac95e 3214 mutex_lock(&kvm->slots_lock);
5bb064dc 3215
b050b015
MT		 3216 r = -EINVAL;
3217 if (log->slot >= KVM_MEMORY_SLOTS)
3218 goto out;
3219
3220 memslot = &kvm->memslots->memslots[log->slot];
3221 r = -ENOENT;
3222 if (!memslot->dirty_bitmap)
3223 goto out;
3224
87bf6e7d 3225 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3226
b050b015
MT		 3227 for (i = 0; !is_dirty && i < n/sizeof(long); i++)
3228 is_dirty = memslot->dirty_bitmap[i];
5bb064dc
ZX		 3229
3230 /* If nothing is dirty, don't bother messing with page tables. */
3231 if (is_dirty) {
b050b015 3232 struct kvm_memslots *slots, *old_slots;
914ebccd 3233 unsigned long *dirty_bitmap;
b050b015 3234
515a0127
TY		 3235 dirty_bitmap = memslot->dirty_bitmap_head;
3236 if (memslot->dirty_bitmap == dirty_bitmap)
3237 dirty_bitmap += n / sizeof(long);
914ebccd 3238 memset(dirty_bitmap, 0, n);
b050b015 3239
914ebccd
TY		 3240 r = -ENOMEM;
3241 slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
515a0127 3242 if (!slots)
914ebccd 3243 goto out;
b050b015
MT		 3244 memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
3245 slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
49c7754c 3246 slots->generation++;
b050b015
MT		 3247
3248 old_slots = kvm->memslots;
3249 rcu_assign_pointer(kvm->memslots, slots);
3250 synchronize_srcu_expedited(&kvm->srcu);
3251 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
3252 kfree(old_slots);
914ebccd 3253
edde99ce
MT		 3254 spin_lock(&kvm->mmu_lock);
3255 kvm_mmu_slot_remove_write_access(kvm, log->slot);
3256 spin_unlock(&kvm->mmu_lock);
3257
914ebccd 3258 r = -EFAULT;
515a0127 3259 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n))
914ebccd 3260 goto out;
914ebccd
TY		 3261 } else {
3262 r = -EFAULT;
3263 if (clear_user(log->dirty_bitmap, n))
3264 goto out;
5bb064dc 3265 }
b050b015 3266
5bb064dc
ZX		 3267 r = 0;
3268out:
79fac95e 3269 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3270 return r;
3271}
3272
1fe779f8
CO		 3273long kvm_arch_vm_ioctl(struct file *filp,
3274 unsigned int ioctl, unsigned long arg)
3275{
3276 struct kvm *kvm = filp->private_data;
3277 void __user *argp = (void __user *)arg;
367e1319 3278 int r = -ENOTTY;
f0d66275
DH		 3279 /*
3280 * This union makes it completely explicit to gcc-3.x
3281 * that these two variables' stack usage should be
3282 * combined, not added together.
3283 */
3284 union {
3285 struct kvm_pit_state ps;
e9f42757 3286 struct kvm_pit_state2 ps2;
c5ff41ce 3287 struct kvm_pit_config pit_config;
f0d66275 3288 } u;
1fe779f8
CO		 3289
3290 switch (ioctl) {
3291 case KVM_SET_TSS_ADDR:
3292 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3293 if (r < 0)
3294 goto out;
3295 break;
b927a3ce
SY		 3296 case KVM_SET_IDENTITY_MAP_ADDR: {
3297 u64 ident_addr;
3298
3299 r = -EFAULT;
3300 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3301 goto out;
3302 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3303 if (r < 0)
3304 goto out;
3305 break;
3306 }
1fe779f8
CO		 3307 case KVM_SET_NR_MMU_PAGES:
3308 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3309 if (r)
3310 goto out;
3311 break;
3312 case KVM_GET_NR_MMU_PAGES:
3313 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3314 break;
3ddea128
MT		 3315 case KVM_CREATE_IRQCHIP: {
3316 struct kvm_pic *vpic;
3317
3318 mutex_lock(&kvm->lock);
3319 r = -EEXIST;
3320 if (kvm->arch.vpic)
3321 goto create_irqchip_unlock;
1fe779f8 3322 r = -ENOMEM;
3ddea128
MT		 3323 vpic = kvm_create_pic(kvm);
3324 if (vpic) {
1fe779f8
CO		 3325 r = kvm_ioapic_init(kvm);
3326 if (r) {
175504cd 3327 mutex_lock(&kvm->slots_lock);
72bb2fcd
WY		 3328 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3329 &vpic->dev);
175504cd 3330 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3331 kfree(vpic);
3332 goto create_irqchip_unlock;
1fe779f8
CO		 3333 }
3334 } else
3ddea128
MT		 3335 goto create_irqchip_unlock;
3336 smp_wmb();
3337 kvm->arch.vpic = vpic;
3338 smp_wmb();
399ec807
AK		 3339 r = kvm_setup_default_irq_routing(kvm);
3340 if (r) {
175504cd 3341 mutex_lock(&kvm->slots_lock);
3ddea128 3342 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3343 kvm_ioapic_destroy(kvm);
3344 kvm_destroy_pic(kvm);
3ddea128 3345 mutex_unlock(&kvm->irq_lock);
175504cd 3346 mutex_unlock(&kvm->slots_lock);
399ec807 3347 }
3ddea128
MT		 3348 create_irqchip_unlock:
3349 mutex_unlock(&kvm->lock);
1fe779f8 3350 break;
3ddea128 3351 }
7837699f 3352 case KVM_CREATE_PIT:
c5ff41ce
JK		 3353 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3354 goto create_pit;
3355 case KVM_CREATE_PIT2:
3356 r = -EFAULT;
3357 if (copy_from_user(&u.pit_config, argp,
3358 sizeof(struct kvm_pit_config)))
3359 goto out;
3360 create_pit:
79fac95e 3361 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3362 r = -EEXIST;
3363 if (kvm->arch.vpit)
3364 goto create_pit_unlock;
7837699f 3365 r = -ENOMEM;
c5ff41ce 3366 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3367 if (kvm->arch.vpit)
3368 r = 0;
269e05e4 3369 create_pit_unlock:
79fac95e 3370 mutex_unlock(&kvm->slots_lock);
7837699f 3371 break;
4925663a 3372 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 3373 case KVM_IRQ_LINE: {
3374 struct kvm_irq_level irq_event;
3375
3376 r = -EFAULT;
3377 if (copy_from_user(&irq_event, argp, sizeof irq_event))
3378 goto out;
160d2f6c 3379 r = -ENXIO;
1fe779f8 3380 if (irqchip_in_kernel(kvm)) {
4925663a 3381 __s32 status;
4925663a
GN		 3382 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3383 irq_event.irq, irq_event.level);
4925663a 3384 if (ioctl == KVM_IRQ_LINE_STATUS) {
160d2f6c 3385 r = -EFAULT;
4925663a
GN		 3386 irq_event.status = status;
3387 if (copy_to_user(argp, &irq_event,
3388 sizeof irq_event))
3389 goto out;
3390 }
1fe779f8
CO		 3391 r = 0;
3392 }
3393 break;
3394 }
3395 case KVM_GET_IRQCHIP: {
3396 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3397 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3398
f0d66275
DH		 3399 r = -ENOMEM;
3400 if (!chip)
1fe779f8 3401 goto out;
f0d66275
DH		 3402 r = -EFAULT;
3403 if (copy_from_user(chip, argp, sizeof *chip))
3404 goto get_irqchip_out;
1fe779f8
CO		 3405 r = -ENXIO;
3406 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3407 goto get_irqchip_out;
3408 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3409 if (r)
f0d66275 3410 goto get_irqchip_out;
1fe779f8 3411 r = -EFAULT;
f0d66275
DH		 3412 if (copy_to_user(argp, chip, sizeof *chip))
3413 goto get_irqchip_out;
1fe779f8 3414 r = 0;
f0d66275
DH		 3415 get_irqchip_out:
3416 kfree(chip);
3417 if (r)
3418 goto out;
1fe779f8
CO		 3419 break;
3420 }
3421 case KVM_SET_IRQCHIP: {
3422 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3423 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3424
f0d66275
DH		 3425 r = -ENOMEM;
3426 if (!chip)
1fe779f8 3427 goto out;
f0d66275
DH		 3428 r = -EFAULT;
3429 if (copy_from_user(chip, argp, sizeof *chip))
3430 goto set_irqchip_out;
1fe779f8
CO		 3431 r = -ENXIO;
3432 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3433 goto set_irqchip_out;
3434 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3435 if (r)
f0d66275 3436 goto set_irqchip_out;
1fe779f8 3437 r = 0;
f0d66275
DH		 3438 set_irqchip_out:
3439 kfree(chip);
3440 if (r)
3441 goto out;
1fe779f8
CO		 3442 break;
3443 }
e0f63cb9 3444 case KVM_GET_PIT: {
e0f63cb9 3445 r = -EFAULT;
f0d66275 3446 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3447 goto out;
3448 r = -ENXIO;
3449 if (!kvm->arch.vpit)
3450 goto out;
f0d66275 3451 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3452 if (r)
3453 goto out;
3454 r = -EFAULT;
f0d66275 3455 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3456 goto out;
3457 r = 0;
3458 break;
3459 }
3460 case KVM_SET_PIT: {
e0f63cb9 3461 r = -EFAULT;
f0d66275 3462 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3463 goto out;
3464 r = -ENXIO;
3465 if (!kvm->arch.vpit)
3466 goto out;
f0d66275 3467 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3468 if (r)
3469 goto out;
3470 r = 0;
3471 break;
3472 }
e9f42757
BK		 3473 case KVM_GET_PIT2: {
3474 r = -ENXIO;
3475 if (!kvm->arch.vpit)
3476 goto out;
3477 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3478 if (r)
3479 goto out;
3480 r = -EFAULT;
3481 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3482 goto out;
3483 r = 0;
3484 break;
3485 }
3486 case KVM_SET_PIT2: {
3487 r = -EFAULT;
3488 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3489 goto out;
3490 r = -ENXIO;
3491 if (!kvm->arch.vpit)
3492 goto out;
3493 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3494 if (r)
3495 goto out;
3496 r = 0;
3497 break;
3498 }
52d939a0
MT		 3499 case KVM_REINJECT_CONTROL: {
3500 struct kvm_reinject_control control;
3501 r = -EFAULT;
3502 if (copy_from_user(&control, argp, sizeof(control)))
3503 goto out;
3504 r = kvm_vm_ioctl_reinject(kvm, &control);
3505 if (r)
3506 goto out;
3507 r = 0;
3508 break;
3509 }
ffde22ac
ES		 3510 case KVM_XEN_HVM_CONFIG: {
3511 r = -EFAULT;
3512 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3513 sizeof(struct kvm_xen_hvm_config)))
3514 goto out;
3515 r = -EINVAL;
3516 if (kvm->arch.xen_hvm_config.flags)
3517 goto out;
3518 r = 0;
3519 break;
3520 }
afbcf7ab 3521 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3522 struct kvm_clock_data user_ns;
3523 u64 now_ns;
3524 s64 delta;
3525
3526 r = -EFAULT;
3527 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3528 goto out;
3529
3530 r = -EINVAL;
3531 if (user_ns.flags)
3532 goto out;
3533
3534 r = 0;
395c6b0a 3535 local_irq_disable();
759379dd 3536 now_ns = get_kernel_ns();
afbcf7ab 3537 delta = user_ns.clock - now_ns;
395c6b0a 3538 local_irq_enable();
afbcf7ab
GC		 3539 kvm->arch.kvmclock_offset = delta;
3540 break;
3541 }
3542 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3543 struct kvm_clock_data user_ns;
3544 u64 now_ns;
3545
395c6b0a 3546 local_irq_disable();
759379dd 3547 now_ns = get_kernel_ns();
afbcf7ab 3548 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3549 local_irq_enable();
afbcf7ab 3550 user_ns.flags = 0;
97e69aa6 3551 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3552
3553 r = -EFAULT;
3554 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3555 goto out;
3556 r = 0;
3557 break;
3558 }
3559
1fe779f8
CO		 3560 default:
3561 ;
3562 }
3563out:
3564 return r;
3565}
3566
a16b043c 3567static void kvm_init_msr_list(void)
043405e1
CO		 3568{
3569 u32 dummy[2];
3570 unsigned i, j;
3571
e3267cbb
GC		 3572 /* skip the first msrs in the list. KVM-specific */
3573 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3574 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3575 continue;
3576 if (j < i)
3577 msrs_to_save[j] = msrs_to_save[i];
3578 j++;
3579 }
3580 num_msrs_to_save = j;
3581}
3582
bda9020e
MT		 3583static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3584 const void *v)
bbd9b64e 3585{
70252a10
AK		 3586 int handled = 0;
3587 int n;
3588
3589 do {
3590 n = min(len, 8);
3591 if (!(vcpu->arch.apic &&
3592 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3593 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3594 break;
3595 handled += n;
3596 addr += n;
3597 len -= n;
3598 v += n;
3599 } while (len);
bbd9b64e 3600
70252a10 3601 return handled;
bbd9b64e
CO		 3602}
3603
bda9020e 3604static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3605{
70252a10
AK		 3606 int handled = 0;
3607 int n;
3608
3609 do {
3610 n = min(len, 8);
3611 if (!(vcpu->arch.apic &&
3612 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3613 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3614 break;
3615 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3616 handled += n;
3617 addr += n;
3618 len -= n;
3619 v += n;
3620 } while (len);
bbd9b64e 3621
70252a10 3622 return handled;
bbd9b64e
CO		 3623}
3624
2dafc6c2
GN		 3625static void kvm_set_segment(struct kvm_vcpu *vcpu,
3626 struct kvm_segment *var, int seg)
3627{
3628 kvm_x86_ops->set_segment(vcpu, var, seg);
3629}
3630
3631void kvm_get_segment(struct kvm_vcpu *vcpu,
3632 struct kvm_segment *var, int seg)
3633{
3634 kvm_x86_ops->get_segment(vcpu, var, seg);
3635}
3636
c30a358d
JR		 3637static gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3638{
3639 return gpa;
3640}
3641
02f59dc9
JR		 3642static gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3643{
3644 gpa_t t_gpa;
ab9ae313 3645 struct x86_exception exception;
02f59dc9
JR		 3646
3647 BUG_ON(!mmu_is_nested(vcpu));
3648
3649 /* NPT walks are always user-walks */
3650 access |= PFERR_USER_MASK;
ab9ae313 3651 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
02f59dc9
JR		 3652
3653 return t_gpa;
3654}
3655
ab9ae313
AK		 3656gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3657 struct x86_exception *exception)
1871c602
GN		 3658{
3659 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 3660 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3661}
3662
ab9ae313
AK		 3663 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3664 struct x86_exception *exception)
1871c602
GN		 3665{
3666 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3667 access |= PFERR_FETCH_MASK;
ab9ae313 3668 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3669}
3670
ab9ae313
AK		 3671gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3672 struct x86_exception *exception)
1871c602
GN		 3673{
3674 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3675 access |= PFERR_WRITE_MASK;
ab9ae313 3676 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3677}
3678
3679/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 3680gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3681 struct x86_exception *exception)
1871c602 3682{
ab9ae313 3683 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 3684}
3685
3686static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3687 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 3688 struct x86_exception *exception)
bbd9b64e
CO		 3689{
3690 void *data = val;
10589a46 3691 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3692
3693 while (bytes) {
14dfe855 3694 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 3695 exception);
bbd9b64e 3696 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3697 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3698 int ret;
3699
bcc55cba 3700 if (gpa == UNMAPPED_GVA)
ab9ae313 3701 return X86EMUL_PROPAGATE_FAULT;
77c2002e 3702 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3703 if (ret < 0) {
c3cd7ffa 3704 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3705 goto out;
3706 }
bbd9b64e 3707
77c2002e
IE		 3708 bytes -= toread;
3709 data += toread;
3710 addr += toread;
bbd9b64e 3711 }
10589a46 3712out:
10589a46 3713 return r;
bbd9b64e 3714}
77c2002e 3715
1871c602
GN		 3716/* used for instruction fetching */
3717static int kvm_fetch_guest_virt(gva_t addr, void *val, unsigned int bytes,
bcc55cba
AK		 3718 struct kvm_vcpu *vcpu,
3719 struct x86_exception *exception)
1871c602
GN		 3720{
3721 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3722 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
bcc55cba
AK		 3723 access | PFERR_FETCH_MASK,
3724 exception);
1871c602
GN		 3725}
3726
3727static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
bcc55cba
AK		 3728 struct kvm_vcpu *vcpu,
3729 struct x86_exception *exception)
1871c602
GN		 3730{
3731 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3732 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 3733 exception);
1871c602
GN		 3734}
3735
3736static int kvm_read_guest_virt_system(gva_t addr, void *val, unsigned int bytes,
bcc55cba
AK		 3737 struct kvm_vcpu *vcpu,
3738 struct x86_exception *exception)
1871c602 3739{
bcc55cba 3740 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 3741}
3742
7972995b 3743static int kvm_write_guest_virt_system(gva_t addr, void *val,
2dafc6c2 3744 unsigned int bytes,
7972995b 3745 struct kvm_vcpu *vcpu,
bcc55cba 3746 struct x86_exception *exception)
77c2002e
IE		 3747{
3748 void *data = val;
3749 int r = X86EMUL_CONTINUE;
3750
3751 while (bytes) {
14dfe855
JR		 3752 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3753 PFERR_WRITE_MASK,
ab9ae313 3754 exception);
77c2002e
IE		 3755 unsigned offset = addr & (PAGE_SIZE-1);
3756 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3757 int ret;
3758
bcc55cba 3759 if (gpa == UNMAPPED_GVA)
ab9ae313 3760 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 3761 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3762 if (ret < 0) {
c3cd7ffa 3763 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 3764 goto out;
3765 }
3766
3767 bytes -= towrite;
3768 data += towrite;
3769 addr += towrite;
3770 }
3771out:
3772 return r;
3773}
3774
bbd9b64e
CO		 3775static int emulator_read_emulated(unsigned long addr,
3776 void *val,
3777 unsigned int bytes,
bcc55cba 3778 struct x86_exception *exception,
bbd9b64e
CO		 3779 struct kvm_vcpu *vcpu)
3780{
bbd9b64e 3781 gpa_t gpa;
70252a10 3782 int handled;
bbd9b64e
CO		 3783
3784 if (vcpu->mmio_read_completed) {
3785 memcpy(val, vcpu->mmio_data, bytes);
aec51dc4
AK		 3786 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3787 vcpu->mmio_phys_addr, *(u64 *)val);
bbd9b64e
CO		 3788 vcpu->mmio_read_completed = 0;
3789 return X86EMUL_CONTINUE;
3790 }
3791
ab9ae313 3792 gpa = kvm_mmu_gva_to_gpa_read(vcpu, addr, exception);
1871c602 3793
8fe681e9 3794 if (gpa == UNMAPPED_GVA)
1871c602 3795 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3796
3797 /* For APIC access vmexit */
3798 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3799 goto mmio;
3800
bcc55cba
AK		 3801 if (kvm_read_guest_virt(addr, val, bytes, vcpu, exception)
3802 == X86EMUL_CONTINUE)
bbd9b64e 3803 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3804
3805mmio:
3806 /*
3807 * Is this MMIO handled locally?
3808 */
70252a10
AK		 3809 handled = vcpu_mmio_read(vcpu, gpa, bytes, val);
3810
3811 if (handled == bytes)
bbd9b64e 3812 return X86EMUL_CONTINUE;
70252a10
AK		 3813
3814 gpa += handled;
3815 bytes -= handled;
3816 val += handled;
aec51dc4
AK		 3817
3818 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
bbd9b64e
CO		 3819
3820 vcpu->mmio_needed = 1;
411c35b7
GN		 3821 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3822 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
cef4dea0
AK		 3823 vcpu->mmio_size = bytes;
3824 vcpu->run->mmio.len = min(vcpu->mmio_size, 8);
411c35b7 3825 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 0;
cef4dea0 3826 vcpu->mmio_index = 0;
bbd9b64e 3827
c3cd7ffa 3828 return X86EMUL_IO_NEEDED;
bbd9b64e
CO		 3829}
3830
3200f405 3831int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 3832 const void *val, int bytes)
bbd9b64e
CO		 3833{
3834 int ret;
3835
3836 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3837 if (ret < 0)
bbd9b64e 3838 return 0;
ad218f85 3839 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 3840 return 1;
3841}
3842
3843static int emulator_write_emulated_onepage(unsigned long addr,
3844 const void *val,
3845 unsigned int bytes,
bcc55cba 3846 struct x86_exception *exception,
bbd9b64e
CO		 3847 struct kvm_vcpu *vcpu)
3848{
10589a46 3849 gpa_t gpa;
70252a10 3850 int handled;
10589a46 3851
ab9ae313 3852 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, exception);
bbd9b64e 3853
8fe681e9 3854 if (gpa == UNMAPPED_GVA)
bbd9b64e 3855 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3856
3857 /* For APIC access vmexit */
3858 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3859 goto mmio;
3860
3861 if (emulator_write_phys(vcpu, gpa, val, bytes))
3862 return X86EMUL_CONTINUE;
3863
3864mmio:
aec51dc4 3865 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3866 /*
3867 * Is this MMIO handled locally?
3868 */
70252a10
AK		 3869 handled = vcpu_mmio_write(vcpu, gpa, bytes, val);
3870 if (handled == bytes)
bbd9b64e 3871 return X86EMUL_CONTINUE;
bbd9b64e 3872
70252a10
AK		 3873 gpa += handled;
3874 bytes -= handled;
3875 val += handled;
3876
bbd9b64e 3877 vcpu->mmio_needed = 1;
cef4dea0 3878 memcpy(vcpu->mmio_data, val, bytes);
411c35b7
GN		 3879 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3880 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
cef4dea0
AK		 3881 vcpu->mmio_size = bytes;
3882 vcpu->run->mmio.len = min(vcpu->mmio_size, 8);
411c35b7 3883 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 1;
cef4dea0
AK		 3884 memcpy(vcpu->run->mmio.data, vcpu->mmio_data, 8);
3885 vcpu->mmio_index = 0;
bbd9b64e
CO		 3886
3887 return X86EMUL_CONTINUE;
3888}
3889
3890int emulator_write_emulated(unsigned long addr,
8f6abd06
GN		 3891 const void *val,
3892 unsigned int bytes,
bcc55cba 3893 struct x86_exception *exception,
8f6abd06 3894 struct kvm_vcpu *vcpu)
bbd9b64e
CO		 3895{
3896 /* Crossing a page boundary? */
3897 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3898 int rc, now;
3899
3900 now = -addr & ~PAGE_MASK;
bcc55cba 3901 rc = emulator_write_emulated_onepage(addr, val, now, exception,
8fe681e9 3902 vcpu);
bbd9b64e
CO		 3903 if (rc != X86EMUL_CONTINUE)
3904 return rc;
3905 addr += now;
3906 val += now;
3907 bytes -= now;
3908 }
bcc55cba 3909 return emulator_write_emulated_onepage(addr, val, bytes, exception,
8fe681e9 3910 vcpu);
bbd9b64e 3911}
bbd9b64e 3912
daea3e73
AK		 3913#define CMPXCHG_TYPE(t, ptr, old, new) \
3914 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
3915
3916#ifdef CONFIG_X86_64
3917# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
3918#else
3919# define CMPXCHG64(ptr, old, new) \
9749a6c0 3920 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 3921#endif
3922
bbd9b64e
CO		 3923static int emulator_cmpxchg_emulated(unsigned long addr,
3924 const void *old,
3925 const void *new,
3926 unsigned int bytes,
bcc55cba 3927 struct x86_exception *exception,
bbd9b64e
CO		 3928 struct kvm_vcpu *vcpu)
3929{
daea3e73
AK		 3930 gpa_t gpa;
3931 struct page *page;
3932 char *kaddr;
3933 bool exchanged;
2bacc55c 3934
daea3e73
AK		 3935 /* guests cmpxchg8b have to be emulated atomically */
3936 if (bytes > 8 || (bytes & (bytes - 1)))
3937 goto emul_write;
10589a46 3938
daea3e73 3939 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 3940
daea3e73
AK		 3941 if (gpa == UNMAPPED_GVA ||
3942 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3943 goto emul_write;
2bacc55c 3944
daea3e73
AK		 3945 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3946 goto emul_write;
72dc67a6 3947
daea3e73 3948 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
c19b8bd6
WY		 3949 if (is_error_page(page)) {
3950 kvm_release_page_clean(page);
3951 goto emul_write;
3952 }
72dc67a6 3953
daea3e73
AK		 3954 kaddr = kmap_atomic(page, KM_USER0);
3955 kaddr += offset_in_page(gpa);
3956 switch (bytes) {
3957 case 1:
3958 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
3959 break;
3960 case 2:
3961 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
3962 break;
3963 case 4:
3964 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
3965 break;
3966 case 8:
3967 exchanged = CMPXCHG64(kaddr, old, new);
3968 break;
3969 default:
3970 BUG();
2bacc55c 3971 }
daea3e73
AK		 3972 kunmap_atomic(kaddr, KM_USER0);
3973 kvm_release_page_dirty(page);
3974
3975 if (!exchanged)
3976 return X86EMUL_CMPXCHG_FAILED;
3977
8f6abd06
GN		 3978 kvm_mmu_pte_write(vcpu, gpa, new, bytes, 1);
3979
3980 return X86EMUL_CONTINUE;
4a5f48f6 3981
3200f405 3982emul_write:
daea3e73 3983 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 3984
bcc55cba 3985 return emulator_write_emulated(addr, new, bytes, exception, vcpu);
bbd9b64e
CO		 3986}
3987
cf8f70bf
GN		 3988static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
3989{
3990 /* TODO: String I/O for in kernel device */
3991 int r;
3992
3993 if (vcpu->arch.pio.in)
3994 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
3995 vcpu->arch.pio.size, pd);
3996 else
3997 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3998 vcpu->arch.pio.port, vcpu->arch.pio.size,
3999 pd);
4000 return r;
4001}
4002
4003
4004static int emulator_pio_in_emulated(int size, unsigned short port, void *val,
4005 unsigned int count, struct kvm_vcpu *vcpu)
4006{
7972995b 4007 if (vcpu->arch.pio.count)
cf8f70bf
GN		 4008 goto data_avail;
4009
61cfab2e 4010 trace_kvm_pio(0, port, size, count);
cf8f70bf
GN		 4011
4012 vcpu->arch.pio.port = port;
4013 vcpu->arch.pio.in = 1;
7972995b 4014 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4015 vcpu->arch.pio.size = size;
4016
4017 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4018 data_avail:
4019 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 4020 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4021 return 1;
4022 }
4023
4024 vcpu->run->exit_reason = KVM_EXIT_IO;
4025 vcpu->run->io.direction = KVM_EXIT_IO_IN;
4026 vcpu->run->io.size = size;
4027 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4028 vcpu->run->io.count = count;
4029 vcpu->run->io.port = port;
4030
4031 return 0;
4032}
4033
4034static int emulator_pio_out_emulated(int size, unsigned short port,
4035 const void *val, unsigned int count,
4036 struct kvm_vcpu *vcpu)
4037{
61cfab2e 4038 trace_kvm_pio(1, port, size, count);
cf8f70bf
GN		 4039
4040 vcpu->arch.pio.port = port;
4041 vcpu->arch.pio.in = 0;
7972995b 4042 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4043 vcpu->arch.pio.size = size;
4044
4045 memcpy(vcpu->arch.pio_data, val, size * count);
4046
4047 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4048 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4049 return 1;
4050 }
4051
4052 vcpu->run->exit_reason = KVM_EXIT_IO;
4053 vcpu->run->io.direction = KVM_EXIT_IO_OUT;
4054 vcpu->run->io.size = size;
4055 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4056 vcpu->run->io.count = count;
4057 vcpu->run->io.port = port;
4058
4059 return 0;
4060}
4061
bbd9b64e
CO		 4062static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4063{
4064 return kvm_x86_ops->get_segment_base(vcpu, seg);
4065}
4066
4067int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
4068{
a7052897 4069 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 4070 return X86EMUL_CONTINUE;
4071}
4072
f5f48ee1
SY		 4073int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4074{
4075 if (!need_emulate_wbinvd(vcpu))
4076 return X86EMUL_CONTINUE;
4077
4078 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4079 int cpu = get_cpu();
4080
4081 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4082 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4083 wbinvd_ipi, NULL, 1);
2eec7343 4084 put_cpu();
f5f48ee1 4085 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4086 } else
4087 wbinvd();
f5f48ee1
SY		 4088 return X86EMUL_CONTINUE;
4089}
4090EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4091
bbd9b64e
CO		 4092int emulate_clts(struct kvm_vcpu *vcpu)
4093{
4d4ec087 4094 kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
6b52d186 4095 kvm_x86_ops->fpu_activate(vcpu);
bbd9b64e
CO		 4096 return X86EMUL_CONTINUE;
4097}
4098
35aa5375 4099int emulator_get_dr(int dr, unsigned long *dest, struct kvm_vcpu *vcpu)
bbd9b64e 4100{
338dbc97 4101 return _kvm_get_dr(vcpu, dr, dest);
bbd9b64e
CO		 4102}
4103
35aa5375 4104int emulator_set_dr(int dr, unsigned long value, struct kvm_vcpu *vcpu)
bbd9b64e 4105{
338dbc97
GN		 4106
4107 return __kvm_set_dr(vcpu, dr, value);
bbd9b64e
CO		 4108}
4109
52a46617 4110static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4111{
52a46617 4112 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4113}
4114
52a46617 4115static unsigned long emulator_get_cr(int cr, struct kvm_vcpu *vcpu)
bbd9b64e 4116{
52a46617
GN		 4117 unsigned long value;
4118
4119 switch (cr) {
4120 case 0:
4121 value = kvm_read_cr0(vcpu);
4122 break;
4123 case 2:
4124 value = vcpu->arch.cr2;
4125 break;
4126 case 3:
9f8fe504 4127 value = kvm_read_cr3(vcpu);
52a46617
GN		 4128 break;
4129 case 4:
4130 value = kvm_read_cr4(vcpu);
4131 break;
4132 case 8:
4133 value = kvm_get_cr8(vcpu);
4134 break;
4135 default:
4136 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
4137 return 0;
4138 }
4139
4140 return value;
4141}
4142
0f12244f 4143static int emulator_set_cr(int cr, unsigned long val, struct kvm_vcpu *vcpu)
52a46617 4144{
0f12244f
GN		 4145 int res = 0;
4146
52a46617
GN		 4147 switch (cr) {
4148 case 0:
49a9b07e 4149 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4150 break;
4151 case 2:
4152 vcpu->arch.cr2 = val;
4153 break;
4154 case 3:
2390218b 4155 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4156 break;
4157 case 4:
a83b29c6 4158 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4159 break;
4160 case 8:
eea1cff9 4161 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4162 break;
4163 default:
4164 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
0f12244f 4165 res = -1;
52a46617 4166 }
0f12244f
GN		 4167
4168 return res;
52a46617
GN		 4169}
4170
9c537244
GN		 4171static int emulator_get_cpl(struct kvm_vcpu *vcpu)
4172{
4173 return kvm_x86_ops->get_cpl(vcpu);
4174}
4175
2dafc6c2
GN		 4176static void emulator_get_gdt(struct desc_ptr *dt, struct kvm_vcpu *vcpu)
4177{
4178 kvm_x86_ops->get_gdt(vcpu, dt);
4179}
4180
160ce1f1
MG		 4181static void emulator_get_idt(struct desc_ptr *dt, struct kvm_vcpu *vcpu)
4182{
4183 kvm_x86_ops->get_idt(vcpu, dt);
4184}
4185
5951c442
GN		 4186static unsigned long emulator_get_cached_segment_base(int seg,
4187 struct kvm_vcpu *vcpu)
4188{
4189 return get_segment_base(vcpu, seg);
4190}
4191
5601d05b
GN		 4192static bool emulator_get_cached_descriptor(struct desc_struct *desc, u32 *base3,
4193 int seg, struct kvm_vcpu *vcpu)
2dafc6c2
GN		 4194{
4195 struct kvm_segment var;
4196
4197 kvm_get_segment(vcpu, &var, seg);
4198
4199 if (var.unusable)
4200 return false;
4201
4202 if (var.g)
4203 var.limit >>= 12;
4204 set_desc_limit(desc, var.limit);
4205 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4206#ifdef CONFIG_X86_64
4207 if (base3)
4208 *base3 = var.base >> 32;
4209#endif
2dafc6c2
GN		 4210 desc->type = var.type;
4211 desc->s = var.s;
4212 desc->dpl = var.dpl;
4213 desc->p = var.present;
4214 desc->avl = var.avl;
4215 desc->l = var.l;
4216 desc->d = var.db;
4217 desc->g = var.g;
4218
4219 return true;
4220}
4221
5601d05b
GN		 4222static void emulator_set_cached_descriptor(struct desc_struct *desc, u32 base3,
4223 int seg, struct kvm_vcpu *vcpu)
2dafc6c2
GN		 4224{
4225 struct kvm_segment var;
4226
4227 /* needed to preserve selector */
4228 kvm_get_segment(vcpu, &var, seg);
4229
4230 var.base = get_desc_base(desc);
5601d05b
GN		 4231#ifdef CONFIG_X86_64
4232 var.base |= ((u64)base3) << 32;
4233#endif
2dafc6c2
GN		 4234 var.limit = get_desc_limit(desc);
4235 if (desc->g)
4236 var.limit = (var.limit << 12) | 0xfff;
4237 var.type = desc->type;
4238 var.present = desc->p;
4239 var.dpl = desc->dpl;
4240 var.db = desc->d;
4241 var.s = desc->s;
4242 var.l = desc->l;
4243 var.g = desc->g;
4244 var.avl = desc->avl;
4245 var.present = desc->p;
4246 var.unusable = !var.present;
4247 var.padding = 0;
4248
4249 kvm_set_segment(vcpu, &var, seg);
4250 return;
4251}
4252
4253static u16 emulator_get_segment_selector(int seg, struct kvm_vcpu *vcpu)
4254{
4255 struct kvm_segment kvm_seg;
4256
4257 kvm_get_segment(vcpu, &kvm_seg, seg);
4258 return kvm_seg.selector;
4259}
4260
4261static void emulator_set_segment_selector(u16 sel, int seg,
4262 struct kvm_vcpu *vcpu)
4263{
4264 struct kvm_segment kvm_seg;
4265
4266 kvm_get_segment(vcpu, &kvm_seg, seg);
4267 kvm_seg.selector = sel;
4268 kvm_set_segment(vcpu, &kvm_seg, seg);
4269}
4270
5037f6f3
AK		 4271static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4272{
4273 preempt_disable();
4274 kvm_load_guest_fpu(ctxt->vcpu);
4275 /*
4276 * CR0.TS may reference the host fpu state, not the guest fpu state,
4277 * so it may be clear at this point.
4278 */
4279 clts();
4280}
4281
4282static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4283{
4284 preempt_enable();
4285}
4286
8a76d7f2
JR		 4287static int emulator_intercept(struct kvm_vcpu *vcpu,
4288 struct x86_instruction_info *info,
c4f035c6
AK		 4289 enum x86_intercept_stage stage)
4290{
8a76d7f2 4291 return kvm_x86_ops->check_intercept(vcpu, info, stage);
c4f035c6
AK		 4292}
4293
14af3f3c 4294static struct x86_emulate_ops emulate_ops = {
1871c602 4295 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4296 .write_std = kvm_write_guest_virt_system,
1871c602 4297 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4298 .read_emulated = emulator_read_emulated,
4299 .write_emulated = emulator_write_emulated,
4300 .cmpxchg_emulated = emulator_cmpxchg_emulated,
cf8f70bf
GN		 4301 .pio_in_emulated = emulator_pio_in_emulated,
4302 .pio_out_emulated = emulator_pio_out_emulated,
2dafc6c2
GN		 4303 .get_cached_descriptor = emulator_get_cached_descriptor,
4304 .set_cached_descriptor = emulator_set_cached_descriptor,
4305 .get_segment_selector = emulator_get_segment_selector,
4306 .set_segment_selector = emulator_set_segment_selector,
5951c442 4307 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4308 .get_gdt = emulator_get_gdt,
160ce1f1 4309 .get_idt = emulator_get_idt,
52a46617
GN		 4310 .get_cr = emulator_get_cr,
4311 .set_cr = emulator_set_cr,
9c537244 4312 .cpl = emulator_get_cpl,
35aa5375
GN		 4313 .get_dr = emulator_get_dr,
4314 .set_dr = emulator_set_dr,
3fb1b5db
GN		 4315 .set_msr = kvm_set_msr,
4316 .get_msr = kvm_get_msr,
5037f6f3
AK		 4317 .get_fpu = emulator_get_fpu,
4318 .put_fpu = emulator_put_fpu,
c4f035c6 4319 .intercept = emulator_intercept,
bbd9b64e
CO		 4320};
4321
5fdbf976
MT		 4322static void cache_all_regs(struct kvm_vcpu *vcpu)
4323{
4324 kvm_register_read(vcpu, VCPU_REGS_RAX);
4325 kvm_register_read(vcpu, VCPU_REGS_RSP);
4326 kvm_register_read(vcpu, VCPU_REGS_RIP);
4327 vcpu->arch.regs_dirty = ~0;
4328}
4329
95cb2295
GN		 4330static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4331{
4332 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4333 /*
4334 * an sti; sti; sequence only disable interrupts for the first
4335 * instruction. So, if the last instruction, be it emulated or
4336 * not, left the system with the INT_STI flag enabled, it
4337 * means that the last instruction is an sti. We should not
4338 * leave the flag on in this case. The same goes for mov ss
4339 */
4340 if (!(int_shadow & mask))
4341 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4342}
4343
54b8486f
GN		 4344static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4345{
4346 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4347 if (ctxt->exception.vector == PF_VECTOR)
6389ee94 4348 kvm_propagate_fault(vcpu, &ctxt->exception);
da9cb575
AK		 4349 else if (ctxt->exception.error_code_valid)
4350 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4351 ctxt->exception.error_code);
54b8486f 4352 else
da9cb575 4353 kvm_queue_exception(vcpu, ctxt->exception.vector);
54b8486f
GN		 4354}
4355
8ec4722d
MG		 4356static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4357{
4358 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
4359 int cs_db, cs_l;
4360
4361 cache_all_regs(vcpu);
4362
4363 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4364
4365 vcpu->arch.emulate_ctxt.vcpu = vcpu;
f6e78475 4366 vcpu->arch.emulate_ctxt.eflags = kvm_get_rflags(vcpu);
8ec4722d
MG		 4367 vcpu->arch.emulate_ctxt.eip = kvm_rip_read(vcpu);
4368 vcpu->arch.emulate_ctxt.mode =
4369 (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4370 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
4371 ? X86EMUL_MODE_VM86 : cs_l
4372 ? X86EMUL_MODE_PROT64 : cs_db
4373 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
c4f035c6 4374 vcpu->arch.emulate_ctxt.guest_mode = is_guest_mode(vcpu);
8ec4722d
MG		 4375 memset(c, 0, sizeof(struct decode_cache));
4376 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
4377}
4378
63995653
MG		 4379int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq)
4380{
4381 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
4382 int ret;
4383
4384 init_emulate_ctxt(vcpu);
4385
4386 vcpu->arch.emulate_ctxt.decode.op_bytes = 2;
4387 vcpu->arch.emulate_ctxt.decode.ad_bytes = 2;
4388 vcpu->arch.emulate_ctxt.decode.eip = vcpu->arch.emulate_ctxt.eip;
4389 ret = emulate_int_real(&vcpu->arch.emulate_ctxt, &emulate_ops, irq);
4390
4391 if (ret != X86EMUL_CONTINUE)
4392 return EMULATE_FAIL;
4393
4394 vcpu->arch.emulate_ctxt.eip = c->eip;
4395 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
4396 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
f6e78475 4397 kvm_set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
63995653
MG		 4398
4399 if (irq == NMI_VECTOR)
4400 vcpu->arch.nmi_pending = false;
4401 else
4402 vcpu->arch.interrupt.pending = false;
4403
4404 return EMULATE_DONE;
4405}
4406EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4407
6d77dbfc
GN		 4408static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4409{
fc3a9157
JR		 4410 int r = EMULATE_DONE;
4411
6d77dbfc
GN		 4412 ++vcpu->stat.insn_emulation_fail;
4413 trace_kvm_emulate_insn_failed(vcpu);
fc3a9157
JR		 4414 if (!is_guest_mode(vcpu)) {
4415 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4416 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4417 vcpu->run->internal.ndata = 0;
4418 r = EMULATE_FAIL;
4419 }
6d77dbfc 4420 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4421
4422 return r;
6d77dbfc
GN		 4423}
4424
a6f177ef
GN		 4425static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
4426{
4427 gpa_t gpa;
4428
68be0803
GN		 4429 if (tdp_enabled)
4430 return false;
4431
a6f177ef
GN		 4432 /*
4433 * if emulation was due to access to shadowed page table
4434 * and it failed try to unshadow page and re-entetr the
4435 * guest to let CPU execute the instruction.
4436 */
4437 if (kvm_mmu_unprotect_page_virt(vcpu, gva))
4438 return true;
4439
4440 gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
4441
4442 if (gpa == UNMAPPED_GVA)
4443 return true; /* let cpu generate fault */
4444
4445 if (!kvm_is_error_hva(gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT)))
4446 return true;
4447
4448 return false;
4449}
4450
51d8b661
AP		 4451int x86_emulate_instruction(struct kvm_vcpu *vcpu,
4452 unsigned long cr2,
dc25e89e
AP		 4453 int emulation_type,
4454 void *insn,
4455 int insn_len)
bbd9b64e 4456{
95cb2295 4457 int r;
4d2179e1 4458 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
bbd9b64e 4459
26eef70c 4460 kvm_clear_exception_queue(vcpu);
ad312c7c 4461 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976 4462 /*
56e82318 4463 * TODO: fix emulate.c to use guest_read/write_register
5fdbf976
MT		 4464 * instead of direct ->regs accesses, can save hundred cycles
4465 * on Intel for instructions that don't read/change RSP, for
4466 * for example.
4467 */
4468 cache_all_regs(vcpu);
bbd9b64e 4469
571008da 4470 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 4471 init_emulate_ctxt(vcpu);
95cb2295 4472 vcpu->arch.emulate_ctxt.interruptibility = 0;
da9cb575 4473 vcpu->arch.emulate_ctxt.have_exception = false;
4fc40f07 4474 vcpu->arch.emulate_ctxt.perm_ok = false;
bbd9b64e 4475
4005996e
AK		 4476 vcpu->arch.emulate_ctxt.only_vendor_specific_insn
4477 = emulation_type & EMULTYPE_TRAP_UD;
4478
dc25e89e 4479 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, insn, insn_len);
bbd9b64e 4480
e46479f8 4481 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 4482 ++vcpu->stat.insn_emulation;
bbd9b64e 4483 if (r) {
4005996e
AK		 4484 if (emulation_type & EMULTYPE_TRAP_UD)
4485 return EMULATE_FAIL;
a6f177ef 4486 if (reexecute_instruction(vcpu, cr2))
bbd9b64e 4487 return EMULATE_DONE;
6d77dbfc
GN		 4488 if (emulation_type & EMULTYPE_SKIP)
4489 return EMULATE_FAIL;
4490 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4491 }
4492 }
4493
ba8afb6b
GN		 4494 if (emulation_type & EMULTYPE_SKIP) {
4495 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
4496 return EMULATE_DONE;
4497 }
4498
4d2179e1
GN		 4499 /* this is needed for vmware backdor interface to work since it
4500 changes registers values during IO operation */
4501 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
4502
5cd21917 4503restart:
9aabc88f 4504 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt);
bbd9b64e 4505
775fde86
JR		 4506 if (r == EMULATION_INTERCEPTED)
4507 return EMULATE_DONE;
4508
d2ddd1c4 4509 if (r == EMULATION_FAILED) {
a6f177ef 4510 if (reexecute_instruction(vcpu, cr2))
c3cd7ffa
GN		 4511 return EMULATE_DONE;
4512
6d77dbfc 4513 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4514 }
4515
da9cb575 4516 if (vcpu->arch.emulate_ctxt.have_exception) {
54b8486f 4517 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 4518 r = EMULATE_DONE;
4519 } else if (vcpu->arch.pio.count) {
3457e419
GN		 4520 if (!vcpu->arch.pio.in)
4521 vcpu->arch.pio.count = 0;
e85d28f8 4522 r = EMULATE_DO_MMIO;
cef4dea0 4523 } else if (vcpu->mmio_needed)
e85d28f8 4524 r = EMULATE_DO_MMIO;
cef4dea0 4525 else if (r == EMULATION_RESTART)
5cd21917 4526 goto restart;
d2ddd1c4
GN		 4527 else
4528 r = EMULATE_DONE;
f850e2e6 4529
e85d28f8 4530 toggle_interruptibility(vcpu, vcpu->arch.emulate_ctxt.interruptibility);
f6e78475 4531 kvm_set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
3842d135 4532 kvm_make_request(KVM_REQ_EVENT, vcpu);
e85d28f8
GN		 4533 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
4534 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
4535
4536 return r;
de7d789a 4537}
51d8b661 4538EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 4539
cf8f70bf 4540int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 4541{
cf8f70bf
GN		 4542 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
4543 int ret = emulator_pio_out_emulated(size, port, &val, 1, vcpu);
4544 /* do not return to emulator after return from userspace */
7972995b 4545 vcpu->arch.pio.count = 0;
de7d789a
CO		 4546 return ret;
4547}
cf8f70bf 4548EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 4549
8cfdc000
ZA		 4550static void tsc_bad(void *info)
4551{
0a3aee0d 4552 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 4553}
4554
4555static void tsc_khz_changed(void *data)
c8076604 4556{
8cfdc000
ZA		 4557 struct cpufreq_freqs *freq = data;
4558 unsigned long khz = 0;
4559
4560 if (data)
4561 khz = freq->new;
4562 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4563 khz = cpufreq_quick_get(raw_smp_processor_id());
4564 if (!khz)
4565 khz = tsc_khz;
0a3aee0d 4566 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 4567}
4568
c8076604
GH		 4569static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4570 void *data)
4571{
4572 struct cpufreq_freqs *freq = data;
4573 struct kvm *kvm;
4574 struct kvm_vcpu *vcpu;
4575 int i, send_ipi = 0;
4576
8cfdc000
ZA		 4577 /*
4578 * We allow guests to temporarily run on slowing clocks,
4579 * provided we notify them after, or to run on accelerating
4580 * clocks, provided we notify them before. Thus time never
4581 * goes backwards.
4582 *
4583 * However, we have a problem. We can't atomically update
4584 * the frequency of a given CPU from this function; it is
4585 * merely a notifier, which can be called from any CPU.
4586 * Changing the TSC frequency at arbitrary points in time
4587 * requires a recomputation of local variables related to
4588 * the TSC for each VCPU. We must flag these local variables
4589 * to be updated and be sure the update takes place with the
4590 * new frequency before any guests proceed.
4591 *
4592 * Unfortunately, the combination of hotplug CPU and frequency
4593 * change creates an intractable locking scenario; the order
4594 * of when these callouts happen is undefined with respect to
4595 * CPU hotplug, and they can race with each other. As such,
4596 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
4597 * undefined; you can actually have a CPU frequency change take
4598 * place in between the computation of X and the setting of the
4599 * variable. To protect against this problem, all updates of
4600 * the per_cpu tsc_khz variable are done in an interrupt
4601 * protected IPI, and all callers wishing to update the value
4602 * must wait for a synchronous IPI to complete (which is trivial
4603 * if the caller is on the CPU already). This establishes the
4604 * necessary total order on variable updates.
4605 *
4606 * Note that because a guest time update may take place
4607 * anytime after the setting of the VCPU's request bit, the
4608 * correct TSC value must be set before the request. However,
4609 * to ensure the update actually makes it to any guest which
4610 * starts running in hardware virtualization between the set
4611 * and the acquisition of the spinlock, we must also ping the
4612 * CPU after setting the request bit.
4613 *
4614 */
4615
c8076604
GH		 4616 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
4617 return 0;
4618 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
4619 return 0;
8cfdc000
ZA		 4620
4621 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 4622
e935b837 4623 raw_spin_lock(&kvm_lock);
c8076604 4624 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 4625 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 4626 if (vcpu->cpu != freq->cpu)
4627 continue;
c285545f 4628 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 4629 if (vcpu->cpu != smp_processor_id())
8cfdc000 4630 send_ipi = 1;
c8076604
GH		 4631 }
4632 }
e935b837 4633 raw_spin_unlock(&kvm_lock);
c8076604
GH		 4634
4635 if (freq->old < freq->new && send_ipi) {
4636 /*
4637 * We upscale the frequency. Must make the guest
4638 * doesn't see old kvmclock values while running with
4639 * the new frequency, otherwise we risk the guest sees
4640 * time go backwards.
4641 *
4642 * In case we update the frequency for another cpu
4643 * (which might be in guest context) send an interrupt
4644 * to kick the cpu out of guest context. Next time
4645 * guest context is entered kvmclock will be updated,
4646 * so the guest will not see stale values.
4647 */
8cfdc000 4648 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 4649 }
4650 return 0;
4651}
4652
4653static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 4654 .notifier_call = kvmclock_cpufreq_notifier
4655};
4656
4657static int kvmclock_cpu_notifier(struct notifier_block *nfb,
4658 unsigned long action, void *hcpu)
4659{
4660 unsigned int cpu = (unsigned long)hcpu;
4661
4662 switch (action) {
4663 case CPU_ONLINE:
4664 case CPU_DOWN_FAILED:
4665 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4666 break;
4667 case CPU_DOWN_PREPARE:
4668 smp_call_function_single(cpu, tsc_bad, NULL, 1);
4669 break;
4670 }
4671 return NOTIFY_OK;
4672}
4673
4674static struct notifier_block kvmclock_cpu_notifier_block = {
4675 .notifier_call = kvmclock_cpu_notifier,
4676 .priority = -INT_MAX
c8076604
GH		 4677};
4678
b820cc0c
ZA		 4679static void kvm_timer_init(void)
4680{
4681 int cpu;
4682
c285545f 4683 max_tsc_khz = tsc_khz;
8cfdc000 4684 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 4685 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 4686#ifdef CONFIG_CPU_FREQ
4687 struct cpufreq_policy policy;
4688 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 4689 cpu = get_cpu();
4690 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 4691 if (policy.cpuinfo.max_freq)
4692 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 4693 put_cpu();
c285545f 4694#endif
b820cc0c
ZA		 4695 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4696 CPUFREQ_TRANSITION_NOTIFIER);
4697 }
c285545f 4698 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 4699 for_each_online_cpu(cpu)
4700 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 4701}
4702
ff9d07a0
ZY		 4703static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
4704
4705static int kvm_is_in_guest(void)
4706{
4707 return percpu_read(current_vcpu) != NULL;
4708}
4709
4710static int kvm_is_user_mode(void)
4711{
4712 int user_mode = 3;
dcf46b94 4713
ff9d07a0
ZY		 4714 if (percpu_read(current_vcpu))
4715 user_mode = kvm_x86_ops->get_cpl(percpu_read(current_vcpu));
dcf46b94 4716
ff9d07a0
ZY		 4717 return user_mode != 0;
4718}
4719
4720static unsigned long kvm_get_guest_ip(void)
4721{
4722 unsigned long ip = 0;
dcf46b94 4723
ff9d07a0
ZY		 4724 if (percpu_read(current_vcpu))
4725 ip = kvm_rip_read(percpu_read(current_vcpu));
dcf46b94 4726
ff9d07a0
ZY		 4727 return ip;
4728}
4729
4730static struct perf_guest_info_callbacks kvm_guest_cbs = {
4731 .is_in_guest = kvm_is_in_guest,
4732 .is_user_mode = kvm_is_user_mode,
4733 .get_guest_ip = kvm_get_guest_ip,
4734};
4735
4736void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4737{
4738 percpu_write(current_vcpu, vcpu);
4739}
4740EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4741
4742void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4743{
4744 percpu_write(current_vcpu, NULL);
4745}
4746EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4747
f8c16bba 4748int kvm_arch_init(void *opaque)
043405e1 4749{
b820cc0c 4750 int r;
f8c16bba
ZX		 4751 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4752
f8c16bba
ZX		 4753 if (kvm_x86_ops) {
4754 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 4755 r = -EEXIST;
4756 goto out;
f8c16bba
ZX		 4757 }
4758
4759 if (!ops->cpu_has_kvm_support()) {
4760 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 4761 r = -EOPNOTSUPP;
4762 goto out;
f8c16bba
ZX		 4763 }
4764 if (ops->disabled_by_bios()) {
4765 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 4766 r = -EOPNOTSUPP;
4767 goto out;
f8c16bba
ZX		 4768 }
4769
97db56ce
AK		 4770 r = kvm_mmu_module_init();
4771 if (r)
4772 goto out;
4773
4774 kvm_init_msr_list();
4775
f8c16bba 4776 kvm_x86_ops = ops;
56c6d28a 4777 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e 4778 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 4779 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 4780
b820cc0c 4781 kvm_timer_init();
c8076604 4782
ff9d07a0
ZY		 4783 perf_register_guest_info_callbacks(&kvm_guest_cbs);
4784
2acf923e
DC		 4785 if (cpu_has_xsave)
4786 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
4787
f8c16bba 4788 return 0;
56c6d28a
ZX		 4789
4790out:
56c6d28a 4791 return r;
043405e1 4792}
8776e519 4793
f8c16bba
ZX		 4794void kvm_arch_exit(void)
4795{
ff9d07a0
ZY		 4796 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4797
888d256e
JK		 4798 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4799 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4800 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 4801 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
f8c16bba 4802 kvm_x86_ops = NULL;
56c6d28a
ZX		 4803 kvm_mmu_module_exit();
4804}
f8c16bba 4805
8776e519
HB		 4806int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4807{
4808 ++vcpu->stat.halt_exits;
4809 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 4810 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 4811 return 1;
4812 } else {
4813 vcpu->run->exit_reason = KVM_EXIT_HLT;
4814 return 0;
4815 }
4816}
4817EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4818
2f333bcb
MT		 4819static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
4820 unsigned long a1)
4821{
4822 if (is_long_mode(vcpu))
4823 return a0;
4824 else
4825 return a0 | ((gpa_t)a1 << 32);
4826}
4827
55cd8e5a
GN		 4828int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
4829{
4830 u64 param, ingpa, outgpa, ret;
4831 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
4832 bool fast, longmode;
4833 int cs_db, cs_l;
4834
4835 /*
4836 * hypercall generates UD from non zero cpl and real mode
4837 * per HYPER-V spec
4838 */
3eeb3288 4839 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 4840 kvm_queue_exception(vcpu, UD_VECTOR);
4841 return 0;
4842 }
4843
4844 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4845 longmode = is_long_mode(vcpu) && cs_l == 1;
4846
4847 if (!longmode) {
ccd46936
GN		 4848 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
4849 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
4850 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
4851 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
4852 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
4853 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 4854 }
4855#ifdef CONFIG_X86_64
4856 else {
4857 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
4858 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
4859 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
4860 }
4861#endif
4862
4863 code = param & 0xffff;
4864 fast = (param >> 16) & 0x1;
4865 rep_cnt = (param >> 32) & 0xfff;
4866 rep_idx = (param >> 48) & 0xfff;
4867
4868 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
4869
c25bc163
GN		 4870 switch (code) {
4871 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
4872 kvm_vcpu_on_spin(vcpu);
4873 break;
4874 default:
4875 res = HV_STATUS_INVALID_HYPERCALL_CODE;
4876 break;
4877 }
55cd8e5a
GN		 4878
4879 ret = res | (((u64)rep_done & 0xfff) << 32);
4880 if (longmode) {
4881 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
4882 } else {
4883 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
4884 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
4885 }
4886
4887 return 1;
4888}
4889
8776e519
HB		 4890int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
4891{
4892 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 4893 int r = 1;
8776e519 4894
55cd8e5a
GN		 4895 if (kvm_hv_hypercall_enabled(vcpu->kvm))
4896 return kvm_hv_hypercall(vcpu);
4897
5fdbf976
MT		 4898 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
4899 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
4900 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
4901 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
4902 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 4903
229456fc 4904 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 4905
8776e519
HB		 4906 if (!is_long_mode(vcpu)) {
4907 nr &= 0xFFFFFFFF;
4908 a0 &= 0xFFFFFFFF;
4909 a1 &= 0xFFFFFFFF;
4910 a2 &= 0xFFFFFFFF;
4911 a3 &= 0xFFFFFFFF;
4912 }
4913
07708c4a
JK		 4914 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
4915 ret = -KVM_EPERM;
4916 goto out;
4917 }
4918
8776e519 4919 switch (nr) {
b93463aa
AK		 4920 case KVM_HC_VAPIC_POLL_IRQ:
4921 ret = 0;
4922 break;
2f333bcb
MT		 4923 case KVM_HC_MMU_OP:
4924 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
4925 break;
8776e519
HB		 4926 default:
4927 ret = -KVM_ENOSYS;
4928 break;
4929 }
07708c4a 4930out:
5fdbf976 4931 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 4932 ++vcpu->stat.hypercalls;
2f333bcb 4933 return r;
8776e519
HB		 4934}
4935EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
4936
4937int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
4938{
4939 char instruction[3];
5fdbf976 4940 unsigned long rip = kvm_rip_read(vcpu);
8776e519 4941
8776e519
HB		 4942 /*
4943 * Blow out the MMU to ensure that no other VCPU has an active mapping
4944 * to ensure that the updated hypercall appears atomically across all
4945 * VCPUs.
4946 */
4947 kvm_mmu_zap_all(vcpu->kvm);
4948
8776e519 4949 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 4950
8fe681e9 4951 return emulator_write_emulated(rip, instruction, 3, NULL, vcpu);
8776e519
HB		 4952}
4953
8776e519
HB		 4954void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4955{
89a27f4d 4956 struct desc_ptr dt = { limit, base };
8776e519
HB		 4957
4958 kvm_x86_ops->set_gdt(vcpu, &dt);
4959}
4960
4961void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
4962{
89a27f4d 4963 struct desc_ptr dt = { limit, base };
8776e519
HB		 4964
4965 kvm_x86_ops->set_idt(vcpu, &dt);
4966}
4967
07716717
DK		 4968static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
4969{
ad312c7c
ZX		 4970 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
4971 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 4972
4973 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
4974 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 4975 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 4976 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 4977 if (ej->function == e->function) {
4978 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
4979 return j;
4980 }
4981 }
4982 return 0; /* silence gcc, even though control never reaches here */
4983}
4984
4985/* find an entry with matching function, matching index (if needed), and that
4986 * should be read next (if it's stateful) */
4987static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
4988 u32 function, u32 index)
4989{
4990 if (e->function != function)
4991 return 0;
4992 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
4993 return 0;
4994 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 4995 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 4996 return 0;
4997 return 1;
4998}
4999
d8017474
AG		 5000struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
5001 u32 function, u32 index)
8776e519
HB		 5002{
5003 int i;
d8017474 5004 struct kvm_cpuid_entry2 *best = NULL;
8776e519 5005
ad312c7c 5006 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 5007 struct kvm_cpuid_entry2 *e;
5008
ad312c7c 5009 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 5010 if (is_matching_cpuid_entry(e, function, index)) {
5011 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
5012 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 5013 best = e;
5014 break;
5015 }
8776e519 5016 }
d8017474
AG		 5017 return best;
5018}
0e851880 5019EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
d8017474 5020
82725b20
DE		 5021int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
5022{
5023 struct kvm_cpuid_entry2 *best;
5024
f7a71197
AK		 5025 best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0);
5026 if (!best || best->eax < 0x80000008)
5027 goto not_found;
82725b20
DE		 5028 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
5029 if (best)
5030 return best->eax & 0xff;
f7a71197 5031not_found:
82725b20
DE		 5032 return 36;
5033}
5034
bd22f5cf
AP		 5035/*
5036 * If no match is found, check whether we exceed the vCPU's limit
5037 * and return the content of the highest valid _standard_ leaf instead.
5038 * This is to satisfy the CPUID specification.
5039 */
5040static struct kvm_cpuid_entry2* check_cpuid_limit(struct kvm_vcpu *vcpu,
5041 u32 function, u32 index)
5042{
5043 struct kvm_cpuid_entry2 *maxlevel;
5044
5045 maxlevel = kvm_find_cpuid_entry(vcpu, function & 0x80000000, 0);
5046 if (!maxlevel || maxlevel->eax >= function)
5047 return NULL;
5048 if (function & 0x80000000) {
5049 maxlevel = kvm_find_cpuid_entry(vcpu, 0, 0);
5050 if (!maxlevel)
5051 return NULL;
5052 }
5053 return kvm_find_cpuid_entry(vcpu, maxlevel->eax, index);
5054}
5055
d8017474
AG		 5056void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
5057{
5058 u32 function, index;
5059 struct kvm_cpuid_entry2 *best;
5060
5061 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
5062 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5063 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
5064 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
5065 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
5066 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
5067 best = kvm_find_cpuid_entry(vcpu, function, index);
bd22f5cf
AP		 5068
5069 if (!best)
5070 best = check_cpuid_limit(vcpu, function, index);
5071
8776e519 5072 if (best) {
5fdbf976
MT		 5073 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
5074 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
5075 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
5076 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 5077 }
8776e519 5078 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 5079 trace_kvm_cpuid(function,
5080 kvm_register_read(vcpu, VCPU_REGS_RAX),
5081 kvm_register_read(vcpu, VCPU_REGS_RBX),
5082 kvm_register_read(vcpu, VCPU_REGS_RCX),
5083 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 5084}
5085EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 5086
b6c7a5dc
HB		 5087/*
5088 * Check if userspace requested an interrupt window, and that the
5089 * interrupt window is open.
5090 *
5091 * No need to exit to userspace if we already have an interrupt queued.
5092 */
851ba692 5093static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5094{
8061823a 5095 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5096 vcpu->run->request_interrupt_window &&
5df56646 5097 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5098}
5099
851ba692 5100static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5101{
851ba692
AK		 5102 struct kvm_run *kvm_run = vcpu->run;
5103
91586a3b 5104 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5105 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5106 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5107 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5108 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5109 else
b6c7a5dc 5110 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5111 kvm_arch_interrupt_allowed(vcpu) &&
5112 !kvm_cpu_has_interrupt(vcpu) &&
5113 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5114}
5115
b93463aa
AK		 5116static void vapic_enter(struct kvm_vcpu *vcpu)
5117{
5118 struct kvm_lapic *apic = vcpu->arch.apic;
5119 struct page *page;
5120
5121 if (!apic || !apic->vapic_addr)
5122 return;
5123
5124 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 5125
5126 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 5127}
5128
5129static void vapic_exit(struct kvm_vcpu *vcpu)
5130{
5131 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 5132 int idx;
b93463aa
AK		 5133
5134 if (!apic || !apic->vapic_addr)
5135 return;
5136
f656ce01 5137 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 5138 kvm_release_page_dirty(apic->vapic_page);
5139 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 5140 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 5141}
5142
95ba8273
GN		 5143static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5144{
5145 int max_irr, tpr;
5146
5147 if (!kvm_x86_ops->update_cr8_intercept)
5148 return;
5149
88c808fd
AK		 5150 if (!vcpu->arch.apic)
5151 return;
5152
8db3baa2
GN		 5153 if (!vcpu->arch.apic->vapic_addr)
5154 max_irr = kvm_lapic_find_highest_irr(vcpu);
5155 else
5156 max_irr = -1;
95ba8273
GN		 5157
5158 if (max_irr != -1)
5159 max_irr >>= 4;
5160
5161 tpr = kvm_lapic_get_cr8(vcpu);
5162
5163 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5164}
5165
851ba692 5166static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 5167{
5168 /* try to reinject previous events if any */
b59bb7bd 5169 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5170 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5171 vcpu->arch.exception.has_error_code,
5172 vcpu->arch.exception.error_code);
b59bb7bd
GN		 5173 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5174 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5175 vcpu->arch.exception.error_code,
5176 vcpu->arch.exception.reinject);
b59bb7bd
GN		 5177 return;
5178 }
5179
95ba8273
GN		 5180 if (vcpu->arch.nmi_injected) {
5181 kvm_x86_ops->set_nmi(vcpu);
5182 return;
5183 }
5184
5185 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5186 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5187 return;
5188 }
5189
5190 /* try to inject new event if pending */
5191 if (vcpu->arch.nmi_pending) {
5192 if (kvm_x86_ops->nmi_allowed(vcpu)) {
5193 vcpu->arch.nmi_pending = false;
5194 vcpu->arch.nmi_injected = true;
5195 kvm_x86_ops->set_nmi(vcpu);
5196 }
5197 } else if (kvm_cpu_has_interrupt(vcpu)) {
5198 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5199 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5200 false);
5201 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5202 }
5203 }
5204}
5205
2acf923e
DC		 5206static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
5207{
5208 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
5209 !vcpu->guest_xcr0_loaded) {
5210 /* kvm_set_xcr() also depends on this */
5211 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
5212 vcpu->guest_xcr0_loaded = 1;
5213 }
5214}
5215
5216static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
5217{
5218 if (vcpu->guest_xcr0_loaded) {
5219 if (vcpu->arch.xcr0 != host_xcr0)
5220 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
5221 vcpu->guest_xcr0_loaded = 0;
5222 }
5223}
5224
851ba692 5225static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5226{
5227 int r;
1499e54a 5228 bool nmi_pending;
6a8b1d13 5229 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5230 vcpu->run->request_interrupt_window;
b6c7a5dc 5231
3e007509 5232 if (vcpu->requests) {
a8eeb04a 5233 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5234 kvm_mmu_unload(vcpu);
a8eeb04a 5235 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5236 __kvm_migrate_timers(vcpu);
34c238a1
ZA		 5237 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5238 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 5239 if (unlikely(r))
5240 goto out;
5241 }
a8eeb04a 5242 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5243 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5244 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5245 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5246 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5247 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5248 r = 0;
5249 goto out;
5250 }
a8eeb04a 5251 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5252 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5253 r = 0;
5254 goto out;
5255 }
a8eeb04a 5256 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5257 vcpu->fpu_active = 0;
5258 kvm_x86_ops->fpu_deactivate(vcpu);
5259 }
af585b92
GN		 5260 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5261 /* Page is swapped out. Do synthetic halt */
5262 vcpu->arch.apf.halted = true;
5263 r = 1;
5264 goto out;
5265 }
2f52d58c 5266 }
b93463aa 5267
3e007509
AK		 5268 r = kvm_mmu_reload(vcpu);
5269 if (unlikely(r))
5270 goto out;
5271
1499e54a
GN		 5272 /*
5273 * An NMI can be injected between local nmi_pending read and
5274 * vcpu->arch.nmi_pending read inside inject_pending_event().
5275 * But in that case, KVM_REQ_EVENT will be set, which makes
5276 * the race described above benign.
5277 */
5278 nmi_pending = ACCESS_ONCE(vcpu->arch.nmi_pending);
5279
b463a6f7
AK		 5280 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5281 inject_pending_event(vcpu);
5282
5283 /* enable NMI/IRQ window open exits if needed */
1499e54a 5284 if (nmi_pending)
b463a6f7
AK		 5285 kvm_x86_ops->enable_nmi_window(vcpu);
5286 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
5287 kvm_x86_ops->enable_irq_window(vcpu);
5288
5289 if (kvm_lapic_enabled(vcpu)) {
5290 update_cr8_intercept(vcpu);
5291 kvm_lapic_sync_to_vapic(vcpu);
5292 }
5293 }
5294
b6c7a5dc
HB		 5295 preempt_disable();
5296
5297 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 5298 if (vcpu->fpu_active)
5299 kvm_load_guest_fpu(vcpu);
2acf923e 5300 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 5301
6b7e2d09
XG		 5302 vcpu->mode = IN_GUEST_MODE;
5303
5304 /* We should set ->mode before check ->requests,
5305 * see the comment in make_all_cpus_request.
5306 */
5307 smp_mb();
b6c7a5dc 5308
d94e1dc9 5309 local_irq_disable();
32f88400 5310
6b7e2d09 5311 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 5312 || need_resched() || signal_pending(current)) {
6b7e2d09 5313 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5314 smp_wmb();
6c142801
AK		 5315 local_irq_enable();
5316 preempt_enable();
b463a6f7 5317 kvm_x86_ops->cancel_injection(vcpu);
6c142801
AK		 5318 r = 1;
5319 goto out;
5320 }
5321
f656ce01 5322 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 5323
b6c7a5dc
HB		 5324 kvm_guest_enter();
5325
42dbaa5a 5326 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 5327 set_debugreg(0, 7);
5328 set_debugreg(vcpu->arch.eff_db[0], 0);
5329 set_debugreg(vcpu->arch.eff_db[1], 1);
5330 set_debugreg(vcpu->arch.eff_db[2], 2);
5331 set_debugreg(vcpu->arch.eff_db[3], 3);
5332 }
b6c7a5dc 5333
229456fc 5334 trace_kvm_entry(vcpu->vcpu_id);
851ba692 5335 kvm_x86_ops->run(vcpu);
b6c7a5dc 5336
24f1e32c
FW		 5337 /*
5338 * If the guest has used debug registers, at least dr7
5339 * will be disabled while returning to the host.
5340 * If we don't have active breakpoints in the host, we don't
5341 * care about the messed up debug address registers. But if
5342 * we have some of them active, restore the old state.
5343 */
59d8eb53 5344 if (hw_breakpoint_active())
24f1e32c 5345 hw_breakpoint_restore();
42dbaa5a 5346
1d5f066e
ZA		 5347 kvm_get_msr(vcpu, MSR_IA32_TSC, &vcpu->arch.last_guest_tsc);
5348
6b7e2d09 5349 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5350 smp_wmb();
b6c7a5dc
HB		 5351 local_irq_enable();
5352
5353 ++vcpu->stat.exits;
5354
5355 /*
5356 * We must have an instruction between local_irq_enable() and
5357 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5358 * the interrupt shadow. The stat.exits increment will do nicely.
5359 * But we need to prevent reordering, hence this barrier():
5360 */
5361 barrier();
5362
5363 kvm_guest_exit();
5364
5365 preempt_enable();
5366
f656ce01 5367 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 5368
b6c7a5dc
HB		 5369 /*
5370 * Profile KVM exit RIPs:
5371 */
5372 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 5373 unsigned long rip = kvm_rip_read(vcpu);
5374 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 5375 }
5376
298101da 5377
b93463aa
AK		 5378 kvm_lapic_sync_from_vapic(vcpu);
5379
851ba692 5380 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 5381out:
5382 return r;
5383}
b6c7a5dc 5384
09cec754 5385
851ba692 5386static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 5387{
5388 int r;
f656ce01 5389 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 5390
5391 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 5392 pr_debug("vcpu %d received sipi with vector # %x\n",
5393 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 5394 kvm_lapic_reset(vcpu);
5f179287 5395 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 5396 if (r)
5397 return r;
5398 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 5399 }
5400
f656ce01 5401 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 5402 vapic_enter(vcpu);
5403
5404 r = 1;
5405 while (r > 0) {
af585b92
GN		 5406 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
5407 !vcpu->arch.apf.halted)
851ba692 5408 r = vcpu_enter_guest(vcpu);
d7690175 5409 else {
f656ce01 5410 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 5411 kvm_vcpu_block(vcpu);
f656ce01 5412 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
a8eeb04a 5413 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
09cec754
GN		 5414 {
5415 switch(vcpu->arch.mp_state) {
5416 case KVM_MP_STATE_HALTED:
d7690175 5417 vcpu->arch.mp_state =
09cec754
GN		 5418 KVM_MP_STATE_RUNNABLE;
5419 case KVM_MP_STATE_RUNNABLE:
af585b92 5420 vcpu->arch.apf.halted = false;
09cec754
GN		 5421 break;
5422 case KVM_MP_STATE_SIPI_RECEIVED:
5423 default:
5424 r = -EINTR;
5425 break;
5426 }
5427 }
d7690175
MT		 5428 }
5429
09cec754
GN		 5430 if (r <= 0)
5431 break;
5432
5433 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5434 if (kvm_cpu_has_pending_timer(vcpu))
5435 kvm_inject_pending_timer_irqs(vcpu);
5436
851ba692 5437 if (dm_request_for_irq_injection(vcpu)) {
09cec754 5438 r = -EINTR;
851ba692 5439 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5440 ++vcpu->stat.request_irq_exits;
5441 }
af585b92
GN		 5442
5443 kvm_check_async_pf_completion(vcpu);
5444
09cec754
GN		 5445 if (signal_pending(current)) {
5446 r = -EINTR;
851ba692 5447 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5448 ++vcpu->stat.signal_exits;
5449 }
5450 if (need_resched()) {
f656ce01 5451 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 5452 kvm_resched(vcpu);
f656ce01 5453 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 5454 }
b6c7a5dc
HB		 5455 }
5456
f656ce01 5457 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 5458
b93463aa
AK		 5459 vapic_exit(vcpu);
5460
b6c7a5dc
HB		 5461 return r;
5462}
5463
5287f194
AK		 5464static int complete_mmio(struct kvm_vcpu *vcpu)
5465{
5466 struct kvm_run *run = vcpu->run;
5467 int r;
5468
5469 if (!(vcpu->arch.pio.count || vcpu->mmio_needed))
5470 return 1;
5471
5472 if (vcpu->mmio_needed) {
5287f194 5473 vcpu->mmio_needed = 0;
cef4dea0
AK		 5474 if (!vcpu->mmio_is_write)
5475 memcpy(vcpu->mmio_data, run->mmio.data, 8);
5476 vcpu->mmio_index += 8;
5477 if (vcpu->mmio_index < vcpu->mmio_size) {
5478 run->exit_reason = KVM_EXIT_MMIO;
5479 run->mmio.phys_addr = vcpu->mmio_phys_addr + vcpu->mmio_index;
5480 memcpy(run->mmio.data, vcpu->mmio_data + vcpu->mmio_index, 8);
5481 run->mmio.len = min(vcpu->mmio_size - vcpu->mmio_index, 8);
5482 run->mmio.is_write = vcpu->mmio_is_write;
5483 vcpu->mmio_needed = 1;
5484 return 0;
5485 }
5486 if (vcpu->mmio_is_write)
5487 return 1;
5488 vcpu->mmio_read_completed = 1;
5287f194
AK		 5489 }
5490 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5491 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
5492 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5493 if (r != EMULATE_DONE)
5494 return 0;
5495 return 1;
5496}
5497
b6c7a5dc
HB		 5498int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
5499{
5500 int r;
5501 sigset_t sigsaved;
5502
e5c30142
AK		 5503 if (!tsk_used_math(current) && init_fpu(current))
5504 return -ENOMEM;
5505
ac9f6dc0
AK		 5506 if (vcpu->sigset_active)
5507 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
5508
a4535290 5509 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 5510 kvm_vcpu_block(vcpu);
d7690175 5511 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 5512 r = -EAGAIN;
5513 goto out;
b6c7a5dc
HB		 5514 }
5515
b6c7a5dc 5516 /* re-sync apic's tpr */
eea1cff9
AP		 5517 if (!irqchip_in_kernel(vcpu->kvm)) {
5518 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
5519 r = -EINVAL;
5520 goto out;
5521 }
5522 }
b6c7a5dc 5523
5287f194
AK		 5524 r = complete_mmio(vcpu);
5525 if (r <= 0)
5526 goto out;
5527
5fdbf976
MT		 5528 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
5529 kvm_register_write(vcpu, VCPU_REGS_RAX,
5530 kvm_run->hypercall.ret);
b6c7a5dc 5531
851ba692 5532 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 5533
5534out:
f1d86e46 5535 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 5536 if (vcpu->sigset_active)
5537 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
5538
b6c7a5dc
HB		 5539 return r;
5540}
5541
5542int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5543{
5fdbf976
MT		 5544 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5545 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5546 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5547 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5548 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
5549 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
5550 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5551 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 5552#ifdef CONFIG_X86_64
5fdbf976
MT		 5553 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
5554 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
5555 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
5556 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
5557 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
5558 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
5559 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
5560 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 5561#endif
5562
5fdbf976 5563 regs->rip = kvm_rip_read(vcpu);
91586a3b 5564 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 5565
b6c7a5dc
HB		 5566 return 0;
5567}
5568
5569int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5570{
5fdbf976
MT		 5571 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
5572 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
5573 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
5574 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
5575 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
5576 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
5577 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
5578 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 5579#ifdef CONFIG_X86_64
5fdbf976
MT		 5580 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
5581 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
5582 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
5583 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
5584 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
5585 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
5586 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
5587 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 5588#endif
5589
5fdbf976 5590 kvm_rip_write(vcpu, regs->rip);
91586a3b 5591 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 5592
b4f14abd
JK		 5593 vcpu->arch.exception.pending = false;
5594
3842d135
AK		 5595 kvm_make_request(KVM_REQ_EVENT, vcpu);
5596
b6c7a5dc
HB		 5597 return 0;
5598}
5599
b6c7a5dc
HB		 5600void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5601{
5602 struct kvm_segment cs;
5603
3e6e0aab 5604 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 5605 *db = cs.db;
5606 *l = cs.l;
5607}
5608EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
5609
5610int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
5611 struct kvm_sregs *sregs)
5612{
89a27f4d 5613 struct desc_ptr dt;
b6c7a5dc 5614
3e6e0aab
GT		 5615 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5616 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5617 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5618 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5619 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5620 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5621
3e6e0aab
GT		 5622 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5623 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 5624
5625 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 5626 sregs->idt.limit = dt.size;
5627 sregs->idt.base = dt.address;
b6c7a5dc 5628 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 5629 sregs->gdt.limit = dt.size;
5630 sregs->gdt.base = dt.address;
b6c7a5dc 5631
4d4ec087 5632 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 5633 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 5634 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 5635 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 5636 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 5637 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 5638 sregs->apic_base = kvm_get_apic_base(vcpu);
5639
923c61bb 5640 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 5641
36752c9b 5642 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 5643 set_bit(vcpu->arch.interrupt.nr,
5644 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 5645
b6c7a5dc
HB		 5646 return 0;
5647}
5648
62d9f0db
MT		 5649int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
5650 struct kvm_mp_state *mp_state)
5651{
62d9f0db 5652 mp_state->mp_state = vcpu->arch.mp_state;
62d9f0db
MT		 5653 return 0;
5654}
5655
5656int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
5657 struct kvm_mp_state *mp_state)
5658{
62d9f0db 5659 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 5660 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 5661 return 0;
5662}
5663
e269fb21
JK		 5664int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason,
5665 bool has_error_code, u32 error_code)
b6c7a5dc 5666{
4d2179e1 5667 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
8ec4722d 5668 int ret;
e01c2426 5669
8ec4722d 5670 init_emulate_ctxt(vcpu);
c697518a 5671
9aabc88f 5672 ret = emulator_task_switch(&vcpu->arch.emulate_ctxt,
e269fb21
JK		 5673 tss_selector, reason, has_error_code,
5674 error_code);
c697518a 5675
c697518a 5676 if (ret)
19d04437 5677 return EMULATE_FAIL;
37817f29 5678
4d2179e1 5679 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
95c55886 5680 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
f6e78475 5681 kvm_set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
3842d135 5682 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 5683 return EMULATE_DONE;
37817f29
IE		 5684}
5685EXPORT_SYMBOL_GPL(kvm_task_switch);
5686
b6c7a5dc
HB		 5687int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5688 struct kvm_sregs *sregs)
5689{
5690 int mmu_reset_needed = 0;
63f42e02 5691 int pending_vec, max_bits, idx;
89a27f4d 5692 struct desc_ptr dt;
b6c7a5dc 5693
89a27f4d
GN		 5694 dt.size = sregs->idt.limit;
5695 dt.address = sregs->idt.base;
b6c7a5dc 5696 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 5697 dt.size = sregs->gdt.limit;
5698 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 5699 kvm_x86_ops->set_gdt(vcpu, &dt);
5700
ad312c7c 5701 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 5702 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 5703 vcpu->arch.cr3 = sregs->cr3;
aff48baa 5704 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 5705
2d3ad1f4 5706 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 5707
f6801dff 5708 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 5709 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 5710 kvm_set_apic_base(vcpu, sregs->apic_base);
5711
4d4ec087 5712 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 5713 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 5714 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 5715
fc78f519 5716 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 5717 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c
SY		 5718 if (sregs->cr4 & X86_CR4_OSXSAVE)
5719 update_cpuid(vcpu);
63f42e02
XG		 5720
5721 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 5722 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 5723 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 5724 mmu_reset_needed = 1;
5725 }
63f42e02 5726 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 5727
5728 if (mmu_reset_needed)
5729 kvm_mmu_reset_context(vcpu);
5730
923c61bb
GN		 5731 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5732 pending_vec = find_first_bit(
5733 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5734 if (pending_vec < max_bits) {
66fd3f7f 5735 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 5736 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 5737 }
5738
3e6e0aab
GT		 5739 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5740 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5741 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5742 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5743 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5744 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5745
3e6e0aab
GT		 5746 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5747 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 5748
5f0269f5
ME		 5749 update_cr8_intercept(vcpu);
5750
9c3e4aab 5751 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 5752 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 5753 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 5754 !is_protmode(vcpu))
9c3e4aab
MT		 5755 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5756
3842d135
AK		 5757 kvm_make_request(KVM_REQ_EVENT, vcpu);
5758
b6c7a5dc
HB		 5759 return 0;
5760}
5761
d0bfb940
JK		 5762int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5763 struct kvm_guest_debug *dbg)
b6c7a5dc 5764{
355be0b9 5765 unsigned long rflags;
ae675ef0 5766 int i, r;
b6c7a5dc 5767
4f926bf2
JK		 5768 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5769 r = -EBUSY;
5770 if (vcpu->arch.exception.pending)
2122ff5e 5771 goto out;
4f926bf2
JK		 5772 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5773 kvm_queue_exception(vcpu, DB_VECTOR);
5774 else
5775 kvm_queue_exception(vcpu, BP_VECTOR);
5776 }
5777
91586a3b
JK		 5778 /*
5779 * Read rflags as long as potentially injected trace flags are still
5780 * filtered out.
5781 */
5782 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 5783
5784 vcpu->guest_debug = dbg->control;
5785 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5786 vcpu->guest_debug = 0;
5787
5788 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 5789 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5790 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5791 vcpu->arch.switch_db_regs =
5792 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5793 } else {
5794 for (i = 0; i < KVM_NR_DB_REGS; i++)
5795 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5796 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5797 }
5798
f92653ee
JK		 5799 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5800 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5801 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 5802
91586a3b
JK		 5803 /*
5804 * Trigger an rflags update that will inject or remove the trace
5805 * flags.
5806 */
5807 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 5808
355be0b9 5809 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 5810
4f926bf2 5811 r = 0;
d0bfb940 5812
2122ff5e 5813out:
b6c7a5dc
HB		 5814
5815 return r;
5816}
5817
8b006791
ZX		 5818/*
5819 * Translate a guest virtual address to a guest physical address.
5820 */
5821int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5822 struct kvm_translation *tr)
5823{
5824 unsigned long vaddr = tr->linear_address;
5825 gpa_t gpa;
f656ce01 5826 int idx;
8b006791 5827
f656ce01 5828 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 5829 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 5830 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 5831 tr->physical_address = gpa;
5832 tr->valid = gpa != UNMAPPED_GVA;
5833 tr->writeable = 1;
5834 tr->usermode = 0;
8b006791
ZX		 5835
5836 return 0;
5837}
5838
d0752060
HB		 5839int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5840{
98918833
SY		 5841 struct i387_fxsave_struct *fxsave =
5842 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5843
d0752060
HB		 5844 memcpy(fpu->fpr, fxsave->st_space, 128);
5845 fpu->fcw = fxsave->cwd;
5846 fpu->fsw = fxsave->swd;
5847 fpu->ftwx = fxsave->twd;
5848 fpu->last_opcode = fxsave->fop;
5849 fpu->last_ip = fxsave->rip;
5850 fpu->last_dp = fxsave->rdp;
5851 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5852
d0752060
HB		 5853 return 0;
5854}
5855
5856int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5857{
98918833
SY		 5858 struct i387_fxsave_struct *fxsave =
5859 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5860
d0752060
HB		 5861 memcpy(fxsave->st_space, fpu->fpr, 128);
5862 fxsave->cwd = fpu->fcw;
5863 fxsave->swd = fpu->fsw;
5864 fxsave->twd = fpu->ftwx;
5865 fxsave->fop = fpu->last_opcode;
5866 fxsave->rip = fpu->last_ip;
5867 fxsave->rdp = fpu->last_dp;
5868 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5869
d0752060
HB		 5870 return 0;
5871}
5872
10ab25cd 5873int fx_init(struct kvm_vcpu *vcpu)
d0752060 5874{
10ab25cd
JK		 5875 int err;
5876
5877 err = fpu_alloc(&vcpu->arch.guest_fpu);
5878 if (err)
5879 return err;
5880
98918833 5881 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 5882
2acf923e
DC		 5883 /*
5884 * Ensure guest xcr0 is valid for loading
5885 */
5886 vcpu->arch.xcr0 = XSTATE_FP;
5887
ad312c7c 5888 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 5889
5890 return 0;
d0752060
HB		 5891}
5892EXPORT_SYMBOL_GPL(fx_init);
5893
98918833
SY		 5894static void fx_free(struct kvm_vcpu *vcpu)
5895{
5896 fpu_free(&vcpu->arch.guest_fpu);
5897}
5898
d0752060
HB		 5899void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5900{
2608d7a1 5901 if (vcpu->guest_fpu_loaded)
d0752060
HB		 5902 return;
5903
2acf923e
DC		 5904 /*
5905 * Restore all possible states in the guest,
5906 * and assume host would use all available bits.
5907 * Guest xcr0 would be loaded later.
5908 */
5909 kvm_put_guest_xcr0(vcpu);
d0752060 5910 vcpu->guest_fpu_loaded = 1;
7cf30855 5911 unlazy_fpu(current);
98918833 5912 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 5913 trace_kvm_fpu(1);
d0752060 5914}
d0752060
HB		 5915
5916void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5917{
2acf923e
DC		 5918 kvm_put_guest_xcr0(vcpu);
5919
d0752060
HB		 5920 if (!vcpu->guest_fpu_loaded)
5921 return;
5922
5923 vcpu->guest_fpu_loaded = 0;
98918833 5924 fpu_save_init(&vcpu->arch.guest_fpu);
f096ed85 5925 ++vcpu->stat.fpu_reload;
a8eeb04a 5926 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 5927 trace_kvm_fpu(0);
d0752060 5928}
e9b11c17
ZX		 5929
5930void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5931{
12f9a48f 5932 kvmclock_reset(vcpu);
7f1ea208 5933
f5f48ee1 5934 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 5935 fx_free(vcpu);
e9b11c17
ZX		 5936 kvm_x86_ops->vcpu_free(vcpu);
5937}
5938
5939struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5940 unsigned int id)
5941{
6755bae8
ZA		 5942 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
5943 printk_once(KERN_WARNING
5944 "kvm: SMP vm created on host with unstable TSC; "
5945 "guest TSC will not be reliable\n");
26e5215f
AK		 5946 return kvm_x86_ops->vcpu_create(kvm, id);
5947}
e9b11c17 5948
26e5215f
AK		 5949int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5950{
5951 int r;
e9b11c17 5952
0bed3b56 5953 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 5954 vcpu_load(vcpu);
5955 r = kvm_arch_vcpu_reset(vcpu);
5956 if (r == 0)
5957 r = kvm_mmu_setup(vcpu);
5958 vcpu_put(vcpu);
5959 if (r < 0)
5960 goto free_vcpu;
5961
26e5215f 5962 return 0;
e9b11c17
ZX		 5963free_vcpu:
5964 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 5965 return r;
e9b11c17
ZX		 5966}
5967
d40ccc62 5968void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 5969{
344d9588
GN		 5970 vcpu->arch.apf.msr_val = 0;
5971
e9b11c17
ZX		 5972 vcpu_load(vcpu);
5973 kvm_mmu_unload(vcpu);
5974 vcpu_put(vcpu);
5975
98918833 5976 fx_free(vcpu);
e9b11c17
ZX		 5977 kvm_x86_ops->vcpu_free(vcpu);
5978}
5979
5980int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
5981{
448fa4a9
JK		 5982 vcpu->arch.nmi_pending = false;
5983 vcpu->arch.nmi_injected = false;
5984
42dbaa5a
JK		 5985 vcpu->arch.switch_db_regs = 0;
5986 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
5987 vcpu->arch.dr6 = DR6_FIXED_1;
5988 vcpu->arch.dr7 = DR7_FIXED_1;
5989
3842d135 5990 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 5991 vcpu->arch.apf.msr_val = 0;
3842d135 5992
12f9a48f
GC		 5993 kvmclock_reset(vcpu);
5994
af585b92
GN		 5995 kvm_clear_async_pf_completion_queue(vcpu);
5996 kvm_async_pf_hash_reset(vcpu);
5997 vcpu->arch.apf.halted = false;
3842d135 5998
e9b11c17
ZX		 5999 return kvm_x86_ops->vcpu_reset(vcpu);
6000}
6001
10474ae8 6002int kvm_arch_hardware_enable(void *garbage)
e9b11c17 6003{
ca84d1a2
ZA		 6004 struct kvm *kvm;
6005 struct kvm_vcpu *vcpu;
6006 int i;
18863bdd
AK		 6007
6008 kvm_shared_msr_cpu_online();
ca84d1a2
ZA		 6009 list_for_each_entry(kvm, &vm_list, vm_list)
6010 kvm_for_each_vcpu(i, vcpu, kvm)
6011 if (vcpu->cpu == smp_processor_id())
c285545f 6012 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
10474ae8 6013 return kvm_x86_ops->hardware_enable(garbage);
e9b11c17
ZX		 6014}
6015
6016void kvm_arch_hardware_disable(void *garbage)
6017{
6018 kvm_x86_ops->hardware_disable(garbage);
3548bab5 6019 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 6020}
6021
6022int kvm_arch_hardware_setup(void)
6023{
6024 return kvm_x86_ops->hardware_setup();
6025}
6026
6027void kvm_arch_hardware_unsetup(void)
6028{
6029 kvm_x86_ops->hardware_unsetup();
6030}
6031
6032void kvm_arch_check_processor_compat(void *rtn)
6033{
6034 kvm_x86_ops->check_processor_compatibility(rtn);
6035}
6036
6037int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6038{
6039 struct page *page;
6040 struct kvm *kvm;
6041 int r;
6042
6043 BUG_ON(vcpu->kvm == NULL);
6044 kvm = vcpu->kvm;
6045
9aabc88f 6046 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
14dfe855 6047 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
ad312c7c 6048 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c30a358d 6049 vcpu->arch.mmu.translate_gpa = translate_gpa;
02f59dc9 6050 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
c5af89b6 6051 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 6052 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 6053 else
a4535290 6054 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 6055
6056 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6057 if (!page) {
6058 r = -ENOMEM;
6059 goto fail;
6060 }
ad312c7c 6061 vcpu->arch.pio_data = page_address(page);
e9b11c17 6062
c285545f
ZA		 6063 if (!kvm->arch.virtual_tsc_khz)
6064 kvm_arch_set_tsc_khz(kvm, max_tsc_khz);
6065
e9b11c17
ZX		 6066 r = kvm_mmu_create(vcpu);
6067 if (r < 0)
6068 goto fail_free_pio_data;
6069
6070 if (irqchip_in_kernel(kvm)) {
6071 r = kvm_create_lapic(vcpu);
6072 if (r < 0)
6073 goto fail_mmu_destroy;
6074 }
6075
890ca9ae
HY		 6076 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6077 GFP_KERNEL);
6078 if (!vcpu->arch.mce_banks) {
6079 r = -ENOMEM;
443c39bc 6080 goto fail_free_lapic;
890ca9ae
HY		 6081 }
6082 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6083
f5f48ee1
SY		 6084 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
6085 goto fail_free_mce_banks;
6086
af585b92
GN		 6087 kvm_async_pf_hash_reset(vcpu);
6088
e9b11c17 6089 return 0;
f5f48ee1
SY		 6090fail_free_mce_banks:
6091 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 6092fail_free_lapic:
6093 kvm_free_lapic(vcpu);
e9b11c17
ZX		 6094fail_mmu_destroy:
6095 kvm_mmu_destroy(vcpu);
6096fail_free_pio_data:
ad312c7c 6097 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 6098fail:
6099 return r;
6100}
6101
6102void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6103{
f656ce01
MT		 6104 int idx;
6105
36cb93fd 6106 kfree(vcpu->arch.mce_banks);
e9b11c17 6107 kvm_free_lapic(vcpu);
f656ce01 6108 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 6109 kvm_mmu_destroy(vcpu);
f656ce01 6110 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 6111 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 6112}
d19a9cd2 6113
d89f5eff 6114int kvm_arch_init_vm(struct kvm *kvm)
d19a9cd2 6115{
f05e70ac 6116 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 6117 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 6118
5550af4d
SY		 6119 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
6120 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
6121
038f8c11 6122 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
53f658b3 6123
d89f5eff 6124 return 0;
d19a9cd2
ZX		 6125}
6126
6127static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
6128{
6129 vcpu_load(vcpu);
6130 kvm_mmu_unload(vcpu);
6131 vcpu_put(vcpu);
6132}
6133
6134static void kvm_free_vcpus(struct kvm *kvm)
6135{
6136 unsigned int i;
988a2cae 6137 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 6138
6139 /*
6140 * Unpin any mmu pages first.
6141 */
af585b92
GN		 6142 kvm_for_each_vcpu(i, vcpu, kvm) {
6143 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 6144 kvm_unload_vcpu_mmu(vcpu);
af585b92 6145 }
988a2cae
GN		 6146 kvm_for_each_vcpu(i, vcpu, kvm)
6147 kvm_arch_vcpu_free(vcpu);
6148
6149 mutex_lock(&kvm->lock);
6150 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
6151 kvm->vcpus[i] = NULL;
d19a9cd2 6152
988a2cae
GN		 6153 atomic_set(&kvm->online_vcpus, 0);
6154 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 6155}
6156
ad8ba2cd
SY		 6157void kvm_arch_sync_events(struct kvm *kvm)
6158{
ba4cef31 6159 kvm_free_all_assigned_devices(kvm);
aea924f6 6160 kvm_free_pit(kvm);
ad8ba2cd
SY		 6161}
6162
d19a9cd2
ZX		 6163void kvm_arch_destroy_vm(struct kvm *kvm)
6164{
6eb55818 6165 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 6166 kfree(kvm->arch.vpic);
6167 kfree(kvm->arch.vioapic);
d19a9cd2 6168 kvm_free_vcpus(kvm);
3d45830c
AK		 6169 if (kvm->arch.apic_access_page)
6170 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 6171 if (kvm->arch.ept_identity_pagetable)
6172 put_page(kvm->arch.ept_identity_pagetable);
d19a9cd2 6173}
0de10343 6174
f7784b8e
MT		 6175int kvm_arch_prepare_memory_region(struct kvm *kvm,
6176 struct kvm_memory_slot *memslot,
0de10343 6177 struct kvm_memory_slot old,
f7784b8e 6178 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 6179 int user_alloc)
6180{
f7784b8e 6181 int npages = memslot->npages;
7ac77099
AK		 6182 int map_flags = MAP_PRIVATE | MAP_ANONYMOUS;
6183
6184 /* Prevent internal slot pages from being moved by fork()/COW. */
6185 if (memslot->id >= KVM_MEMORY_SLOTS)
6186 map_flags = MAP_SHARED | MAP_ANONYMOUS;
0de10343
ZX		 6187
6188 /*To keep backward compatibility with older userspace,
6189 *x86 needs to hanlde !user_alloc case.
6190 */
6191 if (!user_alloc) {
6192 if (npages && !old.rmap) {
604b38ac
AA		 6193 unsigned long userspace_addr;
6194
72dc67a6 6195 down_write(&current->mm->mmap_sem);
604b38ac
AA		 6196 userspace_addr = do_mmap(NULL, 0,
6197 npages * PAGE_SIZE,
6198 PROT_READ | PROT_WRITE,
7ac77099 6199 map_flags,
604b38ac 6200 0);
72dc67a6 6201 up_write(&current->mm->mmap_sem);
0de10343 6202
604b38ac
AA		 6203 if (IS_ERR((void *)userspace_addr))
6204 return PTR_ERR((void *)userspace_addr);
6205
604b38ac 6206 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 6207 }
6208 }
6209
f7784b8e
MT		 6210
6211 return 0;
6212}
6213
6214void kvm_arch_commit_memory_region(struct kvm *kvm,
6215 struct kvm_userspace_memory_region *mem,
6216 struct kvm_memory_slot old,
6217 int user_alloc)
6218{
6219
48c0e4e9 6220 int nr_mmu_pages = 0, npages = mem->memory_size >> PAGE_SHIFT;
f7784b8e
MT		 6221
6222 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
6223 int ret;
6224
6225 down_write(&current->mm->mmap_sem);
6226 ret = do_munmap(current->mm, old.userspace_addr,
6227 old.npages * PAGE_SIZE);
6228 up_write(&current->mm->mmap_sem);
6229 if (ret < 0)
6230 printk(KERN_WARNING
6231 "kvm_vm_ioctl_set_memory_region: "
6232 "failed to munmap memory\n");
6233 }
6234
48c0e4e9
XG		 6235 if (!kvm->arch.n_requested_mmu_pages)
6236 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
6237
7c8a83b7 6238 spin_lock(&kvm->mmu_lock);
48c0e4e9 6239 if (nr_mmu_pages)
0de10343 6240 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
0de10343 6241 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 6242 spin_unlock(&kvm->mmu_lock);
0de10343 6243}
1d737c8a 6244
34d4cb8f
MT		 6245void kvm_arch_flush_shadow(struct kvm *kvm)
6246{
6247 kvm_mmu_zap_all(kvm);
8986ecc0 6248 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 6249}
6250
1d737c8a
ZX		 6251int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
6252{
af585b92
GN		 6253 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6254 !vcpu->arch.apf.halted)
6255 || !list_empty_careful(&vcpu->async_pf.done)
a1b37100
GN		 6256 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
6257 || vcpu->arch.nmi_pending ||
6258 (kvm_arch_interrupt_allowed(vcpu) &&
6259 kvm_cpu_has_interrupt(vcpu));
1d737c8a 6260}
5736199a 6261
5736199a
ZX		 6262void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
6263{
32f88400
MT		 6264 int me;
6265 int cpu = vcpu->cpu;
5736199a
ZX		 6266
6267 if (waitqueue_active(&vcpu->wq)) {
6268 wake_up_interruptible(&vcpu->wq);
6269 ++vcpu->stat.halt_wakeup;
6270 }
32f88400
MT		 6271
6272 me = get_cpu();
6273 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
6b7e2d09 6274 if (kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE)
32f88400 6275 smp_send_reschedule(cpu);
e9571ed5 6276 put_cpu();
5736199a 6277}
78646121
GN		 6278
6279int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
6280{
6281 return kvm_x86_ops->interrupt_allowed(vcpu);
6282}
229456fc 6283
f92653ee
JK		 6284bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
6285{
6286 unsigned long current_rip = kvm_rip_read(vcpu) +
6287 get_segment_base(vcpu, VCPU_SREG_CS);
6288
6289 return current_rip == linear_rip;
6290}
6291EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
6292
94fe45da
JK		 6293unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
6294{
6295 unsigned long rflags;
6296
6297 rflags = kvm_x86_ops->get_rflags(vcpu);
6298 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 6299 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 6300 return rflags;
6301}
6302EXPORT_SYMBOL_GPL(kvm_get_rflags);
6303
6304void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
6305{
6306 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 6307 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 6308 rflags |= X86_EFLAGS_TF;
94fe45da 6309 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 6310 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 6311}
6312EXPORT_SYMBOL_GPL(kvm_set_rflags);
6313
56028d08
GN		 6314void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
6315{
6316 int r;
6317
fb67e14f 6318 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
c4806acd 6319 is_error_page(work->page))
56028d08
GN		 6320 return;
6321
6322 r = kvm_mmu_reload(vcpu);
6323 if (unlikely(r))
6324 return;
6325
fb67e14f
XG		 6326 if (!vcpu->arch.mmu.direct_map &&
6327 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
6328 return;
6329
56028d08
GN		 6330 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
6331}
6332
af585b92
GN		 6333static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
6334{
6335 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
6336}
6337
6338static inline u32 kvm_async_pf_next_probe(u32 key)
6339{
6340 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
6341}
6342
6343static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6344{
6345 u32 key = kvm_async_pf_hash_fn(gfn);
6346
6347 while (vcpu->arch.apf.gfns[key] != ~0)
6348 key = kvm_async_pf_next_probe(key);
6349
6350 vcpu->arch.apf.gfns[key] = gfn;
6351}
6352
6353static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
6354{
6355 int i;
6356 u32 key = kvm_async_pf_hash_fn(gfn);
6357
6358 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 6359 (vcpu->arch.apf.gfns[key] != gfn &&
6360 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 6361 key = kvm_async_pf_next_probe(key);
6362
6363 return key;
6364}
6365
6366bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6367{
6368 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
6369}
6370
6371static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6372{
6373 u32 i, j, k;
6374
6375 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
6376 while (true) {
6377 vcpu->arch.apf.gfns[i] = ~0;
6378 do {
6379 j = kvm_async_pf_next_probe(j);
6380 if (vcpu->arch.apf.gfns[j] == ~0)
6381 return;
6382 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
6383 /*
6384 * k lies cyclically in ]i,j]
6385 * | i.k.j |
6386 * |....j i.k.| or |.k..j i...|
6387 */
6388 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
6389 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
6390 i = j;
6391 }
6392}
6393
7c90705b
GN		 6394static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
6395{
6396
6397 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
6398 sizeof(val));
6399}
6400
af585b92
GN		 6401void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
6402 struct kvm_async_pf *work)
6403{
6389ee94
AK		 6404 struct x86_exception fault;
6405
7c90705b 6406 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 6407 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 6408
6409 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 6410 (vcpu->arch.apf.send_user_only &&
6411 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 6412 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
6413 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 6414 fault.vector = PF_VECTOR;
6415 fault.error_code_valid = true;
6416 fault.error_code = 0;
6417 fault.nested_page_fault = false;
6418 fault.address = work->arch.token;
6419 kvm_inject_page_fault(vcpu, &fault);
7c90705b 6420 }
af585b92
GN		 6421}
6422
6423void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
6424 struct kvm_async_pf *work)
6425{
6389ee94
AK		 6426 struct x86_exception fault;
6427
7c90705b
GN		 6428 trace_kvm_async_pf_ready(work->arch.token, work->gva);
6429 if (is_error_page(work->page))
6430 work->arch.token = ~0; /* broadcast wakeup */
6431 else
6432 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
6433
6434 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
6435 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 6436 fault.vector = PF_VECTOR;
6437 fault.error_code_valid = true;
6438 fault.error_code = 0;
6439 fault.nested_page_fault = false;
6440 fault.address = work->arch.token;
6441 kvm_inject_page_fault(vcpu, &fault);
7c90705b 6442 }
e6d53e3b 6443 vcpu->arch.apf.halted = false;
7c90705b
GN		 6444}
6445
6446bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
6447{
6448 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
6449 return true;
6450 else
6451 return !kvm_event_needs_reinjection(vcpu) &&
6452 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 6453}
6454
229456fc
MT		 6455EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
6456EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
6457EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
6458EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
6459EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 6460EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 6461EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 6462EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 6463EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 6464EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 6465EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 6466EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
kernel source for telekom puls (alcatel/mediatek)