projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
KVM: perform an invalid memslot step for gpa base change
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
313a3dc7 30
18068523 31#include <linux/clocksource.h>
4d5c5d0f 32#include <linux/interrupt.h>
313a3dc7
CO		 33#include <linux/kvm.h>
34#include <linux/fs.h>
35#include <linux/vmalloc.h>
5fb76f9b 36#include <linux/module.h>
0de10343 37#include <linux/mman.h>
2bacc55c 38#include <linux/highmem.h>
19de40a8 39#include <linux/iommu.h>
62c476c7 40#include <linux/intel-iommu.h>
c8076604 41#include <linux/cpufreq.h>
18863bdd 42#include <linux/user-return-notifier.h>
a983fb23 43#include <linux/srcu.h>
5a0e3ad6 44#include <linux/slab.h>
ff9d07a0 45#include <linux/perf_event.h>
7bee342a 46#include <linux/uaccess.h>
af585b92 47#include <linux/hash.h>
a1b60c1c 48#include <linux/pci.h>
aec51dc4 49#include <trace/events/kvm.h>
2ed152af 50
229456fc
MT		 51#define CREATE_TRACE_POINTS
52#include "trace.h"
043405e1 53
24f1e32c 54#include <asm/debugreg.h>
d825ed0a 55#include <asm/msr.h>
a5f61300 56#include <asm/desc.h>
0bed3b56 57#include <asm/mtrr.h>
890ca9ae 58#include <asm/mce.h>
7cf30855 59#include <asm/i387.h>
1361b83a 60#include <asm/fpu-internal.h> /* Ugh! */
98918833 61#include <asm/xcr.h>
1d5f066e 62#include <asm/pvclock.h>
217fc9cf 63#include <asm/div64.h>
043405e1 64
313a3dc7 65#define MAX_IO_MSRS 256
890ca9ae 66#define KVM_MAX_MCE_BANKS 32
5854dbca 67#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 68
0f65dd70
AK		 69#define emul_to_vcpu(ctxt) \
70 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
71
50a37eb4
JR		 72/* EFER defaults:
73 * - enable syscall per default because its emulated by KVM
74 * - enable LME and LMA per default on 64 bit KVM
75 */
76#ifdef CONFIG_X86_64
1260edbe
LJ		 77static
78u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 79#else
1260edbe 80static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 81#endif
313a3dc7 82
ba1389b7
AK		 83#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
84#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 85
cb142eb7 86static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 87static void process_nmi(struct kvm_vcpu *vcpu);
674eea0f 88
97896d04 89struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 90EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 91
476bc001
RR		 92static bool ignore_msrs = 0;
93module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 94
92a1f12d
JR		 95bool kvm_has_tsc_control;
96EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
97u32 kvm_max_guest_tsc_khz;
98EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
99
cc578287
ZA		 100/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
101static u32 tsc_tolerance_ppm = 250;
102module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
103
18863bdd
AK		 104#define KVM_NR_SHARED_MSRS 16
105
106struct kvm_shared_msrs_global {
107 int nr;
2bf78fa7 108 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 109};
110
111struct kvm_shared_msrs {
112 struct user_return_notifier urn;
113 bool registered;
2bf78fa7
SY		 114 struct kvm_shared_msr_values {
115 u64 host;
116 u64 curr;
117 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 118};
119
120static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
121static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
122
417bc304 123struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 124 { "pf_fixed", VCPU_STAT(pf_fixed) },
125 { "pf_guest", VCPU_STAT(pf_guest) },
126 { "tlb_flush", VCPU_STAT(tlb_flush) },
127 { "invlpg", VCPU_STAT(invlpg) },
128 { "exits", VCPU_STAT(exits) },
129 { "io_exits", VCPU_STAT(io_exits) },
130 { "mmio_exits", VCPU_STAT(mmio_exits) },
131 { "signal_exits", VCPU_STAT(signal_exits) },
132 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 133 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 134 { "halt_exits", VCPU_STAT(halt_exits) },
135 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 136 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 137 { "request_irq", VCPU_STAT(request_irq_exits) },
138 { "irq_exits", VCPU_STAT(irq_exits) },
139 { "host_state_reload", VCPU_STAT(host_state_reload) },
140 { "efer_reload", VCPU_STAT(efer_reload) },
141 { "fpu_reload", VCPU_STAT(fpu_reload) },
142 { "insn_emulation", VCPU_STAT(insn_emulation) },
143 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 144 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 145 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 146 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
147 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
148 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
149 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
150 { "mmu_flooded", VM_STAT(mmu_flooded) },
151 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 152 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 153 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 154 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 155 { "largepages", VM_STAT(lpages) },
417bc304
HB		 156 { NULL }
157};
158
2acf923e
DC		 159u64 __read_mostly host_xcr0;
160
d6aa1000
AK		 161int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
162
af585b92
GN		 163static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
164{
165 int i;
166 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
167 vcpu->arch.apf.gfns[i] = ~0;
168}
169
18863bdd
AK		 170static void kvm_on_user_return(struct user_return_notifier *urn)
171{
172 unsigned slot;
18863bdd
AK		 173 struct kvm_shared_msrs *locals
174 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 175 struct kvm_shared_msr_values *values;
18863bdd
AK		 176
177 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 178 values = &locals->values[slot];
179 if (values->host != values->curr) {
180 wrmsrl(shared_msrs_global.msrs[slot], values->host);
181 values->curr = values->host;
18863bdd
AK		 182 }
183 }
184 locals->registered = false;
185 user_return_notifier_unregister(urn);
186}
187
2bf78fa7 188static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 189{
2bf78fa7 190 struct kvm_shared_msrs *smsr;
18863bdd
AK		 191 u64 value;
192
2bf78fa7
SY		 193 smsr = &__get_cpu_var(shared_msrs);
194 /* only read, and nobody should modify it at this time,
195 * so don't need lock */
196 if (slot >= shared_msrs_global.nr) {
197 printk(KERN_ERR "kvm: invalid MSR slot!");
198 return;
199 }
200 rdmsrl_safe(msr, &value);
201 smsr->values[slot].host = value;
202 smsr->values[slot].curr = value;
203}
204
205void kvm_define_shared_msr(unsigned slot, u32 msr)
206{
18863bdd
AK		 207 if (slot >= shared_msrs_global.nr)
208 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 209 shared_msrs_global.msrs[slot] = msr;
210 /* we need ensured the shared_msr_global have been updated */
211 smp_wmb();
18863bdd
AK		 212}
213EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
214
215static void kvm_shared_msr_cpu_online(void)
216{
217 unsigned i;
18863bdd
AK		 218
219 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 220 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 221}
222
d5696725 223void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 224{
225 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
226
2bf78fa7 227 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 228 return;
2bf78fa7
SY		 229 smsr->values[slot].curr = value;
230 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 231 if (!smsr->registered) {
232 smsr->urn.on_user_return = kvm_on_user_return;
233 user_return_notifier_register(&smsr->urn);
234 smsr->registered = true;
235 }
236}
237EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
238
3548bab5
AK		 239static void drop_user_return_notifiers(void *ignore)
240{
241 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
242
243 if (smsr->registered)
244 kvm_on_user_return(&smsr->urn);
245}
246
6866b83e
CO		 247u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
248{
8a5a87d9 249 return vcpu->arch.apic_base;
6866b83e
CO		 250}
251EXPORT_SYMBOL_GPL(kvm_get_apic_base);
252
253void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
254{
255 /* TODO: reserve bits check */
8a5a87d9 256 kvm_lapic_set_base(vcpu, data);
6866b83e
CO		 257}
258EXPORT_SYMBOL_GPL(kvm_set_apic_base);
259
3fd28fce
ED		 260#define EXCPT_BENIGN 0
261#define EXCPT_CONTRIBUTORY 1
262#define EXCPT_PF 2
263
264static int exception_class(int vector)
265{
266 switch (vector) {
267 case PF_VECTOR:
268 return EXCPT_PF;
269 case DE_VECTOR:
270 case TS_VECTOR:
271 case NP_VECTOR:
272 case SS_VECTOR:
273 case GP_VECTOR:
274 return EXCPT_CONTRIBUTORY;
275 default:
276 break;
277 }
278 return EXCPT_BENIGN;
279}
280
281static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 282 unsigned nr, bool has_error, u32 error_code,
283 bool reinject)
3fd28fce
ED		 284{
285 u32 prev_nr;
286 int class1, class2;
287
3842d135
AK		 288 kvm_make_request(KVM_REQ_EVENT, vcpu);
289
3fd28fce
ED		 290 if (!vcpu->arch.exception.pending) {
291 queue:
292 vcpu->arch.exception.pending = true;
293 vcpu->arch.exception.has_error_code = has_error;
294 vcpu->arch.exception.nr = nr;
295 vcpu->arch.exception.error_code = error_code;
3f0fd292 296 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 297 return;
298 }
299
300 /* to check exception */
301 prev_nr = vcpu->arch.exception.nr;
302 if (prev_nr == DF_VECTOR) {
303 /* triple fault -> shutdown */
a8eeb04a 304 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 305 return;
306 }
307 class1 = exception_class(prev_nr);
308 class2 = exception_class(nr);
309 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
310 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
311 /* generate double fault per SDM Table 5-5 */
312 vcpu->arch.exception.pending = true;
313 vcpu->arch.exception.has_error_code = true;
314 vcpu->arch.exception.nr = DF_VECTOR;
315 vcpu->arch.exception.error_code = 0;
316 } else
317 /* replace previous exception with a new one in a hope
318 that instruction re-execution will regenerate lost
319 exception */
320 goto queue;
321}
322
298101da
AK		 323void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
324{
ce7ddec4 325 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 326}
327EXPORT_SYMBOL_GPL(kvm_queue_exception);
328
ce7ddec4
JR		 329void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
330{
331 kvm_multiple_exception(vcpu, nr, false, 0, true);
332}
333EXPORT_SYMBOL_GPL(kvm_requeue_exception);
334
db8fcefa 335void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 336{
db8fcefa
AP		 337 if (err)
338 kvm_inject_gp(vcpu, 0);
339 else
340 kvm_x86_ops->skip_emulated_instruction(vcpu);
341}
342EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 343
6389ee94 344void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 345{
346 ++vcpu->stat.pf_guest;
6389ee94
AK		 347 vcpu->arch.cr2 = fault->address;
348 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 349}
27d6c865 350EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 351
6389ee94 352void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 353{
6389ee94
AK		 354 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
355 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 356 else
6389ee94 357 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
d4f8cf66
JR		 358}
359
3419ffc8
SY		 360void kvm_inject_nmi(struct kvm_vcpu *vcpu)
361{
7460fb4a
AK		 362 atomic_inc(&vcpu->arch.nmi_queued);
363 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 364}
365EXPORT_SYMBOL_GPL(kvm_inject_nmi);
366
298101da
AK		 367void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
368{
ce7ddec4 369 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 370}
371EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
372
ce7ddec4
JR		 373void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
374{
375 kvm_multiple_exception(vcpu, nr, true, error_code, true);
376}
377EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
378
0a79b009
AK		 379/*
380 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
381 * a #GP and return false.
382 */
383bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 384{
0a79b009
AK		 385 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
386 return true;
387 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
388 return false;
298101da 389}
0a79b009 390EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 391
ec92fe44
JR		 392/*
393 * This function will be used to read from the physical memory of the currently
394 * running guest. The difference to kvm_read_guest_page is that this function
395 * can read from guest physical or from the guest's guest physical memory.
396 */
397int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
398 gfn_t ngfn, void *data, int offset, int len,
399 u32 access)
400{
401 gfn_t real_gfn;
402 gpa_t ngpa;
403
404 ngpa = gfn_to_gpa(ngfn);
405 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
406 if (real_gfn == UNMAPPED_GVA)
407 return -EFAULT;
408
409 real_gfn = gpa_to_gfn(real_gfn);
410
411 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
412}
413EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
414
3d06b8bf
JR		 415int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
416 void *data, int offset, int len, u32 access)
417{
418 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
419 data, offset, len, access);
420}
421
a03490ed
CO		 422/*
423 * Load the pae pdptrs. Return true is they are all valid.
424 */
ff03a073 425int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 426{
427 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
428 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
429 int i;
430 int ret;
ff03a073 431 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 432
ff03a073
JR		 433 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
434 offset * sizeof(u64), sizeof(pdpte),
435 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 436 if (ret < 0) {
437 ret = 0;
438 goto out;
439 }
440 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 441 if (is_present_gpte(pdpte[i]) &&
20c466b5 442 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 443 ret = 0;
444 goto out;
445 }
446 }
447 ret = 1;
448
ff03a073 449 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 450 __set_bit(VCPU_EXREG_PDPTR,
451 (unsigned long *)&vcpu->arch.regs_avail);
452 __set_bit(VCPU_EXREG_PDPTR,
453 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 454out:
a03490ed
CO		 455
456 return ret;
457}
cc4b6871 458EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 459
d835dfec
AK		 460static bool pdptrs_changed(struct kvm_vcpu *vcpu)
461{
ff03a073 462 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 463 bool changed = true;
3d06b8bf
JR		 464 int offset;
465 gfn_t gfn;
d835dfec
AK		 466 int r;
467
468 if (is_long_mode(vcpu) || !is_pae(vcpu))
469 return false;
470
6de4f3ad
AK		 471 if (!test_bit(VCPU_EXREG_PDPTR,
472 (unsigned long *)&vcpu->arch.regs_avail))
473 return true;
474
9f8fe504
AK		 475 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
476 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 477 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
478 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 479 if (r < 0)
480 goto out;
ff03a073 481 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 482out:
d835dfec
AK		 483
484 return changed;
485}
486
49a9b07e 487int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 488{
aad82703
SY		 489 unsigned long old_cr0 = kvm_read_cr0(vcpu);
490 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
491 X86_CR0_CD | X86_CR0_NW;
492
f9a48e6a
AK		 493 cr0 |= X86_CR0_ET;
494
ab344828 495#ifdef CONFIG_X86_64
0f12244f
GN		 496 if (cr0 & 0xffffffff00000000UL)
497 return 1;
ab344828
GN		 498#endif
499
500 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 501
0f12244f
GN		 502 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
503 return 1;
a03490ed 504
0f12244f
GN		 505 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
506 return 1;
a03490ed
CO		 507
508 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
509#ifdef CONFIG_X86_64
f6801dff 510 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 511 int cs_db, cs_l;
512
0f12244f
GN		 513 if (!is_pae(vcpu))
514 return 1;
a03490ed 515 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 516 if (cs_l)
517 return 1;
a03490ed
CO		 518 } else
519#endif
ff03a073 520 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 521 kvm_read_cr3(vcpu)))
0f12244f 522 return 1;
a03490ed
CO		 523 }
524
ad756a16
MJ		 525 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
526 return 1;
527
a03490ed 528 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 529
d170c419 530 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 531 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 532 kvm_async_pf_hash_reset(vcpu);
533 }
e5f3f027 534
aad82703
SY		 535 if ((cr0 ^ old_cr0) & update_bits)
536 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 537 return 0;
538}
2d3ad1f4 539EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 540
2d3ad1f4 541void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 542{
49a9b07e 543 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 544}
2d3ad1f4 545EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 546
2acf923e
DC		 547int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
548{
549 u64 xcr0;
550
551 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
552 if (index != XCR_XFEATURE_ENABLED_MASK)
553 return 1;
554 xcr0 = xcr;
555 if (kvm_x86_ops->get_cpl(vcpu) != 0)
556 return 1;
557 if (!(xcr0 & XSTATE_FP))
558 return 1;
559 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
560 return 1;
561 if (xcr0 & ~host_xcr0)
562 return 1;
563 vcpu->arch.xcr0 = xcr0;
564 vcpu->guest_xcr0_loaded = 0;
565 return 0;
566}
567
568int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
569{
570 if (__kvm_set_xcr(vcpu, index, xcr)) {
571 kvm_inject_gp(vcpu, 0);
572 return 1;
573 }
574 return 0;
575}
576EXPORT_SYMBOL_GPL(kvm_set_xcr);
577
a83b29c6 578int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 579{
fc78f519 580 unsigned long old_cr4 = kvm_read_cr4(vcpu);
c68b734f
YW		 581 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
582 X86_CR4_PAE | X86_CR4_SMEP;
0f12244f
GN		 583 if (cr4 & CR4_RESERVED_BITS)
584 return 1;
a03490ed 585
2acf923e
DC		 586 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
587 return 1;
588
c68b734f
YW		 589 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
590 return 1;
591
74dc2b4f
YW		 592 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_RDWRGSFS))
593 return 1;
594
a03490ed 595 if (is_long_mode(vcpu)) {
0f12244f
GN		 596 if (!(cr4 & X86_CR4_PAE))
597 return 1;
a2edf57f
AK		 598 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
599 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 600 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
601 kvm_read_cr3(vcpu)))
0f12244f
GN		 602 return 1;
603
ad756a16
MJ		 604 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
605 if (!guest_cpuid_has_pcid(vcpu))
606 return 1;
607
608 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
609 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
610 return 1;
611 }
612
5e1746d6 613 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 614 return 1;
a03490ed 615
ad756a16
MJ		 616 if (((cr4 ^ old_cr4) & pdptr_bits) ||
617 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 618 kvm_mmu_reset_context(vcpu);
0f12244f 619
2acf923e 620 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 621 kvm_update_cpuid(vcpu);
2acf923e 622
0f12244f
GN		 623 return 0;
624}
2d3ad1f4 625EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 626
2390218b 627int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 628{
9f8fe504 629 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 630 kvm_mmu_sync_roots(vcpu);
d835dfec 631 kvm_mmu_flush_tlb(vcpu);
0f12244f 632 return 0;
d835dfec
AK		 633 }
634
a03490ed 635 if (is_long_mode(vcpu)) {
ad756a16
MJ		 636 if (kvm_read_cr4(vcpu) & X86_CR4_PCIDE) {
637 if (cr3 & CR3_PCID_ENABLED_RESERVED_BITS)
638 return 1;
639 } else
640 if (cr3 & CR3_L_MODE_RESERVED_BITS)
641 return 1;
a03490ed
CO		 642 } else {
643 if (is_pae(vcpu)) {
0f12244f
GN		 644 if (cr3 & CR3_PAE_RESERVED_BITS)
645 return 1;
ff03a073
JR		 646 if (is_paging(vcpu) &&
647 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
0f12244f 648 return 1;
a03490ed
CO		 649 }
650 /*
651 * We don't check reserved bits in nonpae mode, because
652 * this isn't enforced, and VMware depends on this.
653 */
654 }
655
a03490ed
CO		 656 /*
657 * Does the new cr3 value map to physical memory? (Note, we
658 * catch an invalid cr3 even in real-mode, because it would
659 * cause trouble later on when we turn on paging anyway.)
660 *
661 * A real CPU would silently accept an invalid cr3 and would
662 * attempt to use it - with largely undefined (and often hard
663 * to debug) behavior on the guest side.
664 */
665 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
0f12244f
GN		 666 return 1;
667 vcpu->arch.cr3 = cr3;
aff48baa 668 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
0f12244f
GN		 669 vcpu->arch.mmu.new_cr3(vcpu);
670 return 0;
671}
2d3ad1f4 672EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 673
eea1cff9 674int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 675{
0f12244f
GN		 676 if (cr8 & CR8_RESERVED_BITS)
677 return 1;
a03490ed
CO		 678 if (irqchip_in_kernel(vcpu->kvm))
679 kvm_lapic_set_tpr(vcpu, cr8);
680 else
ad312c7c 681 vcpu->arch.cr8 = cr8;
0f12244f
GN		 682 return 0;
683}
2d3ad1f4 684EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 685
2d3ad1f4 686unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 687{
688 if (irqchip_in_kernel(vcpu->kvm))
689 return kvm_lapic_get_cr8(vcpu);
690 else
ad312c7c 691 return vcpu->arch.cr8;
a03490ed 692}
2d3ad1f4 693EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 694
338dbc97 695static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 696{
697 switch (dr) {
698 case 0 ... 3:
699 vcpu->arch.db[dr] = val;
700 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
701 vcpu->arch.eff_db[dr] = val;
702 break;
703 case 4:
338dbc97
GN		 704 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
705 return 1; /* #UD */
020df079
GN		 706 /* fall through */
707 case 6:
338dbc97
GN		 708 if (val & 0xffffffff00000000ULL)
709 return -1; /* #GP */
020df079
GN		 710 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
711 break;
712 case 5:
338dbc97
GN		 713 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
714 return 1; /* #UD */
020df079
GN		 715 /* fall through */
716 default: /* 7 */
338dbc97
GN		 717 if (val & 0xffffffff00000000ULL)
718 return -1; /* #GP */
020df079
GN		 719 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
720 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
721 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
722 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
723 }
724 break;
725 }
726
727 return 0;
728}
338dbc97
GN		 729
730int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
731{
732 int res;
733
734 res = __kvm_set_dr(vcpu, dr, val);
735 if (res > 0)
736 kvm_queue_exception(vcpu, UD_VECTOR);
737 else if (res < 0)
738 kvm_inject_gp(vcpu, 0);
739
740 return res;
741}
020df079
GN		 742EXPORT_SYMBOL_GPL(kvm_set_dr);
743
338dbc97 744static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 745{
746 switch (dr) {
747 case 0 ... 3:
748 *val = vcpu->arch.db[dr];
749 break;
750 case 4:
338dbc97 751 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 752 return 1;
020df079
GN		 753 /* fall through */
754 case 6:
755 *val = vcpu->arch.dr6;
756 break;
757 case 5:
338dbc97 758 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 759 return 1;
020df079
GN		 760 /* fall through */
761 default: /* 7 */
762 *val = vcpu->arch.dr7;
763 break;
764 }
765
766 return 0;
767}
338dbc97
GN		 768
769int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
770{
771 if (_kvm_get_dr(vcpu, dr, val)) {
772 kvm_queue_exception(vcpu, UD_VECTOR);
773 return 1;
774 }
775 return 0;
776}
020df079
GN		 777EXPORT_SYMBOL_GPL(kvm_get_dr);
778
022cd0e8
AK		 779bool kvm_rdpmc(struct kvm_vcpu *vcpu)
780{
781 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
782 u64 data;
783 int err;
784
785 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
786 if (err)
787 return err;
788 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
789 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
790 return err;
791}
792EXPORT_SYMBOL_GPL(kvm_rdpmc);
793
043405e1
CO		 794/*
795 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
796 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
797 *
798 * This list is modified at module load time to reflect the
e3267cbb
GC		 799 * capabilities of the host cpu. This capabilities test skips MSRs that are
800 * kvm-specific. Those are put in the beginning of the list.
043405e1 801 */
e3267cbb 802
e115676e 803#define KVM_SAVE_MSRS_BEGIN 10
043405e1 804static u32 msrs_to_save[] = {
e3267cbb 805 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 806 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 807 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
c9aaa895 808 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
ae7a2a3f 809 MSR_KVM_PV_EOI_EN,
043405e1 810 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 811 MSR_STAR,
043405e1
CO		 812#ifdef CONFIG_X86_64
813 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
814#endif
e90aa41e 815 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 816};
817
818static unsigned num_msrs_to_save;
819
f1d24831 820static const u32 emulated_msrs[] = {
a3e06bbe 821 MSR_IA32_TSCDEADLINE,
043405e1 822 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 823 MSR_IA32_MCG_STATUS,
824 MSR_IA32_MCG_CTL,
043405e1
CO		 825};
826
b69e8cae 827static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 828{
aad82703
SY		 829 u64 old_efer = vcpu->arch.efer;
830
b69e8cae
RJ		 831 if (efer & efer_reserved_bits)
832 return 1;
15c4a640
CO		 833
834 if (is_paging(vcpu)
b69e8cae
RJ		 835 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
836 return 1;
15c4a640 837
1b2fd70c
AG		 838 if (efer & EFER_FFXSR) {
839 struct kvm_cpuid_entry2 *feat;
840
841 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 842 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
843 return 1;
1b2fd70c
AG		 844 }
845
d8017474
AG		 846 if (efer & EFER_SVME) {
847 struct kvm_cpuid_entry2 *feat;
848
849 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 850 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
851 return 1;
d8017474
AG		 852 }
853
15c4a640 854 efer &= ~EFER_LMA;
f6801dff 855 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 856
a3d204e2
SY		 857 kvm_x86_ops->set_efer(vcpu, efer);
858
9645bb56 859 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
b69e8cae 860
aad82703
SY		 861 /* Update reserved bits */
862 if ((efer ^ old_efer) & EFER_NX)
863 kvm_mmu_reset_context(vcpu);
864
b69e8cae 865 return 0;
15c4a640
CO		 866}
867
f2b4b7dd
JR		 868void kvm_enable_efer_bits(u64 mask)
869{
870 efer_reserved_bits &= ~mask;
871}
872EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
873
874
15c4a640
CO		 875/*
876 * Writes msr value into into the appropriate "register".
877 * Returns 0 on success, non-0 otherwise.
878 * Assumes vcpu_load() was already called.
879 */
880int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
881{
882 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
883}
884
313a3dc7
CO		 885/*
886 * Adapt set_msr() to msr_io()'s calling convention
887 */
888static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
889{
890 return kvm_set_msr(vcpu, index, *data);
891}
892
18068523
GOC		 893static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
894{
9ed3c444
AK		 895 int version;
896 int r;
50d0a0f9 897 struct pvclock_wall_clock wc;
923de3cf 898 struct timespec boot;
18068523
GOC		 899
900 if (!wall_clock)
901 return;
902
9ed3c444
AK		 903 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
904 if (r)
905 return;
906
907 if (version & 1)
908 ++version; /* first time write, random junk */
909
910 ++version;
18068523 911
18068523
GOC		 912 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
913
50d0a0f9
GH		 914 /*
915 * The guest calculates current wall clock time by adding
34c238a1 916 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 917 * wall clock specified here. guest system time equals host
918 * system time for us, thus we must fill in host boot time here.
919 */
923de3cf 920 getboottime(&boot);
50d0a0f9 921
4b648665
BR		 922 if (kvm->arch.kvmclock_offset) {
923 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
924 boot = timespec_sub(boot, ts);
925 }
50d0a0f9
GH		 926 wc.sec = boot.tv_sec;
927 wc.nsec = boot.tv_nsec;
928 wc.version = version;
18068523
GOC		 929
930 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
931
932 version++;
933 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 934}
935
50d0a0f9
GH		 936static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
937{
938 uint32_t quotient, remainder;
939
940 /* Don't try to replace with do_div(), this one calculates
941 * "(dividend << 32) / divisor" */
942 __asm__ ( "divl %4"
943 : "=a" (quotient), "=d" (remainder)
944 : "0" (0), "1" (dividend), "r" (divisor) );
945 return quotient;
946}
947
5f4e3f88
ZA		 948static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
949 s8 *pshift, u32 *pmultiplier)
50d0a0f9 950{
5f4e3f88 951 uint64_t scaled64;
50d0a0f9
GH		 952 int32_t shift = 0;
953 uint64_t tps64;
954 uint32_t tps32;
955
5f4e3f88
ZA		 956 tps64 = base_khz * 1000LL;
957 scaled64 = scaled_khz * 1000LL;
50933623 958 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 959 tps64 >>= 1;
960 shift--;
961 }
962
963 tps32 = (uint32_t)tps64;
50933623
JK		 964 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
965 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 966 scaled64 >>= 1;
967 else
968 tps32 <<= 1;
50d0a0f9
GH		 969 shift++;
970 }
971
5f4e3f88
ZA		 972 *pshift = shift;
973 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 974
5f4e3f88
ZA		 975 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
976 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 977}
978
759379dd
ZA		 979static inline u64 get_kernel_ns(void)
980{
981 struct timespec ts;
982
983 WARN_ON(preemptible());
984 ktime_get_ts(&ts);
985 monotonic_to_bootbased(&ts);
986 return timespec_to_ns(&ts);
50d0a0f9
GH		 987}
988
c8076604 989static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 990unsigned long max_tsc_khz;
c8076604 991
cc578287 992static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 993{
cc578287
ZA		 994 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
995 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 996}
997
cc578287 998static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 999{
cc578287
ZA		 1000 u64 v = (u64)khz * (1000000 + ppm);
1001 do_div(v, 1000000);
1002 return v;
1e993611
JR		 1003}
1004
cc578287 1005static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1006{
cc578287
ZA		 1007 u32 thresh_lo, thresh_hi;
1008 int use_scaling = 0;
217fc9cf 1009
c285545f
ZA		 1010 /* Compute a scale to convert nanoseconds in TSC cycles */
1011 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1012 &vcpu->arch.virtual_tsc_shift,
1013 &vcpu->arch.virtual_tsc_mult);
1014 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1015
1016 /*
1017 * Compute the variation in TSC rate which is acceptable
1018 * within the range of tolerance and decide if the
1019 * rate being applied is within that bounds of the hardware
1020 * rate. If so, no scaling or compensation need be done.
1021 */
1022 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1023 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1024 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1025 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1026 use_scaling = 1;
1027 }
1028 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1029}
1030
1031static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1032{
e26101b1 1033 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1034 vcpu->arch.virtual_tsc_mult,
1035 vcpu->arch.virtual_tsc_shift);
e26101b1 1036 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1037 return tsc;
1038}
1039
99e3e30a
ZA		 1040void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
1041{
1042 struct kvm *kvm = vcpu->kvm;
f38e098f 1043 u64 offset, ns, elapsed;
99e3e30a 1044 unsigned long flags;
02626b6a 1045 s64 usdiff;
99e3e30a 1046
038f8c11 1047 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1048 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1049 ns = get_kernel_ns();
f38e098f 1050 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6
ZA		 1051
1052 /* n.b - signed multiplication and division required */
02626b6a 1053 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1054#ifdef CONFIG_X86_64
02626b6a 1055 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6
ZA		 1056#else
1057 /* do_div() only does unsigned */
1058 asm("idivl %2; xor %%edx, %%edx"
02626b6a
MT		 1059 : "=A"(usdiff)
1060 : "A"(usdiff * 1000), "rm"(vcpu->arch.virtual_tsc_khz));
5d3cb0f6 1061#endif
02626b6a
MT		 1062 do_div(elapsed, 1000);
1063 usdiff -= elapsed;
1064 if (usdiff < 0)
1065 usdiff = -usdiff;
f38e098f
ZA		 1066
1067 /*
5d3cb0f6
ZA		 1068 * Special case: TSC write with a small delta (1 second) of virtual
1069 * cycle time against real time is interpreted as an attempt to
1070 * synchronize the CPU.
1071 *
1072 * For a reliable TSC, we can match TSC offsets, and for an unstable
1073 * TSC, we add elapsed time in this computation. We could let the
1074 * compensation code attempt to catch up if we fall behind, but
1075 * it's better to try to match offsets from the beginning.
1076 */
02626b6a 1077 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1078 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1079 if (!check_tsc_unstable()) {
e26101b1 1080 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1081 pr_debug("kvm: matched tsc offset for %llu\n", data);
1082 } else {
857e4099 1083 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1084 data += delta;
1085 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1086 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1087 }
e26101b1
ZA		 1088 } else {
1089 /*
1090 * We split periods of matched TSC writes into generations.
1091 * For each generation, we track the original measured
1092 * nanosecond time, offset, and write, so if TSCs are in
1093 * sync, we can match exact offset, and if not, we can match
4a969980 1094 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1095 *
1096 * These values are tracked in kvm->arch.cur_xxx variables.
1097 */
1098 kvm->arch.cur_tsc_generation++;
1099 kvm->arch.cur_tsc_nsec = ns;
1100 kvm->arch.cur_tsc_write = data;
1101 kvm->arch.cur_tsc_offset = offset;
1102 pr_debug("kvm: new tsc generation %u, clock %llu\n",
1103 kvm->arch.cur_tsc_generation, data);
f38e098f 1104 }
e26101b1
ZA		 1105
1106 /*
1107 * We also track th most recent recorded KHZ, write and time to
1108 * allow the matching interval to be extended at each write.
1109 */
f38e098f
ZA		 1110 kvm->arch.last_tsc_nsec = ns;
1111 kvm->arch.last_tsc_write = data;
5d3cb0f6 1112 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a
ZA		 1113
1114 /* Reset of TSC must disable overshoot protection below */
1115 vcpu->arch.hv_clock.tsc_timestamp = 0;
b183aa58 1116 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1117
1118 /* Keep track of which generation this VCPU has synchronized to */
1119 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1120 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1121 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1122
1123 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1124 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
99e3e30a 1125}
e26101b1 1126
99e3e30a
ZA		 1127EXPORT_SYMBOL_GPL(kvm_write_tsc);
1128
34c238a1 1129static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1130{
18068523
GOC		 1131 unsigned long flags;
1132 struct kvm_vcpu_arch *vcpu = &v->arch;
1133 void *shared_kaddr;
463656c0 1134 unsigned long this_tsc_khz;
1d5f066e
ZA		 1135 s64 kernel_ns, max_kernel_ns;
1136 u64 tsc_timestamp;
51d59c6b 1137 u8 pvclock_flags;
18068523 1138
18068523
GOC		 1139 /* Keep irq disabled to prevent changes to the clock */
1140 local_irq_save(flags);
d5c1785d 1141 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v);
759379dd 1142 kernel_ns = get_kernel_ns();
cc578287 1143 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
8cfdc000 1144 if (unlikely(this_tsc_khz == 0)) {
c285545f 1145 local_irq_restore(flags);
34c238a1 1146 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
8cfdc000
ZA		 1147 return 1;
1148 }
18068523 1149
c285545f
ZA		 1150 /*
1151 * We may have to catch up the TSC to match elapsed wall clock
1152 * time for two reasons, even if kvmclock is used.
1153 * 1) CPU could have been running below the maximum TSC rate
1154 * 2) Broken TSC compensation resets the base at each VCPU
1155 * entry to avoid unknown leaps of TSC even when running
1156 * again on the same CPU. This may cause apparent elapsed
1157 * time to disappear, and the guest to stand still or run
1158 * very slowly.
1159 */
1160 if (vcpu->tsc_catchup) {
1161 u64 tsc = compute_guest_tsc(v, kernel_ns);
1162 if (tsc > tsc_timestamp) {
f1e2b260 1163 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1164 tsc_timestamp = tsc;
1165 }
50d0a0f9
GH		 1166 }
1167
18068523
GOC		 1168 local_irq_restore(flags);
1169
c285545f
ZA		 1170 if (!vcpu->time_page)
1171 return 0;
18068523 1172
1d5f066e
ZA		 1173 /*
1174 * Time as measured by the TSC may go backwards when resetting the base
1175 * tsc_timestamp. The reason for this is that the TSC resolution is
1176 * higher than the resolution of the other clock scales. Thus, many
1177 * possible measurments of the TSC correspond to one measurement of any
1178 * other clock, and so a spread of values is possible. This is not a
1179 * problem for the computation of the nanosecond clock; with TSC rates
1180 * around 1GHZ, there can only be a few cycles which correspond to one
1181 * nanosecond value, and any path through this code will inevitably
1182 * take longer than that. However, with the kernel_ns value itself,
1183 * the precision may be much lower, down to HZ granularity. If the
1184 * first sampling of TSC against kernel_ns ends in the low part of the
1185 * range, and the second in the high end of the range, we can get:
1186 *
1187 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1188 *
1189 * As the sampling errors potentially range in the thousands of cycles,
1190 * it is possible such a time value has already been observed by the
1191 * guest. To protect against this, we must compute the system time as
1192 * observed by the guest and ensure the new system time is greater.
1193 */
1194 max_kernel_ns = 0;
b183aa58 1195 if (vcpu->hv_clock.tsc_timestamp) {
1d5f066e
ZA		 1196 max_kernel_ns = vcpu->last_guest_tsc -
1197 vcpu->hv_clock.tsc_timestamp;
1198 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1199 vcpu->hv_clock.tsc_to_system_mul,
1200 vcpu->hv_clock.tsc_shift);
1201 max_kernel_ns += vcpu->last_kernel_ns;
1202 }
afbcf7ab 1203
e48672fa 1204 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1205 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1206 &vcpu->hv_clock.tsc_shift,
1207 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1208 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1209 }
1210
1d5f066e
ZA		 1211 if (max_kernel_ns > kernel_ns)
1212 kernel_ns = max_kernel_ns;
1213
8cfdc000 1214 /* With all the info we got, fill in the values */
1d5f066e 1215 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1216 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1d5f066e 1217 vcpu->last_kernel_ns = kernel_ns;
28e4639a 1218 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b
MT		 1219
1220 pvclock_flags = 0;
1221 if (vcpu->pvclock_set_guest_stopped_request) {
1222 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1223 vcpu->pvclock_set_guest_stopped_request = false;
1224 }
1225
1226 vcpu->hv_clock.flags = pvclock_flags;
371bcf64 1227
18068523
GOC		 1228 /*
1229 * The interface expects us to write an even number signaling that the
1230 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1231 * state, we just increase by 2 at the end.
18068523 1232 */
50d0a0f9 1233 vcpu->hv_clock.version += 2;
18068523 1234
8fd75e12 1235 shared_kaddr = kmap_atomic(vcpu->time_page);
18068523
GOC		 1236
1237 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 1238 sizeof(vcpu->hv_clock));
18068523 1239
8fd75e12 1240 kunmap_atomic(shared_kaddr);
18068523
GOC		 1241
1242 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
8cfdc000 1243 return 0;
c8076604
GH		 1244}
1245
9ba075a6
AK		 1246static bool msr_mtrr_valid(unsigned msr)
1247{
1248 switch (msr) {
1249 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1250 case MSR_MTRRfix64K_00000:
1251 case MSR_MTRRfix16K_80000:
1252 case MSR_MTRRfix16K_A0000:
1253 case MSR_MTRRfix4K_C0000:
1254 case MSR_MTRRfix4K_C8000:
1255 case MSR_MTRRfix4K_D0000:
1256 case MSR_MTRRfix4K_D8000:
1257 case MSR_MTRRfix4K_E0000:
1258 case MSR_MTRRfix4K_E8000:
1259 case MSR_MTRRfix4K_F0000:
1260 case MSR_MTRRfix4K_F8000:
1261 case MSR_MTRRdefType:
1262 case MSR_IA32_CR_PAT:
1263 return true;
1264 case 0x2f8:
1265 return true;
1266 }
1267 return false;
1268}
1269
d6289b93
MT		 1270static bool valid_pat_type(unsigned t)
1271{
1272 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1273}
1274
1275static bool valid_mtrr_type(unsigned t)
1276{
1277 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1278}
1279
1280static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1281{
1282 int i;
1283
1284 if (!msr_mtrr_valid(msr))
1285 return false;
1286
1287 if (msr == MSR_IA32_CR_PAT) {
1288 for (i = 0; i < 8; i++)
1289 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1290 return false;
1291 return true;
1292 } else if (msr == MSR_MTRRdefType) {
1293 if (data & ~0xcff)
1294 return false;
1295 return valid_mtrr_type(data & 0xff);
1296 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1297 for (i = 0; i < 8 ; i++)
1298 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1299 return false;
1300 return true;
1301 }
1302
1303 /* variable MTRRs */
1304 return valid_mtrr_type(data & 0xff);
1305}
1306
9ba075a6
AK		 1307static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1308{
0bed3b56
SY		 1309 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1310
d6289b93 1311 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1312 return 1;
1313
0bed3b56
SY		 1314 if (msr == MSR_MTRRdefType) {
1315 vcpu->arch.mtrr_state.def_type = data;
1316 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1317 } else if (msr == MSR_MTRRfix64K_00000)
1318 p[0] = data;
1319 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1320 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1321 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1322 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1323 else if (msr == MSR_IA32_CR_PAT)
1324 vcpu->arch.pat = data;
1325 else { /* Variable MTRRs */
1326 int idx, is_mtrr_mask;
1327 u64 *pt;
1328
1329 idx = (msr - 0x200) / 2;
1330 is_mtrr_mask = msr - 0x200 - 2 * idx;
1331 if (!is_mtrr_mask)
1332 pt =
1333 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1334 else
1335 pt =
1336 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1337 *pt = data;
1338 }
1339
1340 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1341 return 0;
1342}
15c4a640 1343
890ca9ae 1344static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1345{
890ca9ae
HY		 1346 u64 mcg_cap = vcpu->arch.mcg_cap;
1347 unsigned bank_num = mcg_cap & 0xff;
1348
15c4a640 1349 switch (msr) {
15c4a640 1350 case MSR_IA32_MCG_STATUS:
890ca9ae 1351 vcpu->arch.mcg_status = data;
15c4a640 1352 break;
c7ac679c 1353 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1354 if (!(mcg_cap & MCG_CTL_P))
1355 return 1;
1356 if (data != 0 && data != ~(u64)0)
1357 return -1;
1358 vcpu->arch.mcg_ctl = data;
1359 break;
1360 default:
1361 if (msr >= MSR_IA32_MC0_CTL &&
1362 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1363 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1364 /* only 0 or all 1s can be written to IA32_MCi_CTL
1365 * some Linux kernels though clear bit 10 in bank 4 to
1366 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1367 * this to avoid an uncatched #GP in the guest
1368 */
890ca9ae 1369 if ((offset & 0x3) == 0 &&
114be429 1370 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1371 return -1;
1372 vcpu->arch.mce_banks[offset] = data;
1373 break;
1374 }
1375 return 1;
1376 }
1377 return 0;
1378}
1379
ffde22ac
ES		 1380static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1381{
1382 struct kvm *kvm = vcpu->kvm;
1383 int lm = is_long_mode(vcpu);
1384 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1385 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1386 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1387 : kvm->arch.xen_hvm_config.blob_size_32;
1388 u32 page_num = data & ~PAGE_MASK;
1389 u64 page_addr = data & PAGE_MASK;
1390 u8 *page;
1391 int r;
1392
1393 r = -E2BIG;
1394 if (page_num >= blob_size)
1395 goto out;
1396 r = -ENOMEM;
ff5c2c03
SL		 1397 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1398 if (IS_ERR(page)) {
1399 r = PTR_ERR(page);
ffde22ac 1400 goto out;
ff5c2c03 1401 }
ffde22ac
ES		 1402 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1403 goto out_free;
1404 r = 0;
1405out_free:
1406 kfree(page);
1407out:
1408 return r;
1409}
1410
55cd8e5a
GN		 1411static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1412{
1413 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1414}
1415
1416static bool kvm_hv_msr_partition_wide(u32 msr)
1417{
1418 bool r = false;
1419 switch (msr) {
1420 case HV_X64_MSR_GUEST_OS_ID:
1421 case HV_X64_MSR_HYPERCALL:
1422 r = true;
1423 break;
1424 }
1425
1426 return r;
1427}
1428
1429static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1430{
1431 struct kvm *kvm = vcpu->kvm;
1432
1433 switch (msr) {
1434 case HV_X64_MSR_GUEST_OS_ID:
1435 kvm->arch.hv_guest_os_id = data;
1436 /* setting guest os id to zero disables hypercall page */
1437 if (!kvm->arch.hv_guest_os_id)
1438 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1439 break;
1440 case HV_X64_MSR_HYPERCALL: {
1441 u64 gfn;
1442 unsigned long addr;
1443 u8 instructions[4];
1444
1445 /* if guest os id is not set hypercall should remain disabled */
1446 if (!kvm->arch.hv_guest_os_id)
1447 break;
1448 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1449 kvm->arch.hv_hypercall = data;
1450 break;
1451 }
1452 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1453 addr = gfn_to_hva(kvm, gfn);
1454 if (kvm_is_error_hva(addr))
1455 return 1;
1456 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1457 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1458 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1459 return 1;
1460 kvm->arch.hv_hypercall = data;
1461 break;
1462 }
1463 default:
a737f256
CD		 1464 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1465 "data 0x%llx\n", msr, data);
55cd8e5a
GN		 1466 return 1;
1467 }
1468 return 0;
1469}
1470
1471static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1472{
10388a07
GN		 1473 switch (msr) {
1474 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1475 unsigned long addr;
55cd8e5a 1476
10388a07
GN		 1477 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1478 vcpu->arch.hv_vapic = data;
1479 break;
1480 }
1481 addr = gfn_to_hva(vcpu->kvm, data >>
1482 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1483 if (kvm_is_error_hva(addr))
1484 return 1;
8b0cedff 1485 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 1486 return 1;
1487 vcpu->arch.hv_vapic = data;
1488 break;
1489 }
1490 case HV_X64_MSR_EOI:
1491 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1492 case HV_X64_MSR_ICR:
1493 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1494 case HV_X64_MSR_TPR:
1495 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1496 default:
a737f256
CD		 1497 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1498 "data 0x%llx\n", msr, data);
10388a07
GN		 1499 return 1;
1500 }
1501
1502 return 0;
55cd8e5a
GN		 1503}
1504
344d9588
GN		 1505static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1506{
1507 gpa_t gpa = data & ~0x3f;
1508
4a969980 1509 /* Bits 2:5 are reserved, Should be zero */
6adba527 1510 if (data & 0x3c)
344d9588
GN		 1511 return 1;
1512
1513 vcpu->arch.apf.msr_val = data;
1514
1515 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1516 kvm_clear_async_pf_completion_queue(vcpu);
1517 kvm_async_pf_hash_reset(vcpu);
1518 return 0;
1519 }
1520
1521 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa))
1522 return 1;
1523
6adba527 1524 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1525 kvm_async_pf_wakeup_all(vcpu);
1526 return 0;
1527}
1528
12f9a48f
GC		 1529static void kvmclock_reset(struct kvm_vcpu *vcpu)
1530{
1531 if (vcpu->arch.time_page) {
1532 kvm_release_page_dirty(vcpu->arch.time_page);
1533 vcpu->arch.time_page = NULL;
1534 }
1535}
1536
c9aaa895
GC		 1537static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1538{
1539 u64 delta;
1540
1541 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1542 return;
1543
1544 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1545 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1546 vcpu->arch.st.accum_steal = delta;
1547}
1548
1549static void record_steal_time(struct kvm_vcpu *vcpu)
1550{
1551 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1552 return;
1553
1554 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1555 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1556 return;
1557
1558 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1559 vcpu->arch.st.steal.version += 2;
1560 vcpu->arch.st.accum_steal = 0;
1561
1562 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1563 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1564}
1565
15c4a640
CO		 1566int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1567{
5753785f
GN		 1568 bool pr = false;
1569
15c4a640 1570 switch (msr) {
15c4a640 1571 case MSR_EFER:
b69e8cae 1572 return set_efer(vcpu, data);
8f1589d9
AP		 1573 case MSR_K7_HWCR:
1574 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1575 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 1576 data &= ~(u64)0x8; /* ignore TLB cache disable */
8f1589d9 1577 if (data != 0) {
a737f256
CD		 1578 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1579 data);
8f1589d9
AP		 1580 return 1;
1581 }
15c4a640 1582 break;
f7c6d140
AP		 1583 case MSR_FAM10H_MMIO_CONF_BASE:
1584 if (data != 0) {
a737f256
CD		 1585 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1586 "0x%llx\n", data);
f7c6d140
AP		 1587 return 1;
1588 }
15c4a640 1589 break;
c323c0e5 1590 case MSR_AMD64_NB_CFG:
c7ac679c 1591 break;
b5e2fec0
AG		 1592 case MSR_IA32_DEBUGCTLMSR:
1593 if (!data) {
1594 /* We support the non-activated case already */
1595 break;
1596 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1597 /* Values other than LBR and BTF are vendor-specific,
1598 thus reserved and should throw a #GP */
1599 return 1;
1600 }
a737f256
CD		 1601 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1602 __func__, data);
b5e2fec0 1603 break;
15c4a640
CO		 1604 case MSR_IA32_UCODE_REV:
1605 case MSR_IA32_UCODE_WRITE:
61a6bd67 1606 case MSR_VM_HSAVE_PA:
6098ca93 1607 case MSR_AMD64_PATCH_LOADER:
15c4a640 1608 break;
9ba075a6
AK		 1609 case 0x200 ... 0x2ff:
1610 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1611 case MSR_IA32_APICBASE:
1612 kvm_set_apic_base(vcpu, data);
1613 break;
0105d1a5
GN		 1614 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1615 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 1616 case MSR_IA32_TSCDEADLINE:
1617 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1618 break;
15c4a640 1619 case MSR_IA32_MISC_ENABLE:
ad312c7c 1620 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1621 break;
11c6bffa 1622 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1623 case MSR_KVM_WALL_CLOCK:
1624 vcpu->kvm->arch.wall_clock = data;
1625 kvm_write_wall_clock(vcpu->kvm, data);
1626 break;
11c6bffa 1627 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 1628 case MSR_KVM_SYSTEM_TIME: {
12f9a48f 1629 kvmclock_reset(vcpu);
18068523
GOC		 1630
1631 vcpu->arch.time = data;
c285545f 1632 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
18068523
GOC		 1633
1634 /* we verify if the enable bit is set... */
1635 if (!(data & 1))
1636 break;
1637
1638 /* ...but clean it before doing the actual write */
1639 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1640
18068523
GOC		 1641 vcpu->arch.time_page =
1642 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523 1643
32cad84f 1644 if (is_error_page(vcpu->arch.time_page))
18068523 1645 vcpu->arch.time_page = NULL;
32cad84f 1646
18068523
GOC		 1647 break;
1648 }
344d9588
GN		 1649 case MSR_KVM_ASYNC_PF_EN:
1650 if (kvm_pv_enable_async_pf(vcpu, data))
1651 return 1;
1652 break;
c9aaa895
GC		 1653 case MSR_KVM_STEAL_TIME:
1654
1655 if (unlikely(!sched_info_on()))
1656 return 1;
1657
1658 if (data & KVM_STEAL_RESERVED_MASK)
1659 return 1;
1660
1661 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
1662 data & KVM_STEAL_VALID_BITS))
1663 return 1;
1664
1665 vcpu->arch.st.msr_val = data;
1666
1667 if (!(data & KVM_MSR_ENABLED))
1668 break;
1669
1670 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1671
1672 preempt_disable();
1673 accumulate_steal_time(vcpu);
1674 preempt_enable();
1675
1676 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
1677
1678 break;
ae7a2a3f
MT		 1679 case MSR_KVM_PV_EOI_EN:
1680 if (kvm_lapic_enable_pv_eoi(vcpu, data))
1681 return 1;
1682 break;
c9aaa895 1683
890ca9ae
HY		 1684 case MSR_IA32_MCG_CTL:
1685 case MSR_IA32_MCG_STATUS:
1686 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1687 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1688
1689 /* Performance counters are not protected by a CPUID bit,
1690 * so we should check all of them in the generic path for the sake of
1691 * cross vendor migration.
1692 * Writing a zero into the event select MSRs disables them,
1693 * which we perfectly emulate ;-). Any other value should be at least
1694 * reported, some guests depend on them.
1695 */
71db6023
AP		 1696 case MSR_K7_EVNTSEL0:
1697 case MSR_K7_EVNTSEL1:
1698 case MSR_K7_EVNTSEL2:
1699 case MSR_K7_EVNTSEL3:
1700 if (data != 0)
a737f256
CD		 1701 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1702 "0x%x data 0x%llx\n", msr, data);
71db6023
AP		 1703 break;
1704 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1705 * so we ignore writes to make it happy.
1706 */
71db6023
AP		 1707 case MSR_K7_PERFCTR0:
1708 case MSR_K7_PERFCTR1:
1709 case MSR_K7_PERFCTR2:
1710 case MSR_K7_PERFCTR3:
a737f256
CD		 1711 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1712 "0x%x data 0x%llx\n", msr, data);
71db6023 1713 break;
5753785f
GN		 1714 case MSR_P6_PERFCTR0:
1715 case MSR_P6_PERFCTR1:
1716 pr = true;
1717 case MSR_P6_EVNTSEL0:
1718 case MSR_P6_EVNTSEL1:
1719 if (kvm_pmu_msr(vcpu, msr))
1720 return kvm_pmu_set_msr(vcpu, msr, data);
1721
1722 if (pr || data != 0)
a737f256
CD		 1723 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
1724 "0x%x data 0x%llx\n", msr, data);
5753785f 1725 break;
84e0cefa
JS		 1726 case MSR_K7_CLK_CTL:
1727 /*
1728 * Ignore all writes to this no longer documented MSR.
1729 * Writes are only relevant for old K7 processors,
1730 * all pre-dating SVM, but a recommended workaround from
4a969980 1731 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 1732 * affected processor models on the command line, hence
1733 * the need to ignore the workaround.
1734 */
1735 break;
55cd8e5a
GN		 1736 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1737 if (kvm_hv_msr_partition_wide(msr)) {
1738 int r;
1739 mutex_lock(&vcpu->kvm->lock);
1740 r = set_msr_hyperv_pw(vcpu, msr, data);
1741 mutex_unlock(&vcpu->kvm->lock);
1742 return r;
1743 } else
1744 return set_msr_hyperv(vcpu, msr, data);
1745 break;
91c9c3ed 1746 case MSR_IA32_BBL_CR_CTL3:
1747 /* Drop writes to this legacy MSR -- see rdmsr
1748 * counterpart for further detail.
1749 */
a737f256 1750 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 1751 break;
2b036c6b
BO		 1752 case MSR_AMD64_OSVW_ID_LENGTH:
1753 if (!guest_cpuid_has_osvw(vcpu))
1754 return 1;
1755 vcpu->arch.osvw.length = data;
1756 break;
1757 case MSR_AMD64_OSVW_STATUS:
1758 if (!guest_cpuid_has_osvw(vcpu))
1759 return 1;
1760 vcpu->arch.osvw.status = data;
1761 break;
15c4a640 1762 default:
ffde22ac
ES		 1763 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1764 return xen_hvm_config(vcpu, data);
f5132b01
GN		 1765 if (kvm_pmu_msr(vcpu, msr))
1766 return kvm_pmu_set_msr(vcpu, msr, data);
ed85c068 1767 if (!ignore_msrs) {
a737f256
CD		 1768 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1769 msr, data);
ed85c068
AP		 1770 return 1;
1771 } else {
a737f256
CD		 1772 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1773 msr, data);
ed85c068
AP		 1774 break;
1775 }
15c4a640
CO		 1776 }
1777 return 0;
1778}
1779EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1780
1781
1782/*
1783 * Reads an msr value (of 'msr_index') into 'pdata'.
1784 * Returns 0 on success, non-0 otherwise.
1785 * Assumes vcpu_load() was already called.
1786 */
1787int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1788{
1789 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1790}
1791
9ba075a6
AK		 1792static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1793{
0bed3b56
SY		 1794 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1795
9ba075a6
AK		 1796 if (!msr_mtrr_valid(msr))
1797 return 1;
1798
0bed3b56
SY		 1799 if (msr == MSR_MTRRdefType)
1800 *pdata = vcpu->arch.mtrr_state.def_type +
1801 (vcpu->arch.mtrr_state.enabled << 10);
1802 else if (msr == MSR_MTRRfix64K_00000)
1803 *pdata = p[0];
1804 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1805 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1806 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1807 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1808 else if (msr == MSR_IA32_CR_PAT)
1809 *pdata = vcpu->arch.pat;
1810 else { /* Variable MTRRs */
1811 int idx, is_mtrr_mask;
1812 u64 *pt;
1813
1814 idx = (msr - 0x200) / 2;
1815 is_mtrr_mask = msr - 0x200 - 2 * idx;
1816 if (!is_mtrr_mask)
1817 pt =
1818 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1819 else
1820 pt =
1821 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1822 *pdata = *pt;
1823 }
1824
9ba075a6
AK		 1825 return 0;
1826}
1827
890ca9ae 1828static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1829{
1830 u64 data;
890ca9ae
HY		 1831 u64 mcg_cap = vcpu->arch.mcg_cap;
1832 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1833
1834 switch (msr) {
15c4a640
CO		 1835 case MSR_IA32_P5_MC_ADDR:
1836 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1837 data = 0;
1838 break;
15c4a640 1839 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1840 data = vcpu->arch.mcg_cap;
1841 break;
c7ac679c 1842 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1843 if (!(mcg_cap & MCG_CTL_P))
1844 return 1;
1845 data = vcpu->arch.mcg_ctl;
1846 break;
1847 case MSR_IA32_MCG_STATUS:
1848 data = vcpu->arch.mcg_status;
1849 break;
1850 default:
1851 if (msr >= MSR_IA32_MC0_CTL &&
1852 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1853 u32 offset = msr - MSR_IA32_MC0_CTL;
1854 data = vcpu->arch.mce_banks[offset];
1855 break;
1856 }
1857 return 1;
1858 }
1859 *pdata = data;
1860 return 0;
1861}
1862
55cd8e5a
GN		 1863static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1864{
1865 u64 data = 0;
1866 struct kvm *kvm = vcpu->kvm;
1867
1868 switch (msr) {
1869 case HV_X64_MSR_GUEST_OS_ID:
1870 data = kvm->arch.hv_guest_os_id;
1871 break;
1872 case HV_X64_MSR_HYPERCALL:
1873 data = kvm->arch.hv_hypercall;
1874 break;
1875 default:
a737f256 1876 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 1877 return 1;
1878 }
1879
1880 *pdata = data;
1881 return 0;
1882}
1883
1884static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1885{
1886 u64 data = 0;
1887
1888 switch (msr) {
1889 case HV_X64_MSR_VP_INDEX: {
1890 int r;
1891 struct kvm_vcpu *v;
1892 kvm_for_each_vcpu(r, v, vcpu->kvm)
1893 if (v == vcpu)
1894 data = r;
1895 break;
1896 }
10388a07
GN		 1897 case HV_X64_MSR_EOI:
1898 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1899 case HV_X64_MSR_ICR:
1900 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1901 case HV_X64_MSR_TPR:
1902 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 1903 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 1904 data = vcpu->arch.hv_vapic;
1905 break;
55cd8e5a 1906 default:
a737f256 1907 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 1908 return 1;
1909 }
1910 *pdata = data;
1911 return 0;
1912}
1913
890ca9ae
HY		 1914int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1915{
1916 u64 data;
1917
1918 switch (msr) {
890ca9ae 1919 case MSR_IA32_PLATFORM_ID:
15c4a640 1920 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1921 case MSR_IA32_DEBUGCTLMSR:
1922 case MSR_IA32_LASTBRANCHFROMIP:
1923 case MSR_IA32_LASTBRANCHTOIP:
1924 case MSR_IA32_LASTINTFROMIP:
1925 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1926 case MSR_K8_SYSCFG:
1927 case MSR_K7_HWCR:
61a6bd67 1928 case MSR_VM_HSAVE_PA:
9e699624 1929 case MSR_K7_EVNTSEL0:
1f3ee616 1930 case MSR_K7_PERFCTR0:
1fdbd48c 1931 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1932 case MSR_AMD64_NB_CFG:
f7c6d140 1933 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1934 data = 0;
1935 break;
5753785f
GN		 1936 case MSR_P6_PERFCTR0:
1937 case MSR_P6_PERFCTR1:
1938 case MSR_P6_EVNTSEL0:
1939 case MSR_P6_EVNTSEL1:
1940 if (kvm_pmu_msr(vcpu, msr))
1941 return kvm_pmu_get_msr(vcpu, msr, pdata);
1942 data = 0;
1943 break;
742bc670
MT		 1944 case MSR_IA32_UCODE_REV:
1945 data = 0x100000000ULL;
1946 break;
9ba075a6
AK		 1947 case MSR_MTRRcap:
1948 data = 0x500 | KVM_NR_VAR_MTRR;
1949 break;
1950 case 0x200 ... 0x2ff:
1951 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1952 case 0xcd: /* fsb frequency */
1953 data = 3;
1954 break;
7b914098
JS		 1955 /*
1956 * MSR_EBC_FREQUENCY_ID
1957 * Conservative value valid for even the basic CPU models.
1958 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
1959 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
1960 * and 266MHz for model 3, or 4. Set Core Clock
1961 * Frequency to System Bus Frequency Ratio to 1 (bits
1962 * 31:24) even though these are only valid for CPU
1963 * models > 2, however guests may end up dividing or
1964 * multiplying by zero otherwise.
1965 */
1966 case MSR_EBC_FREQUENCY_ID:
1967 data = 1 << 24;
1968 break;
15c4a640
CO		 1969 case MSR_IA32_APICBASE:
1970 data = kvm_get_apic_base(vcpu);
1971 break;
0105d1a5
GN		 1972 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1973 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1974 break;
a3e06bbe
LJ		 1975 case MSR_IA32_TSCDEADLINE:
1976 data = kvm_get_lapic_tscdeadline_msr(vcpu);
1977 break;
15c4a640 1978 case MSR_IA32_MISC_ENABLE:
ad312c7c 1979 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1980 break;
847f0ad8
AG		 1981 case MSR_IA32_PERF_STATUS:
1982 /* TSC increment by tick */
1983 data = 1000ULL;
1984 /* CPU multiplier */
1985 data |= (((uint64_t)4ULL) << 40);
1986 break;
15c4a640 1987 case MSR_EFER:
f6801dff 1988 data = vcpu->arch.efer;
15c4a640 1989 break;
18068523 1990 case MSR_KVM_WALL_CLOCK:
11c6bffa 1991 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1992 data = vcpu->kvm->arch.wall_clock;
1993 break;
1994 case MSR_KVM_SYSTEM_TIME:
11c6bffa 1995 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1996 data = vcpu->arch.time;
1997 break;
344d9588
GN		 1998 case MSR_KVM_ASYNC_PF_EN:
1999 data = vcpu->arch.apf.msr_val;
2000 break;
c9aaa895
GC		 2001 case MSR_KVM_STEAL_TIME:
2002 data = vcpu->arch.st.msr_val;
2003 break;
890ca9ae
HY		 2004 case MSR_IA32_P5_MC_ADDR:
2005 case MSR_IA32_P5_MC_TYPE:
2006 case MSR_IA32_MCG_CAP:
2007 case MSR_IA32_MCG_CTL:
2008 case MSR_IA32_MCG_STATUS:
2009 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2010 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 2011 case MSR_K7_CLK_CTL:
2012 /*
2013 * Provide expected ramp-up count for K7. All other
2014 * are set to zero, indicating minimum divisors for
2015 * every field.
2016 *
2017 * This prevents guest kernels on AMD host with CPU
2018 * type 6, model 8 and higher from exploding due to
2019 * the rdmsr failing.
2020 */
2021 data = 0x20000000;
2022 break;
55cd8e5a
GN		 2023 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2024 if (kvm_hv_msr_partition_wide(msr)) {
2025 int r;
2026 mutex_lock(&vcpu->kvm->lock);
2027 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2028 mutex_unlock(&vcpu->kvm->lock);
2029 return r;
2030 } else
2031 return get_msr_hyperv(vcpu, msr, pdata);
2032 break;
91c9c3ed 2033 case MSR_IA32_BBL_CR_CTL3:
2034 /* This legacy MSR exists but isn't fully documented in current
2035 * silicon. It is however accessed by winxp in very narrow
2036 * scenarios where it sets bit #19, itself documented as
2037 * a "reserved" bit. Best effort attempt to source coherent
2038 * read data here should the balance of the register be
2039 * interpreted by the guest:
2040 *
2041 * L2 cache control register 3: 64GB range, 256KB size,
2042 * enabled, latency 0x1, configured
2043 */
2044 data = 0xbe702111;
2045 break;
2b036c6b
BO		 2046 case MSR_AMD64_OSVW_ID_LENGTH:
2047 if (!guest_cpuid_has_osvw(vcpu))
2048 return 1;
2049 data = vcpu->arch.osvw.length;
2050 break;
2051 case MSR_AMD64_OSVW_STATUS:
2052 if (!guest_cpuid_has_osvw(vcpu))
2053 return 1;
2054 data = vcpu->arch.osvw.status;
2055 break;
15c4a640 2056 default:
f5132b01
GN		 2057 if (kvm_pmu_msr(vcpu, msr))
2058 return kvm_pmu_get_msr(vcpu, msr, pdata);
ed85c068 2059 if (!ignore_msrs) {
a737f256 2060 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
ed85c068
AP		 2061 return 1;
2062 } else {
a737f256 2063 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
ed85c068
AP		 2064 data = 0;
2065 }
2066 break;
15c4a640
CO		 2067 }
2068 *pdata = data;
2069 return 0;
2070}
2071EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2072
313a3dc7
CO		 2073/*
2074 * Read or write a bunch of msrs. All parameters are kernel addresses.
2075 *
2076 * @return number of msrs set successfully.
2077 */
2078static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2079 struct kvm_msr_entry *entries,
2080 int (*do_msr)(struct kvm_vcpu *vcpu,
2081 unsigned index, u64 *data))
2082{
f656ce01 2083 int i, idx;
313a3dc7 2084
f656ce01 2085 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2086 for (i = 0; i < msrs->nmsrs; ++i)
2087 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2088 break;
f656ce01 2089 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2090
313a3dc7
CO		 2091 return i;
2092}
2093
2094/*
2095 * Read or write a bunch of msrs. Parameters are user addresses.
2096 *
2097 * @return number of msrs set successfully.
2098 */
2099static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2100 int (*do_msr)(struct kvm_vcpu *vcpu,
2101 unsigned index, u64 *data),
2102 int writeback)
2103{
2104 struct kvm_msrs msrs;
2105 struct kvm_msr_entry *entries;
2106 int r, n;
2107 unsigned size;
2108
2109 r = -EFAULT;
2110 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2111 goto out;
2112
2113 r = -E2BIG;
2114 if (msrs.nmsrs >= MAX_IO_MSRS)
2115 goto out;
2116
313a3dc7 2117 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2118 entries = memdup_user(user_msrs->entries, size);
2119 if (IS_ERR(entries)) {
2120 r = PTR_ERR(entries);
313a3dc7 2121 goto out;
ff5c2c03 2122 }
313a3dc7
CO		 2123
2124 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2125 if (r < 0)
2126 goto out_free;
2127
2128 r = -EFAULT;
2129 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2130 goto out_free;
2131
2132 r = n;
2133
2134out_free:
7a73c028 2135 kfree(entries);
313a3dc7
CO		 2136out:
2137 return r;
2138}
2139
018d00d2
ZX		 2140int kvm_dev_ioctl_check_extension(long ext)
2141{
2142 int r;
2143
2144 switch (ext) {
2145 case KVM_CAP_IRQCHIP:
2146 case KVM_CAP_HLT:
2147 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2148 case KVM_CAP_SET_TSS_ADDR:
07716717 2149 case KVM_CAP_EXT_CPUID:
c8076604 2150 case KVM_CAP_CLOCKSOURCE:
7837699f 2151 case KVM_CAP_PIT:
a28e4f5a 2152 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2153 case KVM_CAP_MP_STATE:
ed848624 2154 case KVM_CAP_SYNC_MMU:
a355c85c 2155 case KVM_CAP_USER_NMI:
52d939a0 2156 case KVM_CAP_REINJECT_CONTROL:
4925663a 2157 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 2158 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 2159 case KVM_CAP_IRQFD:
d34e6b17 2160 case KVM_CAP_IOEVENTFD:
c5ff41ce 2161 case KVM_CAP_PIT2:
e9f42757 2162 case KVM_CAP_PIT_STATE2:
b927a3ce 2163 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2164 case KVM_CAP_XEN_HVM:
afbcf7ab 2165 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2166 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2167 case KVM_CAP_HYPERV:
10388a07 2168 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2169 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2170 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2171 case KVM_CAP_DEBUGREGS:
d2be1651 2172 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2173 case KVM_CAP_XSAVE:
344d9588 2174 case KVM_CAP_ASYNC_PF:
92a1f12d 2175 case KVM_CAP_GET_TSC_KHZ:
07700a94 2176 case KVM_CAP_PCI_2_3:
1c0b28c2 2177 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2178 case KVM_CAP_READONLY_MEM:
018d00d2
ZX		 2179 r = 1;
2180 break;
542472b5
LV		 2181 case KVM_CAP_COALESCED_MMIO:
2182 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2183 break;
774ead3a
AK		 2184 case KVM_CAP_VAPIC:
2185 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2186 break;
f725230a 2187 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2188 r = KVM_SOFT_MAX_VCPUS;
2189 break;
2190 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2191 r = KVM_MAX_VCPUS;
2192 break;
a988b910
AK		 2193 case KVM_CAP_NR_MEMSLOTS:
2194 r = KVM_MEMORY_SLOTS;
2195 break;
a68a6a72
MT		 2196 case KVM_CAP_PV_MMU: /* obsolete */
2197 r = 0;
2f333bcb 2198 break;
62c476c7 2199 case KVM_CAP_IOMMU:
a1b60c1c 2200 r = iommu_present(&pci_bus_type);
62c476c7 2201 break;
890ca9ae
HY		 2202 case KVM_CAP_MCE:
2203 r = KVM_MAX_MCE_BANKS;
2204 break;
2d5b5a66
SY		 2205 case KVM_CAP_XCRS:
2206 r = cpu_has_xsave;
2207 break;
92a1f12d
JR		 2208 case KVM_CAP_TSC_CONTROL:
2209 r = kvm_has_tsc_control;
2210 break;
4d25a066
JK		 2211 case KVM_CAP_TSC_DEADLINE_TIMER:
2212 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2213 break;
018d00d2
ZX		 2214 default:
2215 r = 0;
2216 break;
2217 }
2218 return r;
2219
2220}
2221
043405e1
CO		 2222long kvm_arch_dev_ioctl(struct file *filp,
2223 unsigned int ioctl, unsigned long arg)
2224{
2225 void __user *argp = (void __user *)arg;
2226 long r;
2227
2228 switch (ioctl) {
2229 case KVM_GET_MSR_INDEX_LIST: {
2230 struct kvm_msr_list __user *user_msr_list = argp;
2231 struct kvm_msr_list msr_list;
2232 unsigned n;
2233
2234 r = -EFAULT;
2235 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2236 goto out;
2237 n = msr_list.nmsrs;
2238 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2239 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2240 goto out;
2241 r = -E2BIG;
e125e7b6 2242 if (n < msr_list.nmsrs)
043405e1
CO		 2243 goto out;
2244 r = -EFAULT;
2245 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2246 num_msrs_to_save * sizeof(u32)))
2247 goto out;
e125e7b6 2248 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2249 &emulated_msrs,
2250 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2251 goto out;
2252 r = 0;
2253 break;
2254 }
674eea0f
AK		 2255 case KVM_GET_SUPPORTED_CPUID: {
2256 struct kvm_cpuid2 __user *cpuid_arg = argp;
2257 struct kvm_cpuid2 cpuid;
2258
2259 r = -EFAULT;
2260 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2261 goto out;
2262 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 2263 cpuid_arg->entries);
674eea0f
AK		 2264 if (r)
2265 goto out;
2266
2267 r = -EFAULT;
2268 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2269 goto out;
2270 r = 0;
2271 break;
2272 }
890ca9ae
HY		 2273 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2274 u64 mce_cap;
2275
2276 mce_cap = KVM_MCE_CAP_SUPPORTED;
2277 r = -EFAULT;
2278 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2279 goto out;
2280 r = 0;
2281 break;
2282 }
043405e1
CO		 2283 default:
2284 r = -EINVAL;
2285 }
2286out:
2287 return r;
2288}
2289
f5f48ee1
SY		 2290static void wbinvd_ipi(void *garbage)
2291{
2292 wbinvd();
2293}
2294
2295static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2296{
2297 return vcpu->kvm->arch.iommu_domain &&
2298 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2299}
2300
313a3dc7
CO		 2301void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2302{
f5f48ee1
SY		 2303 /* Address WBINVD may be executed by guest */
2304 if (need_emulate_wbinvd(vcpu)) {
2305 if (kvm_x86_ops->has_wbinvd_exit())
2306 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2307 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2308 smp_call_function_single(vcpu->cpu,
2309 wbinvd_ipi, NULL, 1);
2310 }
2311
313a3dc7 2312 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2313
0dd6a6ed
ZA		 2314 /* Apply any externally detected TSC adjustments (due to suspend) */
2315 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2316 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2317 vcpu->arch.tsc_offset_adjustment = 0;
2318 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2319 }
8f6055cb 2320
48434c20 2321 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5
ZA		 2322 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2323 native_read_tsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2324 if (tsc_delta < 0)
2325 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2326 if (check_tsc_unstable()) {
b183aa58
ZA		 2327 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2328 vcpu->arch.last_guest_tsc);
2329 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2330 vcpu->arch.tsc_catchup = 1;
c285545f 2331 }
1aa8ceef 2332 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2333 if (vcpu->cpu != cpu)
2334 kvm_migrate_timers(vcpu);
e48672fa 2335 vcpu->cpu = cpu;
6b7d7e76 2336 }
c9aaa895
GC		 2337
2338 accumulate_steal_time(vcpu);
2339 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2340}
2341
2342void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2343{
02daab21 2344 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2345 kvm_put_guest_fpu(vcpu);
6f526ec5 2346 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2347}
2348
313a3dc7
CO		 2349static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2350 struct kvm_lapic_state *s)
2351{
ad312c7c 2352 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2353
2354 return 0;
2355}
2356
2357static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2358 struct kvm_lapic_state *s)
2359{
64eb0620 2360 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2361 update_cr8_intercept(vcpu);
313a3dc7
CO		 2362
2363 return 0;
2364}
2365
f77bc6a4
ZX		 2366static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2367 struct kvm_interrupt *irq)
2368{
2369 if (irq->irq < 0 || irq->irq >= 256)
2370 return -EINVAL;
2371 if (irqchip_in_kernel(vcpu->kvm))
2372 return -ENXIO;
f77bc6a4 2373
66fd3f7f 2374 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2375 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2376
f77bc6a4
ZX		 2377 return 0;
2378}
2379
c4abb7c9
JK		 2380static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2381{
c4abb7c9 2382 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2383
2384 return 0;
2385}
2386
b209749f
AK		 2387static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2388 struct kvm_tpr_access_ctl *tac)
2389{
2390 if (tac->flags)
2391 return -EINVAL;
2392 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2393 return 0;
2394}
2395
890ca9ae
HY		 2396static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2397 u64 mcg_cap)
2398{
2399 int r;
2400 unsigned bank_num = mcg_cap & 0xff, bank;
2401
2402 r = -EINVAL;
a9e38c3e 2403 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2404 goto out;
2405 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2406 goto out;
2407 r = 0;
2408 vcpu->arch.mcg_cap = mcg_cap;
2409 /* Init IA32_MCG_CTL to all 1s */
2410 if (mcg_cap & MCG_CTL_P)
2411 vcpu->arch.mcg_ctl = ~(u64)0;
2412 /* Init IA32_MCi_CTL to all 1s */
2413 for (bank = 0; bank < bank_num; bank++)
2414 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2415out:
2416 return r;
2417}
2418
2419static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2420 struct kvm_x86_mce *mce)
2421{
2422 u64 mcg_cap = vcpu->arch.mcg_cap;
2423 unsigned bank_num = mcg_cap & 0xff;
2424 u64 *banks = vcpu->arch.mce_banks;
2425
2426 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2427 return -EINVAL;
2428 /*
2429 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2430 * reporting is disabled
2431 */
2432 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2433 vcpu->arch.mcg_ctl != ~(u64)0)
2434 return 0;
2435 banks += 4 * mce->bank;
2436 /*
2437 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2438 * reporting is disabled for the bank
2439 */
2440 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2441 return 0;
2442 if (mce->status & MCI_STATUS_UC) {
2443 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2444 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2445 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2446 return 0;
2447 }
2448 if (banks[1] & MCI_STATUS_VAL)
2449 mce->status |= MCI_STATUS_OVER;
2450 banks[2] = mce->addr;
2451 banks[3] = mce->misc;
2452 vcpu->arch.mcg_status = mce->mcg_status;
2453 banks[1] = mce->status;
2454 kvm_queue_exception(vcpu, MC_VECTOR);
2455 } else if (!(banks[1] & MCI_STATUS_VAL)
2456 || !(banks[1] & MCI_STATUS_UC)) {
2457 if (banks[1] & MCI_STATUS_VAL)
2458 mce->status |= MCI_STATUS_OVER;
2459 banks[2] = mce->addr;
2460 banks[3] = mce->misc;
2461 banks[1] = mce->status;
2462 } else
2463 banks[1] |= MCI_STATUS_OVER;
2464 return 0;
2465}
2466
3cfc3092
JK		 2467static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2468 struct kvm_vcpu_events *events)
2469{
7460fb4a 2470 process_nmi(vcpu);
03b82a30
JK		 2471 events->exception.injected =
2472 vcpu->arch.exception.pending &&
2473 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2474 events->exception.nr = vcpu->arch.exception.nr;
2475 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2476 events->exception.pad = 0;
3cfc3092
JK		 2477 events->exception.error_code = vcpu->arch.exception.error_code;
2478
03b82a30
JK		 2479 events->interrupt.injected =
2480 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2481 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2482 events->interrupt.soft = 0;
48005f64
JK		 2483 events->interrupt.shadow =
2484 kvm_x86_ops->get_interrupt_shadow(vcpu,
2485 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2486
2487 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2488 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2489 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2490 events->nmi.pad = 0;
3cfc3092
JK		 2491
2492 events->sipi_vector = vcpu->arch.sipi_vector;
2493
dab4b911 2494 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2495 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2496 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 2497 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2498}
2499
2500static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2501 struct kvm_vcpu_events *events)
2502{
dab4b911 2503 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2504 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2505 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2506 return -EINVAL;
2507
7460fb4a 2508 process_nmi(vcpu);
3cfc3092
JK		 2509 vcpu->arch.exception.pending = events->exception.injected;
2510 vcpu->arch.exception.nr = events->exception.nr;
2511 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2512 vcpu->arch.exception.error_code = events->exception.error_code;
2513
2514 vcpu->arch.interrupt.pending = events->interrupt.injected;
2515 vcpu->arch.interrupt.nr = events->interrupt.nr;
2516 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2517 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2518 kvm_x86_ops->set_interrupt_shadow(vcpu,
2519 events->interrupt.shadow);
3cfc3092
JK		 2520
2521 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2522 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2523 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2524 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2525
dab4b911
JK		 2526 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2527 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092 2528
3842d135
AK		 2529 kvm_make_request(KVM_REQ_EVENT, vcpu);
2530
3cfc3092
JK		 2531 return 0;
2532}
2533
a1efbe77
JK		 2534static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2535 struct kvm_debugregs *dbgregs)
2536{
a1efbe77
JK		 2537 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2538 dbgregs->dr6 = vcpu->arch.dr6;
2539 dbgregs->dr7 = vcpu->arch.dr7;
2540 dbgregs->flags = 0;
97e69aa6 2541 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 2542}
2543
2544static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2545 struct kvm_debugregs *dbgregs)
2546{
2547 if (dbgregs->flags)
2548 return -EINVAL;
2549
a1efbe77
JK		 2550 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2551 vcpu->arch.dr6 = dbgregs->dr6;
2552 vcpu->arch.dr7 = dbgregs->dr7;
2553
a1efbe77
JK		 2554 return 0;
2555}
2556
2d5b5a66
SY		 2557static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2558 struct kvm_xsave *guest_xsave)
2559{
2560 if (cpu_has_xsave)
2561 memcpy(guest_xsave->region,
2562 &vcpu->arch.guest_fpu.state->xsave,
f45755b8 2563 xstate_size);
2d5b5a66
SY		 2564 else {
2565 memcpy(guest_xsave->region,
2566 &vcpu->arch.guest_fpu.state->fxsave,
2567 sizeof(struct i387_fxsave_struct));
2568 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2569 XSTATE_FPSSE;
2570 }
2571}
2572
2573static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2574 struct kvm_xsave *guest_xsave)
2575{
2576 u64 xstate_bv =
2577 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2578
2579 if (cpu_has_xsave)
2580 memcpy(&vcpu->arch.guest_fpu.state->xsave,
f45755b8 2581 guest_xsave->region, xstate_size);
2d5b5a66
SY		 2582 else {
2583 if (xstate_bv & ~XSTATE_FPSSE)
2584 return -EINVAL;
2585 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2586 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2587 }
2588 return 0;
2589}
2590
2591static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2592 struct kvm_xcrs *guest_xcrs)
2593{
2594 if (!cpu_has_xsave) {
2595 guest_xcrs->nr_xcrs = 0;
2596 return;
2597 }
2598
2599 guest_xcrs->nr_xcrs = 1;
2600 guest_xcrs->flags = 0;
2601 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2602 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2603}
2604
2605static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2606 struct kvm_xcrs *guest_xcrs)
2607{
2608 int i, r = 0;
2609
2610 if (!cpu_has_xsave)
2611 return -EINVAL;
2612
2613 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2614 return -EINVAL;
2615
2616 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2617 /* Only support XCR0 currently */
2618 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2619 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2620 guest_xcrs->xcrs[0].value);
2621 break;
2622 }
2623 if (r)
2624 r = -EINVAL;
2625 return r;
2626}
2627
1c0b28c2
EM		 2628/*
2629 * kvm_set_guest_paused() indicates to the guest kernel that it has been
2630 * stopped by the hypervisor. This function will be called from the host only.
2631 * EINVAL is returned when the host attempts to set the flag for a guest that
2632 * does not support pv clocks.
2633 */
2634static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
2635{
1c0b28c2
EM		 2636 if (!vcpu->arch.time_page)
2637 return -EINVAL;
51d59c6b 2638 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 2639 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2640 return 0;
2641}
2642
313a3dc7
CO		 2643long kvm_arch_vcpu_ioctl(struct file *filp,
2644 unsigned int ioctl, unsigned long arg)
2645{
2646 struct kvm_vcpu *vcpu = filp->private_data;
2647 void __user *argp = (void __user *)arg;
2648 int r;
d1ac91d8
AK		 2649 union {
2650 struct kvm_lapic_state *lapic;
2651 struct kvm_xsave *xsave;
2652 struct kvm_xcrs *xcrs;
2653 void *buffer;
2654 } u;
2655
2656 u.buffer = NULL;
313a3dc7
CO		 2657 switch (ioctl) {
2658 case KVM_GET_LAPIC: {
2204ae3c
MT		 2659 r = -EINVAL;
2660 if (!vcpu->arch.apic)
2661 goto out;
d1ac91d8 2662 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2663
b772ff36 2664 r = -ENOMEM;
d1ac91d8 2665 if (!u.lapic)
b772ff36 2666 goto out;
d1ac91d8 2667 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 2668 if (r)
2669 goto out;
2670 r = -EFAULT;
d1ac91d8 2671 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2672 goto out;
2673 r = 0;
2674 break;
2675 }
2676 case KVM_SET_LAPIC: {
2204ae3c
MT		 2677 r = -EINVAL;
2678 if (!vcpu->arch.apic)
2679 goto out;
ff5c2c03
SL		 2680 u.lapic = memdup_user(argp, sizeof(*u.lapic));
2681 if (IS_ERR(u.lapic)) {
2682 r = PTR_ERR(u.lapic);
313a3dc7 2683 goto out;
ff5c2c03
SL		 2684 }
2685
d1ac91d8 2686 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 2687 if (r)
2688 goto out;
2689 r = 0;
2690 break;
2691 }
f77bc6a4
ZX		 2692 case KVM_INTERRUPT: {
2693 struct kvm_interrupt irq;
2694
2695 r = -EFAULT;
2696 if (copy_from_user(&irq, argp, sizeof irq))
2697 goto out;
2698 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2699 if (r)
2700 goto out;
2701 r = 0;
2702 break;
2703 }
c4abb7c9
JK		 2704 case KVM_NMI: {
2705 r = kvm_vcpu_ioctl_nmi(vcpu);
2706 if (r)
2707 goto out;
2708 r = 0;
2709 break;
2710 }
313a3dc7
CO		 2711 case KVM_SET_CPUID: {
2712 struct kvm_cpuid __user *cpuid_arg = argp;
2713 struct kvm_cpuid cpuid;
2714
2715 r = -EFAULT;
2716 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2717 goto out;
2718 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2719 if (r)
2720 goto out;
2721 break;
2722 }
07716717
DK		 2723 case KVM_SET_CPUID2: {
2724 struct kvm_cpuid2 __user *cpuid_arg = argp;
2725 struct kvm_cpuid2 cpuid;
2726
2727 r = -EFAULT;
2728 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2729 goto out;
2730 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2731 cpuid_arg->entries);
07716717
DK		 2732 if (r)
2733 goto out;
2734 break;
2735 }
2736 case KVM_GET_CPUID2: {
2737 struct kvm_cpuid2 __user *cpuid_arg = argp;
2738 struct kvm_cpuid2 cpuid;
2739
2740 r = -EFAULT;
2741 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2742 goto out;
2743 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2744 cpuid_arg->entries);
07716717
DK		 2745 if (r)
2746 goto out;
2747 r = -EFAULT;
2748 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2749 goto out;
2750 r = 0;
2751 break;
2752 }
313a3dc7
CO		 2753 case KVM_GET_MSRS:
2754 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2755 break;
2756 case KVM_SET_MSRS:
2757 r = msr_io(vcpu, argp, do_set_msr, 0);
2758 break;
b209749f
AK		 2759 case KVM_TPR_ACCESS_REPORTING: {
2760 struct kvm_tpr_access_ctl tac;
2761
2762 r = -EFAULT;
2763 if (copy_from_user(&tac, argp, sizeof tac))
2764 goto out;
2765 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2766 if (r)
2767 goto out;
2768 r = -EFAULT;
2769 if (copy_to_user(argp, &tac, sizeof tac))
2770 goto out;
2771 r = 0;
2772 break;
2773 };
b93463aa
AK		 2774 case KVM_SET_VAPIC_ADDR: {
2775 struct kvm_vapic_addr va;
2776
2777 r = -EINVAL;
2778 if (!irqchip_in_kernel(vcpu->kvm))
2779 goto out;
2780 r = -EFAULT;
2781 if (copy_from_user(&va, argp, sizeof va))
2782 goto out;
2783 r = 0;
2784 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2785 break;
2786 }
890ca9ae
HY		 2787 case KVM_X86_SETUP_MCE: {
2788 u64 mcg_cap;
2789
2790 r = -EFAULT;
2791 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2792 goto out;
2793 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2794 break;
2795 }
2796 case KVM_X86_SET_MCE: {
2797 struct kvm_x86_mce mce;
2798
2799 r = -EFAULT;
2800 if (copy_from_user(&mce, argp, sizeof mce))
2801 goto out;
2802 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2803 break;
2804 }
3cfc3092
JK		 2805 case KVM_GET_VCPU_EVENTS: {
2806 struct kvm_vcpu_events events;
2807
2808 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2809
2810 r = -EFAULT;
2811 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2812 break;
2813 r = 0;
2814 break;
2815 }
2816 case KVM_SET_VCPU_EVENTS: {
2817 struct kvm_vcpu_events events;
2818
2819 r = -EFAULT;
2820 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2821 break;
2822
2823 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2824 break;
2825 }
a1efbe77
JK		 2826 case KVM_GET_DEBUGREGS: {
2827 struct kvm_debugregs dbgregs;
2828
2829 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2830
2831 r = -EFAULT;
2832 if (copy_to_user(argp, &dbgregs,
2833 sizeof(struct kvm_debugregs)))
2834 break;
2835 r = 0;
2836 break;
2837 }
2838 case KVM_SET_DEBUGREGS: {
2839 struct kvm_debugregs dbgregs;
2840
2841 r = -EFAULT;
2842 if (copy_from_user(&dbgregs, argp,
2843 sizeof(struct kvm_debugregs)))
2844 break;
2845
2846 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2847 break;
2848 }
2d5b5a66 2849 case KVM_GET_XSAVE: {
d1ac91d8 2850 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 2851 r = -ENOMEM;
d1ac91d8 2852 if (!u.xsave)
2d5b5a66
SY		 2853 break;
2854
d1ac91d8 2855 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2856
2857 r = -EFAULT;
d1ac91d8 2858 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 2859 break;
2860 r = 0;
2861 break;
2862 }
2863 case KVM_SET_XSAVE: {
ff5c2c03
SL		 2864 u.xsave = memdup_user(argp, sizeof(*u.xsave));
2865 if (IS_ERR(u.xsave)) {
2866 r = PTR_ERR(u.xsave);
2867 goto out;
2868 }
2d5b5a66 2869
d1ac91d8 2870 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2871 break;
2872 }
2873 case KVM_GET_XCRS: {
d1ac91d8 2874 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 2875 r = -ENOMEM;
d1ac91d8 2876 if (!u.xcrs)
2d5b5a66
SY		 2877 break;
2878
d1ac91d8 2879 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 2880
2881 r = -EFAULT;
d1ac91d8 2882 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 2883 sizeof(struct kvm_xcrs)))
2884 break;
2885 r = 0;
2886 break;
2887 }
2888 case KVM_SET_XCRS: {
ff5c2c03
SL		 2889 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
2890 if (IS_ERR(u.xcrs)) {
2891 r = PTR_ERR(u.xcrs);
2892 goto out;
2893 }
2d5b5a66 2894
d1ac91d8 2895 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 2896 break;
2897 }
92a1f12d
JR		 2898 case KVM_SET_TSC_KHZ: {
2899 u32 user_tsc_khz;
2900
2901 r = -EINVAL;
92a1f12d
JR		 2902 user_tsc_khz = (u32)arg;
2903
2904 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
2905 goto out;
2906
cc578287
ZA		 2907 if (user_tsc_khz == 0)
2908 user_tsc_khz = tsc_khz;
2909
2910 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 2911
2912 r = 0;
2913 goto out;
2914 }
2915 case KVM_GET_TSC_KHZ: {
cc578287 2916 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 2917 goto out;
2918 }
1c0b28c2
EM		 2919 case KVM_KVMCLOCK_CTRL: {
2920 r = kvm_set_guest_paused(vcpu);
2921 goto out;
2922 }
313a3dc7
CO		 2923 default:
2924 r = -EINVAL;
2925 }
2926out:
d1ac91d8 2927 kfree(u.buffer);
313a3dc7
CO		 2928 return r;
2929}
2930
5b1c1493
CO		 2931int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
2932{
2933 return VM_FAULT_SIGBUS;
2934}
2935
1fe779f8
CO		 2936static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2937{
2938 int ret;
2939
2940 if (addr > (unsigned int)(-3 * PAGE_SIZE))
2941 return -1;
2942 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2943 return ret;
2944}
2945
b927a3ce
SY		 2946static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2947 u64 ident_addr)
2948{
2949 kvm->arch.ept_identity_map_addr = ident_addr;
2950 return 0;
2951}
2952
1fe779f8
CO		 2953static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
2954 u32 kvm_nr_mmu_pages)
2955{
2956 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
2957 return -EINVAL;
2958
79fac95e 2959 mutex_lock(&kvm->slots_lock);
7c8a83b7 2960 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 2961
2962 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 2963 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 2964
7c8a83b7 2965 spin_unlock(&kvm->mmu_lock);
79fac95e 2966 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2967 return 0;
2968}
2969
2970static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2971{
39de71ec 2972 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 2973}
2974
1fe779f8
CO		 2975static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2976{
2977 int r;
2978
2979 r = 0;
2980 switch (chip->chip_id) {
2981 case KVM_IRQCHIP_PIC_MASTER:
2982 memcpy(&chip->chip.pic,
2983 &pic_irqchip(kvm)->pics[0],
2984 sizeof(struct kvm_pic_state));
2985 break;
2986 case KVM_IRQCHIP_PIC_SLAVE:
2987 memcpy(&chip->chip.pic,
2988 &pic_irqchip(kvm)->pics[1],
2989 sizeof(struct kvm_pic_state));
2990 break;
2991 case KVM_IRQCHIP_IOAPIC:
eba0226b 2992 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2993 break;
2994 default:
2995 r = -EINVAL;
2996 break;
2997 }
2998 return r;
2999}
3000
3001static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3002{
3003 int r;
3004
3005 r = 0;
3006 switch (chip->chip_id) {
3007 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3008 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3009 memcpy(&pic_irqchip(kvm)->pics[0],
3010 &chip->chip.pic,
3011 sizeof(struct kvm_pic_state));
f4f51050 3012 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3013 break;
3014 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3015 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3016 memcpy(&pic_irqchip(kvm)->pics[1],
3017 &chip->chip.pic,
3018 sizeof(struct kvm_pic_state));
f4f51050 3019 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3020 break;
3021 case KVM_IRQCHIP_IOAPIC:
eba0226b 3022 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3023 break;
3024 default:
3025 r = -EINVAL;
3026 break;
3027 }
3028 kvm_pic_update_irq(pic_irqchip(kvm));
3029 return r;
3030}
3031
e0f63cb9
SY		 3032static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3033{
3034 int r = 0;
3035
894a9c55 3036 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3037 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3038 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3039 return r;
3040}
3041
3042static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3043{
3044 int r = 0;
3045
894a9c55 3046 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3047 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3048 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3049 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3050 return r;
3051}
3052
3053static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3054{
3055 int r = 0;
3056
3057 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3058 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3059 sizeof(ps->channels));
3060 ps->flags = kvm->arch.vpit->pit_state.flags;
3061 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3062 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3063 return r;
3064}
3065
3066static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3067{
3068 int r = 0, start = 0;
3069 u32 prev_legacy, cur_legacy;
3070 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3071 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3072 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3073 if (!prev_legacy && cur_legacy)
3074 start = 1;
3075 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3076 sizeof(kvm->arch.vpit->pit_state.channels));
3077 kvm->arch.vpit->pit_state.flags = ps->flags;
3078 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3079 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3080 return r;
3081}
3082
52d939a0
MT		 3083static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3084 struct kvm_reinject_control *control)
3085{
3086 if (!kvm->arch.vpit)
3087 return -ENXIO;
894a9c55 3088 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3089 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3090 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3091 return 0;
3092}
3093
95d4c16c 3094/**
60c34612
TY		 3095 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3096 * @kvm: kvm instance
3097 * @log: slot id and address to which we copy the log
95d4c16c 3098 *
60c34612
TY		 3099 * We need to keep it in mind that VCPU threads can write to the bitmap
3100 * concurrently. So, to avoid losing data, we keep the following order for
3101 * each bit:
95d4c16c 3102 *
60c34612
TY		 3103 * 1. Take a snapshot of the bit and clear it if needed.
3104 * 2. Write protect the corresponding page.
3105 * 3. Flush TLB's if needed.
3106 * 4. Copy the snapshot to the userspace.
95d4c16c 3107 *
60c34612
TY		 3108 * Between 2 and 3, the guest may write to the page using the remaining TLB
3109 * entry. This is not a problem because the page will be reported dirty at
3110 * step 4 using the snapshot taken before and step 3 ensures that successive
3111 * writes will be logged for the next call.
5bb064dc 3112 */
60c34612 3113int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3114{
7850ac54 3115 int r;
5bb064dc 3116 struct kvm_memory_slot *memslot;
60c34612
TY		 3117 unsigned long n, i;
3118 unsigned long *dirty_bitmap;
3119 unsigned long *dirty_bitmap_buffer;
3120 bool is_dirty = false;
5bb064dc 3121
79fac95e 3122 mutex_lock(&kvm->slots_lock);
5bb064dc 3123
b050b015
MT		 3124 r = -EINVAL;
3125 if (log->slot >= KVM_MEMORY_SLOTS)
3126 goto out;
3127
28a37544 3128 memslot = id_to_memslot(kvm->memslots, log->slot);
60c34612
TY		 3129
3130 dirty_bitmap = memslot->dirty_bitmap;
b050b015 3131 r = -ENOENT;
60c34612 3132 if (!dirty_bitmap)
b050b015
MT		 3133 goto out;
3134
87bf6e7d 3135 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3136
60c34612
TY		 3137 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3138 memset(dirty_bitmap_buffer, 0, n);
b050b015 3139
60c34612 3140 spin_lock(&kvm->mmu_lock);
b050b015 3141
60c34612
TY		 3142 for (i = 0; i < n / sizeof(long); i++) {
3143 unsigned long mask;
3144 gfn_t offset;
cdfca7b3 3145
60c34612
TY		 3146 if (!dirty_bitmap[i])
3147 continue;
b050b015 3148
60c34612 3149 is_dirty = true;
914ebccd 3150
60c34612
TY		 3151 mask = xchg(&dirty_bitmap[i], 0);
3152 dirty_bitmap_buffer[i] = mask;
edde99ce 3153
60c34612
TY		 3154 offset = i * BITS_PER_LONG;
3155 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
5bb064dc 3156 }
60c34612
TY		 3157 if (is_dirty)
3158 kvm_flush_remote_tlbs(kvm);
3159
3160 spin_unlock(&kvm->mmu_lock);
3161
3162 r = -EFAULT;
3163 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3164 goto out;
b050b015 3165
5bb064dc
ZX		 3166 r = 0;
3167out:
79fac95e 3168 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3169 return r;
3170}
3171
23d43cf9
CD		 3172int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event)
3173{
3174 if (!irqchip_in_kernel(kvm))
3175 return -ENXIO;
3176
3177 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3178 irq_event->irq, irq_event->level);
3179 return 0;
3180}
3181
1fe779f8
CO		 3182long kvm_arch_vm_ioctl(struct file *filp,
3183 unsigned int ioctl, unsigned long arg)
3184{
3185 struct kvm *kvm = filp->private_data;
3186 void __user *argp = (void __user *)arg;
367e1319 3187 int r = -ENOTTY;
f0d66275
DH		 3188 /*
3189 * This union makes it completely explicit to gcc-3.x
3190 * that these two variables' stack usage should be
3191 * combined, not added together.
3192 */
3193 union {
3194 struct kvm_pit_state ps;
e9f42757 3195 struct kvm_pit_state2 ps2;
c5ff41ce 3196 struct kvm_pit_config pit_config;
f0d66275 3197 } u;
1fe779f8
CO		 3198
3199 switch (ioctl) {
3200 case KVM_SET_TSS_ADDR:
3201 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3202 if (r < 0)
3203 goto out;
3204 break;
b927a3ce
SY		 3205 case KVM_SET_IDENTITY_MAP_ADDR: {
3206 u64 ident_addr;
3207
3208 r = -EFAULT;
3209 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3210 goto out;
3211 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3212 if (r < 0)
3213 goto out;
3214 break;
3215 }
1fe779f8
CO		 3216 case KVM_SET_NR_MMU_PAGES:
3217 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3218 if (r)
3219 goto out;
3220 break;
3221 case KVM_GET_NR_MMU_PAGES:
3222 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3223 break;
3ddea128
MT		 3224 case KVM_CREATE_IRQCHIP: {
3225 struct kvm_pic *vpic;
3226
3227 mutex_lock(&kvm->lock);
3228 r = -EEXIST;
3229 if (kvm->arch.vpic)
3230 goto create_irqchip_unlock;
3e515705
AK		 3231 r = -EINVAL;
3232 if (atomic_read(&kvm->online_vcpus))
3233 goto create_irqchip_unlock;
1fe779f8 3234 r = -ENOMEM;
3ddea128
MT		 3235 vpic = kvm_create_pic(kvm);
3236 if (vpic) {
1fe779f8
CO		 3237 r = kvm_ioapic_init(kvm);
3238 if (r) {
175504cd 3239 mutex_lock(&kvm->slots_lock);
72bb2fcd 3240 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3241 &vpic->dev_master);
3242 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3243 &vpic->dev_slave);
3244 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3245 &vpic->dev_eclr);
175504cd 3246 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3247 kfree(vpic);
3248 goto create_irqchip_unlock;
1fe779f8
CO		 3249 }
3250 } else
3ddea128
MT		 3251 goto create_irqchip_unlock;
3252 smp_wmb();
3253 kvm->arch.vpic = vpic;
3254 smp_wmb();
399ec807
AK		 3255 r = kvm_setup_default_irq_routing(kvm);
3256 if (r) {
175504cd 3257 mutex_lock(&kvm->slots_lock);
3ddea128 3258 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3259 kvm_ioapic_destroy(kvm);
3260 kvm_destroy_pic(kvm);
3ddea128 3261 mutex_unlock(&kvm->irq_lock);
175504cd 3262 mutex_unlock(&kvm->slots_lock);
399ec807 3263 }
3ddea128
MT		 3264 create_irqchip_unlock:
3265 mutex_unlock(&kvm->lock);
1fe779f8 3266 break;
3ddea128 3267 }
7837699f 3268 case KVM_CREATE_PIT:
c5ff41ce
JK		 3269 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3270 goto create_pit;
3271 case KVM_CREATE_PIT2:
3272 r = -EFAULT;
3273 if (copy_from_user(&u.pit_config, argp,
3274 sizeof(struct kvm_pit_config)))
3275 goto out;
3276 create_pit:
79fac95e 3277 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3278 r = -EEXIST;
3279 if (kvm->arch.vpit)
3280 goto create_pit_unlock;
7837699f 3281 r = -ENOMEM;
c5ff41ce 3282 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3283 if (kvm->arch.vpit)
3284 r = 0;
269e05e4 3285 create_pit_unlock:
79fac95e 3286 mutex_unlock(&kvm->slots_lock);
7837699f 3287 break;
1fe779f8
CO		 3288 case KVM_GET_IRQCHIP: {
3289 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3290 struct kvm_irqchip *chip;
1fe779f8 3291
ff5c2c03
SL		 3292 chip = memdup_user(argp, sizeof(*chip));
3293 if (IS_ERR(chip)) {
3294 r = PTR_ERR(chip);
1fe779f8 3295 goto out;
ff5c2c03
SL		 3296 }
3297
1fe779f8
CO		 3298 r = -ENXIO;
3299 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3300 goto get_irqchip_out;
3301 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3302 if (r)
f0d66275 3303 goto get_irqchip_out;
1fe779f8 3304 r = -EFAULT;
f0d66275
DH		 3305 if (copy_to_user(argp, chip, sizeof *chip))
3306 goto get_irqchip_out;
1fe779f8 3307 r = 0;
f0d66275
DH		 3308 get_irqchip_out:
3309 kfree(chip);
3310 if (r)
3311 goto out;
1fe779f8
CO		 3312 break;
3313 }
3314 case KVM_SET_IRQCHIP: {
3315 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3316 struct kvm_irqchip *chip;
1fe779f8 3317
ff5c2c03
SL		 3318 chip = memdup_user(argp, sizeof(*chip));
3319 if (IS_ERR(chip)) {
3320 r = PTR_ERR(chip);
1fe779f8 3321 goto out;
ff5c2c03
SL		 3322 }
3323
1fe779f8
CO		 3324 r = -ENXIO;
3325 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3326 goto set_irqchip_out;
3327 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3328 if (r)
f0d66275 3329 goto set_irqchip_out;
1fe779f8 3330 r = 0;
f0d66275
DH		 3331 set_irqchip_out:
3332 kfree(chip);
3333 if (r)
3334 goto out;
1fe779f8
CO		 3335 break;
3336 }
e0f63cb9 3337 case KVM_GET_PIT: {
e0f63cb9 3338 r = -EFAULT;
f0d66275 3339 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3340 goto out;
3341 r = -ENXIO;
3342 if (!kvm->arch.vpit)
3343 goto out;
f0d66275 3344 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3345 if (r)
3346 goto out;
3347 r = -EFAULT;
f0d66275 3348 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3349 goto out;
3350 r = 0;
3351 break;
3352 }
3353 case KVM_SET_PIT: {
e0f63cb9 3354 r = -EFAULT;
f0d66275 3355 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3356 goto out;
3357 r = -ENXIO;
3358 if (!kvm->arch.vpit)
3359 goto out;
f0d66275 3360 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3361 if (r)
3362 goto out;
3363 r = 0;
3364 break;
3365 }
e9f42757
BK		 3366 case KVM_GET_PIT2: {
3367 r = -ENXIO;
3368 if (!kvm->arch.vpit)
3369 goto out;
3370 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3371 if (r)
3372 goto out;
3373 r = -EFAULT;
3374 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3375 goto out;
3376 r = 0;
3377 break;
3378 }
3379 case KVM_SET_PIT2: {
3380 r = -EFAULT;
3381 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3382 goto out;
3383 r = -ENXIO;
3384 if (!kvm->arch.vpit)
3385 goto out;
3386 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3387 if (r)
3388 goto out;
3389 r = 0;
3390 break;
3391 }
52d939a0
MT		 3392 case KVM_REINJECT_CONTROL: {
3393 struct kvm_reinject_control control;
3394 r = -EFAULT;
3395 if (copy_from_user(&control, argp, sizeof(control)))
3396 goto out;
3397 r = kvm_vm_ioctl_reinject(kvm, &control);
3398 if (r)
3399 goto out;
3400 r = 0;
3401 break;
3402 }
ffde22ac
ES		 3403 case KVM_XEN_HVM_CONFIG: {
3404 r = -EFAULT;
3405 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3406 sizeof(struct kvm_xen_hvm_config)))
3407 goto out;
3408 r = -EINVAL;
3409 if (kvm->arch.xen_hvm_config.flags)
3410 goto out;
3411 r = 0;
3412 break;
3413 }
afbcf7ab 3414 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3415 struct kvm_clock_data user_ns;
3416 u64 now_ns;
3417 s64 delta;
3418
3419 r = -EFAULT;
3420 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3421 goto out;
3422
3423 r = -EINVAL;
3424 if (user_ns.flags)
3425 goto out;
3426
3427 r = 0;
395c6b0a 3428 local_irq_disable();
759379dd 3429 now_ns = get_kernel_ns();
afbcf7ab 3430 delta = user_ns.clock - now_ns;
395c6b0a 3431 local_irq_enable();
afbcf7ab
GC		 3432 kvm->arch.kvmclock_offset = delta;
3433 break;
3434 }
3435 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3436 struct kvm_clock_data user_ns;
3437 u64 now_ns;
3438
395c6b0a 3439 local_irq_disable();
759379dd 3440 now_ns = get_kernel_ns();
afbcf7ab 3441 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3442 local_irq_enable();
afbcf7ab 3443 user_ns.flags = 0;
97e69aa6 3444 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3445
3446 r = -EFAULT;
3447 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3448 goto out;
3449 r = 0;
3450 break;
3451 }
3452
1fe779f8
CO		 3453 default:
3454 ;
3455 }
3456out:
3457 return r;
3458}
3459
a16b043c 3460static void kvm_init_msr_list(void)
043405e1
CO		 3461{
3462 u32 dummy[2];
3463 unsigned i, j;
3464
e3267cbb
GC		 3465 /* skip the first msrs in the list. KVM-specific */
3466 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3467 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3468 continue;
3469 if (j < i)
3470 msrs_to_save[j] = msrs_to_save[i];
3471 j++;
3472 }
3473 num_msrs_to_save = j;
3474}
3475
bda9020e
MT		 3476static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3477 const void *v)
bbd9b64e 3478{
70252a10
AK		 3479 int handled = 0;
3480 int n;
3481
3482 do {
3483 n = min(len, 8);
3484 if (!(vcpu->arch.apic &&
3485 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3486 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3487 break;
3488 handled += n;
3489 addr += n;
3490 len -= n;
3491 v += n;
3492 } while (len);
bbd9b64e 3493
70252a10 3494 return handled;
bbd9b64e
CO		 3495}
3496
bda9020e 3497static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3498{
70252a10
AK		 3499 int handled = 0;
3500 int n;
3501
3502 do {
3503 n = min(len, 8);
3504 if (!(vcpu->arch.apic &&
3505 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3506 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3507 break;
3508 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3509 handled += n;
3510 addr += n;
3511 len -= n;
3512 v += n;
3513 } while (len);
bbd9b64e 3514
70252a10 3515 return handled;
bbd9b64e
CO		 3516}
3517
2dafc6c2
GN		 3518static void kvm_set_segment(struct kvm_vcpu *vcpu,
3519 struct kvm_segment *var, int seg)
3520{
3521 kvm_x86_ops->set_segment(vcpu, var, seg);
3522}
3523
3524void kvm_get_segment(struct kvm_vcpu *vcpu,
3525 struct kvm_segment *var, int seg)
3526{
3527 kvm_x86_ops->get_segment(vcpu, var, seg);
3528}
3529
e459e322 3530gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
02f59dc9
JR		 3531{
3532 gpa_t t_gpa;
ab9ae313 3533 struct x86_exception exception;
02f59dc9
JR		 3534
3535 BUG_ON(!mmu_is_nested(vcpu));
3536
3537 /* NPT walks are always user-walks */
3538 access |= PFERR_USER_MASK;
ab9ae313 3539 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
02f59dc9
JR		 3540
3541 return t_gpa;
3542}
3543
ab9ae313
AK		 3544gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3545 struct x86_exception *exception)
1871c602
GN		 3546{
3547 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 3548 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3549}
3550
ab9ae313
AK		 3551 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3552 struct x86_exception *exception)
1871c602
GN		 3553{
3554 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3555 access |= PFERR_FETCH_MASK;
ab9ae313 3556 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3557}
3558
ab9ae313
AK		 3559gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3560 struct x86_exception *exception)
1871c602
GN		 3561{
3562 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3563 access |= PFERR_WRITE_MASK;
ab9ae313 3564 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3565}
3566
3567/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 3568gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3569 struct x86_exception *exception)
1871c602 3570{
ab9ae313 3571 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 3572}
3573
3574static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3575 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 3576 struct x86_exception *exception)
bbd9b64e
CO		 3577{
3578 void *data = val;
10589a46 3579 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3580
3581 while (bytes) {
14dfe855 3582 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 3583 exception);
bbd9b64e 3584 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3585 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3586 int ret;
3587
bcc55cba 3588 if (gpa == UNMAPPED_GVA)
ab9ae313 3589 return X86EMUL_PROPAGATE_FAULT;
77c2002e 3590 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3591 if (ret < 0) {
c3cd7ffa 3592 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3593 goto out;
3594 }
bbd9b64e 3595
77c2002e
IE		 3596 bytes -= toread;
3597 data += toread;
3598 addr += toread;
bbd9b64e 3599 }
10589a46 3600out:
10589a46 3601 return r;
bbd9b64e 3602}
77c2002e 3603
1871c602 3604/* used for instruction fetching */
0f65dd70
AK		 3605static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
3606 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3607 struct x86_exception *exception)
1871c602 3608{
0f65dd70 3609 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3610 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3611
1871c602 3612 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
bcc55cba
AK		 3613 access | PFERR_FETCH_MASK,
3614 exception);
1871c602
GN		 3615}
3616
064aea77 3617int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 3618 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3619 struct x86_exception *exception)
1871c602 3620{
0f65dd70 3621 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3622 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3623
1871c602 3624 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 3625 exception);
1871c602 3626}
064aea77 3627EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 3628
0f65dd70
AK		 3629static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3630 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3631 struct x86_exception *exception)
1871c602 3632{
0f65dd70 3633 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 3634 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 3635}
3636
6a4d7550 3637int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 3638 gva_t addr, void *val,
2dafc6c2 3639 unsigned int bytes,
bcc55cba 3640 struct x86_exception *exception)
77c2002e 3641{
0f65dd70 3642 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 3643 void *data = val;
3644 int r = X86EMUL_CONTINUE;
3645
3646 while (bytes) {
14dfe855
JR		 3647 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3648 PFERR_WRITE_MASK,
ab9ae313 3649 exception);
77c2002e
IE		 3650 unsigned offset = addr & (PAGE_SIZE-1);
3651 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3652 int ret;
3653
bcc55cba 3654 if (gpa == UNMAPPED_GVA)
ab9ae313 3655 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 3656 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3657 if (ret < 0) {
c3cd7ffa 3658 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 3659 goto out;
3660 }
3661
3662 bytes -= towrite;
3663 data += towrite;
3664 addr += towrite;
3665 }
3666out:
3667 return r;
3668}
6a4d7550 3669EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 3670
af7cc7d1
XG		 3671static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
3672 gpa_t *gpa, struct x86_exception *exception,
3673 bool write)
3674{
3675 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3676
bebb106a
XG		 3677 if (vcpu_match_mmio_gva(vcpu, gva) &&
3678 check_write_user_access(vcpu, write, access,
3679 vcpu->arch.access)) {
3680 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
3681 (gva & (PAGE_SIZE - 1));
4f022648 3682 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 3683 return 1;
3684 }
3685
af7cc7d1
XG		 3686 if (write)
3687 access |= PFERR_WRITE_MASK;
3688
3689 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3690
3691 if (*gpa == UNMAPPED_GVA)
3692 return -1;
3693
3694 /* For APIC access vmexit */
3695 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3696 return 1;
3697
4f022648
XG		 3698 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
3699 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 3700 return 1;
4f022648 3701 }
bebb106a 3702
af7cc7d1
XG		 3703 return 0;
3704}
3705
3200f405 3706int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 3707 const void *val, int bytes)
bbd9b64e
CO		 3708{
3709 int ret;
3710
3711 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3712 if (ret < 0)
bbd9b64e 3713 return 0;
f57f2ef5 3714 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 3715 return 1;
3716}
3717
77d197b2
XG		 3718struct read_write_emulator_ops {
3719 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
3720 int bytes);
3721 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
3722 void *val, int bytes);
3723 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
3724 int bytes, void *val);
3725 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
3726 void *val, int bytes);
3727 bool write;
3728};
3729
3730static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
3731{
3732 if (vcpu->mmio_read_completed) {
77d197b2 3733 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 3734 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 3735 vcpu->mmio_read_completed = 0;
3736 return 1;
3737 }
3738
3739 return 0;
3740}
3741
3742static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
3743 void *val, int bytes)
3744{
3745 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
3746}
3747
3748static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
3749 void *val, int bytes)
3750{
3751 return emulator_write_phys(vcpu, gpa, val, bytes);
3752}
3753
3754static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
3755{
3756 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
3757 return vcpu_mmio_write(vcpu, gpa, bytes, val);
3758}
3759
3760static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
3761 void *val, int bytes)
3762{
3763 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
3764 return X86EMUL_IO_NEEDED;
3765}
3766
3767static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
3768 void *val, int bytes)
3769{
f78146b0
AK		 3770 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
3771
3772 memcpy(vcpu->run->mmio.data, frag->data, frag->len);
77d197b2
XG		 3773 return X86EMUL_CONTINUE;
3774}
3775
0fbe9b0b 3776static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 3777 .read_write_prepare = read_prepare,
3778 .read_write_emulate = read_emulate,
3779 .read_write_mmio = vcpu_mmio_read,
3780 .read_write_exit_mmio = read_exit_mmio,
3781};
3782
0fbe9b0b 3783static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 3784 .read_write_emulate = write_emulate,
3785 .read_write_mmio = write_mmio,
3786 .read_write_exit_mmio = write_exit_mmio,
3787 .write = true,
3788};
3789
22388a3c
XG		 3790static int emulator_read_write_onepage(unsigned long addr, void *val,
3791 unsigned int bytes,
3792 struct x86_exception *exception,
3793 struct kvm_vcpu *vcpu,
0fbe9b0b 3794 const struct read_write_emulator_ops *ops)
bbd9b64e 3795{
af7cc7d1
XG		 3796 gpa_t gpa;
3797 int handled, ret;
22388a3c 3798 bool write = ops->write;
f78146b0 3799 struct kvm_mmio_fragment *frag;
10589a46 3800
22388a3c 3801 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 3802
af7cc7d1 3803 if (ret < 0)
bbd9b64e 3804 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3805
3806 /* For APIC access vmexit */
af7cc7d1 3807 if (ret)
bbd9b64e
CO		 3808 goto mmio;
3809
22388a3c 3810 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 3811 return X86EMUL_CONTINUE;
3812
3813mmio:
3814 /*
3815 * Is this MMIO handled locally?
3816 */
22388a3c 3817 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 3818 if (handled == bytes)
bbd9b64e 3819 return X86EMUL_CONTINUE;
bbd9b64e 3820
70252a10
AK		 3821 gpa += handled;
3822 bytes -= handled;
3823 val += handled;
3824
f78146b0
AK		 3825 while (bytes) {
3826 unsigned now = min(bytes, 8U);
bbd9b64e 3827
f78146b0
AK		 3828 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
3829 frag->gpa = gpa;
3830 frag->data = val;
3831 frag->len = now;
3832
3833 gpa += now;
3834 val += now;
3835 bytes -= now;
3836 }
3837 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3838}
3839
22388a3c
XG		 3840int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
3841 void *val, unsigned int bytes,
3842 struct x86_exception *exception,
0fbe9b0b 3843 const struct read_write_emulator_ops *ops)
bbd9b64e 3844{
0f65dd70 3845 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 3846 gpa_t gpa;
3847 int rc;
3848
3849 if (ops->read_write_prepare &&
3850 ops->read_write_prepare(vcpu, val, bytes))
3851 return X86EMUL_CONTINUE;
3852
3853 vcpu->mmio_nr_fragments = 0;
0f65dd70 3854
bbd9b64e
CO		 3855 /* Crossing a page boundary? */
3856 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 3857 int now;
bbd9b64e
CO		 3858
3859 now = -addr & ~PAGE_MASK;
22388a3c
XG		 3860 rc = emulator_read_write_onepage(addr, val, now, exception,
3861 vcpu, ops);
3862
bbd9b64e
CO		 3863 if (rc != X86EMUL_CONTINUE)
3864 return rc;
3865 addr += now;
3866 val += now;
3867 bytes -= now;
3868 }
22388a3c 3869
f78146b0
AK		 3870 rc = emulator_read_write_onepage(addr, val, bytes, exception,
3871 vcpu, ops);
3872 if (rc != X86EMUL_CONTINUE)
3873 return rc;
3874
3875 if (!vcpu->mmio_nr_fragments)
3876 return rc;
3877
3878 gpa = vcpu->mmio_fragments[0].gpa;
3879
3880 vcpu->mmio_needed = 1;
3881 vcpu->mmio_cur_fragment = 0;
3882
3883 vcpu->run->mmio.len = vcpu->mmio_fragments[0].len;
3884 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
3885 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3886 vcpu->run->mmio.phys_addr = gpa;
3887
3888 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 3889}
3890
3891static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
3892 unsigned long addr,
3893 void *val,
3894 unsigned int bytes,
3895 struct x86_exception *exception)
3896{
3897 return emulator_read_write(ctxt, addr, val, bytes,
3898 exception, &read_emultor);
3899}
3900
3901int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
3902 unsigned long addr,
3903 const void *val,
3904 unsigned int bytes,
3905 struct x86_exception *exception)
3906{
3907 return emulator_read_write(ctxt, addr, (void *)val, bytes,
3908 exception, &write_emultor);
bbd9b64e 3909}
bbd9b64e 3910
daea3e73
AK		 3911#define CMPXCHG_TYPE(t, ptr, old, new) \
3912 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
3913
3914#ifdef CONFIG_X86_64
3915# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
3916#else
3917# define CMPXCHG64(ptr, old, new) \
9749a6c0 3918 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 3919#endif
3920
0f65dd70
AK		 3921static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
3922 unsigned long addr,
bbd9b64e
CO		 3923 const void *old,
3924 const void *new,
3925 unsigned int bytes,
0f65dd70 3926 struct x86_exception *exception)
bbd9b64e 3927{
0f65dd70 3928 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 3929 gpa_t gpa;
3930 struct page *page;
3931 char *kaddr;
3932 bool exchanged;
2bacc55c 3933
daea3e73
AK		 3934 /* guests cmpxchg8b have to be emulated atomically */
3935 if (bytes > 8 || (bytes & (bytes - 1)))
3936 goto emul_write;
10589a46 3937
daea3e73 3938 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 3939
daea3e73
AK		 3940 if (gpa == UNMAPPED_GVA ||
3941 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3942 goto emul_write;
2bacc55c 3943
daea3e73
AK		 3944 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3945 goto emul_write;
72dc67a6 3946
daea3e73 3947 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
32cad84f 3948 if (is_error_page(page))
c19b8bd6 3949 goto emul_write;
72dc67a6 3950
8fd75e12 3951 kaddr = kmap_atomic(page);
daea3e73
AK		 3952 kaddr += offset_in_page(gpa);
3953 switch (bytes) {
3954 case 1:
3955 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
3956 break;
3957 case 2:
3958 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
3959 break;
3960 case 4:
3961 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
3962 break;
3963 case 8:
3964 exchanged = CMPXCHG64(kaddr, old, new);
3965 break;
3966 default:
3967 BUG();
2bacc55c 3968 }
8fd75e12 3969 kunmap_atomic(kaddr);
daea3e73
AK		 3970 kvm_release_page_dirty(page);
3971
3972 if (!exchanged)
3973 return X86EMUL_CMPXCHG_FAILED;
3974
f57f2ef5 3975 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 3976
3977 return X86EMUL_CONTINUE;
4a5f48f6 3978
3200f405 3979emul_write:
daea3e73 3980 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 3981
0f65dd70 3982 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 3983}
3984
cf8f70bf
GN		 3985static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
3986{
3987 /* TODO: String I/O for in kernel device */
3988 int r;
3989
3990 if (vcpu->arch.pio.in)
3991 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
3992 vcpu->arch.pio.size, pd);
3993 else
3994 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3995 vcpu->arch.pio.port, vcpu->arch.pio.size,
3996 pd);
3997 return r;
3998}
3999
6f6fbe98
XG		 4000static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4001 unsigned short port, void *val,
4002 unsigned int count, bool in)
cf8f70bf 4003{
6f6fbe98 4004 trace_kvm_pio(!in, port, size, count);
cf8f70bf
GN		 4005
4006 vcpu->arch.pio.port = port;
6f6fbe98 4007 vcpu->arch.pio.in = in;
7972995b 4008 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4009 vcpu->arch.pio.size = size;
4010
4011 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4012 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4013 return 1;
4014 }
4015
4016 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4017 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4018 vcpu->run->io.size = size;
4019 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4020 vcpu->run->io.count = count;
4021 vcpu->run->io.port = port;
4022
4023 return 0;
4024}
4025
6f6fbe98
XG		 4026static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4027 int size, unsigned short port, void *val,
4028 unsigned int count)
cf8f70bf 4029{
ca1d4a9e 4030 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4031 int ret;
ca1d4a9e 4032
6f6fbe98
XG		 4033 if (vcpu->arch.pio.count)
4034 goto data_avail;
cf8f70bf 4035
6f6fbe98
XG		 4036 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4037 if (ret) {
4038data_avail:
4039 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 4040 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4041 return 1;
4042 }
4043
cf8f70bf
GN		 4044 return 0;
4045}
4046
6f6fbe98
XG		 4047static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4048 int size, unsigned short port,
4049 const void *val, unsigned int count)
4050{
4051 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4052
4053 memcpy(vcpu->arch.pio_data, val, size * count);
4054 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4055}
4056
bbd9b64e
CO		 4057static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4058{
4059 return kvm_x86_ops->get_segment_base(vcpu, seg);
4060}
4061
3cb16fe7 4062static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4063{
3cb16fe7 4064 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4065}
4066
f5f48ee1
SY		 4067int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4068{
4069 if (!need_emulate_wbinvd(vcpu))
4070 return X86EMUL_CONTINUE;
4071
4072 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4073 int cpu = get_cpu();
4074
4075 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4076 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4077 wbinvd_ipi, NULL, 1);
2eec7343 4078 put_cpu();
f5f48ee1 4079 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4080 } else
4081 wbinvd();
f5f48ee1
SY		 4082 return X86EMUL_CONTINUE;
4083}
4084EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4085
bcaf5cc5
AK		 4086static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4087{
4088 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4089}
4090
717746e3 4091int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
bbd9b64e 4092{
717746e3 4093 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4094}
4095
717746e3 4096int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
bbd9b64e 4097{
338dbc97 4098
717746e3 4099 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4100}
4101
52a46617 4102static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4103{
52a46617 4104 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4105}
4106
717746e3 4107static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4108{
717746e3 4109 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4110 unsigned long value;
4111
4112 switch (cr) {
4113 case 0:
4114 value = kvm_read_cr0(vcpu);
4115 break;
4116 case 2:
4117 value = vcpu->arch.cr2;
4118 break;
4119 case 3:
9f8fe504 4120 value = kvm_read_cr3(vcpu);
52a46617
GN		 4121 break;
4122 case 4:
4123 value = kvm_read_cr4(vcpu);
4124 break;
4125 case 8:
4126 value = kvm_get_cr8(vcpu);
4127 break;
4128 default:
a737f256 4129 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4130 return 0;
4131 }
4132
4133 return value;
4134}
4135
717746e3 4136static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4137{
717746e3 4138 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4139 int res = 0;
4140
52a46617
GN		 4141 switch (cr) {
4142 case 0:
49a9b07e 4143 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4144 break;
4145 case 2:
4146 vcpu->arch.cr2 = val;
4147 break;
4148 case 3:
2390218b 4149 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4150 break;
4151 case 4:
a83b29c6 4152 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4153 break;
4154 case 8:
eea1cff9 4155 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4156 break;
4157 default:
a737f256 4158 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4159 res = -1;
52a46617 4160 }
0f12244f
GN		 4161
4162 return res;
52a46617
GN		 4163}
4164
4cee4798
KW		 4165static void emulator_set_rflags(struct x86_emulate_ctxt *ctxt, ulong val)
4166{
4167 kvm_set_rflags(emul_to_vcpu(ctxt), val);
4168}
4169
717746e3 4170static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4171{
717746e3 4172 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4173}
4174
4bff1e86 4175static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4176{
4bff1e86 4177 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4178}
4179
4bff1e86 4180static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4181{
4bff1e86 4182 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4183}
4184
1ac9d0cf
AK		 4185static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4186{
4187 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4188}
4189
4190static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4191{
4192 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4193}
4194
4bff1e86
AK		 4195static unsigned long emulator_get_cached_segment_base(
4196 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4197{
4bff1e86 4198 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4199}
4200
1aa36616
AK		 4201static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4202 struct desc_struct *desc, u32 *base3,
4203 int seg)
2dafc6c2
GN		 4204{
4205 struct kvm_segment var;
4206
4bff1e86 4207 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4208 *selector = var.selector;
2dafc6c2
GN		 4209
4210 if (var.unusable)
4211 return false;
4212
4213 if (var.g)
4214 var.limit >>= 12;
4215 set_desc_limit(desc, var.limit);
4216 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4217#ifdef CONFIG_X86_64
4218 if (base3)
4219 *base3 = var.base >> 32;
4220#endif
2dafc6c2
GN		 4221 desc->type = var.type;
4222 desc->s = var.s;
4223 desc->dpl = var.dpl;
4224 desc->p = var.present;
4225 desc->avl = var.avl;
4226 desc->l = var.l;
4227 desc->d = var.db;
4228 desc->g = var.g;
4229
4230 return true;
4231}
4232
1aa36616
AK		 4233static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4234 struct desc_struct *desc, u32 base3,
4235 int seg)
2dafc6c2 4236{
4bff1e86 4237 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4238 struct kvm_segment var;
4239
1aa36616 4240 var.selector = selector;
2dafc6c2 4241 var.base = get_desc_base(desc);
5601d05b
GN		 4242#ifdef CONFIG_X86_64
4243 var.base |= ((u64)base3) << 32;
4244#endif
2dafc6c2
GN		 4245 var.limit = get_desc_limit(desc);
4246 if (desc->g)
4247 var.limit = (var.limit << 12) | 0xfff;
4248 var.type = desc->type;
4249 var.present = desc->p;
4250 var.dpl = desc->dpl;
4251 var.db = desc->d;
4252 var.s = desc->s;
4253 var.l = desc->l;
4254 var.g = desc->g;
4255 var.avl = desc->avl;
4256 var.present = desc->p;
4257 var.unusable = !var.present;
4258 var.padding = 0;
4259
4260 kvm_set_segment(vcpu, &var, seg);
4261 return;
4262}
4263
717746e3
AK		 4264static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4265 u32 msr_index, u64 *pdata)
4266{
4267 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4268}
4269
4270static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4271 u32 msr_index, u64 data)
4272{
4273 return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
4274}
4275
222d21aa
AK		 4276static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4277 u32 pmc, u64 *pdata)
4278{
4279 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4280}
4281
6c3287f7
AK		 4282static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4283{
4284 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4285}
4286
5037f6f3
AK		 4287static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4288{
4289 preempt_disable();
5197b808 4290 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4291 /*
4292 * CR0.TS may reference the host fpu state, not the guest fpu state,
4293 * so it may be clear at this point.
4294 */
4295 clts();
4296}
4297
4298static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4299{
4300 preempt_enable();
4301}
4302
2953538e 4303static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4304 struct x86_instruction_info *info,
c4f035c6
AK		 4305 enum x86_intercept_stage stage)
4306{
2953538e 4307 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4308}
4309
0017f93a 4310static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4311 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4312{
0017f93a 4313 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4314}
4315
dd856efa
AK		 4316static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4317{
4318 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4319}
4320
4321static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4322{
4323 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4324}
4325
0225fb50 4326static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 4327 .read_gpr = emulator_read_gpr,
4328 .write_gpr = emulator_write_gpr,
1871c602 4329 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4330 .write_std = kvm_write_guest_virt_system,
1871c602 4331 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4332 .read_emulated = emulator_read_emulated,
4333 .write_emulated = emulator_write_emulated,
4334 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4335 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4336 .pio_in_emulated = emulator_pio_in_emulated,
4337 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4338 .get_segment = emulator_get_segment,
4339 .set_segment = emulator_set_segment,
5951c442 4340 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4341 .get_gdt = emulator_get_gdt,
160ce1f1 4342 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4343 .set_gdt = emulator_set_gdt,
4344 .set_idt = emulator_set_idt,
52a46617
GN		 4345 .get_cr = emulator_get_cr,
4346 .set_cr = emulator_set_cr,
4cee4798 4347 .set_rflags = emulator_set_rflags,
9c537244 4348 .cpl = emulator_get_cpl,
35aa5375
GN		 4349 .get_dr = emulator_get_dr,
4350 .set_dr = emulator_set_dr,
717746e3
AK		 4351 .set_msr = emulator_set_msr,
4352 .get_msr = emulator_get_msr,
222d21aa 4353 .read_pmc = emulator_read_pmc,
6c3287f7 4354 .halt = emulator_halt,
bcaf5cc5 4355 .wbinvd = emulator_wbinvd,
d6aa1000 4356 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4357 .get_fpu = emulator_get_fpu,
4358 .put_fpu = emulator_put_fpu,
c4f035c6 4359 .intercept = emulator_intercept,
bdb42f5a 4360 .get_cpuid = emulator_get_cpuid,
bbd9b64e
CO		 4361};
4362
95cb2295
GN		 4363static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4364{
4365 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4366 /*
4367 * an sti; sti; sequence only disable interrupts for the first
4368 * instruction. So, if the last instruction, be it emulated or
4369 * not, left the system with the INT_STI flag enabled, it
4370 * means that the last instruction is an sti. We should not
4371 * leave the flag on in this case. The same goes for mov ss
4372 */
4373 if (!(int_shadow & mask))
4374 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4375}
4376
54b8486f
GN		 4377static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4378{
4379 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4380 if (ctxt->exception.vector == PF_VECTOR)
6389ee94 4381 kvm_propagate_fault(vcpu, &ctxt->exception);
da9cb575
AK		 4382 else if (ctxt->exception.error_code_valid)
4383 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4384 ctxt->exception.error_code);
54b8486f 4385 else
da9cb575 4386 kvm_queue_exception(vcpu, ctxt->exception.vector);
54b8486f
GN		 4387}
4388
dd856efa 4389static void init_decode_cache(struct x86_emulate_ctxt *ctxt)
b5c9ff73 4390{
9dac77fa 4391 memset(&ctxt->twobyte, 0,
dd856efa 4392 (void *)&ctxt->_regs - (void *)&ctxt->twobyte);
b5c9ff73 4393
9dac77fa
AK		 4394 ctxt->fetch.start = 0;
4395 ctxt->fetch.end = 0;
4396 ctxt->io_read.pos = 0;
4397 ctxt->io_read.end = 0;
4398 ctxt->mem_read.pos = 0;
4399 ctxt->mem_read.end = 0;
b5c9ff73
TY		 4400}
4401
8ec4722d
MG		 4402static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4403{
adf52235 4404 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4405 int cs_db, cs_l;
4406
8ec4722d
MG		 4407 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4408
adf52235
TY		 4409 ctxt->eflags = kvm_get_rflags(vcpu);
4410 ctxt->eip = kvm_rip_read(vcpu);
4411 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4412 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4413 cs_l ? X86EMUL_MODE_PROT64 :
4414 cs_db ? X86EMUL_MODE_PROT32 :
4415 X86EMUL_MODE_PROT16;
4416 ctxt->guest_mode = is_guest_mode(vcpu);
4417
dd856efa 4418 init_decode_cache(ctxt);
7ae441ea 4419 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4420}
4421
71f9833b 4422int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 4423{
9d74191a 4424 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 4425 int ret;
4426
4427 init_emulate_ctxt(vcpu);
4428
9dac77fa
AK		 4429 ctxt->op_bytes = 2;
4430 ctxt->ad_bytes = 2;
4431 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 4432 ret = emulate_int_real(ctxt, irq);
63995653
MG		 4433
4434 if (ret != X86EMUL_CONTINUE)
4435 return EMULATE_FAIL;
4436
9dac77fa 4437 ctxt->eip = ctxt->_eip;
9d74191a
TY		 4438 kvm_rip_write(vcpu, ctxt->eip);
4439 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 4440
4441 if (irq == NMI_VECTOR)
7460fb4a 4442 vcpu->arch.nmi_pending = 0;
63995653
MG		 4443 else
4444 vcpu->arch.interrupt.pending = false;
4445
4446 return EMULATE_DONE;
4447}
4448EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4449
6d77dbfc
GN		 4450static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4451{
fc3a9157
JR		 4452 int r = EMULATE_DONE;
4453
6d77dbfc
GN		 4454 ++vcpu->stat.insn_emulation_fail;
4455 trace_kvm_emulate_insn_failed(vcpu);
fc3a9157
JR		 4456 if (!is_guest_mode(vcpu)) {
4457 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4458 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4459 vcpu->run->internal.ndata = 0;
4460 r = EMULATE_FAIL;
4461 }
6d77dbfc 4462 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4463
4464 return r;
6d77dbfc
GN		 4465}
4466
a6f177ef
GN		 4467static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
4468{
4469 gpa_t gpa;
8e3d9d06 4470 pfn_t pfn;
a6f177ef 4471
68be0803
GN		 4472 if (tdp_enabled)
4473 return false;
4474
a6f177ef
GN		 4475 /*
4476 * if emulation was due to access to shadowed page table
4a969980 4477 * and it failed try to unshadow page and re-enter the
a6f177ef
GN		 4478 * guest to let CPU execute the instruction.
4479 */
4480 if (kvm_mmu_unprotect_page_virt(vcpu, gva))
4481 return true;
4482
4483 gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
4484
4485 if (gpa == UNMAPPED_GVA)
4486 return true; /* let cpu generate fault */
4487
8e3d9d06
XG		 4488 /*
4489 * Do not retry the unhandleable instruction if it faults on the
4490 * readonly host memory, otherwise it will goto a infinite loop:
4491 * retry instruction -> write #PF -> emulation fail -> retry
4492 * instruction -> ...
4493 */
4494 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
4495 if (!is_error_pfn(pfn)) {
4496 kvm_release_pfn_clean(pfn);
a6f177ef 4497 return true;
8e3d9d06 4498 }
a6f177ef
GN		 4499
4500 return false;
4501}
4502
1cb3f3ae
XG		 4503static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
4504 unsigned long cr2, int emulation_type)
4505{
4506 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4507 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
4508
4509 last_retry_eip = vcpu->arch.last_retry_eip;
4510 last_retry_addr = vcpu->arch.last_retry_addr;
4511
4512 /*
4513 * If the emulation is caused by #PF and it is non-page_table
4514 * writing instruction, it means the VM-EXIT is caused by shadow
4515 * page protected, we can zap the shadow page and retry this
4516 * instruction directly.
4517 *
4518 * Note: if the guest uses a non-page-table modifying instruction
4519 * on the PDE that points to the instruction, then we will unmap
4520 * the instruction and go to an infinite loop. So, we cache the
4521 * last retried eip and the last fault address, if we meet the eip
4522 * and the address again, we can break out of the potential infinite
4523 * loop.
4524 */
4525 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
4526
4527 if (!(emulation_type & EMULTYPE_RETRY))
4528 return false;
4529
4530 if (x86_page_table_writing_insn(ctxt))
4531 return false;
4532
4533 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
4534 return false;
4535
4536 vcpu->arch.last_retry_eip = ctxt->eip;
4537 vcpu->arch.last_retry_addr = cr2;
4538
4539 if (!vcpu->arch.mmu.direct_map)
4540 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4541
4542 kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4543
4544 return true;
4545}
4546
51d8b661
AP		 4547int x86_emulate_instruction(struct kvm_vcpu *vcpu,
4548 unsigned long cr2,
dc25e89e
AP		 4549 int emulation_type,
4550 void *insn,
4551 int insn_len)
bbd9b64e 4552{
95cb2295 4553 int r;
9d74191a 4554 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 4555 bool writeback = true;
bbd9b64e 4556
26eef70c 4557 kvm_clear_exception_queue(vcpu);
8d7d8102 4558
571008da 4559 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 4560 init_emulate_ctxt(vcpu);
9d74191a
TY		 4561 ctxt->interruptibility = 0;
4562 ctxt->have_exception = false;
4563 ctxt->perm_ok = false;
bbd9b64e 4564
9d74191a 4565 ctxt->only_vendor_specific_insn
4005996e
AK		 4566 = emulation_type & EMULTYPE_TRAP_UD;
4567
9d74191a 4568 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 4569
e46479f8 4570 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 4571 ++vcpu->stat.insn_emulation;
1d2887e2 4572 if (r != EMULATION_OK) {
4005996e
AK		 4573 if (emulation_type & EMULTYPE_TRAP_UD)
4574 return EMULATE_FAIL;
a6f177ef 4575 if (reexecute_instruction(vcpu, cr2))
bbd9b64e 4576 return EMULATE_DONE;
6d77dbfc
GN		 4577 if (emulation_type & EMULTYPE_SKIP)
4578 return EMULATE_FAIL;
4579 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4580 }
4581 }
4582
ba8afb6b 4583 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 4584 kvm_rip_write(vcpu, ctxt->_eip);
ba8afb6b
GN		 4585 return EMULATE_DONE;
4586 }
4587
1cb3f3ae
XG		 4588 if (retry_instruction(ctxt, cr2, emulation_type))
4589 return EMULATE_DONE;
4590
7ae441ea 4591 /* this is needed for vmware backdoor interface to work since it
4d2179e1 4592 changes registers values during IO operation */
7ae441ea
GN		 4593 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
4594 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 4595 emulator_invalidate_register_cache(ctxt);
7ae441ea 4596 }
4d2179e1 4597
5cd21917 4598restart:
9d74191a 4599 r = x86_emulate_insn(ctxt);
bbd9b64e 4600
775fde86
JR		 4601 if (r == EMULATION_INTERCEPTED)
4602 return EMULATE_DONE;
4603
d2ddd1c4 4604 if (r == EMULATION_FAILED) {
a6f177ef 4605 if (reexecute_instruction(vcpu, cr2))
c3cd7ffa
GN		 4606 return EMULATE_DONE;
4607
6d77dbfc 4608 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4609 }
4610
9d74191a 4611 if (ctxt->have_exception) {
54b8486f 4612 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 4613 r = EMULATE_DONE;
4614 } else if (vcpu->arch.pio.count) {
3457e419
GN		 4615 if (!vcpu->arch.pio.in)
4616 vcpu->arch.pio.count = 0;
7ae441ea
GN		 4617 else
4618 writeback = false;
e85d28f8 4619 r = EMULATE_DO_MMIO;
7ae441ea
GN		 4620 } else if (vcpu->mmio_needed) {
4621 if (!vcpu->mmio_is_write)
4622 writeback = false;
e85d28f8 4623 r = EMULATE_DO_MMIO;
7ae441ea 4624 } else if (r == EMULATION_RESTART)
5cd21917 4625 goto restart;
d2ddd1c4
GN		 4626 else
4627 r = EMULATE_DONE;
f850e2e6 4628
7ae441ea 4629 if (writeback) {
9d74191a
TY		 4630 toggle_interruptibility(vcpu, ctxt->interruptibility);
4631 kvm_set_rflags(vcpu, ctxt->eflags);
7ae441ea 4632 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea 4633 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 4634 kvm_rip_write(vcpu, ctxt->eip);
7ae441ea
GN		 4635 } else
4636 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 4637
4638 return r;
de7d789a 4639}
51d8b661 4640EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 4641
cf8f70bf 4642int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 4643{
cf8f70bf 4644 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 4645 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
4646 size, port, &val, 1);
cf8f70bf 4647 /* do not return to emulator after return from userspace */
7972995b 4648 vcpu->arch.pio.count = 0;
de7d789a
CO		 4649 return ret;
4650}
cf8f70bf 4651EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 4652
8cfdc000
ZA		 4653static void tsc_bad(void *info)
4654{
0a3aee0d 4655 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 4656}
4657
4658static void tsc_khz_changed(void *data)
c8076604 4659{
8cfdc000
ZA		 4660 struct cpufreq_freqs *freq = data;
4661 unsigned long khz = 0;
4662
4663 if (data)
4664 khz = freq->new;
4665 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4666 khz = cpufreq_quick_get(raw_smp_processor_id());
4667 if (!khz)
4668 khz = tsc_khz;
0a3aee0d 4669 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 4670}
4671
c8076604
GH		 4672static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4673 void *data)
4674{
4675 struct cpufreq_freqs *freq = data;
4676 struct kvm *kvm;
4677 struct kvm_vcpu *vcpu;
4678 int i, send_ipi = 0;
4679
8cfdc000
ZA		 4680 /*
4681 * We allow guests to temporarily run on slowing clocks,
4682 * provided we notify them after, or to run on accelerating
4683 * clocks, provided we notify them before. Thus time never
4684 * goes backwards.
4685 *
4686 * However, we have a problem. We can't atomically update
4687 * the frequency of a given CPU from this function; it is
4688 * merely a notifier, which can be called from any CPU.
4689 * Changing the TSC frequency at arbitrary points in time
4690 * requires a recomputation of local variables related to
4691 * the TSC for each VCPU. We must flag these local variables
4692 * to be updated and be sure the update takes place with the
4693 * new frequency before any guests proceed.
4694 *
4695 * Unfortunately, the combination of hotplug CPU and frequency
4696 * change creates an intractable locking scenario; the order
4697 * of when these callouts happen is undefined with respect to
4698 * CPU hotplug, and they can race with each other. As such,
4699 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
4700 * undefined; you can actually have a CPU frequency change take
4701 * place in between the computation of X and the setting of the
4702 * variable. To protect against this problem, all updates of
4703 * the per_cpu tsc_khz variable are done in an interrupt
4704 * protected IPI, and all callers wishing to update the value
4705 * must wait for a synchronous IPI to complete (which is trivial
4706 * if the caller is on the CPU already). This establishes the
4707 * necessary total order on variable updates.
4708 *
4709 * Note that because a guest time update may take place
4710 * anytime after the setting of the VCPU's request bit, the
4711 * correct TSC value must be set before the request. However,
4712 * to ensure the update actually makes it to any guest which
4713 * starts running in hardware virtualization between the set
4714 * and the acquisition of the spinlock, we must also ping the
4715 * CPU after setting the request bit.
4716 *
4717 */
4718
c8076604
GH		 4719 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
4720 return 0;
4721 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
4722 return 0;
8cfdc000
ZA		 4723
4724 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 4725
e935b837 4726 raw_spin_lock(&kvm_lock);
c8076604 4727 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 4728 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 4729 if (vcpu->cpu != freq->cpu)
4730 continue;
c285545f 4731 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 4732 if (vcpu->cpu != smp_processor_id())
8cfdc000 4733 send_ipi = 1;
c8076604
GH		 4734 }
4735 }
e935b837 4736 raw_spin_unlock(&kvm_lock);
c8076604
GH		 4737
4738 if (freq->old < freq->new && send_ipi) {
4739 /*
4740 * We upscale the frequency. Must make the guest
4741 * doesn't see old kvmclock values while running with
4742 * the new frequency, otherwise we risk the guest sees
4743 * time go backwards.
4744 *
4745 * In case we update the frequency for another cpu
4746 * (which might be in guest context) send an interrupt
4747 * to kick the cpu out of guest context. Next time
4748 * guest context is entered kvmclock will be updated,
4749 * so the guest will not see stale values.
4750 */
8cfdc000 4751 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 4752 }
4753 return 0;
4754}
4755
4756static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 4757 .notifier_call = kvmclock_cpufreq_notifier
4758};
4759
4760static int kvmclock_cpu_notifier(struct notifier_block *nfb,
4761 unsigned long action, void *hcpu)
4762{
4763 unsigned int cpu = (unsigned long)hcpu;
4764
4765 switch (action) {
4766 case CPU_ONLINE:
4767 case CPU_DOWN_FAILED:
4768 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4769 break;
4770 case CPU_DOWN_PREPARE:
4771 smp_call_function_single(cpu, tsc_bad, NULL, 1);
4772 break;
4773 }
4774 return NOTIFY_OK;
4775}
4776
4777static struct notifier_block kvmclock_cpu_notifier_block = {
4778 .notifier_call = kvmclock_cpu_notifier,
4779 .priority = -INT_MAX
c8076604
GH		 4780};
4781
b820cc0c
ZA		 4782static void kvm_timer_init(void)
4783{
4784 int cpu;
4785
c285545f 4786 max_tsc_khz = tsc_khz;
8cfdc000 4787 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 4788 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 4789#ifdef CONFIG_CPU_FREQ
4790 struct cpufreq_policy policy;
4791 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 4792 cpu = get_cpu();
4793 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 4794 if (policy.cpuinfo.max_freq)
4795 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 4796 put_cpu();
c285545f 4797#endif
b820cc0c
ZA		 4798 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4799 CPUFREQ_TRANSITION_NOTIFIER);
4800 }
c285545f 4801 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 4802 for_each_online_cpu(cpu)
4803 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 4804}
4805
ff9d07a0
ZY		 4806static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
4807
f5132b01 4808int kvm_is_in_guest(void)
ff9d07a0 4809{
086c9855 4810 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 4811}
4812
4813static int kvm_is_user_mode(void)
4814{
4815 int user_mode = 3;
dcf46b94 4816
086c9855
AS		 4817 if (__this_cpu_read(current_vcpu))
4818 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 4819
ff9d07a0
ZY		 4820 return user_mode != 0;
4821}
4822
4823static unsigned long kvm_get_guest_ip(void)
4824{
4825 unsigned long ip = 0;
dcf46b94 4826
086c9855
AS		 4827 if (__this_cpu_read(current_vcpu))
4828 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 4829
ff9d07a0
ZY		 4830 return ip;
4831}
4832
4833static struct perf_guest_info_callbacks kvm_guest_cbs = {
4834 .is_in_guest = kvm_is_in_guest,
4835 .is_user_mode = kvm_is_user_mode,
4836 .get_guest_ip = kvm_get_guest_ip,
4837};
4838
4839void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4840{
086c9855 4841 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 4842}
4843EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4844
4845void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4846{
086c9855 4847 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 4848}
4849EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4850
ce88decf
XG		 4851static void kvm_set_mmio_spte_mask(void)
4852{
4853 u64 mask;
4854 int maxphyaddr = boot_cpu_data.x86_phys_bits;
4855
4856 /*
4857 * Set the reserved bits and the present bit of an paging-structure
4858 * entry to generate page fault with PFER.RSV = 1.
4859 */
4860 mask = ((1ull << (62 - maxphyaddr + 1)) - 1) << maxphyaddr;
4861 mask |= 1ull;
4862
4863#ifdef CONFIG_X86_64
4864 /*
4865 * If reserved bit is not supported, clear the present bit to disable
4866 * mmio page fault.
4867 */
4868 if (maxphyaddr == 52)
4869 mask &= ~1ull;
4870#endif
4871
4872 kvm_mmu_set_mmio_spte_mask(mask);
4873}
4874
f8c16bba 4875int kvm_arch_init(void *opaque)
043405e1 4876{
b820cc0c 4877 int r;
f8c16bba
ZX		 4878 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4879
f8c16bba
ZX		 4880 if (kvm_x86_ops) {
4881 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 4882 r = -EEXIST;
4883 goto out;
f8c16bba
ZX		 4884 }
4885
4886 if (!ops->cpu_has_kvm_support()) {
4887 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 4888 r = -EOPNOTSUPP;
4889 goto out;
f8c16bba
ZX		 4890 }
4891 if (ops->disabled_by_bios()) {
4892 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 4893 r = -EOPNOTSUPP;
4894 goto out;
f8c16bba
ZX		 4895 }
4896
97db56ce
AK		 4897 r = kvm_mmu_module_init();
4898 if (r)
4899 goto out;
4900
ce88decf 4901 kvm_set_mmio_spte_mask();
97db56ce
AK		 4902 kvm_init_msr_list();
4903
f8c16bba 4904 kvm_x86_ops = ops;
7b52345e 4905 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 4906 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 4907
b820cc0c 4908 kvm_timer_init();
c8076604 4909
ff9d07a0
ZY		 4910 perf_register_guest_info_callbacks(&kvm_guest_cbs);
4911
2acf923e
DC		 4912 if (cpu_has_xsave)
4913 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
4914
c5cc421b 4915 kvm_lapic_init();
f8c16bba 4916 return 0;
56c6d28a
ZX		 4917
4918out:
56c6d28a 4919 return r;
043405e1 4920}
8776e519 4921
f8c16bba
ZX		 4922void kvm_arch_exit(void)
4923{
ff9d07a0
ZY		 4924 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4925
888d256e
JK		 4926 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4927 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4928 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 4929 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
f8c16bba 4930 kvm_x86_ops = NULL;
56c6d28a
ZX		 4931 kvm_mmu_module_exit();
4932}
f8c16bba 4933
8776e519
HB		 4934int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4935{
4936 ++vcpu->stat.halt_exits;
4937 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 4938 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 4939 return 1;
4940 } else {
4941 vcpu->run->exit_reason = KVM_EXIT_HLT;
4942 return 0;
4943 }
4944}
4945EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4946
55cd8e5a
GN		 4947int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
4948{
4949 u64 param, ingpa, outgpa, ret;
4950 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
4951 bool fast, longmode;
4952 int cs_db, cs_l;
4953
4954 /*
4955 * hypercall generates UD from non zero cpl and real mode
4956 * per HYPER-V spec
4957 */
3eeb3288 4958 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 4959 kvm_queue_exception(vcpu, UD_VECTOR);
4960 return 0;
4961 }
4962
4963 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4964 longmode = is_long_mode(vcpu) && cs_l == 1;
4965
4966 if (!longmode) {
ccd46936
GN		 4967 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
4968 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
4969 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
4970 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
4971 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
4972 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 4973 }
4974#ifdef CONFIG_X86_64
4975 else {
4976 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
4977 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
4978 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
4979 }
4980#endif
4981
4982 code = param & 0xffff;
4983 fast = (param >> 16) & 0x1;
4984 rep_cnt = (param >> 32) & 0xfff;
4985 rep_idx = (param >> 48) & 0xfff;
4986
4987 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
4988
c25bc163
GN		 4989 switch (code) {
4990 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
4991 kvm_vcpu_on_spin(vcpu);
4992 break;
4993 default:
4994 res = HV_STATUS_INVALID_HYPERCALL_CODE;
4995 break;
4996 }
55cd8e5a
GN		 4997
4998 ret = res | (((u64)rep_done & 0xfff) << 32);
4999 if (longmode) {
5000 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5001 } else {
5002 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5003 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5004 }
5005
5006 return 1;
5007}
5008
8776e519
HB		 5009int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5010{
5011 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 5012 int r = 1;
8776e519 5013
55cd8e5a
GN		 5014 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5015 return kvm_hv_hypercall(vcpu);
5016
5fdbf976
MT		 5017 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5018 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5019 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5020 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5021 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5022
229456fc 5023 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5024
8776e519
HB		 5025 if (!is_long_mode(vcpu)) {
5026 nr &= 0xFFFFFFFF;
5027 a0 &= 0xFFFFFFFF;
5028 a1 &= 0xFFFFFFFF;
5029 a2 &= 0xFFFFFFFF;
5030 a3 &= 0xFFFFFFFF;
5031 }
5032
07708c4a
JK		 5033 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5034 ret = -KVM_EPERM;
5035 goto out;
5036 }
5037
8776e519 5038 switch (nr) {
b93463aa
AK		 5039 case KVM_HC_VAPIC_POLL_IRQ:
5040 ret = 0;
5041 break;
8776e519
HB		 5042 default:
5043 ret = -KVM_ENOSYS;
5044 break;
5045 }
07708c4a 5046out:
5fdbf976 5047 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5048 ++vcpu->stat.hypercalls;
2f333bcb 5049 return r;
8776e519
HB		 5050}
5051EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5052
d6aa1000 5053int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5054{
d6aa1000 5055 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5056 char instruction[3];
5fdbf976 5057 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5058
8776e519
HB		 5059 /*
5060 * Blow out the MMU to ensure that no other VCPU has an active mapping
5061 * to ensure that the updated hypercall appears atomically across all
5062 * VCPUs.
5063 */
5064 kvm_mmu_zap_all(vcpu->kvm);
5065
8776e519 5066 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5067
9d74191a 5068 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5069}
5070
b6c7a5dc
HB		 5071/*
5072 * Check if userspace requested an interrupt window, and that the
5073 * interrupt window is open.
5074 *
5075 * No need to exit to userspace if we already have an interrupt queued.
5076 */
851ba692 5077static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5078{
8061823a 5079 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5080 vcpu->run->request_interrupt_window &&
5df56646 5081 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5082}
5083
851ba692 5084static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5085{
851ba692
AK		 5086 struct kvm_run *kvm_run = vcpu->run;
5087
91586a3b 5088 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5089 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5090 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5091 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5092 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5093 else
b6c7a5dc 5094 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5095 kvm_arch_interrupt_allowed(vcpu) &&
5096 !kvm_cpu_has_interrupt(vcpu) &&
5097 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5098}
5099
b93463aa
AK		 5100static void vapic_enter(struct kvm_vcpu *vcpu)
5101{
5102 struct kvm_lapic *apic = vcpu->arch.apic;
5103 struct page *page;
5104
5105 if (!apic || !apic->vapic_addr)
5106 return;
5107
5108 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 5109
5110 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 5111}
5112
5113static void vapic_exit(struct kvm_vcpu *vcpu)
5114{
5115 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 5116 int idx;
b93463aa
AK		 5117
5118 if (!apic || !apic->vapic_addr)
5119 return;
5120
f656ce01 5121 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 5122 kvm_release_page_dirty(apic->vapic_page);
5123 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 5124 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 5125}
5126
95ba8273
GN		 5127static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5128{
5129 int max_irr, tpr;
5130
5131 if (!kvm_x86_ops->update_cr8_intercept)
5132 return;
5133
88c808fd
AK		 5134 if (!vcpu->arch.apic)
5135 return;
5136
8db3baa2
GN		 5137 if (!vcpu->arch.apic->vapic_addr)
5138 max_irr = kvm_lapic_find_highest_irr(vcpu);
5139 else
5140 max_irr = -1;
95ba8273
GN		 5141
5142 if (max_irr != -1)
5143 max_irr >>= 4;
5144
5145 tpr = kvm_lapic_get_cr8(vcpu);
5146
5147 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5148}
5149
851ba692 5150static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 5151{
5152 /* try to reinject previous events if any */
b59bb7bd 5153 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5154 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5155 vcpu->arch.exception.has_error_code,
5156 vcpu->arch.exception.error_code);
b59bb7bd
GN		 5157 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5158 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5159 vcpu->arch.exception.error_code,
5160 vcpu->arch.exception.reinject);
b59bb7bd
GN		 5161 return;
5162 }
5163
95ba8273
GN		 5164 if (vcpu->arch.nmi_injected) {
5165 kvm_x86_ops->set_nmi(vcpu);
5166 return;
5167 }
5168
5169 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5170 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5171 return;
5172 }
5173
5174 /* try to inject new event if pending */
5175 if (vcpu->arch.nmi_pending) {
5176 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 5177 --vcpu->arch.nmi_pending;
95ba8273
GN		 5178 vcpu->arch.nmi_injected = true;
5179 kvm_x86_ops->set_nmi(vcpu);
5180 }
5181 } else if (kvm_cpu_has_interrupt(vcpu)) {
5182 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5183 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5184 false);
5185 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5186 }
5187 }
5188}
5189
2acf923e
DC		 5190static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
5191{
5192 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
5193 !vcpu->guest_xcr0_loaded) {
5194 /* kvm_set_xcr() also depends on this */
5195 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
5196 vcpu->guest_xcr0_loaded = 1;
5197 }
5198}
5199
5200static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
5201{
5202 if (vcpu->guest_xcr0_loaded) {
5203 if (vcpu->arch.xcr0 != host_xcr0)
5204 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
5205 vcpu->guest_xcr0_loaded = 0;
5206 }
5207}
5208
7460fb4a
AK		 5209static void process_nmi(struct kvm_vcpu *vcpu)
5210{
5211 unsigned limit = 2;
5212
5213 /*
5214 * x86 is limited to one NMI running, and one NMI pending after it.
5215 * If an NMI is already in progress, limit further NMIs to just one.
5216 * Otherwise, allow two (and we'll inject the first one immediately).
5217 */
5218 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5219 limit = 1;
5220
5221 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5222 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5223 kvm_make_request(KVM_REQ_EVENT, vcpu);
5224}
5225
851ba692 5226static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5227{
5228 int r;
6a8b1d13 5229 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5230 vcpu->run->request_interrupt_window;
d6185f20 5231 bool req_immediate_exit = 0;
b6c7a5dc 5232
3e007509 5233 if (vcpu->requests) {
a8eeb04a 5234 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5235 kvm_mmu_unload(vcpu);
a8eeb04a 5236 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5237 __kvm_migrate_timers(vcpu);
34c238a1
ZA		 5238 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5239 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 5240 if (unlikely(r))
5241 goto out;
5242 }
a8eeb04a 5243 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5244 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5245 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5246 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5247 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5248 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5249 r = 0;
5250 goto out;
5251 }
a8eeb04a 5252 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5253 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5254 r = 0;
5255 goto out;
5256 }
a8eeb04a 5257 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5258 vcpu->fpu_active = 0;
5259 kvm_x86_ops->fpu_deactivate(vcpu);
5260 }
af585b92
GN		 5261 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5262 /* Page is swapped out. Do synthetic halt */
5263 vcpu->arch.apf.halted = true;
5264 r = 1;
5265 goto out;
5266 }
c9aaa895
GC		 5267 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5268 record_steal_time(vcpu);
7460fb4a
AK		 5269 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5270 process_nmi(vcpu);
d6185f20
NHE		 5271 req_immediate_exit =
5272 kvm_check_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
f5132b01
GN		 5273 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5274 kvm_handle_pmu_event(vcpu);
5275 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5276 kvm_deliver_pmi(vcpu);
2f52d58c 5277 }
b93463aa 5278
b463a6f7
AK		 5279 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5280 inject_pending_event(vcpu);
5281
5282 /* enable NMI/IRQ window open exits if needed */
7460fb4a 5283 if (vcpu->arch.nmi_pending)
b463a6f7
AK		 5284 kvm_x86_ops->enable_nmi_window(vcpu);
5285 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
5286 kvm_x86_ops->enable_irq_window(vcpu);
5287
5288 if (kvm_lapic_enabled(vcpu)) {
5289 update_cr8_intercept(vcpu);
5290 kvm_lapic_sync_to_vapic(vcpu);
5291 }
5292 }
5293
d8368af8
AK		 5294 r = kvm_mmu_reload(vcpu);
5295 if (unlikely(r)) {
d905c069 5296 goto cancel_injection;
d8368af8
AK		 5297 }
5298
b6c7a5dc
HB		 5299 preempt_disable();
5300
5301 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 5302 if (vcpu->fpu_active)
5303 kvm_load_guest_fpu(vcpu);
2acf923e 5304 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 5305
6b7e2d09
XG		 5306 vcpu->mode = IN_GUEST_MODE;
5307
5308 /* We should set ->mode before check ->requests,
5309 * see the comment in make_all_cpus_request.
5310 */
5311 smp_mb();
b6c7a5dc 5312
d94e1dc9 5313 local_irq_disable();
32f88400 5314
6b7e2d09 5315 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 5316 || need_resched() || signal_pending(current)) {
6b7e2d09 5317 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5318 smp_wmb();
6c142801
AK		 5319 local_irq_enable();
5320 preempt_enable();
5321 r = 1;
d905c069 5322 goto cancel_injection;
6c142801
AK		 5323 }
5324
f656ce01 5325 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 5326
d6185f20
NHE		 5327 if (req_immediate_exit)
5328 smp_send_reschedule(vcpu->cpu);
5329
b6c7a5dc
HB		 5330 kvm_guest_enter();
5331
42dbaa5a 5332 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 5333 set_debugreg(0, 7);
5334 set_debugreg(vcpu->arch.eff_db[0], 0);
5335 set_debugreg(vcpu->arch.eff_db[1], 1);
5336 set_debugreg(vcpu->arch.eff_db[2], 2);
5337 set_debugreg(vcpu->arch.eff_db[3], 3);
5338 }
b6c7a5dc 5339
229456fc 5340 trace_kvm_entry(vcpu->vcpu_id);
851ba692 5341 kvm_x86_ops->run(vcpu);
b6c7a5dc 5342
24f1e32c
FW		 5343 /*
5344 * If the guest has used debug registers, at least dr7
5345 * will be disabled while returning to the host.
5346 * If we don't have active breakpoints in the host, we don't
5347 * care about the messed up debug address registers. But if
5348 * we have some of them active, restore the old state.
5349 */
59d8eb53 5350 if (hw_breakpoint_active())
24f1e32c 5351 hw_breakpoint_restore();
42dbaa5a 5352
d5c1785d 5353 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu);
1d5f066e 5354
6b7e2d09 5355 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5356 smp_wmb();
b6c7a5dc
HB		 5357 local_irq_enable();
5358
5359 ++vcpu->stat.exits;
5360
5361 /*
5362 * We must have an instruction between local_irq_enable() and
5363 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5364 * the interrupt shadow. The stat.exits increment will do nicely.
5365 * But we need to prevent reordering, hence this barrier():
5366 */
5367 barrier();
5368
5369 kvm_guest_exit();
5370
5371 preempt_enable();
5372
f656ce01 5373 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 5374
b6c7a5dc
HB		 5375 /*
5376 * Profile KVM exit RIPs:
5377 */
5378 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 5379 unsigned long rip = kvm_rip_read(vcpu);
5380 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 5381 }
5382
cc578287
ZA		 5383 if (unlikely(vcpu->arch.tsc_always_catchup))
5384 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 5385
5cfb1d5a
MT		 5386 if (vcpu->arch.apic_attention)
5387 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 5388
851ba692 5389 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 5390 return r;
5391
5392cancel_injection:
5393 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 5394 if (unlikely(vcpu->arch.apic_attention))
5395 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 5396out:
5397 return r;
5398}
b6c7a5dc 5399
09cec754 5400
851ba692 5401static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 5402{
5403 int r;
f656ce01 5404 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 5405
5406 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 5407 pr_debug("vcpu %d received sipi with vector # %x\n",
5408 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 5409 kvm_lapic_reset(vcpu);
5f179287 5410 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 5411 if (r)
5412 return r;
5413 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 5414 }
5415
f656ce01 5416 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 5417 vapic_enter(vcpu);
5418
5419 r = 1;
5420 while (r > 0) {
af585b92
GN		 5421 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
5422 !vcpu->arch.apf.halted)
851ba692 5423 r = vcpu_enter_guest(vcpu);
d7690175 5424 else {
f656ce01 5425 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 5426 kvm_vcpu_block(vcpu);
f656ce01 5427 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
a8eeb04a 5428 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
09cec754
GN		 5429 {
5430 switch(vcpu->arch.mp_state) {
5431 case KVM_MP_STATE_HALTED:
d7690175 5432 vcpu->arch.mp_state =
09cec754
GN		 5433 KVM_MP_STATE_RUNNABLE;
5434 case KVM_MP_STATE_RUNNABLE:
af585b92 5435 vcpu->arch.apf.halted = false;
09cec754
GN		 5436 break;
5437 case KVM_MP_STATE_SIPI_RECEIVED:
5438 default:
5439 r = -EINTR;
5440 break;
5441 }
5442 }
d7690175
MT		 5443 }
5444
09cec754
GN		 5445 if (r <= 0)
5446 break;
5447
5448 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5449 if (kvm_cpu_has_pending_timer(vcpu))
5450 kvm_inject_pending_timer_irqs(vcpu);
5451
851ba692 5452 if (dm_request_for_irq_injection(vcpu)) {
09cec754 5453 r = -EINTR;
851ba692 5454 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5455 ++vcpu->stat.request_irq_exits;
5456 }
af585b92
GN		 5457
5458 kvm_check_async_pf_completion(vcpu);
5459
09cec754
GN		 5460 if (signal_pending(current)) {
5461 r = -EINTR;
851ba692 5462 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5463 ++vcpu->stat.signal_exits;
5464 }
5465 if (need_resched()) {
f656ce01 5466 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 5467 kvm_resched(vcpu);
f656ce01 5468 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 5469 }
b6c7a5dc
HB		 5470 }
5471
f656ce01 5472 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 5473
b93463aa
AK		 5474 vapic_exit(vcpu);
5475
b6c7a5dc
HB		 5476 return r;
5477}
5478
f78146b0
AK		 5479/*
5480 * Implements the following, as a state machine:
5481 *
5482 * read:
5483 * for each fragment
5484 * write gpa, len
5485 * exit
5486 * copy data
5487 * execute insn
5488 *
5489 * write:
5490 * for each fragment
5491 * write gpa, len
5492 * copy data
5493 * exit
5494 */
5287f194
AK		 5495static int complete_mmio(struct kvm_vcpu *vcpu)
5496{
5497 struct kvm_run *run = vcpu->run;
f78146b0 5498 struct kvm_mmio_fragment *frag;
5287f194
AK		 5499 int r;
5500
5501 if (!(vcpu->arch.pio.count || vcpu->mmio_needed))
5502 return 1;
5503
5504 if (vcpu->mmio_needed) {
f78146b0
AK		 5505 /* Complete previous fragment */
5506 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment++];
cef4dea0 5507 if (!vcpu->mmio_is_write)
f78146b0
AK		 5508 memcpy(frag->data, run->mmio.data, frag->len);
5509 if (vcpu->mmio_cur_fragment == vcpu->mmio_nr_fragments) {
5510 vcpu->mmio_needed = 0;
5511 if (vcpu->mmio_is_write)
5512 return 1;
5513 vcpu->mmio_read_completed = 1;
5514 goto done;
cef4dea0 5515 }
f78146b0
AK		 5516 /* Initiate next fragment */
5517 ++frag;
5518 run->exit_reason = KVM_EXIT_MMIO;
5519 run->mmio.phys_addr = frag->gpa;
cef4dea0 5520 if (vcpu->mmio_is_write)
f78146b0
AK		 5521 memcpy(run->mmio.data, frag->data, frag->len);
5522 run->mmio.len = frag->len;
5523 run->mmio.is_write = vcpu->mmio_is_write;
5524 return 0;
5525
5287f194 5526 }
f78146b0 5527done:
5287f194
AK		 5528 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5529 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
5530 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5531 if (r != EMULATE_DONE)
5532 return 0;
5533 return 1;
5534}
5535
b6c7a5dc
HB		 5536int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
5537{
5538 int r;
5539 sigset_t sigsaved;
5540
e5c30142
AK		 5541 if (!tsk_used_math(current) && init_fpu(current))
5542 return -ENOMEM;
5543
ac9f6dc0
AK		 5544 if (vcpu->sigset_active)
5545 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
5546
a4535290 5547 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 5548 kvm_vcpu_block(vcpu);
d7690175 5549 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 5550 r = -EAGAIN;
5551 goto out;
b6c7a5dc
HB		 5552 }
5553
b6c7a5dc 5554 /* re-sync apic's tpr */
eea1cff9
AP		 5555 if (!irqchip_in_kernel(vcpu->kvm)) {
5556 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
5557 r = -EINVAL;
5558 goto out;
5559 }
5560 }
b6c7a5dc 5561
5287f194
AK		 5562 r = complete_mmio(vcpu);
5563 if (r <= 0)
5564 goto out;
5565
851ba692 5566 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 5567
5568out:
f1d86e46 5569 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 5570 if (vcpu->sigset_active)
5571 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
5572
b6c7a5dc
HB		 5573 return r;
5574}
5575
5576int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5577{
7ae441ea
GN		 5578 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
5579 /*
5580 * We are here if userspace calls get_regs() in the middle of
5581 * instruction emulation. Registers state needs to be copied
4a969980 5582 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 5583 * that usually, but some bad designed PV devices (vmware
5584 * backdoor interface) need this to work
5585 */
dd856efa 5586 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 5587 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5588 }
5fdbf976
MT		 5589 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5590 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5591 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5592 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5593 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
5594 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
5595 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5596 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 5597#ifdef CONFIG_X86_64
5fdbf976
MT		 5598 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
5599 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
5600 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
5601 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
5602 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
5603 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
5604 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
5605 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 5606#endif
5607
5fdbf976 5608 regs->rip = kvm_rip_read(vcpu);
91586a3b 5609 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 5610
b6c7a5dc
HB		 5611 return 0;
5612}
5613
5614int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5615{
7ae441ea
GN		 5616 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
5617 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5618
5fdbf976
MT		 5619 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
5620 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
5621 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
5622 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
5623 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
5624 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
5625 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
5626 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 5627#ifdef CONFIG_X86_64
5fdbf976
MT		 5628 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
5629 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
5630 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
5631 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
5632 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
5633 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
5634 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
5635 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 5636#endif
5637
5fdbf976 5638 kvm_rip_write(vcpu, regs->rip);
91586a3b 5639 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 5640
b4f14abd
JK		 5641 vcpu->arch.exception.pending = false;
5642
3842d135
AK		 5643 kvm_make_request(KVM_REQ_EVENT, vcpu);
5644
b6c7a5dc
HB		 5645 return 0;
5646}
5647
b6c7a5dc
HB		 5648void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5649{
5650 struct kvm_segment cs;
5651
3e6e0aab 5652 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 5653 *db = cs.db;
5654 *l = cs.l;
5655}
5656EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
5657
5658int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
5659 struct kvm_sregs *sregs)
5660{
89a27f4d 5661 struct desc_ptr dt;
b6c7a5dc 5662
3e6e0aab
GT		 5663 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5664 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5665 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5666 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5667 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5668 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5669
3e6e0aab
GT		 5670 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5671 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 5672
5673 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 5674 sregs->idt.limit = dt.size;
5675 sregs->idt.base = dt.address;
b6c7a5dc 5676 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 5677 sregs->gdt.limit = dt.size;
5678 sregs->gdt.base = dt.address;
b6c7a5dc 5679
4d4ec087 5680 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 5681 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 5682 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 5683 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 5684 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 5685 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 5686 sregs->apic_base = kvm_get_apic_base(vcpu);
5687
923c61bb 5688 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 5689
36752c9b 5690 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 5691 set_bit(vcpu->arch.interrupt.nr,
5692 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 5693
b6c7a5dc
HB		 5694 return 0;
5695}
5696
62d9f0db
MT		 5697int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
5698 struct kvm_mp_state *mp_state)
5699{
62d9f0db 5700 mp_state->mp_state = vcpu->arch.mp_state;
62d9f0db
MT		 5701 return 0;
5702}
5703
5704int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
5705 struct kvm_mp_state *mp_state)
5706{
62d9f0db 5707 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 5708 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 5709 return 0;
5710}
5711
7f3d35fd
KW		 5712int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
5713 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 5714{
9d74191a 5715 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 5716 int ret;
e01c2426 5717
8ec4722d 5718 init_emulate_ctxt(vcpu);
c697518a 5719
7f3d35fd 5720 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 5721 has_error_code, error_code);
c697518a 5722
c697518a 5723 if (ret)
19d04437 5724 return EMULATE_FAIL;
37817f29 5725
9d74191a
TY		 5726 kvm_rip_write(vcpu, ctxt->eip);
5727 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 5728 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 5729 return EMULATE_DONE;
37817f29
IE		 5730}
5731EXPORT_SYMBOL_GPL(kvm_task_switch);
5732
b6c7a5dc
HB		 5733int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5734 struct kvm_sregs *sregs)
5735{
5736 int mmu_reset_needed = 0;
63f42e02 5737 int pending_vec, max_bits, idx;
89a27f4d 5738 struct desc_ptr dt;
b6c7a5dc 5739
89a27f4d
GN		 5740 dt.size = sregs->idt.limit;
5741 dt.address = sregs->idt.base;
b6c7a5dc 5742 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 5743 dt.size = sregs->gdt.limit;
5744 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 5745 kvm_x86_ops->set_gdt(vcpu, &dt);
5746
ad312c7c 5747 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 5748 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 5749 vcpu->arch.cr3 = sregs->cr3;
aff48baa 5750 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 5751
2d3ad1f4 5752 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 5753
f6801dff 5754 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 5755 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 5756 kvm_set_apic_base(vcpu, sregs->apic_base);
5757
4d4ec087 5758 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 5759 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 5760 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 5761
fc78f519 5762 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 5763 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 5764 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 5765 kvm_update_cpuid(vcpu);
63f42e02
XG		 5766
5767 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 5768 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 5769 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 5770 mmu_reset_needed = 1;
5771 }
63f42e02 5772 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 5773
5774 if (mmu_reset_needed)
5775 kvm_mmu_reset_context(vcpu);
5776
923c61bb
GN		 5777 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5778 pending_vec = find_first_bit(
5779 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5780 if (pending_vec < max_bits) {
66fd3f7f 5781 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 5782 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 5783 }
5784
3e6e0aab
GT		 5785 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5786 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5787 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5788 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5789 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5790 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5791
3e6e0aab
GT		 5792 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5793 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 5794
5f0269f5
ME		 5795 update_cr8_intercept(vcpu);
5796
9c3e4aab 5797 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 5798 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 5799 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 5800 !is_protmode(vcpu))
9c3e4aab
MT		 5801 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5802
3842d135
AK		 5803 kvm_make_request(KVM_REQ_EVENT, vcpu);
5804
b6c7a5dc
HB		 5805 return 0;
5806}
5807
d0bfb940
JK		 5808int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5809 struct kvm_guest_debug *dbg)
b6c7a5dc 5810{
355be0b9 5811 unsigned long rflags;
ae675ef0 5812 int i, r;
b6c7a5dc 5813
4f926bf2
JK		 5814 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5815 r = -EBUSY;
5816 if (vcpu->arch.exception.pending)
2122ff5e 5817 goto out;
4f926bf2
JK		 5818 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5819 kvm_queue_exception(vcpu, DB_VECTOR);
5820 else
5821 kvm_queue_exception(vcpu, BP_VECTOR);
5822 }
5823
91586a3b
JK		 5824 /*
5825 * Read rflags as long as potentially injected trace flags are still
5826 * filtered out.
5827 */
5828 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 5829
5830 vcpu->guest_debug = dbg->control;
5831 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5832 vcpu->guest_debug = 0;
5833
5834 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 5835 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5836 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5837 vcpu->arch.switch_db_regs =
5838 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5839 } else {
5840 for (i = 0; i < KVM_NR_DB_REGS; i++)
5841 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5842 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5843 }
5844
f92653ee
JK		 5845 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5846 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5847 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 5848
91586a3b
JK		 5849 /*
5850 * Trigger an rflags update that will inject or remove the trace
5851 * flags.
5852 */
5853 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 5854
355be0b9 5855 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 5856
4f926bf2 5857 r = 0;
d0bfb940 5858
2122ff5e 5859out:
b6c7a5dc
HB		 5860
5861 return r;
5862}
5863
8b006791
ZX		 5864/*
5865 * Translate a guest virtual address to a guest physical address.
5866 */
5867int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5868 struct kvm_translation *tr)
5869{
5870 unsigned long vaddr = tr->linear_address;
5871 gpa_t gpa;
f656ce01 5872 int idx;
8b006791 5873
f656ce01 5874 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 5875 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 5876 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 5877 tr->physical_address = gpa;
5878 tr->valid = gpa != UNMAPPED_GVA;
5879 tr->writeable = 1;
5880 tr->usermode = 0;
8b006791
ZX		 5881
5882 return 0;
5883}
5884
d0752060
HB		 5885int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5886{
98918833
SY		 5887 struct i387_fxsave_struct *fxsave =
5888 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5889
d0752060
HB		 5890 memcpy(fpu->fpr, fxsave->st_space, 128);
5891 fpu->fcw = fxsave->cwd;
5892 fpu->fsw = fxsave->swd;
5893 fpu->ftwx = fxsave->twd;
5894 fpu->last_opcode = fxsave->fop;
5895 fpu->last_ip = fxsave->rip;
5896 fpu->last_dp = fxsave->rdp;
5897 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5898
d0752060
HB		 5899 return 0;
5900}
5901
5902int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5903{
98918833
SY		 5904 struct i387_fxsave_struct *fxsave =
5905 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5906
d0752060
HB		 5907 memcpy(fxsave->st_space, fpu->fpr, 128);
5908 fxsave->cwd = fpu->fcw;
5909 fxsave->swd = fpu->fsw;
5910 fxsave->twd = fpu->ftwx;
5911 fxsave->fop = fpu->last_opcode;
5912 fxsave->rip = fpu->last_ip;
5913 fxsave->rdp = fpu->last_dp;
5914 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5915
d0752060
HB		 5916 return 0;
5917}
5918
10ab25cd 5919int fx_init(struct kvm_vcpu *vcpu)
d0752060 5920{
10ab25cd
JK		 5921 int err;
5922
5923 err = fpu_alloc(&vcpu->arch.guest_fpu);
5924 if (err)
5925 return err;
5926
98918833 5927 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 5928
2acf923e
DC		 5929 /*
5930 * Ensure guest xcr0 is valid for loading
5931 */
5932 vcpu->arch.xcr0 = XSTATE_FP;
5933
ad312c7c 5934 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 5935
5936 return 0;
d0752060
HB		 5937}
5938EXPORT_SYMBOL_GPL(fx_init);
5939
98918833
SY		 5940static void fx_free(struct kvm_vcpu *vcpu)
5941{
5942 fpu_free(&vcpu->arch.guest_fpu);
5943}
5944
d0752060
HB		 5945void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5946{
2608d7a1 5947 if (vcpu->guest_fpu_loaded)
d0752060
HB		 5948 return;
5949
2acf923e
DC		 5950 /*
5951 * Restore all possible states in the guest,
5952 * and assume host would use all available bits.
5953 * Guest xcr0 would be loaded later.
5954 */
5955 kvm_put_guest_xcr0(vcpu);
d0752060 5956 vcpu->guest_fpu_loaded = 1;
7cf30855 5957 unlazy_fpu(current);
98918833 5958 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 5959 trace_kvm_fpu(1);
d0752060 5960}
d0752060
HB		 5961
5962void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5963{
2acf923e
DC		 5964 kvm_put_guest_xcr0(vcpu);
5965
d0752060
HB		 5966 if (!vcpu->guest_fpu_loaded)
5967 return;
5968
5969 vcpu->guest_fpu_loaded = 0;
98918833 5970 fpu_save_init(&vcpu->arch.guest_fpu);
f096ed85 5971 ++vcpu->stat.fpu_reload;
a8eeb04a 5972 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 5973 trace_kvm_fpu(0);
d0752060 5974}
e9b11c17
ZX		 5975
5976void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5977{
12f9a48f 5978 kvmclock_reset(vcpu);
7f1ea208 5979
f5f48ee1 5980 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 5981 fx_free(vcpu);
e9b11c17
ZX		 5982 kvm_x86_ops->vcpu_free(vcpu);
5983}
5984
5985struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5986 unsigned int id)
5987{
6755bae8
ZA		 5988 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
5989 printk_once(KERN_WARNING
5990 "kvm: SMP vm created on host with unstable TSC; "
5991 "guest TSC will not be reliable\n");
26e5215f
AK		 5992 return kvm_x86_ops->vcpu_create(kvm, id);
5993}
e9b11c17 5994
26e5215f
AK		 5995int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5996{
5997 int r;
e9b11c17 5998
0bed3b56 5999 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 6000 vcpu_load(vcpu);
6001 r = kvm_arch_vcpu_reset(vcpu);
6002 if (r == 0)
6003 r = kvm_mmu_setup(vcpu);
6004 vcpu_put(vcpu);
e9b11c17 6005
26e5215f 6006 return r;
e9b11c17
ZX		 6007}
6008
d40ccc62 6009void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 6010{
344d9588
GN		 6011 vcpu->arch.apf.msr_val = 0;
6012
e9b11c17
ZX		 6013 vcpu_load(vcpu);
6014 kvm_mmu_unload(vcpu);
6015 vcpu_put(vcpu);
6016
98918833 6017 fx_free(vcpu);
e9b11c17
ZX		 6018 kvm_x86_ops->vcpu_free(vcpu);
6019}
6020
6021int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
6022{
7460fb4a
AK		 6023 atomic_set(&vcpu->arch.nmi_queued, 0);
6024 vcpu->arch.nmi_pending = 0;
448fa4a9
JK		 6025 vcpu->arch.nmi_injected = false;
6026
42dbaa5a
JK		 6027 vcpu->arch.switch_db_regs = 0;
6028 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6029 vcpu->arch.dr6 = DR6_FIXED_1;
6030 vcpu->arch.dr7 = DR7_FIXED_1;
6031
3842d135 6032 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 6033 vcpu->arch.apf.msr_val = 0;
c9aaa895 6034 vcpu->arch.st.msr_val = 0;
3842d135 6035
12f9a48f
GC		 6036 kvmclock_reset(vcpu);
6037
af585b92
GN		 6038 kvm_clear_async_pf_completion_queue(vcpu);
6039 kvm_async_pf_hash_reset(vcpu);
6040 vcpu->arch.apf.halted = false;
3842d135 6041
f5132b01
GN		 6042 kvm_pmu_reset(vcpu);
6043
e9b11c17
ZX		 6044 return kvm_x86_ops->vcpu_reset(vcpu);
6045}
6046
10474ae8 6047int kvm_arch_hardware_enable(void *garbage)
e9b11c17 6048{
ca84d1a2
ZA		 6049 struct kvm *kvm;
6050 struct kvm_vcpu *vcpu;
6051 int i;
0dd6a6ed
ZA		 6052 int ret;
6053 u64 local_tsc;
6054 u64 max_tsc = 0;
6055 bool stable, backwards_tsc = false;
18863bdd
AK		 6056
6057 kvm_shared_msr_cpu_online();
0dd6a6ed
ZA		 6058 ret = kvm_x86_ops->hardware_enable(garbage);
6059 if (ret != 0)
6060 return ret;
6061
6062 local_tsc = native_read_tsc();
6063 stable = !check_tsc_unstable();
6064 list_for_each_entry(kvm, &vm_list, vm_list) {
6065 kvm_for_each_vcpu(i, vcpu, kvm) {
6066 if (!stable && vcpu->cpu == smp_processor_id())
6067 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6068 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6069 backwards_tsc = true;
6070 if (vcpu->arch.last_host_tsc > max_tsc)
6071 max_tsc = vcpu->arch.last_host_tsc;
6072 }
6073 }
6074 }
6075
6076 /*
6077 * Sometimes, even reliable TSCs go backwards. This happens on
6078 * platforms that reset TSC during suspend or hibernate actions, but
6079 * maintain synchronization. We must compensate. Fortunately, we can
6080 * detect that condition here, which happens early in CPU bringup,
6081 * before any KVM threads can be running. Unfortunately, we can't
6082 * bring the TSCs fully up to date with real time, as we aren't yet far
6083 * enough into CPU bringup that we know how much real time has actually
6084 * elapsed; our helper function, get_kernel_ns() will be using boot
6085 * variables that haven't been updated yet.
6086 *
6087 * So we simply find the maximum observed TSC above, then record the
6088 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
6089 * the adjustment will be applied. Note that we accumulate
6090 * adjustments, in case multiple suspend cycles happen before some VCPU
6091 * gets a chance to run again. In the event that no KVM threads get a
6092 * chance to run, we will miss the entire elapsed period, as we'll have
6093 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6094 * loose cycle time. This isn't too big a deal, since the loss will be
6095 * uniform across all VCPUs (not to mention the scenario is extremely
6096 * unlikely). It is possible that a second hibernate recovery happens
6097 * much faster than a first, causing the observed TSC here to be
6098 * smaller; this would require additional padding adjustment, which is
6099 * why we set last_host_tsc to the local tsc observed here.
6100 *
6101 * N.B. - this code below runs only on platforms with reliable TSC,
6102 * as that is the only way backwards_tsc is set above. Also note
6103 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
6104 * have the same delta_cyc adjustment applied if backwards_tsc
6105 * is detected. Note further, this adjustment is only done once,
6106 * as we reset last_host_tsc on all VCPUs to stop this from being
6107 * called multiple times (one for each physical CPU bringup).
6108 *
4a969980 6109 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 6110 * will be compensated by the logic in vcpu_load, which sets the TSC to
6111 * catchup mode. This will catchup all VCPUs to real time, but cannot
6112 * guarantee that they stay in perfect synchronization.
6113 */
6114 if (backwards_tsc) {
6115 u64 delta_cyc = max_tsc - local_tsc;
6116 list_for_each_entry(kvm, &vm_list, vm_list) {
6117 kvm_for_each_vcpu(i, vcpu, kvm) {
6118 vcpu->arch.tsc_offset_adjustment += delta_cyc;
6119 vcpu->arch.last_host_tsc = local_tsc;
6120 }
6121
6122 /*
6123 * We have to disable TSC offset matching.. if you were
6124 * booting a VM while issuing an S4 host suspend....
6125 * you may have some problem. Solving this issue is
6126 * left as an exercise to the reader.
6127 */
6128 kvm->arch.last_tsc_nsec = 0;
6129 kvm->arch.last_tsc_write = 0;
6130 }
6131
6132 }
6133 return 0;
e9b11c17
ZX		 6134}
6135
6136void kvm_arch_hardware_disable(void *garbage)
6137{
6138 kvm_x86_ops->hardware_disable(garbage);
3548bab5 6139 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 6140}
6141
6142int kvm_arch_hardware_setup(void)
6143{
6144 return kvm_x86_ops->hardware_setup();
6145}
6146
6147void kvm_arch_hardware_unsetup(void)
6148{
6149 kvm_x86_ops->hardware_unsetup();
6150}
6151
6152void kvm_arch_check_processor_compat(void *rtn)
6153{
6154 kvm_x86_ops->check_processor_compatibility(rtn);
6155}
6156
3e515705
AK		 6157bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
6158{
6159 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
6160}
6161
54e9818f
GN		 6162struct static_key kvm_no_apic_vcpu __read_mostly;
6163
e9b11c17
ZX		 6164int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6165{
6166 struct page *page;
6167 struct kvm *kvm;
6168 int r;
6169
6170 BUG_ON(vcpu->kvm == NULL);
6171 kvm = vcpu->kvm;
6172
9aabc88f 6173 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
c5af89b6 6174 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 6175 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 6176 else
a4535290 6177 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 6178
6179 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6180 if (!page) {
6181 r = -ENOMEM;
6182 goto fail;
6183 }
ad312c7c 6184 vcpu->arch.pio_data = page_address(page);
e9b11c17 6185
cc578287 6186 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 6187
e9b11c17
ZX		 6188 r = kvm_mmu_create(vcpu);
6189 if (r < 0)
6190 goto fail_free_pio_data;
6191
6192 if (irqchip_in_kernel(kvm)) {
6193 r = kvm_create_lapic(vcpu);
6194 if (r < 0)
6195 goto fail_mmu_destroy;
54e9818f
GN		 6196 } else
6197 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 6198
890ca9ae
HY		 6199 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6200 GFP_KERNEL);
6201 if (!vcpu->arch.mce_banks) {
6202 r = -ENOMEM;
443c39bc 6203 goto fail_free_lapic;
890ca9ae
HY		 6204 }
6205 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6206
f5f48ee1
SY		 6207 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
6208 goto fail_free_mce_banks;
6209
af585b92 6210 kvm_async_pf_hash_reset(vcpu);
f5132b01 6211 kvm_pmu_init(vcpu);
af585b92 6212
e9b11c17 6213 return 0;
f5f48ee1
SY		 6214fail_free_mce_banks:
6215 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 6216fail_free_lapic:
6217 kvm_free_lapic(vcpu);
e9b11c17
ZX		 6218fail_mmu_destroy:
6219 kvm_mmu_destroy(vcpu);
6220fail_free_pio_data:
ad312c7c 6221 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 6222fail:
6223 return r;
6224}
6225
6226void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6227{
f656ce01
MT		 6228 int idx;
6229
f5132b01 6230 kvm_pmu_destroy(vcpu);
36cb93fd 6231 kfree(vcpu->arch.mce_banks);
e9b11c17 6232 kvm_free_lapic(vcpu);
f656ce01 6233 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 6234 kvm_mmu_destroy(vcpu);
f656ce01 6235 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 6236 free_page((unsigned long)vcpu->arch.pio_data);
54e9818f
GN		 6237 if (!irqchip_in_kernel(vcpu->kvm))
6238 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 6239}
d19a9cd2 6240
e08b9637 6241int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 6242{
e08b9637
CO		 6243 if (type)
6244 return -EINVAL;
6245
f05e70ac 6246 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 6247 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 6248
5550af4d
SY		 6249 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
6250 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
6251
038f8c11 6252 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
53f658b3 6253
d89f5eff 6254 return 0;
d19a9cd2
ZX		 6255}
6256
6257static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
6258{
6259 vcpu_load(vcpu);
6260 kvm_mmu_unload(vcpu);
6261 vcpu_put(vcpu);
6262}
6263
6264static void kvm_free_vcpus(struct kvm *kvm)
6265{
6266 unsigned int i;
988a2cae 6267 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 6268
6269 /*
6270 * Unpin any mmu pages first.
6271 */
af585b92
GN		 6272 kvm_for_each_vcpu(i, vcpu, kvm) {
6273 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 6274 kvm_unload_vcpu_mmu(vcpu);
af585b92 6275 }
988a2cae
GN		 6276 kvm_for_each_vcpu(i, vcpu, kvm)
6277 kvm_arch_vcpu_free(vcpu);
6278
6279 mutex_lock(&kvm->lock);
6280 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
6281 kvm->vcpus[i] = NULL;
d19a9cd2 6282
988a2cae
GN		 6283 atomic_set(&kvm->online_vcpus, 0);
6284 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 6285}
6286
ad8ba2cd
SY		 6287void kvm_arch_sync_events(struct kvm *kvm)
6288{
ba4cef31 6289 kvm_free_all_assigned_devices(kvm);
aea924f6 6290 kvm_free_pit(kvm);
ad8ba2cd
SY		 6291}
6292
d19a9cd2
ZX		 6293void kvm_arch_destroy_vm(struct kvm *kvm)
6294{
6eb55818 6295 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 6296 kfree(kvm->arch.vpic);
6297 kfree(kvm->arch.vioapic);
d19a9cd2 6298 kvm_free_vcpus(kvm);
3d45830c
AK		 6299 if (kvm->arch.apic_access_page)
6300 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 6301 if (kvm->arch.ept_identity_pagetable)
6302 put_page(kvm->arch.ept_identity_pagetable);
d19a9cd2 6303}
0de10343 6304
db3fe4eb
TY		 6305void kvm_arch_free_memslot(struct kvm_memory_slot *free,
6306 struct kvm_memory_slot *dont)
6307{
6308 int i;
6309
d89cc617
TY		 6310 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
6311 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
6312 kvm_kvfree(free->arch.rmap[i]);
6313 free->arch.rmap[i] = NULL;
77d11309 6314 }
d89cc617
TY		 6315 if (i == 0)
6316 continue;
6317
6318 if (!dont || free->arch.lpage_info[i - 1] !=
6319 dont->arch.lpage_info[i - 1]) {
6320 kvm_kvfree(free->arch.lpage_info[i - 1]);
6321 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 6322 }
6323 }
6324}
6325
6326int kvm_arch_create_memslot(struct kvm_memory_slot *slot, unsigned long npages)
6327{
6328 int i;
6329
d89cc617 6330 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 6331 unsigned long ugfn;
6332 int lpages;
d89cc617 6333 int level = i + 1;
db3fe4eb
TY		 6334
6335 lpages = gfn_to_index(slot->base_gfn + npages - 1,
6336 slot->base_gfn, level) + 1;
6337
d89cc617
TY		 6338 slot->arch.rmap[i] =
6339 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
6340 if (!slot->arch.rmap[i])
77d11309 6341 goto out_free;
d89cc617
TY		 6342 if (i == 0)
6343 continue;
77d11309 6344
d89cc617
TY		 6345 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
6346 sizeof(*slot->arch.lpage_info[i - 1]));
6347 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 6348 goto out_free;
6349
6350 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 6351 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 6352 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 6353 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 6354 ugfn = slot->userspace_addr >> PAGE_SHIFT;
6355 /*
6356 * If the gfn and userspace address are not aligned wrt each
6357 * other, or if explicitly asked to, disable large page
6358 * support for this slot
6359 */
6360 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
6361 !kvm_largepages_enabled()) {
6362 unsigned long j;
6363
6364 for (j = 0; j < lpages; ++j)
d89cc617 6365 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 6366 }
6367 }
6368
6369 return 0;
6370
6371out_free:
d89cc617
TY		 6372 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
6373 kvm_kvfree(slot->arch.rmap[i]);
6374 slot->arch.rmap[i] = NULL;
6375 if (i == 0)
6376 continue;
6377
6378 kvm_kvfree(slot->arch.lpage_info[i - 1]);
6379 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 6380 }
6381 return -ENOMEM;
6382}
6383
f7784b8e
MT		 6384int kvm_arch_prepare_memory_region(struct kvm *kvm,
6385 struct kvm_memory_slot *memslot,
0de10343 6386 struct kvm_memory_slot old,
f7784b8e 6387 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 6388 int user_alloc)
6389{
f7784b8e 6390 int npages = memslot->npages;
7ac77099
AK		 6391 int map_flags = MAP_PRIVATE | MAP_ANONYMOUS;
6392
6393 /* Prevent internal slot pages from being moved by fork()/COW. */
6394 if (memslot->id >= KVM_MEMORY_SLOTS)
6395 map_flags = MAP_SHARED | MAP_ANONYMOUS;
0de10343
ZX		 6396
6397 /*To keep backward compatibility with older userspace,
4a969980 6398 *x86 needs to handle !user_alloc case.
0de10343
ZX		 6399 */
6400 if (!user_alloc) {
aab2eb7a 6401 if (npages && !old.npages) {
604b38ac
AA		 6402 unsigned long userspace_addr;
6403
6be5ceb0 6404 userspace_addr = vm_mmap(NULL, 0,
604b38ac
AA		 6405 npages * PAGE_SIZE,
6406 PROT_READ | PROT_WRITE,
7ac77099 6407 map_flags,
604b38ac 6408 0);
0de10343 6409
604b38ac
AA		 6410 if (IS_ERR((void *)userspace_addr))
6411 return PTR_ERR((void *)userspace_addr);
6412
604b38ac 6413 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 6414 }
6415 }
6416
f7784b8e
MT		 6417
6418 return 0;
6419}
6420
6421void kvm_arch_commit_memory_region(struct kvm *kvm,
6422 struct kvm_userspace_memory_region *mem,
6423 struct kvm_memory_slot old,
6424 int user_alloc)
6425{
6426
48c0e4e9 6427 int nr_mmu_pages = 0, npages = mem->memory_size >> PAGE_SHIFT;
f7784b8e 6428
aab2eb7a 6429 if (!user_alloc && !old.user_alloc && old.npages && !npages) {
f7784b8e
MT		 6430 int ret;
6431
bfce281c 6432 ret = vm_munmap(old.userspace_addr,
f7784b8e 6433 old.npages * PAGE_SIZE);
f7784b8e
MT		 6434 if (ret < 0)
6435 printk(KERN_WARNING
6436 "kvm_vm_ioctl_set_memory_region: "
6437 "failed to munmap memory\n");
6438 }
6439
48c0e4e9
XG		 6440 if (!kvm->arch.n_requested_mmu_pages)
6441 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
6442
7c8a83b7 6443 spin_lock(&kvm->mmu_lock);
48c0e4e9 6444 if (nr_mmu_pages)
0de10343 6445 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
0de10343 6446 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 6447 spin_unlock(&kvm->mmu_lock);
0de10343 6448}
1d737c8a 6449
2df72e9b 6450void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f
MT		 6451{
6452 kvm_mmu_zap_all(kvm);
8986ecc0 6453 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 6454}
6455
2df72e9b
MT		 6456void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
6457 struct kvm_memory_slot *slot)
6458{
6459 kvm_arch_flush_shadow_all(kvm);
6460}
6461
1d737c8a
ZX		 6462int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
6463{
af585b92
GN		 6464 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6465 !vcpu->arch.apf.halted)
6466 || !list_empty_careful(&vcpu->async_pf.done)
a1b37100 6467 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
7460fb4a 6468 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 6469 (kvm_arch_interrupt_allowed(vcpu) &&
6470 kvm_cpu_has_interrupt(vcpu));
1d737c8a 6471}
5736199a 6472
b6d33834 6473int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 6474{
b6d33834 6475 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 6476}
78646121
GN		 6477
6478int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
6479{
6480 return kvm_x86_ops->interrupt_allowed(vcpu);
6481}
229456fc 6482
f92653ee
JK		 6483bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
6484{
6485 unsigned long current_rip = kvm_rip_read(vcpu) +
6486 get_segment_base(vcpu, VCPU_SREG_CS);
6487
6488 return current_rip == linear_rip;
6489}
6490EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
6491
94fe45da
JK		 6492unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
6493{
6494 unsigned long rflags;
6495
6496 rflags = kvm_x86_ops->get_rflags(vcpu);
6497 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 6498 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 6499 return rflags;
6500}
6501EXPORT_SYMBOL_GPL(kvm_get_rflags);
6502
6503void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
6504{
6505 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 6506 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 6507 rflags |= X86_EFLAGS_TF;
94fe45da 6508 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 6509 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 6510}
6511EXPORT_SYMBOL_GPL(kvm_set_rflags);
6512
56028d08
GN		 6513void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
6514{
6515 int r;
6516
fb67e14f 6517 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
c4806acd 6518 is_error_page(work->page))
56028d08
GN		 6519 return;
6520
6521 r = kvm_mmu_reload(vcpu);
6522 if (unlikely(r))
6523 return;
6524
fb67e14f
XG		 6525 if (!vcpu->arch.mmu.direct_map &&
6526 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
6527 return;
6528
56028d08
GN		 6529 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
6530}
6531
af585b92
GN		 6532static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
6533{
6534 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
6535}
6536
6537static inline u32 kvm_async_pf_next_probe(u32 key)
6538{
6539 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
6540}
6541
6542static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6543{
6544 u32 key = kvm_async_pf_hash_fn(gfn);
6545
6546 while (vcpu->arch.apf.gfns[key] != ~0)
6547 key = kvm_async_pf_next_probe(key);
6548
6549 vcpu->arch.apf.gfns[key] = gfn;
6550}
6551
6552static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
6553{
6554 int i;
6555 u32 key = kvm_async_pf_hash_fn(gfn);
6556
6557 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 6558 (vcpu->arch.apf.gfns[key] != gfn &&
6559 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 6560 key = kvm_async_pf_next_probe(key);
6561
6562 return key;
6563}
6564
6565bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6566{
6567 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
6568}
6569
6570static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6571{
6572 u32 i, j, k;
6573
6574 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
6575 while (true) {
6576 vcpu->arch.apf.gfns[i] = ~0;
6577 do {
6578 j = kvm_async_pf_next_probe(j);
6579 if (vcpu->arch.apf.gfns[j] == ~0)
6580 return;
6581 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
6582 /*
6583 * k lies cyclically in ]i,j]
6584 * | i.k.j |
6585 * |....j i.k.| or |.k..j i...|
6586 */
6587 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
6588 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
6589 i = j;
6590 }
6591}
6592
7c90705b
GN		 6593static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
6594{
6595
6596 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
6597 sizeof(val));
6598}
6599
af585b92
GN		 6600void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
6601 struct kvm_async_pf *work)
6602{
6389ee94
AK		 6603 struct x86_exception fault;
6604
7c90705b 6605 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 6606 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 6607
6608 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 6609 (vcpu->arch.apf.send_user_only &&
6610 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 6611 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
6612 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 6613 fault.vector = PF_VECTOR;
6614 fault.error_code_valid = true;
6615 fault.error_code = 0;
6616 fault.nested_page_fault = false;
6617 fault.address = work->arch.token;
6618 kvm_inject_page_fault(vcpu, &fault);
7c90705b 6619 }
af585b92
GN		 6620}
6621
6622void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
6623 struct kvm_async_pf *work)
6624{
6389ee94
AK		 6625 struct x86_exception fault;
6626
7c90705b
GN		 6627 trace_kvm_async_pf_ready(work->arch.token, work->gva);
6628 if (is_error_page(work->page))
6629 work->arch.token = ~0; /* broadcast wakeup */
6630 else
6631 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
6632
6633 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
6634 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 6635 fault.vector = PF_VECTOR;
6636 fault.error_code_valid = true;
6637 fault.error_code = 0;
6638 fault.nested_page_fault = false;
6639 fault.address = work->arch.token;
6640 kvm_inject_page_fault(vcpu, &fault);
7c90705b 6641 }
e6d53e3b 6642 vcpu->arch.apf.halted = false;
a4fa1635 6643 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 6644}
6645
6646bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
6647{
6648 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
6649 return true;
6650 else
6651 return !kvm_event_needs_reinjection(vcpu) &&
6652 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 6653}
6654
229456fc
MT		 6655EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
6656EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
6657EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
6658EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
6659EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 6660EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 6661EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 6662EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 6663EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 6664EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 6665EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 6666EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
kernel source for telekom puls (alcatel/mediatek)