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kvm: KVM_CAP_IOMMU only available with device assignment
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
313a3dc7 30
18068523 31#include <linux/clocksource.h>
4d5c5d0f 32#include <linux/interrupt.h>
313a3dc7
CO		 33#include <linux/kvm.h>
34#include <linux/fs.h>
35#include <linux/vmalloc.h>
5fb76f9b 36#include <linux/module.h>
0de10343 37#include <linux/mman.h>
2bacc55c 38#include <linux/highmem.h>
19de40a8 39#include <linux/iommu.h>
62c476c7 40#include <linux/intel-iommu.h>
c8076604 41#include <linux/cpufreq.h>
18863bdd 42#include <linux/user-return-notifier.h>
a983fb23 43#include <linux/srcu.h>
5a0e3ad6 44#include <linux/slab.h>
ff9d07a0 45#include <linux/perf_event.h>
7bee342a 46#include <linux/uaccess.h>
af585b92 47#include <linux/hash.h>
a1b60c1c 48#include <linux/pci.h>
16e8d74d
MT		 49#include <linux/timekeeper_internal.h>
50#include <linux/pvclock_gtod.h>
aec51dc4 51#include <trace/events/kvm.h>
2ed152af 52
229456fc
MT		 53#define CREATE_TRACE_POINTS
54#include "trace.h"
043405e1 55
24f1e32c 56#include <asm/debugreg.h>
d825ed0a 57#include <asm/msr.h>
a5f61300 58#include <asm/desc.h>
0bed3b56 59#include <asm/mtrr.h>
890ca9ae 60#include <asm/mce.h>
7cf30855 61#include <asm/i387.h>
1361b83a 62#include <asm/fpu-internal.h> /* Ugh! */
98918833 63#include <asm/xcr.h>
1d5f066e 64#include <asm/pvclock.h>
217fc9cf 65#include <asm/div64.h>
043405e1 66
313a3dc7 67#define MAX_IO_MSRS 256
890ca9ae 68#define KVM_MAX_MCE_BANKS 32
5854dbca 69#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 70
0f65dd70
AK		 71#define emul_to_vcpu(ctxt) \
72 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
73
50a37eb4
JR		 74/* EFER defaults:
75 * - enable syscall per default because its emulated by KVM
76 * - enable LME and LMA per default on 64 bit KVM
77 */
78#ifdef CONFIG_X86_64
1260edbe
LJ		 79static
80u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 81#else
1260edbe 82static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 83#endif
313a3dc7 84
ba1389b7
AK		 85#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
86#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 87
cb142eb7 88static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 89static void process_nmi(struct kvm_vcpu *vcpu);
674eea0f 90
97896d04 91struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 92EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 93
476bc001
RR		 94static bool ignore_msrs = 0;
95module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 96
92a1f12d
JR		 97bool kvm_has_tsc_control;
98EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
99u32 kvm_max_guest_tsc_khz;
100EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
101
cc578287
ZA		 102/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
103static u32 tsc_tolerance_ppm = 250;
104module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
105
18863bdd
AK		 106#define KVM_NR_SHARED_MSRS 16
107
108struct kvm_shared_msrs_global {
109 int nr;
2bf78fa7 110 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 111};
112
113struct kvm_shared_msrs {
114 struct user_return_notifier urn;
115 bool registered;
2bf78fa7
SY		 116 struct kvm_shared_msr_values {
117 u64 host;
118 u64 curr;
119 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 120};
121
122static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 123static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 124
417bc304 125struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 126 { "pf_fixed", VCPU_STAT(pf_fixed) },
127 { "pf_guest", VCPU_STAT(pf_guest) },
128 { "tlb_flush", VCPU_STAT(tlb_flush) },
129 { "invlpg", VCPU_STAT(invlpg) },
130 { "exits", VCPU_STAT(exits) },
131 { "io_exits", VCPU_STAT(io_exits) },
132 { "mmio_exits", VCPU_STAT(mmio_exits) },
133 { "signal_exits", VCPU_STAT(signal_exits) },
134 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 135 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 136 { "halt_exits", VCPU_STAT(halt_exits) },
137 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 138 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 139 { "request_irq", VCPU_STAT(request_irq_exits) },
140 { "irq_exits", VCPU_STAT(irq_exits) },
141 { "host_state_reload", VCPU_STAT(host_state_reload) },
142 { "efer_reload", VCPU_STAT(efer_reload) },
143 { "fpu_reload", VCPU_STAT(fpu_reload) },
144 { "insn_emulation", VCPU_STAT(insn_emulation) },
145 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 146 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 147 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 148 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
149 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
150 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
151 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
152 { "mmu_flooded", VM_STAT(mmu_flooded) },
153 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 154 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 155 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 156 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 157 { "largepages", VM_STAT(lpages) },
417bc304
HB		 158 { NULL }
159};
160
2acf923e
DC		 161u64 __read_mostly host_xcr0;
162
b6785def 163static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 164
af585b92
GN		 165static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
166{
167 int i;
168 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
169 vcpu->arch.apf.gfns[i] = ~0;
170}
171
18863bdd
AK		 172static void kvm_on_user_return(struct user_return_notifier *urn)
173{
174 unsigned slot;
18863bdd
AK		 175 struct kvm_shared_msrs *locals
176 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 177 struct kvm_shared_msr_values *values;
18863bdd
AK		 178
179 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 180 values = &locals->values[slot];
181 if (values->host != values->curr) {
182 wrmsrl(shared_msrs_global.msrs[slot], values->host);
183 values->curr = values->host;
18863bdd
AK		 184 }
185 }
186 locals->registered = false;
187 user_return_notifier_unregister(urn);
188}
189
2bf78fa7 190static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 191{
18863bdd 192 u64 value;
013f6a5d
MT		 193 unsigned int cpu = smp_processor_id();
194 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 195
2bf78fa7
SY		 196 /* only read, and nobody should modify it at this time,
197 * so don't need lock */
198 if (slot >= shared_msrs_global.nr) {
199 printk(KERN_ERR "kvm: invalid MSR slot!");
200 return;
201 }
202 rdmsrl_safe(msr, &value);
203 smsr->values[slot].host = value;
204 smsr->values[slot].curr = value;
205}
206
207void kvm_define_shared_msr(unsigned slot, u32 msr)
208{
18863bdd
AK		 209 if (slot >= shared_msrs_global.nr)
210 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 211 shared_msrs_global.msrs[slot] = msr;
212 /* we need ensured the shared_msr_global have been updated */
213 smp_wmb();
18863bdd
AK		 214}
215EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
216
217static void kvm_shared_msr_cpu_online(void)
218{
219 unsigned i;
18863bdd
AK		 220
221 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 222 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 223}
224
d5696725 225void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 226{
013f6a5d
MT		 227 unsigned int cpu = smp_processor_id();
228 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 229
2bf78fa7 230 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 231 return;
2bf78fa7
SY		 232 smsr->values[slot].curr = value;
233 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 234 if (!smsr->registered) {
235 smsr->urn.on_user_return = kvm_on_user_return;
236 user_return_notifier_register(&smsr->urn);
237 smsr->registered = true;
238 }
239}
240EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
241
3548bab5
AK		 242static void drop_user_return_notifiers(void *ignore)
243{
013f6a5d
MT		 244 unsigned int cpu = smp_processor_id();
245 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 246
247 if (smsr->registered)
248 kvm_on_user_return(&smsr->urn);
249}
250
6866b83e
CO		 251u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
252{
8a5a87d9 253 return vcpu->arch.apic_base;
6866b83e
CO		 254}
255EXPORT_SYMBOL_GPL(kvm_get_apic_base);
256
257void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
258{
259 /* TODO: reserve bits check */
8a5a87d9 260 kvm_lapic_set_base(vcpu, data);
6866b83e
CO		 261}
262EXPORT_SYMBOL_GPL(kvm_set_apic_base);
263
e3ba45b8
GL		 264asmlinkage void kvm_spurious_fault(void)
265{
266 /* Fault while not rebooting. We want the trace. */
267 BUG();
268}
269EXPORT_SYMBOL_GPL(kvm_spurious_fault);
270
3fd28fce
ED		 271#define EXCPT_BENIGN 0
272#define EXCPT_CONTRIBUTORY 1
273#define EXCPT_PF 2
274
275static int exception_class(int vector)
276{
277 switch (vector) {
278 case PF_VECTOR:
279 return EXCPT_PF;
280 case DE_VECTOR:
281 case TS_VECTOR:
282 case NP_VECTOR:
283 case SS_VECTOR:
284 case GP_VECTOR:
285 return EXCPT_CONTRIBUTORY;
286 default:
287 break;
288 }
289 return EXCPT_BENIGN;
290}
291
292static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 293 unsigned nr, bool has_error, u32 error_code,
294 bool reinject)
3fd28fce
ED		 295{
296 u32 prev_nr;
297 int class1, class2;
298
3842d135
AK		 299 kvm_make_request(KVM_REQ_EVENT, vcpu);
300
3fd28fce
ED		 301 if (!vcpu->arch.exception.pending) {
302 queue:
303 vcpu->arch.exception.pending = true;
304 vcpu->arch.exception.has_error_code = has_error;
305 vcpu->arch.exception.nr = nr;
306 vcpu->arch.exception.error_code = error_code;
3f0fd292 307 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 308 return;
309 }
310
311 /* to check exception */
312 prev_nr = vcpu->arch.exception.nr;
313 if (prev_nr == DF_VECTOR) {
314 /* triple fault -> shutdown */
a8eeb04a 315 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 316 return;
317 }
318 class1 = exception_class(prev_nr);
319 class2 = exception_class(nr);
320 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
321 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
322 /* generate double fault per SDM Table 5-5 */
323 vcpu->arch.exception.pending = true;
324 vcpu->arch.exception.has_error_code = true;
325 vcpu->arch.exception.nr = DF_VECTOR;
326 vcpu->arch.exception.error_code = 0;
327 } else
328 /* replace previous exception with a new one in a hope
329 that instruction re-execution will regenerate lost
330 exception */
331 goto queue;
332}
333
298101da
AK		 334void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
335{
ce7ddec4 336 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 337}
338EXPORT_SYMBOL_GPL(kvm_queue_exception);
339
ce7ddec4
JR		 340void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
341{
342 kvm_multiple_exception(vcpu, nr, false, 0, true);
343}
344EXPORT_SYMBOL_GPL(kvm_requeue_exception);
345
db8fcefa 346void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 347{
db8fcefa
AP		 348 if (err)
349 kvm_inject_gp(vcpu, 0);
350 else
351 kvm_x86_ops->skip_emulated_instruction(vcpu);
352}
353EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 354
6389ee94 355void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 356{
357 ++vcpu->stat.pf_guest;
6389ee94
AK		 358 vcpu->arch.cr2 = fault->address;
359 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 360}
27d6c865 361EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 362
6389ee94 363void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 364{
6389ee94
AK		 365 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
366 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 367 else
6389ee94 368 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
d4f8cf66
JR		 369}
370
3419ffc8
SY		 371void kvm_inject_nmi(struct kvm_vcpu *vcpu)
372{
7460fb4a
AK		 373 atomic_inc(&vcpu->arch.nmi_queued);
374 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 375}
376EXPORT_SYMBOL_GPL(kvm_inject_nmi);
377
298101da
AK		 378void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
379{
ce7ddec4 380 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 381}
382EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
383
ce7ddec4
JR		 384void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
385{
386 kvm_multiple_exception(vcpu, nr, true, error_code, true);
387}
388EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
389
0a79b009
AK		 390/*
391 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
392 * a #GP and return false.
393 */
394bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 395{
0a79b009
AK		 396 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
397 return true;
398 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
399 return false;
298101da 400}
0a79b009 401EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 402
ec92fe44
JR		 403/*
404 * This function will be used to read from the physical memory of the currently
405 * running guest. The difference to kvm_read_guest_page is that this function
406 * can read from guest physical or from the guest's guest physical memory.
407 */
408int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
409 gfn_t ngfn, void *data, int offset, int len,
410 u32 access)
411{
412 gfn_t real_gfn;
413 gpa_t ngpa;
414
415 ngpa = gfn_to_gpa(ngfn);
416 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
417 if (real_gfn == UNMAPPED_GVA)
418 return -EFAULT;
419
420 real_gfn = gpa_to_gfn(real_gfn);
421
422 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
423}
424EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
425
3d06b8bf
JR		 426int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
427 void *data, int offset, int len, u32 access)
428{
429 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
430 data, offset, len, access);
431}
432
a03490ed
CO		 433/*
434 * Load the pae pdptrs. Return true is they are all valid.
435 */
ff03a073 436int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 437{
438 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
439 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
440 int i;
441 int ret;
ff03a073 442 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 443
ff03a073
JR		 444 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
445 offset * sizeof(u64), sizeof(pdpte),
446 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 447 if (ret < 0) {
448 ret = 0;
449 goto out;
450 }
451 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 452 if (is_present_gpte(pdpte[i]) &&
20c466b5 453 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 454 ret = 0;
455 goto out;
456 }
457 }
458 ret = 1;
459
ff03a073 460 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 461 __set_bit(VCPU_EXREG_PDPTR,
462 (unsigned long *)&vcpu->arch.regs_avail);
463 __set_bit(VCPU_EXREG_PDPTR,
464 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 465out:
a03490ed
CO		 466
467 return ret;
468}
cc4b6871 469EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 470
d835dfec
AK		 471static bool pdptrs_changed(struct kvm_vcpu *vcpu)
472{
ff03a073 473 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 474 bool changed = true;
3d06b8bf
JR		 475 int offset;
476 gfn_t gfn;
d835dfec
AK		 477 int r;
478
479 if (is_long_mode(vcpu) || !is_pae(vcpu))
480 return false;
481
6de4f3ad
AK		 482 if (!test_bit(VCPU_EXREG_PDPTR,
483 (unsigned long *)&vcpu->arch.regs_avail))
484 return true;
485
9f8fe504
AK		 486 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
487 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 488 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
489 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 490 if (r < 0)
491 goto out;
ff03a073 492 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 493out:
d835dfec
AK		 494
495 return changed;
496}
497
49a9b07e 498int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 499{
aad82703
SY		 500 unsigned long old_cr0 = kvm_read_cr0(vcpu);
501 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
502 X86_CR0_CD | X86_CR0_NW;
503
f9a48e6a
AK		 504 cr0 |= X86_CR0_ET;
505
ab344828 506#ifdef CONFIG_X86_64
0f12244f
GN		 507 if (cr0 & 0xffffffff00000000UL)
508 return 1;
ab344828
GN		 509#endif
510
511 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 512
0f12244f
GN		 513 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
514 return 1;
a03490ed 515
0f12244f
GN		 516 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
517 return 1;
a03490ed
CO		 518
519 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
520#ifdef CONFIG_X86_64
f6801dff 521 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 522 int cs_db, cs_l;
523
0f12244f
GN		 524 if (!is_pae(vcpu))
525 return 1;
a03490ed 526 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 527 if (cs_l)
528 return 1;
a03490ed
CO		 529 } else
530#endif
ff03a073 531 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 532 kvm_read_cr3(vcpu)))
0f12244f 533 return 1;
a03490ed
CO		 534 }
535
ad756a16
MJ		 536 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
537 return 1;
538
a03490ed 539 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 540
d170c419 541 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 542 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 543 kvm_async_pf_hash_reset(vcpu);
544 }
e5f3f027 545
aad82703
SY		 546 if ((cr0 ^ old_cr0) & update_bits)
547 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 548 return 0;
549}
2d3ad1f4 550EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 551
2d3ad1f4 552void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 553{
49a9b07e 554 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 555}
2d3ad1f4 556EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 557
2acf923e
DC		 558int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
559{
560 u64 xcr0;
561
562 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
563 if (index != XCR_XFEATURE_ENABLED_MASK)
564 return 1;
565 xcr0 = xcr;
566 if (kvm_x86_ops->get_cpl(vcpu) != 0)
567 return 1;
568 if (!(xcr0 & XSTATE_FP))
569 return 1;
570 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
571 return 1;
572 if (xcr0 & ~host_xcr0)
573 return 1;
574 vcpu->arch.xcr0 = xcr0;
575 vcpu->guest_xcr0_loaded = 0;
576 return 0;
577}
578
579int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
580{
581 if (__kvm_set_xcr(vcpu, index, xcr)) {
582 kvm_inject_gp(vcpu, 0);
583 return 1;
584 }
585 return 0;
586}
587EXPORT_SYMBOL_GPL(kvm_set_xcr);
588
a83b29c6 589int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 590{
fc78f519 591 unsigned long old_cr4 = kvm_read_cr4(vcpu);
c68b734f
YW		 592 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
593 X86_CR4_PAE | X86_CR4_SMEP;
0f12244f
GN		 594 if (cr4 & CR4_RESERVED_BITS)
595 return 1;
a03490ed 596
2acf923e
DC		 597 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
598 return 1;
599
c68b734f
YW		 600 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
601 return 1;
602
74dc2b4f
YW		 603 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_RDWRGSFS))
604 return 1;
605
a03490ed 606 if (is_long_mode(vcpu)) {
0f12244f
GN		 607 if (!(cr4 & X86_CR4_PAE))
608 return 1;
a2edf57f
AK		 609 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
610 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 611 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
612 kvm_read_cr3(vcpu)))
0f12244f
GN		 613 return 1;
614
ad756a16
MJ		 615 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
616 if (!guest_cpuid_has_pcid(vcpu))
617 return 1;
618
619 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
620 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
621 return 1;
622 }
623
5e1746d6 624 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 625 return 1;
a03490ed 626
ad756a16
MJ		 627 if (((cr4 ^ old_cr4) & pdptr_bits) ||
628 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 629 kvm_mmu_reset_context(vcpu);
0f12244f 630
2acf923e 631 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 632 kvm_update_cpuid(vcpu);
2acf923e 633
0f12244f
GN		 634 return 0;
635}
2d3ad1f4 636EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 637
2390218b 638int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 639{
9f8fe504 640 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 641 kvm_mmu_sync_roots(vcpu);
d835dfec 642 kvm_mmu_flush_tlb(vcpu);
0f12244f 643 return 0;
d835dfec
AK		 644 }
645
a03490ed 646 if (is_long_mode(vcpu)) {
471842ec 647 if (kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) {
ad756a16
MJ		 648 if (cr3 & CR3_PCID_ENABLED_RESERVED_BITS)
649 return 1;
650 } else
651 if (cr3 & CR3_L_MODE_RESERVED_BITS)
652 return 1;
a03490ed
CO		 653 } else {
654 if (is_pae(vcpu)) {
0f12244f
GN		 655 if (cr3 & CR3_PAE_RESERVED_BITS)
656 return 1;
ff03a073
JR		 657 if (is_paging(vcpu) &&
658 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
0f12244f 659 return 1;
a03490ed
CO		 660 }
661 /*
662 * We don't check reserved bits in nonpae mode, because
663 * this isn't enforced, and VMware depends on this.
664 */
665 }
666
a03490ed
CO		 667 /*
668 * Does the new cr3 value map to physical memory? (Note, we
669 * catch an invalid cr3 even in real-mode, because it would
670 * cause trouble later on when we turn on paging anyway.)
671 *
672 * A real CPU would silently accept an invalid cr3 and would
673 * attempt to use it - with largely undefined (and often hard
674 * to debug) behavior on the guest side.
675 */
676 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
0f12244f
GN		 677 return 1;
678 vcpu->arch.cr3 = cr3;
aff48baa 679 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
0f12244f
GN		 680 vcpu->arch.mmu.new_cr3(vcpu);
681 return 0;
682}
2d3ad1f4 683EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 684
eea1cff9 685int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 686{
0f12244f
GN		 687 if (cr8 & CR8_RESERVED_BITS)
688 return 1;
a03490ed
CO		 689 if (irqchip_in_kernel(vcpu->kvm))
690 kvm_lapic_set_tpr(vcpu, cr8);
691 else
ad312c7c 692 vcpu->arch.cr8 = cr8;
0f12244f
GN		 693 return 0;
694}
2d3ad1f4 695EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 696
2d3ad1f4 697unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 698{
699 if (irqchip_in_kernel(vcpu->kvm))
700 return kvm_lapic_get_cr8(vcpu);
701 else
ad312c7c 702 return vcpu->arch.cr8;
a03490ed 703}
2d3ad1f4 704EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 705
c8639010
JK		 706static void kvm_update_dr7(struct kvm_vcpu *vcpu)
707{
708 unsigned long dr7;
709
710 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
711 dr7 = vcpu->arch.guest_debug_dr7;
712 else
713 dr7 = vcpu->arch.dr7;
714 kvm_x86_ops->set_dr7(vcpu, dr7);
715 vcpu->arch.switch_db_regs = (dr7 & DR7_BP_EN_MASK);
716}
717
338dbc97 718static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 719{
720 switch (dr) {
721 case 0 ... 3:
722 vcpu->arch.db[dr] = val;
723 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
724 vcpu->arch.eff_db[dr] = val;
725 break;
726 case 4:
338dbc97
GN		 727 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
728 return 1; /* #UD */
020df079
GN		 729 /* fall through */
730 case 6:
338dbc97
GN		 731 if (val & 0xffffffff00000000ULL)
732 return -1; /* #GP */
020df079
GN		 733 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
734 break;
735 case 5:
338dbc97
GN		 736 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
737 return 1; /* #UD */
020df079
GN		 738 /* fall through */
739 default: /* 7 */
338dbc97
GN		 740 if (val & 0xffffffff00000000ULL)
741 return -1; /* #GP */
020df079 742 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 743 kvm_update_dr7(vcpu);
020df079
GN		 744 break;
745 }
746
747 return 0;
748}
338dbc97
GN		 749
750int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
751{
752 int res;
753
754 res = __kvm_set_dr(vcpu, dr, val);
755 if (res > 0)
756 kvm_queue_exception(vcpu, UD_VECTOR);
757 else if (res < 0)
758 kvm_inject_gp(vcpu, 0);
759
760 return res;
761}
020df079
GN		 762EXPORT_SYMBOL_GPL(kvm_set_dr);
763
338dbc97 764static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 765{
766 switch (dr) {
767 case 0 ... 3:
768 *val = vcpu->arch.db[dr];
769 break;
770 case 4:
338dbc97 771 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 772 return 1;
020df079
GN		 773 /* fall through */
774 case 6:
775 *val = vcpu->arch.dr6;
776 break;
777 case 5:
338dbc97 778 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 779 return 1;
020df079
GN		 780 /* fall through */
781 default: /* 7 */
782 *val = vcpu->arch.dr7;
783 break;
784 }
785
786 return 0;
787}
338dbc97
GN		 788
789int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
790{
791 if (_kvm_get_dr(vcpu, dr, val)) {
792 kvm_queue_exception(vcpu, UD_VECTOR);
793 return 1;
794 }
795 return 0;
796}
020df079
GN		 797EXPORT_SYMBOL_GPL(kvm_get_dr);
798
022cd0e8
AK		 799bool kvm_rdpmc(struct kvm_vcpu *vcpu)
800{
801 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
802 u64 data;
803 int err;
804
805 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
806 if (err)
807 return err;
808 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
809 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
810 return err;
811}
812EXPORT_SYMBOL_GPL(kvm_rdpmc);
813
043405e1
CO		 814/*
815 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
816 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
817 *
818 * This list is modified at module load time to reflect the
e3267cbb
GC		 819 * capabilities of the host cpu. This capabilities test skips MSRs that are
820 * kvm-specific. Those are put in the beginning of the list.
043405e1 821 */
e3267cbb 822
439793d4 823#define KVM_SAVE_MSRS_BEGIN 10
043405e1 824static u32 msrs_to_save[] = {
e3267cbb 825 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 826 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 827 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
c9aaa895 828 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
ae7a2a3f 829 MSR_KVM_PV_EOI_EN,
043405e1 830 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 831 MSR_STAR,
043405e1
CO		 832#ifdef CONFIG_X86_64
833 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
834#endif
e90aa41e 835 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 836};
837
838static unsigned num_msrs_to_save;
839
f1d24831 840static const u32 emulated_msrs[] = {
ba904635 841 MSR_IA32_TSC_ADJUST,
a3e06bbe 842 MSR_IA32_TSCDEADLINE,
043405e1 843 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 844 MSR_IA32_MCG_STATUS,
845 MSR_IA32_MCG_CTL,
043405e1
CO		 846};
847
384bb783 848bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 849{
b69e8cae 850 if (efer & efer_reserved_bits)
384bb783 851 return false;
15c4a640 852
1b2fd70c
AG		 853 if (efer & EFER_FFXSR) {
854 struct kvm_cpuid_entry2 *feat;
855
856 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 857 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 858 return false;
1b2fd70c
AG		 859 }
860
d8017474
AG		 861 if (efer & EFER_SVME) {
862 struct kvm_cpuid_entry2 *feat;
863
864 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 865 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 866 return false;
d8017474
AG		 867 }
868
384bb783
JK		 869 return true;
870}
871EXPORT_SYMBOL_GPL(kvm_valid_efer);
872
873static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
874{
875 u64 old_efer = vcpu->arch.efer;
876
877 if (!kvm_valid_efer(vcpu, efer))
878 return 1;
879
880 if (is_paging(vcpu)
881 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
882 return 1;
883
15c4a640 884 efer &= ~EFER_LMA;
f6801dff 885 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 886
a3d204e2
SY		 887 kvm_x86_ops->set_efer(vcpu, efer);
888
aad82703
SY		 889 /* Update reserved bits */
890 if ((efer ^ old_efer) & EFER_NX)
891 kvm_mmu_reset_context(vcpu);
892
b69e8cae 893 return 0;
15c4a640
CO		 894}
895
f2b4b7dd
JR		 896void kvm_enable_efer_bits(u64 mask)
897{
898 efer_reserved_bits &= ~mask;
899}
900EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
901
902
15c4a640
CO		 903/*
904 * Writes msr value into into the appropriate "register".
905 * Returns 0 on success, non-0 otherwise.
906 * Assumes vcpu_load() was already called.
907 */
8fe8ab46 908int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 909{
8fe8ab46 910 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640
CO		 911}
912
313a3dc7
CO		 913/*
914 * Adapt set_msr() to msr_io()'s calling convention
915 */
916static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
917{
8fe8ab46
WA		 918 struct msr_data msr;
919
920 msr.data = *data;
921 msr.index = index;
922 msr.host_initiated = true;
923 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 924}
925
16e8d74d
MT		 926#ifdef CONFIG_X86_64
927struct pvclock_gtod_data {
928 seqcount_t seq;
929
930 struct { /* extract of a clocksource struct */
931 int vclock_mode;
932 cycle_t cycle_last;
933 cycle_t mask;
934 u32 mult;
935 u32 shift;
936 } clock;
937
938 /* open coded 'struct timespec' */
939 u64 monotonic_time_snsec;
940 time_t monotonic_time_sec;
941};
942
943static struct pvclock_gtod_data pvclock_gtod_data;
944
945static void update_pvclock_gtod(struct timekeeper *tk)
946{
947 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
948
949 write_seqcount_begin(&vdata->seq);
950
951 /* copy pvclock gtod data */
952 vdata->clock.vclock_mode = tk->clock->archdata.vclock_mode;
953 vdata->clock.cycle_last = tk->clock->cycle_last;
954 vdata->clock.mask = tk->clock->mask;
955 vdata->clock.mult = tk->mult;
956 vdata->clock.shift = tk->shift;
957
958 vdata->monotonic_time_sec = tk->xtime_sec
959 + tk->wall_to_monotonic.tv_sec;
960 vdata->monotonic_time_snsec = tk->xtime_nsec
961 + (tk->wall_to_monotonic.tv_nsec
962 << tk->shift);
963 while (vdata->monotonic_time_snsec >=
964 (((u64)NSEC_PER_SEC) << tk->shift)) {
965 vdata->monotonic_time_snsec -=
966 ((u64)NSEC_PER_SEC) << tk->shift;
967 vdata->monotonic_time_sec++;
968 }
969
970 write_seqcount_end(&vdata->seq);
971}
972#endif
973
974
18068523
GOC		 975static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
976{
9ed3c444
AK		 977 int version;
978 int r;
50d0a0f9 979 struct pvclock_wall_clock wc;
923de3cf 980 struct timespec boot;
18068523
GOC		 981
982 if (!wall_clock)
983 return;
984
9ed3c444
AK		 985 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
986 if (r)
987 return;
988
989 if (version & 1)
990 ++version; /* first time write, random junk */
991
992 ++version;
18068523 993
18068523
GOC		 994 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
995
50d0a0f9
GH		 996 /*
997 * The guest calculates current wall clock time by adding
34c238a1 998 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 999 * wall clock specified here. guest system time equals host
1000 * system time for us, thus we must fill in host boot time here.
1001 */
923de3cf 1002 getboottime(&boot);
50d0a0f9 1003
4b648665
BR		 1004 if (kvm->arch.kvmclock_offset) {
1005 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1006 boot = timespec_sub(boot, ts);
1007 }
50d0a0f9
GH		 1008 wc.sec = boot.tv_sec;
1009 wc.nsec = boot.tv_nsec;
1010 wc.version = version;
18068523
GOC		 1011
1012 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1013
1014 version++;
1015 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1016}
1017
50d0a0f9
GH		 1018static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1019{
1020 uint32_t quotient, remainder;
1021
1022 /* Don't try to replace with do_div(), this one calculates
1023 * "(dividend << 32) / divisor" */
1024 __asm__ ( "divl %4"
1025 : "=a" (quotient), "=d" (remainder)
1026 : "0" (0), "1" (dividend), "r" (divisor) );
1027 return quotient;
1028}
1029
5f4e3f88
ZA		 1030static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1031 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1032{
5f4e3f88 1033 uint64_t scaled64;
50d0a0f9
GH		 1034 int32_t shift = 0;
1035 uint64_t tps64;
1036 uint32_t tps32;
1037
5f4e3f88
ZA		 1038 tps64 = base_khz * 1000LL;
1039 scaled64 = scaled_khz * 1000LL;
50933623 1040 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1041 tps64 >>= 1;
1042 shift--;
1043 }
1044
1045 tps32 = (uint32_t)tps64;
50933623
JK		 1046 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1047 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1048 scaled64 >>= 1;
1049 else
1050 tps32 <<= 1;
50d0a0f9
GH		 1051 shift++;
1052 }
1053
5f4e3f88
ZA		 1054 *pshift = shift;
1055 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1056
5f4e3f88
ZA		 1057 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1058 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1059}
1060
759379dd
ZA		 1061static inline u64 get_kernel_ns(void)
1062{
1063 struct timespec ts;
1064
1065 WARN_ON(preemptible());
1066 ktime_get_ts(&ts);
1067 monotonic_to_bootbased(&ts);
1068 return timespec_to_ns(&ts);
50d0a0f9
GH		 1069}
1070
d828199e 1071#ifdef CONFIG_X86_64
16e8d74d 1072static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1073#endif
16e8d74d 1074
c8076604 1075static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 1076unsigned long max_tsc_khz;
c8076604 1077
cc578287 1078static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1079{
cc578287
ZA		 1080 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1081 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1082}
1083
cc578287 1084static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1085{
cc578287
ZA		 1086 u64 v = (u64)khz * (1000000 + ppm);
1087 do_div(v, 1000000);
1088 return v;
1e993611
JR		 1089}
1090
cc578287 1091static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1092{
cc578287
ZA		 1093 u32 thresh_lo, thresh_hi;
1094 int use_scaling = 0;
217fc9cf 1095
03ba32ca
MT		 1096 /* tsc_khz can be zero if TSC calibration fails */
1097 if (this_tsc_khz == 0)
1098 return;
1099
c285545f
ZA		 1100 /* Compute a scale to convert nanoseconds in TSC cycles */
1101 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1102 &vcpu->arch.virtual_tsc_shift,
1103 &vcpu->arch.virtual_tsc_mult);
1104 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1105
1106 /*
1107 * Compute the variation in TSC rate which is acceptable
1108 * within the range of tolerance and decide if the
1109 * rate being applied is within that bounds of the hardware
1110 * rate. If so, no scaling or compensation need be done.
1111 */
1112 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1113 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1114 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1115 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1116 use_scaling = 1;
1117 }
1118 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1119}
1120
1121static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1122{
e26101b1 1123 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1124 vcpu->arch.virtual_tsc_mult,
1125 vcpu->arch.virtual_tsc_shift);
e26101b1 1126 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1127 return tsc;
1128}
1129
b48aa97e
MT		 1130void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1131{
1132#ifdef CONFIG_X86_64
1133 bool vcpus_matched;
1134 bool do_request = false;
1135 struct kvm_arch *ka = &vcpu->kvm->arch;
1136 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1137
1138 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1139 atomic_read(&vcpu->kvm->online_vcpus));
1140
1141 if (vcpus_matched && gtod->clock.vclock_mode == VCLOCK_TSC)
1142 if (!ka->use_master_clock)
1143 do_request = 1;
1144
1145 if (!vcpus_matched && ka->use_master_clock)
1146 do_request = 1;
1147
1148 if (do_request)
1149 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1150
1151 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1152 atomic_read(&vcpu->kvm->online_vcpus),
1153 ka->use_master_clock, gtod->clock.vclock_mode);
1154#endif
1155}
1156
ba904635
WA		 1157static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1158{
1159 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1160 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1161}
1162
8fe8ab46 1163void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1164{
1165 struct kvm *kvm = vcpu->kvm;
f38e098f 1166 u64 offset, ns, elapsed;
99e3e30a 1167 unsigned long flags;
02626b6a 1168 s64 usdiff;
b48aa97e 1169 bool matched;
8fe8ab46 1170 u64 data = msr->data;
99e3e30a 1171
038f8c11 1172 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1173 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1174 ns = get_kernel_ns();
f38e098f 1175 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1176
03ba32ca
MT		 1177 if (vcpu->arch.virtual_tsc_khz) {
1178 /* n.b - signed multiplication and division required */
1179 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1180#ifdef CONFIG_X86_64
03ba32ca 1181 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1182#else
03ba32ca
MT		 1183 /* do_div() only does unsigned */
1184 asm("idivl %2; xor %%edx, %%edx"
1185 : "=A"(usdiff)
1186 : "A"(usdiff * 1000), "rm"(vcpu->arch.virtual_tsc_khz));
5d3cb0f6 1187#endif
03ba32ca
MT		 1188 do_div(elapsed, 1000);
1189 usdiff -= elapsed;
1190 if (usdiff < 0)
1191 usdiff = -usdiff;
1192 } else
1193 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1194
1195 /*
5d3cb0f6
ZA		 1196 * Special case: TSC write with a small delta (1 second) of virtual
1197 * cycle time against real time is interpreted as an attempt to
1198 * synchronize the CPU.
1199 *
1200 * For a reliable TSC, we can match TSC offsets, and for an unstable
1201 * TSC, we add elapsed time in this computation. We could let the
1202 * compensation code attempt to catch up if we fall behind, but
1203 * it's better to try to match offsets from the beginning.
1204 */
02626b6a 1205 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1206 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1207 if (!check_tsc_unstable()) {
e26101b1 1208 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1209 pr_debug("kvm: matched tsc offset for %llu\n", data);
1210 } else {
857e4099 1211 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1212 data += delta;
1213 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1214 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1215 }
b48aa97e 1216 matched = true;
e26101b1
ZA		 1217 } else {
1218 /*
1219 * We split periods of matched TSC writes into generations.
1220 * For each generation, we track the original measured
1221 * nanosecond time, offset, and write, so if TSCs are in
1222 * sync, we can match exact offset, and if not, we can match
4a969980 1223 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1224 *
1225 * These values are tracked in kvm->arch.cur_xxx variables.
1226 */
1227 kvm->arch.cur_tsc_generation++;
1228 kvm->arch.cur_tsc_nsec = ns;
1229 kvm->arch.cur_tsc_write = data;
1230 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1231 matched = false;
e26101b1
ZA		 1232 pr_debug("kvm: new tsc generation %u, clock %llu\n",
1233 kvm->arch.cur_tsc_generation, data);
f38e098f 1234 }
e26101b1
ZA		 1235
1236 /*
1237 * We also track th most recent recorded KHZ, write and time to
1238 * allow the matching interval to be extended at each write.
1239 */
f38e098f
ZA		 1240 kvm->arch.last_tsc_nsec = ns;
1241 kvm->arch.last_tsc_write = data;
5d3cb0f6 1242 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a
ZA		 1243
1244 /* Reset of TSC must disable overshoot protection below */
1245 vcpu->arch.hv_clock.tsc_timestamp = 0;
b183aa58 1246 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1247
1248 /* Keep track of which generation this VCPU has synchronized to */
1249 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1250 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1251 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1252
ba904635
WA		 1253 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1254 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1255 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1256 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1257
1258 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1259 if (matched)
1260 kvm->arch.nr_vcpus_matched_tsc++;
1261 else
1262 kvm->arch.nr_vcpus_matched_tsc = 0;
1263
1264 kvm_track_tsc_matching(vcpu);
1265 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1266}
e26101b1 1267
99e3e30a
ZA		 1268EXPORT_SYMBOL_GPL(kvm_write_tsc);
1269
d828199e
MT		 1270#ifdef CONFIG_X86_64
1271
1272static cycle_t read_tsc(void)
1273{
1274 cycle_t ret;
1275 u64 last;
1276
1277 /*
1278 * Empirically, a fence (of type that depends on the CPU)
1279 * before rdtsc is enough to ensure that rdtsc is ordered
1280 * with respect to loads. The various CPU manuals are unclear
1281 * as to whether rdtsc can be reordered with later loads,
1282 * but no one has ever seen it happen.
1283 */
1284 rdtsc_barrier();
1285 ret = (cycle_t)vget_cycles();
1286
1287 last = pvclock_gtod_data.clock.cycle_last;
1288
1289 if (likely(ret >= last))
1290 return ret;
1291
1292 /*
1293 * GCC likes to generate cmov here, but this branch is extremely
1294 * predictable (it's just a funciton of time and the likely is
1295 * very likely) and there's a data dependence, so force GCC
1296 * to generate a branch instead. I don't barrier() because
1297 * we don't actually need a barrier, and if this function
1298 * ever gets inlined it will generate worse code.
1299 */
1300 asm volatile ("");
1301 return last;
1302}
1303
1304static inline u64 vgettsc(cycle_t *cycle_now)
1305{
1306 long v;
1307 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1308
1309 *cycle_now = read_tsc();
1310
1311 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1312 return v * gtod->clock.mult;
1313}
1314
1315static int do_monotonic(struct timespec *ts, cycle_t *cycle_now)
1316{
1317 unsigned long seq;
1318 u64 ns;
1319 int mode;
1320 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1321
1322 ts->tv_nsec = 0;
1323 do {
1324 seq = read_seqcount_begin(&gtod->seq);
1325 mode = gtod->clock.vclock_mode;
1326 ts->tv_sec = gtod->monotonic_time_sec;
1327 ns = gtod->monotonic_time_snsec;
1328 ns += vgettsc(cycle_now);
1329 ns >>= gtod->clock.shift;
1330 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1331 timespec_add_ns(ts, ns);
1332
1333 return mode;
1334}
1335
1336/* returns true if host is using tsc clocksource */
1337static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1338{
1339 struct timespec ts;
1340
1341 /* checked again under seqlock below */
1342 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1343 return false;
1344
1345 if (do_monotonic(&ts, cycle_now) != VCLOCK_TSC)
1346 return false;
1347
1348 monotonic_to_bootbased(&ts);
1349 *kernel_ns = timespec_to_ns(&ts);
1350
1351 return true;
1352}
1353#endif
1354
1355/*
1356 *
b48aa97e
MT		 1357 * Assuming a stable TSC across physical CPUS, and a stable TSC
1358 * across virtual CPUs, the following condition is possible.
1359 * Each numbered line represents an event visible to both
d828199e
MT		 1360 * CPUs at the next numbered event.
1361 *
1362 * "timespecX" represents host monotonic time. "tscX" represents
1363 * RDTSC value.
1364 *
1365 * VCPU0 on CPU0 | VCPU1 on CPU1
1366 *
1367 * 1. read timespec0,tsc0
1368 * 2. | timespec1 = timespec0 + N
1369 * | tsc1 = tsc0 + M
1370 * 3. transition to guest | transition to guest
1371 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1372 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1373 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1374 *
1375 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1376 *
1377 * - ret0 < ret1
1378 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1379 * ...
1380 * - 0 < N - M => M < N
1381 *
1382 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1383 * always the case (the difference between two distinct xtime instances
1384 * might be smaller then the difference between corresponding TSC reads,
1385 * when updating guest vcpus pvclock areas).
1386 *
1387 * To avoid that problem, do not allow visibility of distinct
1388 * system_timestamp/tsc_timestamp values simultaneously: use a master
1389 * copy of host monotonic time values. Update that master copy
1390 * in lockstep.
1391 *
b48aa97e 1392 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1393 *
1394 */
1395
1396static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1397{
1398#ifdef CONFIG_X86_64
1399 struct kvm_arch *ka = &kvm->arch;
1400 int vclock_mode;
b48aa97e
MT		 1401 bool host_tsc_clocksource, vcpus_matched;
1402
1403 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1404 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1405
1406 /*
1407 * If the host uses TSC clock, then passthrough TSC as stable
1408 * to the guest.
1409 */
b48aa97e 1410 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1411 &ka->master_kernel_ns,
1412 &ka->master_cycle_now);
1413
b48aa97e
MT		 1414 ka->use_master_clock = host_tsc_clocksource & vcpus_matched;
1415
d828199e
MT		 1416 if (ka->use_master_clock)
1417 atomic_set(&kvm_guest_has_master_clock, 1);
1418
1419 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1420 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1421 vcpus_matched);
d828199e
MT		 1422#endif
1423}
1424
34c238a1 1425static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1426{
d828199e 1427 unsigned long flags, this_tsc_khz;
18068523 1428 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1429 struct kvm_arch *ka = &v->kvm->arch;
1d5f066e 1430 s64 kernel_ns, max_kernel_ns;
d828199e 1431 u64 tsc_timestamp, host_tsc;
0b79459b 1432 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1433 u8 pvclock_flags;
d828199e
MT		 1434 bool use_master_clock;
1435
1436 kernel_ns = 0;
1437 host_tsc = 0;
18068523 1438
d828199e
MT		 1439 /*
1440 * If the host uses TSC clock, then passthrough TSC as stable
1441 * to the guest.
1442 */
1443 spin_lock(&ka->pvclock_gtod_sync_lock);
1444 use_master_clock = ka->use_master_clock;
1445 if (use_master_clock) {
1446 host_tsc = ka->master_cycle_now;
1447 kernel_ns = ka->master_kernel_ns;
1448 }
1449 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1450
1451 /* Keep irq disabled to prevent changes to the clock */
1452 local_irq_save(flags);
1453 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1454 if (unlikely(this_tsc_khz == 0)) {
1455 local_irq_restore(flags);
1456 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1457 return 1;
1458 }
d828199e
MT		 1459 if (!use_master_clock) {
1460 host_tsc = native_read_tsc();
1461 kernel_ns = get_kernel_ns();
1462 }
1463
1464 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1465
c285545f
ZA		 1466 /*
1467 * We may have to catch up the TSC to match elapsed wall clock
1468 * time for two reasons, even if kvmclock is used.
1469 * 1) CPU could have been running below the maximum TSC rate
1470 * 2) Broken TSC compensation resets the base at each VCPU
1471 * entry to avoid unknown leaps of TSC even when running
1472 * again on the same CPU. This may cause apparent elapsed
1473 * time to disappear, and the guest to stand still or run
1474 * very slowly.
1475 */
1476 if (vcpu->tsc_catchup) {
1477 u64 tsc = compute_guest_tsc(v, kernel_ns);
1478 if (tsc > tsc_timestamp) {
f1e2b260 1479 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1480 tsc_timestamp = tsc;
1481 }
50d0a0f9
GH		 1482 }
1483
18068523
GOC		 1484 local_irq_restore(flags);
1485
0b79459b 1486 if (!vcpu->pv_time_enabled)
c285545f 1487 return 0;
18068523 1488
1d5f066e
ZA		 1489 /*
1490 * Time as measured by the TSC may go backwards when resetting the base
1491 * tsc_timestamp. The reason for this is that the TSC resolution is
1492 * higher than the resolution of the other clock scales. Thus, many
1493 * possible measurments of the TSC correspond to one measurement of any
1494 * other clock, and so a spread of values is possible. This is not a
1495 * problem for the computation of the nanosecond clock; with TSC rates
1496 * around 1GHZ, there can only be a few cycles which correspond to one
1497 * nanosecond value, and any path through this code will inevitably
1498 * take longer than that. However, with the kernel_ns value itself,
1499 * the precision may be much lower, down to HZ granularity. If the
1500 * first sampling of TSC against kernel_ns ends in the low part of the
1501 * range, and the second in the high end of the range, we can get:
1502 *
1503 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1504 *
1505 * As the sampling errors potentially range in the thousands of cycles,
1506 * it is possible such a time value has already been observed by the
1507 * guest. To protect against this, we must compute the system time as
1508 * observed by the guest and ensure the new system time is greater.
1509 */
1510 max_kernel_ns = 0;
b183aa58 1511 if (vcpu->hv_clock.tsc_timestamp) {
1d5f066e
ZA		 1512 max_kernel_ns = vcpu->last_guest_tsc -
1513 vcpu->hv_clock.tsc_timestamp;
1514 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1515 vcpu->hv_clock.tsc_to_system_mul,
1516 vcpu->hv_clock.tsc_shift);
1517 max_kernel_ns += vcpu->last_kernel_ns;
1518 }
afbcf7ab 1519
e48672fa 1520 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1521 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1522 &vcpu->hv_clock.tsc_shift,
1523 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1524 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1525 }
1526
d828199e
MT		 1527 /* with a master <monotonic time, tsc value> tuple,
1528 * pvclock clock reads always increase at the (scaled) rate
1529 * of guest TSC - no need to deal with sampling errors.
1530 */
1531 if (!use_master_clock) {
1532 if (max_kernel_ns > kernel_ns)
1533 kernel_ns = max_kernel_ns;
1534 }
8cfdc000 1535 /* With all the info we got, fill in the values */
1d5f066e 1536 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1537 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1d5f066e 1538 vcpu->last_kernel_ns = kernel_ns;
28e4639a 1539 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1540
18068523
GOC		 1541 /*
1542 * The interface expects us to write an even number signaling that the
1543 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1544 * state, we just increase by 2 at the end.
18068523 1545 */
50d0a0f9 1546 vcpu->hv_clock.version += 2;
18068523 1547
0b79459b
AH		 1548 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1549 &guest_hv_clock, sizeof(guest_hv_clock))))
1550 return 0;
78c0337a
MT		 1551
1552 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1553 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1554
1555 if (vcpu->pvclock_set_guest_stopped_request) {
1556 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1557 vcpu->pvclock_set_guest_stopped_request = false;
1558 }
1559
d828199e
MT		 1560 /* If the host uses TSC clocksource, then it is stable */
1561 if (use_master_clock)
1562 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1563
78c0337a
MT		 1564 vcpu->hv_clock.flags = pvclock_flags;
1565
0b79459b
AH		 1566 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1567 &vcpu->hv_clock,
1568 sizeof(vcpu->hv_clock));
8cfdc000 1569 return 0;
c8076604
GH		 1570}
1571
9ba075a6
AK		 1572static bool msr_mtrr_valid(unsigned msr)
1573{
1574 switch (msr) {
1575 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1576 case MSR_MTRRfix64K_00000:
1577 case MSR_MTRRfix16K_80000:
1578 case MSR_MTRRfix16K_A0000:
1579 case MSR_MTRRfix4K_C0000:
1580 case MSR_MTRRfix4K_C8000:
1581 case MSR_MTRRfix4K_D0000:
1582 case MSR_MTRRfix4K_D8000:
1583 case MSR_MTRRfix4K_E0000:
1584 case MSR_MTRRfix4K_E8000:
1585 case MSR_MTRRfix4K_F0000:
1586 case MSR_MTRRfix4K_F8000:
1587 case MSR_MTRRdefType:
1588 case MSR_IA32_CR_PAT:
1589 return true;
1590 case 0x2f8:
1591 return true;
1592 }
1593 return false;
1594}
1595
d6289b93
MT		 1596static bool valid_pat_type(unsigned t)
1597{
1598 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1599}
1600
1601static bool valid_mtrr_type(unsigned t)
1602{
1603 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1604}
1605
1606static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1607{
1608 int i;
1609
1610 if (!msr_mtrr_valid(msr))
1611 return false;
1612
1613 if (msr == MSR_IA32_CR_PAT) {
1614 for (i = 0; i < 8; i++)
1615 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1616 return false;
1617 return true;
1618 } else if (msr == MSR_MTRRdefType) {
1619 if (data & ~0xcff)
1620 return false;
1621 return valid_mtrr_type(data & 0xff);
1622 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1623 for (i = 0; i < 8 ; i++)
1624 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1625 return false;
1626 return true;
1627 }
1628
1629 /* variable MTRRs */
1630 return valid_mtrr_type(data & 0xff);
1631}
1632
9ba075a6
AK		 1633static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1634{
0bed3b56
SY		 1635 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1636
d6289b93 1637 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1638 return 1;
1639
0bed3b56
SY		 1640 if (msr == MSR_MTRRdefType) {
1641 vcpu->arch.mtrr_state.def_type = data;
1642 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1643 } else if (msr == MSR_MTRRfix64K_00000)
1644 p[0] = data;
1645 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1646 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1647 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1648 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1649 else if (msr == MSR_IA32_CR_PAT)
1650 vcpu->arch.pat = data;
1651 else { /* Variable MTRRs */
1652 int idx, is_mtrr_mask;
1653 u64 *pt;
1654
1655 idx = (msr - 0x200) / 2;
1656 is_mtrr_mask = msr - 0x200 - 2 * idx;
1657 if (!is_mtrr_mask)
1658 pt =
1659 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1660 else
1661 pt =
1662 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1663 *pt = data;
1664 }
1665
1666 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1667 return 0;
1668}
15c4a640 1669
890ca9ae 1670static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1671{
890ca9ae
HY		 1672 u64 mcg_cap = vcpu->arch.mcg_cap;
1673 unsigned bank_num = mcg_cap & 0xff;
1674
15c4a640 1675 switch (msr) {
15c4a640 1676 case MSR_IA32_MCG_STATUS:
890ca9ae 1677 vcpu->arch.mcg_status = data;
15c4a640 1678 break;
c7ac679c 1679 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1680 if (!(mcg_cap & MCG_CTL_P))
1681 return 1;
1682 if (data != 0 && data != ~(u64)0)
1683 return -1;
1684 vcpu->arch.mcg_ctl = data;
1685 break;
1686 default:
1687 if (msr >= MSR_IA32_MC0_CTL &&
1688 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1689 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1690 /* only 0 or all 1s can be written to IA32_MCi_CTL
1691 * some Linux kernels though clear bit 10 in bank 4 to
1692 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1693 * this to avoid an uncatched #GP in the guest
1694 */
890ca9ae 1695 if ((offset & 0x3) == 0 &&
114be429 1696 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1697 return -1;
1698 vcpu->arch.mce_banks[offset] = data;
1699 break;
1700 }
1701 return 1;
1702 }
1703 return 0;
1704}
1705
ffde22ac
ES		 1706static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1707{
1708 struct kvm *kvm = vcpu->kvm;
1709 int lm = is_long_mode(vcpu);
1710 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1711 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1712 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1713 : kvm->arch.xen_hvm_config.blob_size_32;
1714 u32 page_num = data & ~PAGE_MASK;
1715 u64 page_addr = data & PAGE_MASK;
1716 u8 *page;
1717 int r;
1718
1719 r = -E2BIG;
1720 if (page_num >= blob_size)
1721 goto out;
1722 r = -ENOMEM;
ff5c2c03
SL		 1723 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1724 if (IS_ERR(page)) {
1725 r = PTR_ERR(page);
ffde22ac 1726 goto out;
ff5c2c03 1727 }
ffde22ac
ES		 1728 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1729 goto out_free;
1730 r = 0;
1731out_free:
1732 kfree(page);
1733out:
1734 return r;
1735}
1736
55cd8e5a
GN		 1737static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1738{
1739 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1740}
1741
1742static bool kvm_hv_msr_partition_wide(u32 msr)
1743{
1744 bool r = false;
1745 switch (msr) {
1746 case HV_X64_MSR_GUEST_OS_ID:
1747 case HV_X64_MSR_HYPERCALL:
1748 r = true;
1749 break;
1750 }
1751
1752 return r;
1753}
1754
1755static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1756{
1757 struct kvm *kvm = vcpu->kvm;
1758
1759 switch (msr) {
1760 case HV_X64_MSR_GUEST_OS_ID:
1761 kvm->arch.hv_guest_os_id = data;
1762 /* setting guest os id to zero disables hypercall page */
1763 if (!kvm->arch.hv_guest_os_id)
1764 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1765 break;
1766 case HV_X64_MSR_HYPERCALL: {
1767 u64 gfn;
1768 unsigned long addr;
1769 u8 instructions[4];
1770
1771 /* if guest os id is not set hypercall should remain disabled */
1772 if (!kvm->arch.hv_guest_os_id)
1773 break;
1774 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1775 kvm->arch.hv_hypercall = data;
1776 break;
1777 }
1778 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1779 addr = gfn_to_hva(kvm, gfn);
1780 if (kvm_is_error_hva(addr))
1781 return 1;
1782 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1783 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1784 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1785 return 1;
1786 kvm->arch.hv_hypercall = data;
1787 break;
1788 }
1789 default:
a737f256
CD		 1790 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1791 "data 0x%llx\n", msr, data);
55cd8e5a
GN		 1792 return 1;
1793 }
1794 return 0;
1795}
1796
1797static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1798{
10388a07
GN		 1799 switch (msr) {
1800 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1801 unsigned long addr;
55cd8e5a 1802
10388a07
GN		 1803 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1804 vcpu->arch.hv_vapic = data;
1805 break;
1806 }
1807 addr = gfn_to_hva(vcpu->kvm, data >>
1808 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1809 if (kvm_is_error_hva(addr))
1810 return 1;
8b0cedff 1811 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 1812 return 1;
1813 vcpu->arch.hv_vapic = data;
1814 break;
1815 }
1816 case HV_X64_MSR_EOI:
1817 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1818 case HV_X64_MSR_ICR:
1819 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1820 case HV_X64_MSR_TPR:
1821 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1822 default:
a737f256
CD		 1823 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1824 "data 0x%llx\n", msr, data);
10388a07
GN		 1825 return 1;
1826 }
1827
1828 return 0;
55cd8e5a
GN		 1829}
1830
344d9588
GN		 1831static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1832{
1833 gpa_t gpa = data & ~0x3f;
1834
4a969980 1835 /* Bits 2:5 are reserved, Should be zero */
6adba527 1836 if (data & 0x3c)
344d9588
GN		 1837 return 1;
1838
1839 vcpu->arch.apf.msr_val = data;
1840
1841 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1842 kvm_clear_async_pf_completion_queue(vcpu);
1843 kvm_async_pf_hash_reset(vcpu);
1844 return 0;
1845 }
1846
1847 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa))
1848 return 1;
1849
6adba527 1850 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1851 kvm_async_pf_wakeup_all(vcpu);
1852 return 0;
1853}
1854
12f9a48f
GC		 1855static void kvmclock_reset(struct kvm_vcpu *vcpu)
1856{
0b79459b 1857 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 1858}
1859
c9aaa895
GC		 1860static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1861{
1862 u64 delta;
1863
1864 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1865 return;
1866
1867 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1868 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1869 vcpu->arch.st.accum_steal = delta;
1870}
1871
1872static void record_steal_time(struct kvm_vcpu *vcpu)
1873{
1874 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1875 return;
1876
1877 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1878 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1879 return;
1880
1881 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1882 vcpu->arch.st.steal.version += 2;
1883 vcpu->arch.st.accum_steal = 0;
1884
1885 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1886 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1887}
1888
8fe8ab46 1889int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 1890{
5753785f 1891 bool pr = false;
8fe8ab46
WA		 1892 u32 msr = msr_info->index;
1893 u64 data = msr_info->data;
5753785f 1894
15c4a640 1895 switch (msr) {
2e32b719
BP		 1896 case MSR_AMD64_NB_CFG:
1897 case MSR_IA32_UCODE_REV:
1898 case MSR_IA32_UCODE_WRITE:
1899 case MSR_VM_HSAVE_PA:
1900 case MSR_AMD64_PATCH_LOADER:
1901 case MSR_AMD64_BU_CFG2:
1902 break;
1903
15c4a640 1904 case MSR_EFER:
b69e8cae 1905 return set_efer(vcpu, data);
8f1589d9
AP		 1906 case MSR_K7_HWCR:
1907 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1908 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 1909 data &= ~(u64)0x8; /* ignore TLB cache disable */
8f1589d9 1910 if (data != 0) {
a737f256
CD		 1911 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1912 data);
8f1589d9
AP		 1913 return 1;
1914 }
15c4a640 1915 break;
f7c6d140
AP		 1916 case MSR_FAM10H_MMIO_CONF_BASE:
1917 if (data != 0) {
a737f256
CD		 1918 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1919 "0x%llx\n", data);
f7c6d140
AP		 1920 return 1;
1921 }
15c4a640 1922 break;
b5e2fec0
AG		 1923 case MSR_IA32_DEBUGCTLMSR:
1924 if (!data) {
1925 /* We support the non-activated case already */
1926 break;
1927 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1928 /* Values other than LBR and BTF are vendor-specific,
1929 thus reserved and should throw a #GP */
1930 return 1;
1931 }
a737f256
CD		 1932 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1933 __func__, data);
b5e2fec0 1934 break;
9ba075a6
AK		 1935 case 0x200 ... 0x2ff:
1936 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1937 case MSR_IA32_APICBASE:
1938 kvm_set_apic_base(vcpu, data);
1939 break;
0105d1a5
GN		 1940 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1941 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 1942 case MSR_IA32_TSCDEADLINE:
1943 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1944 break;
ba904635
WA		 1945 case MSR_IA32_TSC_ADJUST:
1946 if (guest_cpuid_has_tsc_adjust(vcpu)) {
1947 if (!msr_info->host_initiated) {
1948 u64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
1949 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
1950 }
1951 vcpu->arch.ia32_tsc_adjust_msr = data;
1952 }
1953 break;
15c4a640 1954 case MSR_IA32_MISC_ENABLE:
ad312c7c 1955 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1956 break;
11c6bffa 1957 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1958 case MSR_KVM_WALL_CLOCK:
1959 vcpu->kvm->arch.wall_clock = data;
1960 kvm_write_wall_clock(vcpu->kvm, data);
1961 break;
11c6bffa 1962 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 1963 case MSR_KVM_SYSTEM_TIME: {
0b79459b 1964 u64 gpa_offset;
12f9a48f 1965 kvmclock_reset(vcpu);
18068523
GOC		 1966
1967 vcpu->arch.time = data;
c285545f 1968 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
18068523
GOC		 1969
1970 /* we verify if the enable bit is set... */
1971 if (!(data & 1))
1972 break;
1973
0b79459b 1974 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 1975
c300aa64 1976 /* Check that the address is 32-byte aligned. */
0b79459b 1977 if (gpa_offset & (sizeof(struct pvclock_vcpu_time_info) - 1))
c300aa64 1978 break;
18068523 1979
0b79459b
AH		 1980 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
1981 &vcpu->arch.pv_time, data & ~1ULL))
1982 vcpu->arch.pv_time_enabled = false;
1983 else
1984 vcpu->arch.pv_time_enabled = true;
32cad84f 1985
18068523
GOC		 1986 break;
1987 }
344d9588
GN		 1988 case MSR_KVM_ASYNC_PF_EN:
1989 if (kvm_pv_enable_async_pf(vcpu, data))
1990 return 1;
1991 break;
c9aaa895
GC		 1992 case MSR_KVM_STEAL_TIME:
1993
1994 if (unlikely(!sched_info_on()))
1995 return 1;
1996
1997 if (data & KVM_STEAL_RESERVED_MASK)
1998 return 1;
1999
2000 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2001 data & KVM_STEAL_VALID_BITS))
2002 return 1;
2003
2004 vcpu->arch.st.msr_val = data;
2005
2006 if (!(data & KVM_MSR_ENABLED))
2007 break;
2008
2009 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2010
2011 preempt_disable();
2012 accumulate_steal_time(vcpu);
2013 preempt_enable();
2014
2015 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2016
2017 break;
ae7a2a3f
MT		 2018 case MSR_KVM_PV_EOI_EN:
2019 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2020 return 1;
2021 break;
c9aaa895 2022
890ca9ae
HY		 2023 case MSR_IA32_MCG_CTL:
2024 case MSR_IA32_MCG_STATUS:
2025 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2026 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 2027
2028 /* Performance counters are not protected by a CPUID bit,
2029 * so we should check all of them in the generic path for the sake of
2030 * cross vendor migration.
2031 * Writing a zero into the event select MSRs disables them,
2032 * which we perfectly emulate ;-). Any other value should be at least
2033 * reported, some guests depend on them.
2034 */
71db6023
AP		 2035 case MSR_K7_EVNTSEL0:
2036 case MSR_K7_EVNTSEL1:
2037 case MSR_K7_EVNTSEL2:
2038 case MSR_K7_EVNTSEL3:
2039 if (data != 0)
a737f256
CD		 2040 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2041 "0x%x data 0x%llx\n", msr, data);
71db6023
AP		 2042 break;
2043 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2044 * so we ignore writes to make it happy.
2045 */
71db6023
AP		 2046 case MSR_K7_PERFCTR0:
2047 case MSR_K7_PERFCTR1:
2048 case MSR_K7_PERFCTR2:
2049 case MSR_K7_PERFCTR3:
a737f256
CD		 2050 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2051 "0x%x data 0x%llx\n", msr, data);
71db6023 2052 break;
5753785f
GN		 2053 case MSR_P6_PERFCTR0:
2054 case MSR_P6_PERFCTR1:
2055 pr = true;
2056 case MSR_P6_EVNTSEL0:
2057 case MSR_P6_EVNTSEL1:
2058 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2059 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2060
2061 if (pr || data != 0)
a737f256
CD		 2062 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2063 "0x%x data 0x%llx\n", msr, data);
5753785f 2064 break;
84e0cefa
JS		 2065 case MSR_K7_CLK_CTL:
2066 /*
2067 * Ignore all writes to this no longer documented MSR.
2068 * Writes are only relevant for old K7 processors,
2069 * all pre-dating SVM, but a recommended workaround from
4a969980 2070 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2071 * affected processor models on the command line, hence
2072 * the need to ignore the workaround.
2073 */
2074 break;
55cd8e5a
GN		 2075 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2076 if (kvm_hv_msr_partition_wide(msr)) {
2077 int r;
2078 mutex_lock(&vcpu->kvm->lock);
2079 r = set_msr_hyperv_pw(vcpu, msr, data);
2080 mutex_unlock(&vcpu->kvm->lock);
2081 return r;
2082 } else
2083 return set_msr_hyperv(vcpu, msr, data);
2084 break;
91c9c3ed 2085 case MSR_IA32_BBL_CR_CTL3:
2086 /* Drop writes to this legacy MSR -- see rdmsr
2087 * counterpart for further detail.
2088 */
a737f256 2089 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2090 break;
2b036c6b
BO		 2091 case MSR_AMD64_OSVW_ID_LENGTH:
2092 if (!guest_cpuid_has_osvw(vcpu))
2093 return 1;
2094 vcpu->arch.osvw.length = data;
2095 break;
2096 case MSR_AMD64_OSVW_STATUS:
2097 if (!guest_cpuid_has_osvw(vcpu))
2098 return 1;
2099 vcpu->arch.osvw.status = data;
2100 break;
15c4a640 2101 default:
ffde22ac
ES		 2102 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2103 return xen_hvm_config(vcpu, data);
f5132b01 2104 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2105 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2106 if (!ignore_msrs) {
a737f256
CD		 2107 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2108 msr, data);
ed85c068
AP		 2109 return 1;
2110 } else {
a737f256
CD		 2111 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2112 msr, data);
ed85c068
AP		 2113 break;
2114 }
15c4a640
CO		 2115 }
2116 return 0;
2117}
2118EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2119
2120
2121/*
2122 * Reads an msr value (of 'msr_index') into 'pdata'.
2123 * Returns 0 on success, non-0 otherwise.
2124 * Assumes vcpu_load() was already called.
2125 */
2126int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2127{
2128 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2129}
2130
9ba075a6
AK		 2131static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2132{
0bed3b56
SY		 2133 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2134
9ba075a6
AK		 2135 if (!msr_mtrr_valid(msr))
2136 return 1;
2137
0bed3b56
SY		 2138 if (msr == MSR_MTRRdefType)
2139 *pdata = vcpu->arch.mtrr_state.def_type +
2140 (vcpu->arch.mtrr_state.enabled << 10);
2141 else if (msr == MSR_MTRRfix64K_00000)
2142 *pdata = p[0];
2143 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2144 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2145 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2146 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2147 else if (msr == MSR_IA32_CR_PAT)
2148 *pdata = vcpu->arch.pat;
2149 else { /* Variable MTRRs */
2150 int idx, is_mtrr_mask;
2151 u64 *pt;
2152
2153 idx = (msr - 0x200) / 2;
2154 is_mtrr_mask = msr - 0x200 - 2 * idx;
2155 if (!is_mtrr_mask)
2156 pt =
2157 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2158 else
2159 pt =
2160 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2161 *pdata = *pt;
2162 }
2163
9ba075a6
AK		 2164 return 0;
2165}
2166
890ca9ae 2167static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2168{
2169 u64 data;
890ca9ae
HY		 2170 u64 mcg_cap = vcpu->arch.mcg_cap;
2171 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2172
2173 switch (msr) {
15c4a640
CO		 2174 case MSR_IA32_P5_MC_ADDR:
2175 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2176 data = 0;
2177 break;
15c4a640 2178 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2179 data = vcpu->arch.mcg_cap;
2180 break;
c7ac679c 2181 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2182 if (!(mcg_cap & MCG_CTL_P))
2183 return 1;
2184 data = vcpu->arch.mcg_ctl;
2185 break;
2186 case MSR_IA32_MCG_STATUS:
2187 data = vcpu->arch.mcg_status;
2188 break;
2189 default:
2190 if (msr >= MSR_IA32_MC0_CTL &&
2191 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
2192 u32 offset = msr - MSR_IA32_MC0_CTL;
2193 data = vcpu->arch.mce_banks[offset];
2194 break;
2195 }
2196 return 1;
2197 }
2198 *pdata = data;
2199 return 0;
2200}
2201
55cd8e5a
GN		 2202static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2203{
2204 u64 data = 0;
2205 struct kvm *kvm = vcpu->kvm;
2206
2207 switch (msr) {
2208 case HV_X64_MSR_GUEST_OS_ID:
2209 data = kvm->arch.hv_guest_os_id;
2210 break;
2211 case HV_X64_MSR_HYPERCALL:
2212 data = kvm->arch.hv_hypercall;
2213 break;
2214 default:
a737f256 2215 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2216 return 1;
2217 }
2218
2219 *pdata = data;
2220 return 0;
2221}
2222
2223static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2224{
2225 u64 data = 0;
2226
2227 switch (msr) {
2228 case HV_X64_MSR_VP_INDEX: {
2229 int r;
2230 struct kvm_vcpu *v;
2231 kvm_for_each_vcpu(r, v, vcpu->kvm)
2232 if (v == vcpu)
2233 data = r;
2234 break;
2235 }
10388a07
GN		 2236 case HV_X64_MSR_EOI:
2237 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2238 case HV_X64_MSR_ICR:
2239 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2240 case HV_X64_MSR_TPR:
2241 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 2242 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 2243 data = vcpu->arch.hv_vapic;
2244 break;
55cd8e5a 2245 default:
a737f256 2246 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2247 return 1;
2248 }
2249 *pdata = data;
2250 return 0;
2251}
2252
890ca9ae
HY		 2253int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2254{
2255 u64 data;
2256
2257 switch (msr) {
890ca9ae 2258 case MSR_IA32_PLATFORM_ID:
15c4a640 2259 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2260 case MSR_IA32_DEBUGCTLMSR:
2261 case MSR_IA32_LASTBRANCHFROMIP:
2262 case MSR_IA32_LASTBRANCHTOIP:
2263 case MSR_IA32_LASTINTFROMIP:
2264 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 2265 case MSR_K8_SYSCFG:
2266 case MSR_K7_HWCR:
61a6bd67 2267 case MSR_VM_HSAVE_PA:
9e699624 2268 case MSR_K7_EVNTSEL0:
1f3ee616 2269 case MSR_K7_PERFCTR0:
1fdbd48c 2270 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2271 case MSR_AMD64_NB_CFG:
f7c6d140 2272 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2273 case MSR_AMD64_BU_CFG2:
15c4a640
CO		 2274 data = 0;
2275 break;
5753785f
GN		 2276 case MSR_P6_PERFCTR0:
2277 case MSR_P6_PERFCTR1:
2278 case MSR_P6_EVNTSEL0:
2279 case MSR_P6_EVNTSEL1:
2280 if (kvm_pmu_msr(vcpu, msr))
2281 return kvm_pmu_get_msr(vcpu, msr, pdata);
2282 data = 0;
2283 break;
742bc670
MT		 2284 case MSR_IA32_UCODE_REV:
2285 data = 0x100000000ULL;
2286 break;
9ba075a6
AK		 2287 case MSR_MTRRcap:
2288 data = 0x500 | KVM_NR_VAR_MTRR;
2289 break;
2290 case 0x200 ... 0x2ff:
2291 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 2292 case 0xcd: /* fsb frequency */
2293 data = 3;
2294 break;
7b914098
JS		 2295 /*
2296 * MSR_EBC_FREQUENCY_ID
2297 * Conservative value valid for even the basic CPU models.
2298 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2299 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2300 * and 266MHz for model 3, or 4. Set Core Clock
2301 * Frequency to System Bus Frequency Ratio to 1 (bits
2302 * 31:24) even though these are only valid for CPU
2303 * models > 2, however guests may end up dividing or
2304 * multiplying by zero otherwise.
2305 */
2306 case MSR_EBC_FREQUENCY_ID:
2307 data = 1 << 24;
2308 break;
15c4a640
CO		 2309 case MSR_IA32_APICBASE:
2310 data = kvm_get_apic_base(vcpu);
2311 break;
0105d1a5
GN		 2312 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2313 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2314 break;
a3e06bbe
LJ		 2315 case MSR_IA32_TSCDEADLINE:
2316 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2317 break;
ba904635
WA		 2318 case MSR_IA32_TSC_ADJUST:
2319 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2320 break;
15c4a640 2321 case MSR_IA32_MISC_ENABLE:
ad312c7c 2322 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2323 break;
847f0ad8
AG		 2324 case MSR_IA32_PERF_STATUS:
2325 /* TSC increment by tick */
2326 data = 1000ULL;
2327 /* CPU multiplier */
2328 data |= (((uint64_t)4ULL) << 40);
2329 break;
15c4a640 2330 case MSR_EFER:
f6801dff 2331 data = vcpu->arch.efer;
15c4a640 2332 break;
18068523 2333 case MSR_KVM_WALL_CLOCK:
11c6bffa 2334 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2335 data = vcpu->kvm->arch.wall_clock;
2336 break;
2337 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2338 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 2339 data = vcpu->arch.time;
2340 break;
344d9588
GN		 2341 case MSR_KVM_ASYNC_PF_EN:
2342 data = vcpu->arch.apf.msr_val;
2343 break;
c9aaa895
GC		 2344 case MSR_KVM_STEAL_TIME:
2345 data = vcpu->arch.st.msr_val;
2346 break;
1d92128f
MT		 2347 case MSR_KVM_PV_EOI_EN:
2348 data = vcpu->arch.pv_eoi.msr_val;
2349 break;
890ca9ae
HY		 2350 case MSR_IA32_P5_MC_ADDR:
2351 case MSR_IA32_P5_MC_TYPE:
2352 case MSR_IA32_MCG_CAP:
2353 case MSR_IA32_MCG_CTL:
2354 case MSR_IA32_MCG_STATUS:
2355 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2356 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 2357 case MSR_K7_CLK_CTL:
2358 /*
2359 * Provide expected ramp-up count for K7. All other
2360 * are set to zero, indicating minimum divisors for
2361 * every field.
2362 *
2363 * This prevents guest kernels on AMD host with CPU
2364 * type 6, model 8 and higher from exploding due to
2365 * the rdmsr failing.
2366 */
2367 data = 0x20000000;
2368 break;
55cd8e5a
GN		 2369 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2370 if (kvm_hv_msr_partition_wide(msr)) {
2371 int r;
2372 mutex_lock(&vcpu->kvm->lock);
2373 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2374 mutex_unlock(&vcpu->kvm->lock);
2375 return r;
2376 } else
2377 return get_msr_hyperv(vcpu, msr, pdata);
2378 break;
91c9c3ed 2379 case MSR_IA32_BBL_CR_CTL3:
2380 /* This legacy MSR exists but isn't fully documented in current
2381 * silicon. It is however accessed by winxp in very narrow
2382 * scenarios where it sets bit #19, itself documented as
2383 * a "reserved" bit. Best effort attempt to source coherent
2384 * read data here should the balance of the register be
2385 * interpreted by the guest:
2386 *
2387 * L2 cache control register 3: 64GB range, 256KB size,
2388 * enabled, latency 0x1, configured
2389 */
2390 data = 0xbe702111;
2391 break;
2b036c6b
BO		 2392 case MSR_AMD64_OSVW_ID_LENGTH:
2393 if (!guest_cpuid_has_osvw(vcpu))
2394 return 1;
2395 data = vcpu->arch.osvw.length;
2396 break;
2397 case MSR_AMD64_OSVW_STATUS:
2398 if (!guest_cpuid_has_osvw(vcpu))
2399 return 1;
2400 data = vcpu->arch.osvw.status;
2401 break;
15c4a640 2402 default:
f5132b01
GN		 2403 if (kvm_pmu_msr(vcpu, msr))
2404 return kvm_pmu_get_msr(vcpu, msr, pdata);
ed85c068 2405 if (!ignore_msrs) {
a737f256 2406 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
ed85c068
AP		 2407 return 1;
2408 } else {
a737f256 2409 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
ed85c068
AP		 2410 data = 0;
2411 }
2412 break;
15c4a640
CO		 2413 }
2414 *pdata = data;
2415 return 0;
2416}
2417EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2418
313a3dc7
CO		 2419/*
2420 * Read or write a bunch of msrs. All parameters are kernel addresses.
2421 *
2422 * @return number of msrs set successfully.
2423 */
2424static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2425 struct kvm_msr_entry *entries,
2426 int (*do_msr)(struct kvm_vcpu *vcpu,
2427 unsigned index, u64 *data))
2428{
f656ce01 2429 int i, idx;
313a3dc7 2430
f656ce01 2431 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2432 for (i = 0; i < msrs->nmsrs; ++i)
2433 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2434 break;
f656ce01 2435 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2436
313a3dc7
CO		 2437 return i;
2438}
2439
2440/*
2441 * Read or write a bunch of msrs. Parameters are user addresses.
2442 *
2443 * @return number of msrs set successfully.
2444 */
2445static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2446 int (*do_msr)(struct kvm_vcpu *vcpu,
2447 unsigned index, u64 *data),
2448 int writeback)
2449{
2450 struct kvm_msrs msrs;
2451 struct kvm_msr_entry *entries;
2452 int r, n;
2453 unsigned size;
2454
2455 r = -EFAULT;
2456 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2457 goto out;
2458
2459 r = -E2BIG;
2460 if (msrs.nmsrs >= MAX_IO_MSRS)
2461 goto out;
2462
313a3dc7 2463 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2464 entries = memdup_user(user_msrs->entries, size);
2465 if (IS_ERR(entries)) {
2466 r = PTR_ERR(entries);
313a3dc7 2467 goto out;
ff5c2c03 2468 }
313a3dc7
CO		 2469
2470 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2471 if (r < 0)
2472 goto out_free;
2473
2474 r = -EFAULT;
2475 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2476 goto out_free;
2477
2478 r = n;
2479
2480out_free:
7a73c028 2481 kfree(entries);
313a3dc7
CO		 2482out:
2483 return r;
2484}
2485
018d00d2
ZX		 2486int kvm_dev_ioctl_check_extension(long ext)
2487{
2488 int r;
2489
2490 switch (ext) {
2491 case KVM_CAP_IRQCHIP:
2492 case KVM_CAP_HLT:
2493 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2494 case KVM_CAP_SET_TSS_ADDR:
07716717 2495 case KVM_CAP_EXT_CPUID:
c8076604 2496 case KVM_CAP_CLOCKSOURCE:
7837699f 2497 case KVM_CAP_PIT:
a28e4f5a 2498 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2499 case KVM_CAP_MP_STATE:
ed848624 2500 case KVM_CAP_SYNC_MMU:
a355c85c 2501 case KVM_CAP_USER_NMI:
52d939a0 2502 case KVM_CAP_REINJECT_CONTROL:
4925663a 2503 case KVM_CAP_IRQ_INJECT_STATUS:
721eecbf 2504 case KVM_CAP_IRQFD:
d34e6b17 2505 case KVM_CAP_IOEVENTFD:
c5ff41ce 2506 case KVM_CAP_PIT2:
e9f42757 2507 case KVM_CAP_PIT_STATE2:
b927a3ce 2508 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2509 case KVM_CAP_XEN_HVM:
afbcf7ab 2510 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2511 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2512 case KVM_CAP_HYPERV:
10388a07 2513 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2514 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2515 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2516 case KVM_CAP_DEBUGREGS:
d2be1651 2517 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2518 case KVM_CAP_XSAVE:
344d9588 2519 case KVM_CAP_ASYNC_PF:
92a1f12d 2520 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2521 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2522 case KVM_CAP_READONLY_MEM:
2a5bab10
AW		 2523#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2524 case KVM_CAP_ASSIGN_DEV_IRQ:
2525 case KVM_CAP_PCI_2_3:
2526#endif
018d00d2
ZX		 2527 r = 1;
2528 break;
542472b5
LV		 2529 case KVM_CAP_COALESCED_MMIO:
2530 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2531 break;
774ead3a
AK		 2532 case KVM_CAP_VAPIC:
2533 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2534 break;
f725230a 2535 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2536 r = KVM_SOFT_MAX_VCPUS;
2537 break;
2538 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2539 r = KVM_MAX_VCPUS;
2540 break;
a988b910 2541 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2542 r = KVM_USER_MEM_SLOTS;
a988b910 2543 break;
a68a6a72
MT		 2544 case KVM_CAP_PV_MMU: /* obsolete */
2545 r = 0;
2f333bcb 2546 break;
4cee4b72 2547#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2548 case KVM_CAP_IOMMU:
a1b60c1c 2549 r = iommu_present(&pci_bus_type);
62c476c7 2550 break;
4cee4b72 2551#endif
890ca9ae
HY		 2552 case KVM_CAP_MCE:
2553 r = KVM_MAX_MCE_BANKS;
2554 break;
2d5b5a66
SY		 2555 case KVM_CAP_XCRS:
2556 r = cpu_has_xsave;
2557 break;
92a1f12d
JR		 2558 case KVM_CAP_TSC_CONTROL:
2559 r = kvm_has_tsc_control;
2560 break;
4d25a066
JK		 2561 case KVM_CAP_TSC_DEADLINE_TIMER:
2562 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2563 break;
018d00d2
ZX		 2564 default:
2565 r = 0;
2566 break;
2567 }
2568 return r;
2569
2570}
2571
043405e1
CO		 2572long kvm_arch_dev_ioctl(struct file *filp,
2573 unsigned int ioctl, unsigned long arg)
2574{
2575 void __user *argp = (void __user *)arg;
2576 long r;
2577
2578 switch (ioctl) {
2579 case KVM_GET_MSR_INDEX_LIST: {
2580 struct kvm_msr_list __user *user_msr_list = argp;
2581 struct kvm_msr_list msr_list;
2582 unsigned n;
2583
2584 r = -EFAULT;
2585 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2586 goto out;
2587 n = msr_list.nmsrs;
2588 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2589 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2590 goto out;
2591 r = -E2BIG;
e125e7b6 2592 if (n < msr_list.nmsrs)
043405e1
CO		 2593 goto out;
2594 r = -EFAULT;
2595 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2596 num_msrs_to_save * sizeof(u32)))
2597 goto out;
e125e7b6 2598 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2599 &emulated_msrs,
2600 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2601 goto out;
2602 r = 0;
2603 break;
2604 }
674eea0f
AK		 2605 case KVM_GET_SUPPORTED_CPUID: {
2606 struct kvm_cpuid2 __user *cpuid_arg = argp;
2607 struct kvm_cpuid2 cpuid;
2608
2609 r = -EFAULT;
2610 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2611 goto out;
2612 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 2613 cpuid_arg->entries);
674eea0f
AK		 2614 if (r)
2615 goto out;
2616
2617 r = -EFAULT;
2618 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2619 goto out;
2620 r = 0;
2621 break;
2622 }
890ca9ae
HY		 2623 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2624 u64 mce_cap;
2625
2626 mce_cap = KVM_MCE_CAP_SUPPORTED;
2627 r = -EFAULT;
2628 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2629 goto out;
2630 r = 0;
2631 break;
2632 }
043405e1
CO		 2633 default:
2634 r = -EINVAL;
2635 }
2636out:
2637 return r;
2638}
2639
f5f48ee1
SY		 2640static void wbinvd_ipi(void *garbage)
2641{
2642 wbinvd();
2643}
2644
2645static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2646{
2647 return vcpu->kvm->arch.iommu_domain &&
2648 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2649}
2650
313a3dc7
CO		 2651void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2652{
f5f48ee1
SY		 2653 /* Address WBINVD may be executed by guest */
2654 if (need_emulate_wbinvd(vcpu)) {
2655 if (kvm_x86_ops->has_wbinvd_exit())
2656 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2657 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2658 smp_call_function_single(vcpu->cpu,
2659 wbinvd_ipi, NULL, 1);
2660 }
2661
313a3dc7 2662 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2663
0dd6a6ed
ZA		 2664 /* Apply any externally detected TSC adjustments (due to suspend) */
2665 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2666 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2667 vcpu->arch.tsc_offset_adjustment = 0;
2668 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2669 }
8f6055cb 2670
48434c20 2671 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5
ZA		 2672 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2673 native_read_tsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2674 if (tsc_delta < 0)
2675 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2676 if (check_tsc_unstable()) {
b183aa58
ZA		 2677 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2678 vcpu->arch.last_guest_tsc);
2679 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2680 vcpu->arch.tsc_catchup = 1;
c285545f 2681 }
d98d07ca
MT		 2682 /*
2683 * On a host with synchronized TSC, there is no need to update
2684 * kvmclock on vcpu->cpu migration
2685 */
2686 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
2687 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2688 if (vcpu->cpu != cpu)
2689 kvm_migrate_timers(vcpu);
e48672fa 2690 vcpu->cpu = cpu;
6b7d7e76 2691 }
c9aaa895
GC		 2692
2693 accumulate_steal_time(vcpu);
2694 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2695}
2696
2697void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2698{
02daab21 2699 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2700 kvm_put_guest_fpu(vcpu);
6f526ec5 2701 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2702}
2703
313a3dc7
CO		 2704static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2705 struct kvm_lapic_state *s)
2706{
5a71785d 2707 kvm_x86_ops->sync_pir_to_irr(vcpu);
ad312c7c 2708 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2709
2710 return 0;
2711}
2712
2713static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2714 struct kvm_lapic_state *s)
2715{
64eb0620 2716 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2717 update_cr8_intercept(vcpu);
313a3dc7
CO		 2718
2719 return 0;
2720}
2721
f77bc6a4
ZX		 2722static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2723 struct kvm_interrupt *irq)
2724{
02cdb50f 2725 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4
ZX		 2726 return -EINVAL;
2727 if (irqchip_in_kernel(vcpu->kvm))
2728 return -ENXIO;
f77bc6a4 2729
66fd3f7f 2730 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2731 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2732
f77bc6a4
ZX		 2733 return 0;
2734}
2735
c4abb7c9
JK		 2736static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2737{
c4abb7c9 2738 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2739
2740 return 0;
2741}
2742
b209749f
AK		 2743static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2744 struct kvm_tpr_access_ctl *tac)
2745{
2746 if (tac->flags)
2747 return -EINVAL;
2748 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2749 return 0;
2750}
2751
890ca9ae
HY		 2752static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2753 u64 mcg_cap)
2754{
2755 int r;
2756 unsigned bank_num = mcg_cap & 0xff, bank;
2757
2758 r = -EINVAL;
a9e38c3e 2759 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2760 goto out;
2761 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2762 goto out;
2763 r = 0;
2764 vcpu->arch.mcg_cap = mcg_cap;
2765 /* Init IA32_MCG_CTL to all 1s */
2766 if (mcg_cap & MCG_CTL_P)
2767 vcpu->arch.mcg_ctl = ~(u64)0;
2768 /* Init IA32_MCi_CTL to all 1s */
2769 for (bank = 0; bank < bank_num; bank++)
2770 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2771out:
2772 return r;
2773}
2774
2775static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2776 struct kvm_x86_mce *mce)
2777{
2778 u64 mcg_cap = vcpu->arch.mcg_cap;
2779 unsigned bank_num = mcg_cap & 0xff;
2780 u64 *banks = vcpu->arch.mce_banks;
2781
2782 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2783 return -EINVAL;
2784 /*
2785 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2786 * reporting is disabled
2787 */
2788 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2789 vcpu->arch.mcg_ctl != ~(u64)0)
2790 return 0;
2791 banks += 4 * mce->bank;
2792 /*
2793 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2794 * reporting is disabled for the bank
2795 */
2796 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2797 return 0;
2798 if (mce->status & MCI_STATUS_UC) {
2799 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2800 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2801 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2802 return 0;
2803 }
2804 if (banks[1] & MCI_STATUS_VAL)
2805 mce->status |= MCI_STATUS_OVER;
2806 banks[2] = mce->addr;
2807 banks[3] = mce->misc;
2808 vcpu->arch.mcg_status = mce->mcg_status;
2809 banks[1] = mce->status;
2810 kvm_queue_exception(vcpu, MC_VECTOR);
2811 } else if (!(banks[1] & MCI_STATUS_VAL)
2812 || !(banks[1] & MCI_STATUS_UC)) {
2813 if (banks[1] & MCI_STATUS_VAL)
2814 mce->status |= MCI_STATUS_OVER;
2815 banks[2] = mce->addr;
2816 banks[3] = mce->misc;
2817 banks[1] = mce->status;
2818 } else
2819 banks[1] |= MCI_STATUS_OVER;
2820 return 0;
2821}
2822
3cfc3092
JK		 2823static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2824 struct kvm_vcpu_events *events)
2825{
7460fb4a 2826 process_nmi(vcpu);
03b82a30
JK		 2827 events->exception.injected =
2828 vcpu->arch.exception.pending &&
2829 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2830 events->exception.nr = vcpu->arch.exception.nr;
2831 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2832 events->exception.pad = 0;
3cfc3092
JK		 2833 events->exception.error_code = vcpu->arch.exception.error_code;
2834
03b82a30
JK		 2835 events->interrupt.injected =
2836 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2837 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2838 events->interrupt.soft = 0;
48005f64
JK		 2839 events->interrupt.shadow =
2840 kvm_x86_ops->get_interrupt_shadow(vcpu,
2841 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2842
2843 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2844 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2845 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2846 events->nmi.pad = 0;
3cfc3092 2847
66450a21 2848 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 2849
dab4b911 2850 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 2851 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 2852 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2853}
2854
2855static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2856 struct kvm_vcpu_events *events)
2857{
dab4b911 2858 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2859 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2860 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2861 return -EINVAL;
2862
7460fb4a 2863 process_nmi(vcpu);
3cfc3092
JK		 2864 vcpu->arch.exception.pending = events->exception.injected;
2865 vcpu->arch.exception.nr = events->exception.nr;
2866 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2867 vcpu->arch.exception.error_code = events->exception.error_code;
2868
2869 vcpu->arch.interrupt.pending = events->interrupt.injected;
2870 vcpu->arch.interrupt.nr = events->interrupt.nr;
2871 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2872 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2873 kvm_x86_ops->set_interrupt_shadow(vcpu,
2874 events->interrupt.shadow);
3cfc3092
JK		 2875
2876 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2877 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2878 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2879 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2880
66450a21
JK		 2881 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
2882 kvm_vcpu_has_lapic(vcpu))
2883 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 2884
3842d135
AK		 2885 kvm_make_request(KVM_REQ_EVENT, vcpu);
2886
3cfc3092
JK		 2887 return 0;
2888}
2889
a1efbe77
JK		 2890static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2891 struct kvm_debugregs *dbgregs)
2892{
a1efbe77
JK		 2893 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2894 dbgregs->dr6 = vcpu->arch.dr6;
2895 dbgregs->dr7 = vcpu->arch.dr7;
2896 dbgregs->flags = 0;
97e69aa6 2897 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 2898}
2899
2900static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2901 struct kvm_debugregs *dbgregs)
2902{
2903 if (dbgregs->flags)
2904 return -EINVAL;
2905
a1efbe77
JK		 2906 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2907 vcpu->arch.dr6 = dbgregs->dr6;
2908 vcpu->arch.dr7 = dbgregs->dr7;
2909
a1efbe77
JK		 2910 return 0;
2911}
2912
2d5b5a66
SY		 2913static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2914 struct kvm_xsave *guest_xsave)
2915{
2916 if (cpu_has_xsave)
2917 memcpy(guest_xsave->region,
2918 &vcpu->arch.guest_fpu.state->xsave,
f45755b8 2919 xstate_size);
2d5b5a66
SY		 2920 else {
2921 memcpy(guest_xsave->region,
2922 &vcpu->arch.guest_fpu.state->fxsave,
2923 sizeof(struct i387_fxsave_struct));
2924 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2925 XSTATE_FPSSE;
2926 }
2927}
2928
2929static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2930 struct kvm_xsave *guest_xsave)
2931{
2932 u64 xstate_bv =
2933 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2934
2935 if (cpu_has_xsave)
2936 memcpy(&vcpu->arch.guest_fpu.state->xsave,
f45755b8 2937 guest_xsave->region, xstate_size);
2d5b5a66
SY		 2938 else {
2939 if (xstate_bv & ~XSTATE_FPSSE)
2940 return -EINVAL;
2941 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2942 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2943 }
2944 return 0;
2945}
2946
2947static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2948 struct kvm_xcrs *guest_xcrs)
2949{
2950 if (!cpu_has_xsave) {
2951 guest_xcrs->nr_xcrs = 0;
2952 return;
2953 }
2954
2955 guest_xcrs->nr_xcrs = 1;
2956 guest_xcrs->flags = 0;
2957 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2958 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2959}
2960
2961static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2962 struct kvm_xcrs *guest_xcrs)
2963{
2964 int i, r = 0;
2965
2966 if (!cpu_has_xsave)
2967 return -EINVAL;
2968
2969 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2970 return -EINVAL;
2971
2972 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2973 /* Only support XCR0 currently */
2974 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2975 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2976 guest_xcrs->xcrs[0].value);
2977 break;
2978 }
2979 if (r)
2980 r = -EINVAL;
2981 return r;
2982}
2983
1c0b28c2
EM		 2984/*
2985 * kvm_set_guest_paused() indicates to the guest kernel that it has been
2986 * stopped by the hypervisor. This function will be called from the host only.
2987 * EINVAL is returned when the host attempts to set the flag for a guest that
2988 * does not support pv clocks.
2989 */
2990static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
2991{
0b79459b 2992 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 2993 return -EINVAL;
51d59c6b 2994 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 2995 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2996 return 0;
2997}
2998
313a3dc7
CO		 2999long kvm_arch_vcpu_ioctl(struct file *filp,
3000 unsigned int ioctl, unsigned long arg)
3001{
3002 struct kvm_vcpu *vcpu = filp->private_data;
3003 void __user *argp = (void __user *)arg;
3004 int r;
d1ac91d8
AK		 3005 union {
3006 struct kvm_lapic_state *lapic;
3007 struct kvm_xsave *xsave;
3008 struct kvm_xcrs *xcrs;
3009 void *buffer;
3010 } u;
3011
3012 u.buffer = NULL;
313a3dc7
CO		 3013 switch (ioctl) {
3014 case KVM_GET_LAPIC: {
2204ae3c
MT		 3015 r = -EINVAL;
3016 if (!vcpu->arch.apic)
3017 goto out;
d1ac91d8 3018 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3019
b772ff36 3020 r = -ENOMEM;
d1ac91d8 3021 if (!u.lapic)
b772ff36 3022 goto out;
d1ac91d8 3023 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3024 if (r)
3025 goto out;
3026 r = -EFAULT;
d1ac91d8 3027 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3028 goto out;
3029 r = 0;
3030 break;
3031 }
3032 case KVM_SET_LAPIC: {
2204ae3c
MT		 3033 r = -EINVAL;
3034 if (!vcpu->arch.apic)
3035 goto out;
ff5c2c03 3036 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3037 if (IS_ERR(u.lapic))
3038 return PTR_ERR(u.lapic);
ff5c2c03 3039
d1ac91d8 3040 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3041 break;
3042 }
f77bc6a4
ZX		 3043 case KVM_INTERRUPT: {
3044 struct kvm_interrupt irq;
3045
3046 r = -EFAULT;
3047 if (copy_from_user(&irq, argp, sizeof irq))
3048 goto out;
3049 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3050 break;
3051 }
c4abb7c9
JK		 3052 case KVM_NMI: {
3053 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3054 break;
3055 }
313a3dc7
CO		 3056 case KVM_SET_CPUID: {
3057 struct kvm_cpuid __user *cpuid_arg = argp;
3058 struct kvm_cpuid cpuid;
3059
3060 r = -EFAULT;
3061 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3062 goto out;
3063 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3064 break;
3065 }
07716717
DK		 3066 case KVM_SET_CPUID2: {
3067 struct kvm_cpuid2 __user *cpuid_arg = argp;
3068 struct kvm_cpuid2 cpuid;
3069
3070 r = -EFAULT;
3071 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3072 goto out;
3073 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3074 cpuid_arg->entries);
07716717
DK		 3075 break;
3076 }
3077 case KVM_GET_CPUID2: {
3078 struct kvm_cpuid2 __user *cpuid_arg = argp;
3079 struct kvm_cpuid2 cpuid;
3080
3081 r = -EFAULT;
3082 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3083 goto out;
3084 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3085 cpuid_arg->entries);
07716717
DK		 3086 if (r)
3087 goto out;
3088 r = -EFAULT;
3089 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3090 goto out;
3091 r = 0;
3092 break;
3093 }
313a3dc7
CO		 3094 case KVM_GET_MSRS:
3095 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3096 break;
3097 case KVM_SET_MSRS:
3098 r = msr_io(vcpu, argp, do_set_msr, 0);
3099 break;
b209749f
AK		 3100 case KVM_TPR_ACCESS_REPORTING: {
3101 struct kvm_tpr_access_ctl tac;
3102
3103 r = -EFAULT;
3104 if (copy_from_user(&tac, argp, sizeof tac))
3105 goto out;
3106 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3107 if (r)
3108 goto out;
3109 r = -EFAULT;
3110 if (copy_to_user(argp, &tac, sizeof tac))
3111 goto out;
3112 r = 0;
3113 break;
3114 };
b93463aa
AK		 3115 case KVM_SET_VAPIC_ADDR: {
3116 struct kvm_vapic_addr va;
3117
3118 r = -EINVAL;
3119 if (!irqchip_in_kernel(vcpu->kvm))
3120 goto out;
3121 r = -EFAULT;
3122 if (copy_from_user(&va, argp, sizeof va))
3123 goto out;
3124 r = 0;
3125 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3126 break;
3127 }
890ca9ae
HY		 3128 case KVM_X86_SETUP_MCE: {
3129 u64 mcg_cap;
3130
3131 r = -EFAULT;
3132 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3133 goto out;
3134 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3135 break;
3136 }
3137 case KVM_X86_SET_MCE: {
3138 struct kvm_x86_mce mce;
3139
3140 r = -EFAULT;
3141 if (copy_from_user(&mce, argp, sizeof mce))
3142 goto out;
3143 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3144 break;
3145 }
3cfc3092
JK		 3146 case KVM_GET_VCPU_EVENTS: {
3147 struct kvm_vcpu_events events;
3148
3149 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3150
3151 r = -EFAULT;
3152 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3153 break;
3154 r = 0;
3155 break;
3156 }
3157 case KVM_SET_VCPU_EVENTS: {
3158 struct kvm_vcpu_events events;
3159
3160 r = -EFAULT;
3161 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3162 break;
3163
3164 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3165 break;
3166 }
a1efbe77
JK		 3167 case KVM_GET_DEBUGREGS: {
3168 struct kvm_debugregs dbgregs;
3169
3170 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3171
3172 r = -EFAULT;
3173 if (copy_to_user(argp, &dbgregs,
3174 sizeof(struct kvm_debugregs)))
3175 break;
3176 r = 0;
3177 break;
3178 }
3179 case KVM_SET_DEBUGREGS: {
3180 struct kvm_debugregs dbgregs;
3181
3182 r = -EFAULT;
3183 if (copy_from_user(&dbgregs, argp,
3184 sizeof(struct kvm_debugregs)))
3185 break;
3186
3187 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3188 break;
3189 }
2d5b5a66 3190 case KVM_GET_XSAVE: {
d1ac91d8 3191 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3192 r = -ENOMEM;
d1ac91d8 3193 if (!u.xsave)
2d5b5a66
SY		 3194 break;
3195
d1ac91d8 3196 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3197
3198 r = -EFAULT;
d1ac91d8 3199 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3200 break;
3201 r = 0;
3202 break;
3203 }
3204 case KVM_SET_XSAVE: {
ff5c2c03 3205 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3206 if (IS_ERR(u.xsave))
3207 return PTR_ERR(u.xsave);
2d5b5a66 3208
d1ac91d8 3209 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3210 break;
3211 }
3212 case KVM_GET_XCRS: {
d1ac91d8 3213 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3214 r = -ENOMEM;
d1ac91d8 3215 if (!u.xcrs)
2d5b5a66
SY		 3216 break;
3217
d1ac91d8 3218 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3219
3220 r = -EFAULT;
d1ac91d8 3221 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3222 sizeof(struct kvm_xcrs)))
3223 break;
3224 r = 0;
3225 break;
3226 }
3227 case KVM_SET_XCRS: {
ff5c2c03 3228 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3229 if (IS_ERR(u.xcrs))
3230 return PTR_ERR(u.xcrs);
2d5b5a66 3231
d1ac91d8 3232 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3233 break;
3234 }
92a1f12d
JR		 3235 case KVM_SET_TSC_KHZ: {
3236 u32 user_tsc_khz;
3237
3238 r = -EINVAL;
92a1f12d
JR		 3239 user_tsc_khz = (u32)arg;
3240
3241 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3242 goto out;
3243
cc578287
ZA		 3244 if (user_tsc_khz == 0)
3245 user_tsc_khz = tsc_khz;
3246
3247 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 3248
3249 r = 0;
3250 goto out;
3251 }
3252 case KVM_GET_TSC_KHZ: {
cc578287 3253 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3254 goto out;
3255 }
1c0b28c2
EM		 3256 case KVM_KVMCLOCK_CTRL: {
3257 r = kvm_set_guest_paused(vcpu);
3258 goto out;
3259 }
313a3dc7
CO		 3260 default:
3261 r = -EINVAL;
3262 }
3263out:
d1ac91d8 3264 kfree(u.buffer);
313a3dc7
CO		 3265 return r;
3266}
3267
5b1c1493
CO		 3268int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3269{
3270 return VM_FAULT_SIGBUS;
3271}
3272
1fe779f8
CO		 3273static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3274{
3275 int ret;
3276
3277 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3278 return -EINVAL;
1fe779f8
CO		 3279 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3280 return ret;
3281}
3282
b927a3ce
SY		 3283static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3284 u64 ident_addr)
3285{
3286 kvm->arch.ept_identity_map_addr = ident_addr;
3287 return 0;
3288}
3289
1fe779f8
CO		 3290static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3291 u32 kvm_nr_mmu_pages)
3292{
3293 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3294 return -EINVAL;
3295
79fac95e 3296 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3297
3298 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3299 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3300
79fac95e 3301 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3302 return 0;
3303}
3304
3305static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3306{
39de71ec 3307 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3308}
3309
1fe779f8
CO		 3310static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3311{
3312 int r;
3313
3314 r = 0;
3315 switch (chip->chip_id) {
3316 case KVM_IRQCHIP_PIC_MASTER:
3317 memcpy(&chip->chip.pic,
3318 &pic_irqchip(kvm)->pics[0],
3319 sizeof(struct kvm_pic_state));
3320 break;
3321 case KVM_IRQCHIP_PIC_SLAVE:
3322 memcpy(&chip->chip.pic,
3323 &pic_irqchip(kvm)->pics[1],
3324 sizeof(struct kvm_pic_state));
3325 break;
3326 case KVM_IRQCHIP_IOAPIC:
eba0226b 3327 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3328 break;
3329 default:
3330 r = -EINVAL;
3331 break;
3332 }
3333 return r;
3334}
3335
3336static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3337{
3338 int r;
3339
3340 r = 0;
3341 switch (chip->chip_id) {
3342 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3343 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3344 memcpy(&pic_irqchip(kvm)->pics[0],
3345 &chip->chip.pic,
3346 sizeof(struct kvm_pic_state));
f4f51050 3347 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3348 break;
3349 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3350 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3351 memcpy(&pic_irqchip(kvm)->pics[1],
3352 &chip->chip.pic,
3353 sizeof(struct kvm_pic_state));
f4f51050 3354 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3355 break;
3356 case KVM_IRQCHIP_IOAPIC:
eba0226b 3357 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3358 break;
3359 default:
3360 r = -EINVAL;
3361 break;
3362 }
3363 kvm_pic_update_irq(pic_irqchip(kvm));
3364 return r;
3365}
3366
e0f63cb9
SY		 3367static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3368{
3369 int r = 0;
3370
894a9c55 3371 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3372 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3373 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3374 return r;
3375}
3376
3377static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3378{
3379 int r = 0;
3380
894a9c55 3381 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3382 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3383 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3384 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3385 return r;
3386}
3387
3388static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3389{
3390 int r = 0;
3391
3392 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3393 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3394 sizeof(ps->channels));
3395 ps->flags = kvm->arch.vpit->pit_state.flags;
3396 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3397 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3398 return r;
3399}
3400
3401static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3402{
3403 int r = 0, start = 0;
3404 u32 prev_legacy, cur_legacy;
3405 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3406 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3407 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3408 if (!prev_legacy && cur_legacy)
3409 start = 1;
3410 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3411 sizeof(kvm->arch.vpit->pit_state.channels));
3412 kvm->arch.vpit->pit_state.flags = ps->flags;
3413 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3414 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3415 return r;
3416}
3417
52d939a0
MT		 3418static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3419 struct kvm_reinject_control *control)
3420{
3421 if (!kvm->arch.vpit)
3422 return -ENXIO;
894a9c55 3423 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3424 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3425 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3426 return 0;
3427}
3428
95d4c16c 3429/**
60c34612
TY		 3430 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3431 * @kvm: kvm instance
3432 * @log: slot id and address to which we copy the log
95d4c16c 3433 *
60c34612
TY		 3434 * We need to keep it in mind that VCPU threads can write to the bitmap
3435 * concurrently. So, to avoid losing data, we keep the following order for
3436 * each bit:
95d4c16c 3437 *
60c34612
TY		 3438 * 1. Take a snapshot of the bit and clear it if needed.
3439 * 2. Write protect the corresponding page.
3440 * 3. Flush TLB's if needed.
3441 * 4. Copy the snapshot to the userspace.
95d4c16c 3442 *
60c34612
TY		 3443 * Between 2 and 3, the guest may write to the page using the remaining TLB
3444 * entry. This is not a problem because the page will be reported dirty at
3445 * step 4 using the snapshot taken before and step 3 ensures that successive
3446 * writes will be logged for the next call.
5bb064dc 3447 */
60c34612 3448int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3449{
7850ac54 3450 int r;
5bb064dc 3451 struct kvm_memory_slot *memslot;
60c34612
TY		 3452 unsigned long n, i;
3453 unsigned long *dirty_bitmap;
3454 unsigned long *dirty_bitmap_buffer;
3455 bool is_dirty = false;
5bb064dc 3456
79fac95e 3457 mutex_lock(&kvm->slots_lock);
5bb064dc 3458
b050b015 3459 r = -EINVAL;
bbacc0c1 3460 if (log->slot >= KVM_USER_MEM_SLOTS)
b050b015
MT		 3461 goto out;
3462
28a37544 3463 memslot = id_to_memslot(kvm->memslots, log->slot);
60c34612
TY		 3464
3465 dirty_bitmap = memslot->dirty_bitmap;
b050b015 3466 r = -ENOENT;
60c34612 3467 if (!dirty_bitmap)
b050b015
MT		 3468 goto out;
3469
87bf6e7d 3470 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3471
60c34612
TY		 3472 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3473 memset(dirty_bitmap_buffer, 0, n);
b050b015 3474
60c34612 3475 spin_lock(&kvm->mmu_lock);
b050b015 3476
60c34612
TY		 3477 for (i = 0; i < n / sizeof(long); i++) {
3478 unsigned long mask;
3479 gfn_t offset;
cdfca7b3 3480
60c34612
TY		 3481 if (!dirty_bitmap[i])
3482 continue;
b050b015 3483
60c34612 3484 is_dirty = true;
914ebccd 3485
60c34612
TY		 3486 mask = xchg(&dirty_bitmap[i], 0);
3487 dirty_bitmap_buffer[i] = mask;
edde99ce 3488
60c34612
TY		 3489 offset = i * BITS_PER_LONG;
3490 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
5bb064dc 3491 }
60c34612
TY		 3492 if (is_dirty)
3493 kvm_flush_remote_tlbs(kvm);
3494
3495 spin_unlock(&kvm->mmu_lock);
3496
3497 r = -EFAULT;
3498 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3499 goto out;
b050b015 3500
5bb064dc
ZX		 3501 r = 0;
3502out:
79fac95e 3503 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3504 return r;
3505}
3506
aa2fbe6d
YZ		 3507int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3508 bool line_status)
23d43cf9
CD		 3509{
3510 if (!irqchip_in_kernel(kvm))
3511 return -ENXIO;
3512
3513 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3514 irq_event->irq, irq_event->level,
3515 line_status);
23d43cf9
CD		 3516 return 0;
3517}
3518
1fe779f8
CO		 3519long kvm_arch_vm_ioctl(struct file *filp,
3520 unsigned int ioctl, unsigned long arg)
3521{
3522 struct kvm *kvm = filp->private_data;
3523 void __user *argp = (void __user *)arg;
367e1319 3524 int r = -ENOTTY;
f0d66275
DH		 3525 /*
3526 * This union makes it completely explicit to gcc-3.x
3527 * that these two variables' stack usage should be
3528 * combined, not added together.
3529 */
3530 union {
3531 struct kvm_pit_state ps;
e9f42757 3532 struct kvm_pit_state2 ps2;
c5ff41ce 3533 struct kvm_pit_config pit_config;
f0d66275 3534 } u;
1fe779f8
CO		 3535
3536 switch (ioctl) {
3537 case KVM_SET_TSS_ADDR:
3538 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3539 break;
b927a3ce
SY		 3540 case KVM_SET_IDENTITY_MAP_ADDR: {
3541 u64 ident_addr;
3542
3543 r = -EFAULT;
3544 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3545 goto out;
3546 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3547 break;
3548 }
1fe779f8
CO		 3549 case KVM_SET_NR_MMU_PAGES:
3550 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3551 break;
3552 case KVM_GET_NR_MMU_PAGES:
3553 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3554 break;
3ddea128
MT		 3555 case KVM_CREATE_IRQCHIP: {
3556 struct kvm_pic *vpic;
3557
3558 mutex_lock(&kvm->lock);
3559 r = -EEXIST;
3560 if (kvm->arch.vpic)
3561 goto create_irqchip_unlock;
3e515705
AK		 3562 r = -EINVAL;
3563 if (atomic_read(&kvm->online_vcpus))
3564 goto create_irqchip_unlock;
1fe779f8 3565 r = -ENOMEM;
3ddea128
MT		 3566 vpic = kvm_create_pic(kvm);
3567 if (vpic) {
1fe779f8
CO		 3568 r = kvm_ioapic_init(kvm);
3569 if (r) {
175504cd 3570 mutex_lock(&kvm->slots_lock);
72bb2fcd 3571 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3572 &vpic->dev_master);
3573 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3574 &vpic->dev_slave);
3575 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3576 &vpic->dev_eclr);
175504cd 3577 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3578 kfree(vpic);
3579 goto create_irqchip_unlock;
1fe779f8
CO		 3580 }
3581 } else
3ddea128
MT		 3582 goto create_irqchip_unlock;
3583 smp_wmb();
3584 kvm->arch.vpic = vpic;
3585 smp_wmb();
399ec807
AK		 3586 r = kvm_setup_default_irq_routing(kvm);
3587 if (r) {
175504cd 3588 mutex_lock(&kvm->slots_lock);
3ddea128 3589 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3590 kvm_ioapic_destroy(kvm);
3591 kvm_destroy_pic(kvm);
3ddea128 3592 mutex_unlock(&kvm->irq_lock);
175504cd 3593 mutex_unlock(&kvm->slots_lock);
399ec807 3594 }
3ddea128
MT		 3595 create_irqchip_unlock:
3596 mutex_unlock(&kvm->lock);
1fe779f8 3597 break;
3ddea128 3598 }
7837699f 3599 case KVM_CREATE_PIT:
c5ff41ce
JK		 3600 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3601 goto create_pit;
3602 case KVM_CREATE_PIT2:
3603 r = -EFAULT;
3604 if (copy_from_user(&u.pit_config, argp,
3605 sizeof(struct kvm_pit_config)))
3606 goto out;
3607 create_pit:
79fac95e 3608 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3609 r = -EEXIST;
3610 if (kvm->arch.vpit)
3611 goto create_pit_unlock;
7837699f 3612 r = -ENOMEM;
c5ff41ce 3613 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3614 if (kvm->arch.vpit)
3615 r = 0;
269e05e4 3616 create_pit_unlock:
79fac95e 3617 mutex_unlock(&kvm->slots_lock);
7837699f 3618 break;
1fe779f8
CO		 3619 case KVM_GET_IRQCHIP: {
3620 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3621 struct kvm_irqchip *chip;
1fe779f8 3622
ff5c2c03
SL		 3623 chip = memdup_user(argp, sizeof(*chip));
3624 if (IS_ERR(chip)) {
3625 r = PTR_ERR(chip);
1fe779f8 3626 goto out;
ff5c2c03
SL		 3627 }
3628
1fe779f8
CO		 3629 r = -ENXIO;
3630 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3631 goto get_irqchip_out;
3632 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3633 if (r)
f0d66275 3634 goto get_irqchip_out;
1fe779f8 3635 r = -EFAULT;
f0d66275
DH		 3636 if (copy_to_user(argp, chip, sizeof *chip))
3637 goto get_irqchip_out;
1fe779f8 3638 r = 0;
f0d66275
DH		 3639 get_irqchip_out:
3640 kfree(chip);
1fe779f8
CO		 3641 break;
3642 }
3643 case KVM_SET_IRQCHIP: {
3644 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3645 struct kvm_irqchip *chip;
1fe779f8 3646
ff5c2c03
SL		 3647 chip = memdup_user(argp, sizeof(*chip));
3648 if (IS_ERR(chip)) {
3649 r = PTR_ERR(chip);
1fe779f8 3650 goto out;
ff5c2c03
SL		 3651 }
3652
1fe779f8
CO		 3653 r = -ENXIO;
3654 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3655 goto set_irqchip_out;
3656 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3657 if (r)
f0d66275 3658 goto set_irqchip_out;
1fe779f8 3659 r = 0;
f0d66275
DH		 3660 set_irqchip_out:
3661 kfree(chip);
1fe779f8
CO		 3662 break;
3663 }
e0f63cb9 3664 case KVM_GET_PIT: {
e0f63cb9 3665 r = -EFAULT;
f0d66275 3666 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3667 goto out;
3668 r = -ENXIO;
3669 if (!kvm->arch.vpit)
3670 goto out;
f0d66275 3671 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3672 if (r)
3673 goto out;
3674 r = -EFAULT;
f0d66275 3675 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3676 goto out;
3677 r = 0;
3678 break;
3679 }
3680 case KVM_SET_PIT: {
e0f63cb9 3681 r = -EFAULT;
f0d66275 3682 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3683 goto out;
3684 r = -ENXIO;
3685 if (!kvm->arch.vpit)
3686 goto out;
f0d66275 3687 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3688 break;
3689 }
e9f42757
BK		 3690 case KVM_GET_PIT2: {
3691 r = -ENXIO;
3692 if (!kvm->arch.vpit)
3693 goto out;
3694 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3695 if (r)
3696 goto out;
3697 r = -EFAULT;
3698 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3699 goto out;
3700 r = 0;
3701 break;
3702 }
3703 case KVM_SET_PIT2: {
3704 r = -EFAULT;
3705 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3706 goto out;
3707 r = -ENXIO;
3708 if (!kvm->arch.vpit)
3709 goto out;
3710 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3711 break;
3712 }
52d939a0
MT		 3713 case KVM_REINJECT_CONTROL: {
3714 struct kvm_reinject_control control;
3715 r = -EFAULT;
3716 if (copy_from_user(&control, argp, sizeof(control)))
3717 goto out;
3718 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 3719 break;
3720 }
ffde22ac
ES		 3721 case KVM_XEN_HVM_CONFIG: {
3722 r = -EFAULT;
3723 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3724 sizeof(struct kvm_xen_hvm_config)))
3725 goto out;
3726 r = -EINVAL;
3727 if (kvm->arch.xen_hvm_config.flags)
3728 goto out;
3729 r = 0;
3730 break;
3731 }
afbcf7ab 3732 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3733 struct kvm_clock_data user_ns;
3734 u64 now_ns;
3735 s64 delta;
3736
3737 r = -EFAULT;
3738 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3739 goto out;
3740
3741 r = -EINVAL;
3742 if (user_ns.flags)
3743 goto out;
3744
3745 r = 0;
395c6b0a 3746 local_irq_disable();
759379dd 3747 now_ns = get_kernel_ns();
afbcf7ab 3748 delta = user_ns.clock - now_ns;
395c6b0a 3749 local_irq_enable();
afbcf7ab
GC		 3750 kvm->arch.kvmclock_offset = delta;
3751 break;
3752 }
3753 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3754 struct kvm_clock_data user_ns;
3755 u64 now_ns;
3756
395c6b0a 3757 local_irq_disable();
759379dd 3758 now_ns = get_kernel_ns();
afbcf7ab 3759 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3760 local_irq_enable();
afbcf7ab 3761 user_ns.flags = 0;
97e69aa6 3762 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3763
3764 r = -EFAULT;
3765 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3766 goto out;
3767 r = 0;
3768 break;
3769 }
3770
1fe779f8
CO		 3771 default:
3772 ;
3773 }
3774out:
3775 return r;
3776}
3777
a16b043c 3778static void kvm_init_msr_list(void)
043405e1
CO		 3779{
3780 u32 dummy[2];
3781 unsigned i, j;
3782
e3267cbb
GC		 3783 /* skip the first msrs in the list. KVM-specific */
3784 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3785 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3786 continue;
3787 if (j < i)
3788 msrs_to_save[j] = msrs_to_save[i];
3789 j++;
3790 }
3791 num_msrs_to_save = j;
3792}
3793
bda9020e
MT		 3794static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3795 const void *v)
bbd9b64e 3796{
70252a10
AK		 3797 int handled = 0;
3798 int n;
3799
3800 do {
3801 n = min(len, 8);
3802 if (!(vcpu->arch.apic &&
3803 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3804 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3805 break;
3806 handled += n;
3807 addr += n;
3808 len -= n;
3809 v += n;
3810 } while (len);
bbd9b64e 3811
70252a10 3812 return handled;
bbd9b64e
CO		 3813}
3814
bda9020e 3815static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3816{
70252a10
AK		 3817 int handled = 0;
3818 int n;
3819
3820 do {
3821 n = min(len, 8);
3822 if (!(vcpu->arch.apic &&
3823 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3824 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3825 break;
3826 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3827 handled += n;
3828 addr += n;
3829 len -= n;
3830 v += n;
3831 } while (len);
bbd9b64e 3832
70252a10 3833 return handled;
bbd9b64e
CO		 3834}
3835
2dafc6c2
GN		 3836static void kvm_set_segment(struct kvm_vcpu *vcpu,
3837 struct kvm_segment *var, int seg)
3838{
3839 kvm_x86_ops->set_segment(vcpu, var, seg);
3840}
3841
3842void kvm_get_segment(struct kvm_vcpu *vcpu,
3843 struct kvm_segment *var, int seg)
3844{
3845 kvm_x86_ops->get_segment(vcpu, var, seg);
3846}
3847
e459e322 3848gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
02f59dc9
JR		 3849{
3850 gpa_t t_gpa;
ab9ae313 3851 struct x86_exception exception;
02f59dc9
JR		 3852
3853 BUG_ON(!mmu_is_nested(vcpu));
3854
3855 /* NPT walks are always user-walks */
3856 access |= PFERR_USER_MASK;
ab9ae313 3857 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
02f59dc9
JR		 3858
3859 return t_gpa;
3860}
3861
ab9ae313
AK		 3862gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3863 struct x86_exception *exception)
1871c602
GN		 3864{
3865 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 3866 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3867}
3868
ab9ae313
AK		 3869 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3870 struct x86_exception *exception)
1871c602
GN		 3871{
3872 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3873 access |= PFERR_FETCH_MASK;
ab9ae313 3874 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3875}
3876
ab9ae313
AK		 3877gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3878 struct x86_exception *exception)
1871c602
GN		 3879{
3880 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3881 access |= PFERR_WRITE_MASK;
ab9ae313 3882 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3883}
3884
3885/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 3886gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3887 struct x86_exception *exception)
1871c602 3888{
ab9ae313 3889 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 3890}
3891
3892static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3893 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 3894 struct x86_exception *exception)
bbd9b64e
CO		 3895{
3896 void *data = val;
10589a46 3897 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3898
3899 while (bytes) {
14dfe855 3900 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 3901 exception);
bbd9b64e 3902 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3903 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3904 int ret;
3905
bcc55cba 3906 if (gpa == UNMAPPED_GVA)
ab9ae313 3907 return X86EMUL_PROPAGATE_FAULT;
77c2002e 3908 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3909 if (ret < 0) {
c3cd7ffa 3910 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3911 goto out;
3912 }
bbd9b64e 3913
77c2002e
IE		 3914 bytes -= toread;
3915 data += toread;
3916 addr += toread;
bbd9b64e 3917 }
10589a46 3918out:
10589a46 3919 return r;
bbd9b64e 3920}
77c2002e 3921
1871c602 3922/* used for instruction fetching */
0f65dd70
AK		 3923static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
3924 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3925 struct x86_exception *exception)
1871c602 3926{
0f65dd70 3927 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3928 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3929
1871c602 3930 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
bcc55cba
AK		 3931 access | PFERR_FETCH_MASK,
3932 exception);
1871c602
GN		 3933}
3934
064aea77 3935int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 3936 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3937 struct x86_exception *exception)
1871c602 3938{
0f65dd70 3939 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3940 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3941
1871c602 3942 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 3943 exception);
1871c602 3944}
064aea77 3945EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 3946
0f65dd70
AK		 3947static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3948 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3949 struct x86_exception *exception)
1871c602 3950{
0f65dd70 3951 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 3952 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 3953}
3954
6a4d7550 3955int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 3956 gva_t addr, void *val,
2dafc6c2 3957 unsigned int bytes,
bcc55cba 3958 struct x86_exception *exception)
77c2002e 3959{
0f65dd70 3960 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 3961 void *data = val;
3962 int r = X86EMUL_CONTINUE;
3963
3964 while (bytes) {
14dfe855
JR		 3965 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3966 PFERR_WRITE_MASK,
ab9ae313 3967 exception);
77c2002e
IE		 3968 unsigned offset = addr & (PAGE_SIZE-1);
3969 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3970 int ret;
3971
bcc55cba 3972 if (gpa == UNMAPPED_GVA)
ab9ae313 3973 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 3974 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3975 if (ret < 0) {
c3cd7ffa 3976 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 3977 goto out;
3978 }
3979
3980 bytes -= towrite;
3981 data += towrite;
3982 addr += towrite;
3983 }
3984out:
3985 return r;
3986}
6a4d7550 3987EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 3988
af7cc7d1
XG		 3989static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
3990 gpa_t *gpa, struct x86_exception *exception,
3991 bool write)
3992{
97d64b78
AK		 3993 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
3994 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 3995
97d64b78
AK		 3996 if (vcpu_match_mmio_gva(vcpu, gva)
3997 && !permission_fault(vcpu->arch.walk_mmu, vcpu->arch.access, access)) {
bebb106a
XG		 3998 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
3999 (gva & (PAGE_SIZE - 1));
4f022648 4000 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4001 return 1;
4002 }
4003
af7cc7d1
XG		 4004 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4005
4006 if (*gpa == UNMAPPED_GVA)
4007 return -1;
4008
4009 /* For APIC access vmexit */
4010 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4011 return 1;
4012
4f022648
XG		 4013 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4014 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4015 return 1;
4f022648 4016 }
bebb106a 4017
af7cc7d1
XG		 4018 return 0;
4019}
4020
3200f405 4021int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4022 const void *val, int bytes)
bbd9b64e
CO		 4023{
4024 int ret;
4025
4026 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 4027 if (ret < 0)
bbd9b64e 4028 return 0;
f57f2ef5 4029 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4030 return 1;
4031}
4032
77d197b2
XG		 4033struct read_write_emulator_ops {
4034 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4035 int bytes);
4036 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4037 void *val, int bytes);
4038 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4039 int bytes, void *val);
4040 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4041 void *val, int bytes);
4042 bool write;
4043};
4044
4045static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4046{
4047 if (vcpu->mmio_read_completed) {
77d197b2 4048 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4049 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4050 vcpu->mmio_read_completed = 0;
4051 return 1;
4052 }
4053
4054 return 0;
4055}
4056
4057static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4058 void *val, int bytes)
4059{
4060 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4061}
4062
4063static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4064 void *val, int bytes)
4065{
4066 return emulator_write_phys(vcpu, gpa, val, bytes);
4067}
4068
4069static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4070{
4071 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4072 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4073}
4074
4075static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4076 void *val, int bytes)
4077{
4078 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4079 return X86EMUL_IO_NEEDED;
4080}
4081
4082static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4083 void *val, int bytes)
4084{
f78146b0
AK		 4085 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4086
87da7e66 4087 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4088 return X86EMUL_CONTINUE;
4089}
4090
0fbe9b0b 4091static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4092 .read_write_prepare = read_prepare,
4093 .read_write_emulate = read_emulate,
4094 .read_write_mmio = vcpu_mmio_read,
4095 .read_write_exit_mmio = read_exit_mmio,
4096};
4097
0fbe9b0b 4098static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4099 .read_write_emulate = write_emulate,
4100 .read_write_mmio = write_mmio,
4101 .read_write_exit_mmio = write_exit_mmio,
4102 .write = true,
4103};
4104
22388a3c
XG		 4105static int emulator_read_write_onepage(unsigned long addr, void *val,
4106 unsigned int bytes,
4107 struct x86_exception *exception,
4108 struct kvm_vcpu *vcpu,
0fbe9b0b 4109 const struct read_write_emulator_ops *ops)
bbd9b64e 4110{
af7cc7d1
XG		 4111 gpa_t gpa;
4112 int handled, ret;
22388a3c 4113 bool write = ops->write;
f78146b0 4114 struct kvm_mmio_fragment *frag;
10589a46 4115
22388a3c 4116 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4117
af7cc7d1 4118 if (ret < 0)
bbd9b64e 4119 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4120
4121 /* For APIC access vmexit */
af7cc7d1 4122 if (ret)
bbd9b64e
CO		 4123 goto mmio;
4124
22388a3c 4125 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4126 return X86EMUL_CONTINUE;
4127
4128mmio:
4129 /*
4130 * Is this MMIO handled locally?
4131 */
22388a3c 4132 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4133 if (handled == bytes)
bbd9b64e 4134 return X86EMUL_CONTINUE;
bbd9b64e 4135
70252a10
AK		 4136 gpa += handled;
4137 bytes -= handled;
4138 val += handled;
4139
87da7e66
XG		 4140 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4141 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4142 frag->gpa = gpa;
4143 frag->data = val;
4144 frag->len = bytes;
f78146b0 4145 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4146}
4147
22388a3c
XG		 4148int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4149 void *val, unsigned int bytes,
4150 struct x86_exception *exception,
0fbe9b0b 4151 const struct read_write_emulator_ops *ops)
bbd9b64e 4152{
0f65dd70 4153 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4154 gpa_t gpa;
4155 int rc;
4156
4157 if (ops->read_write_prepare &&
4158 ops->read_write_prepare(vcpu, val, bytes))
4159 return X86EMUL_CONTINUE;
4160
4161 vcpu->mmio_nr_fragments = 0;
0f65dd70 4162
bbd9b64e
CO		 4163 /* Crossing a page boundary? */
4164 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4165 int now;
bbd9b64e
CO		 4166
4167 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4168 rc = emulator_read_write_onepage(addr, val, now, exception,
4169 vcpu, ops);
4170
bbd9b64e
CO		 4171 if (rc != X86EMUL_CONTINUE)
4172 return rc;
4173 addr += now;
4174 val += now;
4175 bytes -= now;
4176 }
22388a3c 4177
f78146b0
AK		 4178 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4179 vcpu, ops);
4180 if (rc != X86EMUL_CONTINUE)
4181 return rc;
4182
4183 if (!vcpu->mmio_nr_fragments)
4184 return rc;
4185
4186 gpa = vcpu->mmio_fragments[0].gpa;
4187
4188 vcpu->mmio_needed = 1;
4189 vcpu->mmio_cur_fragment = 0;
4190
87da7e66 4191 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4192 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4193 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4194 vcpu->run->mmio.phys_addr = gpa;
4195
4196 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4197}
4198
4199static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4200 unsigned long addr,
4201 void *val,
4202 unsigned int bytes,
4203 struct x86_exception *exception)
4204{
4205 return emulator_read_write(ctxt, addr, val, bytes,
4206 exception, &read_emultor);
4207}
4208
4209int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4210 unsigned long addr,
4211 const void *val,
4212 unsigned int bytes,
4213 struct x86_exception *exception)
4214{
4215 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4216 exception, &write_emultor);
bbd9b64e 4217}
bbd9b64e 4218
daea3e73
AK		 4219#define CMPXCHG_TYPE(t, ptr, old, new) \
4220 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4221
4222#ifdef CONFIG_X86_64
4223# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4224#else
4225# define CMPXCHG64(ptr, old, new) \
9749a6c0 4226 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4227#endif
4228
0f65dd70
AK		 4229static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4230 unsigned long addr,
bbd9b64e
CO		 4231 const void *old,
4232 const void *new,
4233 unsigned int bytes,
0f65dd70 4234 struct x86_exception *exception)
bbd9b64e 4235{
0f65dd70 4236 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4237 gpa_t gpa;
4238 struct page *page;
4239 char *kaddr;
4240 bool exchanged;
2bacc55c 4241
daea3e73
AK		 4242 /* guests cmpxchg8b have to be emulated atomically */
4243 if (bytes > 8 || (bytes & (bytes - 1)))
4244 goto emul_write;
10589a46 4245
daea3e73 4246 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4247
daea3e73
AK		 4248 if (gpa == UNMAPPED_GVA ||
4249 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4250 goto emul_write;
2bacc55c 4251
daea3e73
AK		 4252 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4253 goto emul_write;
72dc67a6 4254
daea3e73 4255 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
32cad84f 4256 if (is_error_page(page))
c19b8bd6 4257 goto emul_write;
72dc67a6 4258
8fd75e12 4259 kaddr = kmap_atomic(page);
daea3e73
AK		 4260 kaddr += offset_in_page(gpa);
4261 switch (bytes) {
4262 case 1:
4263 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4264 break;
4265 case 2:
4266 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4267 break;
4268 case 4:
4269 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4270 break;
4271 case 8:
4272 exchanged = CMPXCHG64(kaddr, old, new);
4273 break;
4274 default:
4275 BUG();
2bacc55c 4276 }
8fd75e12 4277 kunmap_atomic(kaddr);
daea3e73
AK		 4278 kvm_release_page_dirty(page);
4279
4280 if (!exchanged)
4281 return X86EMUL_CMPXCHG_FAILED;
4282
f57f2ef5 4283 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4284
4285 return X86EMUL_CONTINUE;
4a5f48f6 4286
3200f405 4287emul_write:
daea3e73 4288 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4289
0f65dd70 4290 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4291}
4292
cf8f70bf
GN		 4293static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4294{
4295 /* TODO: String I/O for in kernel device */
4296 int r;
4297
4298 if (vcpu->arch.pio.in)
4299 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4300 vcpu->arch.pio.size, pd);
4301 else
4302 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4303 vcpu->arch.pio.port, vcpu->arch.pio.size,
4304 pd);
4305 return r;
4306}
4307
6f6fbe98
XG		 4308static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4309 unsigned short port, void *val,
4310 unsigned int count, bool in)
cf8f70bf 4311{
6f6fbe98 4312 trace_kvm_pio(!in, port, size, count);
cf8f70bf
GN		 4313
4314 vcpu->arch.pio.port = port;
6f6fbe98 4315 vcpu->arch.pio.in = in;
7972995b 4316 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4317 vcpu->arch.pio.size = size;
4318
4319 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4320 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4321 return 1;
4322 }
4323
4324 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4325 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4326 vcpu->run->io.size = size;
4327 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4328 vcpu->run->io.count = count;
4329 vcpu->run->io.port = port;
4330
4331 return 0;
4332}
4333
6f6fbe98
XG		 4334static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4335 int size, unsigned short port, void *val,
4336 unsigned int count)
cf8f70bf 4337{
ca1d4a9e 4338 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4339 int ret;
ca1d4a9e 4340
6f6fbe98
XG		 4341 if (vcpu->arch.pio.count)
4342 goto data_avail;
cf8f70bf 4343
6f6fbe98
XG		 4344 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4345 if (ret) {
4346data_avail:
4347 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 4348 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4349 return 1;
4350 }
4351
cf8f70bf
GN		 4352 return 0;
4353}
4354
6f6fbe98
XG		 4355static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4356 int size, unsigned short port,
4357 const void *val, unsigned int count)
4358{
4359 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4360
4361 memcpy(vcpu->arch.pio_data, val, size * count);
4362 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4363}
4364
bbd9b64e
CO		 4365static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4366{
4367 return kvm_x86_ops->get_segment_base(vcpu, seg);
4368}
4369
3cb16fe7 4370static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4371{
3cb16fe7 4372 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4373}
4374
f5f48ee1
SY		 4375int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4376{
4377 if (!need_emulate_wbinvd(vcpu))
4378 return X86EMUL_CONTINUE;
4379
4380 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4381 int cpu = get_cpu();
4382
4383 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4384 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4385 wbinvd_ipi, NULL, 1);
2eec7343 4386 put_cpu();
f5f48ee1 4387 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4388 } else
4389 wbinvd();
f5f48ee1
SY		 4390 return X86EMUL_CONTINUE;
4391}
4392EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4393
bcaf5cc5
AK		 4394static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4395{
4396 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4397}
4398
717746e3 4399int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
bbd9b64e 4400{
717746e3 4401 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4402}
4403
717746e3 4404int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
bbd9b64e 4405{
338dbc97 4406
717746e3 4407 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4408}
4409
52a46617 4410static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4411{
52a46617 4412 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4413}
4414
717746e3 4415static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4416{
717746e3 4417 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4418 unsigned long value;
4419
4420 switch (cr) {
4421 case 0:
4422 value = kvm_read_cr0(vcpu);
4423 break;
4424 case 2:
4425 value = vcpu->arch.cr2;
4426 break;
4427 case 3:
9f8fe504 4428 value = kvm_read_cr3(vcpu);
52a46617
GN		 4429 break;
4430 case 4:
4431 value = kvm_read_cr4(vcpu);
4432 break;
4433 case 8:
4434 value = kvm_get_cr8(vcpu);
4435 break;
4436 default:
a737f256 4437 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4438 return 0;
4439 }
4440
4441 return value;
4442}
4443
717746e3 4444static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4445{
717746e3 4446 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4447 int res = 0;
4448
52a46617
GN		 4449 switch (cr) {
4450 case 0:
49a9b07e 4451 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4452 break;
4453 case 2:
4454 vcpu->arch.cr2 = val;
4455 break;
4456 case 3:
2390218b 4457 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4458 break;
4459 case 4:
a83b29c6 4460 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4461 break;
4462 case 8:
eea1cff9 4463 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4464 break;
4465 default:
a737f256 4466 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4467 res = -1;
52a46617 4468 }
0f12244f
GN		 4469
4470 return res;
52a46617
GN		 4471}
4472
4cee4798
KW		 4473static void emulator_set_rflags(struct x86_emulate_ctxt *ctxt, ulong val)
4474{
4475 kvm_set_rflags(emul_to_vcpu(ctxt), val);
4476}
4477
717746e3 4478static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4479{
717746e3 4480 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4481}
4482
4bff1e86 4483static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4484{
4bff1e86 4485 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4486}
4487
4bff1e86 4488static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4489{
4bff1e86 4490 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4491}
4492
1ac9d0cf
AK		 4493static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4494{
4495 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4496}
4497
4498static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4499{
4500 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4501}
4502
4bff1e86
AK		 4503static unsigned long emulator_get_cached_segment_base(
4504 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4505{
4bff1e86 4506 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4507}
4508
1aa36616
AK		 4509static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4510 struct desc_struct *desc, u32 *base3,
4511 int seg)
2dafc6c2
GN		 4512{
4513 struct kvm_segment var;
4514
4bff1e86 4515 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4516 *selector = var.selector;
2dafc6c2 4517
378a8b09
GN		 4518 if (var.unusable) {
4519 memset(desc, 0, sizeof(*desc));
2dafc6c2 4520 return false;
378a8b09 4521 }
2dafc6c2
GN		 4522
4523 if (var.g)
4524 var.limit >>= 12;
4525 set_desc_limit(desc, var.limit);
4526 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4527#ifdef CONFIG_X86_64
4528 if (base3)
4529 *base3 = var.base >> 32;
4530#endif
2dafc6c2
GN		 4531 desc->type = var.type;
4532 desc->s = var.s;
4533 desc->dpl = var.dpl;
4534 desc->p = var.present;
4535 desc->avl = var.avl;
4536 desc->l = var.l;
4537 desc->d = var.db;
4538 desc->g = var.g;
4539
4540 return true;
4541}
4542
1aa36616
AK		 4543static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4544 struct desc_struct *desc, u32 base3,
4545 int seg)
2dafc6c2 4546{
4bff1e86 4547 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4548 struct kvm_segment var;
4549
1aa36616 4550 var.selector = selector;
2dafc6c2 4551 var.base = get_desc_base(desc);
5601d05b
GN		 4552#ifdef CONFIG_X86_64
4553 var.base |= ((u64)base3) << 32;
4554#endif
2dafc6c2
GN		 4555 var.limit = get_desc_limit(desc);
4556 if (desc->g)
4557 var.limit = (var.limit << 12) | 0xfff;
4558 var.type = desc->type;
4559 var.present = desc->p;
4560 var.dpl = desc->dpl;
4561 var.db = desc->d;
4562 var.s = desc->s;
4563 var.l = desc->l;
4564 var.g = desc->g;
4565 var.avl = desc->avl;
4566 var.present = desc->p;
4567 var.unusable = !var.present;
4568 var.padding = 0;
4569
4570 kvm_set_segment(vcpu, &var, seg);
4571 return;
4572}
4573
717746e3
AK		 4574static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4575 u32 msr_index, u64 *pdata)
4576{
4577 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4578}
4579
4580static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4581 u32 msr_index, u64 data)
4582{
8fe8ab46
WA		 4583 struct msr_data msr;
4584
4585 msr.data = data;
4586 msr.index = msr_index;
4587 msr.host_initiated = false;
4588 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4589}
4590
222d21aa
AK		 4591static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4592 u32 pmc, u64 *pdata)
4593{
4594 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4595}
4596
6c3287f7
AK		 4597static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4598{
4599 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4600}
4601
5037f6f3
AK		 4602static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4603{
4604 preempt_disable();
5197b808 4605 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4606 /*
4607 * CR0.TS may reference the host fpu state, not the guest fpu state,
4608 * so it may be clear at this point.
4609 */
4610 clts();
4611}
4612
4613static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4614{
4615 preempt_enable();
4616}
4617
2953538e 4618static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4619 struct x86_instruction_info *info,
c4f035c6
AK		 4620 enum x86_intercept_stage stage)
4621{
2953538e 4622 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4623}
4624
0017f93a 4625static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4626 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4627{
0017f93a 4628 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4629}
4630
dd856efa
AK		 4631static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4632{
4633 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4634}
4635
4636static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4637{
4638 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4639}
4640
0225fb50 4641static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 4642 .read_gpr = emulator_read_gpr,
4643 .write_gpr = emulator_write_gpr,
1871c602 4644 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4645 .write_std = kvm_write_guest_virt_system,
1871c602 4646 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4647 .read_emulated = emulator_read_emulated,
4648 .write_emulated = emulator_write_emulated,
4649 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4650 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4651 .pio_in_emulated = emulator_pio_in_emulated,
4652 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4653 .get_segment = emulator_get_segment,
4654 .set_segment = emulator_set_segment,
5951c442 4655 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4656 .get_gdt = emulator_get_gdt,
160ce1f1 4657 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4658 .set_gdt = emulator_set_gdt,
4659 .set_idt = emulator_set_idt,
52a46617
GN		 4660 .get_cr = emulator_get_cr,
4661 .set_cr = emulator_set_cr,
4cee4798 4662 .set_rflags = emulator_set_rflags,
9c537244 4663 .cpl = emulator_get_cpl,
35aa5375
GN		 4664 .get_dr = emulator_get_dr,
4665 .set_dr = emulator_set_dr,
717746e3
AK		 4666 .set_msr = emulator_set_msr,
4667 .get_msr = emulator_get_msr,
222d21aa 4668 .read_pmc = emulator_read_pmc,
6c3287f7 4669 .halt = emulator_halt,
bcaf5cc5 4670 .wbinvd = emulator_wbinvd,
d6aa1000 4671 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4672 .get_fpu = emulator_get_fpu,
4673 .put_fpu = emulator_put_fpu,
c4f035c6 4674 .intercept = emulator_intercept,
bdb42f5a 4675 .get_cpuid = emulator_get_cpuid,
bbd9b64e
CO		 4676};
4677
95cb2295
GN		 4678static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4679{
4680 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4681 /*
4682 * an sti; sti; sequence only disable interrupts for the first
4683 * instruction. So, if the last instruction, be it emulated or
4684 * not, left the system with the INT_STI flag enabled, it
4685 * means that the last instruction is an sti. We should not
4686 * leave the flag on in this case. The same goes for mov ss
4687 */
4688 if (!(int_shadow & mask))
4689 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4690}
4691
54b8486f
GN		 4692static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4693{
4694 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4695 if (ctxt->exception.vector == PF_VECTOR)
6389ee94 4696 kvm_propagate_fault(vcpu, &ctxt->exception);
da9cb575
AK		 4697 else if (ctxt->exception.error_code_valid)
4698 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4699 ctxt->exception.error_code);
54b8486f 4700 else
da9cb575 4701 kvm_queue_exception(vcpu, ctxt->exception.vector);
54b8486f
GN		 4702}
4703
dd856efa 4704static void init_decode_cache(struct x86_emulate_ctxt *ctxt)
b5c9ff73 4705{
9dac77fa 4706 memset(&ctxt->twobyte, 0,
dd856efa 4707 (void *)&ctxt->_regs - (void *)&ctxt->twobyte);
b5c9ff73 4708
9dac77fa
AK		 4709 ctxt->fetch.start = 0;
4710 ctxt->fetch.end = 0;
4711 ctxt->io_read.pos = 0;
4712 ctxt->io_read.end = 0;
4713 ctxt->mem_read.pos = 0;
4714 ctxt->mem_read.end = 0;
b5c9ff73
TY		 4715}
4716
8ec4722d
MG		 4717static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4718{
adf52235 4719 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4720 int cs_db, cs_l;
4721
8ec4722d
MG		 4722 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4723
adf52235
TY		 4724 ctxt->eflags = kvm_get_rflags(vcpu);
4725 ctxt->eip = kvm_rip_read(vcpu);
4726 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4727 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4728 cs_l ? X86EMUL_MODE_PROT64 :
4729 cs_db ? X86EMUL_MODE_PROT32 :
4730 X86EMUL_MODE_PROT16;
4731 ctxt->guest_mode = is_guest_mode(vcpu);
4732
dd856efa 4733 init_decode_cache(ctxt);
7ae441ea 4734 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4735}
4736
71f9833b 4737int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 4738{
9d74191a 4739 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 4740 int ret;
4741
4742 init_emulate_ctxt(vcpu);
4743
9dac77fa
AK		 4744 ctxt->op_bytes = 2;
4745 ctxt->ad_bytes = 2;
4746 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 4747 ret = emulate_int_real(ctxt, irq);
63995653
MG		 4748
4749 if (ret != X86EMUL_CONTINUE)
4750 return EMULATE_FAIL;
4751
9dac77fa 4752 ctxt->eip = ctxt->_eip;
9d74191a
TY		 4753 kvm_rip_write(vcpu, ctxt->eip);
4754 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 4755
4756 if (irq == NMI_VECTOR)
7460fb4a 4757 vcpu->arch.nmi_pending = 0;
63995653
MG		 4758 else
4759 vcpu->arch.interrupt.pending = false;
4760
4761 return EMULATE_DONE;
4762}
4763EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4764
6d77dbfc
GN		 4765static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4766{
fc3a9157
JR		 4767 int r = EMULATE_DONE;
4768
6d77dbfc
GN		 4769 ++vcpu->stat.insn_emulation_fail;
4770 trace_kvm_emulate_insn_failed(vcpu);
fc3a9157
JR		 4771 if (!is_guest_mode(vcpu)) {
4772 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4773 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4774 vcpu->run->internal.ndata = 0;
4775 r = EMULATE_FAIL;
4776 }
6d77dbfc 4777 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4778
4779 return r;
6d77dbfc
GN		 4780}
4781
93c05d3e 4782static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 4783 bool write_fault_to_shadow_pgtable,
4784 int emulation_type)
a6f177ef 4785{
95b3cf69 4786 gpa_t gpa = cr2;
8e3d9d06 4787 pfn_t pfn;
a6f177ef 4788
991eebf9
GN		 4789 if (emulation_type & EMULTYPE_NO_REEXECUTE)
4790 return false;
4791
95b3cf69
XG		 4792 if (!vcpu->arch.mmu.direct_map) {
4793 /*
4794 * Write permission should be allowed since only
4795 * write access need to be emulated.
4796 */
4797 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
22368028 4798
95b3cf69
XG		 4799 /*
4800 * If the mapping is invalid in guest, let cpu retry
4801 * it to generate fault.
4802 */
4803 if (gpa == UNMAPPED_GVA)
4804 return true;
4805 }
a6f177ef 4806
8e3d9d06
XG		 4807 /*
4808 * Do not retry the unhandleable instruction if it faults on the
4809 * readonly host memory, otherwise it will goto a infinite loop:
4810 * retry instruction -> write #PF -> emulation fail -> retry
4811 * instruction -> ...
4812 */
4813 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 4814
4815 /*
4816 * If the instruction failed on the error pfn, it can not be fixed,
4817 * report the error to userspace.
4818 */
4819 if (is_error_noslot_pfn(pfn))
4820 return false;
4821
4822 kvm_release_pfn_clean(pfn);
4823
4824 /* The instructions are well-emulated on direct mmu. */
4825 if (vcpu->arch.mmu.direct_map) {
4826 unsigned int indirect_shadow_pages;
4827
4828 spin_lock(&vcpu->kvm->mmu_lock);
4829 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
4830 spin_unlock(&vcpu->kvm->mmu_lock);
4831
4832 if (indirect_shadow_pages)
4833 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
4834
a6f177ef 4835 return true;
8e3d9d06 4836 }
a6f177ef 4837
95b3cf69
XG		 4838 /*
4839 * if emulation was due to access to shadowed page table
4840 * and it failed try to unshadow page and re-enter the
4841 * guest to let CPU execute the instruction.
4842 */
4843 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 4844
4845 /*
4846 * If the access faults on its page table, it can not
4847 * be fixed by unprotecting shadow page and it should
4848 * be reported to userspace.
4849 */
4850 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 4851}
4852
1cb3f3ae
XG		 4853static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
4854 unsigned long cr2, int emulation_type)
4855{
4856 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4857 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
4858
4859 last_retry_eip = vcpu->arch.last_retry_eip;
4860 last_retry_addr = vcpu->arch.last_retry_addr;
4861
4862 /*
4863 * If the emulation is caused by #PF and it is non-page_table
4864 * writing instruction, it means the VM-EXIT is caused by shadow
4865 * page protected, we can zap the shadow page and retry this
4866 * instruction directly.
4867 *
4868 * Note: if the guest uses a non-page-table modifying instruction
4869 * on the PDE that points to the instruction, then we will unmap
4870 * the instruction and go to an infinite loop. So, we cache the
4871 * last retried eip and the last fault address, if we meet the eip
4872 * and the address again, we can break out of the potential infinite
4873 * loop.
4874 */
4875 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
4876
4877 if (!(emulation_type & EMULTYPE_RETRY))
4878 return false;
4879
4880 if (x86_page_table_writing_insn(ctxt))
4881 return false;
4882
4883 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
4884 return false;
4885
4886 vcpu->arch.last_retry_eip = ctxt->eip;
4887 vcpu->arch.last_retry_addr = cr2;
4888
4889 if (!vcpu->arch.mmu.direct_map)
4890 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4891
22368028 4892 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 4893
4894 return true;
4895}
4896
716d51ab
GN		 4897static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
4898static int complete_emulated_pio(struct kvm_vcpu *vcpu);
4899
51d8b661
AP		 4900int x86_emulate_instruction(struct kvm_vcpu *vcpu,
4901 unsigned long cr2,
dc25e89e
AP		 4902 int emulation_type,
4903 void *insn,
4904 int insn_len)
bbd9b64e 4905{
95cb2295 4906 int r;
9d74191a 4907 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 4908 bool writeback = true;
93c05d3e 4909 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 4910
93c05d3e
XG		 4911 /*
4912 * Clear write_fault_to_shadow_pgtable here to ensure it is
4913 * never reused.
4914 */
4915 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 4916 kvm_clear_exception_queue(vcpu);
8d7d8102 4917
571008da 4918 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 4919 init_emulate_ctxt(vcpu);
9d74191a
TY		 4920 ctxt->interruptibility = 0;
4921 ctxt->have_exception = false;
4922 ctxt->perm_ok = false;
bbd9b64e 4923
9d74191a 4924 ctxt->only_vendor_specific_insn
4005996e
AK		 4925 = emulation_type & EMULTYPE_TRAP_UD;
4926
9d74191a 4927 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 4928
e46479f8 4929 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 4930 ++vcpu->stat.insn_emulation;
1d2887e2 4931 if (r != EMULATION_OK) {
4005996e
AK		 4932 if (emulation_type & EMULTYPE_TRAP_UD)
4933 return EMULATE_FAIL;
991eebf9
GN		 4934 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
4935 emulation_type))
bbd9b64e 4936 return EMULATE_DONE;
6d77dbfc
GN		 4937 if (emulation_type & EMULTYPE_SKIP)
4938 return EMULATE_FAIL;
4939 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4940 }
4941 }
4942
ba8afb6b 4943 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 4944 kvm_rip_write(vcpu, ctxt->_eip);
ba8afb6b
GN		 4945 return EMULATE_DONE;
4946 }
4947
1cb3f3ae
XG		 4948 if (retry_instruction(ctxt, cr2, emulation_type))
4949 return EMULATE_DONE;
4950
7ae441ea 4951 /* this is needed for vmware backdoor interface to work since it
4d2179e1 4952 changes registers values during IO operation */
7ae441ea
GN		 4953 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
4954 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 4955 emulator_invalidate_register_cache(ctxt);
7ae441ea 4956 }
4d2179e1 4957
5cd21917 4958restart:
9d74191a 4959 r = x86_emulate_insn(ctxt);
bbd9b64e 4960
775fde86
JR		 4961 if (r == EMULATION_INTERCEPTED)
4962 return EMULATE_DONE;
4963
d2ddd1c4 4964 if (r == EMULATION_FAILED) {
991eebf9
GN		 4965 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
4966 emulation_type))
c3cd7ffa
GN		 4967 return EMULATE_DONE;
4968
6d77dbfc 4969 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4970 }
4971
9d74191a 4972 if (ctxt->have_exception) {
54b8486f 4973 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 4974 r = EMULATE_DONE;
4975 } else if (vcpu->arch.pio.count) {
3457e419
GN		 4976 if (!vcpu->arch.pio.in)
4977 vcpu->arch.pio.count = 0;
716d51ab 4978 else {
7ae441ea 4979 writeback = false;
716d51ab
GN		 4980 vcpu->arch.complete_userspace_io = complete_emulated_pio;
4981 }
e85d28f8 4982 r = EMULATE_DO_MMIO;
7ae441ea
GN		 4983 } else if (vcpu->mmio_needed) {
4984 if (!vcpu->mmio_is_write)
4985 writeback = false;
e85d28f8 4986 r = EMULATE_DO_MMIO;
716d51ab 4987 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 4988 } else if (r == EMULATION_RESTART)
5cd21917 4989 goto restart;
d2ddd1c4
GN		 4990 else
4991 r = EMULATE_DONE;
f850e2e6 4992
7ae441ea 4993 if (writeback) {
9d74191a
TY		 4994 toggle_interruptibility(vcpu, ctxt->interruptibility);
4995 kvm_set_rflags(vcpu, ctxt->eflags);
7ae441ea 4996 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea 4997 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 4998 kvm_rip_write(vcpu, ctxt->eip);
7ae441ea
GN		 4999 } else
5000 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5001
5002 return r;
de7d789a 5003}
51d8b661 5004EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5005
cf8f70bf 5006int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5007{
cf8f70bf 5008 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5009 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5010 size, port, &val, 1);
cf8f70bf 5011 /* do not return to emulator after return from userspace */
7972995b 5012 vcpu->arch.pio.count = 0;
de7d789a
CO		 5013 return ret;
5014}
cf8f70bf 5015EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5016
8cfdc000
ZA		 5017static void tsc_bad(void *info)
5018{
0a3aee0d 5019 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5020}
5021
5022static void tsc_khz_changed(void *data)
c8076604 5023{
8cfdc000
ZA		 5024 struct cpufreq_freqs *freq = data;
5025 unsigned long khz = 0;
5026
5027 if (data)
5028 khz = freq->new;
5029 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5030 khz = cpufreq_quick_get(raw_smp_processor_id());
5031 if (!khz)
5032 khz = tsc_khz;
0a3aee0d 5033 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5034}
5035
c8076604
GH		 5036static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5037 void *data)
5038{
5039 struct cpufreq_freqs *freq = data;
5040 struct kvm *kvm;
5041 struct kvm_vcpu *vcpu;
5042 int i, send_ipi = 0;
5043
8cfdc000
ZA		 5044 /*
5045 * We allow guests to temporarily run on slowing clocks,
5046 * provided we notify them after, or to run on accelerating
5047 * clocks, provided we notify them before. Thus time never
5048 * goes backwards.
5049 *
5050 * However, we have a problem. We can't atomically update
5051 * the frequency of a given CPU from this function; it is
5052 * merely a notifier, which can be called from any CPU.
5053 * Changing the TSC frequency at arbitrary points in time
5054 * requires a recomputation of local variables related to
5055 * the TSC for each VCPU. We must flag these local variables
5056 * to be updated and be sure the update takes place with the
5057 * new frequency before any guests proceed.
5058 *
5059 * Unfortunately, the combination of hotplug CPU and frequency
5060 * change creates an intractable locking scenario; the order
5061 * of when these callouts happen is undefined with respect to
5062 * CPU hotplug, and they can race with each other. As such,
5063 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5064 * undefined; you can actually have a CPU frequency change take
5065 * place in between the computation of X and the setting of the
5066 * variable. To protect against this problem, all updates of
5067 * the per_cpu tsc_khz variable are done in an interrupt
5068 * protected IPI, and all callers wishing to update the value
5069 * must wait for a synchronous IPI to complete (which is trivial
5070 * if the caller is on the CPU already). This establishes the
5071 * necessary total order on variable updates.
5072 *
5073 * Note that because a guest time update may take place
5074 * anytime after the setting of the VCPU's request bit, the
5075 * correct TSC value must be set before the request. However,
5076 * to ensure the update actually makes it to any guest which
5077 * starts running in hardware virtualization between the set
5078 * and the acquisition of the spinlock, we must also ping the
5079 * CPU after setting the request bit.
5080 *
5081 */
5082
c8076604
GH		 5083 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5084 return 0;
5085 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5086 return 0;
8cfdc000
ZA		 5087
5088 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5089
e935b837 5090 raw_spin_lock(&kvm_lock);
c8076604 5091 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5092 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5093 if (vcpu->cpu != freq->cpu)
5094 continue;
c285545f 5095 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5096 if (vcpu->cpu != smp_processor_id())
8cfdc000 5097 send_ipi = 1;
c8076604
GH		 5098 }
5099 }
e935b837 5100 raw_spin_unlock(&kvm_lock);
c8076604
GH		 5101
5102 if (freq->old < freq->new && send_ipi) {
5103 /*
5104 * We upscale the frequency. Must make the guest
5105 * doesn't see old kvmclock values while running with
5106 * the new frequency, otherwise we risk the guest sees
5107 * time go backwards.
5108 *
5109 * In case we update the frequency for another cpu
5110 * (which might be in guest context) send an interrupt
5111 * to kick the cpu out of guest context. Next time
5112 * guest context is entered kvmclock will be updated,
5113 * so the guest will not see stale values.
5114 */
8cfdc000 5115 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5116 }
5117 return 0;
5118}
5119
5120static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5121 .notifier_call = kvmclock_cpufreq_notifier
5122};
5123
5124static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5125 unsigned long action, void *hcpu)
5126{
5127 unsigned int cpu = (unsigned long)hcpu;
5128
5129 switch (action) {
5130 case CPU_ONLINE:
5131 case CPU_DOWN_FAILED:
5132 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5133 break;
5134 case CPU_DOWN_PREPARE:
5135 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5136 break;
5137 }
5138 return NOTIFY_OK;
5139}
5140
5141static struct notifier_block kvmclock_cpu_notifier_block = {
5142 .notifier_call = kvmclock_cpu_notifier,
5143 .priority = -INT_MAX
c8076604
GH		 5144};
5145
b820cc0c
ZA		 5146static void kvm_timer_init(void)
5147{
5148 int cpu;
5149
c285545f 5150 max_tsc_khz = tsc_khz;
8cfdc000 5151 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 5152 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5153#ifdef CONFIG_CPU_FREQ
5154 struct cpufreq_policy policy;
5155 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5156 cpu = get_cpu();
5157 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5158 if (policy.cpuinfo.max_freq)
5159 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5160 put_cpu();
c285545f 5161#endif
b820cc0c
ZA		 5162 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5163 CPUFREQ_TRANSITION_NOTIFIER);
5164 }
c285545f 5165 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5166 for_each_online_cpu(cpu)
5167 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 5168}
5169
ff9d07a0
ZY		 5170static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5171
f5132b01 5172int kvm_is_in_guest(void)
ff9d07a0 5173{
086c9855 5174 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5175}
5176
5177static int kvm_is_user_mode(void)
5178{
5179 int user_mode = 3;
dcf46b94 5180
086c9855
AS		 5181 if (__this_cpu_read(current_vcpu))
5182 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5183
ff9d07a0
ZY		 5184 return user_mode != 0;
5185}
5186
5187static unsigned long kvm_get_guest_ip(void)
5188{
5189 unsigned long ip = 0;
dcf46b94 5190
086c9855
AS		 5191 if (__this_cpu_read(current_vcpu))
5192 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5193
ff9d07a0
ZY		 5194 return ip;
5195}
5196
5197static struct perf_guest_info_callbacks kvm_guest_cbs = {
5198 .is_in_guest = kvm_is_in_guest,
5199 .is_user_mode = kvm_is_user_mode,
5200 .get_guest_ip = kvm_get_guest_ip,
5201};
5202
5203void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5204{
086c9855 5205 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5206}
5207EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5208
5209void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5210{
086c9855 5211 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5212}
5213EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5214
ce88decf
XG		 5215static void kvm_set_mmio_spte_mask(void)
5216{
5217 u64 mask;
5218 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5219
5220 /*
5221 * Set the reserved bits and the present bit of an paging-structure
5222 * entry to generate page fault with PFER.RSV = 1.
5223 */
5224 mask = ((1ull << (62 - maxphyaddr + 1)) - 1) << maxphyaddr;
5225 mask |= 1ull;
5226
5227#ifdef CONFIG_X86_64
5228 /*
5229 * If reserved bit is not supported, clear the present bit to disable
5230 * mmio page fault.
5231 */
5232 if (maxphyaddr == 52)
5233 mask &= ~1ull;
5234#endif
5235
5236 kvm_mmu_set_mmio_spte_mask(mask);
5237}
5238
16e8d74d
MT		 5239#ifdef CONFIG_X86_64
5240static void pvclock_gtod_update_fn(struct work_struct *work)
5241{
d828199e
MT		 5242 struct kvm *kvm;
5243
5244 struct kvm_vcpu *vcpu;
5245 int i;
5246
5247 raw_spin_lock(&kvm_lock);
5248 list_for_each_entry(kvm, &vm_list, vm_list)
5249 kvm_for_each_vcpu(i, vcpu, kvm)
5250 set_bit(KVM_REQ_MASTERCLOCK_UPDATE, &vcpu->requests);
5251 atomic_set(&kvm_guest_has_master_clock, 0);
5252 raw_spin_unlock(&kvm_lock);
16e8d74d
MT		 5253}
5254
5255static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5256
5257/*
5258 * Notification about pvclock gtod data update.
5259 */
5260static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5261 void *priv)
5262{
5263 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5264 struct timekeeper *tk = priv;
5265
5266 update_pvclock_gtod(tk);
5267
5268 /* disable master clock if host does not trust, or does not
5269 * use, TSC clocksource
5270 */
5271 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5272 atomic_read(&kvm_guest_has_master_clock) != 0)
5273 queue_work(system_long_wq, &pvclock_gtod_work);
5274
5275 return 0;
5276}
5277
5278static struct notifier_block pvclock_gtod_notifier = {
5279 .notifier_call = pvclock_gtod_notify,
5280};
5281#endif
5282
f8c16bba 5283int kvm_arch_init(void *opaque)
043405e1 5284{
b820cc0c 5285 int r;
f8c16bba
ZX		 5286 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
5287
f8c16bba
ZX		 5288 if (kvm_x86_ops) {
5289 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5290 r = -EEXIST;
5291 goto out;
f8c16bba
ZX		 5292 }
5293
5294 if (!ops->cpu_has_kvm_support()) {
5295 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5296 r = -EOPNOTSUPP;
5297 goto out;
f8c16bba
ZX		 5298 }
5299 if (ops->disabled_by_bios()) {
5300 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5301 r = -EOPNOTSUPP;
5302 goto out;
f8c16bba
ZX		 5303 }
5304
013f6a5d
MT		 5305 r = -ENOMEM;
5306 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5307 if (!shared_msrs) {
5308 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5309 goto out;
5310 }
5311
97db56ce
AK		 5312 r = kvm_mmu_module_init();
5313 if (r)
013f6a5d 5314 goto out_free_percpu;
97db56ce 5315
ce88decf 5316 kvm_set_mmio_spte_mask();
97db56ce
AK		 5317 kvm_init_msr_list();
5318
f8c16bba 5319 kvm_x86_ops = ops;
7b52345e 5320 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5321 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5322
b820cc0c 5323 kvm_timer_init();
c8076604 5324
ff9d07a0
ZY		 5325 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5326
2acf923e
DC		 5327 if (cpu_has_xsave)
5328 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5329
c5cc421b 5330 kvm_lapic_init();
16e8d74d
MT		 5331#ifdef CONFIG_X86_64
5332 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5333#endif
5334
f8c16bba 5335 return 0;
56c6d28a 5336
013f6a5d
MT		 5337out_free_percpu:
5338 free_percpu(shared_msrs);
56c6d28a 5339out:
56c6d28a 5340 return r;
043405e1 5341}
8776e519 5342
f8c16bba
ZX		 5343void kvm_arch_exit(void)
5344{
ff9d07a0
ZY		 5345 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5346
888d256e
JK		 5347 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5348 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5349 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5350 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5351#ifdef CONFIG_X86_64
5352 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5353#endif
f8c16bba 5354 kvm_x86_ops = NULL;
56c6d28a 5355 kvm_mmu_module_exit();
013f6a5d 5356 free_percpu(shared_msrs);
56c6d28a 5357}
f8c16bba 5358
8776e519
HB		 5359int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5360{
5361 ++vcpu->stat.halt_exits;
5362 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 5363 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5364 return 1;
5365 } else {
5366 vcpu->run->exit_reason = KVM_EXIT_HLT;
5367 return 0;
5368 }
5369}
5370EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5371
55cd8e5a
GN		 5372int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5373{
5374 u64 param, ingpa, outgpa, ret;
5375 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5376 bool fast, longmode;
5377 int cs_db, cs_l;
5378
5379 /*
5380 * hypercall generates UD from non zero cpl and real mode
5381 * per HYPER-V spec
5382 */
3eeb3288 5383 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 5384 kvm_queue_exception(vcpu, UD_VECTOR);
5385 return 0;
5386 }
5387
5388 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5389 longmode = is_long_mode(vcpu) && cs_l == 1;
5390
5391 if (!longmode) {
ccd46936
GN		 5392 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5393 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5394 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5395 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5396 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5397 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 5398 }
5399#ifdef CONFIG_X86_64
5400 else {
5401 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5402 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5403 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5404 }
5405#endif
5406
5407 code = param & 0xffff;
5408 fast = (param >> 16) & 0x1;
5409 rep_cnt = (param >> 32) & 0xfff;
5410 rep_idx = (param >> 48) & 0xfff;
5411
5412 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5413
c25bc163
GN		 5414 switch (code) {
5415 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5416 kvm_vcpu_on_spin(vcpu);
5417 break;
5418 default:
5419 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5420 break;
5421 }
55cd8e5a
GN		 5422
5423 ret = res | (((u64)rep_done & 0xfff) << 32);
5424 if (longmode) {
5425 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5426 } else {
5427 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5428 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5429 }
5430
5431 return 1;
5432}
5433
8776e519
HB		 5434int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5435{
5436 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 5437 int r = 1;
8776e519 5438
55cd8e5a
GN		 5439 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5440 return kvm_hv_hypercall(vcpu);
5441
5fdbf976
MT		 5442 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5443 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5444 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5445 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5446 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5447
229456fc 5448 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5449
8776e519
HB		 5450 if (!is_long_mode(vcpu)) {
5451 nr &= 0xFFFFFFFF;
5452 a0 &= 0xFFFFFFFF;
5453 a1 &= 0xFFFFFFFF;
5454 a2 &= 0xFFFFFFFF;
5455 a3 &= 0xFFFFFFFF;
5456 }
5457
07708c4a
JK		 5458 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5459 ret = -KVM_EPERM;
5460 goto out;
5461 }
5462
8776e519 5463 switch (nr) {
b93463aa
AK		 5464 case KVM_HC_VAPIC_POLL_IRQ:
5465 ret = 0;
5466 break;
8776e519
HB		 5467 default:
5468 ret = -KVM_ENOSYS;
5469 break;
5470 }
07708c4a 5471out:
5fdbf976 5472 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5473 ++vcpu->stat.hypercalls;
2f333bcb 5474 return r;
8776e519
HB		 5475}
5476EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5477
b6785def 5478static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5479{
d6aa1000 5480 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5481 char instruction[3];
5fdbf976 5482 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5483
8776e519
HB		 5484 /*
5485 * Blow out the MMU to ensure that no other VCPU has an active mapping
5486 * to ensure that the updated hypercall appears atomically across all
5487 * VCPUs.
5488 */
5489 kvm_mmu_zap_all(vcpu->kvm);
5490
8776e519 5491 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5492
9d74191a 5493 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5494}
5495
b6c7a5dc
HB		 5496/*
5497 * Check if userspace requested an interrupt window, and that the
5498 * interrupt window is open.
5499 *
5500 * No need to exit to userspace if we already have an interrupt queued.
5501 */
851ba692 5502static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5503{
8061823a 5504 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5505 vcpu->run->request_interrupt_window &&
5df56646 5506 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5507}
5508
851ba692 5509static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5510{
851ba692
AK		 5511 struct kvm_run *kvm_run = vcpu->run;
5512
91586a3b 5513 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5514 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5515 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5516 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5517 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5518 else
b6c7a5dc 5519 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5520 kvm_arch_interrupt_allowed(vcpu) &&
5521 !kvm_cpu_has_interrupt(vcpu) &&
5522 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5523}
5524
4484141a 5525static int vapic_enter(struct kvm_vcpu *vcpu)
b93463aa
AK		 5526{
5527 struct kvm_lapic *apic = vcpu->arch.apic;
5528 struct page *page;
5529
5530 if (!apic || !apic->vapic_addr)
4484141a 5531 return 0;
b93463aa
AK		 5532
5533 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
4484141a
XG		 5534 if (is_error_page(page))
5535 return -EFAULT;
72dc67a6
IE		 5536
5537 vcpu->arch.apic->vapic_page = page;
4484141a 5538 return 0;
b93463aa
AK		 5539}
5540
5541static void vapic_exit(struct kvm_vcpu *vcpu)
5542{
5543 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 5544 int idx;
b93463aa
AK		 5545
5546 if (!apic || !apic->vapic_addr)
5547 return;
5548
f656ce01 5549 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 5550 kvm_release_page_dirty(apic->vapic_page);
5551 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 5552 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 5553}
5554
95ba8273
GN		 5555static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5556{
5557 int max_irr, tpr;
5558
5559 if (!kvm_x86_ops->update_cr8_intercept)
5560 return;
5561
88c808fd
AK		 5562 if (!vcpu->arch.apic)
5563 return;
5564
8db3baa2
GN		 5565 if (!vcpu->arch.apic->vapic_addr)
5566 max_irr = kvm_lapic_find_highest_irr(vcpu);
5567 else
5568 max_irr = -1;
95ba8273
GN		 5569
5570 if (max_irr != -1)
5571 max_irr >>= 4;
5572
5573 tpr = kvm_lapic_get_cr8(vcpu);
5574
5575 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5576}
5577
851ba692 5578static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 5579{
5580 /* try to reinject previous events if any */
b59bb7bd 5581 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5582 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5583 vcpu->arch.exception.has_error_code,
5584 vcpu->arch.exception.error_code);
b59bb7bd
GN		 5585 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5586 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5587 vcpu->arch.exception.error_code,
5588 vcpu->arch.exception.reinject);
b59bb7bd
GN		 5589 return;
5590 }
5591
95ba8273
GN		 5592 if (vcpu->arch.nmi_injected) {
5593 kvm_x86_ops->set_nmi(vcpu);
5594 return;
5595 }
5596
5597 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5598 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5599 return;
5600 }
5601
5602 /* try to inject new event if pending */
5603 if (vcpu->arch.nmi_pending) {
5604 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 5605 --vcpu->arch.nmi_pending;
95ba8273
GN		 5606 vcpu->arch.nmi_injected = true;
5607 kvm_x86_ops->set_nmi(vcpu);
5608 }
c7c9c56c 5609 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
95ba8273 5610 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5611 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5612 false);
5613 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5614 }
5615 }
5616}
5617
2acf923e
DC		 5618static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
5619{
5620 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
5621 !vcpu->guest_xcr0_loaded) {
5622 /* kvm_set_xcr() also depends on this */
5623 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
5624 vcpu->guest_xcr0_loaded = 1;
5625 }
5626}
5627
5628static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
5629{
5630 if (vcpu->guest_xcr0_loaded) {
5631 if (vcpu->arch.xcr0 != host_xcr0)
5632 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
5633 vcpu->guest_xcr0_loaded = 0;
5634 }
5635}
5636
7460fb4a
AK		 5637static void process_nmi(struct kvm_vcpu *vcpu)
5638{
5639 unsigned limit = 2;
5640
5641 /*
5642 * x86 is limited to one NMI running, and one NMI pending after it.
5643 * If an NMI is already in progress, limit further NMIs to just one.
5644 * Otherwise, allow two (and we'll inject the first one immediately).
5645 */
5646 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5647 limit = 1;
5648
5649 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5650 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5651 kvm_make_request(KVM_REQ_EVENT, vcpu);
5652}
5653
d828199e
MT		 5654static void kvm_gen_update_masterclock(struct kvm *kvm)
5655{
5656#ifdef CONFIG_X86_64
5657 int i;
5658 struct kvm_vcpu *vcpu;
5659 struct kvm_arch *ka = &kvm->arch;
5660
5661 spin_lock(&ka->pvclock_gtod_sync_lock);
5662 kvm_make_mclock_inprogress_request(kvm);
5663 /* no guest entries from this point */
5664 pvclock_update_vm_gtod_copy(kvm);
5665
5666 kvm_for_each_vcpu(i, vcpu, kvm)
5667 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
5668
5669 /* guest entries allowed */
5670 kvm_for_each_vcpu(i, vcpu, kvm)
5671 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
5672
5673 spin_unlock(&ka->pvclock_gtod_sync_lock);
5674#endif
5675}
5676
3d81bc7e 5677static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c
YZ		 5678{
5679 u64 eoi_exit_bitmap[4];
cf9e65b7 5680 u32 tmr[8];
c7c9c56c 5681
3d81bc7e
YZ		 5682 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
5683 return;
5684
c7c9c56c 5685 memset(eoi_exit_bitmap, 0, 32);
cf9e65b7 5686 memset(tmr, 0, 32);
c7c9c56c 5687
cf9e65b7 5688 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
c7c9c56c 5689 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
cf9e65b7 5690 kvm_apic_update_tmr(vcpu, tmr);
c7c9c56c
YZ		 5691}
5692
851ba692 5693static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5694{
5695 int r;
6a8b1d13 5696 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5697 vcpu->run->request_interrupt_window;
730dca42 5698 bool req_immediate_exit = false;
b6c7a5dc 5699
3e007509 5700 if (vcpu->requests) {
a8eeb04a 5701 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5702 kvm_mmu_unload(vcpu);
a8eeb04a 5703 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5704 __kvm_migrate_timers(vcpu);
d828199e
MT		 5705 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
5706 kvm_gen_update_masterclock(vcpu->kvm);
34c238a1
ZA		 5707 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5708 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 5709 if (unlikely(r))
5710 goto out;
5711 }
a8eeb04a 5712 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5713 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5714 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5715 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5716 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5717 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5718 r = 0;
5719 goto out;
5720 }
a8eeb04a 5721 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5722 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5723 r = 0;
5724 goto out;
5725 }
a8eeb04a 5726 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5727 vcpu->fpu_active = 0;
5728 kvm_x86_ops->fpu_deactivate(vcpu);
5729 }
af585b92
GN		 5730 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5731 /* Page is swapped out. Do synthetic halt */
5732 vcpu->arch.apf.halted = true;
5733 r = 1;
5734 goto out;
5735 }
c9aaa895
GC		 5736 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5737 record_steal_time(vcpu);
7460fb4a
AK		 5738 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5739 process_nmi(vcpu);
f5132b01
GN		 5740 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5741 kvm_handle_pmu_event(vcpu);
5742 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5743 kvm_deliver_pmi(vcpu);
3d81bc7e
YZ		 5744 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
5745 vcpu_scan_ioapic(vcpu);
2f52d58c 5746 }
b93463aa 5747
b463a6f7 5748 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 5749 kvm_apic_accept_events(vcpu);
5750 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
5751 r = 1;
5752 goto out;
5753 }
5754
b463a6f7
AK		 5755 inject_pending_event(vcpu);
5756
5757 /* enable NMI/IRQ window open exits if needed */
7460fb4a 5758 if (vcpu->arch.nmi_pending)
b463a6f7 5759 kvm_x86_ops->enable_nmi_window(vcpu);
c7c9c56c 5760 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
730dca42
JK		 5761 req_immediate_exit =
5762 kvm_x86_ops->enable_irq_window(vcpu) != 0;
b463a6f7
AK		 5763
5764 if (kvm_lapic_enabled(vcpu)) {
c7c9c56c
YZ		 5765 /*
5766 * Update architecture specific hints for APIC
5767 * virtual interrupt delivery.
5768 */
5769 if (kvm_x86_ops->hwapic_irr_update)
5770 kvm_x86_ops->hwapic_irr_update(vcpu,
5771 kvm_lapic_find_highest_irr(vcpu));
b463a6f7
AK		 5772 update_cr8_intercept(vcpu);
5773 kvm_lapic_sync_to_vapic(vcpu);
5774 }
5775 }
5776
d8368af8
AK		 5777 r = kvm_mmu_reload(vcpu);
5778 if (unlikely(r)) {
d905c069 5779 goto cancel_injection;
d8368af8
AK		 5780 }
5781
b6c7a5dc
HB		 5782 preempt_disable();
5783
5784 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 5785 if (vcpu->fpu_active)
5786 kvm_load_guest_fpu(vcpu);
2acf923e 5787 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 5788
6b7e2d09
XG		 5789 vcpu->mode = IN_GUEST_MODE;
5790
5791 /* We should set ->mode before check ->requests,
5792 * see the comment in make_all_cpus_request.
5793 */
5794 smp_mb();
b6c7a5dc 5795
d94e1dc9 5796 local_irq_disable();
32f88400 5797
6b7e2d09 5798 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 5799 || need_resched() || signal_pending(current)) {
6b7e2d09 5800 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5801 smp_wmb();
6c142801
AK		 5802 local_irq_enable();
5803 preempt_enable();
5804 r = 1;
d905c069 5805 goto cancel_injection;
6c142801
AK		 5806 }
5807
f656ce01 5808 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 5809
d6185f20
NHE		 5810 if (req_immediate_exit)
5811 smp_send_reschedule(vcpu->cpu);
5812
b6c7a5dc
HB		 5813 kvm_guest_enter();
5814
42dbaa5a 5815 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 5816 set_debugreg(0, 7);
5817 set_debugreg(vcpu->arch.eff_db[0], 0);
5818 set_debugreg(vcpu->arch.eff_db[1], 1);
5819 set_debugreg(vcpu->arch.eff_db[2], 2);
5820 set_debugreg(vcpu->arch.eff_db[3], 3);
5821 }
b6c7a5dc 5822
229456fc 5823 trace_kvm_entry(vcpu->vcpu_id);
851ba692 5824 kvm_x86_ops->run(vcpu);
b6c7a5dc 5825
24f1e32c
FW		 5826 /*
5827 * If the guest has used debug registers, at least dr7
5828 * will be disabled while returning to the host.
5829 * If we don't have active breakpoints in the host, we don't
5830 * care about the messed up debug address registers. But if
5831 * we have some of them active, restore the old state.
5832 */
59d8eb53 5833 if (hw_breakpoint_active())
24f1e32c 5834 hw_breakpoint_restore();
42dbaa5a 5835
886b470c
MT		 5836 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
5837 native_read_tsc());
1d5f066e 5838
6b7e2d09 5839 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5840 smp_wmb();
a547c6db
YZ		 5841
5842 /* Interrupt is enabled by handle_external_intr() */
5843 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 5844
5845 ++vcpu->stat.exits;
5846
5847 /*
5848 * We must have an instruction between local_irq_enable() and
5849 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5850 * the interrupt shadow. The stat.exits increment will do nicely.
5851 * But we need to prevent reordering, hence this barrier():
5852 */
5853 barrier();
5854
5855 kvm_guest_exit();
5856
5857 preempt_enable();
5858
f656ce01 5859 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 5860
b6c7a5dc
HB		 5861 /*
5862 * Profile KVM exit RIPs:
5863 */
5864 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 5865 unsigned long rip = kvm_rip_read(vcpu);
5866 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 5867 }
5868
cc578287
ZA		 5869 if (unlikely(vcpu->arch.tsc_always_catchup))
5870 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 5871
5cfb1d5a
MT		 5872 if (vcpu->arch.apic_attention)
5873 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 5874
851ba692 5875 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 5876 return r;
5877
5878cancel_injection:
5879 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 5880 if (unlikely(vcpu->arch.apic_attention))
5881 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 5882out:
5883 return r;
5884}
b6c7a5dc 5885
09cec754 5886
851ba692 5887static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 5888{
5889 int r;
f656ce01 5890 struct kvm *kvm = vcpu->kvm;
d7690175 5891
f656ce01 5892 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
4484141a
XG		 5893 r = vapic_enter(vcpu);
5894 if (r) {
5895 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5896 return r;
5897 }
d7690175
MT		 5898
5899 r = 1;
5900 while (r > 0) {
af585b92
GN		 5901 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
5902 !vcpu->arch.apf.halted)
851ba692 5903 r = vcpu_enter_guest(vcpu);
d7690175 5904 else {
f656ce01 5905 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 5906 kvm_vcpu_block(vcpu);
f656ce01 5907 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
66450a21
JK		 5908 if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) {
5909 kvm_apic_accept_events(vcpu);
09cec754
GN		 5910 switch(vcpu->arch.mp_state) {
5911 case KVM_MP_STATE_HALTED:
d7690175 5912 vcpu->arch.mp_state =
09cec754
GN		 5913 KVM_MP_STATE_RUNNABLE;
5914 case KVM_MP_STATE_RUNNABLE:
af585b92 5915 vcpu->arch.apf.halted = false;
09cec754 5916 break;
66450a21
JK		 5917 case KVM_MP_STATE_INIT_RECEIVED:
5918 break;
09cec754
GN		 5919 default:
5920 r = -EINTR;
5921 break;
5922 }
5923 }
d7690175
MT		 5924 }
5925
09cec754
GN		 5926 if (r <= 0)
5927 break;
5928
5929 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5930 if (kvm_cpu_has_pending_timer(vcpu))
5931 kvm_inject_pending_timer_irqs(vcpu);
5932
851ba692 5933 if (dm_request_for_irq_injection(vcpu)) {
09cec754 5934 r = -EINTR;
851ba692 5935 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5936 ++vcpu->stat.request_irq_exits;
5937 }
af585b92
GN		 5938
5939 kvm_check_async_pf_completion(vcpu);
5940
09cec754
GN		 5941 if (signal_pending(current)) {
5942 r = -EINTR;
851ba692 5943 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5944 ++vcpu->stat.signal_exits;
5945 }
5946 if (need_resched()) {
f656ce01 5947 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 5948 kvm_resched(vcpu);
f656ce01 5949 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 5950 }
b6c7a5dc
HB		 5951 }
5952
f656ce01 5953 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 5954
b93463aa
AK		 5955 vapic_exit(vcpu);
5956
b6c7a5dc
HB		 5957 return r;
5958}
5959
716d51ab
GN		 5960static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
5961{
5962 int r;
5963 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5964 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
5965 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5966 if (r != EMULATE_DONE)
5967 return 0;
5968 return 1;
5969}
5970
5971static int complete_emulated_pio(struct kvm_vcpu *vcpu)
5972{
5973 BUG_ON(!vcpu->arch.pio.count);
5974
5975 return complete_emulated_io(vcpu);
5976}
5977
f78146b0
AK		 5978/*
5979 * Implements the following, as a state machine:
5980 *
5981 * read:
5982 * for each fragment
87da7e66
XG		 5983 * for each mmio piece in the fragment
5984 * write gpa, len
5985 * exit
5986 * copy data
f78146b0
AK		 5987 * execute insn
5988 *
5989 * write:
5990 * for each fragment
87da7e66
XG		 5991 * for each mmio piece in the fragment
5992 * write gpa, len
5993 * copy data
5994 * exit
f78146b0 5995 */
716d51ab 5996static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 5997{
5998 struct kvm_run *run = vcpu->run;
f78146b0 5999 struct kvm_mmio_fragment *frag;
87da7e66 6000 unsigned len;
5287f194 6001
716d51ab 6002 BUG_ON(!vcpu->mmio_needed);
5287f194 6003
716d51ab 6004 /* Complete previous fragment */
87da7e66
XG		 6005 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6006 len = min(8u, frag->len);
716d51ab 6007 if (!vcpu->mmio_is_write)
87da7e66
XG		 6008 memcpy(frag->data, run->mmio.data, len);
6009
6010 if (frag->len <= 8) {
6011 /* Switch to the next fragment. */
6012 frag++;
6013 vcpu->mmio_cur_fragment++;
6014 } else {
6015 /* Go forward to the next mmio piece. */
6016 frag->data += len;
6017 frag->gpa += len;
6018 frag->len -= len;
6019 }
6020
716d51ab
GN		 6021 if (vcpu->mmio_cur_fragment == vcpu->mmio_nr_fragments) {
6022 vcpu->mmio_needed = 0;
cef4dea0 6023 if (vcpu->mmio_is_write)
716d51ab
GN		 6024 return 1;
6025 vcpu->mmio_read_completed = 1;
6026 return complete_emulated_io(vcpu);
6027 }
87da7e66 6028
716d51ab
GN		 6029 run->exit_reason = KVM_EXIT_MMIO;
6030 run->mmio.phys_addr = frag->gpa;
6031 if (vcpu->mmio_is_write)
87da7e66
XG		 6032 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6033 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6034 run->mmio.is_write = vcpu->mmio_is_write;
6035 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6036 return 0;
5287f194
AK		 6037}
6038
716d51ab 6039
b6c7a5dc
HB		 6040int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6041{
6042 int r;
6043 sigset_t sigsaved;
6044
e5c30142
AK		 6045 if (!tsk_used_math(current) && init_fpu(current))
6046 return -ENOMEM;
6047
ac9f6dc0
AK		 6048 if (vcpu->sigset_active)
6049 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6050
a4535290 6051 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6052 kvm_vcpu_block(vcpu);
66450a21 6053 kvm_apic_accept_events(vcpu);
d7690175 6054 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6055 r = -EAGAIN;
6056 goto out;
b6c7a5dc
HB		 6057 }
6058
b6c7a5dc 6059 /* re-sync apic's tpr */
eea1cff9
AP		 6060 if (!irqchip_in_kernel(vcpu->kvm)) {
6061 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6062 r = -EINVAL;
6063 goto out;
6064 }
6065 }
b6c7a5dc 6066
716d51ab
GN		 6067 if (unlikely(vcpu->arch.complete_userspace_io)) {
6068 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6069 vcpu->arch.complete_userspace_io = NULL;
6070 r = cui(vcpu);
6071 if (r <= 0)
6072 goto out;
6073 } else
6074 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6075
851ba692 6076 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 6077
6078out:
f1d86e46 6079 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6080 if (vcpu->sigset_active)
6081 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6082
b6c7a5dc
HB		 6083 return r;
6084}
6085
6086int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6087{
7ae441ea
GN		 6088 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6089 /*
6090 * We are here if userspace calls get_regs() in the middle of
6091 * instruction emulation. Registers state needs to be copied
4a969980 6092 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6093 * that usually, but some bad designed PV devices (vmware
6094 * backdoor interface) need this to work
6095 */
dd856efa 6096 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6097 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6098 }
5fdbf976
MT		 6099 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6100 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6101 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6102 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6103 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6104 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6105 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6106 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6107#ifdef CONFIG_X86_64
5fdbf976
MT		 6108 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6109 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6110 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6111 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6112 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6113 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6114 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6115 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6116#endif
6117
5fdbf976 6118 regs->rip = kvm_rip_read(vcpu);
91586a3b 6119 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6120
b6c7a5dc
HB		 6121 return 0;
6122}
6123
6124int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6125{
7ae441ea
GN		 6126 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6127 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6128
5fdbf976
MT		 6129 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6130 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6131 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6132 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6133 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6134 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6135 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6136 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6137#ifdef CONFIG_X86_64
5fdbf976
MT		 6138 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6139 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6140 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6141 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6142 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6143 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6144 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6145 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6146#endif
6147
5fdbf976 6148 kvm_rip_write(vcpu, regs->rip);
91586a3b 6149 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6150
b4f14abd
JK		 6151 vcpu->arch.exception.pending = false;
6152
3842d135
AK		 6153 kvm_make_request(KVM_REQ_EVENT, vcpu);
6154
b6c7a5dc
HB		 6155 return 0;
6156}
6157
b6c7a5dc
HB		 6158void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6159{
6160 struct kvm_segment cs;
6161
3e6e0aab 6162 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6163 *db = cs.db;
6164 *l = cs.l;
6165}
6166EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6167
6168int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6169 struct kvm_sregs *sregs)
6170{
89a27f4d 6171 struct desc_ptr dt;
b6c7a5dc 6172
3e6e0aab
GT		 6173 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6174 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6175 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6176 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6177 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6178 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6179
3e6e0aab
GT		 6180 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6181 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6182
6183 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6184 sregs->idt.limit = dt.size;
6185 sregs->idt.base = dt.address;
b6c7a5dc 6186 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6187 sregs->gdt.limit = dt.size;
6188 sregs->gdt.base = dt.address;
b6c7a5dc 6189
4d4ec087 6190 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6191 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6192 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6193 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6194 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6195 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6196 sregs->apic_base = kvm_get_apic_base(vcpu);
6197
923c61bb 6198 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6199
36752c9b 6200 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6201 set_bit(vcpu->arch.interrupt.nr,
6202 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6203
b6c7a5dc
HB		 6204 return 0;
6205}
6206
62d9f0db
MT		 6207int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6208 struct kvm_mp_state *mp_state)
6209{
66450a21 6210 kvm_apic_accept_events(vcpu);
62d9f0db 6211 mp_state->mp_state = vcpu->arch.mp_state;
62d9f0db
MT		 6212 return 0;
6213}
6214
6215int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6216 struct kvm_mp_state *mp_state)
6217{
66450a21
JK		 6218 if (!kvm_vcpu_has_lapic(vcpu) &&
6219 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6220 return -EINVAL;
6221
6222 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6223 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6224 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6225 } else
6226 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6227 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6228 return 0;
6229}
6230
7f3d35fd
KW		 6231int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6232 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 6233{
9d74191a 6234 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6235 int ret;
e01c2426 6236
8ec4722d 6237 init_emulate_ctxt(vcpu);
c697518a 6238
7f3d35fd 6239 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 6240 has_error_code, error_code);
c697518a 6241
c697518a 6242 if (ret)
19d04437 6243 return EMULATE_FAIL;
37817f29 6244
9d74191a
TY		 6245 kvm_rip_write(vcpu, ctxt->eip);
6246 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6247 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6248 return EMULATE_DONE;
37817f29
IE		 6249}
6250EXPORT_SYMBOL_GPL(kvm_task_switch);
6251
b6c7a5dc
HB		 6252int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6253 struct kvm_sregs *sregs)
6254{
6255 int mmu_reset_needed = 0;
63f42e02 6256 int pending_vec, max_bits, idx;
89a27f4d 6257 struct desc_ptr dt;
b6c7a5dc 6258
6d1068b3
PM		 6259 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6260 return -EINVAL;
6261
89a27f4d
GN		 6262 dt.size = sregs->idt.limit;
6263 dt.address = sregs->idt.base;
b6c7a5dc 6264 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 6265 dt.size = sregs->gdt.limit;
6266 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 6267 kvm_x86_ops->set_gdt(vcpu, &dt);
6268
ad312c7c 6269 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 6270 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 6271 vcpu->arch.cr3 = sregs->cr3;
aff48baa 6272 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 6273
2d3ad1f4 6274 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 6275
f6801dff 6276 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 6277 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 6278 kvm_set_apic_base(vcpu, sregs->apic_base);
6279
4d4ec087 6280 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 6281 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 6282 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 6283
fc78f519 6284 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 6285 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 6286 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 6287 kvm_update_cpuid(vcpu);
63f42e02
XG		 6288
6289 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 6290 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 6291 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 6292 mmu_reset_needed = 1;
6293 }
63f42e02 6294 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 6295
6296 if (mmu_reset_needed)
6297 kvm_mmu_reset_context(vcpu);
6298
a50abc3b 6299 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 6300 pending_vec = find_first_bit(
6301 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6302 if (pending_vec < max_bits) {
66fd3f7f 6303 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 6304 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 6305 }
6306
3e6e0aab
GT		 6307 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6308 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6309 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6310 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6311 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6312 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6313
3e6e0aab
GT		 6314 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6315 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 6316
5f0269f5
ME		 6317 update_cr8_intercept(vcpu);
6318
9c3e4aab 6319 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 6320 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 6321 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 6322 !is_protmode(vcpu))
9c3e4aab
MT		 6323 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6324
3842d135
AK		 6325 kvm_make_request(KVM_REQ_EVENT, vcpu);
6326
b6c7a5dc
HB		 6327 return 0;
6328}
6329
d0bfb940
JK		 6330int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6331 struct kvm_guest_debug *dbg)
b6c7a5dc 6332{
355be0b9 6333 unsigned long rflags;
ae675ef0 6334 int i, r;
b6c7a5dc 6335
4f926bf2
JK		 6336 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6337 r = -EBUSY;
6338 if (vcpu->arch.exception.pending)
2122ff5e 6339 goto out;
4f926bf2
JK		 6340 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6341 kvm_queue_exception(vcpu, DB_VECTOR);
6342 else
6343 kvm_queue_exception(vcpu, BP_VECTOR);
6344 }
6345
91586a3b
JK		 6346 /*
6347 * Read rflags as long as potentially injected trace flags are still
6348 * filtered out.
6349 */
6350 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 6351
6352 vcpu->guest_debug = dbg->control;
6353 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6354 vcpu->guest_debug = 0;
6355
6356 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 6357 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6358 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 6359 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 6360 } else {
6361 for (i = 0; i < KVM_NR_DB_REGS; i++)
6362 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 6363 }
c8639010 6364 kvm_update_dr7(vcpu);
ae675ef0 6365
f92653ee
JK		 6366 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6367 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6368 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 6369
91586a3b
JK		 6370 /*
6371 * Trigger an rflags update that will inject or remove the trace
6372 * flags.
6373 */
6374 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 6375
c8639010 6376 kvm_x86_ops->update_db_bp_intercept(vcpu);
b6c7a5dc 6377
4f926bf2 6378 r = 0;
d0bfb940 6379
2122ff5e 6380out:
b6c7a5dc
HB		 6381
6382 return r;
6383}
6384
8b006791
ZX		 6385/*
6386 * Translate a guest virtual address to a guest physical address.
6387 */
6388int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6389 struct kvm_translation *tr)
6390{
6391 unsigned long vaddr = tr->linear_address;
6392 gpa_t gpa;
f656ce01 6393 int idx;
8b006791 6394
f656ce01 6395 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 6396 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 6397 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 6398 tr->physical_address = gpa;
6399 tr->valid = gpa != UNMAPPED_GVA;
6400 tr->writeable = 1;
6401 tr->usermode = 0;
8b006791
ZX		 6402
6403 return 0;
6404}
6405
d0752060
HB		 6406int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6407{
98918833
SY		 6408 struct i387_fxsave_struct *fxsave =
6409 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6410
d0752060
HB		 6411 memcpy(fpu->fpr, fxsave->st_space, 128);
6412 fpu->fcw = fxsave->cwd;
6413 fpu->fsw = fxsave->swd;
6414 fpu->ftwx = fxsave->twd;
6415 fpu->last_opcode = fxsave->fop;
6416 fpu->last_ip = fxsave->rip;
6417 fpu->last_dp = fxsave->rdp;
6418 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6419
d0752060
HB		 6420 return 0;
6421}
6422
6423int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6424{
98918833
SY		 6425 struct i387_fxsave_struct *fxsave =
6426 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6427
d0752060
HB		 6428 memcpy(fxsave->st_space, fpu->fpr, 128);
6429 fxsave->cwd = fpu->fcw;
6430 fxsave->swd = fpu->fsw;
6431 fxsave->twd = fpu->ftwx;
6432 fxsave->fop = fpu->last_opcode;
6433 fxsave->rip = fpu->last_ip;
6434 fxsave->rdp = fpu->last_dp;
6435 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6436
d0752060
HB		 6437 return 0;
6438}
6439
10ab25cd 6440int fx_init(struct kvm_vcpu *vcpu)
d0752060 6441{
10ab25cd
JK		 6442 int err;
6443
6444 err = fpu_alloc(&vcpu->arch.guest_fpu);
6445 if (err)
6446 return err;
6447
98918833 6448 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 6449
2acf923e
DC		 6450 /*
6451 * Ensure guest xcr0 is valid for loading
6452 */
6453 vcpu->arch.xcr0 = XSTATE_FP;
6454
ad312c7c 6455 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 6456
6457 return 0;
d0752060
HB		 6458}
6459EXPORT_SYMBOL_GPL(fx_init);
6460
98918833
SY		 6461static void fx_free(struct kvm_vcpu *vcpu)
6462{
6463 fpu_free(&vcpu->arch.guest_fpu);
6464}
6465
d0752060
HB		 6466void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6467{
2608d7a1 6468 if (vcpu->guest_fpu_loaded)
d0752060
HB		 6469 return;
6470
2acf923e
DC		 6471 /*
6472 * Restore all possible states in the guest,
6473 * and assume host would use all available bits.
6474 * Guest xcr0 would be loaded later.
6475 */
6476 kvm_put_guest_xcr0(vcpu);
d0752060 6477 vcpu->guest_fpu_loaded = 1;
b1a74bf8 6478 __kernel_fpu_begin();
98918833 6479 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 6480 trace_kvm_fpu(1);
d0752060 6481}
d0752060
HB		 6482
6483void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6484{
2acf923e
DC		 6485 kvm_put_guest_xcr0(vcpu);
6486
d0752060
HB		 6487 if (!vcpu->guest_fpu_loaded)
6488 return;
6489
6490 vcpu->guest_fpu_loaded = 0;
98918833 6491 fpu_save_init(&vcpu->arch.guest_fpu);
b1a74bf8 6492 __kernel_fpu_end();
f096ed85 6493 ++vcpu->stat.fpu_reload;
a8eeb04a 6494 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 6495 trace_kvm_fpu(0);
d0752060 6496}
e9b11c17
ZX		 6497
6498void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6499{
12f9a48f 6500 kvmclock_reset(vcpu);
7f1ea208 6501
f5f48ee1 6502 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 6503 fx_free(vcpu);
e9b11c17
ZX		 6504 kvm_x86_ops->vcpu_free(vcpu);
6505}
6506
6507struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6508 unsigned int id)
6509{
6755bae8
ZA		 6510 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6511 printk_once(KERN_WARNING
6512 "kvm: SMP vm created on host with unstable TSC; "
6513 "guest TSC will not be reliable\n");
26e5215f
AK		 6514 return kvm_x86_ops->vcpu_create(kvm, id);
6515}
e9b11c17 6516
26e5215f
AK		 6517int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6518{
6519 int r;
e9b11c17 6520
0bed3b56 6521 vcpu->arch.mtrr_state.have_fixed = 1;
9fc77441
MT		 6522 r = vcpu_load(vcpu);
6523 if (r)
6524 return r;
57f252f2
JK		 6525 kvm_vcpu_reset(vcpu);
6526 r = kvm_mmu_setup(vcpu);
e9b11c17 6527 vcpu_put(vcpu);
e9b11c17 6528
26e5215f 6529 return r;
e9b11c17
ZX		 6530}
6531
42897d86
MT		 6532int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
6533{
6534 int r;
8fe8ab46 6535 struct msr_data msr;
42897d86
MT		 6536
6537 r = vcpu_load(vcpu);
6538 if (r)
6539 return r;
8fe8ab46
WA		 6540 msr.data = 0x0;
6541 msr.index = MSR_IA32_TSC;
6542 msr.host_initiated = true;
6543 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 6544 vcpu_put(vcpu);
6545
6546 return r;
6547}
6548
d40ccc62 6549void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 6550{
9fc77441 6551 int r;
344d9588
GN		 6552 vcpu->arch.apf.msr_val = 0;
6553
9fc77441
MT		 6554 r = vcpu_load(vcpu);
6555 BUG_ON(r);
e9b11c17
ZX		 6556 kvm_mmu_unload(vcpu);
6557 vcpu_put(vcpu);
6558
98918833 6559 fx_free(vcpu);
e9b11c17
ZX		 6560 kvm_x86_ops->vcpu_free(vcpu);
6561}
6562
66450a21 6563void kvm_vcpu_reset(struct kvm_vcpu *vcpu)
e9b11c17 6564{
7460fb4a
AK		 6565 atomic_set(&vcpu->arch.nmi_queued, 0);
6566 vcpu->arch.nmi_pending = 0;
448fa4a9
JK		 6567 vcpu->arch.nmi_injected = false;
6568
42dbaa5a
JK		 6569 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6570 vcpu->arch.dr6 = DR6_FIXED_1;
6571 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 6572 kvm_update_dr7(vcpu);
42dbaa5a 6573
3842d135 6574 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 6575 vcpu->arch.apf.msr_val = 0;
c9aaa895 6576 vcpu->arch.st.msr_val = 0;
3842d135 6577
12f9a48f
GC		 6578 kvmclock_reset(vcpu);
6579
af585b92
GN		 6580 kvm_clear_async_pf_completion_queue(vcpu);
6581 kvm_async_pf_hash_reset(vcpu);
6582 vcpu->arch.apf.halted = false;
3842d135 6583
f5132b01
GN		 6584 kvm_pmu_reset(vcpu);
6585
66f7b72e
JS		 6586 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
6587 vcpu->arch.regs_avail = ~0;
6588 vcpu->arch.regs_dirty = ~0;
6589
57f252f2 6590 kvm_x86_ops->vcpu_reset(vcpu);
e9b11c17
ZX		 6591}
6592
66450a21
JK		 6593void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, unsigned int vector)
6594{
6595 struct kvm_segment cs;
6596
6597 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6598 cs.selector = vector << 8;
6599 cs.base = vector << 12;
6600 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6601 kvm_rip_write(vcpu, 0);
6602}
6603
10474ae8 6604int kvm_arch_hardware_enable(void *garbage)
e9b11c17 6605{
ca84d1a2
ZA		 6606 struct kvm *kvm;
6607 struct kvm_vcpu *vcpu;
6608 int i;
0dd6a6ed
ZA		 6609 int ret;
6610 u64 local_tsc;
6611 u64 max_tsc = 0;
6612 bool stable, backwards_tsc = false;
18863bdd
AK		 6613
6614 kvm_shared_msr_cpu_online();
0dd6a6ed
ZA		 6615 ret = kvm_x86_ops->hardware_enable(garbage);
6616 if (ret != 0)
6617 return ret;
6618
6619 local_tsc = native_read_tsc();
6620 stable = !check_tsc_unstable();
6621 list_for_each_entry(kvm, &vm_list, vm_list) {
6622 kvm_for_each_vcpu(i, vcpu, kvm) {
6623 if (!stable && vcpu->cpu == smp_processor_id())
6624 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6625 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6626 backwards_tsc = true;
6627 if (vcpu->arch.last_host_tsc > max_tsc)
6628 max_tsc = vcpu->arch.last_host_tsc;
6629 }
6630 }
6631 }
6632
6633 /*
6634 * Sometimes, even reliable TSCs go backwards. This happens on
6635 * platforms that reset TSC during suspend or hibernate actions, but
6636 * maintain synchronization. We must compensate. Fortunately, we can
6637 * detect that condition here, which happens early in CPU bringup,
6638 * before any KVM threads can be running. Unfortunately, we can't
6639 * bring the TSCs fully up to date with real time, as we aren't yet far
6640 * enough into CPU bringup that we know how much real time has actually
6641 * elapsed; our helper function, get_kernel_ns() will be using boot
6642 * variables that haven't been updated yet.
6643 *
6644 * So we simply find the maximum observed TSC above, then record the
6645 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
6646 * the adjustment will be applied. Note that we accumulate
6647 * adjustments, in case multiple suspend cycles happen before some VCPU
6648 * gets a chance to run again. In the event that no KVM threads get a
6649 * chance to run, we will miss the entire elapsed period, as we'll have
6650 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6651 * loose cycle time. This isn't too big a deal, since the loss will be
6652 * uniform across all VCPUs (not to mention the scenario is extremely
6653 * unlikely). It is possible that a second hibernate recovery happens
6654 * much faster than a first, causing the observed TSC here to be
6655 * smaller; this would require additional padding adjustment, which is
6656 * why we set last_host_tsc to the local tsc observed here.
6657 *
6658 * N.B. - this code below runs only on platforms with reliable TSC,
6659 * as that is the only way backwards_tsc is set above. Also note
6660 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
6661 * have the same delta_cyc adjustment applied if backwards_tsc
6662 * is detected. Note further, this adjustment is only done once,
6663 * as we reset last_host_tsc on all VCPUs to stop this from being
6664 * called multiple times (one for each physical CPU bringup).
6665 *
4a969980 6666 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 6667 * will be compensated by the logic in vcpu_load, which sets the TSC to
6668 * catchup mode. This will catchup all VCPUs to real time, but cannot
6669 * guarantee that they stay in perfect synchronization.
6670 */
6671 if (backwards_tsc) {
6672 u64 delta_cyc = max_tsc - local_tsc;
6673 list_for_each_entry(kvm, &vm_list, vm_list) {
6674 kvm_for_each_vcpu(i, vcpu, kvm) {
6675 vcpu->arch.tsc_offset_adjustment += delta_cyc;
6676 vcpu->arch.last_host_tsc = local_tsc;
d828199e
MT		 6677 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
6678 &vcpu->requests);
0dd6a6ed
ZA		 6679 }
6680
6681 /*
6682 * We have to disable TSC offset matching.. if you were
6683 * booting a VM while issuing an S4 host suspend....
6684 * you may have some problem. Solving this issue is
6685 * left as an exercise to the reader.
6686 */
6687 kvm->arch.last_tsc_nsec = 0;
6688 kvm->arch.last_tsc_write = 0;
6689 }
6690
6691 }
6692 return 0;
e9b11c17
ZX		 6693}
6694
6695void kvm_arch_hardware_disable(void *garbage)
6696{
6697 kvm_x86_ops->hardware_disable(garbage);
3548bab5 6698 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 6699}
6700
6701int kvm_arch_hardware_setup(void)
6702{
6703 return kvm_x86_ops->hardware_setup();
6704}
6705
6706void kvm_arch_hardware_unsetup(void)
6707{
6708 kvm_x86_ops->hardware_unsetup();
6709}
6710
6711void kvm_arch_check_processor_compat(void *rtn)
6712{
6713 kvm_x86_ops->check_processor_compatibility(rtn);
6714}
6715
3e515705
AK		 6716bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
6717{
6718 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
6719}
6720
54e9818f
GN		 6721struct static_key kvm_no_apic_vcpu __read_mostly;
6722
e9b11c17
ZX		 6723int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6724{
6725 struct page *page;
6726 struct kvm *kvm;
6727 int r;
6728
6729 BUG_ON(vcpu->kvm == NULL);
6730 kvm = vcpu->kvm;
6731
9aabc88f 6732 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
c5af89b6 6733 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 6734 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 6735 else
a4535290 6736 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 6737
6738 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6739 if (!page) {
6740 r = -ENOMEM;
6741 goto fail;
6742 }
ad312c7c 6743 vcpu->arch.pio_data = page_address(page);
e9b11c17 6744
cc578287 6745 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 6746
e9b11c17
ZX		 6747 r = kvm_mmu_create(vcpu);
6748 if (r < 0)
6749 goto fail_free_pio_data;
6750
6751 if (irqchip_in_kernel(kvm)) {
6752 r = kvm_create_lapic(vcpu);
6753 if (r < 0)
6754 goto fail_mmu_destroy;
54e9818f
GN		 6755 } else
6756 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 6757
890ca9ae
HY		 6758 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6759 GFP_KERNEL);
6760 if (!vcpu->arch.mce_banks) {
6761 r = -ENOMEM;
443c39bc 6762 goto fail_free_lapic;
890ca9ae
HY		 6763 }
6764 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6765
f1797359
WY		 6766 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
6767 r = -ENOMEM;
f5f48ee1 6768 goto fail_free_mce_banks;
f1797359 6769 }
f5f48ee1 6770
66f7b72e
JS		 6771 r = fx_init(vcpu);
6772 if (r)
6773 goto fail_free_wbinvd_dirty_mask;
6774
ba904635 6775 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 6776 vcpu->arch.pv_time_enabled = false;
af585b92 6777 kvm_async_pf_hash_reset(vcpu);
f5132b01 6778 kvm_pmu_init(vcpu);
af585b92 6779
e9b11c17 6780 return 0;
66f7b72e
JS		 6781fail_free_wbinvd_dirty_mask:
6782 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 6783fail_free_mce_banks:
6784 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 6785fail_free_lapic:
6786 kvm_free_lapic(vcpu);
e9b11c17
ZX		 6787fail_mmu_destroy:
6788 kvm_mmu_destroy(vcpu);
6789fail_free_pio_data:
ad312c7c 6790 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 6791fail:
6792 return r;
6793}
6794
6795void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6796{
f656ce01
MT		 6797 int idx;
6798
f5132b01 6799 kvm_pmu_destroy(vcpu);
36cb93fd 6800 kfree(vcpu->arch.mce_banks);
e9b11c17 6801 kvm_free_lapic(vcpu);
f656ce01 6802 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 6803 kvm_mmu_destroy(vcpu);
f656ce01 6804 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 6805 free_page((unsigned long)vcpu->arch.pio_data);
54e9818f
GN		 6806 if (!irqchip_in_kernel(vcpu->kvm))
6807 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 6808}
d19a9cd2 6809
e08b9637 6810int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 6811{
e08b9637
CO		 6812 if (type)
6813 return -EINVAL;
6814
f05e70ac 6815 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 6816 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 6817
5550af4d
SY		 6818 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
6819 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 6820 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
6821 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
6822 &kvm->arch.irq_sources_bitmap);
5550af4d 6823
038f8c11 6824 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 6825 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 6826 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
6827
6828 pvclock_update_vm_gtod_copy(kvm);
53f658b3 6829
d89f5eff 6830 return 0;
d19a9cd2
ZX		 6831}
6832
6833static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
6834{
9fc77441
MT		 6835 int r;
6836 r = vcpu_load(vcpu);
6837 BUG_ON(r);
d19a9cd2
ZX		 6838 kvm_mmu_unload(vcpu);
6839 vcpu_put(vcpu);
6840}
6841
6842static void kvm_free_vcpus(struct kvm *kvm)
6843{
6844 unsigned int i;
988a2cae 6845 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 6846
6847 /*
6848 * Unpin any mmu pages first.
6849 */
af585b92
GN		 6850 kvm_for_each_vcpu(i, vcpu, kvm) {
6851 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 6852 kvm_unload_vcpu_mmu(vcpu);
af585b92 6853 }
988a2cae
GN		 6854 kvm_for_each_vcpu(i, vcpu, kvm)
6855 kvm_arch_vcpu_free(vcpu);
6856
6857 mutex_lock(&kvm->lock);
6858 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
6859 kvm->vcpus[i] = NULL;
d19a9cd2 6860
988a2cae
GN		 6861 atomic_set(&kvm->online_vcpus, 0);
6862 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 6863}
6864
ad8ba2cd
SY		 6865void kvm_arch_sync_events(struct kvm *kvm)
6866{
ba4cef31 6867 kvm_free_all_assigned_devices(kvm);
aea924f6 6868 kvm_free_pit(kvm);
ad8ba2cd
SY		 6869}
6870
d19a9cd2
ZX		 6871void kvm_arch_destroy_vm(struct kvm *kvm)
6872{
27469d29
AH		 6873 if (current->mm == kvm->mm) {
6874 /*
6875 * Free memory regions allocated on behalf of userspace,
6876 * unless the the memory map has changed due to process exit
6877 * or fd copying.
6878 */
6879 struct kvm_userspace_memory_region mem;
6880 memset(&mem, 0, sizeof(mem));
6881 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
6882 kvm_set_memory_region(kvm, &mem);
6883
6884 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
6885 kvm_set_memory_region(kvm, &mem);
6886
6887 mem.slot = TSS_PRIVATE_MEMSLOT;
6888 kvm_set_memory_region(kvm, &mem);
6889 }
6eb55818 6890 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 6891 kfree(kvm->arch.vpic);
6892 kfree(kvm->arch.vioapic);
d19a9cd2 6893 kvm_free_vcpus(kvm);
3d45830c
AK		 6894 if (kvm->arch.apic_access_page)
6895 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 6896 if (kvm->arch.ept_identity_pagetable)
6897 put_page(kvm->arch.ept_identity_pagetable);
1e08ec4a 6898 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 6899}
0de10343 6900
db3fe4eb
TY		 6901void kvm_arch_free_memslot(struct kvm_memory_slot *free,
6902 struct kvm_memory_slot *dont)
6903{
6904 int i;
6905
d89cc617
TY		 6906 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
6907 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
6908 kvm_kvfree(free->arch.rmap[i]);
6909 free->arch.rmap[i] = NULL;
77d11309 6910 }
d89cc617
TY		 6911 if (i == 0)
6912 continue;
6913
6914 if (!dont || free->arch.lpage_info[i - 1] !=
6915 dont->arch.lpage_info[i - 1]) {
6916 kvm_kvfree(free->arch.lpage_info[i - 1]);
6917 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 6918 }
6919 }
6920}
6921
6922int kvm_arch_create_memslot(struct kvm_memory_slot *slot, unsigned long npages)
6923{
6924 int i;
6925
d89cc617 6926 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 6927 unsigned long ugfn;
6928 int lpages;
d89cc617 6929 int level = i + 1;
db3fe4eb
TY		 6930
6931 lpages = gfn_to_index(slot->base_gfn + npages - 1,
6932 slot->base_gfn, level) + 1;
6933
d89cc617
TY		 6934 slot->arch.rmap[i] =
6935 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
6936 if (!slot->arch.rmap[i])
77d11309 6937 goto out_free;
d89cc617
TY		 6938 if (i == 0)
6939 continue;
77d11309 6940
d89cc617
TY		 6941 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
6942 sizeof(*slot->arch.lpage_info[i - 1]));
6943 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 6944 goto out_free;
6945
6946 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 6947 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 6948 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 6949 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 6950 ugfn = slot->userspace_addr >> PAGE_SHIFT;
6951 /*
6952 * If the gfn and userspace address are not aligned wrt each
6953 * other, or if explicitly asked to, disable large page
6954 * support for this slot
6955 */
6956 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
6957 !kvm_largepages_enabled()) {
6958 unsigned long j;
6959
6960 for (j = 0; j < lpages; ++j)
d89cc617 6961 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 6962 }
6963 }
6964
6965 return 0;
6966
6967out_free:
d89cc617
TY		 6968 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
6969 kvm_kvfree(slot->arch.rmap[i]);
6970 slot->arch.rmap[i] = NULL;
6971 if (i == 0)
6972 continue;
6973
6974 kvm_kvfree(slot->arch.lpage_info[i - 1]);
6975 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 6976 }
6977 return -ENOMEM;
6978}
6979
f7784b8e
MT		 6980int kvm_arch_prepare_memory_region(struct kvm *kvm,
6981 struct kvm_memory_slot *memslot,
7b6195a9
TY		 6982 struct kvm_userspace_memory_region *mem,
6983 enum kvm_mr_change change)
0de10343 6984{
7a905b14
TY		 6985 /*
6986 * Only private memory slots need to be mapped here since
6987 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
0de10343 6988 */
7b6195a9 6989 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7a905b14 6990 unsigned long userspace_addr;
604b38ac 6991
7a905b14
TY		 6992 /*
6993 * MAP_SHARED to prevent internal slot pages from being moved
6994 * by fork()/COW.
6995 */
7b6195a9 6996 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7a905b14
TY		 6997 PROT_READ | PROT_WRITE,
6998 MAP_SHARED | MAP_ANONYMOUS, 0);
0de10343 6999
7a905b14
TY		 7000 if (IS_ERR((void *)userspace_addr))
7001 return PTR_ERR((void *)userspace_addr);
604b38ac 7002
7a905b14 7003 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 7004 }
7005
f7784b8e
MT		 7006 return 0;
7007}
7008
7009void kvm_arch_commit_memory_region(struct kvm *kvm,
7010 struct kvm_userspace_memory_region *mem,
8482644a
TY		 7011 const struct kvm_memory_slot *old,
7012 enum kvm_mr_change change)
f7784b8e
MT		 7013{
7014
8482644a 7015 int nr_mmu_pages = 0;
f7784b8e 7016
8482644a 7017 if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) {
f7784b8e
MT		 7018 int ret;
7019
8482644a
TY		 7020 ret = vm_munmap(old->userspace_addr,
7021 old->npages * PAGE_SIZE);
f7784b8e
MT		 7022 if (ret < 0)
7023 printk(KERN_WARNING
7024 "kvm_vm_ioctl_set_memory_region: "
7025 "failed to munmap memory\n");
7026 }
7027
48c0e4e9
XG		 7028 if (!kvm->arch.n_requested_mmu_pages)
7029 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7030
48c0e4e9 7031 if (nr_mmu_pages)
0de10343 7032 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
c972f3b1
TY		 7033 /*
7034 * Write protect all pages for dirty logging.
7035 * Existing largepage mappings are destroyed here and new ones will
7036 * not be created until the end of the logging.
7037 */
8482644a 7038 if ((change != KVM_MR_DELETE) && (mem->flags & KVM_MEM_LOG_DIRTY_PAGES))
c972f3b1 7039 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
3b4dc3a0
MT		 7040 /*
7041 * If memory slot is created, or moved, we need to clear all
7042 * mmio sptes.
7043 */
8482644a 7044 if ((change == KVM_MR_CREATE) || (change == KVM_MR_MOVE)) {
982b3394 7045 kvm_mmu_zap_mmio_sptes(kvm);
3b4dc3a0
MT		 7046 kvm_reload_remote_mmus(kvm);
7047 }
0de10343 7048}
1d737c8a 7049
2df72e9b 7050void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f
MT		 7051{
7052 kvm_mmu_zap_all(kvm);
8986ecc0 7053 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 7054}
7055
2df72e9b
MT		 7056void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7057 struct kvm_memory_slot *slot)
7058{
7059 kvm_arch_flush_shadow_all(kvm);
7060}
7061
1d737c8a
ZX		 7062int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7063{
af585b92
GN		 7064 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7065 !vcpu->arch.apf.halted)
7066 || !list_empty_careful(&vcpu->async_pf.done)
66450a21 7067 || kvm_apic_has_events(vcpu)
7460fb4a 7068 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 7069 (kvm_arch_interrupt_allowed(vcpu) &&
7070 kvm_cpu_has_interrupt(vcpu));
1d737c8a 7071}
5736199a 7072
b6d33834 7073int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 7074{
b6d33834 7075 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 7076}
78646121
GN		 7077
7078int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7079{
7080 return kvm_x86_ops->interrupt_allowed(vcpu);
7081}
229456fc 7082
f92653ee
JK		 7083bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7084{
7085 unsigned long current_rip = kvm_rip_read(vcpu) +
7086 get_segment_base(vcpu, VCPU_SREG_CS);
7087
7088 return current_rip == linear_rip;
7089}
7090EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7091
94fe45da
JK		 7092unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7093{
7094 unsigned long rflags;
7095
7096 rflags = kvm_x86_ops->get_rflags(vcpu);
7097 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 7098 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 7099 return rflags;
7100}
7101EXPORT_SYMBOL_GPL(kvm_get_rflags);
7102
7103void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7104{
7105 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 7106 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 7107 rflags |= X86_EFLAGS_TF;
94fe45da 7108 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 7109 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 7110}
7111EXPORT_SYMBOL_GPL(kvm_set_rflags);
7112
56028d08
GN		 7113void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7114{
7115 int r;
7116
fb67e14f 7117 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
c4806acd 7118 is_error_page(work->page))
56028d08
GN		 7119 return;
7120
7121 r = kvm_mmu_reload(vcpu);
7122 if (unlikely(r))
7123 return;
7124
fb67e14f
XG		 7125 if (!vcpu->arch.mmu.direct_map &&
7126 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7127 return;
7128
56028d08
GN		 7129 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7130}
7131
af585b92
GN		 7132static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7133{
7134 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7135}
7136
7137static inline u32 kvm_async_pf_next_probe(u32 key)
7138{
7139 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7140}
7141
7142static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7143{
7144 u32 key = kvm_async_pf_hash_fn(gfn);
7145
7146 while (vcpu->arch.apf.gfns[key] != ~0)
7147 key = kvm_async_pf_next_probe(key);
7148
7149 vcpu->arch.apf.gfns[key] = gfn;
7150}
7151
7152static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7153{
7154 int i;
7155 u32 key = kvm_async_pf_hash_fn(gfn);
7156
7157 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 7158 (vcpu->arch.apf.gfns[key] != gfn &&
7159 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 7160 key = kvm_async_pf_next_probe(key);
7161
7162 return key;
7163}
7164
7165bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7166{
7167 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7168}
7169
7170static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7171{
7172 u32 i, j, k;
7173
7174 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7175 while (true) {
7176 vcpu->arch.apf.gfns[i] = ~0;
7177 do {
7178 j = kvm_async_pf_next_probe(j);
7179 if (vcpu->arch.apf.gfns[j] == ~0)
7180 return;
7181 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7182 /*
7183 * k lies cyclically in ]i,j]
7184 * | i.k.j |
7185 * |....j i.k.| or |.k..j i...|
7186 */
7187 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7188 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7189 i = j;
7190 }
7191}
7192
7c90705b
GN		 7193static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7194{
7195
7196 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7197 sizeof(val));
7198}
7199
af585b92
GN		 7200void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7201 struct kvm_async_pf *work)
7202{
6389ee94
AK		 7203 struct x86_exception fault;
7204
7c90705b 7205 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 7206 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 7207
7208 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 7209 (vcpu->arch.apf.send_user_only &&
7210 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 7211 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7212 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 7213 fault.vector = PF_VECTOR;
7214 fault.error_code_valid = true;
7215 fault.error_code = 0;
7216 fault.nested_page_fault = false;
7217 fault.address = work->arch.token;
7218 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7219 }
af585b92
GN		 7220}
7221
7222void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7223 struct kvm_async_pf *work)
7224{
6389ee94
AK		 7225 struct x86_exception fault;
7226
7c90705b
GN		 7227 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7228 if (is_error_page(work->page))
7229 work->arch.token = ~0; /* broadcast wakeup */
7230 else
7231 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7232
7233 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7234 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 7235 fault.vector = PF_VECTOR;
7236 fault.error_code_valid = true;
7237 fault.error_code = 0;
7238 fault.nested_page_fault = false;
7239 fault.address = work->arch.token;
7240 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7241 }
e6d53e3b 7242 vcpu->arch.apf.halted = false;
a4fa1635 7243 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 7244}
7245
7246bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7247{
7248 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7249 return true;
7250 else
7251 return !kvm_event_needs_reinjection(vcpu) &&
7252 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 7253}
7254
229456fc
MT		 7255EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7256EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7257EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7258EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7259EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 7260EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 7261EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 7262EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 7263EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 7264EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 7265EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 7266EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
kernel source for telekom puls (alcatel/mediatek)