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Merge tag 'v3.10.73' into update
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / radeon / r100.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <linux/seq_file.h>
5a0e3ad6 29#include <linux/slab.h>
760285e7
DH		 30#include <drm/drmP.h>
31#include <drm/radeon_drm.h>
771fe6b9
JG		 32#include "radeon_reg.h"
33#include "radeon.h"
e6990375 34#include "radeon_asic.h"
3ce0a23d 35#include "r100d.h"
d4550907
JG		 36#include "rs100d.h"
37#include "rv200d.h"
38#include "rv250d.h"
49e02b73 39#include "atom.h"
3ce0a23d 40
70967ab9
BH		 41#include <linux/firmware.h>
42#include <linux/platform_device.h>
e0cd3608 43#include <linux/module.h>
70967ab9 44
551ebd83
DA		 45#include "r100_reg_safe.h"
46#include "rn50_reg_safe.h"
47
70967ab9
BH		 48/* Firmware Names */
49#define FIRMWARE_R100 "radeon/R100_cp.bin"
50#define FIRMWARE_R200 "radeon/R200_cp.bin"
51#define FIRMWARE_R300 "radeon/R300_cp.bin"
52#define FIRMWARE_R420 "radeon/R420_cp.bin"
53#define FIRMWARE_RS690 "radeon/RS690_cp.bin"
54#define FIRMWARE_RS600 "radeon/RS600_cp.bin"
55#define FIRMWARE_R520 "radeon/R520_cp.bin"
56
57MODULE_FIRMWARE(FIRMWARE_R100);
58MODULE_FIRMWARE(FIRMWARE_R200);
59MODULE_FIRMWARE(FIRMWARE_R300);
60MODULE_FIRMWARE(FIRMWARE_R420);
61MODULE_FIRMWARE(FIRMWARE_RS690);
62MODULE_FIRMWARE(FIRMWARE_RS600);
63MODULE_FIRMWARE(FIRMWARE_R520);
771fe6b9 64
551ebd83
DA		 65#include "r100_track.h"
66
48ef779f
AD		 67/* This files gather functions specifics to:
68 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
69 * and others in some cases.
70 */
71
2b48b968
AD		 72static bool r100_is_in_vblank(struct radeon_device *rdev, int crtc)
73{
74 if (crtc == 0) {
75 if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR)
76 return true;
77 else
78 return false;
79 } else {
80 if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR)
81 return true;
82 else
83 return false;
84 }
85}
86
87static bool r100_is_counter_moving(struct radeon_device *rdev, int crtc)
88{
89 u32 vline1, vline2;
90
91 if (crtc == 0) {
92 vline1 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
93 vline2 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
94 } else {
95 vline1 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
96 vline2 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
97 }
98 if (vline1 != vline2)
99 return true;
100 else
101 return false;
102}
103
48ef779f
AD		 104/**
105 * r100_wait_for_vblank - vblank wait asic callback.
106 *
107 * @rdev: radeon_device pointer
108 * @crtc: crtc to wait for vblank on
109 *
110 * Wait for vblank on the requested crtc (r1xx-r4xx).
111 */
3ae19b75
AD		 112void r100_wait_for_vblank(struct radeon_device *rdev, int crtc)
113{
2b48b968 114 unsigned i = 0;
3ae19b75 115
94f768fd
AD		 116 if (crtc >= rdev->num_crtc)
117 return;
118
119 if (crtc == 0) {
2b48b968
AD		 120 if (!(RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN))
121 return;
3ae19b75 122 } else {
2b48b968
AD		 123 if (!(RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN))
124 return;
125 }
126
127 /* depending on when we hit vblank, we may be close to active; if so,
128 * wait for another frame.
129 */
130 while (r100_is_in_vblank(rdev, crtc)) {
131 if (i++ % 100 == 0) {
132 if (!r100_is_counter_moving(rdev, crtc))
133 break;
134 }
135 }
136
137 while (!r100_is_in_vblank(rdev, crtc)) {
138 if (i++ % 100 == 0) {
139 if (!r100_is_counter_moving(rdev, crtc))
140 break;
3ae19b75
AD		 141 }
142 }
143}
144
48ef779f
AD		 145/**
146 * r100_pre_page_flip - pre-pageflip callback.
147 *
148 * @rdev: radeon_device pointer
149 * @crtc: crtc to prepare for pageflip on
150 *
151 * Pre-pageflip callback (r1xx-r4xx).
152 * Enables the pageflip irq (vblank irq).
771fe6b9 153 */
6f34be50
AD		 154void r100_pre_page_flip(struct radeon_device *rdev, int crtc)
155{
6f34be50
AD		 156 /* enable the pflip int */
157 radeon_irq_kms_pflip_irq_get(rdev, crtc);
158}
159
48ef779f
AD		 160/**
161 * r100_post_page_flip - pos-pageflip callback.
162 *
163 * @rdev: radeon_device pointer
164 * @crtc: crtc to cleanup pageflip on
165 *
166 * Post-pageflip callback (r1xx-r4xx).
167 * Disables the pageflip irq (vblank irq).
168 */
6f34be50
AD		 169void r100_post_page_flip(struct radeon_device *rdev, int crtc)
170{
171 /* disable the pflip int */
172 radeon_irq_kms_pflip_irq_put(rdev, crtc);
173}
174
48ef779f
AD		 175/**
176 * r100_page_flip - pageflip callback.
177 *
178 * @rdev: radeon_device pointer
179 * @crtc_id: crtc to cleanup pageflip on
180 * @crtc_base: new address of the crtc (GPU MC address)
181 *
182 * Does the actual pageflip (r1xx-r4xx).
183 * During vblank we take the crtc lock and wait for the update_pending
184 * bit to go high, when it does, we release the lock, and allow the
185 * double buffered update to take place.
186 * Returns the current update pending status.
187 */
6f34be50
AD		 188u32 r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
189{
190 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
191 u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK;
f6496479 192 int i;
6f34be50
AD		 193
194 /* Lock the graphics update lock */
195 /* update the scanout addresses */
196 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
197
acb32506 198 /* Wait for update_pending to go high. */
f6496479
AD		 199 for (i = 0; i < rdev->usec_timeout; i++) {
200 if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET)
201 break;
202 udelay(1);
203 }
acb32506 204 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
6f34be50
AD		 205
206 /* Unlock the lock, so double-buffering can take place inside vblank */
207 tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK;
208 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
209
210 /* Return current update_pending status: */
211 return RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET;
212}
213
48ef779f
AD		 214/**
215 * r100_pm_get_dynpm_state - look up dynpm power state callback.
216 *
217 * @rdev: radeon_device pointer
218 *
219 * Look up the optimal power state based on the
220 * current state of the GPU (r1xx-r5xx).
221 * Used for dynpm only.
222 */
ce8f5370 223void r100_pm_get_dynpm_state(struct radeon_device *rdev)
a48b9b4e
AD		 224{
225 int i;
ce8f5370
AD		 226 rdev->pm.dynpm_can_upclock = true;
227 rdev->pm.dynpm_can_downclock = true;
a48b9b4e 228
ce8f5370
AD		 229 switch (rdev->pm.dynpm_planned_action) {
230 case DYNPM_ACTION_MINIMUM:
a48b9b4e 231 rdev->pm.requested_power_state_index = 0;
ce8f5370 232 rdev->pm.dynpm_can_downclock = false;
a48b9b4e 233 break;
ce8f5370 234 case DYNPM_ACTION_DOWNCLOCK:
a48b9b4e
AD		 235 if (rdev->pm.current_power_state_index == 0) {
236 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
ce8f5370 237 rdev->pm.dynpm_can_downclock = false;
a48b9b4e
AD		 238 } else {
239 if (rdev->pm.active_crtc_count > 1) {
240 for (i = 0; i < rdev->pm.num_power_states; i++) {
d7311171 241 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 242 continue;
243 else if (i >= rdev->pm.current_power_state_index) {
244 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
245 break;
246 } else {
247 rdev->pm.requested_power_state_index = i;
248 break;
249 }
250 }
251 } else
252 rdev->pm.requested_power_state_index =
253 rdev->pm.current_power_state_index - 1;
254 }
d7311171
AD		 255 /* don't use the power state if crtcs are active and no display flag is set */
256 if ((rdev->pm.active_crtc_count > 0) &&
257 (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags &
258 RADEON_PM_MODE_NO_DISPLAY)) {
259 rdev->pm.requested_power_state_index++;
260 }
a48b9b4e 261 break;
ce8f5370 262 case DYNPM_ACTION_UPCLOCK:
a48b9b4e
AD		 263 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
264 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
ce8f5370 265 rdev->pm.dynpm_can_upclock = false;
a48b9b4e
AD		 266 } else {
267 if (rdev->pm.active_crtc_count > 1) {
268 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
d7311171 269 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 270 continue;
271 else if (i <= rdev->pm.current_power_state_index) {
272 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
273 break;
274 } else {
275 rdev->pm.requested_power_state_index = i;
276 break;
277 }
278 }
279 } else
280 rdev->pm.requested_power_state_index =
281 rdev->pm.current_power_state_index + 1;
282 }
283 break;
ce8f5370 284 case DYNPM_ACTION_DEFAULT:
58e21dff 285 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
ce8f5370 286 rdev->pm.dynpm_can_upclock = false;
58e21dff 287 break;
ce8f5370 288 case DYNPM_ACTION_NONE:
a48b9b4e
AD		 289 default:
290 DRM_ERROR("Requested mode for not defined action\n");
291 return;
292 }
293 /* only one clock mode per power state */
294 rdev->pm.requested_clock_mode_index = 0;
295
d9fdaafb 296 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
ce8a3eb2
AD		 297 rdev->pm.power_state[rdev->pm.requested_power_state_index].
298 clock_info[rdev->pm.requested_clock_mode_index].sclk,
299 rdev->pm.power_state[rdev->pm.requested_power_state_index].
300 clock_info[rdev->pm.requested_clock_mode_index].mclk,
301 rdev->pm.power_state[rdev->pm.requested_power_state_index].
302 pcie_lanes);
a48b9b4e
AD		 303}
304
48ef779f
AD		 305/**
306 * r100_pm_init_profile - Initialize power profiles callback.
307 *
308 * @rdev: radeon_device pointer
309 *
310 * Initialize the power states used in profile mode
311 * (r1xx-r3xx).
312 * Used for profile mode only.
313 */
ce8f5370
AD		 314void r100_pm_init_profile(struct radeon_device *rdev)
315{
316 /* default */
317 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
318 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
319 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
320 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
321 /* low sh */
322 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
323 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
324 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
325 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 326 /* mid sh */
327 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
328 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
329 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
330 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 331 /* high sh */
332 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
333 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
334 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
335 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
336 /* low mh */
337 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
338 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
339 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
340 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 341 /* mid mh */
342 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
343 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
344 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
345 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 346 /* high mh */
347 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
348 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
349 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
350 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
bae6b562
AD		 351}
352
48ef779f
AD		 353/**
354 * r100_pm_misc - set additional pm hw parameters callback.
355 *
356 * @rdev: radeon_device pointer
357 *
358 * Set non-clock parameters associated with a power state
359 * (voltage, pcie lanes, etc.) (r1xx-r4xx).
360 */
49e02b73
AD		 361void r100_pm_misc(struct radeon_device *rdev)
362{
49e02b73
AD		 363 int requested_index = rdev->pm.requested_power_state_index;
364 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
365 struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
366 u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl;
367
368 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
369 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
370 tmp = RREG32(voltage->gpio.reg);
371 if (voltage->active_high)
372 tmp |= voltage->gpio.mask;
373 else
374 tmp &= ~(voltage->gpio.mask);
375 WREG32(voltage->gpio.reg, tmp);
376 if (voltage->delay)
377 udelay(voltage->delay);
378 } else {
379 tmp = RREG32(voltage->gpio.reg);
380 if (voltage->active_high)
381 tmp &= ~voltage->gpio.mask;
382 else
383 tmp |= voltage->gpio.mask;
384 WREG32(voltage->gpio.reg, tmp);
385 if (voltage->delay)
386 udelay(voltage->delay);
387 }
388 }
389
390 sclk_cntl = RREG32_PLL(SCLK_CNTL);
391 sclk_cntl2 = RREG32_PLL(SCLK_CNTL2);
392 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3);
393 sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL);
394 sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3);
395 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
396 sclk_more_cntl |= REDUCED_SPEED_SCLK_EN;
397 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE)
398 sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE;
399 else
400 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE;
401 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2)
402 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0);
403 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4)
404 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2);
405 } else
406 sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN;
407
408 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
409 sclk_more_cntl |= IO_CG_VOLTAGE_DROP;
410 if (voltage->delay) {
411 sclk_more_cntl |= VOLTAGE_DROP_SYNC;
412 switch (voltage->delay) {
413 case 33:
414 sclk_more_cntl |= VOLTAGE_DELAY_SEL(0);
415 break;
416 case 66:
417 sclk_more_cntl |= VOLTAGE_DELAY_SEL(1);
418 break;
419 case 99:
420 sclk_more_cntl |= VOLTAGE_DELAY_SEL(2);
421 break;
422 case 132:
423 sclk_more_cntl |= VOLTAGE_DELAY_SEL(3);
424 break;
425 }
426 } else
427 sclk_more_cntl &= ~VOLTAGE_DROP_SYNC;
428 } else
429 sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP;
430
431 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
432 sclk_cntl &= ~FORCE_HDP;
433 else
434 sclk_cntl |= FORCE_HDP;
435
436 WREG32_PLL(SCLK_CNTL, sclk_cntl);
437 WREG32_PLL(SCLK_CNTL2, sclk_cntl2);
438 WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl);
439
440 /* set pcie lanes */
441 if ((rdev->flags & RADEON_IS_PCIE) &&
442 !(rdev->flags & RADEON_IS_IGP) &&
798bcf73 443 rdev->asic->pm.set_pcie_lanes &&
49e02b73
AD		 444 (ps->pcie_lanes !=
445 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
446 radeon_set_pcie_lanes(rdev,
447 ps->pcie_lanes);
d9fdaafb 448 DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes);
49e02b73 449 }
49e02b73
AD		 450}
451
48ef779f
AD		 452/**
453 * r100_pm_prepare - pre-power state change callback.
454 *
455 * @rdev: radeon_device pointer
456 *
457 * Prepare for a power state change (r1xx-r4xx).
458 */
49e02b73
AD		 459void r100_pm_prepare(struct radeon_device *rdev)
460{
461 struct drm_device *ddev = rdev->ddev;
462 struct drm_crtc *crtc;
463 struct radeon_crtc *radeon_crtc;
464 u32 tmp;
465
466 /* disable any active CRTCs */
467 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
468 radeon_crtc = to_radeon_crtc(crtc);
469 if (radeon_crtc->enabled) {
470 if (radeon_crtc->crtc_id) {
471 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
472 tmp |= RADEON_CRTC2_DISP_REQ_EN_B;
473 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
474 } else {
475 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
476 tmp |= RADEON_CRTC_DISP_REQ_EN_B;
477 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
478 }
479 }
480 }
481}
482
48ef779f
AD		 483/**
484 * r100_pm_finish - post-power state change callback.
485 *
486 * @rdev: radeon_device pointer
487 *
488 * Clean up after a power state change (r1xx-r4xx).
489 */
49e02b73
AD		 490void r100_pm_finish(struct radeon_device *rdev)
491{
492 struct drm_device *ddev = rdev->ddev;
493 struct drm_crtc *crtc;
494 struct radeon_crtc *radeon_crtc;
495 u32 tmp;
496
497 /* enable any active CRTCs */
498 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
499 radeon_crtc = to_radeon_crtc(crtc);
500 if (radeon_crtc->enabled) {
501 if (radeon_crtc->crtc_id) {
502 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
503 tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B;
504 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
505 } else {
506 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
507 tmp &= ~RADEON_CRTC_DISP_REQ_EN_B;
508 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
509 }
510 }
511 }
512}
513
48ef779f
AD		 514/**
515 * r100_gui_idle - gui idle callback.
516 *
517 * @rdev: radeon_device pointer
518 *
519 * Check of the GUI (2D/3D engines) are idle (r1xx-r5xx).
520 * Returns true if idle, false if not.
521 */
def9ba9c
AD		 522bool r100_gui_idle(struct radeon_device *rdev)
523{
524 if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)
525 return false;
526 else
527 return true;
528}
529
05a05c50 530/* hpd for digital panel detect/disconnect */
48ef779f
AD		 531/**
532 * r100_hpd_sense - hpd sense callback.
533 *
534 * @rdev: radeon_device pointer
535 * @hpd: hpd (hotplug detect) pin
536 *
537 * Checks if a digital monitor is connected (r1xx-r4xx).
538 * Returns true if connected, false if not connected.
539 */
05a05c50
AD		 540bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
541{
542 bool connected = false;
543
544 switch (hpd) {
545 case RADEON_HPD_1:
546 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
547 connected = true;
548 break;
549 case RADEON_HPD_2:
550 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
551 connected = true;
552 break;
553 default:
554 break;
555 }
556 return connected;
557}
558
48ef779f
AD		 559/**
560 * r100_hpd_set_polarity - hpd set polarity callback.
561 *
562 * @rdev: radeon_device pointer
563 * @hpd: hpd (hotplug detect) pin
564 *
565 * Set the polarity of the hpd pin (r1xx-r4xx).
566 */
05a05c50
AD		 567void r100_hpd_set_polarity(struct radeon_device *rdev,
568 enum radeon_hpd_id hpd)
569{
570 u32 tmp;
571 bool connected = r100_hpd_sense(rdev, hpd);
572
573 switch (hpd) {
574 case RADEON_HPD_1:
575 tmp = RREG32(RADEON_FP_GEN_CNTL);
576 if (connected)
577 tmp &= ~RADEON_FP_DETECT_INT_POL;
578 else
579 tmp |= RADEON_FP_DETECT_INT_POL;
580 WREG32(RADEON_FP_GEN_CNTL, tmp);
581 break;
582 case RADEON_HPD_2:
583 tmp = RREG32(RADEON_FP2_GEN_CNTL);
584 if (connected)
585 tmp &= ~RADEON_FP2_DETECT_INT_POL;
586 else
587 tmp |= RADEON_FP2_DETECT_INT_POL;
588 WREG32(RADEON_FP2_GEN_CNTL, tmp);
589 break;
590 default:
591 break;
592 }
593}
594
48ef779f
AD		 595/**
596 * r100_hpd_init - hpd setup callback.
597 *
598 * @rdev: radeon_device pointer
599 *
600 * Setup the hpd pins used by the card (r1xx-r4xx).
601 * Set the polarity, and enable the hpd interrupts.
602 */
05a05c50
AD		 603void r100_hpd_init(struct radeon_device *rdev)
604{
605 struct drm_device *dev = rdev->ddev;
606 struct drm_connector *connector;
fb98257a 607 unsigned enable = 0;
05a05c50
AD		 608
609 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
610 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
fb98257a 611 enable |= 1 << radeon_connector->hpd.hpd;
64912e99 612 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
05a05c50 613 }
fb98257a 614 radeon_irq_kms_enable_hpd(rdev, enable);
05a05c50
AD		 615}
616
48ef779f
AD		 617/**
618 * r100_hpd_fini - hpd tear down callback.
619 *
620 * @rdev: radeon_device pointer
621 *
622 * Tear down the hpd pins used by the card (r1xx-r4xx).
623 * Disable the hpd interrupts.
624 */
05a05c50
AD		 625void r100_hpd_fini(struct radeon_device *rdev)
626{
627 struct drm_device *dev = rdev->ddev;
628 struct drm_connector *connector;
fb98257a 629 unsigned disable = 0;
05a05c50
AD		 630
631 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
632 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
fb98257a 633 disable |= 1 << radeon_connector->hpd.hpd;
05a05c50 634 }
fb98257a 635 radeon_irq_kms_disable_hpd(rdev, disable);
05a05c50
AD		 636}
637
771fe6b9
JG		 638/*
639 * PCI GART
640 */
641void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
642{
643 /* TODO: can we do somethings here ? */
644 /* It seems hw only cache one entry so we should discard this
645 * entry otherwise if first GPU GART read hit this entry it
646 * could end up in wrong address. */
647}
648
4aac0473 649int r100_pci_gart_init(struct radeon_device *rdev)
771fe6b9 650{
771fe6b9
JG		 651 int r;
652
c9a1be96 653 if (rdev->gart.ptr) {
fce7d61b 654 WARN(1, "R100 PCI GART already initialized\n");
4aac0473
JG		 655 return 0;
656 }
771fe6b9
JG		 657 /* Initialize common gart structure */
658 r = radeon_gart_init(rdev);
4aac0473 659 if (r)
771fe6b9 660 return r;
4aac0473 661 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
c5b3b850
AD		 662 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
663 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
4aac0473
JG		 664 return radeon_gart_table_ram_alloc(rdev);
665}
666
667int r100_pci_gart_enable(struct radeon_device *rdev)
668{
669 uint32_t tmp;
670
82568565 671 radeon_gart_restore(rdev);
771fe6b9
JG		 672 /* discard memory request outside of configured range */
673 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
674 WREG32(RADEON_AIC_CNTL, tmp);
675 /* set address range for PCI address translate */
d594e46a
JG		 676 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
677 WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
771fe6b9
JG		 678 /* set PCI GART page-table base address */
679 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
680 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
681 WREG32(RADEON_AIC_CNTL, tmp);
682 r100_pci_gart_tlb_flush(rdev);
43caf451 683 DRM_INFO("PCI GART of %uM enabled (table at 0x%016llX).\n",
fcf4de5a
TV		 684 (unsigned)(rdev->mc.gtt_size >> 20),
685 (unsigned long long)rdev->gart.table_addr);
771fe6b9
JG		 686 rdev->gart.ready = true;
687 return 0;
688}
689
690void r100_pci_gart_disable(struct radeon_device *rdev)
691{
692 uint32_t tmp;
693
694 /* discard memory request outside of configured range */
695 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
696 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
697 WREG32(RADEON_AIC_LO_ADDR, 0);
698 WREG32(RADEON_AIC_HI_ADDR, 0);
699}
700
701int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
702{
c9a1be96
JG		 703 u32 *gtt = rdev->gart.ptr;
704
771fe6b9
JG		 705 if (i < 0 || i > rdev->gart.num_gpu_pages) {
706 return -EINVAL;
707 }
c9a1be96 708 gtt[i] = cpu_to_le32(lower_32_bits(addr));
771fe6b9
JG		 709 return 0;
710}
711
4aac0473 712void r100_pci_gart_fini(struct radeon_device *rdev)
771fe6b9 713{
f9274562 714 radeon_gart_fini(rdev);
4aac0473
JG		 715 r100_pci_gart_disable(rdev);
716 radeon_gart_table_ram_free(rdev);
771fe6b9
JG		 717}
718
7ed220d7
MD		 719int r100_irq_set(struct radeon_device *rdev)
720{
721 uint32_t tmp = 0;
722
003e69f9 723 if (!rdev->irq.installed) {
fce7d61b 724 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
003e69f9
JG		 725 WREG32(R_000040_GEN_INT_CNTL, 0);
726 return -EINVAL;
727 }
736fc37f 728 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
7ed220d7
MD		 729 tmp |= RADEON_SW_INT_ENABLE;
730 }
6f34be50 731 if (rdev->irq.crtc_vblank_int[0] ||
736fc37f 732 atomic_read(&rdev->irq.pflip[0])) {
7ed220d7
MD		 733 tmp |= RADEON_CRTC_VBLANK_MASK;
734 }
6f34be50 735 if (rdev->irq.crtc_vblank_int[1] ||
736fc37f 736 atomic_read(&rdev->irq.pflip[1])) {
7ed220d7
MD		 737 tmp |= RADEON_CRTC2_VBLANK_MASK;
738 }
05a05c50
AD		 739 if (rdev->irq.hpd[0]) {
740 tmp |= RADEON_FP_DETECT_MASK;
741 }
742 if (rdev->irq.hpd[1]) {
743 tmp |= RADEON_FP2_DETECT_MASK;
744 }
7ed220d7 745 WREG32(RADEON_GEN_INT_CNTL, tmp);
a02db0f2
AD		 746
747 /* read back to post the write */
748 RREG32(RADEON_GEN_INT_CNTL);
749
7ed220d7
MD		 750 return 0;
751}
752
9f022ddf
JG		 753void r100_irq_disable(struct radeon_device *rdev)
754{
755 u32 tmp;
756
757 WREG32(R_000040_GEN_INT_CNTL, 0);
758 /* Wait and acknowledge irq */
759 mdelay(1);
760 tmp = RREG32(R_000044_GEN_INT_STATUS);
761 WREG32(R_000044_GEN_INT_STATUS, tmp);
762}
763
cbdd4501 764static uint32_t r100_irq_ack(struct radeon_device *rdev)
7ed220d7
MD		 765{
766 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
05a05c50
AD		 767 uint32_t irq_mask = RADEON_SW_INT_TEST |
768 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
769 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
7ed220d7
MD		 770
771 if (irqs) {
772 WREG32(RADEON_GEN_INT_STATUS, irqs);
773 }
774 return irqs & irq_mask;
775}
776
777int r100_irq_process(struct radeon_device *rdev)
778{
3e5cb98d 779 uint32_t status, msi_rearm;
d4877cf2 780 bool queue_hotplug = false;
7ed220d7
MD		 781
782 status = r100_irq_ack(rdev);
783 if (!status) {
784 return IRQ_NONE;
785 }
a513c184
JG		 786 if (rdev->shutdown) {
787 return IRQ_NONE;
788 }
7ed220d7
MD		 789 while (status) {
790 /* SW interrupt */
791 if (status & RADEON_SW_INT_TEST) {
7465280c 792 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
7ed220d7
MD		 793 }
794 /* Vertical blank interrupts */
795 if (status & RADEON_CRTC_VBLANK_STAT) {
6f34be50
AD		 796 if (rdev->irq.crtc_vblank_int[0]) {
797 drm_handle_vblank(rdev->ddev, 0);
798 rdev->pm.vblank_sync = true;
799 wake_up(&rdev->irq.vblank_queue);
800 }
736fc37f 801 if (atomic_read(&rdev->irq.pflip[0]))
3e4ea742 802 radeon_crtc_handle_flip(rdev, 0);
7ed220d7
MD		 803 }
804 if (status & RADEON_CRTC2_VBLANK_STAT) {
6f34be50
AD		 805 if (rdev->irq.crtc_vblank_int[1]) {
806 drm_handle_vblank(rdev->ddev, 1);
807 rdev->pm.vblank_sync = true;
808 wake_up(&rdev->irq.vblank_queue);
809 }
736fc37f 810 if (atomic_read(&rdev->irq.pflip[1]))
3e4ea742 811 radeon_crtc_handle_flip(rdev, 1);
7ed220d7 812 }
05a05c50 813 if (status & RADEON_FP_DETECT_STAT) {
d4877cf2
AD		 814 queue_hotplug = true;
815 DRM_DEBUG("HPD1\n");
05a05c50
AD		 816 }
817 if (status & RADEON_FP2_DETECT_STAT) {
d4877cf2
AD		 818 queue_hotplug = true;
819 DRM_DEBUG("HPD2\n");
05a05c50 820 }
7ed220d7
MD		 821 status = r100_irq_ack(rdev);
822 }
d4877cf2 823 if (queue_hotplug)
32c87fca 824 schedule_work(&rdev->hotplug_work);
3e5cb98d
AD		 825 if (rdev->msi_enabled) {
826 switch (rdev->family) {
827 case CHIP_RS400:
828 case CHIP_RS480:
829 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
830 WREG32(RADEON_AIC_CNTL, msi_rearm);
831 WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
832 break;
833 default:
b7f5b7de 834 WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN);
3e5cb98d
AD		 835 break;
836 }
837 }
7ed220d7
MD		 838 return IRQ_HANDLED;
839}
840
841u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
842{
843 if (crtc == 0)
844 return RREG32(RADEON_CRTC_CRNT_FRAME);
845 else
846 return RREG32(RADEON_CRTC2_CRNT_FRAME);
847}
848
9e5b2af7
PN		 849/* Who ever call radeon_fence_emit should call ring_lock and ask
850 * for enough space (today caller are ib schedule and buffer move) */
771fe6b9
JG		 851void r100_fence_ring_emit(struct radeon_device *rdev,
852 struct radeon_fence *fence)
853{
e32eb50d 854 struct radeon_ring *ring = &rdev->ring[fence->ring];
7b1f2485 855
9e5b2af7
PN		 856 /* We have to make sure that caches are flushed before
857 * CPU might read something from VRAM. */
e32eb50d
CK		 858 radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
859 radeon_ring_write(ring, RADEON_RB3D_DC_FLUSH_ALL);
860 radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
861 radeon_ring_write(ring, RADEON_RB3D_ZC_FLUSH_ALL);
771fe6b9 862 /* Wait until IDLE & CLEAN */
e32eb50d
CK		 863 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
864 radeon_ring_write(ring, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
865 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
866 radeon_ring_write(ring, rdev->config.r100.hdp_cntl |
cafe6609 867 RADEON_HDP_READ_BUFFER_INVALIDATE);
e32eb50d
CK		 868 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
869 radeon_ring_write(ring, rdev->config.r100.hdp_cntl);
771fe6b9 870 /* Emit fence sequence & fire IRQ */
e32eb50d
CK		 871 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
872 radeon_ring_write(ring, fence->seq);
873 radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0));
874 radeon_ring_write(ring, RADEON_SW_INT_FIRE);
771fe6b9
JG		 875}
876
15d3332f 877void r100_semaphore_ring_emit(struct radeon_device *rdev,
e32eb50d 878 struct radeon_ring *ring,
15d3332f 879 struct radeon_semaphore *semaphore,
7b1f2485 880 bool emit_wait)
15d3332f
CK		 881{
882 /* Unused on older asics, since we don't have semaphores or multiple rings */
883 BUG();
884}
885
771fe6b9
JG		 886int r100_copy_blit(struct radeon_device *rdev,
887 uint64_t src_offset,
888 uint64_t dst_offset,
003cefe0 889 unsigned num_gpu_pages,
876dc9f3 890 struct radeon_fence **fence)
771fe6b9 891{
e32eb50d 892 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
771fe6b9 893 uint32_t cur_pages;
003cefe0 894 uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE;
771fe6b9
JG		 895 uint32_t pitch;
896 uint32_t stride_pixels;
897 unsigned ndw;
898 int num_loops;
899 int r = 0;
900
901 /* radeon limited to 16k stride */
902 stride_bytes &= 0x3fff;
903 /* radeon pitch is /64 */
904 pitch = stride_bytes / 64;
905 stride_pixels = stride_bytes / 4;
003cefe0 906 num_loops = DIV_ROUND_UP(num_gpu_pages, 8191);
771fe6b9
JG		 907
908 /* Ask for enough room for blit + flush + fence */
909 ndw = 64 + (10 * num_loops);
e32eb50d 910 r = radeon_ring_lock(rdev, ring, ndw);
771fe6b9
JG		 911 if (r) {
912 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
913 return -EINVAL;
914 }
003cefe0
AD		 915 while (num_gpu_pages > 0) {
916 cur_pages = num_gpu_pages;
771fe6b9
JG		 917 if (cur_pages > 8191) {
918 cur_pages = 8191;
919 }
003cefe0 920 num_gpu_pages -= cur_pages;
771fe6b9
JG		 921
922 /* pages are in Y direction - height
923 page width in X direction - width */
e32eb50d
CK		 924 radeon_ring_write(ring, PACKET3(PACKET3_BITBLT_MULTI, 8));
925 radeon_ring_write(ring,
771fe6b9
JG		 926 RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
927 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
928 RADEON_GMC_SRC_CLIPPING |
929 RADEON_GMC_DST_CLIPPING |
930 RADEON_GMC_BRUSH_NONE |
931 (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
932 RADEON_GMC_SRC_DATATYPE_COLOR |
933 RADEON_ROP3_S |
934 RADEON_DP_SRC_SOURCE_MEMORY |
935 RADEON_GMC_CLR_CMP_CNTL_DIS |
936 RADEON_GMC_WR_MSK_DIS);
e32eb50d
CK		 937 radeon_ring_write(ring, (pitch << 22) | (src_offset >> 10));
938 radeon_ring_write(ring, (pitch << 22) | (dst_offset >> 10));
939 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
940 radeon_ring_write(ring, 0);
941 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
942 radeon_ring_write(ring, num_gpu_pages);
943 radeon_ring_write(ring, num_gpu_pages);
944 radeon_ring_write(ring, cur_pages | (stride_pixels << 16));
945 }
946 radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
947 radeon_ring_write(ring, RADEON_RB2D_DC_FLUSH_ALL);
948 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
949 radeon_ring_write(ring,
771fe6b9
JG		 950 RADEON_WAIT_2D_IDLECLEAN |
951 RADEON_WAIT_HOST_IDLECLEAN |
952 RADEON_WAIT_DMA_GUI_IDLE);
953 if (fence) {
876dc9f3 954 r = radeon_fence_emit(rdev, fence, RADEON_RING_TYPE_GFX_INDEX);
771fe6b9 955 }
e32eb50d 956 radeon_ring_unlock_commit(rdev, ring);
771fe6b9
JG		 957 return r;
958}
959
45600232
JG		 960static int r100_cp_wait_for_idle(struct radeon_device *rdev)
961{
962 unsigned i;
963 u32 tmp;
964
965 for (i = 0; i < rdev->usec_timeout; i++) {
966 tmp = RREG32(R_000E40_RBBM_STATUS);
967 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
968 return 0;
969 }
970 udelay(1);
971 }
972 return -1;
973}
974
f712812e 975void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)
771fe6b9
JG		 976{
977 int r;
978
e32eb50d 979 r = radeon_ring_lock(rdev, ring, 2);
771fe6b9
JG		 980 if (r) {
981 return;
982 }
e32eb50d
CK		 983 radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0));
984 radeon_ring_write(ring,
771fe6b9
JG		 985 RADEON_ISYNC_ANY2D_IDLE3D |
986 RADEON_ISYNC_ANY3D_IDLE2D |
987 RADEON_ISYNC_WAIT_IDLEGUI |
988 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
e32eb50d 989 radeon_ring_unlock_commit(rdev, ring);
771fe6b9
JG		 990}
991
70967ab9
BH		 992
993/* Load the microcode for the CP */
994static int r100_cp_init_microcode(struct radeon_device *rdev)
771fe6b9 995{
70967ab9
BH		 996 struct platform_device *pdev;
997 const char *fw_name = NULL;
998 int err;
771fe6b9 999
d9fdaafb 1000 DRM_DEBUG_KMS("\n");
771fe6b9 1001
70967ab9
BH		 1002 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
1003 err = IS_ERR(pdev);
1004 if (err) {
1005 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1006 return -EINVAL;
1007 }
771fe6b9
JG		 1008 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
1009 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
1010 (rdev->family == CHIP_RS200)) {
1011 DRM_INFO("Loading R100 Microcode\n");
70967ab9 1012 fw_name = FIRMWARE_R100;
771fe6b9
JG		 1013 } else if ((rdev->family == CHIP_R200) ||
1014 (rdev->family == CHIP_RV250) ||
1015 (rdev->family == CHIP_RV280) ||
1016 (rdev->family == CHIP_RS300)) {
1017 DRM_INFO("Loading R200 Microcode\n");
70967ab9 1018 fw_name = FIRMWARE_R200;
771fe6b9
JG		 1019 } else if ((rdev->family == CHIP_R300) ||
1020 (rdev->family == CHIP_R350) ||
1021 (rdev->family == CHIP_RV350) ||
1022 (rdev->family == CHIP_RV380) ||
1023 (rdev->family == CHIP_RS400) ||
1024 (rdev->family == CHIP_RS480)) {
1025 DRM_INFO("Loading R300 Microcode\n");
70967ab9 1026 fw_name = FIRMWARE_R300;
771fe6b9
JG		 1027 } else if ((rdev->family == CHIP_R420) ||
1028 (rdev->family == CHIP_R423) ||
1029 (rdev->family == CHIP_RV410)) {
1030 DRM_INFO("Loading R400 Microcode\n");
70967ab9 1031 fw_name = FIRMWARE_R420;
771fe6b9
JG		 1032 } else if ((rdev->family == CHIP_RS690) ||
1033 (rdev->family == CHIP_RS740)) {
1034 DRM_INFO("Loading RS690/RS740 Microcode\n");
70967ab9 1035 fw_name = FIRMWARE_RS690;
771fe6b9
JG		 1036 } else if (rdev->family == CHIP_RS600) {
1037 DRM_INFO("Loading RS600 Microcode\n");
70967ab9 1038 fw_name = FIRMWARE_RS600;
771fe6b9
JG		 1039 } else if ((rdev->family == CHIP_RV515) ||
1040 (rdev->family == CHIP_R520) ||
1041 (rdev->family == CHIP_RV530) ||
1042 (rdev->family == CHIP_R580) ||
1043 (rdev->family == CHIP_RV560) ||
1044 (rdev->family == CHIP_RV570)) {
1045 DRM_INFO("Loading R500 Microcode\n");
70967ab9
BH		 1046 fw_name = FIRMWARE_R520;
1047 }
1048
3ce0a23d 1049 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
70967ab9
BH		 1050 platform_device_unregister(pdev);
1051 if (err) {
1052 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
1053 fw_name);
3ce0a23d 1054 } else if (rdev->me_fw->size % 8) {
70967ab9
BH		 1055 printk(KERN_ERR
1056 "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
3ce0a23d 1057 rdev->me_fw->size, fw_name);
70967ab9 1058 err = -EINVAL;
3ce0a23d
JG		 1059 release_firmware(rdev->me_fw);
1060 rdev->me_fw = NULL;
70967ab9
BH		 1061 }
1062 return err;
1063}
d4550907 1064
70967ab9
BH		 1065static void r100_cp_load_microcode(struct radeon_device *rdev)
1066{
1067 const __be32 *fw_data;
1068 int i, size;
1069
1070 if (r100_gui_wait_for_idle(rdev)) {
1071 printk(KERN_WARNING "Failed to wait GUI idle while "
1072 "programming pipes. Bad things might happen.\n");
1073 }
1074
3ce0a23d
JG		 1075 if (rdev->me_fw) {
1076 size = rdev->me_fw->size / 4;
1077 fw_data = (const __be32 *)&rdev->me_fw->data[0];
70967ab9
BH		 1078 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
1079 for (i = 0; i < size; i += 2) {
1080 WREG32(RADEON_CP_ME_RAM_DATAH,
1081 be32_to_cpup(&fw_data[i]));
1082 WREG32(RADEON_CP_ME_RAM_DATAL,
1083 be32_to_cpup(&fw_data[i + 1]));
771fe6b9
JG		 1084 }
1085 }
1086}
1087
1088int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
1089{
e32eb50d 1090 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
771fe6b9
JG		 1091 unsigned rb_bufsz;
1092 unsigned rb_blksz;
1093 unsigned max_fetch;
1094 unsigned pre_write_timer;
1095 unsigned pre_write_limit;
1096 unsigned indirect2_start;
1097 unsigned indirect1_start;
1098 uint32_t tmp;
1099 int r;
1100
1101 if (r100_debugfs_cp_init(rdev)) {
1102 DRM_ERROR("Failed to register debugfs file for CP !\n");
1103 }
3ce0a23d 1104 if (!rdev->me_fw) {
70967ab9
BH		 1105 r = r100_cp_init_microcode(rdev);
1106 if (r) {
1107 DRM_ERROR("Failed to load firmware!\n");
1108 return r;
1109 }
1110 }
1111
771fe6b9
JG		 1112 /* Align ring size */
1113 rb_bufsz = drm_order(ring_size / 8);
1114 ring_size = (1 << (rb_bufsz + 1)) * 4;
1115 r100_cp_load_microcode(rdev);
e32eb50d 1116 r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET,
78c5560a
AD		 1117 RADEON_CP_RB_RPTR, RADEON_CP_RB_WPTR,
1118 0, 0x7fffff, RADEON_CP_PACKET2);
771fe6b9
JG		 1119 if (r) {
1120 return r;
1121 }
1122 /* Each time the cp read 1024 bytes (16 dword/quadword) update
1123 * the rptr copy in system ram */
1124 rb_blksz = 9;
1125 /* cp will read 128bytes at a time (4 dwords) */
1126 max_fetch = 1;
e32eb50d 1127 ring->align_mask = 16 - 1;
771fe6b9
JG		 1128 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
1129 pre_write_timer = 64;
1130 /* Force CP_RB_WPTR write if written more than one time before the
1131 * delay expire
1132 */
1133 pre_write_limit = 0;
1134 /* Setup the cp cache like this (cache size is 96 dwords) :
1135 * RING 0 to 15
1136 * INDIRECT1 16 to 79
1137 * INDIRECT2 80 to 95
1138 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1139 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
1140 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1141 * Idea being that most of the gpu cmd will be through indirect1 buffer
1142 * so it gets the bigger cache.
1143 */
1144 indirect2_start = 80;
1145 indirect1_start = 16;
1146 /* cp setup */
1147 WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
d6f28938 1148 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
771fe6b9 1149 REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
724c80e1 1150 REG_SET(RADEON_MAX_FETCH, max_fetch));
d6f28938
AD		 1151#ifdef __BIG_ENDIAN
1152 tmp |= RADEON_BUF_SWAP_32BIT;
1153#endif
724c80e1 1154 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE);
d6f28938 1155
771fe6b9 1156 /* Set ring address */
e32eb50d
CK		 1157 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)ring->gpu_addr);
1158 WREG32(RADEON_CP_RB_BASE, ring->gpu_addr);
771fe6b9 1159 /* Force read & write ptr to 0 */
724c80e1 1160 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE);
771fe6b9 1161 WREG32(RADEON_CP_RB_RPTR_WR, 0);
e32eb50d
CK		 1162 ring->wptr = 0;
1163 WREG32(RADEON_CP_RB_WPTR, ring->wptr);
724c80e1
AD		 1164
1165 /* set the wb address whether it's enabled or not */
1166 WREG32(R_00070C_CP_RB_RPTR_ADDR,
1167 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2));
1168 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET);
1169
1170 if (rdev->wb.enabled)
1171 WREG32(R_000770_SCRATCH_UMSK, 0xff);
1172 else {
1173 tmp |= RADEON_RB_NO_UPDATE;
1174 WREG32(R_000770_SCRATCH_UMSK, 0);
1175 }
1176
771fe6b9
JG		 1177 WREG32(RADEON_CP_RB_CNTL, tmp);
1178 udelay(10);
e32eb50d 1179 ring->rptr = RREG32(RADEON_CP_RB_RPTR);
771fe6b9
JG		 1180 /* Set cp mode to bus mastering & enable cp*/
1181 WREG32(RADEON_CP_CSQ_MODE,
1182 REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
1183 REG_SET(RADEON_INDIRECT1_START, indirect1_start));
d75ee3be
AD		 1184 WREG32(RADEON_CP_RB_WPTR_DELAY, 0);
1185 WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D);
771fe6b9 1186 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
2099810f
DA		 1187
1188 /* at this point everything should be setup correctly to enable master */
1189 pci_set_master(rdev->pdev);
1190
f712812e
AD		 1191 radeon_ring_start(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1192 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
771fe6b9
JG		 1193 if (r) {
1194 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
1195 return r;
1196 }
e32eb50d 1197 ring->ready = true;
53595338 1198 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
c7eff978 1199
16c58081
SK		 1200 if (!ring->rptr_save_reg /* not resuming from suspend */
1201 && radeon_ring_supports_scratch_reg(rdev, ring)) {
c7eff978
AD		 1202 r = radeon_scratch_get(rdev, &ring->rptr_save_reg);
1203 if (r) {
1204 DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r);
1205 ring->rptr_save_reg = 0;
1206 }
1207 }
771fe6b9
JG		 1208 return 0;
1209}
1210
1211void r100_cp_fini(struct radeon_device *rdev)
1212{
45600232
JG		 1213 if (r100_cp_wait_for_idle(rdev)) {
1214 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
1215 }
771fe6b9 1216 /* Disable ring */
a18d7ea1 1217 r100_cp_disable(rdev);
c7eff978 1218 radeon_scratch_free(rdev, rdev->ring[RADEON_RING_TYPE_GFX_INDEX].rptr_save_reg);
e32eb50d 1219 radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
771fe6b9
JG		 1220 DRM_INFO("radeon: cp finalized\n");
1221}
1222
1223void r100_cp_disable(struct radeon_device *rdev)
1224{
1225 /* Disable ring */
53595338 1226 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
e32eb50d 1227 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
771fe6b9
JG		 1228 WREG32(RADEON_CP_CSQ_MODE, 0);
1229 WREG32(RADEON_CP_CSQ_CNTL, 0);
724c80e1 1230 WREG32(R_000770_SCRATCH_UMSK, 0);
771fe6b9
JG		 1231 if (r100_gui_wait_for_idle(rdev)) {
1232 printk(KERN_WARNING "Failed to wait GUI idle while "
1233 "programming pipes. Bad things might happen.\n");
1234 }
1235}
1236
771fe6b9
JG		 1237/*
1238 * CS functions
1239 */
0242f74d
AD		 1240int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
1241 struct radeon_cs_packet *pkt,
1242 unsigned idx,
1243 unsigned reg)
1244{
1245 int r;
1246 u32 tile_flags = 0;
1247 u32 tmp;
1248 struct radeon_cs_reloc *reloc;
1249 u32 value;
1250
012e976d 1251 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
0242f74d
AD		 1252 if (r) {
1253 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1254 idx, reg);
c3ad63af 1255 radeon_cs_dump_packet(p, pkt);
0242f74d
AD		 1256 return r;
1257 }
1258
1259 value = radeon_get_ib_value(p, idx);
1260 tmp = value & 0x003fffff;
1261 tmp += (((u32)reloc->lobj.gpu_offset) >> 10);
1262
1263 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1264 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1265 tile_flags |= RADEON_DST_TILE_MACRO;
1266 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
1267 if (reg == RADEON_SRC_PITCH_OFFSET) {
1268 DRM_ERROR("Cannot src blit from microtiled surface\n");
c3ad63af 1269 radeon_cs_dump_packet(p, pkt);
0242f74d
AD		 1270 return -EINVAL;
1271 }
1272 tile_flags |= RADEON_DST_TILE_MICRO;
1273 }
1274
1275 tmp |= tile_flags;
1276 p->ib.ptr[idx] = (value & 0x3fc00000) | tmp;
1277 } else
1278 p->ib.ptr[idx] = (value & 0xffc00000) | tmp;
1279 return 0;
1280}
1281
1282int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
1283 struct radeon_cs_packet *pkt,
1284 int idx)
1285{
1286 unsigned c, i;
1287 struct radeon_cs_reloc *reloc;
1288 struct r100_cs_track *track;
1289 int r = 0;
1290 volatile uint32_t *ib;
1291 u32 idx_value;
1292
1293 ib = p->ib.ptr;
1294 track = (struct r100_cs_track *)p->track;
1295 c = radeon_get_ib_value(p, idx++) & 0x1F;
1296 if (c > 16) {
1297 DRM_ERROR("Only 16 vertex buffers are allowed %d\n",
1298 pkt->opcode);
c3ad63af 1299 radeon_cs_dump_packet(p, pkt);
0242f74d
AD		 1300 return -EINVAL;
1301 }
1302 track->num_arrays = c;
1303 for (i = 0; i < (c - 1); i+=2, idx+=3) {
012e976d 1304 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
0242f74d
AD		 1305 if (r) {
1306 DRM_ERROR("No reloc for packet3 %d\n",
1307 pkt->opcode);
c3ad63af 1308 radeon_cs_dump_packet(p, pkt);
0242f74d
AD		 1309 return r;
1310 }
1311 idx_value = radeon_get_ib_value(p, idx);
1312 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
1313
1314 track->arrays[i + 0].esize = idx_value >> 8;
1315 track->arrays[i + 0].robj = reloc->robj;
1316 track->arrays[i + 0].esize &= 0x7F;
012e976d 1317 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
0242f74d
AD		 1318 if (r) {
1319 DRM_ERROR("No reloc for packet3 %d\n",
1320 pkt->opcode);
c3ad63af 1321 radeon_cs_dump_packet(p, pkt);
0242f74d
AD		 1322 return r;
1323 }
1324 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->lobj.gpu_offset);
1325 track->arrays[i + 1].robj = reloc->robj;
1326 track->arrays[i + 1].esize = idx_value >> 24;
1327 track->arrays[i + 1].esize &= 0x7F;
1328 }
1329 if (c & 1) {
012e976d 1330 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
0242f74d
AD		 1331 if (r) {
1332 DRM_ERROR("No reloc for packet3 %d\n",
1333 pkt->opcode);
c3ad63af 1334 radeon_cs_dump_packet(p, pkt);
0242f74d
AD		 1335 return r;
1336 }
1337 idx_value = radeon_get_ib_value(p, idx);
1338 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
1339 track->arrays[i + 0].robj = reloc->robj;
1340 track->arrays[i + 0].esize = idx_value >> 8;
1341 track->arrays[i + 0].esize &= 0x7F;
1342 }
1343 return r;
1344}
1345
771fe6b9
JG		 1346int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1347 struct radeon_cs_packet *pkt,
068a117c 1348 const unsigned *auth, unsigned n,
771fe6b9
JG		 1349 radeon_packet0_check_t check)
1350{
1351 unsigned reg;
1352 unsigned i, j, m;
1353 unsigned idx;
1354 int r;
1355
1356 idx = pkt->idx + 1;
1357 reg = pkt->reg;
068a117c
JG		 1358 /* Check that register fall into register range
1359 * determined by the number of entry (n) in the
1360 * safe register bitmap.
1361 */
771fe6b9
JG		 1362 if (pkt->one_reg_wr) {
1363 if ((reg >> 7) > n) {
1364 return -EINVAL;
1365 }
1366 } else {
1367 if (((reg + (pkt->count << 2)) >> 7) > n) {
1368 return -EINVAL;
1369 }
1370 }
1371 for (i = 0; i <= pkt->count; i++, idx++) {
1372 j = (reg >> 7);
1373 m = 1 << ((reg >> 2) & 31);
1374 if (auth[j] & m) {
1375 r = check(p, pkt, idx, reg);
1376 if (r) {
1377 return r;
1378 }
1379 }
1380 if (pkt->one_reg_wr) {
1381 if (!(auth[j] & m)) {
1382 break;
1383 }
1384 } else {
1385 reg += 4;
1386 }
1387 }
1388 return 0;
1389}
1390
531369e6
DA		 1391/**
1392 * r100_cs_packet_next_vline() - parse userspace VLINE packet
1393 * @parser: parser structure holding parsing context.
1394 *
1395 * Userspace sends a special sequence for VLINE waits.
1396 * PACKET0 - VLINE_START_END + value
1397 * PACKET0 - WAIT_UNTIL +_value
1398 * RELOC (P3) - crtc_id in reloc.
1399 *
1400 * This function parses this and relocates the VLINE START END
1401 * and WAIT UNTIL packets to the correct crtc.
1402 * It also detects a switched off crtc and nulls out the
1403 * wait in that case.
1404 */
1405int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
1406{
531369e6
DA		 1407 struct drm_mode_object *obj;
1408 struct drm_crtc *crtc;
1409 struct radeon_crtc *radeon_crtc;
1410 struct radeon_cs_packet p3reloc, waitreloc;
1411 int crtc_id;
1412 int r;
1413 uint32_t header, h_idx, reg;
513bcb46 1414 volatile uint32_t *ib;
531369e6 1415
f2e39221 1416 ib = p->ib.ptr;
531369e6
DA		 1417
1418 /* parse the wait until */
c38f34b5 1419 r = radeon_cs_packet_parse(p, &waitreloc, p->idx);
531369e6
DA		 1420 if (r)
1421 return r;
1422
1423 /* check its a wait until and only 1 count */
1424 if (waitreloc.reg != RADEON_WAIT_UNTIL ||
1425 waitreloc.count != 0) {
1426 DRM_ERROR("vline wait had illegal wait until segment\n");
a3a88a66 1427 return -EINVAL;
531369e6
DA		 1428 }
1429
513bcb46 1430 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
531369e6 1431 DRM_ERROR("vline wait had illegal wait until\n");
a3a88a66 1432 return -EINVAL;
531369e6
DA		 1433 }
1434
1435 /* jump over the NOP */
c38f34b5 1436 r = radeon_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
531369e6
DA		 1437 if (r)
1438 return r;
1439
1440 h_idx = p->idx - 2;
90ebd065
AD		 1441 p->idx += waitreloc.count + 2;
1442 p->idx += p3reloc.count + 2;
531369e6 1443
513bcb46
DA		 1444 header = radeon_get_ib_value(p, h_idx);
1445 crtc_id = radeon_get_ib_value(p, h_idx + 5);
4e872ae2 1446 reg = R100_CP_PACKET0_GET_REG(header);
531369e6
DA		 1447 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
1448 if (!obj) {
1449 DRM_ERROR("cannot find crtc %d\n", crtc_id);
a3a88a66 1450 return -EINVAL;
531369e6
DA		 1451 }
1452 crtc = obj_to_crtc(obj);
1453 radeon_crtc = to_radeon_crtc(crtc);
1454 crtc_id = radeon_crtc->crtc_id;
1455
1456 if (!crtc->enabled) {
1457 /* if the CRTC isn't enabled - we need to nop out the wait until */
513bcb46
DA		 1458 ib[h_idx + 2] = PACKET2(0);
1459 ib[h_idx + 3] = PACKET2(0);
531369e6
DA		 1460 } else if (crtc_id == 1) {
1461 switch (reg) {
1462 case AVIVO_D1MODE_VLINE_START_END:
90ebd065 1463 header &= ~R300_CP_PACKET0_REG_MASK;
531369e6
DA		 1464 header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1465 break;
1466 case RADEON_CRTC_GUI_TRIG_VLINE:
90ebd065 1467 header &= ~R300_CP_PACKET0_REG_MASK;
531369e6
DA		 1468 header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1469 break;
1470 default:
1471 DRM_ERROR("unknown crtc reloc\n");
a3a88a66 1472 return -EINVAL;
531369e6 1473 }
513bcb46
DA		 1474 ib[h_idx] = header;
1475 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
531369e6 1476 }
a3a88a66
PB		 1477
1478 return 0;
531369e6
DA		 1479}
1480
551ebd83
DA		 1481static int r100_get_vtx_size(uint32_t vtx_fmt)
1482{
1483 int vtx_size;
1484 vtx_size = 2;
1485 /* ordered according to bits in spec */
1486 if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1487 vtx_size++;
1488 if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1489 vtx_size += 3;
1490 if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1491 vtx_size++;
1492 if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1493 vtx_size++;
1494 if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1495 vtx_size += 3;
1496 if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1497 vtx_size++;
1498 if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1499 vtx_size++;
1500 if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1501 vtx_size += 2;
1502 if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1503 vtx_size += 2;
1504 if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1505 vtx_size++;
1506 if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1507 vtx_size += 2;
1508 if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1509 vtx_size++;
1510 if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1511 vtx_size += 2;
1512 if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1513 vtx_size++;
1514 if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1515 vtx_size++;
1516 /* blend weight */
1517 if (vtx_fmt & (0x7 << 15))
1518 vtx_size += (vtx_fmt >> 15) & 0x7;
1519 if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1520 vtx_size += 3;
1521 if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1522 vtx_size += 2;
1523 if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1524 vtx_size++;
1525 if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1526 vtx_size++;
1527 if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1528 vtx_size++;
1529 if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1530 vtx_size++;
1531 return vtx_size;
1532}
1533
771fe6b9 1534static int r100_packet0_check(struct radeon_cs_parser *p,
551ebd83
DA		 1535 struct radeon_cs_packet *pkt,
1536 unsigned idx, unsigned reg)
771fe6b9 1537{
771fe6b9 1538 struct radeon_cs_reloc *reloc;
551ebd83 1539 struct r100_cs_track *track;
771fe6b9
JG		 1540 volatile uint32_t *ib;
1541 uint32_t tmp;
771fe6b9 1542 int r;
551ebd83 1543 int i, face;
e024e110 1544 u32 tile_flags = 0;
513bcb46 1545 u32 idx_value;
771fe6b9 1546
f2e39221 1547 ib = p->ib.ptr;
551ebd83
DA		 1548 track = (struct r100_cs_track *)p->track;
1549
513bcb46
DA		 1550 idx_value = radeon_get_ib_value(p, idx);
1551
551ebd83
DA		 1552 switch (reg) {
1553 case RADEON_CRTC_GUI_TRIG_VLINE:
1554 r = r100_cs_packet_parse_vline(p);
1555 if (r) {
1556 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1557 idx, reg);
c3ad63af 1558 radeon_cs_dump_packet(p, pkt);
551ebd83
DA		 1559 return r;
1560 }
1561 break;
771fe6b9
JG		 1562 /* FIXME: only allow PACKET3 blit? easier to check for out of
1563 * range access */
551ebd83
DA		 1564 case RADEON_DST_PITCH_OFFSET:
1565 case RADEON_SRC_PITCH_OFFSET:
1566 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1567 if (r)
1568 return r;
1569 break;
1570 case RADEON_RB3D_DEPTHOFFSET:
012e976d 1571 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
551ebd83
DA		 1572 if (r) {
1573 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1574 idx, reg);
c3ad63af 1575 radeon_cs_dump_packet(p, pkt);
551ebd83
DA		 1576 return r;
1577 }
1578 track->zb.robj = reloc->robj;
513bcb46 1579 track->zb.offset = idx_value;
40b4a759 1580 track->zb_dirty = true;
513bcb46 1581 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1582 break;
1583 case RADEON_RB3D_COLOROFFSET:
012e976d 1584 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
551ebd83
DA		 1585 if (r) {
1586 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1587 idx, reg);
c3ad63af 1588 radeon_cs_dump_packet(p, pkt);
551ebd83
DA		 1589 return r;
1590 }
1591 track->cb[0].robj = reloc->robj;
513bcb46 1592 track->cb[0].offset = idx_value;
40b4a759 1593 track->cb_dirty = true;
513bcb46 1594 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1595 break;
1596 case RADEON_PP_TXOFFSET_0:
1597 case RADEON_PP_TXOFFSET_1:
1598 case RADEON_PP_TXOFFSET_2:
1599 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
012e976d 1600 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
551ebd83
DA		 1601 if (r) {
1602 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1603 idx, reg);
c3ad63af 1604 radeon_cs_dump_packet(p, pkt);
551ebd83
DA		 1605 return r;
1606 }
f2746f83
AD		 1607 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1608 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1609 tile_flags |= RADEON_TXO_MACRO_TILE;
1610 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1611 tile_flags |= RADEON_TXO_MICRO_TILE_X2;
1612
1613 tmp = idx_value & ~(0x7 << 2);
1614 tmp |= tile_flags;
1615 ib[idx] = tmp + ((u32)reloc->lobj.gpu_offset);
1616 } else
1617 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83 1618 track->textures[i].robj = reloc->robj;
40b4a759 1619 track->tex_dirty = true;
551ebd83
DA		 1620 break;
1621 case RADEON_PP_CUBIC_OFFSET_T0_0:
1622 case RADEON_PP_CUBIC_OFFSET_T0_1:
1623 case RADEON_PP_CUBIC_OFFSET_T0_2:
1624 case RADEON_PP_CUBIC_OFFSET_T0_3:
1625 case RADEON_PP_CUBIC_OFFSET_T0_4:
1626 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
012e976d 1627 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
551ebd83
DA		 1628 if (r) {
1629 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1630 idx, reg);
c3ad63af 1631 radeon_cs_dump_packet(p, pkt);
551ebd83
DA		 1632 return r;
1633 }
513bcb46
DA		 1634 track->textures[0].cube_info[i].offset = idx_value;
1635 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83 1636 track->textures[0].cube_info[i].robj = reloc->robj;
40b4a759 1637 track->tex_dirty = true;
551ebd83
DA		 1638 break;
1639 case RADEON_PP_CUBIC_OFFSET_T1_0:
1640 case RADEON_PP_CUBIC_OFFSET_T1_1:
1641 case RADEON_PP_CUBIC_OFFSET_T1_2:
1642 case RADEON_PP_CUBIC_OFFSET_T1_3:
1643 case RADEON_PP_CUBIC_OFFSET_T1_4:
1644 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
012e976d 1645 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
551ebd83
DA		 1646 if (r) {
1647 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1648 idx, reg);
c3ad63af 1649 radeon_cs_dump_packet(p, pkt);
551ebd83
DA		 1650 return r;
1651 }
513bcb46
DA		 1652 track->textures[1].cube_info[i].offset = idx_value;
1653 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83 1654 track->textures[1].cube_info[i].robj = reloc->robj;
40b4a759 1655 track->tex_dirty = true;
551ebd83
DA		 1656 break;
1657 case RADEON_PP_CUBIC_OFFSET_T2_0:
1658 case RADEON_PP_CUBIC_OFFSET_T2_1:
1659 case RADEON_PP_CUBIC_OFFSET_T2_2:
1660 case RADEON_PP_CUBIC_OFFSET_T2_3:
1661 case RADEON_PP_CUBIC_OFFSET_T2_4:
1662 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
012e976d 1663 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
551ebd83
DA		 1664 if (r) {
1665 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1666 idx, reg);
c3ad63af 1667 radeon_cs_dump_packet(p, pkt);
551ebd83
DA		 1668 return r;
1669 }
513bcb46
DA		 1670 track->textures[2].cube_info[i].offset = idx_value;
1671 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83 1672 track->textures[2].cube_info[i].robj = reloc->robj;
40b4a759 1673 track->tex_dirty = true;
551ebd83
DA		 1674 break;
1675 case RADEON_RE_WIDTH_HEIGHT:
513bcb46 1676 track->maxy = ((idx_value >> 16) & 0x7FF);
40b4a759
MO		 1677 track->cb_dirty = true;
1678 track->zb_dirty = true;
551ebd83
DA		 1679 break;
1680 case RADEON_RB3D_COLORPITCH:
012e976d 1681 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
551ebd83
DA		 1682 if (r) {
1683 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1684 idx, reg);
c3ad63af 1685 radeon_cs_dump_packet(p, pkt);
551ebd83
DA		 1686 return r;
1687 }
c9068eb2
AD		 1688 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1689 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1690 tile_flags |= RADEON_COLOR_TILE_ENABLE;
1691 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1692 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1693
1694 tmp = idx_value & ~(0x7 << 16);
1695 tmp |= tile_flags;
1696 ib[idx] = tmp;
1697 } else
1698 ib[idx] = idx_value;
e024e110 1699
513bcb46 1700 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
40b4a759 1701 track->cb_dirty = true;
551ebd83
DA		 1702 break;
1703 case RADEON_RB3D_DEPTHPITCH:
513bcb46 1704 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
40b4a759 1705 track->zb_dirty = true;
551ebd83
DA		 1706 break;
1707 case RADEON_RB3D_CNTL:
513bcb46 1708 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
551ebd83
DA		 1709 case 7:
1710 case 8:
1711 case 9:
1712 case 11:
1713 case 12:
1714 track->cb[0].cpp = 1;
e024e110 1715 break;
551ebd83
DA		 1716 case 3:
1717 case 4:
1718 case 15:
1719 track->cb[0].cpp = 2;
1720 break;
1721 case 6:
1722 track->cb[0].cpp = 4;
1723 break;
1724 default:
1725 DRM_ERROR("Invalid color buffer format (%d) !\n",
513bcb46 1726 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
551ebd83
DA		 1727 return -EINVAL;
1728 }
513bcb46 1729 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
40b4a759
MO		 1730 track->cb_dirty = true;
1731 track->zb_dirty = true;
551ebd83
DA		 1732 break;
1733 case RADEON_RB3D_ZSTENCILCNTL:
513bcb46 1734 switch (idx_value & 0xf) {
551ebd83
DA		 1735 case 0:
1736 track->zb.cpp = 2;
1737 break;
1738 case 2:
1739 case 3:
1740 case 4:
1741 case 5:
1742 case 9:
1743 case 11:
1744 track->zb.cpp = 4;
17782d99 1745 break;
771fe6b9 1746 default:
771fe6b9
JG		 1747 break;
1748 }
40b4a759 1749 track->zb_dirty = true;
551ebd83
DA		 1750 break;
1751 case RADEON_RB3D_ZPASS_ADDR:
012e976d 1752 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
551ebd83
DA		 1753 if (r) {
1754 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1755 idx, reg);
c3ad63af 1756 radeon_cs_dump_packet(p, pkt);
551ebd83
DA		 1757 return r;
1758 }
513bcb46 1759 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1760 break;
1761 case RADEON_PP_CNTL:
1762 {
513bcb46 1763 uint32_t temp = idx_value >> 4;
551ebd83
DA		 1764 for (i = 0; i < track->num_texture; i++)
1765 track->textures[i].enabled = !!(temp & (1 << i));
40b4a759 1766 track->tex_dirty = true;
551ebd83
DA		 1767 }
1768 break;
1769 case RADEON_SE_VF_CNTL:
513bcb46 1770 track->vap_vf_cntl = idx_value;
551ebd83
DA		 1771 break;
1772 case RADEON_SE_VTX_FMT:
513bcb46 1773 track->vtx_size = r100_get_vtx_size(idx_value);
551ebd83
DA		 1774 break;
1775 case RADEON_PP_TEX_SIZE_0:
1776 case RADEON_PP_TEX_SIZE_1:
1777 case RADEON_PP_TEX_SIZE_2:
1778 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
513bcb46
DA		 1779 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1780 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
40b4a759 1781 track->tex_dirty = true;
551ebd83
DA		 1782 break;
1783 case RADEON_PP_TEX_PITCH_0:
1784 case RADEON_PP_TEX_PITCH_1:
1785 case RADEON_PP_TEX_PITCH_2:
1786 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
513bcb46 1787 track->textures[i].pitch = idx_value + 32;
40b4a759 1788 track->tex_dirty = true;
551ebd83
DA		 1789 break;
1790 case RADEON_PP_TXFILTER_0:
1791 case RADEON_PP_TXFILTER_1:
1792 case RADEON_PP_TXFILTER_2:
1793 i = (reg - RADEON_PP_TXFILTER_0) / 24;
513bcb46 1794 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
551ebd83 1795 >> RADEON_MAX_MIP_LEVEL_SHIFT);
513bcb46 1796 tmp = (idx_value >> 23) & 0x7;
551ebd83
DA		 1797 if (tmp == 2 || tmp == 6)
1798 track->textures[i].roundup_w = false;
513bcb46 1799 tmp = (idx_value >> 27) & 0x7;
551ebd83
DA		 1800 if (tmp == 2 || tmp == 6)
1801 track->textures[i].roundup_h = false;
40b4a759 1802 track->tex_dirty = true;
551ebd83
DA		 1803 break;
1804 case RADEON_PP_TXFORMAT_0:
1805 case RADEON_PP_TXFORMAT_1:
1806 case RADEON_PP_TXFORMAT_2:
1807 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
513bcb46 1808 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
551ebd83
DA		 1809 track->textures[i].use_pitch = 1;
1810 } else {
1811 track->textures[i].use_pitch = 0;
513bcb46
DA		 1812 track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1813 track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
551ebd83 1814 }
513bcb46 1815 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
551ebd83 1816 track->textures[i].tex_coord_type = 2;
513bcb46 1817 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
551ebd83
DA		 1818 case RADEON_TXFORMAT_I8:
1819 case RADEON_TXFORMAT_RGB332:
1820 case RADEON_TXFORMAT_Y8:
1821 track->textures[i].cpp = 1;
f9da52d5 1822 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
551ebd83
DA		 1823 break;
1824 case RADEON_TXFORMAT_AI88:
1825 case RADEON_TXFORMAT_ARGB1555:
1826 case RADEON_TXFORMAT_RGB565:
1827 case RADEON_TXFORMAT_ARGB4444:
1828 case RADEON_TXFORMAT_VYUY422:
1829 case RADEON_TXFORMAT_YVYU422:
551ebd83
DA		 1830 case RADEON_TXFORMAT_SHADOW16:
1831 case RADEON_TXFORMAT_LDUDV655:
1832 case RADEON_TXFORMAT_DUDV88:
1833 track->textures[i].cpp = 2;
f9da52d5 1834 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
771fe6b9 1835 break;
551ebd83
DA		 1836 case RADEON_TXFORMAT_ARGB8888:
1837 case RADEON_TXFORMAT_RGBA8888:
551ebd83
DA		 1838 case RADEON_TXFORMAT_SHADOW32:
1839 case RADEON_TXFORMAT_LDUDUV8888:
1840 track->textures[i].cpp = 4;
f9da52d5 1841 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
551ebd83 1842 break;
d785d78b
DA		 1843 case RADEON_TXFORMAT_DXT1:
1844 track->textures[i].cpp = 1;
1845 track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1846 break;
1847 case RADEON_TXFORMAT_DXT23:
1848 case RADEON_TXFORMAT_DXT45:
1849 track->textures[i].cpp = 1;
1850 track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1851 break;
551ebd83 1852 }
513bcb46
DA		 1853 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1854 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
40b4a759 1855 track->tex_dirty = true;
551ebd83
DA		 1856 break;
1857 case RADEON_PP_CUBIC_FACES_0:
1858 case RADEON_PP_CUBIC_FACES_1:
1859 case RADEON_PP_CUBIC_FACES_2:
513bcb46 1860 tmp = idx_value;
551ebd83
DA		 1861 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1862 for (face = 0; face < 4; face++) {
1863 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1864 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
771fe6b9 1865 }
40b4a759 1866 track->tex_dirty = true;
551ebd83
DA		 1867 break;
1868 default:
1869 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1870 reg, idx);
1871 return -EINVAL;
771fe6b9
JG		 1872 }
1873 return 0;
1874}
1875
068a117c
JG		 1876int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1877 struct radeon_cs_packet *pkt,
4c788679 1878 struct radeon_bo *robj)
068a117c 1879{
068a117c 1880 unsigned idx;
513bcb46 1881 u32 value;
068a117c 1882 idx = pkt->idx + 1;
513bcb46 1883 value = radeon_get_ib_value(p, idx + 2);
4c788679 1884 if ((value + 1) > radeon_bo_size(robj)) {
068a117c
JG		 1885 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1886 "(need %u have %lu) !\n",
513bcb46 1887 value + 1,
4c788679 1888 radeon_bo_size(robj));
068a117c
JG		 1889 return -EINVAL;
1890 }
1891 return 0;
1892}
1893
771fe6b9
JG		 1894static int r100_packet3_check(struct radeon_cs_parser *p,
1895 struct radeon_cs_packet *pkt)
1896{
771fe6b9 1897 struct radeon_cs_reloc *reloc;
551ebd83 1898 struct r100_cs_track *track;
771fe6b9 1899 unsigned idx;
771fe6b9
JG		 1900 volatile uint32_t *ib;
1901 int r;
1902
f2e39221 1903 ib = p->ib.ptr;
771fe6b9 1904 idx = pkt->idx + 1;
551ebd83 1905 track = (struct r100_cs_track *)p->track;
771fe6b9
JG		 1906 switch (pkt->opcode) {
1907 case PACKET3_3D_LOAD_VBPNTR:
513bcb46
DA		 1908 r = r100_packet3_load_vbpntr(p, pkt, idx);
1909 if (r)
1910 return r;
771fe6b9
JG		 1911 break;
1912 case PACKET3_INDX_BUFFER:
012e976d 1913 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
771fe6b9
JG		 1914 if (r) {
1915 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
c3ad63af 1916 radeon_cs_dump_packet(p, pkt);
771fe6b9
JG		 1917 return r;
1918 }
513bcb46 1919 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
068a117c
JG		 1920 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1921 if (r) {
1922 return r;
1923 }
771fe6b9
JG		 1924 break;
1925 case 0x23:
771fe6b9 1926 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
012e976d 1927 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
771fe6b9
JG		 1928 if (r) {
1929 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
c3ad63af 1930 radeon_cs_dump_packet(p, pkt);
771fe6b9
JG		 1931 return r;
1932 }
513bcb46 1933 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
551ebd83 1934 track->num_arrays = 1;
513bcb46 1935 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
551ebd83
DA		 1936
1937 track->arrays[0].robj = reloc->robj;
1938 track->arrays[0].esize = track->vtx_size;
1939
513bcb46 1940 track->max_indx = radeon_get_ib_value(p, idx+1);
551ebd83 1941
513bcb46 1942 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
551ebd83
DA		 1943 track->immd_dwords = pkt->count - 1;
1944 r = r100_cs_track_check(p->rdev, track);
1945 if (r)
1946 return r;
771fe6b9
JG		 1947 break;
1948 case PACKET3_3D_DRAW_IMMD:
513bcb46 1949 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
551ebd83
DA		 1950 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1951 return -EINVAL;
1952 }
cf57fc7a 1953 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
513bcb46 1954 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
551ebd83
DA		 1955 track->immd_dwords = pkt->count - 1;
1956 r = r100_cs_track_check(p->rdev, track);
1957 if (r)
1958 return r;
1959 break;
771fe6b9
JG		 1960 /* triggers drawing using in-packet vertex data */
1961 case PACKET3_3D_DRAW_IMMD_2:
513bcb46 1962 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
551ebd83
DA		 1963 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1964 return -EINVAL;
1965 }
513bcb46 1966 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
551ebd83
DA		 1967 track->immd_dwords = pkt->count;
1968 r = r100_cs_track_check(p->rdev, track);
1969 if (r)
1970 return r;
1971 break;
771fe6b9
JG		 1972 /* triggers drawing using in-packet vertex data */
1973 case PACKET3_3D_DRAW_VBUF_2:
513bcb46 1974 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
551ebd83
DA		 1975 r = r100_cs_track_check(p->rdev, track);
1976 if (r)
1977 return r;
1978 break;
771fe6b9
JG		 1979 /* triggers drawing of vertex buffers setup elsewhere */
1980 case PACKET3_3D_DRAW_INDX_2:
513bcb46 1981 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
551ebd83
DA		 1982 r = r100_cs_track_check(p->rdev, track);
1983 if (r)
1984 return r;
1985 break;
771fe6b9
JG		 1986 /* triggers drawing using indices to vertex buffer */
1987 case PACKET3_3D_DRAW_VBUF:
513bcb46 1988 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
551ebd83
DA		 1989 r = r100_cs_track_check(p->rdev, track);
1990 if (r)
1991 return r;
1992 break;
771fe6b9
JG		 1993 /* triggers drawing of vertex buffers setup elsewhere */
1994 case PACKET3_3D_DRAW_INDX:
513bcb46 1995 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
551ebd83
DA		 1996 r = r100_cs_track_check(p->rdev, track);
1997 if (r)
1998 return r;
1999 break;
771fe6b9 2000 /* triggers drawing using indices to vertex buffer */
ab9e1f59
DA		 2001 case PACKET3_3D_CLEAR_HIZ:
2002 case PACKET3_3D_CLEAR_ZMASK:
2003 if (p->rdev->hyperz_filp != p->filp)
2004 return -EINVAL;
2005 break;
771fe6b9
JG		 2006 case PACKET3_NOP:
2007 break;
2008 default:
2009 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
2010 return -EINVAL;
2011 }
2012 return 0;
2013}
2014
2015int r100_cs_parse(struct radeon_cs_parser *p)
2016{
2017 struct radeon_cs_packet pkt;
9f022ddf 2018 struct r100_cs_track *track;
771fe6b9
JG		 2019 int r;
2020
9f022ddf 2021 track = kzalloc(sizeof(*track), GFP_KERNEL);
ce067913
DC		 2022 if (!track)
2023 return -ENOMEM;
9f022ddf
JG		 2024 r100_cs_track_clear(p->rdev, track);
2025 p->track = track;
771fe6b9 2026 do {
c38f34b5 2027 r = radeon_cs_packet_parse(p, &pkt, p->idx);
771fe6b9
JG		 2028 if (r) {
2029 return r;
2030 }
2031 p->idx += pkt.count + 2;
2032 switch (pkt.type) {
4e872ae2 2033 case RADEON_PACKET_TYPE0:
66b3543e
IH		 2034 if (p->rdev->family >= CHIP_R200)
2035 r = r100_cs_parse_packet0(p, &pkt,
2036 p->rdev->config.r100.reg_safe_bm,
2037 p->rdev->config.r100.reg_safe_bm_size,
2038 &r200_packet0_check);
2039 else
2040 r = r100_cs_parse_packet0(p, &pkt,
2041 p->rdev->config.r100.reg_safe_bm,
2042 p->rdev->config.r100.reg_safe_bm_size,
2043 &r100_packet0_check);
2044 break;
4e872ae2 2045 case RADEON_PACKET_TYPE2:
66b3543e 2046 break;
4e872ae2 2047 case RADEON_PACKET_TYPE3:
66b3543e
IH		 2048 r = r100_packet3_check(p, &pkt);
2049 break;
2050 default:
2051 DRM_ERROR("Unknown packet type %d !\n",
2052 pkt.type);
2053 return -EINVAL;
771fe6b9 2054 }
66b3543e 2055 if (r)
771fe6b9 2056 return r;
771fe6b9
JG		 2057 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
2058 return 0;
2059}
2060
0242f74d 2061static void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
771fe6b9 2062{
0242f74d
AD		 2063 DRM_ERROR("pitch %d\n", t->pitch);
2064 DRM_ERROR("use_pitch %d\n", t->use_pitch);
2065 DRM_ERROR("width %d\n", t->width);
2066 DRM_ERROR("width_11 %d\n", t->width_11);
2067 DRM_ERROR("height %d\n", t->height);
2068 DRM_ERROR("height_11 %d\n", t->height_11);
2069 DRM_ERROR("num levels %d\n", t->num_levels);
2070 DRM_ERROR("depth %d\n", t->txdepth);
2071 DRM_ERROR("bpp %d\n", t->cpp);
2072 DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
2073 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
2074 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
2075 DRM_ERROR("compress format %d\n", t->compress_format);
771fe6b9
JG		 2076}
2077
0242f74d 2078static int r100_track_compress_size(int compress_format, int w, int h)
771fe6b9 2079{
0242f74d
AD		 2080 int block_width, block_height, block_bytes;
2081 int wblocks, hblocks;
2082 int min_wblocks;
2083 int sz;
771fe6b9 2084
0242f74d
AD		 2085 block_width = 4;
2086 block_height = 4;
2087
2088 switch (compress_format) {
2089 case R100_TRACK_COMP_DXT1:
2090 block_bytes = 8;
2091 min_wblocks = 4;
2092 break;
2093 default:
2094 case R100_TRACK_COMP_DXT35:
2095 block_bytes = 16;
2096 min_wblocks = 2;
2097 break;
771fe6b9 2098 }
0242f74d
AD		 2099
2100 hblocks = (h + block_height - 1) / block_height;
2101 wblocks = (w + block_width - 1) / block_width;
2102 if (wblocks < min_wblocks)
2103 wblocks = min_wblocks;
2104 sz = wblocks * hblocks * block_bytes;
2105 return sz;
771fe6b9
JG		 2106}
2107
0242f74d
AD		 2108static int r100_cs_track_cube(struct radeon_device *rdev,
2109 struct r100_cs_track *track, unsigned idx)
771fe6b9 2110{
0242f74d
AD		 2111 unsigned face, w, h;
2112 struct radeon_bo *cube_robj;
2113 unsigned long size;
2114 unsigned compress_format = track->textures[idx].compress_format;
771fe6b9 2115
0242f74d
AD		 2116 for (face = 0; face < 5; face++) {
2117 cube_robj = track->textures[idx].cube_info[face].robj;
2118 w = track->textures[idx].cube_info[face].width;
2119 h = track->textures[idx].cube_info[face].height;
771fe6b9 2120
0242f74d
AD		 2121 if (compress_format) {
2122 size = r100_track_compress_size(compress_format, w, h);
2123 } else
2124 size = w * h;
2125 size *= track->textures[idx].cpp;
2126
2127 size += track->textures[idx].cube_info[face].offset;
2128
2129 if (size > radeon_bo_size(cube_robj)) {
2130 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
2131 size, radeon_bo_size(cube_robj));
2132 r100_cs_track_texture_print(&track->textures[idx]);
2133 return -1;
771fe6b9 2134 }
771fe6b9 2135 }
0242f74d 2136 return 0;
771fe6b9
JG		 2137}
2138
0242f74d
AD		 2139static int r100_cs_track_texture_check(struct radeon_device *rdev,
2140 struct r100_cs_track *track)
771fe6b9 2141{
0242f74d
AD		 2142 struct radeon_bo *robj;
2143 unsigned long size;
2144 unsigned u, i, w, h, d;
2145 int ret;
771fe6b9 2146
0242f74d
AD		 2147 for (u = 0; u < track->num_texture; u++) {
2148 if (!track->textures[u].enabled)
2149 continue;
2150 if (track->textures[u].lookup_disable)
2151 continue;
2152 robj = track->textures[u].robj;
2153 if (robj == NULL) {
2154 DRM_ERROR("No texture bound to unit %u\n", u);
2155 return -EINVAL;
771fe6b9 2156 }
0242f74d
AD		 2157 size = 0;
2158 for (i = 0; i <= track->textures[u].num_levels; i++) {
2159 if (track->textures[u].use_pitch) {
2160 if (rdev->family < CHIP_R300)
2161 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
2162 else
2163 w = track->textures[u].pitch / (1 << i);
2164 } else {
2165 w = track->textures[u].width;
2166 if (rdev->family >= CHIP_RV515)
2167 w |= track->textures[u].width_11;
2168 w = w / (1 << i);
2169 if (track->textures[u].roundup_w)
2170 w = roundup_pow_of_two(w);
2171 }
2172 h = track->textures[u].height;
2173 if (rdev->family >= CHIP_RV515)
2174 h |= track->textures[u].height_11;
2175 h = h / (1 << i);
2176 if (track->textures[u].roundup_h)
2177 h = roundup_pow_of_two(h);
2178 if (track->textures[u].tex_coord_type == 1) {
2179 d = (1 << track->textures[u].txdepth) / (1 << i);
2180 if (!d)
2181 d = 1;
2182 } else {
2183 d = 1;
2184 }
2185 if (track->textures[u].compress_format) {
771fe6b9 2186
0242f74d
AD		 2187 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
2188 /* compressed textures are block based */
2189 } else
2190 size += w * h * d;
2191 }
2192 size *= track->textures[u].cpp;
771fe6b9 2193
0242f74d
AD		 2194 switch (track->textures[u].tex_coord_type) {
2195 case 0:
2196 case 1:
2197 break;
2198 case 2:
2199 if (track->separate_cube) {
2200 ret = r100_cs_track_cube(rdev, track, u);
2201 if (ret)
2202 return ret;
2203 } else
2204 size *= 6;
2205 break;
2206 default:
2207 DRM_ERROR("Invalid texture coordinate type %u for unit "
2208 "%u\n", track->textures[u].tex_coord_type, u);
2209 return -EINVAL;
2210 }
2211 if (size > radeon_bo_size(robj)) {
2212 DRM_ERROR("Texture of unit %u needs %lu bytes but is "
2213 "%lu\n", u, size, radeon_bo_size(robj));
2214 r100_cs_track_texture_print(&track->textures[u]);
2215 return -EINVAL;
771fe6b9 2216 }
771fe6b9 2217 }
0242f74d 2218 return 0;
771fe6b9
JG		 2219}
2220
0242f74d 2221int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
771fe6b9
JG		 2222{
2223 unsigned i;
0242f74d
AD		 2224 unsigned long size;
2225 unsigned prim_walk;
2226 unsigned nverts;
2227 unsigned num_cb = track->cb_dirty ? track->num_cb : 0;
771fe6b9 2228
0242f74d
AD		 2229 if (num_cb && !track->zb_cb_clear && !track->color_channel_mask &&
2230 !track->blend_read_enable)
2231 num_cb = 0;
2232
2233 for (i = 0; i < num_cb; i++) {
2234 if (track->cb[i].robj == NULL) {
2235 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
2236 return -EINVAL;
2237 }
2238 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
2239 size += track->cb[i].offset;
2240 if (size > radeon_bo_size(track->cb[i].robj)) {
2241 DRM_ERROR("[drm] Buffer too small for color buffer %d "
2242 "(need %lu have %lu) !\n", i, size,
2243 radeon_bo_size(track->cb[i].robj));
2244 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
2245 i, track->cb[i].pitch, track->cb[i].cpp,
2246 track->cb[i].offset, track->maxy);
2247 return -EINVAL;
771fe6b9 2248 }
771fe6b9 2249 }
0242f74d 2250 track->cb_dirty = false;
771fe6b9 2251
0242f74d
AD		 2252 if (track->zb_dirty && track->z_enabled) {
2253 if (track->zb.robj == NULL) {
2254 DRM_ERROR("[drm] No buffer for z buffer !\n");
2255 return -EINVAL;
2256 }
2257 size = track->zb.pitch * track->zb.cpp * track->maxy;
2258 size += track->zb.offset;
2259 if (size > radeon_bo_size(track->zb.robj)) {
2260 DRM_ERROR("[drm] Buffer too small for z buffer "
2261 "(need %lu have %lu) !\n", size,
2262 radeon_bo_size(track->zb.robj));
2263 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
2264 track->zb.pitch, track->zb.cpp,
2265 track->zb.offset, track->maxy);
2266 return -EINVAL;
2267 }
225758d8 2268 }
0242f74d 2269 track->zb_dirty = false;
771fe6b9 2270
0242f74d
AD		 2271 if (track->aa_dirty && track->aaresolve) {
2272 if (track->aa.robj == NULL) {
2273 DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i);
2274 return -EINVAL;
2275 }
2276 /* I believe the format comes from colorbuffer0. */
2277 size = track->aa.pitch * track->cb[0].cpp * track->maxy;
2278 size += track->aa.offset;
2279 if (size > radeon_bo_size(track->aa.robj)) {
2280 DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d "
2281 "(need %lu have %lu) !\n", i, size,
2282 radeon_bo_size(track->aa.robj));
2283 DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n",
2284 i, track->aa.pitch, track->cb[0].cpp,
2285 track->aa.offset, track->maxy);
2286 return -EINVAL;
2287 }
2288 }
2289 track->aa_dirty = false;
771fe6b9 2290
0242f74d
AD		 2291 prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
2292 if (track->vap_vf_cntl & (1 << 14)) {
2293 nverts = track->vap_alt_nverts;
2294 } else {
2295 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
2739d49c 2296 }
0242f74d
AD		 2297 switch (prim_walk) {
2298 case 1:
2299 for (i = 0; i < track->num_arrays; i++) {
2300 size = track->arrays[i].esize * track->max_indx * 4;
2301 if (track->arrays[i].robj == NULL) {
2302 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2303 "bound\n", prim_walk, i);
2304 return -EINVAL;
2305 }
2306 if (size > radeon_bo_size(track->arrays[i].robj)) {
2307 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2308 "need %lu dwords have %lu dwords\n",
2309 prim_walk, i, size >> 2,
2310 radeon_bo_size(track->arrays[i].robj)
2311 >> 2);
2312 DRM_ERROR("Max indices %u\n", track->max_indx);
2313 return -EINVAL;
2314 }
771fe6b9 2315 }
0242f74d
AD		 2316 break;
2317 case 2:
2318 for (i = 0; i < track->num_arrays; i++) {
2319 size = track->arrays[i].esize * (nverts - 1) * 4;
2320 if (track->arrays[i].robj == NULL) {
2321 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2322 "bound\n", prim_walk, i);
2323 return -EINVAL;
2324 }
2325 if (size > radeon_bo_size(track->arrays[i].robj)) {
2326 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2327 "need %lu dwords have %lu dwords\n",
2328 prim_walk, i, size >> 2,
2329 radeon_bo_size(track->arrays[i].robj)
2330 >> 2);
2331 return -EINVAL;
2332 }
771fe6b9 2333 }
0242f74d
AD		 2334 break;
2335 case 3:
2336 size = track->vtx_size * nverts;
2337 if (size != track->immd_dwords) {
2338 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
2339 track->immd_dwords, size);
2340 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
2341 nverts, track->vtx_size);
2342 return -EINVAL;
771fe6b9 2343 }
0242f74d
AD		 2344 break;
2345 default:
2346 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
2347 prim_walk);
2348 return -EINVAL;
2a0f8918
DA		 2349 }
2350
0242f74d
AD		 2351 if (track->tex_dirty) {
2352 track->tex_dirty = false;
2353 return r100_cs_track_texture_check(rdev, track);
2a0f8918 2354 }
0242f74d 2355 return 0;
2a0f8918
DA		 2356}
2357
0242f74d 2358void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
2a0f8918 2359{
0242f74d 2360 unsigned i, face;
2a0f8918 2361
0242f74d
AD		 2362 track->cb_dirty = true;
2363 track->zb_dirty = true;
2364 track->tex_dirty = true;
2365 track->aa_dirty = true;
b7d8cce5 2366
0242f74d
AD		 2367 if (rdev->family < CHIP_R300) {
2368 track->num_cb = 1;
2369 if (rdev->family <= CHIP_RS200)
2370 track->num_texture = 3;
7a50f01a 2371 else
0242f74d
AD		 2372 track->num_texture = 6;
2373 track->maxy = 2048;
2374 track->separate_cube = 1;
28d52043 2375 } else {
0242f74d
AD		 2376 track->num_cb = 4;
2377 track->num_texture = 16;
2378 track->maxy = 4096;
2379 track->separate_cube = 0;
2380 track->aaresolve = false;
2381 track->aa.robj = NULL;
28d52043 2382 }
2a0f8918 2383
0242f74d
AD		 2384 for (i = 0; i < track->num_cb; i++) {
2385 track->cb[i].robj = NULL;
2386 track->cb[i].pitch = 8192;
2387 track->cb[i].cpp = 16;
2388 track->cb[i].offset = 0;
771fe6b9 2389 }
0242f74d
AD		 2390 track->z_enabled = true;
2391 track->zb.robj = NULL;
2392 track->zb.pitch = 8192;
2393 track->zb.cpp = 4;
2394 track->zb.offset = 0;
2395 track->vtx_size = 0x7F;
2396 track->immd_dwords = 0xFFFFFFFFUL;
2397 track->num_arrays = 11;
2398 track->max_indx = 0x00FFFFFFUL;
2399 for (i = 0; i < track->num_arrays; i++) {
2400 track->arrays[i].robj = NULL;
2401 track->arrays[i].esize = 0x7F;
771fe6b9 2402 }
0242f74d
AD		 2403 for (i = 0; i < track->num_texture; i++) {
2404 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
2405 track->textures[i].pitch = 16536;
2406 track->textures[i].width = 16536;
2407 track->textures[i].height = 16536;
2408 track->textures[i].width_11 = 1 << 11;
2409 track->textures[i].height_11 = 1 << 11;
2410 track->textures[i].num_levels = 12;
2411 if (rdev->family <= CHIP_RS200) {
2412 track->textures[i].tex_coord_type = 0;
2413 track->textures[i].txdepth = 0;
2414 } else {
2415 track->textures[i].txdepth = 16;
2416 track->textures[i].tex_coord_type = 1;
2417 }
2418 track->textures[i].cpp = 64;
2419 track->textures[i].robj = NULL;
2420 /* CS IB emission code makes sure texture unit are disabled */
2421 track->textures[i].enabled = false;
2422 track->textures[i].lookup_disable = false;
2423 track->textures[i].roundup_w = true;
2424 track->textures[i].roundup_h = true;
2425 if (track->separate_cube)
2426 for (face = 0; face < 5; face++) {
2427 track->textures[i].cube_info[face].robj = NULL;
2428 track->textures[i].cube_info[face].width = 16536;
2429 track->textures[i].cube_info[face].height = 16536;
2430 track->textures[i].cube_info[face].offset = 0;
2431 }
771fe6b9
JG		 2432 }
2433}
2434
0242f74d
AD		 2435/*
2436 * Global GPU functions
2437 */
1109ca09 2438static void r100_errata(struct radeon_device *rdev)
771fe6b9 2439{
0242f74d 2440 rdev->pll_errata = 0;
771fe6b9 2441
0242f74d
AD		 2442 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
2443 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
2444 }
771fe6b9 2445
0242f74d
AD		 2446 if (rdev->family == CHIP_RV100 ||
2447 rdev->family == CHIP_RS100 ||
2448 rdev->family == CHIP_RS200) {
2449 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
2450 }
771fe6b9
JG		 2451}
2452
1109ca09 2453static int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
771fe6b9 2454{
0242f74d
AD		 2455 unsigned i;
2456 uint32_t tmp;
771fe6b9 2457
0242f74d
AD		 2458 for (i = 0; i < rdev->usec_timeout; i++) {
2459 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
2460 if (tmp >= n) {
2461 return 0;
2462 }
2463 DRM_UDELAY(1);
771fe6b9 2464 }
0242f74d 2465 return -1;
771fe6b9
JG		 2466}
2467
0242f74d 2468int r100_gui_wait_for_idle(struct radeon_device *rdev)
771fe6b9 2469{
771fe6b9 2470 unsigned i;
0242f74d 2471 uint32_t tmp;
771fe6b9 2472
0242f74d
AD		 2473 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
2474 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
2475 " Bad things might happen.\n");
771fe6b9 2476 }
0242f74d
AD		 2477 for (i = 0; i < rdev->usec_timeout; i++) {
2478 tmp = RREG32(RADEON_RBBM_STATUS);
2479 if (!(tmp & RADEON_RBBM_ACTIVE)) {
2480 return 0;
2481 }
2482 DRM_UDELAY(1);
771fe6b9 2483 }
0242f74d 2484 return -1;
771fe6b9
JG		 2485}
2486
0242f74d 2487int r100_mc_wait_for_idle(struct radeon_device *rdev)
771fe6b9 2488{
0242f74d 2489 unsigned i;
771fe6b9
JG		 2490 uint32_t tmp;
2491
0242f74d
AD		 2492 for (i = 0; i < rdev->usec_timeout; i++) {
2493 /* read MC_STATUS */
2494 tmp = RREG32(RADEON_MC_STATUS);
2495 if (tmp & RADEON_MC_IDLE) {
2496 return 0;
2497 }
2498 DRM_UDELAY(1);
2499 }
2500 return -1;
771fe6b9
JG		 2501}
2502
0242f74d 2503bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
771fe6b9 2504{
0242f74d 2505 u32 rbbm_status;
771fe6b9 2506
0242f74d
AD		 2507 rbbm_status = RREG32(R_000E40_RBBM_STATUS);
2508 if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
2509 radeon_ring_lockup_update(ring);
2510 return false;
2511 }
2512 /* force CP activities */
2513 radeon_ring_force_activity(rdev, ring);
2514 return radeon_ring_test_lockup(rdev, ring);
771fe6b9
JG		 2515}
2516
74da01dc
AD		 2517/* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
2518void r100_enable_bm(struct radeon_device *rdev)
2519{
2520 uint32_t tmp;
2521 /* Enable bus mastering */
2522 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
2523 WREG32(RADEON_BUS_CNTL, tmp);
2524}
2525
0242f74d 2526void r100_bm_disable(struct radeon_device *rdev)
771fe6b9 2527{
0242f74d
AD		 2528 u32 tmp;
2529
2530 /* disable bus mastering */
2531 tmp = RREG32(R_000030_BUS_CNTL);
2532 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044);
2533 mdelay(1);
2534 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042);
2535 mdelay(1);
2536 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);
2537 tmp = RREG32(RADEON_BUS_CNTL);
2538 mdelay(1);
2539 pci_clear_master(rdev->pdev);
2540 mdelay(1);
771fe6b9 2541}
e024e110 2542
0242f74d 2543int r100_asic_reset(struct radeon_device *rdev)
e024e110 2544{
0242f74d
AD		 2545 struct r100_mc_save save;
2546 u32 status, tmp;
2547 int ret = 0;
e024e110 2548
0242f74d
AD		 2549 status = RREG32(R_000E40_RBBM_STATUS);
2550 if (!G_000E40_GUI_ACTIVE(status)) {
2551 return 0;
e024e110 2552 }
0242f74d
AD		 2553 r100_mc_stop(rdev, &save);
2554 status = RREG32(R_000E40_RBBM_STATUS);
2555 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2556 /* stop CP */
2557 WREG32(RADEON_CP_CSQ_CNTL, 0);
2558 tmp = RREG32(RADEON_CP_RB_CNTL);
2559 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
2560 WREG32(RADEON_CP_RB_RPTR_WR, 0);
2561 WREG32(RADEON_CP_RB_WPTR, 0);
2562 WREG32(RADEON_CP_RB_CNTL, tmp);
2563 /* save PCI state */
2564 pci_save_state(rdev->pdev);
2565 /* disable bus mastering */
2566 r100_bm_disable(rdev);
2567 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) |
2568 S_0000F0_SOFT_RESET_RE(1) |
2569 S_0000F0_SOFT_RESET_PP(1) |
2570 S_0000F0_SOFT_RESET_RB(1));
2571 RREG32(R_0000F0_RBBM_SOFT_RESET);
2572 mdelay(500);
2573 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2574 mdelay(1);
2575 status = RREG32(R_000E40_RBBM_STATUS);
2576 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2577 /* reset CP */
2578 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
2579 RREG32(R_0000F0_RBBM_SOFT_RESET);
2580 mdelay(500);
2581 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2582 mdelay(1);
2583 status = RREG32(R_000E40_RBBM_STATUS);
2584 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2585 /* restore PCI & busmastering */
2586 pci_restore_state(rdev->pdev);
2587 r100_enable_bm(rdev);
2588 /* Check if GPU is idle */
2589 if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) ||
2590 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) {
2591 dev_err(rdev->dev, "failed to reset GPU\n");
2592 ret = -1;
2593 } else
2594 dev_info(rdev->dev, "GPU reset succeed\n");
2595 r100_mc_resume(rdev, &save);
2596 return ret;
2597}
e024e110 2598
0242f74d
AD		 2599void r100_set_common_regs(struct radeon_device *rdev)
2600{
2601 struct drm_device *dev = rdev->ddev;
2602 bool force_dac2 = false;
2603 u32 tmp;
f5c5f040 2604
0242f74d
AD		 2605 /* set these so they don't interfere with anything */
2606 WREG32(RADEON_OV0_SCALE_CNTL, 0);
2607 WREG32(RADEON_SUBPIC_CNTL, 0);
2608 WREG32(RADEON_VIPH_CONTROL, 0);
2609 WREG32(RADEON_I2C_CNTL_1, 0);
2610 WREG32(RADEON_DVI_I2C_CNTL_1, 0);
2611 WREG32(RADEON_CAP0_TRIG_CNTL, 0);
2612 WREG32(RADEON_CAP1_TRIG_CNTL, 0);
f5c5f040 2613
0242f74d
AD		 2614 /* always set up dac2 on rn50 and some rv100 as lots
2615 * of servers seem to wire it up to a VGA port but
2616 * don't report it in the bios connector
2617 * table.
2618 */
2619 switch (dev->pdev->device) {
2620 /* RN50 */
2621 case 0x515e:
2622 case 0x5969:
2623 force_dac2 = true;
2624 break;
2625 /* RV100*/
2626 case 0x5159:
2627 case 0x515a:
2628 /* DELL triple head servers */
2629 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
2630 ((dev->pdev->subsystem_device == 0x016c) ||
2631 (dev->pdev->subsystem_device == 0x016d) ||
2632 (dev->pdev->subsystem_device == 0x016e) ||
2633 (dev->pdev->subsystem_device == 0x016f) ||
2634 (dev->pdev->subsystem_device == 0x0170) ||
2635 (dev->pdev->subsystem_device == 0x017d) ||
2636 (dev->pdev->subsystem_device == 0x017e) ||
2637 (dev->pdev->subsystem_device == 0x0183) ||
2638 (dev->pdev->subsystem_device == 0x018a) ||
2639 (dev->pdev->subsystem_device == 0x019a)))
2640 force_dac2 = true;
2641 break;
2642 }
f5c5f040 2643
0242f74d
AD		 2644 if (force_dac2) {
2645 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
2646 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
2647 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
e024e110 2648
0242f74d
AD		 2649 /* For CRT on DAC2, don't turn it on if BIOS didn't
2650 enable it, even it's detected.
2651 */
c93bb85b 2652
0242f74d
AD		 2653 /* force it to crtc0 */
2654 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
2655 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
2656 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
c93bb85b 2657
0242f74d
AD		 2658 /* set up the TV DAC */
2659 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
2660 RADEON_TV_DAC_STD_MASK |
2661 RADEON_TV_DAC_RDACPD |
2662 RADEON_TV_DAC_GDACPD |
2663 RADEON_TV_DAC_BDACPD |
2664 RADEON_TV_DAC_BGADJ_MASK |
2665 RADEON_TV_DAC_DACADJ_MASK);
2666 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
2667 RADEON_TV_DAC_NHOLD |
2668 RADEON_TV_DAC_STD_PS2 |
2669 (0x58 << 16));
f46c0120 2670
0242f74d
AD		 2671 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
2672 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
2673 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
c93bb85b 2674 }
0242f74d
AD		 2675
2676 /* switch PM block to ACPI mode */
2677 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
2678 tmp &= ~RADEON_PM_MODE_SEL;
2679 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
2680
2681}
2682
2683/*
2684 * VRAM info
2685 */
2686static void r100_vram_get_type(struct radeon_device *rdev)
2687{
2688 uint32_t tmp;
2689
2690 rdev->mc.vram_is_ddr = false;
2691 if (rdev->flags & RADEON_IS_IGP)
2692 rdev->mc.vram_is_ddr = true;
2693 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
2694 rdev->mc.vram_is_ddr = true;
2695 if ((rdev->family == CHIP_RV100) ||
2696 (rdev->family == CHIP_RS100) ||
2697 (rdev->family == CHIP_RS200)) {
2698 tmp = RREG32(RADEON_MEM_CNTL);
2699 if (tmp & RV100_HALF_MODE) {
2700 rdev->mc.vram_width = 32;
2701 } else {
2702 rdev->mc.vram_width = 64;
2703 }
2704 if (rdev->flags & RADEON_SINGLE_CRTC) {
2705 rdev->mc.vram_width /= 4;
2706 rdev->mc.vram_is_ddr = true;
dfee5614 2707 }
0242f74d
AD		 2708 } else if (rdev->family <= CHIP_RV280) {
2709 tmp = RREG32(RADEON_MEM_CNTL);
2710 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
2711 rdev->mc.vram_width = 128;
2712 } else {
2713 rdev->mc.vram_width = 64;
2714 }
2715 } else {
2716 /* newer IGPs */
2717 rdev->mc.vram_width = 128;
c93bb85b 2718 }
0242f74d 2719}
c93bb85b 2720
0242f74d
AD		 2721static u32 r100_get_accessible_vram(struct radeon_device *rdev)
2722{
2723 u32 aper_size;
2724 u8 byte;
2725
2726 aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2727
2728 /* Set HDP_APER_CNTL only on cards that are known not to be broken,
2729 * that is has the 2nd generation multifunction PCI interface
2730 */
2731 if (rdev->family == CHIP_RV280 ||
2732 rdev->family >= CHIP_RV350) {
2733 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
2734 ~RADEON_HDP_APER_CNTL);
2735 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
2736 return aper_size * 2;
c93bb85b
JG		 2737 }
2738
0242f74d
AD		 2739 /* Older cards have all sorts of funny issues to deal with. First
2740 * check if it's a multifunction card by reading the PCI config
2741 * header type... Limit those to one aperture size
c93bb85b 2742 */
0242f74d
AD		 2743 pci_read_config_byte(rdev->pdev, 0xe, &byte);
2744 if (byte & 0x80) {
2745 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
2746 DRM_INFO("Limiting VRAM to one aperture\n");
2747 return aper_size;
2748 }
c93bb85b 2749
0242f74d
AD		 2750 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
2751 * have set it up. We don't write this as it's broken on some ASICs but
2752 * we expect the BIOS to have done the right thing (might be too optimistic...)
2753 */
2754 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
2755 return aper_size * 2;
2756 return aper_size;
2757}
c93bb85b 2758
0242f74d
AD		 2759void r100_vram_init_sizes(struct radeon_device *rdev)
2760{
2761 u64 config_aper_size;
c93bb85b 2762
0242f74d
AD		 2763 /* work out accessible VRAM */
2764 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2765 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2766 rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
2767 /* FIXME we don't use the second aperture yet when we could use it */
2768 if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
2769 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2770 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2771 if (rdev->flags & RADEON_IS_IGP) {
2772 uint32_t tom;
2773 /* read NB_TOM to get the amount of ram stolen for the GPU */
2774 tom = RREG32(RADEON_NB_TOM);
2775 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
2776 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2777 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2778 } else {
2779 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
2780 /* Some production boards of m6 will report 0
2781 * if it's 8 MB
2782 */
2783 if (rdev->mc.real_vram_size == 0) {
2784 rdev->mc.real_vram_size = 8192 * 1024;
2785 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2786 }
2787 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
2788 * Novell bug 204882 + along with lots of ubuntu ones
2789 */
2790 if (rdev->mc.aper_size > config_aper_size)
2791 config_aper_size = rdev->mc.aper_size;
2792
2793 if (config_aper_size > rdev->mc.real_vram_size)
2794 rdev->mc.mc_vram_size = config_aper_size;
2795 else
2796 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
c93bb85b 2797 }
0242f74d 2798}
c93bb85b 2799
0242f74d
AD		 2800void r100_vga_set_state(struct radeon_device *rdev, bool state)
2801{
2802 uint32_t temp;
2803
2804 temp = RREG32(RADEON_CONFIG_CNTL);
2805 if (state == false) {
2806 temp &= ~RADEON_CFG_VGA_RAM_EN;
2807 temp |= RADEON_CFG_VGA_IO_DIS;
2808 } else {
2809 temp &= ~RADEON_CFG_VGA_IO_DIS;
c93bb85b 2810 }
0242f74d
AD		 2811 WREG32(RADEON_CONFIG_CNTL, temp);
2812}
c93bb85b 2813
1109ca09 2814static void r100_mc_init(struct radeon_device *rdev)
0242f74d
AD		 2815{
2816 u64 base;
c93bb85b 2817
0242f74d
AD		 2818 r100_vram_get_type(rdev);
2819 r100_vram_init_sizes(rdev);
2820 base = rdev->mc.aper_base;
2821 if (rdev->flags & RADEON_IS_IGP)
2822 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2823 radeon_vram_location(rdev, &rdev->mc, base);
2824 rdev->mc.gtt_base_align = 0;
2825 if (!(rdev->flags & RADEON_IS_AGP))
2826 radeon_gtt_location(rdev, &rdev->mc);
2827 radeon_update_bandwidth_info(rdev);
2828}
2829
2830
2831/*
2832 * Indirect registers accessor
2833 */
2834void r100_pll_errata_after_index(struct radeon_device *rdev)
2835{
2836 if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) {
2837 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2838 (void)RREG32(RADEON_CRTC_GEN_CNTL);
c93bb85b 2839 }
0242f74d 2840}
c93bb85b 2841
0242f74d
AD		 2842static void r100_pll_errata_after_data(struct radeon_device *rdev)
2843{
2844 /* This workarounds is necessary on RV100, RS100 and RS200 chips
2845 * or the chip could hang on a subsequent access
2846 */
2847 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2848 mdelay(5);
c93bb85b
JG		 2849 }
2850
0242f74d
AD		 2851 /* This function is required to workaround a hardware bug in some (all?)
2852 * revisions of the R300. This workaround should be called after every
2853 * CLOCK_CNTL_INDEX register access. If not, register reads afterward
2854 * may not be correct.
2855 */
2856 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2857 uint32_t save, tmp;
c93bb85b 2858
0242f74d
AD		 2859 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
2860 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2861 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
2862 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
2863 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
c93bb85b 2864 }
0242f74d 2865}
c93bb85b 2866
0242f74d
AD		 2867uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2868{
2869 uint32_t data;
c93bb85b 2870
0242f74d
AD		 2871 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
2872 r100_pll_errata_after_index(rdev);
2873 data = RREG32(RADEON_CLOCK_CNTL_DATA);
2874 r100_pll_errata_after_data(rdev);
2875 return data;
2876}
c93bb85b 2877
0242f74d
AD		 2878void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2879{
2880 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2881 r100_pll_errata_after_index(rdev);
2882 WREG32(RADEON_CLOCK_CNTL_DATA, v);
2883 r100_pll_errata_after_data(rdev);
2884}
2885
1109ca09 2886static void r100_set_safe_registers(struct radeon_device *rdev)
0242f74d
AD		 2887{
2888 if (ASIC_IS_RN50(rdev)) {
2889 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2890 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2891 } else if (rdev->family < CHIP_R200) {
2892 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2893 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
c93bb85b 2894 } else {
0242f74d 2895 r200_set_safe_registers(rdev);
c93bb85b 2896 }
0242f74d 2897}
c93bb85b 2898
0242f74d
AD		 2899/*
2900 * Debugfs info
2901 */
2902#if defined(CONFIG_DEBUG_FS)
2903static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
2904{
2905 struct drm_info_node *node = (struct drm_info_node *) m->private;
2906 struct drm_device *dev = node->minor->dev;
2907 struct radeon_device *rdev = dev->dev_private;
2908 uint32_t reg, value;
2909 unsigned i;
c93bb85b 2910
0242f74d
AD		 2911 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2912 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2913 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2914 for (i = 0; i < 64; i++) {
2915 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2916 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2917 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2918 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2919 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2920 }
2921 return 0;
2922}
c93bb85b 2923
0242f74d
AD		 2924static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2925{
2926 struct drm_info_node *node = (struct drm_info_node *) m->private;
2927 struct drm_device *dev = node->minor->dev;
2928 struct radeon_device *rdev = dev->dev_private;
2929 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2930 uint32_t rdp, wdp;
2931 unsigned count, i, j;
c93bb85b 2932
0242f74d
AD		 2933 radeon_ring_free_size(rdev, ring);
2934 rdp = RREG32(RADEON_CP_RB_RPTR);
2935 wdp = RREG32(RADEON_CP_RB_WPTR);
2936 count = (rdp + ring->ring_size - wdp) & ring->ptr_mask;
2937 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2938 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2939 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2940 seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
2941 seq_printf(m, "%u dwords in ring\n", count);
f3290557
AI		 2942 if (ring->ready) {
2943 for (j = 0; j <= count; j++) {
2944 i = (rdp + j) & ring->ptr_mask;
2945 seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]);
2946 }
0242f74d
AD		 2947 }
2948 return 0;
2949}
c93bb85b 2950
c93bb85b 2951
0242f74d
AD		 2952static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2953{
2954 struct drm_info_node *node = (struct drm_info_node *) m->private;
2955 struct drm_device *dev = node->minor->dev;
2956 struct radeon_device *rdev = dev->dev_private;
2957 uint32_t csq_stat, csq2_stat, tmp;
2958 unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2959 unsigned i;
c93bb85b 2960
0242f74d
AD		 2961 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2962 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2963 csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2964 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2965 r_rptr = (csq_stat >> 0) & 0x3ff;
2966 r_wptr = (csq_stat >> 10) & 0x3ff;
2967 ib1_rptr = (csq_stat >> 20) & 0x3ff;
2968 ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2969 ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2970 ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2971 seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2972 seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2973 seq_printf(m, "Ring rptr %u\n", r_rptr);
2974 seq_printf(m, "Ring wptr %u\n", r_wptr);
2975 seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
2976 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2977 seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
2978 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
2979 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
2980 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
2981 seq_printf(m, "Ring fifo:\n");
2982 for (i = 0; i < 256; i++) {
2983 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2984 tmp = RREG32(RADEON_CP_CSQ_DATA);
2985 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
2986 }
2987 seq_printf(m, "Indirect1 fifo:\n");
2988 for (i = 256; i <= 512; i++) {
2989 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2990 tmp = RREG32(RADEON_CP_CSQ_DATA);
2991 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
2992 }
2993 seq_printf(m, "Indirect2 fifo:\n");
2994 for (i = 640; i < ib1_wptr; i++) {
2995 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2996 tmp = RREG32(RADEON_CP_CSQ_DATA);
2997 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
2998 }
2999 return 0;
3000}
3001
3002static int r100_debugfs_mc_info(struct seq_file *m, void *data)
3003{
3004 struct drm_info_node *node = (struct drm_info_node *) m->private;
3005 struct drm_device *dev = node->minor->dev;
3006 struct radeon_device *rdev = dev->dev_private;
3007 uint32_t tmp;
c93bb85b 3008
0242f74d
AD		 3009 tmp = RREG32(RADEON_CONFIG_MEMSIZE);
3010 seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
3011 tmp = RREG32(RADEON_MC_FB_LOCATION);
3012 seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
3013 tmp = RREG32(RADEON_BUS_CNTL);
3014 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
3015 tmp = RREG32(RADEON_MC_AGP_LOCATION);
3016 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
3017 tmp = RREG32(RADEON_AGP_BASE);
3018 seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
3019 tmp = RREG32(RADEON_HOST_PATH_CNTL);
3020 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
3021 tmp = RREG32(0x01D0);
3022 seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
3023 tmp = RREG32(RADEON_AIC_LO_ADDR);
3024 seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
3025 tmp = RREG32(RADEON_AIC_HI_ADDR);
3026 seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
3027 tmp = RREG32(0x01E4);
3028 seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
3029 return 0;
3030}
c93bb85b 3031
0242f74d
AD		 3032static struct drm_info_list r100_debugfs_rbbm_list[] = {
3033 {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
3034};
c93bb85b 3035
0242f74d
AD		 3036static struct drm_info_list r100_debugfs_cp_list[] = {
3037 {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
3038 {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
3039};
c93bb85b 3040
0242f74d
AD		 3041static struct drm_info_list r100_debugfs_mc_info_list[] = {
3042 {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
3043};
3044#endif
c93bb85b 3045
0242f74d
AD		 3046int r100_debugfs_rbbm_init(struct radeon_device *rdev)
3047{
3048#if defined(CONFIG_DEBUG_FS)
3049 return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
3050#else
3051 return 0;
3052#endif
3053}
c93bb85b 3054
0242f74d
AD		 3055int r100_debugfs_cp_init(struct radeon_device *rdev)
3056{
3057#if defined(CONFIG_DEBUG_FS)
3058 return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
3059#else
3060 return 0;
3061#endif
3062}
c93bb85b 3063
0242f74d
AD		 3064int r100_debugfs_mc_info_init(struct radeon_device *rdev)
3065{
3066#if defined(CONFIG_DEBUG_FS)
3067 return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
3068#else
3069 return 0;
3070#endif
3071}
c93bb85b 3072
0242f74d
AD		 3073int r100_set_surface_reg(struct radeon_device *rdev, int reg,
3074 uint32_t tiling_flags, uint32_t pitch,
3075 uint32_t offset, uint32_t obj_size)
3076{
3077 int surf_index = reg * 16;
3078 int flags = 0;
c93bb85b 3079
0242f74d
AD		 3080 if (rdev->family <= CHIP_RS200) {
3081 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3082 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3083 flags |= RADEON_SURF_TILE_COLOR_BOTH;
3084 if (tiling_flags & RADEON_TILING_MACRO)
3085 flags |= RADEON_SURF_TILE_COLOR_MACRO;
3086 } else if (rdev->family <= CHIP_RV280) {
3087 if (tiling_flags & (RADEON_TILING_MACRO))
3088 flags |= R200_SURF_TILE_COLOR_MACRO;
3089 if (tiling_flags & RADEON_TILING_MICRO)
3090 flags |= R200_SURF_TILE_COLOR_MICRO;
3091 } else {
3092 if (tiling_flags & RADEON_TILING_MACRO)
3093 flags |= R300_SURF_TILE_MACRO;
3094 if (tiling_flags & RADEON_TILING_MICRO)
3095 flags |= R300_SURF_TILE_MICRO;
3096 }
c93bb85b 3097
0242f74d
AD		 3098 if (tiling_flags & RADEON_TILING_SWAP_16BIT)
3099 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
3100 if (tiling_flags & RADEON_TILING_SWAP_32BIT)
3101 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
3102
3103 /* when we aren't tiling the pitch seems to needs to be furtherdivided down. - tested on power5 + rn50 server */
3104 if (tiling_flags & (RADEON_TILING_SWAP_16BIT | RADEON_TILING_SWAP_32BIT)) {
3105 if (!(tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO)))
3106 if (ASIC_IS_RN50(rdev))
3107 pitch /= 16;
c93bb85b
JG		 3108 }
3109
0242f74d
AD		 3110 /* r100/r200 divide by 16 */
3111 if (rdev->family < CHIP_R300)
3112 flags |= pitch / 16;
3113 else
3114 flags |= pitch / 8;
c93bb85b 3115
c93bb85b 3116
0242f74d
AD		 3117 DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
3118 WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
3119 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
3120 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
3121 return 0;
3122}
c93bb85b 3123
0242f74d
AD		 3124void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
3125{
3126 int surf_index = reg * 16;
3127 WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
3128}
c93bb85b 3129
0242f74d
AD		 3130void r100_bandwidth_update(struct radeon_device *rdev)
3131{
3132 fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
3133 fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
3134 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
3135 uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
3136 fixed20_12 memtcas_ff[8] = {
3137 dfixed_init(1),
3138 dfixed_init(2),
3139 dfixed_init(3),
3140 dfixed_init(0),
3141 dfixed_init_half(1),
3142 dfixed_init_half(2),
3143 dfixed_init(0),
3144 };
3145 fixed20_12 memtcas_rs480_ff[8] = {
3146 dfixed_init(0),
3147 dfixed_init(1),
3148 dfixed_init(2),
3149 dfixed_init(3),
3150 dfixed_init(0),
3151 dfixed_init_half(1),
3152 dfixed_init_half(2),
3153 dfixed_init_half(3),
3154 };
3155 fixed20_12 memtcas2_ff[8] = {
3156 dfixed_init(0),
3157 dfixed_init(1),
3158 dfixed_init(2),
3159 dfixed_init(3),
3160 dfixed_init(4),
3161 dfixed_init(5),
3162 dfixed_init(6),
3163 dfixed_init(7),
3164 };
3165 fixed20_12 memtrbs[8] = {
3166 dfixed_init(1),
3167 dfixed_init_half(1),
3168 dfixed_init(2),
3169 dfixed_init_half(2),
3170 dfixed_init(3),
3171 dfixed_init_half(3),
3172 dfixed_init(4),
3173 dfixed_init_half(4)
3174 };
3175 fixed20_12 memtrbs_r4xx[8] = {
3176 dfixed_init(4),
3177 dfixed_init(5),
3178 dfixed_init(6),
3179 dfixed_init(7),
3180 dfixed_init(8),
3181 dfixed_init(9),
3182 dfixed_init(10),
3183 dfixed_init(11)
3184 };
3185 fixed20_12 min_mem_eff;
3186 fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
3187 fixed20_12 cur_latency_mclk, cur_latency_sclk;
3188 fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
3189 disp_drain_rate2, read_return_rate;
3190 fixed20_12 time_disp1_drop_priority;
3191 int c;
3192 int cur_size = 16; /* in octawords */
3193 int critical_point = 0, critical_point2;
3194/* uint32_t read_return_rate, time_disp1_drop_priority; */
3195 int stop_req, max_stop_req;
3196 struct drm_display_mode *mode1 = NULL;
3197 struct drm_display_mode *mode2 = NULL;
3198 uint32_t pixel_bytes1 = 0;
3199 uint32_t pixel_bytes2 = 0;
c93bb85b 3200
0242f74d 3201 radeon_update_display_priority(rdev);
c93bb85b 3202
0242f74d
AD		 3203 if (rdev->mode_info.crtcs[0]->base.enabled) {
3204 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
3205 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
3206 }
3207 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3208 if (rdev->mode_info.crtcs[1]->base.enabled) {
3209 mode2 = &rdev->mode_info.crtcs[1]->base.mode;
3210 pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
3211 }
3212 }
c93bb85b 3213
0242f74d
AD		 3214 min_mem_eff.full = dfixed_const_8(0);
3215 /* get modes */
3216 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
3217 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
3218 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
3219 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
3220 /* check crtc enables */
3221 if (mode2)
3222 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
3223 if (mode1)
3224 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
3225 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
3226 }
c93bb85b 3227
0242f74d
AD		 3228 /*
3229 * determine is there is enough bw for current mode
3230 */
3231 sclk_ff = rdev->pm.sclk;
3232 mclk_ff = rdev->pm.mclk;
c93bb85b 3233
0242f74d
AD		 3234 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
3235 temp_ff.full = dfixed_const(temp);
3236 mem_bw.full = dfixed_mul(mclk_ff, temp_ff);
c93bb85b 3237
0242f74d
AD		 3238 pix_clk.full = 0;
3239 pix_clk2.full = 0;
3240 peak_disp_bw.full = 0;
3241 if (mode1) {
3242 temp_ff.full = dfixed_const(1000);
3243 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */
3244 pix_clk.full = dfixed_div(pix_clk, temp_ff);
3245 temp_ff.full = dfixed_const(pixel_bytes1);
3246 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff);
3247 }
3248 if (mode2) {
3249 temp_ff.full = dfixed_const(1000);
3250 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */
3251 pix_clk2.full = dfixed_div(pix_clk2, temp_ff);
3252 temp_ff.full = dfixed_const(pixel_bytes2);
3253 peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff);
3254 }
c93bb85b 3255
0242f74d
AD		 3256 mem_bw.full = dfixed_mul(mem_bw, min_mem_eff);
3257 if (peak_disp_bw.full >= mem_bw.full) {
3258 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
3259 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
3260 }
c93bb85b 3261
0242f74d
AD		 3262 /* Get values from the EXT_MEM_CNTL register...converting its contents. */
3263 temp = RREG32(RADEON_MEM_TIMING_CNTL);
3264 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
3265 mem_trcd = ((temp >> 2) & 0x3) + 1;
3266 mem_trp = ((temp & 0x3)) + 1;
3267 mem_tras = ((temp & 0x70) >> 4) + 1;
3268 } else if (rdev->family == CHIP_R300 ||
3269 rdev->family == CHIP_R350) { /* r300, r350 */
3270 mem_trcd = (temp & 0x7) + 1;
3271 mem_trp = ((temp >> 8) & 0x7) + 1;
3272 mem_tras = ((temp >> 11) & 0xf) + 4;
3273 } else if (rdev->family == CHIP_RV350 ||
3274 rdev->family <= CHIP_RV380) {
3275 /* rv3x0 */
3276 mem_trcd = (temp & 0x7) + 3;
3277 mem_trp = ((temp >> 8) & 0x7) + 3;
3278 mem_tras = ((temp >> 11) & 0xf) + 6;
3279 } else if (rdev->family == CHIP_R420 ||
3280 rdev->family == CHIP_R423 ||
3281 rdev->family == CHIP_RV410) {
3282 /* r4xx */
3283 mem_trcd = (temp & 0xf) + 3;
3284 if (mem_trcd > 15)
3285 mem_trcd = 15;
3286 mem_trp = ((temp >> 8) & 0xf) + 3;
3287 if (mem_trp > 15)
3288 mem_trp = 15;
3289 mem_tras = ((temp >> 12) & 0x1f) + 6;
3290 if (mem_tras > 31)
3291 mem_tras = 31;
3292 } else { /* RV200, R200 */
3293 mem_trcd = (temp & 0x7) + 1;
3294 mem_trp = ((temp >> 8) & 0x7) + 1;
3295 mem_tras = ((temp >> 12) & 0xf) + 4;
3296 }
3297 /* convert to FF */
3298 trcd_ff.full = dfixed_const(mem_trcd);
3299 trp_ff.full = dfixed_const(mem_trp);
3300 tras_ff.full = dfixed_const(mem_tras);
c93bb85b 3301
0242f74d
AD		 3302 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
3303 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3304 data = (temp & (7 << 20)) >> 20;
3305 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
3306 if (rdev->family == CHIP_RS480) /* don't think rs400 */
3307 tcas_ff = memtcas_rs480_ff[data];
3308 else
3309 tcas_ff = memtcas_ff[data];
3310 } else
3311 tcas_ff = memtcas2_ff[data];
c93bb85b 3312
0242f74d
AD		 3313 if (rdev->family == CHIP_RS400 ||
3314 rdev->family == CHIP_RS480) {
3315 /* extra cas latency stored in bits 23-25 0-4 clocks */
3316 data = (temp >> 23) & 0x7;
3317 if (data < 5)
3318 tcas_ff.full += dfixed_const(data);
c93bb85b 3319 }
551ebd83 3320
0242f74d
AD		 3321 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
3322 /* on the R300, Tcas is included in Trbs.
3323 */
3324 temp = RREG32(RADEON_MEM_CNTL);
3325 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
3326 if (data == 1) {
3327 if (R300_MEM_USE_CD_CH_ONLY & temp) {
3328 temp = RREG32(R300_MC_IND_INDEX);
3329 temp &= ~R300_MC_IND_ADDR_MASK;
3330 temp |= R300_MC_READ_CNTL_CD_mcind;
3331 WREG32(R300_MC_IND_INDEX, temp);
3332 temp = RREG32(R300_MC_IND_DATA);
3333 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
3334 } else {
3335 temp = RREG32(R300_MC_READ_CNTL_AB);
3336 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
3337 }
3338 } else {
3339 temp = RREG32(R300_MC_READ_CNTL_AB);
3340 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
3341 }
3342 if (rdev->family == CHIP_RV410 ||
3343 rdev->family == CHIP_R420 ||
3344 rdev->family == CHIP_R423)
3345 trbs_ff = memtrbs_r4xx[data];
3346 else
3347 trbs_ff = memtrbs[data];
3348 tcas_ff.full += trbs_ff.full;
3349 }
551ebd83 3350
0242f74d 3351 sclk_eff_ff.full = sclk_ff.full;
d785d78b 3352
0242f74d
AD		 3353 if (rdev->flags & RADEON_IS_AGP) {
3354 fixed20_12 agpmode_ff;
3355 agpmode_ff.full = dfixed_const(radeon_agpmode);
3356 temp_ff.full = dfixed_const_666(16);
3357 sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff);
3358 }
3359 /* TODO PCIE lanes may affect this - agpmode == 16?? */
d785d78b 3360
0242f74d
AD		 3361 if (ASIC_IS_R300(rdev)) {
3362 sclk_delay_ff.full = dfixed_const(250);
3363 } else {
3364 if ((rdev->family == CHIP_RV100) ||
3365 rdev->flags & RADEON_IS_IGP) {
3366 if (rdev->mc.vram_is_ddr)
3367 sclk_delay_ff.full = dfixed_const(41);
3368 else
3369 sclk_delay_ff.full = dfixed_const(33);
3370 } else {
3371 if (rdev->mc.vram_width == 128)
3372 sclk_delay_ff.full = dfixed_const(57);
3373 else
3374 sclk_delay_ff.full = dfixed_const(41);
3375 }
d785d78b
DA		 3376 }
3377
0242f74d 3378 mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff);
d785d78b 3379
0242f74d
AD		 3380 if (rdev->mc.vram_is_ddr) {
3381 if (rdev->mc.vram_width == 32) {
3382 k1.full = dfixed_const(40);
3383 c = 3;
3384 } else {
3385 k1.full = dfixed_const(20);
3386 c = 1;
3387 }
3388 } else {
3389 k1.full = dfixed_const(40);
3390 c = 3;
3391 }
37cf6b03 3392
0242f74d
AD		 3393 temp_ff.full = dfixed_const(2);
3394 mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff);
3395 temp_ff.full = dfixed_const(c);
3396 mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff);
3397 temp_ff.full = dfixed_const(4);
3398 mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff);
3399 mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff);
3400 mc_latency_mclk.full += k1.full;
37cf6b03 3401
0242f74d
AD		 3402 mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff);
3403 mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff);
37cf6b03 3404
0242f74d
AD		 3405 /*
3406 HW cursor time assuming worst case of full size colour cursor.
3407 */
3408 temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
3409 temp_ff.full += trcd_ff.full;
3410 if (temp_ff.full < tras_ff.full)
3411 temp_ff.full = tras_ff.full;
3412 cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff);
37cf6b03 3413
0242f74d
AD		 3414 temp_ff.full = dfixed_const(cur_size);
3415 cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff);
3416 /*
3417 Find the total latency for the display data.
3418 */
3419 disp_latency_overhead.full = dfixed_const(8);
3420 disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff);
3421 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
3422 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
37cf6b03 3423
0242f74d
AD		 3424 if (mc_latency_mclk.full > mc_latency_sclk.full)
3425 disp_latency.full = mc_latency_mclk.full;
3426 else
3427 disp_latency.full = mc_latency_sclk.full;
551ebd83 3428
0242f74d
AD		 3429 /* setup Max GRPH_STOP_REQ default value */
3430 if (ASIC_IS_RV100(rdev))
3431 max_stop_req = 0x5c;
3432 else
3433 max_stop_req = 0x7c;
d785d78b 3434
0242f74d
AD		 3435 if (mode1) {
3436 /* CRTC1
3437 Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
3438 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
3439 */
3440 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
d785d78b 3441
0242f74d
AD		 3442 if (stop_req > max_stop_req)
3443 stop_req = max_stop_req;
551ebd83 3444
0242f74d
AD		 3445 /*
3446 Find the drain rate of the display buffer.
3447 */
3448 temp_ff.full = dfixed_const((16/pixel_bytes1));
3449 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff);
551ebd83 3450
0242f74d
AD		 3451 /*
3452 Find the critical point of the display buffer.
3453 */
3454 crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency);
3455 crit_point_ff.full += dfixed_const_half(0);
a41ceb1c 3456
0242f74d
AD		 3457 critical_point = dfixed_trunc(crit_point_ff);
3458
3459 if (rdev->disp_priority == 2) {
3460 critical_point = 0;
551ebd83 3461 }
40b4a759 3462
0242f74d
AD		 3463 /*
3464 The critical point should never be above max_stop_req-4. Setting
3465 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
3466 */
3467 if (max_stop_req - critical_point < 4)
3468 critical_point = 0;
3469
3470 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
3471 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
3472 critical_point = 0x10;
551ebd83 3473 }
0242f74d
AD		 3474
3475 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
3476 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
3477 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3478 temp &= ~(RADEON_GRPH_START_REQ_MASK);
3479 if ((rdev->family == CHIP_R350) &&
3480 (stop_req > 0x15)) {
3481 stop_req -= 0x10;
551ebd83 3482 }
0242f74d
AD		 3483 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3484 temp |= RADEON_GRPH_BUFFER_SIZE;
3485 temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
3486 RADEON_GRPH_CRITICAL_AT_SOF |
3487 RADEON_GRPH_STOP_CNTL);
3488 /*
3489 Write the result into the register.
3490 */
3491 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3492 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
40b4a759 3493
0242f74d
AD		 3494#if 0
3495 if ((rdev->family == CHIP_RS400) ||
3496 (rdev->family == CHIP_RS480)) {
3497 /* attempt to program RS400 disp regs correctly ??? */
3498 temp = RREG32(RS400_DISP1_REG_CNTL);
3499 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
3500 RS400_DISP1_STOP_REQ_LEVEL_MASK);
3501 WREG32(RS400_DISP1_REQ_CNTL1, (temp |
3502 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3503 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3504 temp = RREG32(RS400_DMIF_MEM_CNTL1);
3505 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
3506 RS400_DISP1_CRITICAL_POINT_STOP_MASK);
3507 WREG32(RS400_DMIF_MEM_CNTL1, (temp |
3508 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
3509 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
fff1ce4d 3510 }
0242f74d 3511#endif
fff1ce4d 3512
0242f74d
AD		 3513 DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n",
3514 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */
3515 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
cae94b0a 3516 }
0242f74d
AD		 3517
3518 if (mode2) {
3519 u32 grph2_cntl;
3520 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
3521
3522 if (stop_req > max_stop_req)
3523 stop_req = max_stop_req;
3524
3525 /*
3526 Find the drain rate of the display buffer.
3527 */
3528 temp_ff.full = dfixed_const((16/pixel_bytes2));
3529 disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff);
3530
3531 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
3532 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
3533 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3534 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
3535 if ((rdev->family == CHIP_R350) &&
3536 (stop_req > 0x15)) {
3537 stop_req -= 0x10;
551ebd83 3538 }
0242f74d
AD		 3539 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3540 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
3541 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL |
3542 RADEON_GRPH_CRITICAL_AT_SOF |
3543 RADEON_GRPH_STOP_CNTL);
3544
3545 if ((rdev->family == CHIP_RS100) ||
3546 (rdev->family == CHIP_RS200))
3547 critical_point2 = 0;
3548 else {
3549 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
3550 temp_ff.full = dfixed_const(temp);
3551 temp_ff.full = dfixed_mul(mclk_ff, temp_ff);
3552 if (sclk_ff.full < temp_ff.full)
3553 temp_ff.full = sclk_ff.full;
3554
3555 read_return_rate.full = temp_ff.full;
3556
3557 if (mode1) {
3558 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
3559 time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff);
3560 } else {
3561 time_disp1_drop_priority.full = 0;
551ebd83 3562 }
0242f74d
AD		 3563 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
3564 crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2);
3565 crit_point_ff.full += dfixed_const_half(0);
3566
3567 critical_point2 = dfixed_trunc(crit_point_ff);
3568
3569 if (rdev->disp_priority == 2) {
3570 critical_point2 = 0;
551ebd83 3571 }
40b4a759 3572
0242f74d
AD		 3573 if (max_stop_req - critical_point2 < 4)
3574 critical_point2 = 0;
551ebd83 3575
0242f74d 3576 }
551ebd83 3577
0242f74d
AD		 3578 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
3579 /* some R300 cards have problem with this set to 0 */
3580 critical_point2 = 0x10;
3581 }
40b4a759 3582
0242f74d
AD		 3583 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3584 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
551ebd83 3585
0242f74d
AD		 3586 if ((rdev->family == CHIP_RS400) ||
3587 (rdev->family == CHIP_RS480)) {
3588#if 0
3589 /* attempt to program RS400 disp2 regs correctly ??? */
3590 temp = RREG32(RS400_DISP2_REQ_CNTL1);
3591 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
3592 RS400_DISP2_STOP_REQ_LEVEL_MASK);
3593 WREG32(RS400_DISP2_REQ_CNTL1, (temp |
3594 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3595 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3596 temp = RREG32(RS400_DISP2_REQ_CNTL2);
3597 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
3598 RS400_DISP2_CRITICAL_POINT_STOP_MASK);
3599 WREG32(RS400_DISP2_REQ_CNTL2, (temp |
3600 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
3601 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
3602#endif
3603 WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
3604 WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
3605 WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
3606 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
551ebd83 3607 }
0242f74d
AD		 3608
3609 DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n",
3610 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
551ebd83
DA		 3611 }
3612}
3ce0a23d 3613
e32eb50d 3614int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
3ce0a23d
JG		 3615{
3616 uint32_t scratch;
3617 uint32_t tmp = 0;
3618 unsigned i;
3619 int r;
3620
3621 r = radeon_scratch_get(rdev, &scratch);
3622 if (r) {
3623 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3624 return r;
3625 }
3626 WREG32(scratch, 0xCAFEDEAD);
e32eb50d 3627 r = radeon_ring_lock(rdev, ring, 2);
3ce0a23d
JG		 3628 if (r) {
3629 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3630 radeon_scratch_free(rdev, scratch);
3631 return r;
3632 }
e32eb50d
CK		 3633 radeon_ring_write(ring, PACKET0(scratch, 0));
3634 radeon_ring_write(ring, 0xDEADBEEF);
3635 radeon_ring_unlock_commit(rdev, ring);
3ce0a23d
JG		 3636 for (i = 0; i < rdev->usec_timeout; i++) {
3637 tmp = RREG32(scratch);
3638 if (tmp == 0xDEADBEEF) {
3639 break;
3640 }
3641 DRM_UDELAY(1);
3642 }
3643 if (i < rdev->usec_timeout) {
3644 DRM_INFO("ring test succeeded in %d usecs\n", i);
3645 } else {
369d7ec1 3646 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
3ce0a23d
JG		 3647 scratch, tmp);
3648 r = -EINVAL;
3649 }
3650 radeon_scratch_free(rdev, scratch);
3651 return r;
3652}
3653
3654void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3655{
e32eb50d 3656 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
7b1f2485 3657
c7eff978
AD		 3658 if (ring->rptr_save_reg) {
3659 u32 next_rptr = ring->wptr + 2 + 3;
3660 radeon_ring_write(ring, PACKET0(ring->rptr_save_reg, 0));
3661 radeon_ring_write(ring, next_rptr);
3662 }
3663
e32eb50d
CK		 3664 radeon_ring_write(ring, PACKET0(RADEON_CP_IB_BASE, 1));
3665 radeon_ring_write(ring, ib->gpu_addr);
3666 radeon_ring_write(ring, ib->length_dw);
3ce0a23d
JG		 3667}
3668
f712812e 3669int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3ce0a23d 3670{
f2e39221 3671 struct radeon_ib ib;
3ce0a23d
JG		 3672 uint32_t scratch;
3673 uint32_t tmp = 0;
3674 unsigned i;
3675 int r;
3676
3677 r = radeon_scratch_get(rdev, &scratch);
3678 if (r) {
3679 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3680 return r;
3681 }
3682 WREG32(scratch, 0xCAFEDEAD);
4bf3dd92 3683 r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &ib, NULL, 256);
3ce0a23d 3684 if (r) {
af026c5b
MD		 3685 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
3686 goto free_scratch;
3ce0a23d 3687 }
f2e39221
JG		 3688 ib.ptr[0] = PACKET0(scratch, 0);
3689 ib.ptr[1] = 0xDEADBEEF;
3690 ib.ptr[2] = PACKET2(0);
3691 ib.ptr[3] = PACKET2(0);
3692 ib.ptr[4] = PACKET2(0);
3693 ib.ptr[5] = PACKET2(0);
3694 ib.ptr[6] = PACKET2(0);
3695 ib.ptr[7] = PACKET2(0);
3696 ib.length_dw = 8;
4ef72566 3697 r = radeon_ib_schedule(rdev, &ib, NULL);
3ce0a23d 3698 if (r) {
af026c5b
MD		 3699 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
3700 goto free_ib;
3ce0a23d 3701 }
f2e39221 3702 r = radeon_fence_wait(ib.fence, false);
3ce0a23d 3703 if (r) {
af026c5b
MD		 3704 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
3705 goto free_ib;
3ce0a23d
JG		 3706 }
3707 for (i = 0; i < rdev->usec_timeout; i++) {
3708 tmp = RREG32(scratch);
3709 if (tmp == 0xDEADBEEF) {
3710 break;
3711 }
3712 DRM_UDELAY(1);
3713 }
3714 if (i < rdev->usec_timeout) {
3715 DRM_INFO("ib test succeeded in %u usecs\n", i);
3716 } else {
62f288cf 3717 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3ce0a23d
JG		 3718 scratch, tmp);
3719 r = -EINVAL;
3720 }
af026c5b 3721free_ib:
3ce0a23d 3722 radeon_ib_free(rdev, &ib);
af026c5b
MD		 3723free_scratch:
3724 radeon_scratch_free(rdev, scratch);
3ce0a23d
JG		 3725 return r;
3726}
9f022ddf 3727
9f022ddf
JG		 3728void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3729{
3730 /* Shutdown CP we shouldn't need to do that but better be safe than
3731 * sorry
3732 */
e32eb50d 3733 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
9f022ddf
JG		 3734 WREG32(R_000740_CP_CSQ_CNTL, 0);
3735
3736 /* Save few CRTC registers */
ca6ffc64 3737 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
9f022ddf
JG		 3738 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3739 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3740 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3741 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3742 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3743 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3744 }
3745
3746 /* Disable VGA aperture access */
ca6ffc64 3747 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
9f022ddf
JG		 3748 /* Disable cursor, overlay, crtc */
3749 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3750 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3751 S_000054_CRTC_DISPLAY_DIS(1));
3752 WREG32(R_000050_CRTC_GEN_CNTL,
3753 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3754 S_000050_CRTC_DISP_REQ_EN_B(1));
3755 WREG32(R_000420_OV0_SCALE_CNTL,
3756 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3757 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3758 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3759 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3760 S_000360_CUR2_LOCK(1));
3761 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3762 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3763 S_0003F8_CRTC2_DISPLAY_DIS(1) |
3764 S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3765 WREG32(R_000360_CUR2_OFFSET,
3766 C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3767 }
3768}
3769
3770void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3771{
3772 /* Update base address for crtc */
d594e46a 3773 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
9f022ddf 3774 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
d594e46a 3775 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
9f022ddf
JG		 3776 }
3777 /* Restore CRTC registers */
ca6ffc64 3778 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
9f022ddf
JG		 3779 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3780 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3781 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3782 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3783 }
3784}
ca6ffc64
JG		 3785
3786void r100_vga_render_disable(struct radeon_device *rdev)
3787{
d4550907 3788 u32 tmp;
ca6ffc64 3789
d4550907 3790 tmp = RREG8(R_0003C2_GENMO_WT);
ca6ffc64
JG		 3791 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3792}
d4550907
JG		 3793
3794static void r100_debugfs(struct radeon_device *rdev)
3795{
3796 int r;
3797
3798 r = r100_debugfs_mc_info_init(rdev);
3799 if (r)
3800 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3801}
3802
3803static void r100_mc_program(struct radeon_device *rdev)
3804{
3805 struct r100_mc_save save;
3806
3807 /* Stops all mc clients */
3808 r100_mc_stop(rdev, &save);
3809 if (rdev->flags & RADEON_IS_AGP) {
3810 WREG32(R_00014C_MC_AGP_LOCATION,
3811 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3812 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3813 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3814 if (rdev->family > CHIP_RV200)
3815 WREG32(R_00015C_AGP_BASE_2,
3816 upper_32_bits(rdev->mc.agp_base) & 0xff);
3817 } else {
3818 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3819 WREG32(R_000170_AGP_BASE, 0);
3820 if (rdev->family > CHIP_RV200)
3821 WREG32(R_00015C_AGP_BASE_2, 0);
3822 }
3823 /* Wait for mc idle */
3824 if (r100_mc_wait_for_idle(rdev))
3825 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3826 /* Program MC, should be a 32bits limited address space */
3827 WREG32(R_000148_MC_FB_LOCATION,
3828 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3829 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3830 r100_mc_resume(rdev, &save);
3831}
3832
1109ca09 3833static void r100_clock_startup(struct radeon_device *rdev)
d4550907
JG		 3834{
3835 u32 tmp;
3836
3837 if (radeon_dynclks != -1 && radeon_dynclks)
3838 radeon_legacy_set_clock_gating(rdev, 1);
3839 /* We need to force on some of the block */
3840 tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3841 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3842 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3843 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3844 WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3845}
3846
3847static int r100_startup(struct radeon_device *rdev)
3848{
3849 int r;
3850
92cde00c
AD		 3851 /* set common regs */
3852 r100_set_common_regs(rdev);
3853 /* program mc */
d4550907
JG		 3854 r100_mc_program(rdev);
3855 /* Resume clock */
3856 r100_clock_startup(rdev);
d4550907
JG		 3857 /* Initialize GART (initialize after TTM so we can allocate
3858 * memory through TTM but finalize after TTM) */
17e15b0c 3859 r100_enable_bm(rdev);
d4550907
JG		 3860 if (rdev->flags & RADEON_IS_PCI) {
3861 r = r100_pci_gart_enable(rdev);
3862 if (r)
3863 return r;
3864 }
724c80e1
AD		 3865
3866 /* allocate wb buffer */
3867 r = radeon_wb_init(rdev);
3868 if (r)
3869 return r;
3870
30eb77f4
JG		 3871 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3872 if (r) {
3873 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3874 return r;
3875 }
3876
d4550907 3877 /* Enable IRQ */
e49f3959
AH		 3878 if (!rdev->irq.installed) {
3879 r = radeon_irq_kms_init(rdev);
3880 if (r)
3881 return r;
3882 }
3883
d4550907 3884 r100_irq_set(rdev);
cafe6609 3885 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
d4550907
JG		 3886 /* 1M ring buffer */
3887 r = r100_cp_init(rdev, 1024 * 1024);
3888 if (r) {
ec4f2ac4 3889 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
d4550907
JG		 3890 return r;
3891 }
b15ba512 3892
2898c348
CK		 3893 r = radeon_ib_pool_init(rdev);
3894 if (r) {
3895 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
b15ba512 3896 return r;
2898c348 3897 }
b15ba512 3898
d4550907
JG		 3899 return 0;
3900}
3901
3902int r100_resume(struct radeon_device *rdev)
3903{
6b7746e8
JG		 3904 int r;
3905
d4550907
JG		 3906 /* Make sur GART are not working */
3907 if (rdev->flags & RADEON_IS_PCI)
3908 r100_pci_gart_disable(rdev);
3909 /* Resume clock before doing reset */
3910 r100_clock_startup(rdev);
3911 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
a2d07b74 3912 if (radeon_asic_reset(rdev)) {
d4550907
JG		 3913 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3914 RREG32(R_000E40_RBBM_STATUS),
3915 RREG32(R_0007C0_CP_STAT));
3916 }
3917 /* post */
3918 radeon_combios_asic_init(rdev->ddev);
3919 /* Resume clock after posting */
3920 r100_clock_startup(rdev);
550e2d92
DA		 3921 /* Initialize surface registers */
3922 radeon_surface_init(rdev);
b15ba512
JG		 3923
3924 rdev->accel_working = true;
6b7746e8
JG		 3925 r = r100_startup(rdev);
3926 if (r) {
3927 rdev->accel_working = false;
3928 }
3929 return r;
d4550907
JG		 3930}
3931
3932int r100_suspend(struct radeon_device *rdev)
3933{
3934 r100_cp_disable(rdev);
724c80e1 3935 radeon_wb_disable(rdev);
d4550907
JG		 3936 r100_irq_disable(rdev);
3937 if (rdev->flags & RADEON_IS_PCI)
3938 r100_pci_gart_disable(rdev);
3939 return 0;
3940}
3941
3942void r100_fini(struct radeon_device *rdev)
3943{
d4550907 3944 r100_cp_fini(rdev);
724c80e1 3945 radeon_wb_fini(rdev);
2898c348 3946 radeon_ib_pool_fini(rdev);
d4550907
JG		 3947 radeon_gem_fini(rdev);
3948 if (rdev->flags & RADEON_IS_PCI)
3949 r100_pci_gart_fini(rdev);
d0269ed8 3950 radeon_agp_fini(rdev);
d4550907
JG		 3951 radeon_irq_kms_fini(rdev);
3952 radeon_fence_driver_fini(rdev);
4c788679 3953 radeon_bo_fini(rdev);
d4550907
JG		 3954 radeon_atombios_fini(rdev);
3955 kfree(rdev->bios);
3956 rdev->bios = NULL;
3957}
3958
4c712e6c
DA		 3959/*
3960 * Due to how kexec works, it can leave the hw fully initialised when it
3961 * boots the new kernel. However doing our init sequence with the CP and
3962 * WB stuff setup causes GPU hangs on the RN50 at least. So at startup
3963 * do some quick sanity checks and restore sane values to avoid this
3964 * problem.
3965 */
3966void r100_restore_sanity(struct radeon_device *rdev)
3967{
3968 u32 tmp;
3969
3970 tmp = RREG32(RADEON_CP_CSQ_CNTL);
3971 if (tmp) {
3972 WREG32(RADEON_CP_CSQ_CNTL, 0);
3973 }
3974 tmp = RREG32(RADEON_CP_RB_CNTL);
3975 if (tmp) {
3976 WREG32(RADEON_CP_RB_CNTL, 0);
3977 }
3978 tmp = RREG32(RADEON_SCRATCH_UMSK);
3979 if (tmp) {
3980 WREG32(RADEON_SCRATCH_UMSK, 0);
3981 }
3982}
3983
d4550907
JG		 3984int r100_init(struct radeon_device *rdev)
3985{
3986 int r;
3987
d4550907
JG		 3988 /* Register debugfs file specific to this group of asics */
3989 r100_debugfs(rdev);
3990 /* Disable VGA */
3991 r100_vga_render_disable(rdev);
3992 /* Initialize scratch registers */
3993 radeon_scratch_init(rdev);
3994 /* Initialize surface registers */
3995 radeon_surface_init(rdev);
4c712e6c
DA		 3996 /* sanity check some register to avoid hangs like after kexec */
3997 r100_restore_sanity(rdev);
d4550907
JG		 3998 /* TODO: disable VGA need to use VGA request */
3999 /* BIOS*/
4000 if (!radeon_get_bios(rdev)) {
4001 if (ASIC_IS_AVIVO(rdev))
4002 return -EINVAL;
4003 }
4004 if (rdev->is_atom_bios) {
4005 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
4006 return -EINVAL;
4007 } else {
4008 r = radeon_combios_init(rdev);
4009 if (r)
4010 return r;
4011 }
4012 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
a2d07b74 4013 if (radeon_asic_reset(rdev)) {
d4550907
JG		 4014 dev_warn(rdev->dev,
4015 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
4016 RREG32(R_000E40_RBBM_STATUS),
4017 RREG32(R_0007C0_CP_STAT));
4018 }
4019 /* check if cards are posted or not */
72542d77
DA		 4020 if (radeon_boot_test_post_card(rdev) == false)
4021 return -EINVAL;
d4550907
JG		 4022 /* Set asic errata */
4023 r100_errata(rdev);
4024 /* Initialize clocks */
4025 radeon_get_clock_info(rdev->ddev);
d594e46a
JG		 4026 /* initialize AGP */
4027 if (rdev->flags & RADEON_IS_AGP) {
4028 r = radeon_agp_init(rdev);
4029 if (r) {
4030 radeon_agp_disable(rdev);
4031 }
4032 }
4033 /* initialize VRAM */
4034 r100_mc_init(rdev);
d4550907 4035 /* Fence driver */
30eb77f4 4036 r = radeon_fence_driver_init(rdev);
d4550907
JG		 4037 if (r)
4038 return r;
d4550907 4039 /* Memory manager */
4c788679 4040 r = radeon_bo_init(rdev);
d4550907
JG		 4041 if (r)
4042 return r;
4043 if (rdev->flags & RADEON_IS_PCI) {
4044 r = r100_pci_gart_init(rdev);
4045 if (r)
4046 return r;
4047 }
4048 r100_set_safe_registers(rdev);
b15ba512 4049
d4550907
JG		 4050 rdev->accel_working = true;
4051 r = r100_startup(rdev);
4052 if (r) {
4053 /* Somethings want wront with the accel init stop accel */
4054 dev_err(rdev->dev, "Disabling GPU acceleration\n");
d4550907 4055 r100_cp_fini(rdev);
724c80e1 4056 radeon_wb_fini(rdev);
2898c348 4057 radeon_ib_pool_fini(rdev);
655efd3d 4058 radeon_irq_kms_fini(rdev);
d4550907
JG		 4059 if (rdev->flags & RADEON_IS_PCI)
4060 r100_pci_gart_fini(rdev);
d4550907
JG		 4061 rdev->accel_working = false;
4062 }
4063 return 0;
4064}
6fcbef7a 4065
2ef9bdfe
DV		 4066uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
4067 bool always_indirect)
6fcbef7a 4068{
2ef9bdfe 4069 if (reg < rdev->rmmio_size && !always_indirect)
6fcbef7a
AK		 4070 return readl(((void __iomem *)rdev->rmmio) + reg);
4071 else {
2c385151
DV		 4072 unsigned long flags;
4073 uint32_t ret;
4074
4075 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
6fcbef7a 4076 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
2c385151
DV		 4077 ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
4078 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
4079
4080 return ret;
6fcbef7a
AK		 4081 }
4082}
4083
2ef9bdfe
DV		 4084void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
4085 bool always_indirect)
6fcbef7a 4086{
2ef9bdfe 4087 if (reg < rdev->rmmio_size && !always_indirect)
6fcbef7a
AK		 4088 writel(v, ((void __iomem *)rdev->rmmio) + reg);
4089 else {
2c385151
DV		 4090 unsigned long flags;
4091
4092 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
6fcbef7a
AK		 4093 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4094 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
2c385151 4095 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
6fcbef7a
AK		 4096 }
4097}
4098
4099u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)
4100{
4101 if (reg < rdev->rio_mem_size)
4102 return ioread32(rdev->rio_mem + reg);
4103 else {
4104 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4105 return ioread32(rdev->rio_mem + RADEON_MM_DATA);
4106 }
4107}
4108
4109void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
4110{
4111 if (reg < rdev->rio_mem_size)
4112 iowrite32(v, rdev->rio_mem + reg);
4113 else {
4114 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4115 iowrite32(v, rdev->rio_mem + RADEON_MM_DATA);
4116 }
4117}
kernel source for telekom puls (alcatel/mediatek)