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drm/radeon/kms: Convert R300 to new init path
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / radeon / r100.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <linux/seq_file.h>
29#include "drmP.h"
30#include "drm.h"
31#include "radeon_drm.h"
771fe6b9
JG		 32#include "radeon_reg.h"
33#include "radeon.h"
3ce0a23d
JG		 34#include "r100d.h"
35
70967ab9
BH		 36#include <linux/firmware.h>
37#include <linux/platform_device.h>
38
551ebd83
DA		 39#include "r100_reg_safe.h"
40#include "rn50_reg_safe.h"
41
70967ab9
BH		 42/* Firmware Names */
43#define FIRMWARE_R100 "radeon/R100_cp.bin"
44#define FIRMWARE_R200 "radeon/R200_cp.bin"
45#define FIRMWARE_R300 "radeon/R300_cp.bin"
46#define FIRMWARE_R420 "radeon/R420_cp.bin"
47#define FIRMWARE_RS690 "radeon/RS690_cp.bin"
48#define FIRMWARE_RS600 "radeon/RS600_cp.bin"
49#define FIRMWARE_R520 "radeon/R520_cp.bin"
50
51MODULE_FIRMWARE(FIRMWARE_R100);
52MODULE_FIRMWARE(FIRMWARE_R200);
53MODULE_FIRMWARE(FIRMWARE_R300);
54MODULE_FIRMWARE(FIRMWARE_R420);
55MODULE_FIRMWARE(FIRMWARE_RS690);
56MODULE_FIRMWARE(FIRMWARE_RS600);
57MODULE_FIRMWARE(FIRMWARE_R520);
771fe6b9 58
551ebd83
DA		 59#include "r100_track.h"
60
771fe6b9
JG		 61/* This files gather functions specifics to:
62 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
63 *
64 * Some of these functions might be used by newer ASICs.
65 */
551ebd83 66int r200_init(struct radeon_device *rdev);
771fe6b9
JG		 67void r100_hdp_reset(struct radeon_device *rdev);
68void r100_gpu_init(struct radeon_device *rdev);
69int r100_gui_wait_for_idle(struct radeon_device *rdev);
70int r100_mc_wait_for_idle(struct radeon_device *rdev);
71void r100_gpu_wait_for_vsync(struct radeon_device *rdev);
72void r100_gpu_wait_for_vsync2(struct radeon_device *rdev);
73int r100_debugfs_mc_info_init(struct radeon_device *rdev);
74
75
76/*
77 * PCI GART
78 */
79void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
80{
81 /* TODO: can we do somethings here ? */
82 /* It seems hw only cache one entry so we should discard this
83 * entry otherwise if first GPU GART read hit this entry it
84 * could end up in wrong address. */
85}
86
4aac0473 87int r100_pci_gart_init(struct radeon_device *rdev)
771fe6b9 88{
771fe6b9
JG		 89 int r;
90
4aac0473
JG		 91 if (rdev->gart.table.ram.ptr) {
92 WARN(1, "R100 PCI GART already initialized.\n");
93 return 0;
94 }
771fe6b9
JG		 95 /* Initialize common gart structure */
96 r = radeon_gart_init(rdev);
4aac0473 97 if (r)
771fe6b9 98 return r;
4aac0473
JG		 99 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
100 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
101 rdev->asic->gart_set_page = &r100_pci_gart_set_page;
102 return radeon_gart_table_ram_alloc(rdev);
103}
104
105int r100_pci_gart_enable(struct radeon_device *rdev)
106{
107 uint32_t tmp;
108
771fe6b9
JG		 109 /* discard memory request outside of configured range */
110 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
111 WREG32(RADEON_AIC_CNTL, tmp);
112 /* set address range for PCI address translate */
113 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_location);
114 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
115 WREG32(RADEON_AIC_HI_ADDR, tmp);
116 /* Enable bus mastering */
117 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
118 WREG32(RADEON_BUS_CNTL, tmp);
119 /* set PCI GART page-table base address */
120 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
121 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
122 WREG32(RADEON_AIC_CNTL, tmp);
123 r100_pci_gart_tlb_flush(rdev);
124 rdev->gart.ready = true;
125 return 0;
126}
127
128void r100_pci_gart_disable(struct radeon_device *rdev)
129{
130 uint32_t tmp;
131
132 /* discard memory request outside of configured range */
133 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
134 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
135 WREG32(RADEON_AIC_LO_ADDR, 0);
136 WREG32(RADEON_AIC_HI_ADDR, 0);
137}
138
139int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
140{
141 if (i < 0 || i > rdev->gart.num_gpu_pages) {
142 return -EINVAL;
143 }
ed10f95d 144 rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr));
771fe6b9
JG		 145 return 0;
146}
147
4aac0473 148void r100_pci_gart_fini(struct radeon_device *rdev)
771fe6b9 149{
4aac0473
JG		 150 r100_pci_gart_disable(rdev);
151 radeon_gart_table_ram_free(rdev);
152 radeon_gart_fini(rdev);
771fe6b9
JG		 153}
154
155
156/*
157 * MC
158 */
159void r100_mc_disable_clients(struct radeon_device *rdev)
160{
161 uint32_t ov0_scale_cntl, crtc_ext_cntl, crtc_gen_cntl, crtc2_gen_cntl;
162
163 /* FIXME: is this function correct for rs100,rs200,rs300 ? */
164 if (r100_gui_wait_for_idle(rdev)) {
165 printk(KERN_WARNING "Failed to wait GUI idle while "
166 "programming pipes. Bad things might happen.\n");
167 }
168
169 /* stop display and memory access */
170 ov0_scale_cntl = RREG32(RADEON_OV0_SCALE_CNTL);
171 WREG32(RADEON_OV0_SCALE_CNTL, ov0_scale_cntl & ~RADEON_SCALER_ENABLE);
172 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
173 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl | RADEON_CRTC_DISPLAY_DIS);
174 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
175
176 r100_gpu_wait_for_vsync(rdev);
177
178 WREG32(RADEON_CRTC_GEN_CNTL,
179 (crtc_gen_cntl & ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_ICON_EN)) |
180 RADEON_CRTC_DISP_REQ_EN_B | RADEON_CRTC_EXT_DISP_EN);
181
182 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
183 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
184
185 r100_gpu_wait_for_vsync2(rdev);
186 WREG32(RADEON_CRTC2_GEN_CNTL,
187 (crtc2_gen_cntl &
188 ~(RADEON_CRTC2_CUR_EN | RADEON_CRTC2_ICON_EN)) |
189 RADEON_CRTC2_DISP_REQ_EN_B);
190 }
191
192 udelay(500);
193}
194
195void r100_mc_setup(struct radeon_device *rdev)
196{
197 uint32_t tmp;
198 int r;
199
200 r = r100_debugfs_mc_info_init(rdev);
201 if (r) {
202 DRM_ERROR("Failed to register debugfs file for R100 MC !\n");
203 }
204 /* Write VRAM size in case we are limiting it */
7a50f01a
DA		 205 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
206 /* Novell bug 204882 for RN50/M6/M7 with 8/16/32MB VRAM,
207 * if the aperture is 64MB but we have 32MB VRAM
208 * we report only 32MB VRAM but we have to set MC_FB_LOCATION
209 * to 64MB, otherwise the gpu accidentially dies */
210 tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
771fe6b9
JG		 211 tmp = REG_SET(RADEON_MC_FB_TOP, tmp >> 16);
212 tmp |= REG_SET(RADEON_MC_FB_START, rdev->mc.vram_location >> 16);
213 WREG32(RADEON_MC_FB_LOCATION, tmp);
214
215 /* Enable bus mastering */
216 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
217 WREG32(RADEON_BUS_CNTL, tmp);
218
219 if (rdev->flags & RADEON_IS_AGP) {
220 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
221 tmp = REG_SET(RADEON_MC_AGP_TOP, tmp >> 16);
222 tmp |= REG_SET(RADEON_MC_AGP_START, rdev->mc.gtt_location >> 16);
223 WREG32(RADEON_MC_AGP_LOCATION, tmp);
224 WREG32(RADEON_AGP_BASE, rdev->mc.agp_base);
225 } else {
226 WREG32(RADEON_MC_AGP_LOCATION, 0x0FFFFFFF);
227 WREG32(RADEON_AGP_BASE, 0);
228 }
229
230 tmp = RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL;
231 tmp |= (7 << 28);
232 WREG32(RADEON_HOST_PATH_CNTL, tmp | RADEON_HDP_SOFT_RESET | RADEON_HDP_READ_BUFFER_INVALIDATE);
233 (void)RREG32(RADEON_HOST_PATH_CNTL);
234 WREG32(RADEON_HOST_PATH_CNTL, tmp);
235 (void)RREG32(RADEON_HOST_PATH_CNTL);
236}
237
238int r100_mc_init(struct radeon_device *rdev)
239{
240 int r;
241
242 if (r100_debugfs_rbbm_init(rdev)) {
243 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
244 }
245
246 r100_gpu_init(rdev);
247 /* Disable gart which also disable out of gart access */
248 r100_pci_gart_disable(rdev);
249
250 /* Setup GPU memory space */
771fe6b9
JG		 251 rdev->mc.gtt_location = 0xFFFFFFFFUL;
252 if (rdev->flags & RADEON_IS_AGP) {
253 r = radeon_agp_init(rdev);
254 if (r) {
255 printk(KERN_WARNING "[drm] Disabling AGP\n");
256 rdev->flags &= ~RADEON_IS_AGP;
257 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
258 } else {
259 rdev->mc.gtt_location = rdev->mc.agp_base;
260 }
261 }
262 r = radeon_mc_setup(rdev);
263 if (r) {
264 return r;
265 }
266
267 r100_mc_disable_clients(rdev);
268 if (r100_mc_wait_for_idle(rdev)) {
269 printk(KERN_WARNING "Failed to wait MC idle while "
270 "programming pipes. Bad things might happen.\n");
271 }
272
273 r100_mc_setup(rdev);
274 return 0;
275}
276
277void r100_mc_fini(struct radeon_device *rdev)
278{
771fe6b9
JG		 279}
280
281
7ed220d7
MD		 282/*
283 * Interrupts
284 */
285int r100_irq_set(struct radeon_device *rdev)
286{
287 uint32_t tmp = 0;
288
289 if (rdev->irq.sw_int) {
290 tmp |= RADEON_SW_INT_ENABLE;
291 }
292 if (rdev->irq.crtc_vblank_int[0]) {
293 tmp |= RADEON_CRTC_VBLANK_MASK;
294 }
295 if (rdev->irq.crtc_vblank_int[1]) {
296 tmp |= RADEON_CRTC2_VBLANK_MASK;
297 }
298 WREG32(RADEON_GEN_INT_CNTL, tmp);
299 return 0;
300}
301
9f022ddf
JG		 302void r100_irq_disable(struct radeon_device *rdev)
303{
304 u32 tmp;
305
306 WREG32(R_000040_GEN_INT_CNTL, 0);
307 /* Wait and acknowledge irq */
308 mdelay(1);
309 tmp = RREG32(R_000044_GEN_INT_STATUS);
310 WREG32(R_000044_GEN_INT_STATUS, tmp);
311}
312
7ed220d7
MD		 313static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
314{
315 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
316 uint32_t irq_mask = RADEON_SW_INT_TEST | RADEON_CRTC_VBLANK_STAT |
317 RADEON_CRTC2_VBLANK_STAT;
318
319 if (irqs) {
320 WREG32(RADEON_GEN_INT_STATUS, irqs);
321 }
322 return irqs & irq_mask;
323}
324
325int r100_irq_process(struct radeon_device *rdev)
326{
327 uint32_t status;
328
329 status = r100_irq_ack(rdev);
330 if (!status) {
331 return IRQ_NONE;
332 }
a513c184
JG		 333 if (rdev->shutdown) {
334 return IRQ_NONE;
335 }
7ed220d7
MD		 336 while (status) {
337 /* SW interrupt */
338 if (status & RADEON_SW_INT_TEST) {
339 radeon_fence_process(rdev);
340 }
341 /* Vertical blank interrupts */
342 if (status & RADEON_CRTC_VBLANK_STAT) {
343 drm_handle_vblank(rdev->ddev, 0);
344 }
345 if (status & RADEON_CRTC2_VBLANK_STAT) {
346 drm_handle_vblank(rdev->ddev, 1);
347 }
348 status = r100_irq_ack(rdev);
349 }
350 return IRQ_HANDLED;
351}
352
353u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
354{
355 if (crtc == 0)
356 return RREG32(RADEON_CRTC_CRNT_FRAME);
357 else
358 return RREG32(RADEON_CRTC2_CRNT_FRAME);
359}
360
361
771fe6b9
JG		 362/*
363 * Fence emission
364 */
365void r100_fence_ring_emit(struct radeon_device *rdev,
366 struct radeon_fence *fence)
367{
368 /* Who ever call radeon_fence_emit should call ring_lock and ask
369 * for enough space (today caller are ib schedule and buffer move) */
370 /* Wait until IDLE & CLEAN */
371 radeon_ring_write(rdev, PACKET0(0x1720, 0));
372 radeon_ring_write(rdev, (1 << 16) | (1 << 17));
373 /* Emit fence sequence & fire IRQ */
374 radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
375 radeon_ring_write(rdev, fence->seq);
376 radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
377 radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
378}
379
380
381/*
382 * Writeback
383 */
384int r100_wb_init(struct radeon_device *rdev)
385{
386 int r;
387
388 if (rdev->wb.wb_obj == NULL) {
389 r = radeon_object_create(rdev, NULL, 4096,
390 true,
391 RADEON_GEM_DOMAIN_GTT,
392 false, &rdev->wb.wb_obj);
393 if (r) {
394 DRM_ERROR("radeon: failed to create WB buffer (%d).\n", r);
395 return r;
396 }
397 r = radeon_object_pin(rdev->wb.wb_obj,
398 RADEON_GEM_DOMAIN_GTT,
399 &rdev->wb.gpu_addr);
400 if (r) {
401 DRM_ERROR("radeon: failed to pin WB buffer (%d).\n", r);
402 return r;
403 }
404 r = radeon_object_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
405 if (r) {
406 DRM_ERROR("radeon: failed to map WB buffer (%d).\n", r);
407 return r;
408 }
409 }
9f022ddf
JG		 410 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr);
411 WREG32(R_00070C_CP_RB_RPTR_ADDR,
412 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + 1024) >> 2));
413 WREG32(R_000770_SCRATCH_UMSK, 0xff);
771fe6b9
JG		 414 return 0;
415}
416
9f022ddf
JG		 417void r100_wb_disable(struct radeon_device *rdev)
418{
419 WREG32(R_000770_SCRATCH_UMSK, 0);
420}
421
771fe6b9
JG		 422void r100_wb_fini(struct radeon_device *rdev)
423{
9f022ddf 424 r100_wb_disable(rdev);
771fe6b9
JG		 425 if (rdev->wb.wb_obj) {
426 radeon_object_kunmap(rdev->wb.wb_obj);
427 radeon_object_unpin(rdev->wb.wb_obj);
428 radeon_object_unref(&rdev->wb.wb_obj);
429 rdev->wb.wb = NULL;
430 rdev->wb.wb_obj = NULL;
431 }
432}
433
434int r100_copy_blit(struct radeon_device *rdev,
435 uint64_t src_offset,
436 uint64_t dst_offset,
437 unsigned num_pages,
438 struct radeon_fence *fence)
439{
440 uint32_t cur_pages;
441 uint32_t stride_bytes = PAGE_SIZE;
442 uint32_t pitch;
443 uint32_t stride_pixels;
444 unsigned ndw;
445 int num_loops;
446 int r = 0;
447
448 /* radeon limited to 16k stride */
449 stride_bytes &= 0x3fff;
450 /* radeon pitch is /64 */
451 pitch = stride_bytes / 64;
452 stride_pixels = stride_bytes / 4;
453 num_loops = DIV_ROUND_UP(num_pages, 8191);
454
455 /* Ask for enough room for blit + flush + fence */
456 ndw = 64 + (10 * num_loops);
457 r = radeon_ring_lock(rdev, ndw);
458 if (r) {
459 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
460 return -EINVAL;
461 }
462 while (num_pages > 0) {
463 cur_pages = num_pages;
464 if (cur_pages > 8191) {
465 cur_pages = 8191;
466 }
467 num_pages -= cur_pages;
468
469 /* pages are in Y direction - height
470 page width in X direction - width */
471 radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8));
472 radeon_ring_write(rdev,
473 RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
474 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
475 RADEON_GMC_SRC_CLIPPING |
476 RADEON_GMC_DST_CLIPPING |
477 RADEON_GMC_BRUSH_NONE |
478 (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
479 RADEON_GMC_SRC_DATATYPE_COLOR |
480 RADEON_ROP3_S |
481 RADEON_DP_SRC_SOURCE_MEMORY |
482 RADEON_GMC_CLR_CMP_CNTL_DIS |
483 RADEON_GMC_WR_MSK_DIS);
484 radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10));
485 radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10));
486 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
487 radeon_ring_write(rdev, 0);
488 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
489 radeon_ring_write(rdev, num_pages);
490 radeon_ring_write(rdev, num_pages);
491 radeon_ring_write(rdev, cur_pages | (stride_pixels << 16));
492 }
493 radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
494 radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL);
495 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
496 radeon_ring_write(rdev,
497 RADEON_WAIT_2D_IDLECLEAN |
498 RADEON_WAIT_HOST_IDLECLEAN |
499 RADEON_WAIT_DMA_GUI_IDLE);
500 if (fence) {
501 r = radeon_fence_emit(rdev, fence);
502 }
503 radeon_ring_unlock_commit(rdev);
504 return r;
505}
506
507
508/*
509 * CP
510 */
45600232
JG		 511static int r100_cp_wait_for_idle(struct radeon_device *rdev)
512{
513 unsigned i;
514 u32 tmp;
515
516 for (i = 0; i < rdev->usec_timeout; i++) {
517 tmp = RREG32(R_000E40_RBBM_STATUS);
518 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
519 return 0;
520 }
521 udelay(1);
522 }
523 return -1;
524}
525
771fe6b9
JG		 526void r100_ring_start(struct radeon_device *rdev)
527{
528 int r;
529
530 r = radeon_ring_lock(rdev, 2);
531 if (r) {
532 return;
533 }
534 radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
535 radeon_ring_write(rdev,
536 RADEON_ISYNC_ANY2D_IDLE3D |
537 RADEON_ISYNC_ANY3D_IDLE2D |
538 RADEON_ISYNC_WAIT_IDLEGUI |
539 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
540 radeon_ring_unlock_commit(rdev);
541}
542
70967ab9
BH		 543
544/* Load the microcode for the CP */
545static int r100_cp_init_microcode(struct radeon_device *rdev)
771fe6b9 546{
70967ab9
BH		 547 struct platform_device *pdev;
548 const char *fw_name = NULL;
549 int err;
771fe6b9 550
70967ab9 551 DRM_DEBUG("\n");
771fe6b9 552
70967ab9
BH		 553 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
554 err = IS_ERR(pdev);
555 if (err) {
556 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
557 return -EINVAL;
558 }
771fe6b9
JG		 559 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
560 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
561 (rdev->family == CHIP_RS200)) {
562 DRM_INFO("Loading R100 Microcode\n");
70967ab9 563 fw_name = FIRMWARE_R100;
771fe6b9
JG		 564 } else if ((rdev->family == CHIP_R200) ||
565 (rdev->family == CHIP_RV250) ||
566 (rdev->family == CHIP_RV280) ||
567 (rdev->family == CHIP_RS300)) {
568 DRM_INFO("Loading R200 Microcode\n");
70967ab9 569 fw_name = FIRMWARE_R200;
771fe6b9
JG		 570 } else if ((rdev->family == CHIP_R300) ||
571 (rdev->family == CHIP_R350) ||
572 (rdev->family == CHIP_RV350) ||
573 (rdev->family == CHIP_RV380) ||
574 (rdev->family == CHIP_RS400) ||
575 (rdev->family == CHIP_RS480)) {
576 DRM_INFO("Loading R300 Microcode\n");
70967ab9 577 fw_name = FIRMWARE_R300;
771fe6b9
JG		 578 } else if ((rdev->family == CHIP_R420) ||
579 (rdev->family == CHIP_R423) ||
580 (rdev->family == CHIP_RV410)) {
581 DRM_INFO("Loading R400 Microcode\n");
70967ab9 582 fw_name = FIRMWARE_R420;
771fe6b9
JG		 583 } else if ((rdev->family == CHIP_RS690) ||
584 (rdev->family == CHIP_RS740)) {
585 DRM_INFO("Loading RS690/RS740 Microcode\n");
70967ab9 586 fw_name = FIRMWARE_RS690;
771fe6b9
JG		 587 } else if (rdev->family == CHIP_RS600) {
588 DRM_INFO("Loading RS600 Microcode\n");
70967ab9 589 fw_name = FIRMWARE_RS600;
771fe6b9
JG		 590 } else if ((rdev->family == CHIP_RV515) ||
591 (rdev->family == CHIP_R520) ||
592 (rdev->family == CHIP_RV530) ||
593 (rdev->family == CHIP_R580) ||
594 (rdev->family == CHIP_RV560) ||
595 (rdev->family == CHIP_RV570)) {
596 DRM_INFO("Loading R500 Microcode\n");
70967ab9
BH		 597 fw_name = FIRMWARE_R520;
598 }
599
3ce0a23d 600 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
70967ab9
BH		 601 platform_device_unregister(pdev);
602 if (err) {
603 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
604 fw_name);
3ce0a23d 605 } else if (rdev->me_fw->size % 8) {
70967ab9
BH		 606 printk(KERN_ERR
607 "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
3ce0a23d 608 rdev->me_fw->size, fw_name);
70967ab9 609 err = -EINVAL;
3ce0a23d
JG		 610 release_firmware(rdev->me_fw);
611 rdev->me_fw = NULL;
70967ab9
BH		 612 }
613 return err;
614}
615static void r100_cp_load_microcode(struct radeon_device *rdev)
616{
617 const __be32 *fw_data;
618 int i, size;
619
620 if (r100_gui_wait_for_idle(rdev)) {
621 printk(KERN_WARNING "Failed to wait GUI idle while "
622 "programming pipes. Bad things might happen.\n");
623 }
624
3ce0a23d
JG		 625 if (rdev->me_fw) {
626 size = rdev->me_fw->size / 4;
627 fw_data = (const __be32 *)&rdev->me_fw->data[0];
70967ab9
BH		 628 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
629 for (i = 0; i < size; i += 2) {
630 WREG32(RADEON_CP_ME_RAM_DATAH,
631 be32_to_cpup(&fw_data[i]));
632 WREG32(RADEON_CP_ME_RAM_DATAL,
633 be32_to_cpup(&fw_data[i + 1]));
771fe6b9
JG		 634 }
635 }
636}
637
638int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
639{
640 unsigned rb_bufsz;
641 unsigned rb_blksz;
642 unsigned max_fetch;
643 unsigned pre_write_timer;
644 unsigned pre_write_limit;
645 unsigned indirect2_start;
646 unsigned indirect1_start;
647 uint32_t tmp;
648 int r;
649
650 if (r100_debugfs_cp_init(rdev)) {
651 DRM_ERROR("Failed to register debugfs file for CP !\n");
652 }
653 /* Reset CP */
654 tmp = RREG32(RADEON_CP_CSQ_STAT);
655 if ((tmp & (1 << 31))) {
656 DRM_INFO("radeon: cp busy (0x%08X) resetting\n", tmp);
657 WREG32(RADEON_CP_CSQ_MODE, 0);
658 WREG32(RADEON_CP_CSQ_CNTL, 0);
659 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
660 tmp = RREG32(RADEON_RBBM_SOFT_RESET);
661 mdelay(2);
662 WREG32(RADEON_RBBM_SOFT_RESET, 0);
663 tmp = RREG32(RADEON_RBBM_SOFT_RESET);
664 mdelay(2);
665 tmp = RREG32(RADEON_CP_CSQ_STAT);
666 if ((tmp & (1 << 31))) {
667 DRM_INFO("radeon: cp reset failed (0x%08X)\n", tmp);
668 }
669 } else {
670 DRM_INFO("radeon: cp idle (0x%08X)\n", tmp);
671 }
70967ab9 672
3ce0a23d 673 if (!rdev->me_fw) {
70967ab9
BH		 674 r = r100_cp_init_microcode(rdev);
675 if (r) {
676 DRM_ERROR("Failed to load firmware!\n");
677 return r;
678 }
679 }
680
771fe6b9
JG		 681 /* Align ring size */
682 rb_bufsz = drm_order(ring_size / 8);
683 ring_size = (1 << (rb_bufsz + 1)) * 4;
684 r100_cp_load_microcode(rdev);
685 r = radeon_ring_init(rdev, ring_size);
686 if (r) {
687 return r;
688 }
689 /* Each time the cp read 1024 bytes (16 dword/quadword) update
690 * the rptr copy in system ram */
691 rb_blksz = 9;
692 /* cp will read 128bytes at a time (4 dwords) */
693 max_fetch = 1;
694 rdev->cp.align_mask = 16 - 1;
695 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
696 pre_write_timer = 64;
697 /* Force CP_RB_WPTR write if written more than one time before the
698 * delay expire
699 */
700 pre_write_limit = 0;
701 /* Setup the cp cache like this (cache size is 96 dwords) :
702 * RING 0 to 15
703 * INDIRECT1 16 to 79
704 * INDIRECT2 80 to 95
705 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
706 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
707 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
708 * Idea being that most of the gpu cmd will be through indirect1 buffer
709 * so it gets the bigger cache.
710 */
711 indirect2_start = 80;
712 indirect1_start = 16;
713 /* cp setup */
714 WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
715 WREG32(RADEON_CP_RB_CNTL,
4e484e7d
MD		 716#ifdef __BIG_ENDIAN
717 RADEON_BUF_SWAP_32BIT |
718#endif
771fe6b9
JG		 719 REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
720 REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
721 REG_SET(RADEON_MAX_FETCH, max_fetch) |
722 RADEON_RB_NO_UPDATE);
723 /* Set ring address */
724 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
725 WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
726 /* Force read & write ptr to 0 */
727 tmp = RREG32(RADEON_CP_RB_CNTL);
728 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
729 WREG32(RADEON_CP_RB_RPTR_WR, 0);
730 WREG32(RADEON_CP_RB_WPTR, 0);
731 WREG32(RADEON_CP_RB_CNTL, tmp);
732 udelay(10);
733 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
734 rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR);
735 /* Set cp mode to bus mastering & enable cp*/
736 WREG32(RADEON_CP_CSQ_MODE,
737 REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
738 REG_SET(RADEON_INDIRECT1_START, indirect1_start));
739 WREG32(0x718, 0);
740 WREG32(0x744, 0x00004D4D);
741 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
742 radeon_ring_start(rdev);
743 r = radeon_ring_test(rdev);
744 if (r) {
745 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
746 return r;
747 }
748 rdev->cp.ready = true;
749 return 0;
750}
751
752void r100_cp_fini(struct radeon_device *rdev)
753{
45600232
JG		 754 if (r100_cp_wait_for_idle(rdev)) {
755 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
756 }
771fe6b9 757 /* Disable ring */
a18d7ea1 758 r100_cp_disable(rdev);
771fe6b9
JG		 759 radeon_ring_fini(rdev);
760 DRM_INFO("radeon: cp finalized\n");
761}
762
763void r100_cp_disable(struct radeon_device *rdev)
764{
765 /* Disable ring */
766 rdev->cp.ready = false;
767 WREG32(RADEON_CP_CSQ_MODE, 0);
768 WREG32(RADEON_CP_CSQ_CNTL, 0);
769 if (r100_gui_wait_for_idle(rdev)) {
770 printk(KERN_WARNING "Failed to wait GUI idle while "
771 "programming pipes. Bad things might happen.\n");
772 }
773}
774
775int r100_cp_reset(struct radeon_device *rdev)
776{
777 uint32_t tmp;
778 bool reinit_cp;
779 int i;
780
781 reinit_cp = rdev->cp.ready;
782 rdev->cp.ready = false;
783 WREG32(RADEON_CP_CSQ_MODE, 0);
784 WREG32(RADEON_CP_CSQ_CNTL, 0);
785 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
786 (void)RREG32(RADEON_RBBM_SOFT_RESET);
787 udelay(200);
788 WREG32(RADEON_RBBM_SOFT_RESET, 0);
789 /* Wait to prevent race in RBBM_STATUS */
790 mdelay(1);
791 for (i = 0; i < rdev->usec_timeout; i++) {
792 tmp = RREG32(RADEON_RBBM_STATUS);
793 if (!(tmp & (1 << 16))) {
794 DRM_INFO("CP reset succeed (RBBM_STATUS=0x%08X)\n",
795 tmp);
796 if (reinit_cp) {
797 return r100_cp_init(rdev, rdev->cp.ring_size);
798 }
799 return 0;
800 }
801 DRM_UDELAY(1);
802 }
803 tmp = RREG32(RADEON_RBBM_STATUS);
804 DRM_ERROR("Failed to reset CP (RBBM_STATUS=0x%08X)!\n", tmp);
805 return -1;
806}
807
3ce0a23d
JG		 808void r100_cp_commit(struct radeon_device *rdev)
809{
810 WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
811 (void)RREG32(RADEON_CP_RB_WPTR);
812}
813
771fe6b9
JG		 814
815/*
816 * CS functions
817 */
818int r100_cs_parse_packet0(struct radeon_cs_parser *p,
819 struct radeon_cs_packet *pkt,
068a117c 820 const unsigned *auth, unsigned n,
771fe6b9
JG		 821 radeon_packet0_check_t check)
822{
823 unsigned reg;
824 unsigned i, j, m;
825 unsigned idx;
826 int r;
827
828 idx = pkt->idx + 1;
829 reg = pkt->reg;
068a117c
JG		 830 /* Check that register fall into register range
831 * determined by the number of entry (n) in the
832 * safe register bitmap.
833 */
771fe6b9
JG		 834 if (pkt->one_reg_wr) {
835 if ((reg >> 7) > n) {
836 return -EINVAL;
837 }
838 } else {
839 if (((reg + (pkt->count << 2)) >> 7) > n) {
840 return -EINVAL;
841 }
842 }
843 for (i = 0; i <= pkt->count; i++, idx++) {
844 j = (reg >> 7);
845 m = 1 << ((reg >> 2) & 31);
846 if (auth[j] & m) {
847 r = check(p, pkt, idx, reg);
848 if (r) {
849 return r;
850 }
851 }
852 if (pkt->one_reg_wr) {
853 if (!(auth[j] & m)) {
854 break;
855 }
856 } else {
857 reg += 4;
858 }
859 }
860 return 0;
861}
862
771fe6b9
JG		 863void r100_cs_dump_packet(struct radeon_cs_parser *p,
864 struct radeon_cs_packet *pkt)
865{
771fe6b9
JG		 866 volatile uint32_t *ib;
867 unsigned i;
868 unsigned idx;
869
870 ib = p->ib->ptr;
771fe6b9
JG		 871 idx = pkt->idx;
872 for (i = 0; i <= (pkt->count + 1); i++, idx++) {
873 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
874 }
875}
876
877/**
878 * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
879 * @parser: parser structure holding parsing context.
880 * @pkt: where to store packet informations
881 *
882 * Assume that chunk_ib_index is properly set. Will return -EINVAL
883 * if packet is bigger than remaining ib size. or if packets is unknown.
884 **/
885int r100_cs_packet_parse(struct radeon_cs_parser *p,
886 struct radeon_cs_packet *pkt,
887 unsigned idx)
888{
889 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
fa99239c 890 uint32_t header;
771fe6b9
JG		 891
892 if (idx >= ib_chunk->length_dw) {
893 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
894 idx, ib_chunk->length_dw);
895 return -EINVAL;
896 }
513bcb46 897 header = radeon_get_ib_value(p, idx);
771fe6b9
JG		 898 pkt->idx = idx;
899 pkt->type = CP_PACKET_GET_TYPE(header);
900 pkt->count = CP_PACKET_GET_COUNT(header);
901 switch (pkt->type) {
902 case PACKET_TYPE0:
903 pkt->reg = CP_PACKET0_GET_REG(header);
904 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
905 break;
906 case PACKET_TYPE3:
907 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
908 break;
909 case PACKET_TYPE2:
910 pkt->count = -1;
911 break;
912 default:
913 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
914 return -EINVAL;
915 }
916 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
917 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
918 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
919 return -EINVAL;
920 }
921 return 0;
922}
923
531369e6
DA		 924/**
925 * r100_cs_packet_next_vline() - parse userspace VLINE packet
926 * @parser: parser structure holding parsing context.
927 *
928 * Userspace sends a special sequence for VLINE waits.
929 * PACKET0 - VLINE_START_END + value
930 * PACKET0 - WAIT_UNTIL +_value
931 * RELOC (P3) - crtc_id in reloc.
932 *
933 * This function parses this and relocates the VLINE START END
934 * and WAIT UNTIL packets to the correct crtc.
935 * It also detects a switched off crtc and nulls out the
936 * wait in that case.
937 */
938int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
939{
531369e6
DA		 940 struct drm_mode_object *obj;
941 struct drm_crtc *crtc;
942 struct radeon_crtc *radeon_crtc;
943 struct radeon_cs_packet p3reloc, waitreloc;
944 int crtc_id;
945 int r;
946 uint32_t header, h_idx, reg;
513bcb46 947 volatile uint32_t *ib;
531369e6 948
513bcb46 949 ib = p->ib->ptr;
531369e6
DA		 950
951 /* parse the wait until */
952 r = r100_cs_packet_parse(p, &waitreloc, p->idx);
953 if (r)
954 return r;
955
956 /* check its a wait until and only 1 count */
957 if (waitreloc.reg != RADEON_WAIT_UNTIL ||
958 waitreloc.count != 0) {
959 DRM_ERROR("vline wait had illegal wait until segment\n");
960 r = -EINVAL;
961 return r;
962 }
963
513bcb46 964 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
531369e6
DA		 965 DRM_ERROR("vline wait had illegal wait until\n");
966 r = -EINVAL;
967 return r;
968 }
969
970 /* jump over the NOP */
90ebd065 971 r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
531369e6
DA		 972 if (r)
973 return r;
974
975 h_idx = p->idx - 2;
90ebd065
AD		 976 p->idx += waitreloc.count + 2;
977 p->idx += p3reloc.count + 2;
531369e6 978
513bcb46
DA		 979 header = radeon_get_ib_value(p, h_idx);
980 crtc_id = radeon_get_ib_value(p, h_idx + 5);
981 reg = header >> 2;
531369e6
DA		 982 mutex_lock(&p->rdev->ddev->mode_config.mutex);
983 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
984 if (!obj) {
985 DRM_ERROR("cannot find crtc %d\n", crtc_id);
986 r = -EINVAL;
987 goto out;
988 }
989 crtc = obj_to_crtc(obj);
990 radeon_crtc = to_radeon_crtc(crtc);
991 crtc_id = radeon_crtc->crtc_id;
992
993 if (!crtc->enabled) {
994 /* if the CRTC isn't enabled - we need to nop out the wait until */
513bcb46
DA		 995 ib[h_idx + 2] = PACKET2(0);
996 ib[h_idx + 3] = PACKET2(0);
531369e6
DA		 997 } else if (crtc_id == 1) {
998 switch (reg) {
999 case AVIVO_D1MODE_VLINE_START_END:
90ebd065 1000 header &= ~R300_CP_PACKET0_REG_MASK;
531369e6
DA		 1001 header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1002 break;
1003 case RADEON_CRTC_GUI_TRIG_VLINE:
90ebd065 1004 header &= ~R300_CP_PACKET0_REG_MASK;
531369e6
DA		 1005 header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1006 break;
1007 default:
1008 DRM_ERROR("unknown crtc reloc\n");
1009 r = -EINVAL;
1010 goto out;
1011 }
513bcb46
DA		 1012 ib[h_idx] = header;
1013 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
531369e6
DA		 1014 }
1015out:
1016 mutex_unlock(&p->rdev->ddev->mode_config.mutex);
1017 return r;
1018}
1019
771fe6b9
JG		 1020/**
1021 * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
1022 * @parser: parser structure holding parsing context.
1023 * @data: pointer to relocation data
1024 * @offset_start: starting offset
1025 * @offset_mask: offset mask (to align start offset on)
1026 * @reloc: reloc informations
1027 *
1028 * Check next packet is relocation packet3, do bo validation and compute
1029 * GPU offset using the provided start.
1030 **/
1031int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
1032 struct radeon_cs_reloc **cs_reloc)
1033{
771fe6b9
JG		 1034 struct radeon_cs_chunk *relocs_chunk;
1035 struct radeon_cs_packet p3reloc;
1036 unsigned idx;
1037 int r;
1038
1039 if (p->chunk_relocs_idx == -1) {
1040 DRM_ERROR("No relocation chunk !\n");
1041 return -EINVAL;
1042 }
1043 *cs_reloc = NULL;
771fe6b9
JG		 1044 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
1045 r = r100_cs_packet_parse(p, &p3reloc, p->idx);
1046 if (r) {
1047 return r;
1048 }
1049 p->idx += p3reloc.count + 2;
1050 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
1051 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1052 p3reloc.idx);
1053 r100_cs_dump_packet(p, &p3reloc);
1054 return -EINVAL;
1055 }
513bcb46 1056 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
771fe6b9
JG		 1057 if (idx >= relocs_chunk->length_dw) {
1058 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1059 idx, relocs_chunk->length_dw);
1060 r100_cs_dump_packet(p, &p3reloc);
1061 return -EINVAL;
1062 }
1063 /* FIXME: we assume reloc size is 4 dwords */
1064 *cs_reloc = p->relocs_ptr[(idx / 4)];
1065 return 0;
1066}
1067
551ebd83
DA		 1068static int r100_get_vtx_size(uint32_t vtx_fmt)
1069{
1070 int vtx_size;
1071 vtx_size = 2;
1072 /* ordered according to bits in spec */
1073 if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1074 vtx_size++;
1075 if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1076 vtx_size += 3;
1077 if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1078 vtx_size++;
1079 if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1080 vtx_size++;
1081 if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1082 vtx_size += 3;
1083 if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1084 vtx_size++;
1085 if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1086 vtx_size++;
1087 if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1088 vtx_size += 2;
1089 if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1090 vtx_size += 2;
1091 if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1092 vtx_size++;
1093 if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1094 vtx_size += 2;
1095 if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1096 vtx_size++;
1097 if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1098 vtx_size += 2;
1099 if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1100 vtx_size++;
1101 if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1102 vtx_size++;
1103 /* blend weight */
1104 if (vtx_fmt & (0x7 << 15))
1105 vtx_size += (vtx_fmt >> 15) & 0x7;
1106 if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1107 vtx_size += 3;
1108 if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1109 vtx_size += 2;
1110 if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1111 vtx_size++;
1112 if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1113 vtx_size++;
1114 if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1115 vtx_size++;
1116 if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1117 vtx_size++;
1118 return vtx_size;
1119}
1120
771fe6b9 1121static int r100_packet0_check(struct radeon_cs_parser *p,
551ebd83
DA		 1122 struct radeon_cs_packet *pkt,
1123 unsigned idx, unsigned reg)
771fe6b9 1124{
771fe6b9 1125 struct radeon_cs_reloc *reloc;
551ebd83 1126 struct r100_cs_track *track;
771fe6b9
JG		 1127 volatile uint32_t *ib;
1128 uint32_t tmp;
771fe6b9 1129 int r;
551ebd83 1130 int i, face;
e024e110 1131 u32 tile_flags = 0;
513bcb46 1132 u32 idx_value;
771fe6b9
JG		 1133
1134 ib = p->ib->ptr;
551ebd83
DA		 1135 track = (struct r100_cs_track *)p->track;
1136
513bcb46
DA		 1137 idx_value = radeon_get_ib_value(p, idx);
1138
551ebd83
DA		 1139 switch (reg) {
1140 case RADEON_CRTC_GUI_TRIG_VLINE:
1141 r = r100_cs_packet_parse_vline(p);
1142 if (r) {
1143 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1144 idx, reg);
1145 r100_cs_dump_packet(p, pkt);
1146 return r;
1147 }
1148 break;
771fe6b9
JG		 1149 /* FIXME: only allow PACKET3 blit? easier to check for out of
1150 * range access */
551ebd83
DA		 1151 case RADEON_DST_PITCH_OFFSET:
1152 case RADEON_SRC_PITCH_OFFSET:
1153 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1154 if (r)
1155 return r;
1156 break;
1157 case RADEON_RB3D_DEPTHOFFSET:
1158 r = r100_cs_packet_next_reloc(p, &reloc);
1159 if (r) {
1160 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1161 idx, reg);
1162 r100_cs_dump_packet(p, pkt);
1163 return r;
1164 }
1165 track->zb.robj = reloc->robj;
513bcb46
DA		 1166 track->zb.offset = idx_value;
1167 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1168 break;
1169 case RADEON_RB3D_COLOROFFSET:
1170 r = r100_cs_packet_next_reloc(p, &reloc);
1171 if (r) {
1172 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1173 idx, reg);
1174 r100_cs_dump_packet(p, pkt);
1175 return r;
1176 }
1177 track->cb[0].robj = reloc->robj;
513bcb46
DA		 1178 track->cb[0].offset = idx_value;
1179 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1180 break;
1181 case RADEON_PP_TXOFFSET_0:
1182 case RADEON_PP_TXOFFSET_1:
1183 case RADEON_PP_TXOFFSET_2:
1184 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1185 r = r100_cs_packet_next_reloc(p, &reloc);
1186 if (r) {
1187 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1188 idx, reg);
1189 r100_cs_dump_packet(p, pkt);
1190 return r;
1191 }
513bcb46 1192 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1193 track->textures[i].robj = reloc->robj;
1194 break;
1195 case RADEON_PP_CUBIC_OFFSET_T0_0:
1196 case RADEON_PP_CUBIC_OFFSET_T0_1:
1197 case RADEON_PP_CUBIC_OFFSET_T0_2:
1198 case RADEON_PP_CUBIC_OFFSET_T0_3:
1199 case RADEON_PP_CUBIC_OFFSET_T0_4:
1200 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1201 r = r100_cs_packet_next_reloc(p, &reloc);
1202 if (r) {
1203 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1204 idx, reg);
1205 r100_cs_dump_packet(p, pkt);
1206 return r;
1207 }
513bcb46
DA		 1208 track->textures[0].cube_info[i].offset = idx_value;
1209 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1210 track->textures[0].cube_info[i].robj = reloc->robj;
1211 break;
1212 case RADEON_PP_CUBIC_OFFSET_T1_0:
1213 case RADEON_PP_CUBIC_OFFSET_T1_1:
1214 case RADEON_PP_CUBIC_OFFSET_T1_2:
1215 case RADEON_PP_CUBIC_OFFSET_T1_3:
1216 case RADEON_PP_CUBIC_OFFSET_T1_4:
1217 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1218 r = r100_cs_packet_next_reloc(p, &reloc);
1219 if (r) {
1220 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1221 idx, reg);
1222 r100_cs_dump_packet(p, pkt);
1223 return r;
1224 }
513bcb46
DA		 1225 track->textures[1].cube_info[i].offset = idx_value;
1226 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1227 track->textures[1].cube_info[i].robj = reloc->robj;
1228 break;
1229 case RADEON_PP_CUBIC_OFFSET_T2_0:
1230 case RADEON_PP_CUBIC_OFFSET_T2_1:
1231 case RADEON_PP_CUBIC_OFFSET_T2_2:
1232 case RADEON_PP_CUBIC_OFFSET_T2_3:
1233 case RADEON_PP_CUBIC_OFFSET_T2_4:
1234 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1235 r = r100_cs_packet_next_reloc(p, &reloc);
1236 if (r) {
1237 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1238 idx, reg);
1239 r100_cs_dump_packet(p, pkt);
1240 return r;
1241 }
513bcb46
DA		 1242 track->textures[2].cube_info[i].offset = idx_value;
1243 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1244 track->textures[2].cube_info[i].robj = reloc->robj;
1245 break;
1246 case RADEON_RE_WIDTH_HEIGHT:
513bcb46 1247 track->maxy = ((idx_value >> 16) & 0x7FF);
551ebd83
DA		 1248 break;
1249 case RADEON_RB3D_COLORPITCH:
1250 r = r100_cs_packet_next_reloc(p, &reloc);
1251 if (r) {
1252 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1253 idx, reg);
1254 r100_cs_dump_packet(p, pkt);
1255 return r;
1256 }
e024e110 1257
551ebd83
DA		 1258 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1259 tile_flags |= RADEON_COLOR_TILE_ENABLE;
1260 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1261 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
e024e110 1262
513bcb46 1263 tmp = idx_value & ~(0x7 << 16);
551ebd83
DA		 1264 tmp |= tile_flags;
1265 ib[idx] = tmp;
e024e110 1266
513bcb46 1267 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
551ebd83
DA		 1268 break;
1269 case RADEON_RB3D_DEPTHPITCH:
513bcb46 1270 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
551ebd83
DA		 1271 break;
1272 case RADEON_RB3D_CNTL:
513bcb46 1273 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
551ebd83
DA		 1274 case 7:
1275 case 8:
1276 case 9:
1277 case 11:
1278 case 12:
1279 track->cb[0].cpp = 1;
e024e110 1280 break;
551ebd83
DA		 1281 case 3:
1282 case 4:
1283 case 15:
1284 track->cb[0].cpp = 2;
1285 break;
1286 case 6:
1287 track->cb[0].cpp = 4;
1288 break;
1289 default:
1290 DRM_ERROR("Invalid color buffer format (%d) !\n",
513bcb46 1291 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
551ebd83
DA		 1292 return -EINVAL;
1293 }
513bcb46 1294 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
551ebd83
DA		 1295 break;
1296 case RADEON_RB3D_ZSTENCILCNTL:
513bcb46 1297 switch (idx_value & 0xf) {
551ebd83
DA		 1298 case 0:
1299 track->zb.cpp = 2;
1300 break;
1301 case 2:
1302 case 3:
1303 case 4:
1304 case 5:
1305 case 9:
1306 case 11:
1307 track->zb.cpp = 4;
17782d99 1308 break;
771fe6b9 1309 default:
771fe6b9
JG		 1310 break;
1311 }
551ebd83
DA		 1312 break;
1313 case RADEON_RB3D_ZPASS_ADDR:
1314 r = r100_cs_packet_next_reloc(p, &reloc);
1315 if (r) {
1316 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1317 idx, reg);
1318 r100_cs_dump_packet(p, pkt);
1319 return r;
1320 }
513bcb46 1321 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1322 break;
1323 case RADEON_PP_CNTL:
1324 {
513bcb46 1325 uint32_t temp = idx_value >> 4;
551ebd83
DA		 1326 for (i = 0; i < track->num_texture; i++)
1327 track->textures[i].enabled = !!(temp & (1 << i));
1328 }
1329 break;
1330 case RADEON_SE_VF_CNTL:
513bcb46 1331 track->vap_vf_cntl = idx_value;
551ebd83
DA		 1332 break;
1333 case RADEON_SE_VTX_FMT:
513bcb46 1334 track->vtx_size = r100_get_vtx_size(idx_value);
551ebd83
DA		 1335 break;
1336 case RADEON_PP_TEX_SIZE_0:
1337 case RADEON_PP_TEX_SIZE_1:
1338 case RADEON_PP_TEX_SIZE_2:
1339 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
513bcb46
DA		 1340 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1341 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
551ebd83
DA		 1342 break;
1343 case RADEON_PP_TEX_PITCH_0:
1344 case RADEON_PP_TEX_PITCH_1:
1345 case RADEON_PP_TEX_PITCH_2:
1346 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
513bcb46 1347 track->textures[i].pitch = idx_value + 32;
551ebd83
DA		 1348 break;
1349 case RADEON_PP_TXFILTER_0:
1350 case RADEON_PP_TXFILTER_1:
1351 case RADEON_PP_TXFILTER_2:
1352 i = (reg - RADEON_PP_TXFILTER_0) / 24;
513bcb46 1353 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
551ebd83 1354 >> RADEON_MAX_MIP_LEVEL_SHIFT);
513bcb46 1355 tmp = (idx_value >> 23) & 0x7;
551ebd83
DA		 1356 if (tmp == 2 || tmp == 6)
1357 track->textures[i].roundup_w = false;
513bcb46 1358 tmp = (idx_value >> 27) & 0x7;
551ebd83
DA		 1359 if (tmp == 2 || tmp == 6)
1360 track->textures[i].roundup_h = false;
1361 break;
1362 case RADEON_PP_TXFORMAT_0:
1363 case RADEON_PP_TXFORMAT_1:
1364 case RADEON_PP_TXFORMAT_2:
1365 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
513bcb46 1366 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
551ebd83
DA		 1367 track->textures[i].use_pitch = 1;
1368 } else {
1369 track->textures[i].use_pitch = 0;
513bcb46
DA		 1370 track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1371 track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
551ebd83 1372 }
513bcb46 1373 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
551ebd83 1374 track->textures[i].tex_coord_type = 2;
513bcb46 1375 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
551ebd83
DA		 1376 case RADEON_TXFORMAT_I8:
1377 case RADEON_TXFORMAT_RGB332:
1378 case RADEON_TXFORMAT_Y8:
1379 track->textures[i].cpp = 1;
1380 break;
1381 case RADEON_TXFORMAT_AI88:
1382 case RADEON_TXFORMAT_ARGB1555:
1383 case RADEON_TXFORMAT_RGB565:
1384 case RADEON_TXFORMAT_ARGB4444:
1385 case RADEON_TXFORMAT_VYUY422:
1386 case RADEON_TXFORMAT_YVYU422:
1387 case RADEON_TXFORMAT_DXT1:
1388 case RADEON_TXFORMAT_SHADOW16:
1389 case RADEON_TXFORMAT_LDUDV655:
1390 case RADEON_TXFORMAT_DUDV88:
1391 track->textures[i].cpp = 2;
771fe6b9 1392 break;
551ebd83
DA		 1393 case RADEON_TXFORMAT_ARGB8888:
1394 case RADEON_TXFORMAT_RGBA8888:
1395 case RADEON_TXFORMAT_DXT23:
1396 case RADEON_TXFORMAT_DXT45:
1397 case RADEON_TXFORMAT_SHADOW32:
1398 case RADEON_TXFORMAT_LDUDUV8888:
1399 track->textures[i].cpp = 4;
1400 break;
1401 }
513bcb46
DA		 1402 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1403 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
551ebd83
DA		 1404 break;
1405 case RADEON_PP_CUBIC_FACES_0:
1406 case RADEON_PP_CUBIC_FACES_1:
1407 case RADEON_PP_CUBIC_FACES_2:
513bcb46 1408 tmp = idx_value;
551ebd83
DA		 1409 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1410 for (face = 0; face < 4; face++) {
1411 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1412 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
771fe6b9 1413 }
551ebd83
DA		 1414 break;
1415 default:
1416 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1417 reg, idx);
1418 return -EINVAL;
771fe6b9
JG		 1419 }
1420 return 0;
1421}
1422
068a117c
JG		 1423int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1424 struct radeon_cs_packet *pkt,
1425 struct radeon_object *robj)
1426{
068a117c 1427 unsigned idx;
513bcb46 1428 u32 value;
068a117c 1429 idx = pkt->idx + 1;
513bcb46
DA		 1430 value = radeon_get_ib_value(p, idx + 2);
1431 if ((value + 1) > radeon_object_size(robj)) {
068a117c
JG		 1432 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1433 "(need %u have %lu) !\n",
513bcb46 1434 value + 1,
068a117c
JG		 1435 radeon_object_size(robj));
1436 return -EINVAL;
1437 }
1438 return 0;
1439}
1440
771fe6b9
JG		 1441static int r100_packet3_check(struct radeon_cs_parser *p,
1442 struct radeon_cs_packet *pkt)
1443{
771fe6b9 1444 struct radeon_cs_reloc *reloc;
551ebd83 1445 struct r100_cs_track *track;
771fe6b9 1446 unsigned idx;
771fe6b9
JG		 1447 volatile uint32_t *ib;
1448 int r;
1449
1450 ib = p->ib->ptr;
771fe6b9 1451 idx = pkt->idx + 1;
551ebd83 1452 track = (struct r100_cs_track *)p->track;
771fe6b9
JG		 1453 switch (pkt->opcode) {
1454 case PACKET3_3D_LOAD_VBPNTR:
513bcb46
DA		 1455 r = r100_packet3_load_vbpntr(p, pkt, idx);
1456 if (r)
1457 return r;
771fe6b9
JG		 1458 break;
1459 case PACKET3_INDX_BUFFER:
1460 r = r100_cs_packet_next_reloc(p, &reloc);
1461 if (r) {
1462 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1463 r100_cs_dump_packet(p, pkt);
1464 return r;
1465 }
513bcb46 1466 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
068a117c
JG		 1467 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1468 if (r) {
1469 return r;
1470 }
771fe6b9
JG		 1471 break;
1472 case 0x23:
771fe6b9
JG		 1473 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1474 r = r100_cs_packet_next_reloc(p, &reloc);
1475 if (r) {
1476 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1477 r100_cs_dump_packet(p, pkt);
1478 return r;
1479 }
513bcb46 1480 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
551ebd83 1481 track->num_arrays = 1;
513bcb46 1482 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
551ebd83
DA		 1483
1484 track->arrays[0].robj = reloc->robj;
1485 track->arrays[0].esize = track->vtx_size;
1486
513bcb46 1487 track->max_indx = radeon_get_ib_value(p, idx+1);
551ebd83 1488
513bcb46 1489 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
551ebd83
DA		 1490 track->immd_dwords = pkt->count - 1;
1491 r = r100_cs_track_check(p->rdev, track);
1492 if (r)
1493 return r;
771fe6b9
JG		 1494 break;
1495 case PACKET3_3D_DRAW_IMMD:
513bcb46 1496 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
551ebd83
DA		 1497 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1498 return -EINVAL;
1499 }
513bcb46 1500 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
551ebd83
DA		 1501 track->immd_dwords = pkt->count - 1;
1502 r = r100_cs_track_check(p->rdev, track);
1503 if (r)
1504 return r;
1505 break;
771fe6b9
JG		 1506 /* triggers drawing using in-packet vertex data */
1507 case PACKET3_3D_DRAW_IMMD_2:
513bcb46 1508 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
551ebd83
DA		 1509 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1510 return -EINVAL;
1511 }
513bcb46 1512 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
551ebd83
DA		 1513 track->immd_dwords = pkt->count;
1514 r = r100_cs_track_check(p->rdev, track);
1515 if (r)
1516 return r;
1517 break;
771fe6b9
JG		 1518 /* triggers drawing using in-packet vertex data */
1519 case PACKET3_3D_DRAW_VBUF_2:
513bcb46 1520 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
551ebd83
DA		 1521 r = r100_cs_track_check(p->rdev, track);
1522 if (r)
1523 return r;
1524 break;
771fe6b9
JG		 1525 /* triggers drawing of vertex buffers setup elsewhere */
1526 case PACKET3_3D_DRAW_INDX_2:
513bcb46 1527 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
551ebd83
DA		 1528 r = r100_cs_track_check(p->rdev, track);
1529 if (r)
1530 return r;
1531 break;
771fe6b9
JG		 1532 /* triggers drawing using indices to vertex buffer */
1533 case PACKET3_3D_DRAW_VBUF:
513bcb46 1534 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
551ebd83
DA		 1535 r = r100_cs_track_check(p->rdev, track);
1536 if (r)
1537 return r;
1538 break;
771fe6b9
JG		 1539 /* triggers drawing of vertex buffers setup elsewhere */
1540 case PACKET3_3D_DRAW_INDX:
513bcb46 1541 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
551ebd83
DA		 1542 r = r100_cs_track_check(p->rdev, track);
1543 if (r)
1544 return r;
1545 break;
771fe6b9
JG		 1546 /* triggers drawing using indices to vertex buffer */
1547 case PACKET3_NOP:
1548 break;
1549 default:
1550 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1551 return -EINVAL;
1552 }
1553 return 0;
1554}
1555
1556int r100_cs_parse(struct radeon_cs_parser *p)
1557{
1558 struct radeon_cs_packet pkt;
9f022ddf 1559 struct r100_cs_track *track;
771fe6b9
JG		 1560 int r;
1561
9f022ddf
JG		 1562 track = kzalloc(sizeof(*track), GFP_KERNEL);
1563 r100_cs_track_clear(p->rdev, track);
1564 p->track = track;
771fe6b9
JG		 1565 do {
1566 r = r100_cs_packet_parse(p, &pkt, p->idx);
1567 if (r) {
1568 return r;
1569 }
1570 p->idx += pkt.count + 2;
1571 switch (pkt.type) {
068a117c 1572 case PACKET_TYPE0:
551ebd83
DA		 1573 if (p->rdev->family >= CHIP_R200)
1574 r = r100_cs_parse_packet0(p, &pkt,
1575 p->rdev->config.r100.reg_safe_bm,
1576 p->rdev->config.r100.reg_safe_bm_size,
1577 &r200_packet0_check);
1578 else
1579 r = r100_cs_parse_packet0(p, &pkt,
1580 p->rdev->config.r100.reg_safe_bm,
1581 p->rdev->config.r100.reg_safe_bm_size,
1582 &r100_packet0_check);
068a117c
JG		 1583 break;
1584 case PACKET_TYPE2:
1585 break;
1586 case PACKET_TYPE3:
1587 r = r100_packet3_check(p, &pkt);
1588 break;
1589 default:
1590 DRM_ERROR("Unknown packet type %d !\n",
1591 pkt.type);
1592 return -EINVAL;
771fe6b9
JG		 1593 }
1594 if (r) {
1595 return r;
1596 }
1597 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1598 return 0;
1599}
1600
1601
1602/*
1603 * Global GPU functions
1604 */
1605void r100_errata(struct radeon_device *rdev)
1606{
1607 rdev->pll_errata = 0;
1608
1609 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
1610 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
1611 }
1612
1613 if (rdev->family == CHIP_RV100 ||
1614 rdev->family == CHIP_RS100 ||
1615 rdev->family == CHIP_RS200) {
1616 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
1617 }
1618}
1619
1620/* Wait for vertical sync on primary CRTC */
1621void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
1622{
1623 uint32_t crtc_gen_cntl, tmp;
1624 int i;
1625
1626 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
1627 if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
1628 !(crtc_gen_cntl & RADEON_CRTC_EN)) {
1629 return;
1630 }
1631 /* Clear the CRTC_VBLANK_SAVE bit */
1632 WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
1633 for (i = 0; i < rdev->usec_timeout; i++) {
1634 tmp = RREG32(RADEON_CRTC_STATUS);
1635 if (tmp & RADEON_CRTC_VBLANK_SAVE) {
1636 return;
1637 }
1638 DRM_UDELAY(1);
1639 }
1640}
1641
1642/* Wait for vertical sync on secondary CRTC */
1643void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
1644{
1645 uint32_t crtc2_gen_cntl, tmp;
1646 int i;
1647
1648 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1649 if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
1650 !(crtc2_gen_cntl & RADEON_CRTC2_EN))
1651 return;
1652
1653 /* Clear the CRTC_VBLANK_SAVE bit */
1654 WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
1655 for (i = 0; i < rdev->usec_timeout; i++) {
1656 tmp = RREG32(RADEON_CRTC2_STATUS);
1657 if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
1658 return;
1659 }
1660 DRM_UDELAY(1);
1661 }
1662}
1663
1664int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
1665{
1666 unsigned i;
1667 uint32_t tmp;
1668
1669 for (i = 0; i < rdev->usec_timeout; i++) {
1670 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
1671 if (tmp >= n) {
1672 return 0;
1673 }
1674 DRM_UDELAY(1);
1675 }
1676 return -1;
1677}
1678
1679int r100_gui_wait_for_idle(struct radeon_device *rdev)
1680{
1681 unsigned i;
1682 uint32_t tmp;
1683
1684 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
1685 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
1686 " Bad things might happen.\n");
1687 }
1688 for (i = 0; i < rdev->usec_timeout; i++) {
1689 tmp = RREG32(RADEON_RBBM_STATUS);
1690 if (!(tmp & (1 << 31))) {
1691 return 0;
1692 }
1693 DRM_UDELAY(1);
1694 }
1695 return -1;
1696}
1697
1698int r100_mc_wait_for_idle(struct radeon_device *rdev)
1699{
1700 unsigned i;
1701 uint32_t tmp;
1702
1703 for (i = 0; i < rdev->usec_timeout; i++) {
1704 /* read MC_STATUS */
1705 tmp = RREG32(0x0150);
1706 if (tmp & (1 << 2)) {
1707 return 0;
1708 }
1709 DRM_UDELAY(1);
1710 }
1711 return -1;
1712}
1713
1714void r100_gpu_init(struct radeon_device *rdev)
1715{
1716 /* TODO: anythings to do here ? pipes ? */
1717 r100_hdp_reset(rdev);
1718}
1719
1720void r100_hdp_reset(struct radeon_device *rdev)
1721{
1722 uint32_t tmp;
1723
1724 tmp = RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL;
1725 tmp |= (7 << 28);
1726 WREG32(RADEON_HOST_PATH_CNTL, tmp | RADEON_HDP_SOFT_RESET | RADEON_HDP_READ_BUFFER_INVALIDATE);
1727 (void)RREG32(RADEON_HOST_PATH_CNTL);
1728 udelay(200);
1729 WREG32(RADEON_RBBM_SOFT_RESET, 0);
1730 WREG32(RADEON_HOST_PATH_CNTL, tmp);
1731 (void)RREG32(RADEON_HOST_PATH_CNTL);
1732}
1733
1734int r100_rb2d_reset(struct radeon_device *rdev)
1735{
1736 uint32_t tmp;
1737 int i;
1738
1739 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_E2);
1740 (void)RREG32(RADEON_RBBM_SOFT_RESET);
1741 udelay(200);
1742 WREG32(RADEON_RBBM_SOFT_RESET, 0);
1743 /* Wait to prevent race in RBBM_STATUS */
1744 mdelay(1);
1745 for (i = 0; i < rdev->usec_timeout; i++) {
1746 tmp = RREG32(RADEON_RBBM_STATUS);
1747 if (!(tmp & (1 << 26))) {
1748 DRM_INFO("RB2D reset succeed (RBBM_STATUS=0x%08X)\n",
1749 tmp);
1750 return 0;
1751 }
1752 DRM_UDELAY(1);
1753 }
1754 tmp = RREG32(RADEON_RBBM_STATUS);
1755 DRM_ERROR("Failed to reset RB2D (RBBM_STATUS=0x%08X)!\n", tmp);
1756 return -1;
1757}
1758
1759int r100_gpu_reset(struct radeon_device *rdev)
1760{
1761 uint32_t status;
1762
1763 /* reset order likely matter */
1764 status = RREG32(RADEON_RBBM_STATUS);
1765 /* reset HDP */
1766 r100_hdp_reset(rdev);
1767 /* reset rb2d */
1768 if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
1769 r100_rb2d_reset(rdev);
1770 }
1771 /* TODO: reset 3D engine */
1772 /* reset CP */
1773 status = RREG32(RADEON_RBBM_STATUS);
1774 if (status & (1 << 16)) {
1775 r100_cp_reset(rdev);
1776 }
1777 /* Check if GPU is idle */
1778 status = RREG32(RADEON_RBBM_STATUS);
1779 if (status & (1 << 31)) {
1780 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
1781 return -1;
1782 }
1783 DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
1784 return 0;
1785}
1786
1787
1788/*
1789 * VRAM info
1790 */
1791static void r100_vram_get_type(struct radeon_device *rdev)
1792{
1793 uint32_t tmp;
1794
1795 rdev->mc.vram_is_ddr = false;
1796 if (rdev->flags & RADEON_IS_IGP)
1797 rdev->mc.vram_is_ddr = true;
1798 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
1799 rdev->mc.vram_is_ddr = true;
1800 if ((rdev->family == CHIP_RV100) ||
1801 (rdev->family == CHIP_RS100) ||
1802 (rdev->family == CHIP_RS200)) {
1803 tmp = RREG32(RADEON_MEM_CNTL);
1804 if (tmp & RV100_HALF_MODE) {
1805 rdev->mc.vram_width = 32;
1806 } else {
1807 rdev->mc.vram_width = 64;
1808 }
1809 if (rdev->flags & RADEON_SINGLE_CRTC) {
1810 rdev->mc.vram_width /= 4;
1811 rdev->mc.vram_is_ddr = true;
1812 }
1813 } else if (rdev->family <= CHIP_RV280) {
1814 tmp = RREG32(RADEON_MEM_CNTL);
1815 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
1816 rdev->mc.vram_width = 128;
1817 } else {
1818 rdev->mc.vram_width = 64;
1819 }
1820 } else {
1821 /* newer IGPs */
1822 rdev->mc.vram_width = 128;
1823 }
1824}
1825
2a0f8918 1826static u32 r100_get_accessible_vram(struct radeon_device *rdev)
771fe6b9 1827{
2a0f8918
DA		 1828 u32 aper_size;
1829 u8 byte;
1830
1831 aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
1832
1833 /* Set HDP_APER_CNTL only on cards that are known not to be broken,
1834 * that is has the 2nd generation multifunction PCI interface
1835 */
1836 if (rdev->family == CHIP_RV280 ||
1837 rdev->family >= CHIP_RV350) {
1838 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
1839 ~RADEON_HDP_APER_CNTL);
1840 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
1841 return aper_size * 2;
1842 }
1843
1844 /* Older cards have all sorts of funny issues to deal with. First
1845 * check if it's a multifunction card by reading the PCI config
1846 * header type... Limit those to one aperture size
1847 */
1848 pci_read_config_byte(rdev->pdev, 0xe, &byte);
1849 if (byte & 0x80) {
1850 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
1851 DRM_INFO("Limiting VRAM to one aperture\n");
1852 return aper_size;
1853 }
1854
1855 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
1856 * have set it up. We don't write this as it's broken on some ASICs but
1857 * we expect the BIOS to have done the right thing (might be too optimistic...)
1858 */
1859 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
1860 return aper_size * 2;
1861 return aper_size;
1862}
1863
1864void r100_vram_init_sizes(struct radeon_device *rdev)
1865{
1866 u64 config_aper_size;
1867 u32 accessible;
1868
1869 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
771fe6b9
JG		 1870
1871 if (rdev->flags & RADEON_IS_IGP) {
1872 uint32_t tom;
1873 /* read NB_TOM to get the amount of ram stolen for the GPU */
1874 tom = RREG32(RADEON_NB_TOM);
7a50f01a 1875 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
3e43d821
DA		 1876 /* for IGPs we need to keep VRAM where it was put by the BIOS */
1877 rdev->mc.vram_location = (tom & 0xffff) << 16;
7a50f01a
DA		 1878 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
1879 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
771fe6b9 1880 } else {
7a50f01a 1881 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
771fe6b9
JG		 1882 /* Some production boards of m6 will report 0
1883 * if it's 8 MB
1884 */
7a50f01a
DA		 1885 if (rdev->mc.real_vram_size == 0) {
1886 rdev->mc.real_vram_size = 8192 * 1024;
1887 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
771fe6b9 1888 }
3e43d821
DA		 1889 /* let driver place VRAM */
1890 rdev->mc.vram_location = 0xFFFFFFFFUL;
2a0f8918
DA		 1891 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
1892 * Novell bug 204882 + along with lots of ubuntu ones */
7a50f01a
DA		 1893 if (config_aper_size > rdev->mc.real_vram_size)
1894 rdev->mc.mc_vram_size = config_aper_size;
1895 else
1896 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
771fe6b9
JG		 1897 }
1898
2a0f8918
DA		 1899 /* work out accessible VRAM */
1900 accessible = r100_get_accessible_vram(rdev);
1901
771fe6b9
JG		 1902 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
1903 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
2a0f8918
DA		 1904
1905 if (accessible > rdev->mc.aper_size)
1906 accessible = rdev->mc.aper_size;
1907
7a50f01a
DA		 1908 if (rdev->mc.mc_vram_size > rdev->mc.aper_size)
1909 rdev->mc.mc_vram_size = rdev->mc.aper_size;
1910
1911 if (rdev->mc.real_vram_size > rdev->mc.aper_size)
1912 rdev->mc.real_vram_size = rdev->mc.aper_size;
2a0f8918
DA		 1913}
1914
1915void r100_vram_info(struct radeon_device *rdev)
1916{
1917 r100_vram_get_type(rdev);
1918
1919 r100_vram_init_sizes(rdev);
771fe6b9
JG		 1920}
1921
1922
1923/*
1924 * Indirect registers accessor
1925 */
1926void r100_pll_errata_after_index(struct radeon_device *rdev)
1927{
1928 if (!(rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS)) {
1929 return;
1930 }
1931 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
1932 (void)RREG32(RADEON_CRTC_GEN_CNTL);
1933}
1934
1935static void r100_pll_errata_after_data(struct radeon_device *rdev)
1936{
1937 /* This workarounds is necessary on RV100, RS100 and RS200 chips
1938 * or the chip could hang on a subsequent access
1939 */
1940 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
1941 udelay(5000);
1942 }
1943
1944 /* This function is required to workaround a hardware bug in some (all?)
1945 * revisions of the R300. This workaround should be called after every
1946 * CLOCK_CNTL_INDEX register access. If not, register reads afterward
1947 * may not be correct.
1948 */
1949 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
1950 uint32_t save, tmp;
1951
1952 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
1953 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
1954 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
1955 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
1956 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
1957 }
1958}
1959
1960uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
1961{
1962 uint32_t data;
1963
1964 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
1965 r100_pll_errata_after_index(rdev);
1966 data = RREG32(RADEON_CLOCK_CNTL_DATA);
1967 r100_pll_errata_after_data(rdev);
1968 return data;
1969}
1970
1971void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1972{
1973 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
1974 r100_pll_errata_after_index(rdev);
1975 WREG32(RADEON_CLOCK_CNTL_DATA, v);
1976 r100_pll_errata_after_data(rdev);
1977}
1978
068a117c
JG		 1979int r100_init(struct radeon_device *rdev)
1980{
551ebd83
DA		 1981 if (ASIC_IS_RN50(rdev)) {
1982 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
1983 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
1984 } else if (rdev->family < CHIP_R200) {
1985 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
1986 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
1987 } else {
1988 return r200_init(rdev);
1989 }
068a117c
JG		 1990 return 0;
1991}
1992
771fe6b9
JG		 1993/*
1994 * Debugfs info
1995 */
1996#if defined(CONFIG_DEBUG_FS)
1997static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
1998{
1999 struct drm_info_node *node = (struct drm_info_node *) m->private;
2000 struct drm_device *dev = node->minor->dev;
2001 struct radeon_device *rdev = dev->dev_private;
2002 uint32_t reg, value;
2003 unsigned i;
2004
2005 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2006 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2007 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2008 for (i = 0; i < 64; i++) {
2009 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2010 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2011 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2012 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2013 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2014 }
2015 return 0;
2016}
2017
2018static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2019{
2020 struct drm_info_node *node = (struct drm_info_node *) m->private;
2021 struct drm_device *dev = node->minor->dev;
2022 struct radeon_device *rdev = dev->dev_private;
2023 uint32_t rdp, wdp;
2024 unsigned count, i, j;
2025
2026 radeon_ring_free_size(rdev);
2027 rdp = RREG32(RADEON_CP_RB_RPTR);
2028 wdp = RREG32(RADEON_CP_RB_WPTR);
2029 count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
2030 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2031 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2032 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2033 seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
2034 seq_printf(m, "%u dwords in ring\n", count);
2035 for (j = 0; j <= count; j++) {
2036 i = (rdp + j) & rdev->cp.ptr_mask;
2037 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
2038 }
2039 return 0;
2040}
2041
2042
2043static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2044{
2045 struct drm_info_node *node = (struct drm_info_node *) m->private;
2046 struct drm_device *dev = node->minor->dev;
2047 struct radeon_device *rdev = dev->dev_private;
2048 uint32_t csq_stat, csq2_stat, tmp;
2049 unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2050 unsigned i;
2051
2052 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2053 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2054 csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2055 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2056 r_rptr = (csq_stat >> 0) & 0x3ff;
2057 r_wptr = (csq_stat >> 10) & 0x3ff;
2058 ib1_rptr = (csq_stat >> 20) & 0x3ff;
2059 ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2060 ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2061 ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2062 seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2063 seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2064 seq_printf(m, "Ring rptr %u\n", r_rptr);
2065 seq_printf(m, "Ring wptr %u\n", r_wptr);
2066 seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
2067 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2068 seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
2069 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
2070 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
2071 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
2072 seq_printf(m, "Ring fifo:\n");
2073 for (i = 0; i < 256; i++) {
2074 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2075 tmp = RREG32(RADEON_CP_CSQ_DATA);
2076 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
2077 }
2078 seq_printf(m, "Indirect1 fifo:\n");
2079 for (i = 256; i <= 512; i++) {
2080 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2081 tmp = RREG32(RADEON_CP_CSQ_DATA);
2082 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
2083 }
2084 seq_printf(m, "Indirect2 fifo:\n");
2085 for (i = 640; i < ib1_wptr; i++) {
2086 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2087 tmp = RREG32(RADEON_CP_CSQ_DATA);
2088 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
2089 }
2090 return 0;
2091}
2092
2093static int r100_debugfs_mc_info(struct seq_file *m, void *data)
2094{
2095 struct drm_info_node *node = (struct drm_info_node *) m->private;
2096 struct drm_device *dev = node->minor->dev;
2097 struct radeon_device *rdev = dev->dev_private;
2098 uint32_t tmp;
2099
2100 tmp = RREG32(RADEON_CONFIG_MEMSIZE);
2101 seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
2102 tmp = RREG32(RADEON_MC_FB_LOCATION);
2103 seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
2104 tmp = RREG32(RADEON_BUS_CNTL);
2105 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
2106 tmp = RREG32(RADEON_MC_AGP_LOCATION);
2107 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
2108 tmp = RREG32(RADEON_AGP_BASE);
2109 seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
2110 tmp = RREG32(RADEON_HOST_PATH_CNTL);
2111 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
2112 tmp = RREG32(0x01D0);
2113 seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
2114 tmp = RREG32(RADEON_AIC_LO_ADDR);
2115 seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
2116 tmp = RREG32(RADEON_AIC_HI_ADDR);
2117 seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
2118 tmp = RREG32(0x01E4);
2119 seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
2120 return 0;
2121}
2122
2123static struct drm_info_list r100_debugfs_rbbm_list[] = {
2124 {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
2125};
2126
2127static struct drm_info_list r100_debugfs_cp_list[] = {
2128 {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
2129 {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
2130};
2131
2132static struct drm_info_list r100_debugfs_mc_info_list[] = {
2133 {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
2134};
2135#endif
2136
2137int r100_debugfs_rbbm_init(struct radeon_device *rdev)
2138{
2139#if defined(CONFIG_DEBUG_FS)
2140 return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
2141#else
2142 return 0;
2143#endif
2144}
2145
2146int r100_debugfs_cp_init(struct radeon_device *rdev)
2147{
2148#if defined(CONFIG_DEBUG_FS)
2149 return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
2150#else
2151 return 0;
2152#endif
2153}
2154
2155int r100_debugfs_mc_info_init(struct radeon_device *rdev)
2156{
2157#if defined(CONFIG_DEBUG_FS)
2158 return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
2159#else
2160 return 0;
2161#endif
2162}
e024e110
DA		 2163
2164int r100_set_surface_reg(struct radeon_device *rdev, int reg,
2165 uint32_t tiling_flags, uint32_t pitch,
2166 uint32_t offset, uint32_t obj_size)
2167{
2168 int surf_index = reg * 16;
2169 int flags = 0;
2170
2171 /* r100/r200 divide by 16 */
2172 if (rdev->family < CHIP_R300)
2173 flags = pitch / 16;
2174 else
2175 flags = pitch / 8;
2176
2177 if (rdev->family <= CHIP_RS200) {
2178 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2179 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2180 flags |= RADEON_SURF_TILE_COLOR_BOTH;
2181 if (tiling_flags & RADEON_TILING_MACRO)
2182 flags |= RADEON_SURF_TILE_COLOR_MACRO;
2183 } else if (rdev->family <= CHIP_RV280) {
2184 if (tiling_flags & (RADEON_TILING_MACRO))
2185 flags |= R200_SURF_TILE_COLOR_MACRO;
2186 if (tiling_flags & RADEON_TILING_MICRO)
2187 flags |= R200_SURF_TILE_COLOR_MICRO;
2188 } else {
2189 if (tiling_flags & RADEON_TILING_MACRO)
2190 flags |= R300_SURF_TILE_MACRO;
2191 if (tiling_flags & RADEON_TILING_MICRO)
2192 flags |= R300_SURF_TILE_MICRO;
2193 }
2194
c88f9f0c
MD		 2195 if (tiling_flags & RADEON_TILING_SWAP_16BIT)
2196 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
2197 if (tiling_flags & RADEON_TILING_SWAP_32BIT)
2198 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
2199
e024e110
DA		 2200 DRM_DEBUG("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
2201 WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
2202 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
2203 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
2204 return 0;
2205}
2206
2207void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
2208{
2209 int surf_index = reg * 16;
2210 WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
2211}
c93bb85b
JG		 2212
2213void r100_bandwidth_update(struct radeon_device *rdev)
2214{
2215 fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
2216 fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
2217 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
2218 uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
2219 fixed20_12 memtcas_ff[8] = {
2220 fixed_init(1),
2221 fixed_init(2),
2222 fixed_init(3),
2223 fixed_init(0),
2224 fixed_init_half(1),
2225 fixed_init_half(2),
2226 fixed_init(0),
2227 };
2228 fixed20_12 memtcas_rs480_ff[8] = {
2229 fixed_init(0),
2230 fixed_init(1),
2231 fixed_init(2),
2232 fixed_init(3),
2233 fixed_init(0),
2234 fixed_init_half(1),
2235 fixed_init_half(2),
2236 fixed_init_half(3),
2237 };
2238 fixed20_12 memtcas2_ff[8] = {
2239 fixed_init(0),
2240 fixed_init(1),
2241 fixed_init(2),
2242 fixed_init(3),
2243 fixed_init(4),
2244 fixed_init(5),
2245 fixed_init(6),
2246 fixed_init(7),
2247 };
2248 fixed20_12 memtrbs[8] = {
2249 fixed_init(1),
2250 fixed_init_half(1),
2251 fixed_init(2),
2252 fixed_init_half(2),
2253 fixed_init(3),
2254 fixed_init_half(3),
2255 fixed_init(4),
2256 fixed_init_half(4)
2257 };
2258 fixed20_12 memtrbs_r4xx[8] = {
2259 fixed_init(4),
2260 fixed_init(5),
2261 fixed_init(6),
2262 fixed_init(7),
2263 fixed_init(8),
2264 fixed_init(9),
2265 fixed_init(10),
2266 fixed_init(11)
2267 };
2268 fixed20_12 min_mem_eff;
2269 fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
2270 fixed20_12 cur_latency_mclk, cur_latency_sclk;
2271 fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
2272 disp_drain_rate2, read_return_rate;
2273 fixed20_12 time_disp1_drop_priority;
2274 int c;
2275 int cur_size = 16; /* in octawords */
2276 int critical_point = 0, critical_point2;
2277/* uint32_t read_return_rate, time_disp1_drop_priority; */
2278 int stop_req, max_stop_req;
2279 struct drm_display_mode *mode1 = NULL;
2280 struct drm_display_mode *mode2 = NULL;
2281 uint32_t pixel_bytes1 = 0;
2282 uint32_t pixel_bytes2 = 0;
2283
2284 if (rdev->mode_info.crtcs[0]->base.enabled) {
2285 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
2286 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
2287 }
2288 if (rdev->mode_info.crtcs[1]->base.enabled) {
2289 mode2 = &rdev->mode_info.crtcs[1]->base.mode;
2290 pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
2291 }
2292
2293 min_mem_eff.full = rfixed_const_8(0);
2294 /* get modes */
2295 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
2296 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
2297 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
2298 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
2299 /* check crtc enables */
2300 if (mode2)
2301 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
2302 if (mode1)
2303 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
2304 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
2305 }
2306
2307 /*
2308 * determine is there is enough bw for current mode
2309 */
2310 mclk_ff.full = rfixed_const(rdev->clock.default_mclk);
2311 temp_ff.full = rfixed_const(100);
2312 mclk_ff.full = rfixed_div(mclk_ff, temp_ff);
2313 sclk_ff.full = rfixed_const(rdev->clock.default_sclk);
2314 sclk_ff.full = rfixed_div(sclk_ff, temp_ff);
2315
2316 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
2317 temp_ff.full = rfixed_const(temp);
2318 mem_bw.full = rfixed_mul(mclk_ff, temp_ff);
2319
2320 pix_clk.full = 0;
2321 pix_clk2.full = 0;
2322 peak_disp_bw.full = 0;
2323 if (mode1) {
2324 temp_ff.full = rfixed_const(1000);
2325 pix_clk.full = rfixed_const(mode1->clock); /* convert to fixed point */
2326 pix_clk.full = rfixed_div(pix_clk, temp_ff);
2327 temp_ff.full = rfixed_const(pixel_bytes1);
2328 peak_disp_bw.full += rfixed_mul(pix_clk, temp_ff);
2329 }
2330 if (mode2) {
2331 temp_ff.full = rfixed_const(1000);
2332 pix_clk2.full = rfixed_const(mode2->clock); /* convert to fixed point */
2333 pix_clk2.full = rfixed_div(pix_clk2, temp_ff);
2334 temp_ff.full = rfixed_const(pixel_bytes2);
2335 peak_disp_bw.full += rfixed_mul(pix_clk2, temp_ff);
2336 }
2337
2338 mem_bw.full = rfixed_mul(mem_bw, min_mem_eff);
2339 if (peak_disp_bw.full >= mem_bw.full) {
2340 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
2341 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
2342 }
2343
2344 /* Get values from the EXT_MEM_CNTL register...converting its contents. */
2345 temp = RREG32(RADEON_MEM_TIMING_CNTL);
2346 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
2347 mem_trcd = ((temp >> 2) & 0x3) + 1;
2348 mem_trp = ((temp & 0x3)) + 1;
2349 mem_tras = ((temp & 0x70) >> 4) + 1;
2350 } else if (rdev->family == CHIP_R300 ||
2351 rdev->family == CHIP_R350) { /* r300, r350 */
2352 mem_trcd = (temp & 0x7) + 1;
2353 mem_trp = ((temp >> 8) & 0x7) + 1;
2354 mem_tras = ((temp >> 11) & 0xf) + 4;
2355 } else if (rdev->family == CHIP_RV350 ||
2356 rdev->family <= CHIP_RV380) {
2357 /* rv3x0 */
2358 mem_trcd = (temp & 0x7) + 3;
2359 mem_trp = ((temp >> 8) & 0x7) + 3;
2360 mem_tras = ((temp >> 11) & 0xf) + 6;
2361 } else if (rdev->family == CHIP_R420 ||
2362 rdev->family == CHIP_R423 ||
2363 rdev->family == CHIP_RV410) {
2364 /* r4xx */
2365 mem_trcd = (temp & 0xf) + 3;
2366 if (mem_trcd > 15)
2367 mem_trcd = 15;
2368 mem_trp = ((temp >> 8) & 0xf) + 3;
2369 if (mem_trp > 15)
2370 mem_trp = 15;
2371 mem_tras = ((temp >> 12) & 0x1f) + 6;
2372 if (mem_tras > 31)
2373 mem_tras = 31;
2374 } else { /* RV200, R200 */
2375 mem_trcd = (temp & 0x7) + 1;
2376 mem_trp = ((temp >> 8) & 0x7) + 1;
2377 mem_tras = ((temp >> 12) & 0xf) + 4;
2378 }
2379 /* convert to FF */
2380 trcd_ff.full = rfixed_const(mem_trcd);
2381 trp_ff.full = rfixed_const(mem_trp);
2382 tras_ff.full = rfixed_const(mem_tras);
2383
2384 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
2385 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2386 data = (temp & (7 << 20)) >> 20;
2387 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
2388 if (rdev->family == CHIP_RS480) /* don't think rs400 */
2389 tcas_ff = memtcas_rs480_ff[data];
2390 else
2391 tcas_ff = memtcas_ff[data];
2392 } else
2393 tcas_ff = memtcas2_ff[data];
2394
2395 if (rdev->family == CHIP_RS400 ||
2396 rdev->family == CHIP_RS480) {
2397 /* extra cas latency stored in bits 23-25 0-4 clocks */
2398 data = (temp >> 23) & 0x7;
2399 if (data < 5)
2400 tcas_ff.full += rfixed_const(data);
2401 }
2402
2403 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2404 /* on the R300, Tcas is included in Trbs.
2405 */
2406 temp = RREG32(RADEON_MEM_CNTL);
2407 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
2408 if (data == 1) {
2409 if (R300_MEM_USE_CD_CH_ONLY & temp) {
2410 temp = RREG32(R300_MC_IND_INDEX);
2411 temp &= ~R300_MC_IND_ADDR_MASK;
2412 temp |= R300_MC_READ_CNTL_CD_mcind;
2413 WREG32(R300_MC_IND_INDEX, temp);
2414 temp = RREG32(R300_MC_IND_DATA);
2415 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
2416 } else {
2417 temp = RREG32(R300_MC_READ_CNTL_AB);
2418 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2419 }
2420 } else {
2421 temp = RREG32(R300_MC_READ_CNTL_AB);
2422 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2423 }
2424 if (rdev->family == CHIP_RV410 ||
2425 rdev->family == CHIP_R420 ||
2426 rdev->family == CHIP_R423)
2427 trbs_ff = memtrbs_r4xx[data];
2428 else
2429 trbs_ff = memtrbs[data];
2430 tcas_ff.full += trbs_ff.full;
2431 }
2432
2433 sclk_eff_ff.full = sclk_ff.full;
2434
2435 if (rdev->flags & RADEON_IS_AGP) {
2436 fixed20_12 agpmode_ff;
2437 agpmode_ff.full = rfixed_const(radeon_agpmode);
2438 temp_ff.full = rfixed_const_666(16);
2439 sclk_eff_ff.full -= rfixed_mul(agpmode_ff, temp_ff);
2440 }
2441 /* TODO PCIE lanes may affect this - agpmode == 16?? */
2442
2443 if (ASIC_IS_R300(rdev)) {
2444 sclk_delay_ff.full = rfixed_const(250);
2445 } else {
2446 if ((rdev->family == CHIP_RV100) ||
2447 rdev->flags & RADEON_IS_IGP) {
2448 if (rdev->mc.vram_is_ddr)
2449 sclk_delay_ff.full = rfixed_const(41);
2450 else
2451 sclk_delay_ff.full = rfixed_const(33);
2452 } else {
2453 if (rdev->mc.vram_width == 128)
2454 sclk_delay_ff.full = rfixed_const(57);
2455 else
2456 sclk_delay_ff.full = rfixed_const(41);
2457 }
2458 }
2459
2460 mc_latency_sclk.full = rfixed_div(sclk_delay_ff, sclk_eff_ff);
2461
2462 if (rdev->mc.vram_is_ddr) {
2463 if (rdev->mc.vram_width == 32) {
2464 k1.full = rfixed_const(40);
2465 c = 3;
2466 } else {
2467 k1.full = rfixed_const(20);
2468 c = 1;
2469 }
2470 } else {
2471 k1.full = rfixed_const(40);
2472 c = 3;
2473 }
2474
2475 temp_ff.full = rfixed_const(2);
2476 mc_latency_mclk.full = rfixed_mul(trcd_ff, temp_ff);
2477 temp_ff.full = rfixed_const(c);
2478 mc_latency_mclk.full += rfixed_mul(tcas_ff, temp_ff);
2479 temp_ff.full = rfixed_const(4);
2480 mc_latency_mclk.full += rfixed_mul(tras_ff, temp_ff);
2481 mc_latency_mclk.full += rfixed_mul(trp_ff, temp_ff);
2482 mc_latency_mclk.full += k1.full;
2483
2484 mc_latency_mclk.full = rfixed_div(mc_latency_mclk, mclk_ff);
2485 mc_latency_mclk.full += rfixed_div(temp_ff, sclk_eff_ff);
2486
2487 /*
2488 HW cursor time assuming worst case of full size colour cursor.
2489 */
2490 temp_ff.full = rfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
2491 temp_ff.full += trcd_ff.full;
2492 if (temp_ff.full < tras_ff.full)
2493 temp_ff.full = tras_ff.full;
2494 cur_latency_mclk.full = rfixed_div(temp_ff, mclk_ff);
2495
2496 temp_ff.full = rfixed_const(cur_size);
2497 cur_latency_sclk.full = rfixed_div(temp_ff, sclk_eff_ff);
2498 /*
2499 Find the total latency for the display data.
2500 */
2501 disp_latency_overhead.full = rfixed_const(80);
2502 disp_latency_overhead.full = rfixed_div(disp_latency_overhead, sclk_ff);
2503 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
2504 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
2505
2506 if (mc_latency_mclk.full > mc_latency_sclk.full)
2507 disp_latency.full = mc_latency_mclk.full;
2508 else
2509 disp_latency.full = mc_latency_sclk.full;
2510
2511 /* setup Max GRPH_STOP_REQ default value */
2512 if (ASIC_IS_RV100(rdev))
2513 max_stop_req = 0x5c;
2514 else
2515 max_stop_req = 0x7c;
2516
2517 if (mode1) {
2518 /* CRTC1
2519 Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
2520 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
2521 */
2522 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
2523
2524 if (stop_req > max_stop_req)
2525 stop_req = max_stop_req;
2526
2527 /*
2528 Find the drain rate of the display buffer.
2529 */
2530 temp_ff.full = rfixed_const((16/pixel_bytes1));
2531 disp_drain_rate.full = rfixed_div(pix_clk, temp_ff);
2532
2533 /*
2534 Find the critical point of the display buffer.
2535 */
2536 crit_point_ff.full = rfixed_mul(disp_drain_rate, disp_latency);
2537 crit_point_ff.full += rfixed_const_half(0);
2538
2539 critical_point = rfixed_trunc(crit_point_ff);
2540
2541 if (rdev->disp_priority == 2) {
2542 critical_point = 0;
2543 }
2544
2545 /*
2546 The critical point should never be above max_stop_req-4. Setting
2547 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
2548 */
2549 if (max_stop_req - critical_point < 4)
2550 critical_point = 0;
2551
2552 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
2553 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
2554 critical_point = 0x10;
2555 }
2556
2557 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
2558 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
2559 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
2560 temp &= ~(RADEON_GRPH_START_REQ_MASK);
2561 if ((rdev->family == CHIP_R350) &&
2562 (stop_req > 0x15)) {
2563 stop_req -= 0x10;
2564 }
2565 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
2566 temp |= RADEON_GRPH_BUFFER_SIZE;
2567 temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
2568 RADEON_GRPH_CRITICAL_AT_SOF |
2569 RADEON_GRPH_STOP_CNTL);
2570 /*
2571 Write the result into the register.
2572 */
2573 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
2574 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
2575
2576#if 0
2577 if ((rdev->family == CHIP_RS400) ||
2578 (rdev->family == CHIP_RS480)) {
2579 /* attempt to program RS400 disp regs correctly ??? */
2580 temp = RREG32(RS400_DISP1_REG_CNTL);
2581 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
2582 RS400_DISP1_STOP_REQ_LEVEL_MASK);
2583 WREG32(RS400_DISP1_REQ_CNTL1, (temp |
2584 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
2585 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
2586 temp = RREG32(RS400_DMIF_MEM_CNTL1);
2587 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
2588 RS400_DISP1_CRITICAL_POINT_STOP_MASK);
2589 WREG32(RS400_DMIF_MEM_CNTL1, (temp |
2590 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
2591 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
2592 }
2593#endif
2594
2595 DRM_DEBUG("GRPH_BUFFER_CNTL from to %x\n",
2596 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */
2597 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
2598 }
2599
2600 if (mode2) {
2601 u32 grph2_cntl;
2602 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
2603
2604 if (stop_req > max_stop_req)
2605 stop_req = max_stop_req;
2606
2607 /*
2608 Find the drain rate of the display buffer.
2609 */
2610 temp_ff.full = rfixed_const((16/pixel_bytes2));
2611 disp_drain_rate2.full = rfixed_div(pix_clk2, temp_ff);
2612
2613 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
2614 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
2615 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
2616 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
2617 if ((rdev->family == CHIP_R350) &&
2618 (stop_req > 0x15)) {
2619 stop_req -= 0x10;
2620 }
2621 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
2622 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
2623 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL |
2624 RADEON_GRPH_CRITICAL_AT_SOF |
2625 RADEON_GRPH_STOP_CNTL);
2626
2627 if ((rdev->family == CHIP_RS100) ||
2628 (rdev->family == CHIP_RS200))
2629 critical_point2 = 0;
2630 else {
2631 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
2632 temp_ff.full = rfixed_const(temp);
2633 temp_ff.full = rfixed_mul(mclk_ff, temp_ff);
2634 if (sclk_ff.full < temp_ff.full)
2635 temp_ff.full = sclk_ff.full;
2636
2637 read_return_rate.full = temp_ff.full;
2638
2639 if (mode1) {
2640 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
2641 time_disp1_drop_priority.full = rfixed_div(crit_point_ff, temp_ff);
2642 } else {
2643 time_disp1_drop_priority.full = 0;
2644 }
2645 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
2646 crit_point_ff.full = rfixed_mul(crit_point_ff, disp_drain_rate2);
2647 crit_point_ff.full += rfixed_const_half(0);
2648
2649 critical_point2 = rfixed_trunc(crit_point_ff);
2650
2651 if (rdev->disp_priority == 2) {
2652 critical_point2 = 0;
2653 }
2654
2655 if (max_stop_req - critical_point2 < 4)
2656 critical_point2 = 0;
2657
2658 }
2659
2660 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
2661 /* some R300 cards have problem with this set to 0 */
2662 critical_point2 = 0x10;
2663 }
2664
2665 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
2666 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
2667
2668 if ((rdev->family == CHIP_RS400) ||
2669 (rdev->family == CHIP_RS480)) {
2670#if 0
2671 /* attempt to program RS400 disp2 regs correctly ??? */
2672 temp = RREG32(RS400_DISP2_REQ_CNTL1);
2673 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
2674 RS400_DISP2_STOP_REQ_LEVEL_MASK);
2675 WREG32(RS400_DISP2_REQ_CNTL1, (temp |
2676 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
2677 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
2678 temp = RREG32(RS400_DISP2_REQ_CNTL2);
2679 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
2680 RS400_DISP2_CRITICAL_POINT_STOP_MASK);
2681 WREG32(RS400_DISP2_REQ_CNTL2, (temp |
2682 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
2683 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
2684#endif
2685 WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
2686 WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
2687 WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
2688 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
2689 }
2690
2691 DRM_DEBUG("GRPH2_BUFFER_CNTL from to %x\n",
2692 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
2693 }
2694}
551ebd83
DA		 2695
2696static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
2697{
2698 DRM_ERROR("pitch %d\n", t->pitch);
2699 DRM_ERROR("width %d\n", t->width);
2700 DRM_ERROR("height %d\n", t->height);
2701 DRM_ERROR("num levels %d\n", t->num_levels);
2702 DRM_ERROR("depth %d\n", t->txdepth);
2703 DRM_ERROR("bpp %d\n", t->cpp);
2704 DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
2705 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
2706 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
2707}
2708
2709static int r100_cs_track_cube(struct radeon_device *rdev,
2710 struct r100_cs_track *track, unsigned idx)
2711{
2712 unsigned face, w, h;
2713 struct radeon_object *cube_robj;
2714 unsigned long size;
2715
2716 for (face = 0; face < 5; face++) {
2717 cube_robj = track->textures[idx].cube_info[face].robj;
2718 w = track->textures[idx].cube_info[face].width;
2719 h = track->textures[idx].cube_info[face].height;
2720
2721 size = w * h;
2722 size *= track->textures[idx].cpp;
2723
2724 size += track->textures[idx].cube_info[face].offset;
2725
2726 if (size > radeon_object_size(cube_robj)) {
2727 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
2728 size, radeon_object_size(cube_robj));
2729 r100_cs_track_texture_print(&track->textures[idx]);
2730 return -1;
2731 }
2732 }
2733 return 0;
2734}
2735
2736static int r100_cs_track_texture_check(struct radeon_device *rdev,
2737 struct r100_cs_track *track)
2738{
2739 struct radeon_object *robj;
2740 unsigned long size;
2741 unsigned u, i, w, h;
2742 int ret;
2743
2744 for (u = 0; u < track->num_texture; u++) {
2745 if (!track->textures[u].enabled)
2746 continue;
2747 robj = track->textures[u].robj;
2748 if (robj == NULL) {
2749 DRM_ERROR("No texture bound to unit %u\n", u);
2750 return -EINVAL;
2751 }
2752 size = 0;
2753 for (i = 0; i <= track->textures[u].num_levels; i++) {
2754 if (track->textures[u].use_pitch) {
2755 if (rdev->family < CHIP_R300)
2756 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
2757 else
2758 w = track->textures[u].pitch / (1 << i);
2759 } else {
2760 w = track->textures[u].width / (1 << i);
2761 if (rdev->family >= CHIP_RV515)
2762 w |= track->textures[u].width_11;
2763 if (track->textures[u].roundup_w)
2764 w = roundup_pow_of_two(w);
2765 }
2766 h = track->textures[u].height / (1 << i);
2767 if (rdev->family >= CHIP_RV515)
2768 h |= track->textures[u].height_11;
2769 if (track->textures[u].roundup_h)
2770 h = roundup_pow_of_two(h);
2771 size += w * h;
2772 }
2773 size *= track->textures[u].cpp;
2774 switch (track->textures[u].tex_coord_type) {
2775 case 0:
2776 break;
2777 case 1:
2778 size *= (1 << track->textures[u].txdepth);
2779 break;
2780 case 2:
2781 if (track->separate_cube) {
2782 ret = r100_cs_track_cube(rdev, track, u);
2783 if (ret)
2784 return ret;
2785 } else
2786 size *= 6;
2787 break;
2788 default:
2789 DRM_ERROR("Invalid texture coordinate type %u for unit "
2790 "%u\n", track->textures[u].tex_coord_type, u);
2791 return -EINVAL;
2792 }
2793 if (size > radeon_object_size(robj)) {
2794 DRM_ERROR("Texture of unit %u needs %lu bytes but is "
2795 "%lu\n", u, size, radeon_object_size(robj));
2796 r100_cs_track_texture_print(&track->textures[u]);
2797 return -EINVAL;
2798 }
2799 }
2800 return 0;
2801}
2802
2803int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
2804{
2805 unsigned i;
2806 unsigned long size;
2807 unsigned prim_walk;
2808 unsigned nverts;
2809
2810 for (i = 0; i < track->num_cb; i++) {
2811 if (track->cb[i].robj == NULL) {
2812 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
2813 return -EINVAL;
2814 }
2815 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
2816 size += track->cb[i].offset;
2817 if (size > radeon_object_size(track->cb[i].robj)) {
2818 DRM_ERROR("[drm] Buffer too small for color buffer %d "
2819 "(need %lu have %lu) !\n", i, size,
2820 radeon_object_size(track->cb[i].robj));
2821 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
2822 i, track->cb[i].pitch, track->cb[i].cpp,
2823 track->cb[i].offset, track->maxy);
2824 return -EINVAL;
2825 }
2826 }
2827 if (track->z_enabled) {
2828 if (track->zb.robj == NULL) {
2829 DRM_ERROR("[drm] No buffer for z buffer !\n");
2830 return -EINVAL;
2831 }
2832 size = track->zb.pitch * track->zb.cpp * track->maxy;
2833 size += track->zb.offset;
2834 if (size > radeon_object_size(track->zb.robj)) {
2835 DRM_ERROR("[drm] Buffer too small for z buffer "
2836 "(need %lu have %lu) !\n", size,
2837 radeon_object_size(track->zb.robj));
2838 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
2839 track->zb.pitch, track->zb.cpp,
2840 track->zb.offset, track->maxy);
2841 return -EINVAL;
2842 }
2843 }
2844 prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
2845 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
2846 switch (prim_walk) {
2847 case 1:
2848 for (i = 0; i < track->num_arrays; i++) {
2849 size = track->arrays[i].esize * track->max_indx * 4;
2850 if (track->arrays[i].robj == NULL) {
2851 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2852 "bound\n", prim_walk, i);
2853 return -EINVAL;
2854 }
2855 if (size > radeon_object_size(track->arrays[i].robj)) {
2856 DRM_ERROR("(PW %u) Vertex array %u need %lu dwords "
2857 "have %lu dwords\n", prim_walk, i,
2858 size >> 2,
2859 radeon_object_size(track->arrays[i].robj) >> 2);
2860 DRM_ERROR("Max indices %u\n", track->max_indx);
2861 return -EINVAL;
2862 }
2863 }
2864 break;
2865 case 2:
2866 for (i = 0; i < track->num_arrays; i++) {
2867 size = track->arrays[i].esize * (nverts - 1) * 4;
2868 if (track->arrays[i].robj == NULL) {
2869 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2870 "bound\n", prim_walk, i);
2871 return -EINVAL;
2872 }
2873 if (size > radeon_object_size(track->arrays[i].robj)) {
2874 DRM_ERROR("(PW %u) Vertex array %u need %lu dwords "
2875 "have %lu dwords\n", prim_walk, i, size >> 2,
2876 radeon_object_size(track->arrays[i].robj) >> 2);
2877 return -EINVAL;
2878 }
2879 }
2880 break;
2881 case 3:
2882 size = track->vtx_size * nverts;
2883 if (size != track->immd_dwords) {
2884 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
2885 track->immd_dwords, size);
2886 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
2887 nverts, track->vtx_size);
2888 return -EINVAL;
2889 }
2890 break;
2891 default:
2892 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
2893 prim_walk);
2894 return -EINVAL;
2895 }
2896 return r100_cs_track_texture_check(rdev, track);
2897}
2898
2899void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
2900{
2901 unsigned i, face;
2902
2903 if (rdev->family < CHIP_R300) {
2904 track->num_cb = 1;
2905 if (rdev->family <= CHIP_RS200)
2906 track->num_texture = 3;
2907 else
2908 track->num_texture = 6;
2909 track->maxy = 2048;
2910 track->separate_cube = 1;
2911 } else {
2912 track->num_cb = 4;
2913 track->num_texture = 16;
2914 track->maxy = 4096;
2915 track->separate_cube = 0;
2916 }
2917
2918 for (i = 0; i < track->num_cb; i++) {
2919 track->cb[i].robj = NULL;
2920 track->cb[i].pitch = 8192;
2921 track->cb[i].cpp = 16;
2922 track->cb[i].offset = 0;
2923 }
2924 track->z_enabled = true;
2925 track->zb.robj = NULL;
2926 track->zb.pitch = 8192;
2927 track->zb.cpp = 4;
2928 track->zb.offset = 0;
2929 track->vtx_size = 0x7F;
2930 track->immd_dwords = 0xFFFFFFFFUL;
2931 track->num_arrays = 11;
2932 track->max_indx = 0x00FFFFFFUL;
2933 for (i = 0; i < track->num_arrays; i++) {
2934 track->arrays[i].robj = NULL;
2935 track->arrays[i].esize = 0x7F;
2936 }
2937 for (i = 0; i < track->num_texture; i++) {
2938 track->textures[i].pitch = 16536;
2939 track->textures[i].width = 16536;
2940 track->textures[i].height = 16536;
2941 track->textures[i].width_11 = 1 << 11;
2942 track->textures[i].height_11 = 1 << 11;
2943 track->textures[i].num_levels = 12;
2944 if (rdev->family <= CHIP_RS200) {
2945 track->textures[i].tex_coord_type = 0;
2946 track->textures[i].txdepth = 0;
2947 } else {
2948 track->textures[i].txdepth = 16;
2949 track->textures[i].tex_coord_type = 1;
2950 }
2951 track->textures[i].cpp = 64;
2952 track->textures[i].robj = NULL;
2953 /* CS IB emission code makes sure texture unit are disabled */
2954 track->textures[i].enabled = false;
2955 track->textures[i].roundup_w = true;
2956 track->textures[i].roundup_h = true;
2957 if (track->separate_cube)
2958 for (face = 0; face < 5; face++) {
2959 track->textures[i].cube_info[face].robj = NULL;
2960 track->textures[i].cube_info[face].width = 16536;
2961 track->textures[i].cube_info[face].height = 16536;
2962 track->textures[i].cube_info[face].offset = 0;
2963 }
2964 }
2965}
3ce0a23d
JG		 2966
2967int r100_ring_test(struct radeon_device *rdev)
2968{
2969 uint32_t scratch;
2970 uint32_t tmp = 0;
2971 unsigned i;
2972 int r;
2973
2974 r = radeon_scratch_get(rdev, &scratch);
2975 if (r) {
2976 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
2977 return r;
2978 }
2979 WREG32(scratch, 0xCAFEDEAD);
2980 r = radeon_ring_lock(rdev, 2);
2981 if (r) {
2982 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2983 radeon_scratch_free(rdev, scratch);
2984 return r;
2985 }
2986 radeon_ring_write(rdev, PACKET0(scratch, 0));
2987 radeon_ring_write(rdev, 0xDEADBEEF);
2988 radeon_ring_unlock_commit(rdev);
2989 for (i = 0; i < rdev->usec_timeout; i++) {
2990 tmp = RREG32(scratch);
2991 if (tmp == 0xDEADBEEF) {
2992 break;
2993 }
2994 DRM_UDELAY(1);
2995 }
2996 if (i < rdev->usec_timeout) {
2997 DRM_INFO("ring test succeeded in %d usecs\n", i);
2998 } else {
2999 DRM_ERROR("radeon: ring test failed (sracth(0x%04X)=0x%08X)\n",
3000 scratch, tmp);
3001 r = -EINVAL;
3002 }
3003 radeon_scratch_free(rdev, scratch);
3004 return r;
3005}
3006
3007void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3008{
3009 radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1));
3010 radeon_ring_write(rdev, ib->gpu_addr);
3011 radeon_ring_write(rdev, ib->length_dw);
3012}
3013
3014int r100_ib_test(struct radeon_device *rdev)
3015{
3016 struct radeon_ib *ib;
3017 uint32_t scratch;
3018 uint32_t tmp = 0;
3019 unsigned i;
3020 int r;
3021
3022 r = radeon_scratch_get(rdev, &scratch);
3023 if (r) {
3024 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3025 return r;
3026 }
3027 WREG32(scratch, 0xCAFEDEAD);
3028 r = radeon_ib_get(rdev, &ib);
3029 if (r) {
3030 return r;
3031 }
3032 ib->ptr[0] = PACKET0(scratch, 0);
3033 ib->ptr[1] = 0xDEADBEEF;
3034 ib->ptr[2] = PACKET2(0);
3035 ib->ptr[3] = PACKET2(0);
3036 ib->ptr[4] = PACKET2(0);
3037 ib->ptr[5] = PACKET2(0);
3038 ib->ptr[6] = PACKET2(0);
3039 ib->ptr[7] = PACKET2(0);
3040 ib->length_dw = 8;
3041 r = radeon_ib_schedule(rdev, ib);
3042 if (r) {
3043 radeon_scratch_free(rdev, scratch);
3044 radeon_ib_free(rdev, &ib);
3045 return r;
3046 }
3047 r = radeon_fence_wait(ib->fence, false);
3048 if (r) {
3049 return r;
3050 }
3051 for (i = 0; i < rdev->usec_timeout; i++) {
3052 tmp = RREG32(scratch);
3053 if (tmp == 0xDEADBEEF) {
3054 break;
3055 }
3056 DRM_UDELAY(1);
3057 }
3058 if (i < rdev->usec_timeout) {
3059 DRM_INFO("ib test succeeded in %u usecs\n", i);
3060 } else {
3061 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
3062 scratch, tmp);
3063 r = -EINVAL;
3064 }
3065 radeon_scratch_free(rdev, scratch);
3066 radeon_ib_free(rdev, &ib);
3067 return r;
3068}
9f022ddf
JG		 3069
3070void r100_ib_fini(struct radeon_device *rdev)
3071{
3072 radeon_ib_pool_fini(rdev);
3073}
3074
3075int r100_ib_init(struct radeon_device *rdev)
3076{
3077 int r;
3078
3079 r = radeon_ib_pool_init(rdev);
3080 if (r) {
3081 dev_err(rdev->dev, "failled initializing IB pool (%d).\n", r);
3082 r100_ib_fini(rdev);
3083 return r;
3084 }
3085 r = r100_ib_test(rdev);
3086 if (r) {
3087 dev_err(rdev->dev, "failled testing IB (%d).\n", r);
3088 r100_ib_fini(rdev);
3089 return r;
3090 }
3091 return 0;
3092}
3093
3094void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3095{
3096 /* Shutdown CP we shouldn't need to do that but better be safe than
3097 * sorry
3098 */
3099 rdev->cp.ready = false;
3100 WREG32(R_000740_CP_CSQ_CNTL, 0);
3101
3102 /* Save few CRTC registers */
ca6ffc64 3103 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
9f022ddf
JG		 3104 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3105 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3106 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3107 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3108 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3109 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3110 }
3111
3112 /* Disable VGA aperture access */
ca6ffc64 3113 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
9f022ddf
JG		 3114 /* Disable cursor, overlay, crtc */
3115 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3116 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3117 S_000054_CRTC_DISPLAY_DIS(1));
3118 WREG32(R_000050_CRTC_GEN_CNTL,
3119 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3120 S_000050_CRTC_DISP_REQ_EN_B(1));
3121 WREG32(R_000420_OV0_SCALE_CNTL,
3122 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3123 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3124 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3125 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3126 S_000360_CUR2_LOCK(1));
3127 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3128 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3129 S_0003F8_CRTC2_DISPLAY_DIS(1) |
3130 S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3131 WREG32(R_000360_CUR2_OFFSET,
3132 C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3133 }
3134}
3135
3136void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3137{
3138 /* Update base address for crtc */
3139 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_location);
3140 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3141 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR,
3142 rdev->mc.vram_location);
3143 }
3144 /* Restore CRTC registers */
ca6ffc64 3145 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
9f022ddf
JG		 3146 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3147 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3148 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3149 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3150 }
3151}
ca6ffc64
JG		 3152
3153void r100_vga_render_disable(struct radeon_device *rdev)
3154{
3155 u32 tmp;
3156
3157 tmp = RREG8(R_0003C2_GENMO_WT);
3158 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3159}
kernel source for telekom puls (alcatel/mediatek)