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drm: do not leak kernel addresses via /proc/dri/*/vma
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / radeon / r100.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <linux/seq_file.h>
5a0e3ad6 29#include <linux/slab.h>
771fe6b9
JG		 30#include "drmP.h"
31#include "drm.h"
32#include "radeon_drm.h"
771fe6b9
JG		 33#include "radeon_reg.h"
34#include "radeon.h"
e6990375 35#include "radeon_asic.h"
3ce0a23d 36#include "r100d.h"
d4550907
JG		 37#include "rs100d.h"
38#include "rv200d.h"
39#include "rv250d.h"
49e02b73 40#include "atom.h"
3ce0a23d 41
70967ab9
BH		 42#include <linux/firmware.h>
43#include <linux/platform_device.h>
44
551ebd83
DA		 45#include "r100_reg_safe.h"
46#include "rn50_reg_safe.h"
47
70967ab9
BH		 48/* Firmware Names */
49#define FIRMWARE_R100 "radeon/R100_cp.bin"
50#define FIRMWARE_R200 "radeon/R200_cp.bin"
51#define FIRMWARE_R300 "radeon/R300_cp.bin"
52#define FIRMWARE_R420 "radeon/R420_cp.bin"
53#define FIRMWARE_RS690 "radeon/RS690_cp.bin"
54#define FIRMWARE_RS600 "radeon/RS600_cp.bin"
55#define FIRMWARE_R520 "radeon/R520_cp.bin"
56
57MODULE_FIRMWARE(FIRMWARE_R100);
58MODULE_FIRMWARE(FIRMWARE_R200);
59MODULE_FIRMWARE(FIRMWARE_R300);
60MODULE_FIRMWARE(FIRMWARE_R420);
61MODULE_FIRMWARE(FIRMWARE_RS690);
62MODULE_FIRMWARE(FIRMWARE_RS600);
63MODULE_FIRMWARE(FIRMWARE_R520);
771fe6b9 64
551ebd83
DA		 65#include "r100_track.h"
66
771fe6b9
JG		 67/* This files gather functions specifics to:
68 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
771fe6b9 69 */
771fe6b9 70
6f34be50
AD		 71void r100_pre_page_flip(struct radeon_device *rdev, int crtc)
72{
73 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc];
74 u32 tmp;
75
76 /* make sure flip is at vb rather than hb */
77 tmp = RREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset);
78 tmp &= ~RADEON_CRTC_OFFSET_FLIP_CNTL;
acb32506
AD		 79 /* make sure pending bit is asserted */
80 tmp |= RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN;
6f34be50
AD		 81 WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, tmp);
82
83 /* set pageflip to happen as late as possible in the vblank interval.
84 * same field for crtc1/2
85 */
86 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
87 tmp &= ~RADEON_CRTC_VSTAT_MODE_MASK;
88 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
89
90 /* enable the pflip int */
91 radeon_irq_kms_pflip_irq_get(rdev, crtc);
92}
93
94void r100_post_page_flip(struct radeon_device *rdev, int crtc)
95{
96 /* disable the pflip int */
97 radeon_irq_kms_pflip_irq_put(rdev, crtc);
98}
99
100u32 r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
101{
102 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
103 u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK;
104
105 /* Lock the graphics update lock */
106 /* update the scanout addresses */
107 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
108
acb32506
AD		 109 /* Wait for update_pending to go high. */
110 while (!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET));
111 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
6f34be50
AD		 112
113 /* Unlock the lock, so double-buffering can take place inside vblank */
114 tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK;
115 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
116
117 /* Return current update_pending status: */
118 return RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET;
119}
120
ce8f5370 121void r100_pm_get_dynpm_state(struct radeon_device *rdev)
a48b9b4e
AD		 122{
123 int i;
ce8f5370
AD		 124 rdev->pm.dynpm_can_upclock = true;
125 rdev->pm.dynpm_can_downclock = true;
a48b9b4e 126
ce8f5370
AD		 127 switch (rdev->pm.dynpm_planned_action) {
128 case DYNPM_ACTION_MINIMUM:
a48b9b4e 129 rdev->pm.requested_power_state_index = 0;
ce8f5370 130 rdev->pm.dynpm_can_downclock = false;
a48b9b4e 131 break;
ce8f5370 132 case DYNPM_ACTION_DOWNCLOCK:
a48b9b4e
AD		 133 if (rdev->pm.current_power_state_index == 0) {
134 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
ce8f5370 135 rdev->pm.dynpm_can_downclock = false;
a48b9b4e
AD		 136 } else {
137 if (rdev->pm.active_crtc_count > 1) {
138 for (i = 0; i < rdev->pm.num_power_states; i++) {
d7311171 139 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 140 continue;
141 else if (i >= rdev->pm.current_power_state_index) {
142 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
143 break;
144 } else {
145 rdev->pm.requested_power_state_index = i;
146 break;
147 }
148 }
149 } else
150 rdev->pm.requested_power_state_index =
151 rdev->pm.current_power_state_index - 1;
152 }
d7311171
AD		 153 /* don't use the power state if crtcs are active and no display flag is set */
154 if ((rdev->pm.active_crtc_count > 0) &&
155 (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags &
156 RADEON_PM_MODE_NO_DISPLAY)) {
157 rdev->pm.requested_power_state_index++;
158 }
a48b9b4e 159 break;
ce8f5370 160 case DYNPM_ACTION_UPCLOCK:
a48b9b4e
AD		 161 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
162 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
ce8f5370 163 rdev->pm.dynpm_can_upclock = false;
a48b9b4e
AD		 164 } else {
165 if (rdev->pm.active_crtc_count > 1) {
166 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
d7311171 167 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
a48b9b4e
AD		 168 continue;
169 else if (i <= rdev->pm.current_power_state_index) {
170 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
171 break;
172 } else {
173 rdev->pm.requested_power_state_index = i;
174 break;
175 }
176 }
177 } else
178 rdev->pm.requested_power_state_index =
179 rdev->pm.current_power_state_index + 1;
180 }
181 break;
ce8f5370 182 case DYNPM_ACTION_DEFAULT:
58e21dff 183 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
ce8f5370 184 rdev->pm.dynpm_can_upclock = false;
58e21dff 185 break;
ce8f5370 186 case DYNPM_ACTION_NONE:
a48b9b4e
AD		 187 default:
188 DRM_ERROR("Requested mode for not defined action\n");
189 return;
190 }
191 /* only one clock mode per power state */
192 rdev->pm.requested_clock_mode_index = 0;
193
d9fdaafb 194 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
ce8a3eb2
AD		 195 rdev->pm.power_state[rdev->pm.requested_power_state_index].
196 clock_info[rdev->pm.requested_clock_mode_index].sclk,
197 rdev->pm.power_state[rdev->pm.requested_power_state_index].
198 clock_info[rdev->pm.requested_clock_mode_index].mclk,
199 rdev->pm.power_state[rdev->pm.requested_power_state_index].
200 pcie_lanes);
a48b9b4e
AD		 201}
202
ce8f5370
AD		 203void r100_pm_init_profile(struct radeon_device *rdev)
204{
205 /* default */
206 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
207 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
208 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
209 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
210 /* low sh */
211 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
212 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
213 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
214 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 215 /* mid sh */
216 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
217 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
218 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
219 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 220 /* high sh */
221 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
222 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
223 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
224 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
225 /* low mh */
226 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
227 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
228 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
229 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
c9e75b21
AD		 230 /* mid mh */
231 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
232 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
233 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
234 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
ce8f5370
AD		 235 /* high mh */
236 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
237 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
238 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
239 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
bae6b562
AD		 240}
241
49e02b73
AD		 242void r100_pm_misc(struct radeon_device *rdev)
243{
49e02b73
AD		 244 int requested_index = rdev->pm.requested_power_state_index;
245 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
246 struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
247 u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl;
248
249 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
250 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
251 tmp = RREG32(voltage->gpio.reg);
252 if (voltage->active_high)
253 tmp |= voltage->gpio.mask;
254 else
255 tmp &= ~(voltage->gpio.mask);
256 WREG32(voltage->gpio.reg, tmp);
257 if (voltage->delay)
258 udelay(voltage->delay);
259 } else {
260 tmp = RREG32(voltage->gpio.reg);
261 if (voltage->active_high)
262 tmp &= ~voltage->gpio.mask;
263 else
264 tmp |= voltage->gpio.mask;
265 WREG32(voltage->gpio.reg, tmp);
266 if (voltage->delay)
267 udelay(voltage->delay);
268 }
269 }
270
271 sclk_cntl = RREG32_PLL(SCLK_CNTL);
272 sclk_cntl2 = RREG32_PLL(SCLK_CNTL2);
273 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3);
274 sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL);
275 sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3);
276 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
277 sclk_more_cntl |= REDUCED_SPEED_SCLK_EN;
278 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE)
279 sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE;
280 else
281 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE;
282 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2)
283 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0);
284 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4)
285 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2);
286 } else
287 sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN;
288
289 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
290 sclk_more_cntl |= IO_CG_VOLTAGE_DROP;
291 if (voltage->delay) {
292 sclk_more_cntl |= VOLTAGE_DROP_SYNC;
293 switch (voltage->delay) {
294 case 33:
295 sclk_more_cntl |= VOLTAGE_DELAY_SEL(0);
296 break;
297 case 66:
298 sclk_more_cntl |= VOLTAGE_DELAY_SEL(1);
299 break;
300 case 99:
301 sclk_more_cntl |= VOLTAGE_DELAY_SEL(2);
302 break;
303 case 132:
304 sclk_more_cntl |= VOLTAGE_DELAY_SEL(3);
305 break;
306 }
307 } else
308 sclk_more_cntl &= ~VOLTAGE_DROP_SYNC;
309 } else
310 sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP;
311
312 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
313 sclk_cntl &= ~FORCE_HDP;
314 else
315 sclk_cntl |= FORCE_HDP;
316
317 WREG32_PLL(SCLK_CNTL, sclk_cntl);
318 WREG32_PLL(SCLK_CNTL2, sclk_cntl2);
319 WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl);
320
321 /* set pcie lanes */
322 if ((rdev->flags & RADEON_IS_PCIE) &&
323 !(rdev->flags & RADEON_IS_IGP) &&
324 rdev->asic->set_pcie_lanes &&
325 (ps->pcie_lanes !=
326 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
327 radeon_set_pcie_lanes(rdev,
328 ps->pcie_lanes);
d9fdaafb 329 DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes);
49e02b73 330 }
49e02b73
AD		 331}
332
333void r100_pm_prepare(struct radeon_device *rdev)
334{
335 struct drm_device *ddev = rdev->ddev;
336 struct drm_crtc *crtc;
337 struct radeon_crtc *radeon_crtc;
338 u32 tmp;
339
340 /* disable any active CRTCs */
341 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
342 radeon_crtc = to_radeon_crtc(crtc);
343 if (radeon_crtc->enabled) {
344 if (radeon_crtc->crtc_id) {
345 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
346 tmp |= RADEON_CRTC2_DISP_REQ_EN_B;
347 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
348 } else {
349 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
350 tmp |= RADEON_CRTC_DISP_REQ_EN_B;
351 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
352 }
353 }
354 }
355}
356
357void r100_pm_finish(struct radeon_device *rdev)
358{
359 struct drm_device *ddev = rdev->ddev;
360 struct drm_crtc *crtc;
361 struct radeon_crtc *radeon_crtc;
362 u32 tmp;
363
364 /* enable any active CRTCs */
365 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
366 radeon_crtc = to_radeon_crtc(crtc);
367 if (radeon_crtc->enabled) {
368 if (radeon_crtc->crtc_id) {
369 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
370 tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B;
371 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
372 } else {
373 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
374 tmp &= ~RADEON_CRTC_DISP_REQ_EN_B;
375 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
376 }
377 }
378 }
379}
380
def9ba9c
AD		 381bool r100_gui_idle(struct radeon_device *rdev)
382{
383 if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)
384 return false;
385 else
386 return true;
387}
388
05a05c50
AD		 389/* hpd for digital panel detect/disconnect */
390bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
391{
392 bool connected = false;
393
394 switch (hpd) {
395 case RADEON_HPD_1:
396 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
397 connected = true;
398 break;
399 case RADEON_HPD_2:
400 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
401 connected = true;
402 break;
403 default:
404 break;
405 }
406 return connected;
407}
408
409void r100_hpd_set_polarity(struct radeon_device *rdev,
410 enum radeon_hpd_id hpd)
411{
412 u32 tmp;
413 bool connected = r100_hpd_sense(rdev, hpd);
414
415 switch (hpd) {
416 case RADEON_HPD_1:
417 tmp = RREG32(RADEON_FP_GEN_CNTL);
418 if (connected)
419 tmp &= ~RADEON_FP_DETECT_INT_POL;
420 else
421 tmp |= RADEON_FP_DETECT_INT_POL;
422 WREG32(RADEON_FP_GEN_CNTL, tmp);
423 break;
424 case RADEON_HPD_2:
425 tmp = RREG32(RADEON_FP2_GEN_CNTL);
426 if (connected)
427 tmp &= ~RADEON_FP2_DETECT_INT_POL;
428 else
429 tmp |= RADEON_FP2_DETECT_INT_POL;
430 WREG32(RADEON_FP2_GEN_CNTL, tmp);
431 break;
432 default:
433 break;
434 }
435}
436
437void r100_hpd_init(struct radeon_device *rdev)
438{
439 struct drm_device *dev = rdev->ddev;
440 struct drm_connector *connector;
441
442 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
443 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
444 switch (radeon_connector->hpd.hpd) {
445 case RADEON_HPD_1:
446 rdev->irq.hpd[0] = true;
447 break;
448 case RADEON_HPD_2:
449 rdev->irq.hpd[1] = true;
450 break;
451 default:
452 break;
453 }
454 }
003e69f9
JG		 455 if (rdev->irq.installed)
456 r100_irq_set(rdev);
05a05c50
AD		 457}
458
459void r100_hpd_fini(struct radeon_device *rdev)
460{
461 struct drm_device *dev = rdev->ddev;
462 struct drm_connector *connector;
463
464 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
465 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
466 switch (radeon_connector->hpd.hpd) {
467 case RADEON_HPD_1:
468 rdev->irq.hpd[0] = false;
469 break;
470 case RADEON_HPD_2:
471 rdev->irq.hpd[1] = false;
472 break;
473 default:
474 break;
475 }
476 }
477}
478
771fe6b9
JG		 479/*
480 * PCI GART
481 */
482void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
483{
484 /* TODO: can we do somethings here ? */
485 /* It seems hw only cache one entry so we should discard this
486 * entry otherwise if first GPU GART read hit this entry it
487 * could end up in wrong address. */
488}
489
4aac0473 490int r100_pci_gart_init(struct radeon_device *rdev)
771fe6b9 491{
771fe6b9
JG		 492 int r;
493
4aac0473 494 if (rdev->gart.table.ram.ptr) {
fce7d61b 495 WARN(1, "R100 PCI GART already initialized\n");
4aac0473
JG		 496 return 0;
497 }
771fe6b9
JG		 498 /* Initialize common gart structure */
499 r = radeon_gart_init(rdev);
4aac0473 500 if (r)
771fe6b9 501 return r;
4aac0473
JG		 502 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
503 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
504 rdev->asic->gart_set_page = &r100_pci_gart_set_page;
505 return radeon_gart_table_ram_alloc(rdev);
506}
507
17e15b0c
DA		 508/* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
509void r100_enable_bm(struct radeon_device *rdev)
510{
511 uint32_t tmp;
512 /* Enable bus mastering */
513 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
514 WREG32(RADEON_BUS_CNTL, tmp);
515}
516
4aac0473
JG		 517int r100_pci_gart_enable(struct radeon_device *rdev)
518{
519 uint32_t tmp;
520
82568565 521 radeon_gart_restore(rdev);
771fe6b9
JG		 522 /* discard memory request outside of configured range */
523 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
524 WREG32(RADEON_AIC_CNTL, tmp);
525 /* set address range for PCI address translate */
d594e46a
JG		 526 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
527 WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
771fe6b9
JG		 528 /* set PCI GART page-table base address */
529 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
530 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
531 WREG32(RADEON_AIC_CNTL, tmp);
532 r100_pci_gart_tlb_flush(rdev);
533 rdev->gart.ready = true;
534 return 0;
535}
536
537void r100_pci_gart_disable(struct radeon_device *rdev)
538{
539 uint32_t tmp;
540
541 /* discard memory request outside of configured range */
542 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
543 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
544 WREG32(RADEON_AIC_LO_ADDR, 0);
545 WREG32(RADEON_AIC_HI_ADDR, 0);
546}
547
548int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
549{
550 if (i < 0 || i > rdev->gart.num_gpu_pages) {
551 return -EINVAL;
552 }
ed10f95d 553 rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr));
771fe6b9
JG		 554 return 0;
555}
556
4aac0473 557void r100_pci_gart_fini(struct radeon_device *rdev)
771fe6b9 558{
f9274562 559 radeon_gart_fini(rdev);
4aac0473
JG		 560 r100_pci_gart_disable(rdev);
561 radeon_gart_table_ram_free(rdev);
771fe6b9
JG		 562}
563
7ed220d7
MD		 564int r100_irq_set(struct radeon_device *rdev)
565{
566 uint32_t tmp = 0;
567
003e69f9 568 if (!rdev->irq.installed) {
fce7d61b 569 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
003e69f9
JG		 570 WREG32(R_000040_GEN_INT_CNTL, 0);
571 return -EINVAL;
572 }
7ed220d7
MD		 573 if (rdev->irq.sw_int) {
574 tmp |= RADEON_SW_INT_ENABLE;
575 }
2031f77c
AD		 576 if (rdev->irq.gui_idle) {
577 tmp |= RADEON_GUI_IDLE_MASK;
578 }
6f34be50
AD		 579 if (rdev->irq.crtc_vblank_int[0] ||
580 rdev->irq.pflip[0]) {
7ed220d7
MD		 581 tmp |= RADEON_CRTC_VBLANK_MASK;
582 }
6f34be50
AD		 583 if (rdev->irq.crtc_vblank_int[1] ||
584 rdev->irq.pflip[1]) {
7ed220d7
MD		 585 tmp |= RADEON_CRTC2_VBLANK_MASK;
586 }
05a05c50
AD		 587 if (rdev->irq.hpd[0]) {
588 tmp |= RADEON_FP_DETECT_MASK;
589 }
590 if (rdev->irq.hpd[1]) {
591 tmp |= RADEON_FP2_DETECT_MASK;
592 }
7ed220d7
MD		 593 WREG32(RADEON_GEN_INT_CNTL, tmp);
594 return 0;
595}
596
9f022ddf
JG		 597void r100_irq_disable(struct radeon_device *rdev)
598{
599 u32 tmp;
600
601 WREG32(R_000040_GEN_INT_CNTL, 0);
602 /* Wait and acknowledge irq */
603 mdelay(1);
604 tmp = RREG32(R_000044_GEN_INT_STATUS);
605 WREG32(R_000044_GEN_INT_STATUS, tmp);
606}
607
7ed220d7
MD		 608static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
609{
610 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
05a05c50
AD		 611 uint32_t irq_mask = RADEON_SW_INT_TEST |
612 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
613 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
7ed220d7 614
2031f77c
AD		 615 /* the interrupt works, but the status bit is permanently asserted */
616 if (rdev->irq.gui_idle && radeon_gui_idle(rdev)) {
617 if (!rdev->irq.gui_idle_acked)
618 irq_mask |= RADEON_GUI_IDLE_STAT;
619 }
620
7ed220d7
MD		 621 if (irqs) {
622 WREG32(RADEON_GEN_INT_STATUS, irqs);
623 }
624 return irqs & irq_mask;
625}
626
627int r100_irq_process(struct radeon_device *rdev)
628{
3e5cb98d 629 uint32_t status, msi_rearm;
d4877cf2 630 bool queue_hotplug = false;
7ed220d7 631
2031f77c
AD		 632 /* reset gui idle ack. the status bit is broken */
633 rdev->irq.gui_idle_acked = false;
634
7ed220d7
MD		 635 status = r100_irq_ack(rdev);
636 if (!status) {
637 return IRQ_NONE;
638 }
a513c184
JG		 639 if (rdev->shutdown) {
640 return IRQ_NONE;
641 }
7ed220d7
MD		 642 while (status) {
643 /* SW interrupt */
644 if (status & RADEON_SW_INT_TEST) {
645 radeon_fence_process(rdev);
646 }
2031f77c
AD		 647 /* gui idle interrupt */
648 if (status & RADEON_GUI_IDLE_STAT) {
649 rdev->irq.gui_idle_acked = true;
650 rdev->pm.gui_idle = true;
651 wake_up(&rdev->irq.idle_queue);
652 }
7ed220d7
MD		 653 /* Vertical blank interrupts */
654 if (status & RADEON_CRTC_VBLANK_STAT) {
6f34be50
AD		 655 if (rdev->irq.crtc_vblank_int[0]) {
656 drm_handle_vblank(rdev->ddev, 0);
657 rdev->pm.vblank_sync = true;
658 wake_up(&rdev->irq.vblank_queue);
659 }
3e4ea742
MK		 660 if (rdev->irq.pflip[0])
661 radeon_crtc_handle_flip(rdev, 0);
7ed220d7
MD		 662 }
663 if (status & RADEON_CRTC2_VBLANK_STAT) {
6f34be50
AD		 664 if (rdev->irq.crtc_vblank_int[1]) {
665 drm_handle_vblank(rdev->ddev, 1);
666 rdev->pm.vblank_sync = true;
667 wake_up(&rdev->irq.vblank_queue);
668 }
3e4ea742
MK		 669 if (rdev->irq.pflip[1])
670 radeon_crtc_handle_flip(rdev, 1);
7ed220d7 671 }
05a05c50 672 if (status & RADEON_FP_DETECT_STAT) {
d4877cf2
AD		 673 queue_hotplug = true;
674 DRM_DEBUG("HPD1\n");
05a05c50
AD		 675 }
676 if (status & RADEON_FP2_DETECT_STAT) {
d4877cf2
AD		 677 queue_hotplug = true;
678 DRM_DEBUG("HPD2\n");
05a05c50 679 }
7ed220d7
MD		 680 status = r100_irq_ack(rdev);
681 }
2031f77c
AD		 682 /* reset gui idle ack. the status bit is broken */
683 rdev->irq.gui_idle_acked = false;
d4877cf2 684 if (queue_hotplug)
32c87fca 685 schedule_work(&rdev->hotplug_work);
3e5cb98d
AD		 686 if (rdev->msi_enabled) {
687 switch (rdev->family) {
688 case CHIP_RS400:
689 case CHIP_RS480:
690 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
691 WREG32(RADEON_AIC_CNTL, msi_rearm);
692 WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
693 break;
694 default:
695 msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN;
696 WREG32(RADEON_MSI_REARM_EN, msi_rearm);
697 WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN);
698 break;
699 }
700 }
7ed220d7
MD		 701 return IRQ_HANDLED;
702}
703
704u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
705{
706 if (crtc == 0)
707 return RREG32(RADEON_CRTC_CRNT_FRAME);
708 else
709 return RREG32(RADEON_CRTC2_CRNT_FRAME);
710}
711
9e5b2af7
PN		 712/* Who ever call radeon_fence_emit should call ring_lock and ask
713 * for enough space (today caller are ib schedule and buffer move) */
771fe6b9
JG		 714void r100_fence_ring_emit(struct radeon_device *rdev,
715 struct radeon_fence *fence)
716{
9e5b2af7
PN		 717 /* We have to make sure that caches are flushed before
718 * CPU might read something from VRAM. */
719 radeon_ring_write(rdev, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
720 radeon_ring_write(rdev, RADEON_RB3D_DC_FLUSH_ALL);
721 radeon_ring_write(rdev, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
722 radeon_ring_write(rdev, RADEON_RB3D_ZC_FLUSH_ALL);
771fe6b9 723 /* Wait until IDLE & CLEAN */
4612dc97
AD		 724 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
725 radeon_ring_write(rdev, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
cafe6609
JG		 726 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
727 radeon_ring_write(rdev, rdev->config.r100.hdp_cntl |
728 RADEON_HDP_READ_BUFFER_INVALIDATE);
729 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
730 radeon_ring_write(rdev, rdev->config.r100.hdp_cntl);
771fe6b9
JG		 731 /* Emit fence sequence & fire IRQ */
732 radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
733 radeon_ring_write(rdev, fence->seq);
734 radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
735 radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
736}
737
771fe6b9
JG		 738int r100_copy_blit(struct radeon_device *rdev,
739 uint64_t src_offset,
740 uint64_t dst_offset,
741 unsigned num_pages,
742 struct radeon_fence *fence)
743{
744 uint32_t cur_pages;
745 uint32_t stride_bytes = PAGE_SIZE;
746 uint32_t pitch;
747 uint32_t stride_pixels;
748 unsigned ndw;
749 int num_loops;
750 int r = 0;
751
752 /* radeon limited to 16k stride */
753 stride_bytes &= 0x3fff;
754 /* radeon pitch is /64 */
755 pitch = stride_bytes / 64;
756 stride_pixels = stride_bytes / 4;
757 num_loops = DIV_ROUND_UP(num_pages, 8191);
758
759 /* Ask for enough room for blit + flush + fence */
760 ndw = 64 + (10 * num_loops);
761 r = radeon_ring_lock(rdev, ndw);
762 if (r) {
763 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
764 return -EINVAL;
765 }
766 while (num_pages > 0) {
767 cur_pages = num_pages;
768 if (cur_pages > 8191) {
769 cur_pages = 8191;
770 }
771 num_pages -= cur_pages;
772
773 /* pages are in Y direction - height
774 page width in X direction - width */
775 radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8));
776 radeon_ring_write(rdev,
777 RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
778 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
779 RADEON_GMC_SRC_CLIPPING |
780 RADEON_GMC_DST_CLIPPING |
781 RADEON_GMC_BRUSH_NONE |
782 (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
783 RADEON_GMC_SRC_DATATYPE_COLOR |
784 RADEON_ROP3_S |
785 RADEON_DP_SRC_SOURCE_MEMORY |
786 RADEON_GMC_CLR_CMP_CNTL_DIS |
787 RADEON_GMC_WR_MSK_DIS);
788 radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10));
789 radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10));
790 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
791 radeon_ring_write(rdev, 0);
792 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
793 radeon_ring_write(rdev, num_pages);
794 radeon_ring_write(rdev, num_pages);
795 radeon_ring_write(rdev, cur_pages | (stride_pixels << 16));
796 }
797 radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
798 radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL);
799 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
800 radeon_ring_write(rdev,
801 RADEON_WAIT_2D_IDLECLEAN |
802 RADEON_WAIT_HOST_IDLECLEAN |
803 RADEON_WAIT_DMA_GUI_IDLE);
804 if (fence) {
805 r = radeon_fence_emit(rdev, fence);
806 }
807 radeon_ring_unlock_commit(rdev);
808 return r;
809}
810
45600232
JG		 811static int r100_cp_wait_for_idle(struct radeon_device *rdev)
812{
813 unsigned i;
814 u32 tmp;
815
816 for (i = 0; i < rdev->usec_timeout; i++) {
817 tmp = RREG32(R_000E40_RBBM_STATUS);
818 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
819 return 0;
820 }
821 udelay(1);
822 }
823 return -1;
824}
825
771fe6b9
JG		 826void r100_ring_start(struct radeon_device *rdev)
827{
828 int r;
829
830 r = radeon_ring_lock(rdev, 2);
831 if (r) {
832 return;
833 }
834 radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
835 radeon_ring_write(rdev,
836 RADEON_ISYNC_ANY2D_IDLE3D |
837 RADEON_ISYNC_ANY3D_IDLE2D |
838 RADEON_ISYNC_WAIT_IDLEGUI |
839 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
840 radeon_ring_unlock_commit(rdev);
841}
842
70967ab9
BH		 843
844/* Load the microcode for the CP */
845static int r100_cp_init_microcode(struct radeon_device *rdev)
771fe6b9 846{
70967ab9
BH		 847 struct platform_device *pdev;
848 const char *fw_name = NULL;
849 int err;
771fe6b9 850
d9fdaafb 851 DRM_DEBUG_KMS("\n");
771fe6b9 852
70967ab9
BH		 853 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
854 err = IS_ERR(pdev);
855 if (err) {
856 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
857 return -EINVAL;
858 }
771fe6b9
JG		 859 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
860 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
861 (rdev->family == CHIP_RS200)) {
862 DRM_INFO("Loading R100 Microcode\n");
70967ab9 863 fw_name = FIRMWARE_R100;
771fe6b9
JG		 864 } else if ((rdev->family == CHIP_R200) ||
865 (rdev->family == CHIP_RV250) ||
866 (rdev->family == CHIP_RV280) ||
867 (rdev->family == CHIP_RS300)) {
868 DRM_INFO("Loading R200 Microcode\n");
70967ab9 869 fw_name = FIRMWARE_R200;
771fe6b9
JG		 870 } else if ((rdev->family == CHIP_R300) ||
871 (rdev->family == CHIP_R350) ||
872 (rdev->family == CHIP_RV350) ||
873 (rdev->family == CHIP_RV380) ||
874 (rdev->family == CHIP_RS400) ||
875 (rdev->family == CHIP_RS480)) {
876 DRM_INFO("Loading R300 Microcode\n");
70967ab9 877 fw_name = FIRMWARE_R300;
771fe6b9
JG		 878 } else if ((rdev->family == CHIP_R420) ||
879 (rdev->family == CHIP_R423) ||
880 (rdev->family == CHIP_RV410)) {
881 DRM_INFO("Loading R400 Microcode\n");
70967ab9 882 fw_name = FIRMWARE_R420;
771fe6b9
JG		 883 } else if ((rdev->family == CHIP_RS690) ||
884 (rdev->family == CHIP_RS740)) {
885 DRM_INFO("Loading RS690/RS740 Microcode\n");
70967ab9 886 fw_name = FIRMWARE_RS690;
771fe6b9
JG		 887 } else if (rdev->family == CHIP_RS600) {
888 DRM_INFO("Loading RS600 Microcode\n");
70967ab9 889 fw_name = FIRMWARE_RS600;
771fe6b9
JG		 890 } else if ((rdev->family == CHIP_RV515) ||
891 (rdev->family == CHIP_R520) ||
892 (rdev->family == CHIP_RV530) ||
893 (rdev->family == CHIP_R580) ||
894 (rdev->family == CHIP_RV560) ||
895 (rdev->family == CHIP_RV570)) {
896 DRM_INFO("Loading R500 Microcode\n");
70967ab9
BH		 897 fw_name = FIRMWARE_R520;
898 }
899
3ce0a23d 900 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
70967ab9
BH		 901 platform_device_unregister(pdev);
902 if (err) {
903 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
904 fw_name);
3ce0a23d 905 } else if (rdev->me_fw->size % 8) {
70967ab9
BH		 906 printk(KERN_ERR
907 "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
3ce0a23d 908 rdev->me_fw->size, fw_name);
70967ab9 909 err = -EINVAL;
3ce0a23d
JG		 910 release_firmware(rdev->me_fw);
911 rdev->me_fw = NULL;
70967ab9
BH		 912 }
913 return err;
914}
d4550907 915
70967ab9
BH		 916static void r100_cp_load_microcode(struct radeon_device *rdev)
917{
918 const __be32 *fw_data;
919 int i, size;
920
921 if (r100_gui_wait_for_idle(rdev)) {
922 printk(KERN_WARNING "Failed to wait GUI idle while "
923 "programming pipes. Bad things might happen.\n");
924 }
925
3ce0a23d
JG		 926 if (rdev->me_fw) {
927 size = rdev->me_fw->size / 4;
928 fw_data = (const __be32 *)&rdev->me_fw->data[0];
70967ab9
BH		 929 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
930 for (i = 0; i < size; i += 2) {
931 WREG32(RADEON_CP_ME_RAM_DATAH,
932 be32_to_cpup(&fw_data[i]));
933 WREG32(RADEON_CP_ME_RAM_DATAL,
934 be32_to_cpup(&fw_data[i + 1]));
771fe6b9
JG		 935 }
936 }
937}
938
939int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
940{
941 unsigned rb_bufsz;
942 unsigned rb_blksz;
943 unsigned max_fetch;
944 unsigned pre_write_timer;
945 unsigned pre_write_limit;
946 unsigned indirect2_start;
947 unsigned indirect1_start;
948 uint32_t tmp;
949 int r;
950
951 if (r100_debugfs_cp_init(rdev)) {
952 DRM_ERROR("Failed to register debugfs file for CP !\n");
953 }
3ce0a23d 954 if (!rdev->me_fw) {
70967ab9
BH		 955 r = r100_cp_init_microcode(rdev);
956 if (r) {
957 DRM_ERROR("Failed to load firmware!\n");
958 return r;
959 }
960 }
961
771fe6b9
JG		 962 /* Align ring size */
963 rb_bufsz = drm_order(ring_size / 8);
964 ring_size = (1 << (rb_bufsz + 1)) * 4;
965 r100_cp_load_microcode(rdev);
966 r = radeon_ring_init(rdev, ring_size);
967 if (r) {
968 return r;
969 }
970 /* Each time the cp read 1024 bytes (16 dword/quadword) update
971 * the rptr copy in system ram */
972 rb_blksz = 9;
973 /* cp will read 128bytes at a time (4 dwords) */
974 max_fetch = 1;
975 rdev->cp.align_mask = 16 - 1;
976 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
977 pre_write_timer = 64;
978 /* Force CP_RB_WPTR write if written more than one time before the
979 * delay expire
980 */
981 pre_write_limit = 0;
982 /* Setup the cp cache like this (cache size is 96 dwords) :
983 * RING 0 to 15
984 * INDIRECT1 16 to 79
985 * INDIRECT2 80 to 95
986 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
987 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
988 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
989 * Idea being that most of the gpu cmd will be through indirect1 buffer
990 * so it gets the bigger cache.
991 */
992 indirect2_start = 80;
993 indirect1_start = 16;
994 /* cp setup */
995 WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
d6f28938 996 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
771fe6b9 997 REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
724c80e1 998 REG_SET(RADEON_MAX_FETCH, max_fetch));
d6f28938
AD		 999#ifdef __BIG_ENDIAN
1000 tmp |= RADEON_BUF_SWAP_32BIT;
1001#endif
724c80e1 1002 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE);
d6f28938 1003
771fe6b9
JG		 1004 /* Set ring address */
1005 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
1006 WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
1007 /* Force read & write ptr to 0 */
724c80e1 1008 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE);
771fe6b9
JG		 1009 WREG32(RADEON_CP_RB_RPTR_WR, 0);
1010 WREG32(RADEON_CP_RB_WPTR, 0);
724c80e1
AD		 1011
1012 /* set the wb address whether it's enabled or not */
1013 WREG32(R_00070C_CP_RB_RPTR_ADDR,
1014 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2));
1015 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET);
1016
1017 if (rdev->wb.enabled)
1018 WREG32(R_000770_SCRATCH_UMSK, 0xff);
1019 else {
1020 tmp |= RADEON_RB_NO_UPDATE;
1021 WREG32(R_000770_SCRATCH_UMSK, 0);
1022 }
1023
771fe6b9
JG		 1024 WREG32(RADEON_CP_RB_CNTL, tmp);
1025 udelay(10);
1026 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
1027 rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR);
9e5786bd
DA		 1028 /* protect against crazy HW on resume */
1029 rdev->cp.wptr &= rdev->cp.ptr_mask;
771fe6b9
JG		 1030 /* Set cp mode to bus mastering & enable cp*/
1031 WREG32(RADEON_CP_CSQ_MODE,
1032 REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
1033 REG_SET(RADEON_INDIRECT1_START, indirect1_start));
d75ee3be
AD		 1034 WREG32(RADEON_CP_RB_WPTR_DELAY, 0);
1035 WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D);
771fe6b9
JG		 1036 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
1037 radeon_ring_start(rdev);
1038 r = radeon_ring_test(rdev);
1039 if (r) {
1040 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
1041 return r;
1042 }
1043 rdev->cp.ready = true;
c919b371 1044 rdev->mc.active_vram_size = rdev->mc.real_vram_size;
771fe6b9
JG		 1045 return 0;
1046}
1047
1048void r100_cp_fini(struct radeon_device *rdev)
1049{
45600232
JG		 1050 if (r100_cp_wait_for_idle(rdev)) {
1051 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
1052 }
771fe6b9 1053 /* Disable ring */
a18d7ea1 1054 r100_cp_disable(rdev);
771fe6b9
JG		 1055 radeon_ring_fini(rdev);
1056 DRM_INFO("radeon: cp finalized\n");
1057}
1058
1059void r100_cp_disable(struct radeon_device *rdev)
1060{
1061 /* Disable ring */
c919b371 1062 rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
771fe6b9
JG		 1063 rdev->cp.ready = false;
1064 WREG32(RADEON_CP_CSQ_MODE, 0);
1065 WREG32(RADEON_CP_CSQ_CNTL, 0);
724c80e1 1066 WREG32(R_000770_SCRATCH_UMSK, 0);
771fe6b9
JG		 1067 if (r100_gui_wait_for_idle(rdev)) {
1068 printk(KERN_WARNING "Failed to wait GUI idle while "
1069 "programming pipes. Bad things might happen.\n");
1070 }
1071}
1072
3ce0a23d
JG		 1073void r100_cp_commit(struct radeon_device *rdev)
1074{
1075 WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
1076 (void)RREG32(RADEON_CP_RB_WPTR);
1077}
1078
771fe6b9
JG		 1079
1080/*
1081 * CS functions
1082 */
1083int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1084 struct radeon_cs_packet *pkt,
068a117c 1085 const unsigned *auth, unsigned n,
771fe6b9
JG		 1086 radeon_packet0_check_t check)
1087{
1088 unsigned reg;
1089 unsigned i, j, m;
1090 unsigned idx;
1091 int r;
1092
1093 idx = pkt->idx + 1;
1094 reg = pkt->reg;
068a117c
JG		 1095 /* Check that register fall into register range
1096 * determined by the number of entry (n) in the
1097 * safe register bitmap.
1098 */
771fe6b9
JG		 1099 if (pkt->one_reg_wr) {
1100 if ((reg >> 7) > n) {
1101 return -EINVAL;
1102 }
1103 } else {
1104 if (((reg + (pkt->count << 2)) >> 7) > n) {
1105 return -EINVAL;
1106 }
1107 }
1108 for (i = 0; i <= pkt->count; i++, idx++) {
1109 j = (reg >> 7);
1110 m = 1 << ((reg >> 2) & 31);
1111 if (auth[j] & m) {
1112 r = check(p, pkt, idx, reg);
1113 if (r) {
1114 return r;
1115 }
1116 }
1117 if (pkt->one_reg_wr) {
1118 if (!(auth[j] & m)) {
1119 break;
1120 }
1121 } else {
1122 reg += 4;
1123 }
1124 }
1125 return 0;
1126}
1127
771fe6b9
JG		 1128void r100_cs_dump_packet(struct radeon_cs_parser *p,
1129 struct radeon_cs_packet *pkt)
1130{
771fe6b9
JG		 1131 volatile uint32_t *ib;
1132 unsigned i;
1133 unsigned idx;
1134
1135 ib = p->ib->ptr;
771fe6b9
JG		 1136 idx = pkt->idx;
1137 for (i = 0; i <= (pkt->count + 1); i++, idx++) {
1138 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
1139 }
1140}
1141
1142/**
1143 * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
1144 * @parser: parser structure holding parsing context.
1145 * @pkt: where to store packet informations
1146 *
1147 * Assume that chunk_ib_index is properly set. Will return -EINVAL
1148 * if packet is bigger than remaining ib size. or if packets is unknown.
1149 **/
1150int r100_cs_packet_parse(struct radeon_cs_parser *p,
1151 struct radeon_cs_packet *pkt,
1152 unsigned idx)
1153{
1154 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
fa99239c 1155 uint32_t header;
771fe6b9
JG		 1156
1157 if (idx >= ib_chunk->length_dw) {
1158 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
1159 idx, ib_chunk->length_dw);
1160 return -EINVAL;
1161 }
513bcb46 1162 header = radeon_get_ib_value(p, idx);
771fe6b9
JG		 1163 pkt->idx = idx;
1164 pkt->type = CP_PACKET_GET_TYPE(header);
1165 pkt->count = CP_PACKET_GET_COUNT(header);
1166 switch (pkt->type) {
1167 case PACKET_TYPE0:
1168 pkt->reg = CP_PACKET0_GET_REG(header);
1169 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
1170 break;
1171 case PACKET_TYPE3:
1172 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
1173 break;
1174 case PACKET_TYPE2:
1175 pkt->count = -1;
1176 break;
1177 default:
1178 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
1179 return -EINVAL;
1180 }
1181 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
1182 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
1183 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
1184 return -EINVAL;
1185 }
1186 return 0;
1187}
1188
531369e6
DA		 1189/**
1190 * r100_cs_packet_next_vline() - parse userspace VLINE packet
1191 * @parser: parser structure holding parsing context.
1192 *
1193 * Userspace sends a special sequence for VLINE waits.
1194 * PACKET0 - VLINE_START_END + value
1195 * PACKET0 - WAIT_UNTIL +_value
1196 * RELOC (P3) - crtc_id in reloc.
1197 *
1198 * This function parses this and relocates the VLINE START END
1199 * and WAIT UNTIL packets to the correct crtc.
1200 * It also detects a switched off crtc and nulls out the
1201 * wait in that case.
1202 */
1203int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
1204{
531369e6
DA		 1205 struct drm_mode_object *obj;
1206 struct drm_crtc *crtc;
1207 struct radeon_crtc *radeon_crtc;
1208 struct radeon_cs_packet p3reloc, waitreloc;
1209 int crtc_id;
1210 int r;
1211 uint32_t header, h_idx, reg;
513bcb46 1212 volatile uint32_t *ib;
531369e6 1213
513bcb46 1214 ib = p->ib->ptr;
531369e6
DA		 1215
1216 /* parse the wait until */
1217 r = r100_cs_packet_parse(p, &waitreloc, p->idx);
1218 if (r)
1219 return r;
1220
1221 /* check its a wait until and only 1 count */
1222 if (waitreloc.reg != RADEON_WAIT_UNTIL ||
1223 waitreloc.count != 0) {
1224 DRM_ERROR("vline wait had illegal wait until segment\n");
1225 r = -EINVAL;
1226 return r;
1227 }
1228
513bcb46 1229 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
531369e6
DA		 1230 DRM_ERROR("vline wait had illegal wait until\n");
1231 r = -EINVAL;
1232 return r;
1233 }
1234
1235 /* jump over the NOP */
90ebd065 1236 r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
531369e6
DA		 1237 if (r)
1238 return r;
1239
1240 h_idx = p->idx - 2;
90ebd065
AD		 1241 p->idx += waitreloc.count + 2;
1242 p->idx += p3reloc.count + 2;
531369e6 1243
513bcb46
DA		 1244 header = radeon_get_ib_value(p, h_idx);
1245 crtc_id = radeon_get_ib_value(p, h_idx + 5);
d4ac6a05 1246 reg = CP_PACKET0_GET_REG(header);
531369e6
DA		 1247 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
1248 if (!obj) {
1249 DRM_ERROR("cannot find crtc %d\n", crtc_id);
1250 r = -EINVAL;
1251 goto out;
1252 }
1253 crtc = obj_to_crtc(obj);
1254 radeon_crtc = to_radeon_crtc(crtc);
1255 crtc_id = radeon_crtc->crtc_id;
1256
1257 if (!crtc->enabled) {
1258 /* if the CRTC isn't enabled - we need to nop out the wait until */
513bcb46
DA		 1259 ib[h_idx + 2] = PACKET2(0);
1260 ib[h_idx + 3] = PACKET2(0);
531369e6
DA		 1261 } else if (crtc_id == 1) {
1262 switch (reg) {
1263 case AVIVO_D1MODE_VLINE_START_END:
90ebd065 1264 header &= ~R300_CP_PACKET0_REG_MASK;
531369e6
DA		 1265 header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1266 break;
1267 case RADEON_CRTC_GUI_TRIG_VLINE:
90ebd065 1268 header &= ~R300_CP_PACKET0_REG_MASK;
531369e6
DA		 1269 header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1270 break;
1271 default:
1272 DRM_ERROR("unknown crtc reloc\n");
1273 r = -EINVAL;
1274 goto out;
1275 }
513bcb46
DA		 1276 ib[h_idx] = header;
1277 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
531369e6
DA		 1278 }
1279out:
531369e6
DA		 1280 return r;
1281}
1282
771fe6b9
JG		 1283/**
1284 * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
1285 * @parser: parser structure holding parsing context.
1286 * @data: pointer to relocation data
1287 * @offset_start: starting offset
1288 * @offset_mask: offset mask (to align start offset on)
1289 * @reloc: reloc informations
1290 *
1291 * Check next packet is relocation packet3, do bo validation and compute
1292 * GPU offset using the provided start.
1293 **/
1294int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
1295 struct radeon_cs_reloc **cs_reloc)
1296{
771fe6b9
JG		 1297 struct radeon_cs_chunk *relocs_chunk;
1298 struct radeon_cs_packet p3reloc;
1299 unsigned idx;
1300 int r;
1301
1302 if (p->chunk_relocs_idx == -1) {
1303 DRM_ERROR("No relocation chunk !\n");
1304 return -EINVAL;
1305 }
1306 *cs_reloc = NULL;
771fe6b9
JG		 1307 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
1308 r = r100_cs_packet_parse(p, &p3reloc, p->idx);
1309 if (r) {
1310 return r;
1311 }
1312 p->idx += p3reloc.count + 2;
1313 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
1314 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1315 p3reloc.idx);
1316 r100_cs_dump_packet(p, &p3reloc);
1317 return -EINVAL;
1318 }
513bcb46 1319 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
771fe6b9
JG		 1320 if (idx >= relocs_chunk->length_dw) {
1321 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1322 idx, relocs_chunk->length_dw);
1323 r100_cs_dump_packet(p, &p3reloc);
1324 return -EINVAL;
1325 }
1326 /* FIXME: we assume reloc size is 4 dwords */
1327 *cs_reloc = p->relocs_ptr[(idx / 4)];
1328 return 0;
1329}
1330
551ebd83
DA		 1331static int r100_get_vtx_size(uint32_t vtx_fmt)
1332{
1333 int vtx_size;
1334 vtx_size = 2;
1335 /* ordered according to bits in spec */
1336 if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1337 vtx_size++;
1338 if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1339 vtx_size += 3;
1340 if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1341 vtx_size++;
1342 if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1343 vtx_size++;
1344 if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1345 vtx_size += 3;
1346 if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1347 vtx_size++;
1348 if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1349 vtx_size++;
1350 if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1351 vtx_size += 2;
1352 if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1353 vtx_size += 2;
1354 if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1355 vtx_size++;
1356 if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1357 vtx_size += 2;
1358 if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1359 vtx_size++;
1360 if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1361 vtx_size += 2;
1362 if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1363 vtx_size++;
1364 if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1365 vtx_size++;
1366 /* blend weight */
1367 if (vtx_fmt & (0x7 << 15))
1368 vtx_size += (vtx_fmt >> 15) & 0x7;
1369 if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1370 vtx_size += 3;
1371 if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1372 vtx_size += 2;
1373 if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1374 vtx_size++;
1375 if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1376 vtx_size++;
1377 if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1378 vtx_size++;
1379 if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1380 vtx_size++;
1381 return vtx_size;
1382}
1383
771fe6b9 1384static int r100_packet0_check(struct radeon_cs_parser *p,
551ebd83
DA		 1385 struct radeon_cs_packet *pkt,
1386 unsigned idx, unsigned reg)
771fe6b9 1387{
771fe6b9 1388 struct radeon_cs_reloc *reloc;
551ebd83 1389 struct r100_cs_track *track;
771fe6b9
JG		 1390 volatile uint32_t *ib;
1391 uint32_t tmp;
771fe6b9 1392 int r;
551ebd83 1393 int i, face;
e024e110 1394 u32 tile_flags = 0;
513bcb46 1395 u32 idx_value;
771fe6b9
JG		 1396
1397 ib = p->ib->ptr;
551ebd83
DA		 1398 track = (struct r100_cs_track *)p->track;
1399
513bcb46
DA		 1400 idx_value = radeon_get_ib_value(p, idx);
1401
551ebd83
DA		 1402 switch (reg) {
1403 case RADEON_CRTC_GUI_TRIG_VLINE:
1404 r = r100_cs_packet_parse_vline(p);
1405 if (r) {
1406 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1407 idx, reg);
1408 r100_cs_dump_packet(p, pkt);
1409 return r;
1410 }
1411 break;
771fe6b9
JG		 1412 /* FIXME: only allow PACKET3 blit? easier to check for out of
1413 * range access */
551ebd83
DA		 1414 case RADEON_DST_PITCH_OFFSET:
1415 case RADEON_SRC_PITCH_OFFSET:
1416 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1417 if (r)
1418 return r;
1419 break;
1420 case RADEON_RB3D_DEPTHOFFSET:
1421 r = r100_cs_packet_next_reloc(p, &reloc);
1422 if (r) {
1423 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1424 idx, reg);
1425 r100_cs_dump_packet(p, pkt);
1426 return r;
1427 }
1428 track->zb.robj = reloc->robj;
513bcb46
DA		 1429 track->zb.offset = idx_value;
1430 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1431 break;
1432 case RADEON_RB3D_COLOROFFSET:
1433 r = r100_cs_packet_next_reloc(p, &reloc);
1434 if (r) {
1435 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1436 idx, reg);
1437 r100_cs_dump_packet(p, pkt);
1438 return r;
1439 }
1440 track->cb[0].robj = reloc->robj;
513bcb46
DA		 1441 track->cb[0].offset = idx_value;
1442 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1443 break;
1444 case RADEON_PP_TXOFFSET_0:
1445 case RADEON_PP_TXOFFSET_1:
1446 case RADEON_PP_TXOFFSET_2:
1447 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1448 r = r100_cs_packet_next_reloc(p, &reloc);
1449 if (r) {
1450 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1451 idx, reg);
1452 r100_cs_dump_packet(p, pkt);
1453 return r;
1454 }
513bcb46 1455 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1456 track->textures[i].robj = reloc->robj;
1457 break;
1458 case RADEON_PP_CUBIC_OFFSET_T0_0:
1459 case RADEON_PP_CUBIC_OFFSET_T0_1:
1460 case RADEON_PP_CUBIC_OFFSET_T0_2:
1461 case RADEON_PP_CUBIC_OFFSET_T0_3:
1462 case RADEON_PP_CUBIC_OFFSET_T0_4:
1463 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1464 r = r100_cs_packet_next_reloc(p, &reloc);
1465 if (r) {
1466 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1467 idx, reg);
1468 r100_cs_dump_packet(p, pkt);
1469 return r;
1470 }
513bcb46
DA		 1471 track->textures[0].cube_info[i].offset = idx_value;
1472 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1473 track->textures[0].cube_info[i].robj = reloc->robj;
1474 break;
1475 case RADEON_PP_CUBIC_OFFSET_T1_0:
1476 case RADEON_PP_CUBIC_OFFSET_T1_1:
1477 case RADEON_PP_CUBIC_OFFSET_T1_2:
1478 case RADEON_PP_CUBIC_OFFSET_T1_3:
1479 case RADEON_PP_CUBIC_OFFSET_T1_4:
1480 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1481 r = r100_cs_packet_next_reloc(p, &reloc);
1482 if (r) {
1483 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1484 idx, reg);
1485 r100_cs_dump_packet(p, pkt);
1486 return r;
1487 }
513bcb46
DA		 1488 track->textures[1].cube_info[i].offset = idx_value;
1489 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1490 track->textures[1].cube_info[i].robj = reloc->robj;
1491 break;
1492 case RADEON_PP_CUBIC_OFFSET_T2_0:
1493 case RADEON_PP_CUBIC_OFFSET_T2_1:
1494 case RADEON_PP_CUBIC_OFFSET_T2_2:
1495 case RADEON_PP_CUBIC_OFFSET_T2_3:
1496 case RADEON_PP_CUBIC_OFFSET_T2_4:
1497 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1498 r = r100_cs_packet_next_reloc(p, &reloc);
1499 if (r) {
1500 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1501 idx, reg);
1502 r100_cs_dump_packet(p, pkt);
1503 return r;
1504 }
513bcb46
DA		 1505 track->textures[2].cube_info[i].offset = idx_value;
1506 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1507 track->textures[2].cube_info[i].robj = reloc->robj;
1508 break;
1509 case RADEON_RE_WIDTH_HEIGHT:
513bcb46 1510 track->maxy = ((idx_value >> 16) & 0x7FF);
551ebd83
DA		 1511 break;
1512 case RADEON_RB3D_COLORPITCH:
1513 r = r100_cs_packet_next_reloc(p, &reloc);
1514 if (r) {
1515 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1516 idx, reg);
1517 r100_cs_dump_packet(p, pkt);
1518 return r;
1519 }
e024e110 1520
551ebd83
DA		 1521 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1522 tile_flags |= RADEON_COLOR_TILE_ENABLE;
1523 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1524 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
e024e110 1525
513bcb46 1526 tmp = idx_value & ~(0x7 << 16);
551ebd83
DA		 1527 tmp |= tile_flags;
1528 ib[idx] = tmp;
e024e110 1529
513bcb46 1530 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
551ebd83
DA		 1531 break;
1532 case RADEON_RB3D_DEPTHPITCH:
513bcb46 1533 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
551ebd83
DA		 1534 break;
1535 case RADEON_RB3D_CNTL:
513bcb46 1536 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
551ebd83
DA		 1537 case 7:
1538 case 8:
1539 case 9:
1540 case 11:
1541 case 12:
1542 track->cb[0].cpp = 1;
e024e110 1543 break;
551ebd83
DA		 1544 case 3:
1545 case 4:
1546 case 15:
1547 track->cb[0].cpp = 2;
1548 break;
1549 case 6:
1550 track->cb[0].cpp = 4;
1551 break;
1552 default:
1553 DRM_ERROR("Invalid color buffer format (%d) !\n",
513bcb46 1554 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
551ebd83
DA		 1555 return -EINVAL;
1556 }
513bcb46 1557 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
551ebd83
DA		 1558 break;
1559 case RADEON_RB3D_ZSTENCILCNTL:
513bcb46 1560 switch (idx_value & 0xf) {
551ebd83
DA		 1561 case 0:
1562 track->zb.cpp = 2;
1563 break;
1564 case 2:
1565 case 3:
1566 case 4:
1567 case 5:
1568 case 9:
1569 case 11:
1570 track->zb.cpp = 4;
17782d99 1571 break;
771fe6b9 1572 default:
771fe6b9
JG		 1573 break;
1574 }
551ebd83
DA		 1575 break;
1576 case RADEON_RB3D_ZPASS_ADDR:
1577 r = r100_cs_packet_next_reloc(p, &reloc);
1578 if (r) {
1579 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1580 idx, reg);
1581 r100_cs_dump_packet(p, pkt);
1582 return r;
1583 }
513bcb46 1584 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
551ebd83
DA		 1585 break;
1586 case RADEON_PP_CNTL:
1587 {
513bcb46 1588 uint32_t temp = idx_value >> 4;
551ebd83
DA		 1589 for (i = 0; i < track->num_texture; i++)
1590 track->textures[i].enabled = !!(temp & (1 << i));
1591 }
1592 break;
1593 case RADEON_SE_VF_CNTL:
513bcb46 1594 track->vap_vf_cntl = idx_value;
551ebd83
DA		 1595 break;
1596 case RADEON_SE_VTX_FMT:
513bcb46 1597 track->vtx_size = r100_get_vtx_size(idx_value);
551ebd83
DA		 1598 break;
1599 case RADEON_PP_TEX_SIZE_0:
1600 case RADEON_PP_TEX_SIZE_1:
1601 case RADEON_PP_TEX_SIZE_2:
1602 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
513bcb46
DA		 1603 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1604 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
551ebd83
DA		 1605 break;
1606 case RADEON_PP_TEX_PITCH_0:
1607 case RADEON_PP_TEX_PITCH_1:
1608 case RADEON_PP_TEX_PITCH_2:
1609 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
513bcb46 1610 track->textures[i].pitch = idx_value + 32;
551ebd83
DA		 1611 break;
1612 case RADEON_PP_TXFILTER_0:
1613 case RADEON_PP_TXFILTER_1:
1614 case RADEON_PP_TXFILTER_2:
1615 i = (reg - RADEON_PP_TXFILTER_0) / 24;
513bcb46 1616 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
551ebd83 1617 >> RADEON_MAX_MIP_LEVEL_SHIFT);
513bcb46 1618 tmp = (idx_value >> 23) & 0x7;
551ebd83
DA		 1619 if (tmp == 2 || tmp == 6)
1620 track->textures[i].roundup_w = false;
513bcb46 1621 tmp = (idx_value >> 27) & 0x7;
551ebd83
DA		 1622 if (tmp == 2 || tmp == 6)
1623 track->textures[i].roundup_h = false;
1624 break;
1625 case RADEON_PP_TXFORMAT_0:
1626 case RADEON_PP_TXFORMAT_1:
1627 case RADEON_PP_TXFORMAT_2:
1628 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
513bcb46 1629 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
551ebd83
DA		 1630 track->textures[i].use_pitch = 1;
1631 } else {
1632 track->textures[i].use_pitch = 0;
513bcb46
DA		 1633 track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1634 track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
551ebd83 1635 }
513bcb46 1636 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
551ebd83 1637 track->textures[i].tex_coord_type = 2;
513bcb46 1638 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
551ebd83
DA		 1639 case RADEON_TXFORMAT_I8:
1640 case RADEON_TXFORMAT_RGB332:
1641 case RADEON_TXFORMAT_Y8:
1642 track->textures[i].cpp = 1;
f9da52d5 1643 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
551ebd83
DA		 1644 break;
1645 case RADEON_TXFORMAT_AI88:
1646 case RADEON_TXFORMAT_ARGB1555:
1647 case RADEON_TXFORMAT_RGB565:
1648 case RADEON_TXFORMAT_ARGB4444:
1649 case RADEON_TXFORMAT_VYUY422:
1650 case RADEON_TXFORMAT_YVYU422:
551ebd83
DA		 1651 case RADEON_TXFORMAT_SHADOW16:
1652 case RADEON_TXFORMAT_LDUDV655:
1653 case RADEON_TXFORMAT_DUDV88:
1654 track->textures[i].cpp = 2;
f9da52d5 1655 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
771fe6b9 1656 break;
551ebd83
DA		 1657 case RADEON_TXFORMAT_ARGB8888:
1658 case RADEON_TXFORMAT_RGBA8888:
551ebd83
DA		 1659 case RADEON_TXFORMAT_SHADOW32:
1660 case RADEON_TXFORMAT_LDUDUV8888:
1661 track->textures[i].cpp = 4;
f9da52d5 1662 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
551ebd83 1663 break;
d785d78b
DA		 1664 case RADEON_TXFORMAT_DXT1:
1665 track->textures[i].cpp = 1;
1666 track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1667 break;
1668 case RADEON_TXFORMAT_DXT23:
1669 case RADEON_TXFORMAT_DXT45:
1670 track->textures[i].cpp = 1;
1671 track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1672 break;
551ebd83 1673 }
513bcb46
DA		 1674 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1675 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
551ebd83
DA		 1676 break;
1677 case RADEON_PP_CUBIC_FACES_0:
1678 case RADEON_PP_CUBIC_FACES_1:
1679 case RADEON_PP_CUBIC_FACES_2:
513bcb46 1680 tmp = idx_value;
551ebd83
DA		 1681 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1682 for (face = 0; face < 4; face++) {
1683 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1684 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
771fe6b9 1685 }
551ebd83
DA		 1686 break;
1687 default:
1688 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1689 reg, idx);
1690 return -EINVAL;
771fe6b9
JG		 1691 }
1692 return 0;
1693}
1694
068a117c
JG		 1695int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1696 struct radeon_cs_packet *pkt,
4c788679 1697 struct radeon_bo *robj)
068a117c 1698{
068a117c 1699 unsigned idx;
513bcb46 1700 u32 value;
068a117c 1701 idx = pkt->idx + 1;
513bcb46 1702 value = radeon_get_ib_value(p, idx + 2);
4c788679 1703 if ((value + 1) > radeon_bo_size(robj)) {
068a117c
JG		 1704 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1705 "(need %u have %lu) !\n",
513bcb46 1706 value + 1,
4c788679 1707 radeon_bo_size(robj));
068a117c
JG		 1708 return -EINVAL;
1709 }
1710 return 0;
1711}
1712
771fe6b9
JG		 1713static int r100_packet3_check(struct radeon_cs_parser *p,
1714 struct radeon_cs_packet *pkt)
1715{
771fe6b9 1716 struct radeon_cs_reloc *reloc;
551ebd83 1717 struct r100_cs_track *track;
771fe6b9 1718 unsigned idx;
771fe6b9
JG		 1719 volatile uint32_t *ib;
1720 int r;
1721
1722 ib = p->ib->ptr;
771fe6b9 1723 idx = pkt->idx + 1;
551ebd83 1724 track = (struct r100_cs_track *)p->track;
771fe6b9
JG		 1725 switch (pkt->opcode) {
1726 case PACKET3_3D_LOAD_VBPNTR:
513bcb46
DA		 1727 r = r100_packet3_load_vbpntr(p, pkt, idx);
1728 if (r)
1729 return r;
771fe6b9
JG		 1730 break;
1731 case PACKET3_INDX_BUFFER:
1732 r = r100_cs_packet_next_reloc(p, &reloc);
1733 if (r) {
1734 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1735 r100_cs_dump_packet(p, pkt);
1736 return r;
1737 }
513bcb46 1738 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
068a117c
JG		 1739 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1740 if (r) {
1741 return r;
1742 }
771fe6b9
JG		 1743 break;
1744 case 0x23:
771fe6b9
JG		 1745 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1746 r = r100_cs_packet_next_reloc(p, &reloc);
1747 if (r) {
1748 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1749 r100_cs_dump_packet(p, pkt);
1750 return r;
1751 }
513bcb46 1752 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
551ebd83 1753 track->num_arrays = 1;
513bcb46 1754 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
551ebd83
DA		 1755
1756 track->arrays[0].robj = reloc->robj;
1757 track->arrays[0].esize = track->vtx_size;
1758
513bcb46 1759 track->max_indx = radeon_get_ib_value(p, idx+1);
551ebd83 1760
513bcb46 1761 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
551ebd83
DA		 1762 track->immd_dwords = pkt->count - 1;
1763 r = r100_cs_track_check(p->rdev, track);
1764 if (r)
1765 return r;
771fe6b9
JG		 1766 break;
1767 case PACKET3_3D_DRAW_IMMD:
513bcb46 1768 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
551ebd83
DA		 1769 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1770 return -EINVAL;
1771 }
cf57fc7a 1772 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
513bcb46 1773 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
551ebd83
DA		 1774 track->immd_dwords = pkt->count - 1;
1775 r = r100_cs_track_check(p->rdev, track);
1776 if (r)
1777 return r;
1778 break;
771fe6b9
JG		 1779 /* triggers drawing using in-packet vertex data */
1780 case PACKET3_3D_DRAW_IMMD_2:
513bcb46 1781 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
551ebd83
DA		 1782 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1783 return -EINVAL;
1784 }
513bcb46 1785 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
551ebd83
DA		 1786 track->immd_dwords = pkt->count;
1787 r = r100_cs_track_check(p->rdev, track);
1788 if (r)
1789 return r;
1790 break;
771fe6b9
JG		 1791 /* triggers drawing using in-packet vertex data */
1792 case PACKET3_3D_DRAW_VBUF_2:
513bcb46 1793 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
551ebd83
DA		 1794 r = r100_cs_track_check(p->rdev, track);
1795 if (r)
1796 return r;
1797 break;
771fe6b9
JG		 1798 /* triggers drawing of vertex buffers setup elsewhere */
1799 case PACKET3_3D_DRAW_INDX_2:
513bcb46 1800 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
551ebd83
DA		 1801 r = r100_cs_track_check(p->rdev, track);
1802 if (r)
1803 return r;
1804 break;
771fe6b9
JG		 1805 /* triggers drawing using indices to vertex buffer */
1806 case PACKET3_3D_DRAW_VBUF:
513bcb46 1807 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
551ebd83
DA		 1808 r = r100_cs_track_check(p->rdev, track);
1809 if (r)
1810 return r;
1811 break;
771fe6b9
JG		 1812 /* triggers drawing of vertex buffers setup elsewhere */
1813 case PACKET3_3D_DRAW_INDX:
513bcb46 1814 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
551ebd83
DA		 1815 r = r100_cs_track_check(p->rdev, track);
1816 if (r)
1817 return r;
1818 break;
771fe6b9 1819 /* triggers drawing using indices to vertex buffer */
ab9e1f59
DA		 1820 case PACKET3_3D_CLEAR_HIZ:
1821 case PACKET3_3D_CLEAR_ZMASK:
1822 if (p->rdev->hyperz_filp != p->filp)
1823 return -EINVAL;
1824 break;
771fe6b9
JG		 1825 case PACKET3_NOP:
1826 break;
1827 default:
1828 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1829 return -EINVAL;
1830 }
1831 return 0;
1832}
1833
1834int r100_cs_parse(struct radeon_cs_parser *p)
1835{
1836 struct radeon_cs_packet pkt;
9f022ddf 1837 struct r100_cs_track *track;
771fe6b9
JG		 1838 int r;
1839
9f022ddf
JG		 1840 track = kzalloc(sizeof(*track), GFP_KERNEL);
1841 r100_cs_track_clear(p->rdev, track);
1842 p->track = track;
771fe6b9
JG		 1843 do {
1844 r = r100_cs_packet_parse(p, &pkt, p->idx);
1845 if (r) {
1846 return r;
1847 }
1848 p->idx += pkt.count + 2;
1849 switch (pkt.type) {
068a117c 1850 case PACKET_TYPE0:
551ebd83
DA		 1851 if (p->rdev->family >= CHIP_R200)
1852 r = r100_cs_parse_packet0(p, &pkt,
1853 p->rdev->config.r100.reg_safe_bm,
1854 p->rdev->config.r100.reg_safe_bm_size,
1855 &r200_packet0_check);
1856 else
1857 r = r100_cs_parse_packet0(p, &pkt,
1858 p->rdev->config.r100.reg_safe_bm,
1859 p->rdev->config.r100.reg_safe_bm_size,
1860 &r100_packet0_check);
068a117c
JG		 1861 break;
1862 case PACKET_TYPE2:
1863 break;
1864 case PACKET_TYPE3:
1865 r = r100_packet3_check(p, &pkt);
1866 break;
1867 default:
1868 DRM_ERROR("Unknown packet type %d !\n",
1869 pkt.type);
1870 return -EINVAL;
771fe6b9
JG		 1871 }
1872 if (r) {
1873 return r;
1874 }
1875 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1876 return 0;
1877}
1878
1879
1880/*
1881 * Global GPU functions
1882 */
1883void r100_errata(struct radeon_device *rdev)
1884{
1885 rdev->pll_errata = 0;
1886
1887 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
1888 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
1889 }
1890
1891 if (rdev->family == CHIP_RV100 ||
1892 rdev->family == CHIP_RS100 ||
1893 rdev->family == CHIP_RS200) {
1894 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
1895 }
1896}
1897
1898/* Wait for vertical sync on primary CRTC */
1899void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
1900{
1901 uint32_t crtc_gen_cntl, tmp;
1902 int i;
1903
1904 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
1905 if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
1906 !(crtc_gen_cntl & RADEON_CRTC_EN)) {
1907 return;
1908 }
1909 /* Clear the CRTC_VBLANK_SAVE bit */
1910 WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
1911 for (i = 0; i < rdev->usec_timeout; i++) {
1912 tmp = RREG32(RADEON_CRTC_STATUS);
1913 if (tmp & RADEON_CRTC_VBLANK_SAVE) {
1914 return;
1915 }
1916 DRM_UDELAY(1);
1917 }
1918}
1919
1920/* Wait for vertical sync on secondary CRTC */
1921void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
1922{
1923 uint32_t crtc2_gen_cntl, tmp;
1924 int i;
1925
1926 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1927 if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
1928 !(crtc2_gen_cntl & RADEON_CRTC2_EN))
1929 return;
1930
1931 /* Clear the CRTC_VBLANK_SAVE bit */
1932 WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
1933 for (i = 0; i < rdev->usec_timeout; i++) {
1934 tmp = RREG32(RADEON_CRTC2_STATUS);
1935 if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
1936 return;
1937 }
1938 DRM_UDELAY(1);
1939 }
1940}
1941
1942int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
1943{
1944 unsigned i;
1945 uint32_t tmp;
1946
1947 for (i = 0; i < rdev->usec_timeout; i++) {
1948 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
1949 if (tmp >= n) {
1950 return 0;
1951 }
1952 DRM_UDELAY(1);
1953 }
1954 return -1;
1955}
1956
1957int r100_gui_wait_for_idle(struct radeon_device *rdev)
1958{
1959 unsigned i;
1960 uint32_t tmp;
1961
1962 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
1963 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
1964 " Bad things might happen.\n");
1965 }
1966 for (i = 0; i < rdev->usec_timeout; i++) {
1967 tmp = RREG32(RADEON_RBBM_STATUS);
4612dc97 1968 if (!(tmp & RADEON_RBBM_ACTIVE)) {
771fe6b9
JG		 1969 return 0;
1970 }
1971 DRM_UDELAY(1);
1972 }
1973 return -1;
1974}
1975
1976int r100_mc_wait_for_idle(struct radeon_device *rdev)
1977{
1978 unsigned i;
1979 uint32_t tmp;
1980
1981 for (i = 0; i < rdev->usec_timeout; i++) {
1982 /* read MC_STATUS */
4612dc97
AD		 1983 tmp = RREG32(RADEON_MC_STATUS);
1984 if (tmp & RADEON_MC_IDLE) {
771fe6b9
JG		 1985 return 0;
1986 }
1987 DRM_UDELAY(1);
1988 }
1989 return -1;
1990}
1991
225758d8 1992void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, struct radeon_cp *cp)
771fe6b9 1993{
225758d8
JG		 1994 lockup->last_cp_rptr = cp->rptr;
1995 lockup->last_jiffies = jiffies;
1996}
1997
1998/**
1999 * r100_gpu_cp_is_lockup() - check if CP is lockup by recording information
2000 * @rdev: radeon device structure
2001 * @lockup: r100_gpu_lockup structure holding CP lockup tracking informations
2002 * @cp: radeon_cp structure holding CP information
2003 *
2004 * We don't need to initialize the lockup tracking information as we will either
2005 * have CP rptr to a different value of jiffies wrap around which will force
2006 * initialization of the lockup tracking informations.
2007 *
2008 * A possible false positivie is if we get call after while and last_cp_rptr ==
2009 * the current CP rptr, even if it's unlikely it might happen. To avoid this
2010 * if the elapsed time since last call is bigger than 2 second than we return
2011 * false and update the tracking information. Due to this the caller must call
2012 * r100_gpu_cp_is_lockup several time in less than 2sec for lockup to be reported
2013 * the fencing code should be cautious about that.
2014 *
2015 * Caller should write to the ring to force CP to do something so we don't get
2016 * false positive when CP is just gived nothing to do.
2017 *
2018 **/
2019bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, struct r100_gpu_lockup *lockup, struct radeon_cp *cp)
2020{
2021 unsigned long cjiffies, elapsed;
2022
2023 cjiffies = jiffies;
2024 if (!time_after(cjiffies, lockup->last_jiffies)) {
2025 /* likely a wrap around */
2026 lockup->last_cp_rptr = cp->rptr;
2027 lockup->last_jiffies = jiffies;
2028 return false;
2029 }
2030 if (cp->rptr != lockup->last_cp_rptr) {
2031 /* CP is still working no lockup */
2032 lockup->last_cp_rptr = cp->rptr;
2033 lockup->last_jiffies = jiffies;
2034 return false;
2035 }
2036 elapsed = jiffies_to_msecs(cjiffies - lockup->last_jiffies);
ec00efb7 2037 if (elapsed >= 10000) {
225758d8
JG		 2038 dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed);
2039 return true;
2040 }
2041 /* give a chance to the GPU ... */
2042 return false;
771fe6b9
JG		 2043}
2044
225758d8 2045bool r100_gpu_is_lockup(struct radeon_device *rdev)
771fe6b9 2046{
225758d8
JG		 2047 u32 rbbm_status;
2048 int r;
771fe6b9 2049
225758d8
JG		 2050 rbbm_status = RREG32(R_000E40_RBBM_STATUS);
2051 if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
2052 r100_gpu_lockup_update(&rdev->config.r100.lockup, &rdev->cp);
2053 return false;
2054 }
2055 /* force CP activities */
2056 r = radeon_ring_lock(rdev, 2);
2057 if (!r) {
2058 /* PACKET2 NOP */
2059 radeon_ring_write(rdev, 0x80000000);
2060 radeon_ring_write(rdev, 0x80000000);
2061 radeon_ring_unlock_commit(rdev);
2062 }
2063 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
2064 return r100_gpu_cp_is_lockup(rdev, &rdev->config.r100.lockup, &rdev->cp);
771fe6b9
JG		 2065}
2066
90aca4d2 2067void r100_bm_disable(struct radeon_device *rdev)
771fe6b9 2068{
90aca4d2 2069 u32 tmp;
771fe6b9 2070
90aca4d2
JG		 2071 /* disable bus mastering */
2072 tmp = RREG32(R_000030_BUS_CNTL);
2073 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044);
2074 mdelay(1);
2075 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042);
2076 mdelay(1);
2077 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);
2078 tmp = RREG32(RADEON_BUS_CNTL);
2079 mdelay(1);
2080 pci_read_config_word(rdev->pdev, 0x4, (u16*)&tmp);
2081 pci_write_config_word(rdev->pdev, 0x4, tmp & 0xFFFB);
771fe6b9 2082 mdelay(1);
771fe6b9
JG		 2083}
2084
a2d07b74 2085int r100_asic_reset(struct radeon_device *rdev)
771fe6b9 2086{
90aca4d2
JG		 2087 struct r100_mc_save save;
2088 u32 status, tmp;
25b2ec5b 2089 int ret = 0;
771fe6b9 2090
90aca4d2
JG		 2091 status = RREG32(R_000E40_RBBM_STATUS);
2092 if (!G_000E40_GUI_ACTIVE(status)) {
2093 return 0;
771fe6b9 2094 }
25b2ec5b 2095 r100_mc_stop(rdev, &save);
90aca4d2
JG		 2096 status = RREG32(R_000E40_RBBM_STATUS);
2097 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2098 /* stop CP */
2099 WREG32(RADEON_CP_CSQ_CNTL, 0);
2100 tmp = RREG32(RADEON_CP_RB_CNTL);
2101 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
2102 WREG32(RADEON_CP_RB_RPTR_WR, 0);
2103 WREG32(RADEON_CP_RB_WPTR, 0);
2104 WREG32(RADEON_CP_RB_CNTL, tmp);
2105 /* save PCI state */
2106 pci_save_state(rdev->pdev);
2107 /* disable bus mastering */
2108 r100_bm_disable(rdev);
2109 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) |
2110 S_0000F0_SOFT_RESET_RE(1) |
2111 S_0000F0_SOFT_RESET_PP(1) |
2112 S_0000F0_SOFT_RESET_RB(1));
2113 RREG32(R_0000F0_RBBM_SOFT_RESET);
2114 mdelay(500);
2115 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2116 mdelay(1);
2117 status = RREG32(R_000E40_RBBM_STATUS);
2118 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
771fe6b9 2119 /* reset CP */
90aca4d2
JG		 2120 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
2121 RREG32(R_0000F0_RBBM_SOFT_RESET);
2122 mdelay(500);
2123 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2124 mdelay(1);
2125 status = RREG32(R_000E40_RBBM_STATUS);
2126 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2127 /* restore PCI & busmastering */
2128 pci_restore_state(rdev->pdev);
2129 r100_enable_bm(rdev);
771fe6b9 2130 /* Check if GPU is idle */
90aca4d2
JG		 2131 if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) ||
2132 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) {
2133 dev_err(rdev->dev, "failed to reset GPU\n");
2134 rdev->gpu_lockup = true;
25b2ec5b
AD		 2135 ret = -1;
2136 } else
2137 dev_info(rdev->dev, "GPU reset succeed\n");
90aca4d2 2138 r100_mc_resume(rdev, &save);
25b2ec5b 2139 return ret;
771fe6b9
JG		 2140}
2141
92cde00c
AD		 2142void r100_set_common_regs(struct radeon_device *rdev)
2143{
2739d49c
AD		 2144 struct drm_device *dev = rdev->ddev;
2145 bool force_dac2 = false;
d668046c 2146 u32 tmp;
2739d49c 2147
92cde00c
AD		 2148 /* set these so they don't interfere with anything */
2149 WREG32(RADEON_OV0_SCALE_CNTL, 0);
2150 WREG32(RADEON_SUBPIC_CNTL, 0);
2151 WREG32(RADEON_VIPH_CONTROL, 0);
2152 WREG32(RADEON_I2C_CNTL_1, 0);
2153 WREG32(RADEON_DVI_I2C_CNTL_1, 0);
2154 WREG32(RADEON_CAP0_TRIG_CNTL, 0);
2155 WREG32(RADEON_CAP1_TRIG_CNTL, 0);
2739d49c
AD		 2156
2157 /* always set up dac2 on rn50 and some rv100 as lots
2158 * of servers seem to wire it up to a VGA port but
2159 * don't report it in the bios connector
2160 * table.
2161 */
2162 switch (dev->pdev->device) {
2163 /* RN50 */
2164 case 0x515e:
2165 case 0x5969:
2166 force_dac2 = true;
2167 break;
2168 /* RV100*/
2169 case 0x5159:
2170 case 0x515a:
2171 /* DELL triple head servers */
2172 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
2173 ((dev->pdev->subsystem_device == 0x016c) ||
2174 (dev->pdev->subsystem_device == 0x016d) ||
2175 (dev->pdev->subsystem_device == 0x016e) ||
2176 (dev->pdev->subsystem_device == 0x016f) ||
2177 (dev->pdev->subsystem_device == 0x0170) ||
2178 (dev->pdev->subsystem_device == 0x017d) ||
2179 (dev->pdev->subsystem_device == 0x017e) ||
2180 (dev->pdev->subsystem_device == 0x0183) ||
2181 (dev->pdev->subsystem_device == 0x018a) ||
2182 (dev->pdev->subsystem_device == 0x019a)))
2183 force_dac2 = true;
2184 break;
2185 }
2186
2187 if (force_dac2) {
2188 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
2189 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
2190 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
2191
2192 /* For CRT on DAC2, don't turn it on if BIOS didn't
2193 enable it, even it's detected.
2194 */
2195
2196 /* force it to crtc0 */
2197 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
2198 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
2199 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
2200
2201 /* set up the TV DAC */
2202 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
2203 RADEON_TV_DAC_STD_MASK |
2204 RADEON_TV_DAC_RDACPD |
2205 RADEON_TV_DAC_GDACPD |
2206 RADEON_TV_DAC_BDACPD |
2207 RADEON_TV_DAC_BGADJ_MASK |
2208 RADEON_TV_DAC_DACADJ_MASK);
2209 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
2210 RADEON_TV_DAC_NHOLD |
2211 RADEON_TV_DAC_STD_PS2 |
2212 (0x58 << 16));
2213
2214 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
2215 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
2216 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
2217 }
d668046c
DA		 2218
2219 /* switch PM block to ACPI mode */
2220 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
2221 tmp &= ~RADEON_PM_MODE_SEL;
2222 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
2223
92cde00c 2224}
771fe6b9
JG		 2225
2226/*
2227 * VRAM info
2228 */
2229static void r100_vram_get_type(struct radeon_device *rdev)
2230{
2231 uint32_t tmp;
2232
2233 rdev->mc.vram_is_ddr = false;
2234 if (rdev->flags & RADEON_IS_IGP)
2235 rdev->mc.vram_is_ddr = true;
2236 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
2237 rdev->mc.vram_is_ddr = true;
2238 if ((rdev->family == CHIP_RV100) ||
2239 (rdev->family == CHIP_RS100) ||
2240 (rdev->family == CHIP_RS200)) {
2241 tmp = RREG32(RADEON_MEM_CNTL);
2242 if (tmp & RV100_HALF_MODE) {
2243 rdev->mc.vram_width = 32;
2244 } else {
2245 rdev->mc.vram_width = 64;
2246 }
2247 if (rdev->flags & RADEON_SINGLE_CRTC) {
2248 rdev->mc.vram_width /= 4;
2249 rdev->mc.vram_is_ddr = true;
2250 }
2251 } else if (rdev->family <= CHIP_RV280) {
2252 tmp = RREG32(RADEON_MEM_CNTL);
2253 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
2254 rdev->mc.vram_width = 128;
2255 } else {
2256 rdev->mc.vram_width = 64;
2257 }
2258 } else {
2259 /* newer IGPs */
2260 rdev->mc.vram_width = 128;
2261 }
2262}
2263
2a0f8918 2264static u32 r100_get_accessible_vram(struct radeon_device *rdev)
771fe6b9 2265{
2a0f8918
DA		 2266 u32 aper_size;
2267 u8 byte;
2268
2269 aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2270
2271 /* Set HDP_APER_CNTL only on cards that are known not to be broken,
2272 * that is has the 2nd generation multifunction PCI interface
2273 */
2274 if (rdev->family == CHIP_RV280 ||
2275 rdev->family >= CHIP_RV350) {
2276 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
2277 ~RADEON_HDP_APER_CNTL);
2278 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
2279 return aper_size * 2;
2280 }
2281
2282 /* Older cards have all sorts of funny issues to deal with. First
2283 * check if it's a multifunction card by reading the PCI config
2284 * header type... Limit those to one aperture size
2285 */
2286 pci_read_config_byte(rdev->pdev, 0xe, &byte);
2287 if (byte & 0x80) {
2288 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
2289 DRM_INFO("Limiting VRAM to one aperture\n");
2290 return aper_size;
2291 }
2292
2293 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
2294 * have set it up. We don't write this as it's broken on some ASICs but
2295 * we expect the BIOS to have done the right thing (might be too optimistic...)
2296 */
2297 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
2298 return aper_size * 2;
2299 return aper_size;
2300}
2301
2302void r100_vram_init_sizes(struct radeon_device *rdev)
2303{
2304 u64 config_aper_size;
2a0f8918 2305
d594e46a 2306 /* work out accessible VRAM */
01d73a69
JC		 2307 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2308 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
51e5fcd3
JG		 2309 rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
2310 /* FIXME we don't use the second aperture yet when we could use it */
2311 if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
2312 rdev->mc.visible_vram_size = rdev->mc.aper_size;
c919b371 2313 rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
2a0f8918 2314 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
771fe6b9
JG		 2315 if (rdev->flags & RADEON_IS_IGP) {
2316 uint32_t tom;
2317 /* read NB_TOM to get the amount of ram stolen for the GPU */
2318 tom = RREG32(RADEON_NB_TOM);
7a50f01a 2319 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
7a50f01a
DA		 2320 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2321 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
771fe6b9 2322 } else {
7a50f01a 2323 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
771fe6b9
JG		 2324 /* Some production boards of m6 will report 0
2325 * if it's 8 MB
2326 */
7a50f01a
DA		 2327 if (rdev->mc.real_vram_size == 0) {
2328 rdev->mc.real_vram_size = 8192 * 1024;
2329 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
771fe6b9 2330 }
d594e46a
JG		 2331 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
2332 * Novell bug 204882 + along with lots of ubuntu ones
2333 */
b7d8cce5
AD		 2334 if (rdev->mc.aper_size > config_aper_size)
2335 config_aper_size = rdev->mc.aper_size;
2336
7a50f01a
DA		 2337 if (config_aper_size > rdev->mc.real_vram_size)
2338 rdev->mc.mc_vram_size = config_aper_size;
2339 else
2340 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
771fe6b9 2341 }
2a0f8918
DA		 2342}
2343
28d52043
DA		 2344void r100_vga_set_state(struct radeon_device *rdev, bool state)
2345{
2346 uint32_t temp;
2347
2348 temp = RREG32(RADEON_CONFIG_CNTL);
2349 if (state == false) {
d75ee3be
AD		 2350 temp &= ~RADEON_CFG_VGA_RAM_EN;
2351 temp |= RADEON_CFG_VGA_IO_DIS;
28d52043 2352 } else {
d75ee3be 2353 temp &= ~RADEON_CFG_VGA_IO_DIS;
28d52043
DA		 2354 }
2355 WREG32(RADEON_CONFIG_CNTL, temp);
2356}
2357
d594e46a 2358void r100_mc_init(struct radeon_device *rdev)
2a0f8918 2359{
d594e46a 2360 u64 base;
2a0f8918 2361
d594e46a 2362 r100_vram_get_type(rdev);
2a0f8918 2363 r100_vram_init_sizes(rdev);
d594e46a
JG		 2364 base = rdev->mc.aper_base;
2365 if (rdev->flags & RADEON_IS_IGP)
2366 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2367 radeon_vram_location(rdev, &rdev->mc, base);
8d369bb1 2368 rdev->mc.gtt_base_align = 0;
d594e46a
JG		 2369 if (!(rdev->flags & RADEON_IS_AGP))
2370 radeon_gtt_location(rdev, &rdev->mc);
f47299c5 2371 radeon_update_bandwidth_info(rdev);
771fe6b9
JG		 2372}
2373
2374
2375/*
2376 * Indirect registers accessor
2377 */
2378void r100_pll_errata_after_index(struct radeon_device *rdev)
2379{
4ce9198e
AD		 2380 if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) {
2381 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2382 (void)RREG32(RADEON_CRTC_GEN_CNTL);
771fe6b9 2383 }
771fe6b9
JG		 2384}
2385
2386static void r100_pll_errata_after_data(struct radeon_device *rdev)
2387{
2388 /* This workarounds is necessary on RV100, RS100 and RS200 chips
2389 * or the chip could hang on a subsequent access
2390 */
2391 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2392 udelay(5000);
2393 }
2394
2395 /* This function is required to workaround a hardware bug in some (all?)
2396 * revisions of the R300. This workaround should be called after every
2397 * CLOCK_CNTL_INDEX register access. If not, register reads afterward
2398 * may not be correct.
2399 */
2400 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2401 uint32_t save, tmp;
2402
2403 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
2404 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2405 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
2406 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
2407 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
2408 }
2409}
2410
2411uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2412{
2413 uint32_t data;
2414
2415 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
2416 r100_pll_errata_after_index(rdev);
2417 data = RREG32(RADEON_CLOCK_CNTL_DATA);
2418 r100_pll_errata_after_data(rdev);
2419 return data;
2420}
2421
2422void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2423{
2424 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2425 r100_pll_errata_after_index(rdev);
2426 WREG32(RADEON_CLOCK_CNTL_DATA, v);
2427 r100_pll_errata_after_data(rdev);
2428}
2429
d4550907 2430void r100_set_safe_registers(struct radeon_device *rdev)
068a117c 2431{
551ebd83
DA		 2432 if (ASIC_IS_RN50(rdev)) {
2433 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2434 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2435 } else if (rdev->family < CHIP_R200) {
2436 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2437 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2438 } else {
d4550907 2439 r200_set_safe_registers(rdev);
551ebd83 2440 }
068a117c
JG		 2441}
2442
771fe6b9
JG		 2443/*
2444 * Debugfs info
2445 */
2446#if defined(CONFIG_DEBUG_FS)
2447static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
2448{
2449 struct drm_info_node *node = (struct drm_info_node *) m->private;
2450 struct drm_device *dev = node->minor->dev;
2451 struct radeon_device *rdev = dev->dev_private;
2452 uint32_t reg, value;
2453 unsigned i;
2454
2455 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2456 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2457 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2458 for (i = 0; i < 64; i++) {
2459 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2460 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2461 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2462 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2463 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2464 }
2465 return 0;
2466}
2467
2468static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2469{
2470 struct drm_info_node *node = (struct drm_info_node *) m->private;
2471 struct drm_device *dev = node->minor->dev;
2472 struct radeon_device *rdev = dev->dev_private;
2473 uint32_t rdp, wdp;
2474 unsigned count, i, j;
2475
2476 radeon_ring_free_size(rdev);
2477 rdp = RREG32(RADEON_CP_RB_RPTR);
2478 wdp = RREG32(RADEON_CP_RB_WPTR);
2479 count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
2480 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2481 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2482 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2483 seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
2484 seq_printf(m, "%u dwords in ring\n", count);
2485 for (j = 0; j <= count; j++) {
2486 i = (rdp + j) & rdev->cp.ptr_mask;
2487 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
2488 }
2489 return 0;
2490}
2491
2492
2493static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2494{
2495 struct drm_info_node *node = (struct drm_info_node *) m->private;
2496 struct drm_device *dev = node->minor->dev;
2497 struct radeon_device *rdev = dev->dev_private;
2498 uint32_t csq_stat, csq2_stat, tmp;
2499 unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2500 unsigned i;
2501
2502 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2503 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2504 csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2505 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2506 r_rptr = (csq_stat >> 0) & 0x3ff;
2507 r_wptr = (csq_stat >> 10) & 0x3ff;
2508 ib1_rptr = (csq_stat >> 20) & 0x3ff;
2509 ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2510 ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2511 ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2512 seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2513 seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2514 seq_printf(m, "Ring rptr %u\n", r_rptr);
2515 seq_printf(m, "Ring wptr %u\n", r_wptr);
2516 seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
2517 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2518 seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
2519 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
2520 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
2521 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
2522 seq_printf(m, "Ring fifo:\n");
2523 for (i = 0; i < 256; i++) {
2524 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2525 tmp = RREG32(RADEON_CP_CSQ_DATA);
2526 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
2527 }
2528 seq_printf(m, "Indirect1 fifo:\n");
2529 for (i = 256; i <= 512; i++) {
2530 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2531 tmp = RREG32(RADEON_CP_CSQ_DATA);
2532 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
2533 }
2534 seq_printf(m, "Indirect2 fifo:\n");
2535 for (i = 640; i < ib1_wptr; i++) {
2536 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2537 tmp = RREG32(RADEON_CP_CSQ_DATA);
2538 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
2539 }
2540 return 0;
2541}
2542
2543static int r100_debugfs_mc_info(struct seq_file *m, void *data)
2544{
2545 struct drm_info_node *node = (struct drm_info_node *) m->private;
2546 struct drm_device *dev = node->minor->dev;
2547 struct radeon_device *rdev = dev->dev_private;
2548 uint32_t tmp;
2549
2550 tmp = RREG32(RADEON_CONFIG_MEMSIZE);
2551 seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
2552 tmp = RREG32(RADEON_MC_FB_LOCATION);
2553 seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
2554 tmp = RREG32(RADEON_BUS_CNTL);
2555 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
2556 tmp = RREG32(RADEON_MC_AGP_LOCATION);
2557 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
2558 tmp = RREG32(RADEON_AGP_BASE);
2559 seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
2560 tmp = RREG32(RADEON_HOST_PATH_CNTL);
2561 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
2562 tmp = RREG32(0x01D0);
2563 seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
2564 tmp = RREG32(RADEON_AIC_LO_ADDR);
2565 seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
2566 tmp = RREG32(RADEON_AIC_HI_ADDR);
2567 seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
2568 tmp = RREG32(0x01E4);
2569 seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
2570 return 0;
2571}
2572
2573static struct drm_info_list r100_debugfs_rbbm_list[] = {
2574 {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
2575};
2576
2577static struct drm_info_list r100_debugfs_cp_list[] = {
2578 {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
2579 {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
2580};
2581
2582static struct drm_info_list r100_debugfs_mc_info_list[] = {
2583 {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
2584};
2585#endif
2586
2587int r100_debugfs_rbbm_init(struct radeon_device *rdev)
2588{
2589#if defined(CONFIG_DEBUG_FS)
2590 return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
2591#else
2592 return 0;
2593#endif
2594}
2595
2596int r100_debugfs_cp_init(struct radeon_device *rdev)
2597{
2598#if defined(CONFIG_DEBUG_FS)
2599 return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
2600#else
2601 return 0;
2602#endif
2603}
2604
2605int r100_debugfs_mc_info_init(struct radeon_device *rdev)
2606{
2607#if defined(CONFIG_DEBUG_FS)
2608 return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
2609#else
2610 return 0;
2611#endif
2612}
e024e110
DA		 2613
2614int r100_set_surface_reg(struct radeon_device *rdev, int reg,
2615 uint32_t tiling_flags, uint32_t pitch,
2616 uint32_t offset, uint32_t obj_size)
2617{
2618 int surf_index = reg * 16;
2619 int flags = 0;
2620
e024e110
DA		 2621 if (rdev->family <= CHIP_RS200) {
2622 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2623 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2624 flags |= RADEON_SURF_TILE_COLOR_BOTH;
2625 if (tiling_flags & RADEON_TILING_MACRO)
2626 flags |= RADEON_SURF_TILE_COLOR_MACRO;
2627 } else if (rdev->family <= CHIP_RV280) {
2628 if (tiling_flags & (RADEON_TILING_MACRO))
2629 flags |= R200_SURF_TILE_COLOR_MACRO;
2630 if (tiling_flags & RADEON_TILING_MICRO)
2631 flags |= R200_SURF_TILE_COLOR_MICRO;
2632 } else {
2633 if (tiling_flags & RADEON_TILING_MACRO)
2634 flags |= R300_SURF_TILE_MACRO;
2635 if (tiling_flags & RADEON_TILING_MICRO)
2636 flags |= R300_SURF_TILE_MICRO;
2637 }
2638
c88f9f0c
MD		 2639 if (tiling_flags & RADEON_TILING_SWAP_16BIT)
2640 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
2641 if (tiling_flags & RADEON_TILING_SWAP_32BIT)
2642 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
2643
f5c5f040
DA		 2644 /* when we aren't tiling the pitch seems to needs to be furtherdivided down. - tested on power5 + rn50 server */
2645 if (tiling_flags & (RADEON_TILING_SWAP_16BIT | RADEON_TILING_SWAP_32BIT)) {
2646 if (!(tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO)))
2647 if (ASIC_IS_RN50(rdev))
2648 pitch /= 16;
2649 }
2650
2651 /* r100/r200 divide by 16 */
2652 if (rdev->family < CHIP_R300)
2653 flags |= pitch / 16;
2654 else
2655 flags |= pitch / 8;
2656
2657
d9fdaafb 2658 DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
e024e110
DA		 2659 WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
2660 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
2661 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
2662 return 0;
2663}
2664
2665void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
2666{
2667 int surf_index = reg * 16;
2668 WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
2669}
c93bb85b
JG		 2670
2671void r100_bandwidth_update(struct radeon_device *rdev)
2672{
2673 fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
2674 fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
2675 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
2676 uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
2677 fixed20_12 memtcas_ff[8] = {
68adac5e
BS		 2678 dfixed_init(1),
2679 dfixed_init(2),
2680 dfixed_init(3),
2681 dfixed_init(0),
2682 dfixed_init_half(1),
2683 dfixed_init_half(2),
2684 dfixed_init(0),
c93bb85b
JG		 2685 };
2686 fixed20_12 memtcas_rs480_ff[8] = {
68adac5e
BS		 2687 dfixed_init(0),
2688 dfixed_init(1),
2689 dfixed_init(2),
2690 dfixed_init(3),
2691 dfixed_init(0),
2692 dfixed_init_half(1),
2693 dfixed_init_half(2),
2694 dfixed_init_half(3),
c93bb85b
JG		 2695 };
2696 fixed20_12 memtcas2_ff[8] = {
68adac5e
BS		 2697 dfixed_init(0),
2698 dfixed_init(1),
2699 dfixed_init(2),
2700 dfixed_init(3),
2701 dfixed_init(4),
2702 dfixed_init(5),
2703 dfixed_init(6),
2704 dfixed_init(7),
c93bb85b
JG		 2705 };
2706 fixed20_12 memtrbs[8] = {
68adac5e
BS		 2707 dfixed_init(1),
2708 dfixed_init_half(1),
2709 dfixed_init(2),
2710 dfixed_init_half(2),
2711 dfixed_init(3),
2712 dfixed_init_half(3),
2713 dfixed_init(4),
2714 dfixed_init_half(4)
c93bb85b
JG		 2715 };
2716 fixed20_12 memtrbs_r4xx[8] = {
68adac5e
BS		 2717 dfixed_init(4),
2718 dfixed_init(5),
2719 dfixed_init(6),
2720 dfixed_init(7),
2721 dfixed_init(8),
2722 dfixed_init(9),
2723 dfixed_init(10),
2724 dfixed_init(11)
c93bb85b
JG		 2725 };
2726 fixed20_12 min_mem_eff;
2727 fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
2728 fixed20_12 cur_latency_mclk, cur_latency_sclk;
2729 fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
2730 disp_drain_rate2, read_return_rate;
2731 fixed20_12 time_disp1_drop_priority;
2732 int c;
2733 int cur_size = 16; /* in octawords */
2734 int critical_point = 0, critical_point2;
2735/* uint32_t read_return_rate, time_disp1_drop_priority; */
2736 int stop_req, max_stop_req;
2737 struct drm_display_mode *mode1 = NULL;
2738 struct drm_display_mode *mode2 = NULL;
2739 uint32_t pixel_bytes1 = 0;
2740 uint32_t pixel_bytes2 = 0;
2741
f46c0120
AD		 2742 radeon_update_display_priority(rdev);
2743
c93bb85b
JG		 2744 if (rdev->mode_info.crtcs[0]->base.enabled) {
2745 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
2746 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
2747 }
dfee5614
DA		 2748 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
2749 if (rdev->mode_info.crtcs[1]->base.enabled) {
2750 mode2 = &rdev->mode_info.crtcs[1]->base.mode;
2751 pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
2752 }
c93bb85b
JG		 2753 }
2754
68adac5e 2755 min_mem_eff.full = dfixed_const_8(0);
c93bb85b
JG		 2756 /* get modes */
2757 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
2758 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
2759 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
2760 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
2761 /* check crtc enables */
2762 if (mode2)
2763 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
2764 if (mode1)
2765 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
2766 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
2767 }
2768
2769 /*
2770 * determine is there is enough bw for current mode
2771 */
f47299c5
AD		 2772 sclk_ff = rdev->pm.sclk;
2773 mclk_ff = rdev->pm.mclk;
c93bb85b
JG		 2774
2775 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
68adac5e
BS		 2776 temp_ff.full = dfixed_const(temp);
2777 mem_bw.full = dfixed_mul(mclk_ff, temp_ff);
c93bb85b
JG		 2778
2779 pix_clk.full = 0;
2780 pix_clk2.full = 0;
2781 peak_disp_bw.full = 0;
2782 if (mode1) {
68adac5e
BS		 2783 temp_ff.full = dfixed_const(1000);
2784 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */
2785 pix_clk.full = dfixed_div(pix_clk, temp_ff);
2786 temp_ff.full = dfixed_const(pixel_bytes1);
2787 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff);
c93bb85b
JG		 2788 }
2789 if (mode2) {
68adac5e
BS		 2790 temp_ff.full = dfixed_const(1000);
2791 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */
2792 pix_clk2.full = dfixed_div(pix_clk2, temp_ff);
2793 temp_ff.full = dfixed_const(pixel_bytes2);
2794 peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff);
c93bb85b
JG		 2795 }
2796
68adac5e 2797 mem_bw.full = dfixed_mul(mem_bw, min_mem_eff);
c93bb85b
JG		 2798 if (peak_disp_bw.full >= mem_bw.full) {
2799 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
2800 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
2801 }
2802
2803 /* Get values from the EXT_MEM_CNTL register...converting its contents. */
2804 temp = RREG32(RADEON_MEM_TIMING_CNTL);
2805 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
2806 mem_trcd = ((temp >> 2) & 0x3) + 1;
2807 mem_trp = ((temp & 0x3)) + 1;
2808 mem_tras = ((temp & 0x70) >> 4) + 1;
2809 } else if (rdev->family == CHIP_R300 ||
2810 rdev->family == CHIP_R350) { /* r300, r350 */
2811 mem_trcd = (temp & 0x7) + 1;
2812 mem_trp = ((temp >> 8) & 0x7) + 1;
2813 mem_tras = ((temp >> 11) & 0xf) + 4;
2814 } else if (rdev->family == CHIP_RV350 ||
2815 rdev->family <= CHIP_RV380) {
2816 /* rv3x0 */
2817 mem_trcd = (temp & 0x7) + 3;
2818 mem_trp = ((temp >> 8) & 0x7) + 3;
2819 mem_tras = ((temp >> 11) & 0xf) + 6;
2820 } else if (rdev->family == CHIP_R420 ||
2821 rdev->family == CHIP_R423 ||
2822 rdev->family == CHIP_RV410) {
2823 /* r4xx */
2824 mem_trcd = (temp & 0xf) + 3;
2825 if (mem_trcd > 15)
2826 mem_trcd = 15;
2827 mem_trp = ((temp >> 8) & 0xf) + 3;
2828 if (mem_trp > 15)
2829 mem_trp = 15;
2830 mem_tras = ((temp >> 12) & 0x1f) + 6;
2831 if (mem_tras > 31)
2832 mem_tras = 31;
2833 } else { /* RV200, R200 */
2834 mem_trcd = (temp & 0x7) + 1;
2835 mem_trp = ((temp >> 8) & 0x7) + 1;
2836 mem_tras = ((temp >> 12) & 0xf) + 4;
2837 }
2838 /* convert to FF */
68adac5e
BS		 2839 trcd_ff.full = dfixed_const(mem_trcd);
2840 trp_ff.full = dfixed_const(mem_trp);
2841 tras_ff.full = dfixed_const(mem_tras);
c93bb85b
JG		 2842
2843 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
2844 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2845 data = (temp & (7 << 20)) >> 20;
2846 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
2847 if (rdev->family == CHIP_RS480) /* don't think rs400 */
2848 tcas_ff = memtcas_rs480_ff[data];
2849 else
2850 tcas_ff = memtcas_ff[data];
2851 } else
2852 tcas_ff = memtcas2_ff[data];
2853
2854 if (rdev->family == CHIP_RS400 ||
2855 rdev->family == CHIP_RS480) {
2856 /* extra cas latency stored in bits 23-25 0-4 clocks */
2857 data = (temp >> 23) & 0x7;
2858 if (data < 5)
68adac5e 2859 tcas_ff.full += dfixed_const(data);
c93bb85b
JG		 2860 }
2861
2862 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2863 /* on the R300, Tcas is included in Trbs.
2864 */
2865 temp = RREG32(RADEON_MEM_CNTL);
2866 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
2867 if (data == 1) {
2868 if (R300_MEM_USE_CD_CH_ONLY & temp) {
2869 temp = RREG32(R300_MC_IND_INDEX);
2870 temp &= ~R300_MC_IND_ADDR_MASK;
2871 temp |= R300_MC_READ_CNTL_CD_mcind;
2872 WREG32(R300_MC_IND_INDEX, temp);
2873 temp = RREG32(R300_MC_IND_DATA);
2874 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
2875 } else {
2876 temp = RREG32(R300_MC_READ_CNTL_AB);
2877 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2878 }
2879 } else {
2880 temp = RREG32(R300_MC_READ_CNTL_AB);
2881 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2882 }
2883 if (rdev->family == CHIP_RV410 ||
2884 rdev->family == CHIP_R420 ||
2885 rdev->family == CHIP_R423)
2886 trbs_ff = memtrbs_r4xx[data];
2887 else
2888 trbs_ff = memtrbs[data];
2889 tcas_ff.full += trbs_ff.full;
2890 }
2891
2892 sclk_eff_ff.full = sclk_ff.full;
2893
2894 if (rdev->flags & RADEON_IS_AGP) {
2895 fixed20_12 agpmode_ff;
68adac5e
BS		 2896 agpmode_ff.full = dfixed_const(radeon_agpmode);
2897 temp_ff.full = dfixed_const_666(16);
2898 sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff);
c93bb85b
JG		 2899 }
2900 /* TODO PCIE lanes may affect this - agpmode == 16?? */
2901
2902 if (ASIC_IS_R300(rdev)) {
68adac5e 2903 sclk_delay_ff.full = dfixed_const(250);
c93bb85b
JG		 2904 } else {
2905 if ((rdev->family == CHIP_RV100) ||
2906 rdev->flags & RADEON_IS_IGP) {
2907 if (rdev->mc.vram_is_ddr)
68adac5e 2908 sclk_delay_ff.full = dfixed_const(41);
c93bb85b 2909 else
68adac5e 2910 sclk_delay_ff.full = dfixed_const(33);
c93bb85b
JG		 2911 } else {
2912 if (rdev->mc.vram_width == 128)
68adac5e 2913 sclk_delay_ff.full = dfixed_const(57);
c93bb85b 2914 else
68adac5e 2915 sclk_delay_ff.full = dfixed_const(41);
c93bb85b
JG		 2916 }
2917 }
2918
68adac5e 2919 mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff);
c93bb85b
JG		 2920
2921 if (rdev->mc.vram_is_ddr) {
2922 if (rdev->mc.vram_width == 32) {
68adac5e 2923 k1.full = dfixed_const(40);
c93bb85b
JG		 2924 c = 3;
2925 } else {
68adac5e 2926 k1.full = dfixed_const(20);
c93bb85b
JG		 2927 c = 1;
2928 }
2929 } else {
68adac5e 2930 k1.full = dfixed_const(40);
c93bb85b
JG		 2931 c = 3;
2932 }
2933
68adac5e
BS		 2934 temp_ff.full = dfixed_const(2);
2935 mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff);
2936 temp_ff.full = dfixed_const(c);
2937 mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff);
2938 temp_ff.full = dfixed_const(4);
2939 mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff);
2940 mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff);
c93bb85b
JG		 2941 mc_latency_mclk.full += k1.full;
2942
68adac5e
BS		 2943 mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff);
2944 mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff);
c93bb85b
JG		 2945
2946 /*
2947 HW cursor time assuming worst case of full size colour cursor.
2948 */
68adac5e 2949 temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
c93bb85b
JG		 2950 temp_ff.full += trcd_ff.full;
2951 if (temp_ff.full < tras_ff.full)
2952 temp_ff.full = tras_ff.full;
68adac5e 2953 cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff);
c93bb85b 2954
68adac5e
BS		 2955 temp_ff.full = dfixed_const(cur_size);
2956 cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff);
c93bb85b
JG		 2957 /*
2958 Find the total latency for the display data.
2959 */
68adac5e
BS		 2960 disp_latency_overhead.full = dfixed_const(8);
2961 disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff);
c93bb85b
JG		 2962 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
2963 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
2964
2965 if (mc_latency_mclk.full > mc_latency_sclk.full)
2966 disp_latency.full = mc_latency_mclk.full;
2967 else
2968 disp_latency.full = mc_latency_sclk.full;
2969
2970 /* setup Max GRPH_STOP_REQ default value */
2971 if (ASIC_IS_RV100(rdev))
2972 max_stop_req = 0x5c;
2973 else
2974 max_stop_req = 0x7c;
2975
2976 if (mode1) {
2977 /* CRTC1
2978 Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
2979 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
2980 */
2981 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
2982
2983 if (stop_req > max_stop_req)
2984 stop_req = max_stop_req;
2985
2986 /*
2987 Find the drain rate of the display buffer.
2988 */
68adac5e
BS		 2989 temp_ff.full = dfixed_const((16/pixel_bytes1));
2990 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff);
c93bb85b
JG		 2991
2992 /*
2993 Find the critical point of the display buffer.
2994 */
68adac5e
BS		 2995 crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency);
2996 crit_point_ff.full += dfixed_const_half(0);
c93bb85b 2997
68adac5e 2998 critical_point = dfixed_trunc(crit_point_ff);
c93bb85b
JG		 2999
3000 if (rdev->disp_priority == 2) {
3001 critical_point = 0;
3002 }
3003
3004 /*
3005 The critical point should never be above max_stop_req-4. Setting
3006 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
3007 */
3008 if (max_stop_req - critical_point < 4)
3009 critical_point = 0;
3010
3011 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
3012 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
3013 critical_point = 0x10;
3014 }
3015
3016 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
3017 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
3018 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3019 temp &= ~(RADEON_GRPH_START_REQ_MASK);
3020 if ((rdev->family == CHIP_R350) &&
3021 (stop_req > 0x15)) {
3022 stop_req -= 0x10;
3023 }
3024 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3025 temp |= RADEON_GRPH_BUFFER_SIZE;
3026 temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
3027 RADEON_GRPH_CRITICAL_AT_SOF |
3028 RADEON_GRPH_STOP_CNTL);
3029 /*
3030 Write the result into the register.
3031 */
3032 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3033 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3034
3035#if 0
3036 if ((rdev->family == CHIP_RS400) ||
3037 (rdev->family == CHIP_RS480)) {
3038 /* attempt to program RS400 disp regs correctly ??? */
3039 temp = RREG32(RS400_DISP1_REG_CNTL);
3040 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
3041 RS400_DISP1_STOP_REQ_LEVEL_MASK);
3042 WREG32(RS400_DISP1_REQ_CNTL1, (temp |
3043 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3044 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3045 temp = RREG32(RS400_DMIF_MEM_CNTL1);
3046 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
3047 RS400_DISP1_CRITICAL_POINT_STOP_MASK);
3048 WREG32(RS400_DMIF_MEM_CNTL1, (temp |
3049 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
3050 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
3051 }
3052#endif
3053
d9fdaafb 3054 DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n",
c93bb85b
JG		 3055 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */
3056 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
3057 }
3058
3059 if (mode2) {
3060 u32 grph2_cntl;
3061 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
3062
3063 if (stop_req > max_stop_req)
3064 stop_req = max_stop_req;
3065
3066 /*
3067 Find the drain rate of the display buffer.
3068 */
68adac5e
BS		 3069 temp_ff.full = dfixed_const((16/pixel_bytes2));
3070 disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff);
c93bb85b
JG		 3071
3072 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
3073 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
3074 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3075 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
3076 if ((rdev->family == CHIP_R350) &&
3077 (stop_req > 0x15)) {
3078 stop_req -= 0x10;
3079 }
3080 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3081 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
3082 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL |
3083 RADEON_GRPH_CRITICAL_AT_SOF |
3084 RADEON_GRPH_STOP_CNTL);
3085
3086 if ((rdev->family == CHIP_RS100) ||
3087 (rdev->family == CHIP_RS200))
3088 critical_point2 = 0;
3089 else {
3090 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
68adac5e
BS		 3091 temp_ff.full = dfixed_const(temp);
3092 temp_ff.full = dfixed_mul(mclk_ff, temp_ff);
c93bb85b
JG		 3093 if (sclk_ff.full < temp_ff.full)
3094 temp_ff.full = sclk_ff.full;
3095
3096 read_return_rate.full = temp_ff.full;
3097
3098 if (mode1) {
3099 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
68adac5e 3100 time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff);
c93bb85b
JG		 3101 } else {
3102 time_disp1_drop_priority.full = 0;
3103 }
3104 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
68adac5e
BS		 3105 crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2);
3106 crit_point_ff.full += dfixed_const_half(0);
c93bb85b 3107
68adac5e 3108 critical_point2 = dfixed_trunc(crit_point_ff);
c93bb85b
JG		 3109
3110 if (rdev->disp_priority == 2) {
3111 critical_point2 = 0;
3112 }
3113
3114 if (max_stop_req - critical_point2 < 4)
3115 critical_point2 = 0;
3116
3117 }
3118
3119 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
3120 /* some R300 cards have problem with this set to 0 */
3121 critical_point2 = 0x10;
3122 }
3123
3124 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3125 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3126
3127 if ((rdev->family == CHIP_RS400) ||
3128 (rdev->family == CHIP_RS480)) {
3129#if 0
3130 /* attempt to program RS400 disp2 regs correctly ??? */
3131 temp = RREG32(RS400_DISP2_REQ_CNTL1);
3132 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
3133 RS400_DISP2_STOP_REQ_LEVEL_MASK);
3134 WREG32(RS400_DISP2_REQ_CNTL1, (temp |
3135 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3136 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3137 temp = RREG32(RS400_DISP2_REQ_CNTL2);
3138 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
3139 RS400_DISP2_CRITICAL_POINT_STOP_MASK);
3140 WREG32(RS400_DISP2_REQ_CNTL2, (temp |
3141 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
3142 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
3143#endif
3144 WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
3145 WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
3146 WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
3147 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
3148 }
3149
d9fdaafb 3150 DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n",
c93bb85b
JG		 3151 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
3152 }
3153}
551ebd83
DA		 3154
3155static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
3156{
3157 DRM_ERROR("pitch %d\n", t->pitch);
ceb776bc 3158 DRM_ERROR("use_pitch %d\n", t->use_pitch);
551ebd83 3159 DRM_ERROR("width %d\n", t->width);
ceb776bc 3160 DRM_ERROR("width_11 %d\n", t->width_11);
551ebd83 3161 DRM_ERROR("height %d\n", t->height);
ceb776bc 3162 DRM_ERROR("height_11 %d\n", t->height_11);
551ebd83
DA		 3163 DRM_ERROR("num levels %d\n", t->num_levels);
3164 DRM_ERROR("depth %d\n", t->txdepth);
3165 DRM_ERROR("bpp %d\n", t->cpp);
3166 DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
3167 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
3168 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
d785d78b 3169 DRM_ERROR("compress format %d\n", t->compress_format);
551ebd83
DA		 3170}
3171
d785d78b
DA		 3172static int r100_track_compress_size(int compress_format, int w, int h)
3173{
3174 int block_width, block_height, block_bytes;
3175 int wblocks, hblocks;
3176 int min_wblocks;
3177 int sz;
3178
3179 block_width = 4;
3180 block_height = 4;
3181
3182 switch (compress_format) {
3183 case R100_TRACK_COMP_DXT1:
3184 block_bytes = 8;
3185 min_wblocks = 4;
3186 break;
3187 default:
3188 case R100_TRACK_COMP_DXT35:
3189 block_bytes = 16;
3190 min_wblocks = 2;
3191 break;
3192 }
3193
3194 hblocks = (h + block_height - 1) / block_height;
3195 wblocks = (w + block_width - 1) / block_width;
3196 if (wblocks < min_wblocks)
3197 wblocks = min_wblocks;
3198 sz = wblocks * hblocks * block_bytes;
3199 return sz;
3200}
3201
37cf6b03
RS		 3202static int r100_cs_track_cube(struct radeon_device *rdev,
3203 struct r100_cs_track *track, unsigned idx)
3204{
3205 unsigned face, w, h;
3206 struct radeon_bo *cube_robj;
3207 unsigned long size;
3208 unsigned compress_format = track->textures[idx].compress_format;
3209
3210 for (face = 0; face < 5; face++) {
3211 cube_robj = track->textures[idx].cube_info[face].robj;
3212 w = track->textures[idx].cube_info[face].width;
3213 h = track->textures[idx].cube_info[face].height;
3214
3215 if (compress_format) {
3216 size = r100_track_compress_size(compress_format, w, h);
3217 } else
3218 size = w * h;
3219 size *= track->textures[idx].cpp;
3220
3221 size += track->textures[idx].cube_info[face].offset;
3222
3223 if (size > radeon_bo_size(cube_robj)) {
3224 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
3225 size, radeon_bo_size(cube_robj));
3226 r100_cs_track_texture_print(&track->textures[idx]);
3227 return -1;
3228 }
3229 }
3230 return 0;
3231}
3232
551ebd83
DA		 3233static int r100_cs_track_texture_check(struct radeon_device *rdev,
3234 struct r100_cs_track *track)
3235{
4c788679 3236 struct radeon_bo *robj;
551ebd83 3237 unsigned long size;
b73c5f8b 3238 unsigned u, i, w, h, d;
551ebd83
DA		 3239 int ret;
3240
3241 for (u = 0; u < track->num_texture; u++) {
3242 if (!track->textures[u].enabled)
3243 continue;
43b93fbf
AD		 3244 if (track->textures[u].lookup_disable)
3245 continue;
551ebd83
DA		 3246 robj = track->textures[u].robj;
3247 if (robj == NULL) {
3248 DRM_ERROR("No texture bound to unit %u\n", u);
3249 return -EINVAL;
3250 }
3251 size = 0;
3252 for (i = 0; i <= track->textures[u].num_levels; i++) {
3253 if (track->textures[u].use_pitch) {
3254 if (rdev->family < CHIP_R300)
3255 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
3256 else
3257 w = track->textures[u].pitch / (1 << i);
3258 } else {
ceb776bc 3259 w = track->textures[u].width;
551ebd83
DA		 3260 if (rdev->family >= CHIP_RV515)
3261 w |= track->textures[u].width_11;
ceb776bc 3262 w = w / (1 << i);
551ebd83
DA		 3263 if (track->textures[u].roundup_w)
3264 w = roundup_pow_of_two(w);
3265 }
ceb776bc 3266 h = track->textures[u].height;
551ebd83
DA		 3267 if (rdev->family >= CHIP_RV515)
3268 h |= track->textures[u].height_11;
ceb776bc 3269 h = h / (1 << i);
551ebd83
DA		 3270 if (track->textures[u].roundup_h)
3271 h = roundup_pow_of_two(h);
b73c5f8b
MO		 3272 if (track->textures[u].tex_coord_type == 1) {
3273 d = (1 << track->textures[u].txdepth) / (1 << i);
3274 if (!d)
3275 d = 1;
3276 } else {
3277 d = 1;
3278 }
d785d78b
DA		 3279 if (track->textures[u].compress_format) {
3280
b73c5f8b 3281 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
d785d78b
DA		 3282 /* compressed textures are block based */
3283 } else
b73c5f8b 3284 size += w * h * d;
551ebd83
DA		 3285 }
3286 size *= track->textures[u].cpp;
d785d78b 3287
551ebd83
DA		 3288 switch (track->textures[u].tex_coord_type) {
3289 case 0:
551ebd83 3290 case 1:
551ebd83
DA		 3291 break;
3292 case 2:
3293 if (track->separate_cube) {
3294 ret = r100_cs_track_cube(rdev, track, u);
3295 if (ret)
3296 return ret;
3297 } else
3298 size *= 6;
3299 break;
3300 default:
3301 DRM_ERROR("Invalid texture coordinate type %u for unit "
3302 "%u\n", track->textures[u].tex_coord_type, u);
3303 return -EINVAL;
3304 }
4c788679 3305 if (size > radeon_bo_size(robj)) {
551ebd83 3306 DRM_ERROR("Texture of unit %u needs %lu bytes but is "
4c788679 3307 "%lu\n", u, size, radeon_bo_size(robj));
551ebd83
DA		 3308 r100_cs_track_texture_print(&track->textures[u]);
3309 return -EINVAL;
3310 }
3311 }
3312 return 0;
3313}
3314
3315int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
3316{
3317 unsigned i;
3318 unsigned long size;
3319 unsigned prim_walk;
3320 unsigned nverts;
a41ceb1c 3321 unsigned num_cb = track->num_cb;
551ebd83 3322
a41ceb1c
MO		 3323 if (!track->zb_cb_clear && !track->color_channel_mask &&
3324 !track->blend_read_enable)
3325 num_cb = 0;
3326
3327 for (i = 0; i < num_cb; i++) {
551ebd83
DA		 3328 if (track->cb[i].robj == NULL) {
3329 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
3330 return -EINVAL;
3331 }
3332 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
3333 size += track->cb[i].offset;
4c788679 3334 if (size > radeon_bo_size(track->cb[i].robj)) {
551ebd83
DA		 3335 DRM_ERROR("[drm] Buffer too small for color buffer %d "
3336 "(need %lu have %lu) !\n", i, size,
4c788679 3337 radeon_bo_size(track->cb[i].robj));
551ebd83
DA		 3338 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
3339 i, track->cb[i].pitch, track->cb[i].cpp,
3340 track->cb[i].offset, track->maxy);
3341 return -EINVAL;
3342 }
3343 }
3344 if (track->z_enabled) {
3345 if (track->zb.robj == NULL) {
3346 DRM_ERROR("[drm] No buffer for z buffer !\n");
3347 return -EINVAL;
3348 }
3349 size = track->zb.pitch * track->zb.cpp * track->maxy;
3350 size += track->zb.offset;
4c788679 3351 if (size > radeon_bo_size(track->zb.robj)) {
551ebd83
DA		 3352 DRM_ERROR("[drm] Buffer too small for z buffer "
3353 "(need %lu have %lu) !\n", size,
4c788679 3354 radeon_bo_size(track->zb.robj));
551ebd83
DA		 3355 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
3356 track->zb.pitch, track->zb.cpp,
3357 track->zb.offset, track->maxy);
3358 return -EINVAL;
3359 }
3360 }
3361 prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
cae94b0a
MO		 3362 if (track->vap_vf_cntl & (1 << 14)) {
3363 nverts = track->vap_alt_nverts;
3364 } else {
3365 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
3366 }
551ebd83
DA		 3367 switch (prim_walk) {
3368 case 1:
3369 for (i = 0; i < track->num_arrays; i++) {
3370 size = track->arrays[i].esize * track->max_indx * 4;
3371 if (track->arrays[i].robj == NULL) {
3372 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3373 "bound\n", prim_walk, i);
3374 return -EINVAL;
3375 }
4c788679
JG		 3376 if (size > radeon_bo_size(track->arrays[i].robj)) {
3377 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3378 "need %lu dwords have %lu dwords\n",
3379 prim_walk, i, size >> 2,
3380 radeon_bo_size(track->arrays[i].robj)
3381 >> 2);
551ebd83
DA		 3382 DRM_ERROR("Max indices %u\n", track->max_indx);
3383 return -EINVAL;
3384 }
3385 }
3386 break;
3387 case 2:
3388 for (i = 0; i < track->num_arrays; i++) {
3389 size = track->arrays[i].esize * (nverts - 1) * 4;
3390 if (track->arrays[i].robj == NULL) {
3391 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3392 "bound\n", prim_walk, i);
3393 return -EINVAL;
3394 }
4c788679
JG		 3395 if (size > radeon_bo_size(track->arrays[i].robj)) {
3396 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3397 "need %lu dwords have %lu dwords\n",
3398 prim_walk, i, size >> 2,
3399 radeon_bo_size(track->arrays[i].robj)
3400 >> 2);
551ebd83
DA		 3401 return -EINVAL;
3402 }
3403 }
3404 break;
3405 case 3:
3406 size = track->vtx_size * nverts;
3407 if (size != track->immd_dwords) {
3408 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
3409 track->immd_dwords, size);
3410 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
3411 nverts, track->vtx_size);
3412 return -EINVAL;
3413 }
3414 break;
3415 default:
3416 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
3417 prim_walk);
3418 return -EINVAL;
3419 }
3420 return r100_cs_track_texture_check(rdev, track);
3421}
3422
3423void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
3424{
3425 unsigned i, face;
3426
3427 if (rdev->family < CHIP_R300) {
3428 track->num_cb = 1;
3429 if (rdev->family <= CHIP_RS200)
3430 track->num_texture = 3;
3431 else
3432 track->num_texture = 6;
3433 track->maxy = 2048;
3434 track->separate_cube = 1;
3435 } else {
3436 track->num_cb = 4;
3437 track->num_texture = 16;
3438 track->maxy = 4096;
3439 track->separate_cube = 0;
3440 }
3441
3442 for (i = 0; i < track->num_cb; i++) {
3443 track->cb[i].robj = NULL;
3444 track->cb[i].pitch = 8192;
3445 track->cb[i].cpp = 16;
3446 track->cb[i].offset = 0;
3447 }
3448 track->z_enabled = true;
3449 track->zb.robj = NULL;
3450 track->zb.pitch = 8192;
3451 track->zb.cpp = 4;
3452 track->zb.offset = 0;
3453 track->vtx_size = 0x7F;
3454 track->immd_dwords = 0xFFFFFFFFUL;
3455 track->num_arrays = 11;
3456 track->max_indx = 0x00FFFFFFUL;
3457 for (i = 0; i < track->num_arrays; i++) {
3458 track->arrays[i].robj = NULL;
3459 track->arrays[i].esize = 0x7F;
3460 }
3461 for (i = 0; i < track->num_texture; i++) {
d785d78b 3462 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
551ebd83
DA		 3463 track->textures[i].pitch = 16536;
3464 track->textures[i].width = 16536;
3465 track->textures[i].height = 16536;
3466 track->textures[i].width_11 = 1 << 11;
3467 track->textures[i].height_11 = 1 << 11;
3468 track->textures[i].num_levels = 12;
3469 if (rdev->family <= CHIP_RS200) {
3470 track->textures[i].tex_coord_type = 0;
3471 track->textures[i].txdepth = 0;
3472 } else {
3473 track->textures[i].txdepth = 16;
3474 track->textures[i].tex_coord_type = 1;
3475 }
3476 track->textures[i].cpp = 64;
3477 track->textures[i].robj = NULL;
3478 /* CS IB emission code makes sure texture unit are disabled */
3479 track->textures[i].enabled = false;
43b93fbf 3480 track->textures[i].lookup_disable = false;
551ebd83
DA		 3481 track->textures[i].roundup_w = true;
3482 track->textures[i].roundup_h = true;
3483 if (track->separate_cube)
3484 for (face = 0; face < 5; face++) {
3485 track->textures[i].cube_info[face].robj = NULL;
3486 track->textures[i].cube_info[face].width = 16536;
3487 track->textures[i].cube_info[face].height = 16536;
3488 track->textures[i].cube_info[face].offset = 0;
3489 }
3490 }
3491}
3ce0a23d
JG		 3492
3493int r100_ring_test(struct radeon_device *rdev)
3494{
3495 uint32_t scratch;
3496 uint32_t tmp = 0;
3497 unsigned i;
3498 int r;
3499
3500 r = radeon_scratch_get(rdev, &scratch);
3501 if (r) {
3502 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3503 return r;
3504 }
3505 WREG32(scratch, 0xCAFEDEAD);
3506 r = radeon_ring_lock(rdev, 2);
3507 if (r) {
3508 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3509 radeon_scratch_free(rdev, scratch);
3510 return r;
3511 }
3512 radeon_ring_write(rdev, PACKET0(scratch, 0));
3513 radeon_ring_write(rdev, 0xDEADBEEF);
3514 radeon_ring_unlock_commit(rdev);
3515 for (i = 0; i < rdev->usec_timeout; i++) {
3516 tmp = RREG32(scratch);
3517 if (tmp == 0xDEADBEEF) {
3518 break;
3519 }
3520 DRM_UDELAY(1);
3521 }
3522 if (i < rdev->usec_timeout) {
3523 DRM_INFO("ring test succeeded in %d usecs\n", i);
3524 } else {
369d7ec1 3525 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
3ce0a23d
JG		 3526 scratch, tmp);
3527 r = -EINVAL;
3528 }
3529 radeon_scratch_free(rdev, scratch);
3530 return r;
3531}
3532
3533void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3534{
3535 radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1));
3536 radeon_ring_write(rdev, ib->gpu_addr);
3537 radeon_ring_write(rdev, ib->length_dw);
3538}
3539
3540int r100_ib_test(struct radeon_device *rdev)
3541{
3542 struct radeon_ib *ib;
3543 uint32_t scratch;
3544 uint32_t tmp = 0;
3545 unsigned i;
3546 int r;
3547
3548 r = radeon_scratch_get(rdev, &scratch);
3549 if (r) {
3550 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3551 return r;
3552 }
3553 WREG32(scratch, 0xCAFEDEAD);
3554 r = radeon_ib_get(rdev, &ib);
3555 if (r) {
3556 return r;
3557 }
3558 ib->ptr[0] = PACKET0(scratch, 0);
3559 ib->ptr[1] = 0xDEADBEEF;
3560 ib->ptr[2] = PACKET2(0);
3561 ib->ptr[3] = PACKET2(0);
3562 ib->ptr[4] = PACKET2(0);
3563 ib->ptr[5] = PACKET2(0);
3564 ib->ptr[6] = PACKET2(0);
3565 ib->ptr[7] = PACKET2(0);
3566 ib->length_dw = 8;
3567 r = radeon_ib_schedule(rdev, ib);
3568 if (r) {
3569 radeon_scratch_free(rdev, scratch);
3570 radeon_ib_free(rdev, &ib);
3571 return r;
3572 }
3573 r = radeon_fence_wait(ib->fence, false);
3574 if (r) {
3575 return r;
3576 }
3577 for (i = 0; i < rdev->usec_timeout; i++) {
3578 tmp = RREG32(scratch);
3579 if (tmp == 0xDEADBEEF) {
3580 break;
3581 }
3582 DRM_UDELAY(1);
3583 }
3584 if (i < rdev->usec_timeout) {
3585 DRM_INFO("ib test succeeded in %u usecs\n", i);
3586 } else {
3587 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
3588 scratch, tmp);
3589 r = -EINVAL;
3590 }
3591 radeon_scratch_free(rdev, scratch);
3592 radeon_ib_free(rdev, &ib);
3593 return r;
3594}
9f022ddf
JG		 3595
3596void r100_ib_fini(struct radeon_device *rdev)
3597{
3598 radeon_ib_pool_fini(rdev);
3599}
3600
3601int r100_ib_init(struct radeon_device *rdev)
3602{
3603 int r;
3604
3605 r = radeon_ib_pool_init(rdev);
3606 if (r) {
3607 dev_err(rdev->dev, "failled initializing IB pool (%d).\n", r);
3608 r100_ib_fini(rdev);
3609 return r;
3610 }
3611 r = r100_ib_test(rdev);
3612 if (r) {
3613 dev_err(rdev->dev, "failled testing IB (%d).\n", r);
3614 r100_ib_fini(rdev);
3615 return r;
3616 }
3617 return 0;
3618}
3619
3620void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3621{
3622 /* Shutdown CP we shouldn't need to do that but better be safe than
3623 * sorry
3624 */
3625 rdev->cp.ready = false;
3626 WREG32(R_000740_CP_CSQ_CNTL, 0);
3627
3628 /* Save few CRTC registers */
ca6ffc64 3629 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
9f022ddf
JG		 3630 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3631 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3632 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3633 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3634 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3635 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3636 }
3637
3638 /* Disable VGA aperture access */
ca6ffc64 3639 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
9f022ddf
JG		 3640 /* Disable cursor, overlay, crtc */
3641 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3642 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3643 S_000054_CRTC_DISPLAY_DIS(1));
3644 WREG32(R_000050_CRTC_GEN_CNTL,
3645 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3646 S_000050_CRTC_DISP_REQ_EN_B(1));
3647 WREG32(R_000420_OV0_SCALE_CNTL,
3648 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3649 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3650 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3651 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3652 S_000360_CUR2_LOCK(1));
3653 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3654 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3655 S_0003F8_CRTC2_DISPLAY_DIS(1) |
3656 S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3657 WREG32(R_000360_CUR2_OFFSET,
3658 C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3659 }
3660}
3661
3662void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3663{
3664 /* Update base address for crtc */
d594e46a 3665 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
9f022ddf 3666 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
d594e46a 3667 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
9f022ddf
JG		 3668 }
3669 /* Restore CRTC registers */
ca6ffc64 3670 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
9f022ddf
JG		 3671 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3672 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3673 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3674 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3675 }
3676}
ca6ffc64
JG		 3677
3678void r100_vga_render_disable(struct radeon_device *rdev)
3679{
d4550907 3680 u32 tmp;
ca6ffc64 3681
d4550907 3682 tmp = RREG8(R_0003C2_GENMO_WT);
ca6ffc64
JG		 3683 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3684}
d4550907
JG		 3685
3686static void r100_debugfs(struct radeon_device *rdev)
3687{
3688 int r;
3689
3690 r = r100_debugfs_mc_info_init(rdev);
3691 if (r)
3692 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3693}
3694
3695static void r100_mc_program(struct radeon_device *rdev)
3696{
3697 struct r100_mc_save save;
3698
3699 /* Stops all mc clients */
3700 r100_mc_stop(rdev, &save);
3701 if (rdev->flags & RADEON_IS_AGP) {
3702 WREG32(R_00014C_MC_AGP_LOCATION,
3703 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3704 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3705 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3706 if (rdev->family > CHIP_RV200)
3707 WREG32(R_00015C_AGP_BASE_2,
3708 upper_32_bits(rdev->mc.agp_base) & 0xff);
3709 } else {
3710 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3711 WREG32(R_000170_AGP_BASE, 0);
3712 if (rdev->family > CHIP_RV200)
3713 WREG32(R_00015C_AGP_BASE_2, 0);
3714 }
3715 /* Wait for mc idle */
3716 if (r100_mc_wait_for_idle(rdev))
3717 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3718 /* Program MC, should be a 32bits limited address space */
3719 WREG32(R_000148_MC_FB_LOCATION,
3720 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3721 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3722 r100_mc_resume(rdev, &save);
3723}
3724
3725void r100_clock_startup(struct radeon_device *rdev)
3726{
3727 u32 tmp;
3728
3729 if (radeon_dynclks != -1 && radeon_dynclks)
3730 radeon_legacy_set_clock_gating(rdev, 1);
3731 /* We need to force on some of the block */
3732 tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3733 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3734 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3735 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3736 WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3737}
3738
3739static int r100_startup(struct radeon_device *rdev)
3740{
3741 int r;
3742
92cde00c
AD		 3743 /* set common regs */
3744 r100_set_common_regs(rdev);
3745 /* program mc */
d4550907
JG		 3746 r100_mc_program(rdev);
3747 /* Resume clock */
3748 r100_clock_startup(rdev);
3749 /* Initialize GPU configuration (# pipes, ...) */
90aca4d2 3750// r100_gpu_init(rdev);
d4550907
JG		 3751 /* Initialize GART (initialize after TTM so we can allocate
3752 * memory through TTM but finalize after TTM) */
17e15b0c 3753 r100_enable_bm(rdev);
d4550907
JG		 3754 if (rdev->flags & RADEON_IS_PCI) {
3755 r = r100_pci_gart_enable(rdev);
3756 if (r)
3757 return r;
3758 }
724c80e1
AD		 3759
3760 /* allocate wb buffer */
3761 r = radeon_wb_init(rdev);
3762 if (r)
3763 return r;
3764
d4550907 3765 /* Enable IRQ */
d4550907 3766 r100_irq_set(rdev);
cafe6609 3767 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
d4550907
JG		 3768 /* 1M ring buffer */
3769 r = r100_cp_init(rdev, 1024 * 1024);
3770 if (r) {
3771 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
3772 return r;
3773 }
d4550907
JG		 3774 r = r100_ib_init(rdev);
3775 if (r) {
3776 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
3777 return r;
3778 }
3779 return 0;
3780}
3781
3782int r100_resume(struct radeon_device *rdev)
3783{
3784 /* Make sur GART are not working */
3785 if (rdev->flags & RADEON_IS_PCI)
3786 r100_pci_gart_disable(rdev);
3787 /* Resume clock before doing reset */
3788 r100_clock_startup(rdev);
3789 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
a2d07b74 3790 if (radeon_asic_reset(rdev)) {
d4550907
JG		 3791 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3792 RREG32(R_000E40_RBBM_STATUS),
3793 RREG32(R_0007C0_CP_STAT));
3794 }
3795 /* post */
3796 radeon_combios_asic_init(rdev->ddev);
3797 /* Resume clock after posting */
3798 r100_clock_startup(rdev);
550e2d92
DA		 3799 /* Initialize surface registers */
3800 radeon_surface_init(rdev);
d4550907
JG		 3801 return r100_startup(rdev);
3802}
3803
3804int r100_suspend(struct radeon_device *rdev)
3805{
3806 r100_cp_disable(rdev);
724c80e1 3807 radeon_wb_disable(rdev);
d4550907
JG		 3808 r100_irq_disable(rdev);
3809 if (rdev->flags & RADEON_IS_PCI)
3810 r100_pci_gart_disable(rdev);
3811 return 0;
3812}
3813
3814void r100_fini(struct radeon_device *rdev)
3815{
d4550907 3816 r100_cp_fini(rdev);
724c80e1 3817 radeon_wb_fini(rdev);
d4550907
JG		 3818 r100_ib_fini(rdev);
3819 radeon_gem_fini(rdev);
3820 if (rdev->flags & RADEON_IS_PCI)
3821 r100_pci_gart_fini(rdev);
d0269ed8 3822 radeon_agp_fini(rdev);
d4550907
JG		 3823 radeon_irq_kms_fini(rdev);
3824 radeon_fence_driver_fini(rdev);
4c788679 3825 radeon_bo_fini(rdev);
d4550907
JG		 3826 radeon_atombios_fini(rdev);
3827 kfree(rdev->bios);
3828 rdev->bios = NULL;
3829}
3830
4c712e6c
DA		 3831/*
3832 * Due to how kexec works, it can leave the hw fully initialised when it
3833 * boots the new kernel. However doing our init sequence with the CP and
3834 * WB stuff setup causes GPU hangs on the RN50 at least. So at startup
3835 * do some quick sanity checks and restore sane values to avoid this
3836 * problem.
3837 */
3838void r100_restore_sanity(struct radeon_device *rdev)
3839{
3840 u32 tmp;
3841
3842 tmp = RREG32(RADEON_CP_CSQ_CNTL);
3843 if (tmp) {
3844 WREG32(RADEON_CP_CSQ_CNTL, 0);
3845 }
3846 tmp = RREG32(RADEON_CP_RB_CNTL);
3847 if (tmp) {
3848 WREG32(RADEON_CP_RB_CNTL, 0);
3849 }
3850 tmp = RREG32(RADEON_SCRATCH_UMSK);
3851 if (tmp) {
3852 WREG32(RADEON_SCRATCH_UMSK, 0);
3853 }
3854}
3855
d4550907
JG		 3856int r100_init(struct radeon_device *rdev)
3857{
3858 int r;
3859
d4550907
JG		 3860 /* Register debugfs file specific to this group of asics */
3861 r100_debugfs(rdev);
3862 /* Disable VGA */
3863 r100_vga_render_disable(rdev);
3864 /* Initialize scratch registers */
3865 radeon_scratch_init(rdev);
3866 /* Initialize surface registers */
3867 radeon_surface_init(rdev);
4c712e6c
DA		 3868 /* sanity check some register to avoid hangs like after kexec */
3869 r100_restore_sanity(rdev);
d4550907
JG		 3870 /* TODO: disable VGA need to use VGA request */
3871 /* BIOS*/
3872 if (!radeon_get_bios(rdev)) {
3873 if (ASIC_IS_AVIVO(rdev))
3874 return -EINVAL;
3875 }
3876 if (rdev->is_atom_bios) {
3877 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
3878 return -EINVAL;
3879 } else {
3880 r = radeon_combios_init(rdev);
3881 if (r)
3882 return r;
3883 }
3884 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
a2d07b74 3885 if (radeon_asic_reset(rdev)) {
d4550907
JG		 3886 dev_warn(rdev->dev,
3887 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3888 RREG32(R_000E40_RBBM_STATUS),
3889 RREG32(R_0007C0_CP_STAT));
3890 }
3891 /* check if cards are posted or not */
72542d77
DA		 3892 if (radeon_boot_test_post_card(rdev) == false)
3893 return -EINVAL;
d4550907
JG		 3894 /* Set asic errata */
3895 r100_errata(rdev);
3896 /* Initialize clocks */
3897 radeon_get_clock_info(rdev->ddev);
d594e46a
JG		 3898 /* initialize AGP */
3899 if (rdev->flags & RADEON_IS_AGP) {
3900 r = radeon_agp_init(rdev);
3901 if (r) {
3902 radeon_agp_disable(rdev);
3903 }
3904 }
3905 /* initialize VRAM */
3906 r100_mc_init(rdev);
d4550907
JG		 3907 /* Fence driver */
3908 r = radeon_fence_driver_init(rdev);
3909 if (r)
3910 return r;
3911 r = radeon_irq_kms_init(rdev);
3912 if (r)
3913 return r;
3914 /* Memory manager */
4c788679 3915 r = radeon_bo_init(rdev);
d4550907
JG		 3916 if (r)
3917 return r;
3918 if (rdev->flags & RADEON_IS_PCI) {
3919 r = r100_pci_gart_init(rdev);
3920 if (r)
3921 return r;
3922 }
3923 r100_set_safe_registers(rdev);
3924 rdev->accel_working = true;
3925 r = r100_startup(rdev);
3926 if (r) {
3927 /* Somethings want wront with the accel init stop accel */
3928 dev_err(rdev->dev, "Disabling GPU acceleration\n");
d4550907 3929 r100_cp_fini(rdev);
724c80e1 3930 radeon_wb_fini(rdev);
d4550907 3931 r100_ib_fini(rdev);
655efd3d 3932 radeon_irq_kms_fini(rdev);
d4550907
JG		 3933 if (rdev->flags & RADEON_IS_PCI)
3934 r100_pci_gart_fini(rdev);
d4550907
JG		 3935 rdev->accel_working = false;
3936 }
3937 return 0;
3938}
kernel source for telekom puls (alcatel/mediatek)