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drm/radeon/kms: add initial colortiling support.
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / radeon / r100.c
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771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <linux/seq_file.h>
29#include "drmP.h"
30#include "drm.h"
31#include "radeon_drm.h"
32#include "radeon_microcode.h"
33#include "radeon_reg.h"
34#include "radeon.h"
35
36/* This files gather functions specifics to:
37 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
38 *
39 * Some of these functions might be used by newer ASICs.
40 */
41void r100_hdp_reset(struct radeon_device *rdev);
42void r100_gpu_init(struct radeon_device *rdev);
43int r100_gui_wait_for_idle(struct radeon_device *rdev);
44int r100_mc_wait_for_idle(struct radeon_device *rdev);
45void r100_gpu_wait_for_vsync(struct radeon_device *rdev);
46void r100_gpu_wait_for_vsync2(struct radeon_device *rdev);
47int r100_debugfs_mc_info_init(struct radeon_device *rdev);
48
49
50/*
51 * PCI GART
52 */
53void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
54{
55 /* TODO: can we do somethings here ? */
56 /* It seems hw only cache one entry so we should discard this
57 * entry otherwise if first GPU GART read hit this entry it
58 * could end up in wrong address. */
59}
60
61int r100_pci_gart_enable(struct radeon_device *rdev)
62{
63 uint32_t tmp;
64 int r;
65
66 /* Initialize common gart structure */
67 r = radeon_gart_init(rdev);
68 if (r) {
69 return r;
70 }
71 if (rdev->gart.table.ram.ptr == NULL) {
72 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
73 r = radeon_gart_table_ram_alloc(rdev);
74 if (r) {
75 return r;
76 }
77 }
78 /* discard memory request outside of configured range */
79 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
80 WREG32(RADEON_AIC_CNTL, tmp);
81 /* set address range for PCI address translate */
82 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_location);
83 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
84 WREG32(RADEON_AIC_HI_ADDR, tmp);
85 /* Enable bus mastering */
86 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
87 WREG32(RADEON_BUS_CNTL, tmp);
88 /* set PCI GART page-table base address */
89 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
90 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
91 WREG32(RADEON_AIC_CNTL, tmp);
92 r100_pci_gart_tlb_flush(rdev);
93 rdev->gart.ready = true;
94 return 0;
95}
96
97void r100_pci_gart_disable(struct radeon_device *rdev)
98{
99 uint32_t tmp;
100
101 /* discard memory request outside of configured range */
102 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
103 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
104 WREG32(RADEON_AIC_LO_ADDR, 0);
105 WREG32(RADEON_AIC_HI_ADDR, 0);
106}
107
108int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
109{
110 if (i < 0 || i > rdev->gart.num_gpu_pages) {
111 return -EINVAL;
112 }
ed10f95d 113 rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr));
771fe6b9
JG		 114 return 0;
115}
116
117int r100_gart_enable(struct radeon_device *rdev)
118{
119 if (rdev->flags & RADEON_IS_AGP) {
120 r100_pci_gart_disable(rdev);
121 return 0;
122 }
123 return r100_pci_gart_enable(rdev);
124}
125
126
127/*
128 * MC
129 */
130void r100_mc_disable_clients(struct radeon_device *rdev)
131{
132 uint32_t ov0_scale_cntl, crtc_ext_cntl, crtc_gen_cntl, crtc2_gen_cntl;
133
134 /* FIXME: is this function correct for rs100,rs200,rs300 ? */
135 if (r100_gui_wait_for_idle(rdev)) {
136 printk(KERN_WARNING "Failed to wait GUI idle while "
137 "programming pipes. Bad things might happen.\n");
138 }
139
140 /* stop display and memory access */
141 ov0_scale_cntl = RREG32(RADEON_OV0_SCALE_CNTL);
142 WREG32(RADEON_OV0_SCALE_CNTL, ov0_scale_cntl & ~RADEON_SCALER_ENABLE);
143 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
144 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl | RADEON_CRTC_DISPLAY_DIS);
145 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
146
147 r100_gpu_wait_for_vsync(rdev);
148
149 WREG32(RADEON_CRTC_GEN_CNTL,
150 (crtc_gen_cntl & ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_ICON_EN)) |
151 RADEON_CRTC_DISP_REQ_EN_B | RADEON_CRTC_EXT_DISP_EN);
152
153 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
154 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
155
156 r100_gpu_wait_for_vsync2(rdev);
157 WREG32(RADEON_CRTC2_GEN_CNTL,
158 (crtc2_gen_cntl &
159 ~(RADEON_CRTC2_CUR_EN | RADEON_CRTC2_ICON_EN)) |
160 RADEON_CRTC2_DISP_REQ_EN_B);
161 }
162
163 udelay(500);
164}
165
166void r100_mc_setup(struct radeon_device *rdev)
167{
168 uint32_t tmp;
169 int r;
170
171 r = r100_debugfs_mc_info_init(rdev);
172 if (r) {
173 DRM_ERROR("Failed to register debugfs file for R100 MC !\n");
174 }
175 /* Write VRAM size in case we are limiting it */
176 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.vram_size);
177 tmp = rdev->mc.vram_location + rdev->mc.vram_size - 1;
178 tmp = REG_SET(RADEON_MC_FB_TOP, tmp >> 16);
179 tmp |= REG_SET(RADEON_MC_FB_START, rdev->mc.vram_location >> 16);
180 WREG32(RADEON_MC_FB_LOCATION, tmp);
181
182 /* Enable bus mastering */
183 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
184 WREG32(RADEON_BUS_CNTL, tmp);
185
186 if (rdev->flags & RADEON_IS_AGP) {
187 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
188 tmp = REG_SET(RADEON_MC_AGP_TOP, tmp >> 16);
189 tmp |= REG_SET(RADEON_MC_AGP_START, rdev->mc.gtt_location >> 16);
190 WREG32(RADEON_MC_AGP_LOCATION, tmp);
191 WREG32(RADEON_AGP_BASE, rdev->mc.agp_base);
192 } else {
193 WREG32(RADEON_MC_AGP_LOCATION, 0x0FFFFFFF);
194 WREG32(RADEON_AGP_BASE, 0);
195 }
196
197 tmp = RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL;
198 tmp |= (7 << 28);
199 WREG32(RADEON_HOST_PATH_CNTL, tmp | RADEON_HDP_SOFT_RESET | RADEON_HDP_READ_BUFFER_INVALIDATE);
200 (void)RREG32(RADEON_HOST_PATH_CNTL);
201 WREG32(RADEON_HOST_PATH_CNTL, tmp);
202 (void)RREG32(RADEON_HOST_PATH_CNTL);
203}
204
205int r100_mc_init(struct radeon_device *rdev)
206{
207 int r;
208
209 if (r100_debugfs_rbbm_init(rdev)) {
210 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
211 }
212
213 r100_gpu_init(rdev);
214 /* Disable gart which also disable out of gart access */
215 r100_pci_gart_disable(rdev);
216
217 /* Setup GPU memory space */
771fe6b9
JG		 218 rdev->mc.gtt_location = 0xFFFFFFFFUL;
219 if (rdev->flags & RADEON_IS_AGP) {
220 r = radeon_agp_init(rdev);
221 if (r) {
222 printk(KERN_WARNING "[drm] Disabling AGP\n");
223 rdev->flags &= ~RADEON_IS_AGP;
224 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
225 } else {
226 rdev->mc.gtt_location = rdev->mc.agp_base;
227 }
228 }
229 r = radeon_mc_setup(rdev);
230 if (r) {
231 return r;
232 }
233
234 r100_mc_disable_clients(rdev);
235 if (r100_mc_wait_for_idle(rdev)) {
236 printk(KERN_WARNING "Failed to wait MC idle while "
237 "programming pipes. Bad things might happen.\n");
238 }
239
240 r100_mc_setup(rdev);
241 return 0;
242}
243
244void r100_mc_fini(struct radeon_device *rdev)
245{
246 r100_pci_gart_disable(rdev);
247 radeon_gart_table_ram_free(rdev);
248 radeon_gart_fini(rdev);
249}
250
251
252/*
253 * Fence emission
254 */
255void r100_fence_ring_emit(struct radeon_device *rdev,
256 struct radeon_fence *fence)
257{
258 /* Who ever call radeon_fence_emit should call ring_lock and ask
259 * for enough space (today caller are ib schedule and buffer move) */
260 /* Wait until IDLE & CLEAN */
261 radeon_ring_write(rdev, PACKET0(0x1720, 0));
262 radeon_ring_write(rdev, (1 << 16) | (1 << 17));
263 /* Emit fence sequence & fire IRQ */
264 radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
265 radeon_ring_write(rdev, fence->seq);
266 radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
267 radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
268}
269
270
271/*
272 * Writeback
273 */
274int r100_wb_init(struct radeon_device *rdev)
275{
276 int r;
277
278 if (rdev->wb.wb_obj == NULL) {
279 r = radeon_object_create(rdev, NULL, 4096,
280 true,
281 RADEON_GEM_DOMAIN_GTT,
282 false, &rdev->wb.wb_obj);
283 if (r) {
284 DRM_ERROR("radeon: failed to create WB buffer (%d).\n", r);
285 return r;
286 }
287 r = radeon_object_pin(rdev->wb.wb_obj,
288 RADEON_GEM_DOMAIN_GTT,
289 &rdev->wb.gpu_addr);
290 if (r) {
291 DRM_ERROR("radeon: failed to pin WB buffer (%d).\n", r);
292 return r;
293 }
294 r = radeon_object_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
295 if (r) {
296 DRM_ERROR("radeon: failed to map WB buffer (%d).\n", r);
297 return r;
298 }
299 }
300 WREG32(0x774, rdev->wb.gpu_addr);
301 WREG32(0x70C, rdev->wb.gpu_addr + 1024);
302 WREG32(0x770, 0xff);
303 return 0;
304}
305
306void r100_wb_fini(struct radeon_device *rdev)
307{
308 if (rdev->wb.wb_obj) {
309 radeon_object_kunmap(rdev->wb.wb_obj);
310 radeon_object_unpin(rdev->wb.wb_obj);
311 radeon_object_unref(&rdev->wb.wb_obj);
312 rdev->wb.wb = NULL;
313 rdev->wb.wb_obj = NULL;
314 }
315}
316
317int r100_copy_blit(struct radeon_device *rdev,
318 uint64_t src_offset,
319 uint64_t dst_offset,
320 unsigned num_pages,
321 struct radeon_fence *fence)
322{
323 uint32_t cur_pages;
324 uint32_t stride_bytes = PAGE_SIZE;
325 uint32_t pitch;
326 uint32_t stride_pixels;
327 unsigned ndw;
328 int num_loops;
329 int r = 0;
330
331 /* radeon limited to 16k stride */
332 stride_bytes &= 0x3fff;
333 /* radeon pitch is /64 */
334 pitch = stride_bytes / 64;
335 stride_pixels = stride_bytes / 4;
336 num_loops = DIV_ROUND_UP(num_pages, 8191);
337
338 /* Ask for enough room for blit + flush + fence */
339 ndw = 64 + (10 * num_loops);
340 r = radeon_ring_lock(rdev, ndw);
341 if (r) {
342 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
343 return -EINVAL;
344 }
345 while (num_pages > 0) {
346 cur_pages = num_pages;
347 if (cur_pages > 8191) {
348 cur_pages = 8191;
349 }
350 num_pages -= cur_pages;
351
352 /* pages are in Y direction - height
353 page width in X direction - width */
354 radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8));
355 radeon_ring_write(rdev,
356 RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
357 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
358 RADEON_GMC_SRC_CLIPPING |
359 RADEON_GMC_DST_CLIPPING |
360 RADEON_GMC_BRUSH_NONE |
361 (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
362 RADEON_GMC_SRC_DATATYPE_COLOR |
363 RADEON_ROP3_S |
364 RADEON_DP_SRC_SOURCE_MEMORY |
365 RADEON_GMC_CLR_CMP_CNTL_DIS |
366 RADEON_GMC_WR_MSK_DIS);
367 radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10));
368 radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10));
369 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
370 radeon_ring_write(rdev, 0);
371 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
372 radeon_ring_write(rdev, num_pages);
373 radeon_ring_write(rdev, num_pages);
374 radeon_ring_write(rdev, cur_pages | (stride_pixels << 16));
375 }
376 radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
377 radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL);
378 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
379 radeon_ring_write(rdev,
380 RADEON_WAIT_2D_IDLECLEAN |
381 RADEON_WAIT_HOST_IDLECLEAN |
382 RADEON_WAIT_DMA_GUI_IDLE);
383 if (fence) {
384 r = radeon_fence_emit(rdev, fence);
385 }
386 radeon_ring_unlock_commit(rdev);
387 return r;
388}
389
390
391/*
392 * CP
393 */
394void r100_ring_start(struct radeon_device *rdev)
395{
396 int r;
397
398 r = radeon_ring_lock(rdev, 2);
399 if (r) {
400 return;
401 }
402 radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
403 radeon_ring_write(rdev,
404 RADEON_ISYNC_ANY2D_IDLE3D |
405 RADEON_ISYNC_ANY3D_IDLE2D |
406 RADEON_ISYNC_WAIT_IDLEGUI |
407 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
408 radeon_ring_unlock_commit(rdev);
409}
410
411static void r100_cp_load_microcode(struct radeon_device *rdev)
412{
413 int i;
414
415 if (r100_gui_wait_for_idle(rdev)) {
416 printk(KERN_WARNING "Failed to wait GUI idle while "
417 "programming pipes. Bad things might happen.\n");
418 }
419
420 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
421 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
422 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
423 (rdev->family == CHIP_RS200)) {
424 DRM_INFO("Loading R100 Microcode\n");
425 for (i = 0; i < 256; i++) {
426 WREG32(RADEON_CP_ME_RAM_DATAH, R100_cp_microcode[i][1]);
427 WREG32(RADEON_CP_ME_RAM_DATAL, R100_cp_microcode[i][0]);
428 }
429 } else if ((rdev->family == CHIP_R200) ||
430 (rdev->family == CHIP_RV250) ||
431 (rdev->family == CHIP_RV280) ||
432 (rdev->family == CHIP_RS300)) {
433 DRM_INFO("Loading R200 Microcode\n");
434 for (i = 0; i < 256; i++) {
435 WREG32(RADEON_CP_ME_RAM_DATAH, R200_cp_microcode[i][1]);
436 WREG32(RADEON_CP_ME_RAM_DATAL, R200_cp_microcode[i][0]);
437 }
438 } else if ((rdev->family == CHIP_R300) ||
439 (rdev->family == CHIP_R350) ||
440 (rdev->family == CHIP_RV350) ||
441 (rdev->family == CHIP_RV380) ||
442 (rdev->family == CHIP_RS400) ||
443 (rdev->family == CHIP_RS480)) {
444 DRM_INFO("Loading R300 Microcode\n");
445 for (i = 0; i < 256; i++) {
446 WREG32(RADEON_CP_ME_RAM_DATAH, R300_cp_microcode[i][1]);
447 WREG32(RADEON_CP_ME_RAM_DATAL, R300_cp_microcode[i][0]);
448 }
449 } else if ((rdev->family == CHIP_R420) ||
450 (rdev->family == CHIP_R423) ||
451 (rdev->family == CHIP_RV410)) {
452 DRM_INFO("Loading R400 Microcode\n");
453 for (i = 0; i < 256; i++) {
454 WREG32(RADEON_CP_ME_RAM_DATAH, R420_cp_microcode[i][1]);
455 WREG32(RADEON_CP_ME_RAM_DATAL, R420_cp_microcode[i][0]);
456 }
457 } else if ((rdev->family == CHIP_RS690) ||
458 (rdev->family == CHIP_RS740)) {
459 DRM_INFO("Loading RS690/RS740 Microcode\n");
460 for (i = 0; i < 256; i++) {
461 WREG32(RADEON_CP_ME_RAM_DATAH, RS690_cp_microcode[i][1]);
462 WREG32(RADEON_CP_ME_RAM_DATAL, RS690_cp_microcode[i][0]);
463 }
464 } else if (rdev->family == CHIP_RS600) {
465 DRM_INFO("Loading RS600 Microcode\n");
466 for (i = 0; i < 256; i++) {
467 WREG32(RADEON_CP_ME_RAM_DATAH, RS600_cp_microcode[i][1]);
468 WREG32(RADEON_CP_ME_RAM_DATAL, RS600_cp_microcode[i][0]);
469 }
470 } else if ((rdev->family == CHIP_RV515) ||
471 (rdev->family == CHIP_R520) ||
472 (rdev->family == CHIP_RV530) ||
473 (rdev->family == CHIP_R580) ||
474 (rdev->family == CHIP_RV560) ||
475 (rdev->family == CHIP_RV570)) {
476 DRM_INFO("Loading R500 Microcode\n");
477 for (i = 0; i < 256; i++) {
478 WREG32(RADEON_CP_ME_RAM_DATAH, R520_cp_microcode[i][1]);
479 WREG32(RADEON_CP_ME_RAM_DATAL, R520_cp_microcode[i][0]);
480 }
481 }
482}
483
484int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
485{
486 unsigned rb_bufsz;
487 unsigned rb_blksz;
488 unsigned max_fetch;
489 unsigned pre_write_timer;
490 unsigned pre_write_limit;
491 unsigned indirect2_start;
492 unsigned indirect1_start;
493 uint32_t tmp;
494 int r;
495
496 if (r100_debugfs_cp_init(rdev)) {
497 DRM_ERROR("Failed to register debugfs file for CP !\n");
498 }
499 /* Reset CP */
500 tmp = RREG32(RADEON_CP_CSQ_STAT);
501 if ((tmp & (1 << 31))) {
502 DRM_INFO("radeon: cp busy (0x%08X) resetting\n", tmp);
503 WREG32(RADEON_CP_CSQ_MODE, 0);
504 WREG32(RADEON_CP_CSQ_CNTL, 0);
505 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
506 tmp = RREG32(RADEON_RBBM_SOFT_RESET);
507 mdelay(2);
508 WREG32(RADEON_RBBM_SOFT_RESET, 0);
509 tmp = RREG32(RADEON_RBBM_SOFT_RESET);
510 mdelay(2);
511 tmp = RREG32(RADEON_CP_CSQ_STAT);
512 if ((tmp & (1 << 31))) {
513 DRM_INFO("radeon: cp reset failed (0x%08X)\n", tmp);
514 }
515 } else {
516 DRM_INFO("radeon: cp idle (0x%08X)\n", tmp);
517 }
518 /* Align ring size */
519 rb_bufsz = drm_order(ring_size / 8);
520 ring_size = (1 << (rb_bufsz + 1)) * 4;
521 r100_cp_load_microcode(rdev);
522 r = radeon_ring_init(rdev, ring_size);
523 if (r) {
524 return r;
525 }
526 /* Each time the cp read 1024 bytes (16 dword/quadword) update
527 * the rptr copy in system ram */
528 rb_blksz = 9;
529 /* cp will read 128bytes at a time (4 dwords) */
530 max_fetch = 1;
531 rdev->cp.align_mask = 16 - 1;
532 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
533 pre_write_timer = 64;
534 /* Force CP_RB_WPTR write if written more than one time before the
535 * delay expire
536 */
537 pre_write_limit = 0;
538 /* Setup the cp cache like this (cache size is 96 dwords) :
539 * RING 0 to 15
540 * INDIRECT1 16 to 79
541 * INDIRECT2 80 to 95
542 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
543 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
544 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
545 * Idea being that most of the gpu cmd will be through indirect1 buffer
546 * so it gets the bigger cache.
547 */
548 indirect2_start = 80;
549 indirect1_start = 16;
550 /* cp setup */
551 WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
552 WREG32(RADEON_CP_RB_CNTL,
4e484e7d
MD		 553#ifdef __BIG_ENDIAN
554 RADEON_BUF_SWAP_32BIT |
555#endif
771fe6b9
JG		 556 REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
557 REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
558 REG_SET(RADEON_MAX_FETCH, max_fetch) |
559 RADEON_RB_NO_UPDATE);
560 /* Set ring address */
561 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
562 WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
563 /* Force read & write ptr to 0 */
564 tmp = RREG32(RADEON_CP_RB_CNTL);
565 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
566 WREG32(RADEON_CP_RB_RPTR_WR, 0);
567 WREG32(RADEON_CP_RB_WPTR, 0);
568 WREG32(RADEON_CP_RB_CNTL, tmp);
569 udelay(10);
570 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
571 rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR);
572 /* Set cp mode to bus mastering & enable cp*/
573 WREG32(RADEON_CP_CSQ_MODE,
574 REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
575 REG_SET(RADEON_INDIRECT1_START, indirect1_start));
576 WREG32(0x718, 0);
577 WREG32(0x744, 0x00004D4D);
578 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
579 radeon_ring_start(rdev);
580 r = radeon_ring_test(rdev);
581 if (r) {
582 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
583 return r;
584 }
585 rdev->cp.ready = true;
586 return 0;
587}
588
589void r100_cp_fini(struct radeon_device *rdev)
590{
591 /* Disable ring */
592 rdev->cp.ready = false;
593 WREG32(RADEON_CP_CSQ_CNTL, 0);
594 radeon_ring_fini(rdev);
595 DRM_INFO("radeon: cp finalized\n");
596}
597
598void r100_cp_disable(struct radeon_device *rdev)
599{
600 /* Disable ring */
601 rdev->cp.ready = false;
602 WREG32(RADEON_CP_CSQ_MODE, 0);
603 WREG32(RADEON_CP_CSQ_CNTL, 0);
604 if (r100_gui_wait_for_idle(rdev)) {
605 printk(KERN_WARNING "Failed to wait GUI idle while "
606 "programming pipes. Bad things might happen.\n");
607 }
608}
609
610int r100_cp_reset(struct radeon_device *rdev)
611{
612 uint32_t tmp;
613 bool reinit_cp;
614 int i;
615
616 reinit_cp = rdev->cp.ready;
617 rdev->cp.ready = false;
618 WREG32(RADEON_CP_CSQ_MODE, 0);
619 WREG32(RADEON_CP_CSQ_CNTL, 0);
620 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
621 (void)RREG32(RADEON_RBBM_SOFT_RESET);
622 udelay(200);
623 WREG32(RADEON_RBBM_SOFT_RESET, 0);
624 /* Wait to prevent race in RBBM_STATUS */
625 mdelay(1);
626 for (i = 0; i < rdev->usec_timeout; i++) {
627 tmp = RREG32(RADEON_RBBM_STATUS);
628 if (!(tmp & (1 << 16))) {
629 DRM_INFO("CP reset succeed (RBBM_STATUS=0x%08X)\n",
630 tmp);
631 if (reinit_cp) {
632 return r100_cp_init(rdev, rdev->cp.ring_size);
633 }
634 return 0;
635 }
636 DRM_UDELAY(1);
637 }
638 tmp = RREG32(RADEON_RBBM_STATUS);
639 DRM_ERROR("Failed to reset CP (RBBM_STATUS=0x%08X)!\n", tmp);
640 return -1;
641}
642
643
644/*
645 * CS functions
646 */
647int r100_cs_parse_packet0(struct radeon_cs_parser *p,
648 struct radeon_cs_packet *pkt,
068a117c 649 const unsigned *auth, unsigned n,
771fe6b9
JG		 650 radeon_packet0_check_t check)
651{
652 unsigned reg;
653 unsigned i, j, m;
654 unsigned idx;
655 int r;
656
657 idx = pkt->idx + 1;
658 reg = pkt->reg;
068a117c
JG		 659 /* Check that register fall into register range
660 * determined by the number of entry (n) in the
661 * safe register bitmap.
662 */
771fe6b9
JG		 663 if (pkt->one_reg_wr) {
664 if ((reg >> 7) > n) {
665 return -EINVAL;
666 }
667 } else {
668 if (((reg + (pkt->count << 2)) >> 7) > n) {
669 return -EINVAL;
670 }
671 }
672 for (i = 0; i <= pkt->count; i++, idx++) {
673 j = (reg >> 7);
674 m = 1 << ((reg >> 2) & 31);
675 if (auth[j] & m) {
676 r = check(p, pkt, idx, reg);
677 if (r) {
678 return r;
679 }
680 }
681 if (pkt->one_reg_wr) {
682 if (!(auth[j] & m)) {
683 break;
684 }
685 } else {
686 reg += 4;
687 }
688 }
689 return 0;
690}
691
771fe6b9
JG		 692void r100_cs_dump_packet(struct radeon_cs_parser *p,
693 struct radeon_cs_packet *pkt)
694{
695 struct radeon_cs_chunk *ib_chunk;
696 volatile uint32_t *ib;
697 unsigned i;
698 unsigned idx;
699
700 ib = p->ib->ptr;
701 ib_chunk = &p->chunks[p->chunk_ib_idx];
702 idx = pkt->idx;
703 for (i = 0; i <= (pkt->count + 1); i++, idx++) {
704 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
705 }
706}
707
708/**
709 * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
710 * @parser: parser structure holding parsing context.
711 * @pkt: where to store packet informations
712 *
713 * Assume that chunk_ib_index is properly set. Will return -EINVAL
714 * if packet is bigger than remaining ib size. or if packets is unknown.
715 **/
716int r100_cs_packet_parse(struct radeon_cs_parser *p,
717 struct radeon_cs_packet *pkt,
718 unsigned idx)
719{
720 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
721 uint32_t header = ib_chunk->kdata[idx];
722
723 if (idx >= ib_chunk->length_dw) {
724 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
725 idx, ib_chunk->length_dw);
726 return -EINVAL;
727 }
728 pkt->idx = idx;
729 pkt->type = CP_PACKET_GET_TYPE(header);
730 pkt->count = CP_PACKET_GET_COUNT(header);
731 switch (pkt->type) {
732 case PACKET_TYPE0:
733 pkt->reg = CP_PACKET0_GET_REG(header);
734 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
735 break;
736 case PACKET_TYPE3:
737 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
738 break;
739 case PACKET_TYPE2:
740 pkt->count = -1;
741 break;
742 default:
743 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
744 return -EINVAL;
745 }
746 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
747 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
748 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
749 return -EINVAL;
750 }
751 return 0;
752}
753
531369e6
DA		 754/**
755 * r100_cs_packet_next_vline() - parse userspace VLINE packet
756 * @parser: parser structure holding parsing context.
757 *
758 * Userspace sends a special sequence for VLINE waits.
759 * PACKET0 - VLINE_START_END + value
760 * PACKET0 - WAIT_UNTIL +_value
761 * RELOC (P3) - crtc_id in reloc.
762 *
763 * This function parses this and relocates the VLINE START END
764 * and WAIT UNTIL packets to the correct crtc.
765 * It also detects a switched off crtc and nulls out the
766 * wait in that case.
767 */
768int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
769{
770 struct radeon_cs_chunk *ib_chunk;
771 struct drm_mode_object *obj;
772 struct drm_crtc *crtc;
773 struct radeon_crtc *radeon_crtc;
774 struct radeon_cs_packet p3reloc, waitreloc;
775 int crtc_id;
776 int r;
777 uint32_t header, h_idx, reg;
778
779 ib_chunk = &p->chunks[p->chunk_ib_idx];
780
781 /* parse the wait until */
782 r = r100_cs_packet_parse(p, &waitreloc, p->idx);
783 if (r)
784 return r;
785
786 /* check its a wait until and only 1 count */
787 if (waitreloc.reg != RADEON_WAIT_UNTIL ||
788 waitreloc.count != 0) {
789 DRM_ERROR("vline wait had illegal wait until segment\n");
790 r = -EINVAL;
791 return r;
792 }
793
794 if (ib_chunk->kdata[waitreloc.idx + 1] != RADEON_WAIT_CRTC_VLINE) {
795 DRM_ERROR("vline wait had illegal wait until\n");
796 r = -EINVAL;
797 return r;
798 }
799
800 /* jump over the NOP */
801 r = r100_cs_packet_parse(p, &p3reloc, p->idx);
802 if (r)
803 return r;
804
805 h_idx = p->idx - 2;
806 p->idx += waitreloc.count;
807 p->idx += p3reloc.count;
808
809 header = ib_chunk->kdata[h_idx];
810 crtc_id = ib_chunk->kdata[h_idx + 5];
811 reg = ib_chunk->kdata[h_idx] >> 2;
812 mutex_lock(&p->rdev->ddev->mode_config.mutex);
813 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
814 if (!obj) {
815 DRM_ERROR("cannot find crtc %d\n", crtc_id);
816 r = -EINVAL;
817 goto out;
818 }
819 crtc = obj_to_crtc(obj);
820 radeon_crtc = to_radeon_crtc(crtc);
821 crtc_id = radeon_crtc->crtc_id;
822
823 if (!crtc->enabled) {
824 /* if the CRTC isn't enabled - we need to nop out the wait until */
825 ib_chunk->kdata[h_idx + 2] = PACKET2(0);
826 ib_chunk->kdata[h_idx + 3] = PACKET2(0);
827 } else if (crtc_id == 1) {
828 switch (reg) {
829 case AVIVO_D1MODE_VLINE_START_END:
830 header &= R300_CP_PACKET0_REG_MASK;
831 header |= AVIVO_D2MODE_VLINE_START_END >> 2;
832 break;
833 case RADEON_CRTC_GUI_TRIG_VLINE:
834 header &= R300_CP_PACKET0_REG_MASK;
835 header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
836 break;
837 default:
838 DRM_ERROR("unknown crtc reloc\n");
839 r = -EINVAL;
840 goto out;
841 }
842 ib_chunk->kdata[h_idx] = header;
843 ib_chunk->kdata[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
844 }
845out:
846 mutex_unlock(&p->rdev->ddev->mode_config.mutex);
847 return r;
848}
849
771fe6b9
JG		 850/**
851 * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
852 * @parser: parser structure holding parsing context.
853 * @data: pointer to relocation data
854 * @offset_start: starting offset
855 * @offset_mask: offset mask (to align start offset on)
856 * @reloc: reloc informations
857 *
858 * Check next packet is relocation packet3, do bo validation and compute
859 * GPU offset using the provided start.
860 **/
861int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
862 struct radeon_cs_reloc **cs_reloc)
863{
864 struct radeon_cs_chunk *ib_chunk;
865 struct radeon_cs_chunk *relocs_chunk;
866 struct radeon_cs_packet p3reloc;
867 unsigned idx;
868 int r;
869
870 if (p->chunk_relocs_idx == -1) {
871 DRM_ERROR("No relocation chunk !\n");
872 return -EINVAL;
873 }
874 *cs_reloc = NULL;
875 ib_chunk = &p->chunks[p->chunk_ib_idx];
876 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
877 r = r100_cs_packet_parse(p, &p3reloc, p->idx);
878 if (r) {
879 return r;
880 }
881 p->idx += p3reloc.count + 2;
882 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
883 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
884 p3reloc.idx);
885 r100_cs_dump_packet(p, &p3reloc);
886 return -EINVAL;
887 }
888 idx = ib_chunk->kdata[p3reloc.idx + 1];
889 if (idx >= relocs_chunk->length_dw) {
890 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
891 idx, relocs_chunk->length_dw);
892 r100_cs_dump_packet(p, &p3reloc);
893 return -EINVAL;
894 }
895 /* FIXME: we assume reloc size is 4 dwords */
896 *cs_reloc = p->relocs_ptr[(idx / 4)];
897 return 0;
898}
899
900static int r100_packet0_check(struct radeon_cs_parser *p,
901 struct radeon_cs_packet *pkt)
902{
903 struct radeon_cs_chunk *ib_chunk;
904 struct radeon_cs_reloc *reloc;
905 volatile uint32_t *ib;
906 uint32_t tmp;
907 unsigned reg;
908 unsigned i;
909 unsigned idx;
910 bool onereg;
911 int r;
e024e110 912 u32 tile_flags = 0;
771fe6b9
JG		 913
914 ib = p->ib->ptr;
915 ib_chunk = &p->chunks[p->chunk_ib_idx];
916 idx = pkt->idx + 1;
917 reg = pkt->reg;
918 onereg = false;
919 if (CP_PACKET0_GET_ONE_REG_WR(ib_chunk->kdata[pkt->idx])) {
920 onereg = true;
921 }
922 for (i = 0; i <= pkt->count; i++, idx++, reg += 4) {
923 switch (reg) {
531369e6
DA		 924 case RADEON_CRTC_GUI_TRIG_VLINE:
925 r = r100_cs_packet_parse_vline(p);
926 if (r) {
927 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
928 idx, reg);
929 r100_cs_dump_packet(p, pkt);
930 return r;
931 }
932 break;
771fe6b9
JG		 933 /* FIXME: only allow PACKET3 blit? easier to check for out of
934 * range access */
935 case RADEON_DST_PITCH_OFFSET:
936 case RADEON_SRC_PITCH_OFFSET:
937 r = r100_cs_packet_next_reloc(p, &reloc);
938 if (r) {
939 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
940 idx, reg);
941 r100_cs_dump_packet(p, pkt);
942 return r;
943 }
944 tmp = ib_chunk->kdata[idx] & 0x003fffff;
945 tmp += (((u32)reloc->lobj.gpu_offset) >> 10);
e024e110
DA		 946
947 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
948 tile_flags |= RADEON_DST_TILE_MACRO;
949 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
950 if (reg == RADEON_SRC_PITCH_OFFSET) {
951 DRM_ERROR("Cannot src blit from microtiled surface\n");
952 r100_cs_dump_packet(p, pkt);
953 return -EINVAL;
954 }
955 tile_flags |= RADEON_DST_TILE_MICRO;
956 }
957
958 tmp |= tile_flags;
959 ib[idx] = (ib_chunk->kdata[idx] & 0x3fc00000) | tmp;
771fe6b9
JG		 960 break;
961 case RADEON_RB3D_DEPTHOFFSET:
962 case RADEON_RB3D_COLOROFFSET:
963 case R300_RB3D_COLOROFFSET0:
964 case R300_ZB_DEPTHOFFSET:
965 case R200_PP_TXOFFSET_0:
966 case R200_PP_TXOFFSET_1:
967 case R200_PP_TXOFFSET_2:
968 case R200_PP_TXOFFSET_3:
969 case R200_PP_TXOFFSET_4:
970 case R200_PP_TXOFFSET_5:
971 case RADEON_PP_TXOFFSET_0:
972 case RADEON_PP_TXOFFSET_1:
973 case RADEON_PP_TXOFFSET_2:
974 case R300_TX_OFFSET_0:
975 case R300_TX_OFFSET_0+4:
976 case R300_TX_OFFSET_0+8:
977 case R300_TX_OFFSET_0+12:
978 case R300_TX_OFFSET_0+16:
979 case R300_TX_OFFSET_0+20:
980 case R300_TX_OFFSET_0+24:
981 case R300_TX_OFFSET_0+28:
982 case R300_TX_OFFSET_0+32:
983 case R300_TX_OFFSET_0+36:
984 case R300_TX_OFFSET_0+40:
985 case R300_TX_OFFSET_0+44:
986 case R300_TX_OFFSET_0+48:
987 case R300_TX_OFFSET_0+52:
988 case R300_TX_OFFSET_0+56:
989 case R300_TX_OFFSET_0+60:
b995e433
DA		 990 /* rn50 has no 3D engine so fail on any 3d setup */
991 if (ASIC_IS_RN50(p->rdev)) {
992 DRM_ERROR("attempt to use RN50 3D engine failed\n");
993 return -EINVAL;
994 }
771fe6b9
JG		 995 r = r100_cs_packet_next_reloc(p, &reloc);
996 if (r) {
997 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
998 idx, reg);
999 r100_cs_dump_packet(p, pkt);
1000 return r;
1001 }
1002 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
1003 break;
e024e110
DA		 1004 case R300_RB3D_COLORPITCH0:
1005 case RADEON_RB3D_COLORPITCH:
1006 r = r100_cs_packet_next_reloc(p, &reloc);
1007 if (r) {
1008 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1009 idx, reg);
1010 r100_cs_dump_packet(p, pkt);
1011 return r;
1012 }
1013
1014 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1015 tile_flags |= RADEON_COLOR_TILE_ENABLE;
1016 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1017 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1018
1019 tmp = ib_chunk->kdata[idx] & ~(0x7 << 16);
1020 tmp |= tile_flags;
1021 ib[idx] = tmp;
1022 break;
771fe6b9
JG		 1023 default:
1024 /* FIXME: we don't want to allow anyothers packet */
1025 break;
1026 }
1027 if (onereg) {
1028 /* FIXME: forbid onereg write to register on relocate */
1029 break;
1030 }
1031 }
1032 return 0;
1033}
1034
068a117c
JG		 1035int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1036 struct radeon_cs_packet *pkt,
1037 struct radeon_object *robj)
1038{
1039 struct radeon_cs_chunk *ib_chunk;
1040 unsigned idx;
1041
1042 ib_chunk = &p->chunks[p->chunk_ib_idx];
1043 idx = pkt->idx + 1;
1044 if ((ib_chunk->kdata[idx+2] + 1) > radeon_object_size(robj)) {
1045 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1046 "(need %u have %lu) !\n",
1047 ib_chunk->kdata[idx+2] + 1,
1048 radeon_object_size(robj));
1049 return -EINVAL;
1050 }
1051 return 0;
1052}
1053
771fe6b9
JG		 1054static int r100_packet3_check(struct radeon_cs_parser *p,
1055 struct radeon_cs_packet *pkt)
1056{
1057 struct radeon_cs_chunk *ib_chunk;
1058 struct radeon_cs_reloc *reloc;
1059 unsigned idx;
1060 unsigned i, c;
1061 volatile uint32_t *ib;
1062 int r;
1063
1064 ib = p->ib->ptr;
1065 ib_chunk = &p->chunks[p->chunk_ib_idx];
1066 idx = pkt->idx + 1;
1067 switch (pkt->opcode) {
1068 case PACKET3_3D_LOAD_VBPNTR:
1069 c = ib_chunk->kdata[idx++];
1070 for (i = 0; i < (c - 1); i += 2, idx += 3) {
1071 r = r100_cs_packet_next_reloc(p, &reloc);
1072 if (r) {
1073 DRM_ERROR("No reloc for packet3 %d\n",
1074 pkt->opcode);
1075 r100_cs_dump_packet(p, pkt);
1076 return r;
1077 }
1078 ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset);
1079 r = r100_cs_packet_next_reloc(p, &reloc);
1080 if (r) {
1081 DRM_ERROR("No reloc for packet3 %d\n",
1082 pkt->opcode);
1083 r100_cs_dump_packet(p, pkt);
1084 return r;
1085 }
1086 ib[idx+2] = ib_chunk->kdata[idx+2] + ((u32)reloc->lobj.gpu_offset);
1087 }
1088 if (c & 1) {
1089 r = r100_cs_packet_next_reloc(p, &reloc);
1090 if (r) {
1091 DRM_ERROR("No reloc for packet3 %d\n",
1092 pkt->opcode);
1093 r100_cs_dump_packet(p, pkt);
1094 return r;
1095 }
1096 ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset);
1097 }
1098 break;
1099 case PACKET3_INDX_BUFFER:
1100 r = r100_cs_packet_next_reloc(p, &reloc);
1101 if (r) {
1102 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1103 r100_cs_dump_packet(p, pkt);
1104 return r;
1105 }
1106 ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset);
068a117c
JG		 1107 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1108 if (r) {
1109 return r;
1110 }
771fe6b9
JG		 1111 break;
1112 case 0x23:
1113 /* FIXME: cleanup */
1114 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1115 r = r100_cs_packet_next_reloc(p, &reloc);
1116 if (r) {
1117 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1118 r100_cs_dump_packet(p, pkt);
1119 return r;
1120 }
1121 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
1122 break;
1123 case PACKET3_3D_DRAW_IMMD:
1124 /* triggers drawing using in-packet vertex data */
1125 case PACKET3_3D_DRAW_IMMD_2:
1126 /* triggers drawing using in-packet vertex data */
1127 case PACKET3_3D_DRAW_VBUF_2:
1128 /* triggers drawing of vertex buffers setup elsewhere */
1129 case PACKET3_3D_DRAW_INDX_2:
1130 /* triggers drawing using indices to vertex buffer */
1131 case PACKET3_3D_DRAW_VBUF:
1132 /* triggers drawing of vertex buffers setup elsewhere */
1133 case PACKET3_3D_DRAW_INDX:
1134 /* triggers drawing using indices to vertex buffer */
1135 case PACKET3_NOP:
1136 break;
1137 default:
1138 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1139 return -EINVAL;
1140 }
1141 return 0;
1142}
1143
1144int r100_cs_parse(struct radeon_cs_parser *p)
1145{
1146 struct radeon_cs_packet pkt;
1147 int r;
1148
1149 do {
1150 r = r100_cs_packet_parse(p, &pkt, p->idx);
1151 if (r) {
1152 return r;
1153 }
1154 p->idx += pkt.count + 2;
1155 switch (pkt.type) {
068a117c
JG		 1156 case PACKET_TYPE0:
1157 r = r100_packet0_check(p, &pkt);
1158 break;
1159 case PACKET_TYPE2:
1160 break;
1161 case PACKET_TYPE3:
1162 r = r100_packet3_check(p, &pkt);
1163 break;
1164 default:
1165 DRM_ERROR("Unknown packet type %d !\n",
1166 pkt.type);
1167 return -EINVAL;
771fe6b9
JG		 1168 }
1169 if (r) {
1170 return r;
1171 }
1172 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1173 return 0;
1174}
1175
1176
1177/*
1178 * Global GPU functions
1179 */
1180void r100_errata(struct radeon_device *rdev)
1181{
1182 rdev->pll_errata = 0;
1183
1184 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
1185 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
1186 }
1187
1188 if (rdev->family == CHIP_RV100 ||
1189 rdev->family == CHIP_RS100 ||
1190 rdev->family == CHIP_RS200) {
1191 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
1192 }
1193}
1194
1195/* Wait for vertical sync on primary CRTC */
1196void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
1197{
1198 uint32_t crtc_gen_cntl, tmp;
1199 int i;
1200
1201 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
1202 if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
1203 !(crtc_gen_cntl & RADEON_CRTC_EN)) {
1204 return;
1205 }
1206 /* Clear the CRTC_VBLANK_SAVE bit */
1207 WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
1208 for (i = 0; i < rdev->usec_timeout; i++) {
1209 tmp = RREG32(RADEON_CRTC_STATUS);
1210 if (tmp & RADEON_CRTC_VBLANK_SAVE) {
1211 return;
1212 }
1213 DRM_UDELAY(1);
1214 }
1215}
1216
1217/* Wait for vertical sync on secondary CRTC */
1218void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
1219{
1220 uint32_t crtc2_gen_cntl, tmp;
1221 int i;
1222
1223 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1224 if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
1225 !(crtc2_gen_cntl & RADEON_CRTC2_EN))
1226 return;
1227
1228 /* Clear the CRTC_VBLANK_SAVE bit */
1229 WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
1230 for (i = 0; i < rdev->usec_timeout; i++) {
1231 tmp = RREG32(RADEON_CRTC2_STATUS);
1232 if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
1233 return;
1234 }
1235 DRM_UDELAY(1);
1236 }
1237}
1238
1239int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
1240{
1241 unsigned i;
1242 uint32_t tmp;
1243
1244 for (i = 0; i < rdev->usec_timeout; i++) {
1245 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
1246 if (tmp >= n) {
1247 return 0;
1248 }
1249 DRM_UDELAY(1);
1250 }
1251 return -1;
1252}
1253
1254int r100_gui_wait_for_idle(struct radeon_device *rdev)
1255{
1256 unsigned i;
1257 uint32_t tmp;
1258
1259 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
1260 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
1261 " Bad things might happen.\n");
1262 }
1263 for (i = 0; i < rdev->usec_timeout; i++) {
1264 tmp = RREG32(RADEON_RBBM_STATUS);
1265 if (!(tmp & (1 << 31))) {
1266 return 0;
1267 }
1268 DRM_UDELAY(1);
1269 }
1270 return -1;
1271}
1272
1273int r100_mc_wait_for_idle(struct radeon_device *rdev)
1274{
1275 unsigned i;
1276 uint32_t tmp;
1277
1278 for (i = 0; i < rdev->usec_timeout; i++) {
1279 /* read MC_STATUS */
1280 tmp = RREG32(0x0150);
1281 if (tmp & (1 << 2)) {
1282 return 0;
1283 }
1284 DRM_UDELAY(1);
1285 }
1286 return -1;
1287}
1288
1289void r100_gpu_init(struct radeon_device *rdev)
1290{
1291 /* TODO: anythings to do here ? pipes ? */
1292 r100_hdp_reset(rdev);
1293}
1294
1295void r100_hdp_reset(struct radeon_device *rdev)
1296{
1297 uint32_t tmp;
1298
1299 tmp = RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL;
1300 tmp |= (7 << 28);
1301 WREG32(RADEON_HOST_PATH_CNTL, tmp | RADEON_HDP_SOFT_RESET | RADEON_HDP_READ_BUFFER_INVALIDATE);
1302 (void)RREG32(RADEON_HOST_PATH_CNTL);
1303 udelay(200);
1304 WREG32(RADEON_RBBM_SOFT_RESET, 0);
1305 WREG32(RADEON_HOST_PATH_CNTL, tmp);
1306 (void)RREG32(RADEON_HOST_PATH_CNTL);
1307}
1308
1309int r100_rb2d_reset(struct radeon_device *rdev)
1310{
1311 uint32_t tmp;
1312 int i;
1313
1314 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_E2);
1315 (void)RREG32(RADEON_RBBM_SOFT_RESET);
1316 udelay(200);
1317 WREG32(RADEON_RBBM_SOFT_RESET, 0);
1318 /* Wait to prevent race in RBBM_STATUS */
1319 mdelay(1);
1320 for (i = 0; i < rdev->usec_timeout; i++) {
1321 tmp = RREG32(RADEON_RBBM_STATUS);
1322 if (!(tmp & (1 << 26))) {
1323 DRM_INFO("RB2D reset succeed (RBBM_STATUS=0x%08X)\n",
1324 tmp);
1325 return 0;
1326 }
1327 DRM_UDELAY(1);
1328 }
1329 tmp = RREG32(RADEON_RBBM_STATUS);
1330 DRM_ERROR("Failed to reset RB2D (RBBM_STATUS=0x%08X)!\n", tmp);
1331 return -1;
1332}
1333
1334int r100_gpu_reset(struct radeon_device *rdev)
1335{
1336 uint32_t status;
1337
1338 /* reset order likely matter */
1339 status = RREG32(RADEON_RBBM_STATUS);
1340 /* reset HDP */
1341 r100_hdp_reset(rdev);
1342 /* reset rb2d */
1343 if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
1344 r100_rb2d_reset(rdev);
1345 }
1346 /* TODO: reset 3D engine */
1347 /* reset CP */
1348 status = RREG32(RADEON_RBBM_STATUS);
1349 if (status & (1 << 16)) {
1350 r100_cp_reset(rdev);
1351 }
1352 /* Check if GPU is idle */
1353 status = RREG32(RADEON_RBBM_STATUS);
1354 if (status & (1 << 31)) {
1355 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
1356 return -1;
1357 }
1358 DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
1359 return 0;
1360}
1361
1362
1363/*
1364 * VRAM info
1365 */
1366static void r100_vram_get_type(struct radeon_device *rdev)
1367{
1368 uint32_t tmp;
1369
1370 rdev->mc.vram_is_ddr = false;
1371 if (rdev->flags & RADEON_IS_IGP)
1372 rdev->mc.vram_is_ddr = true;
1373 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
1374 rdev->mc.vram_is_ddr = true;
1375 if ((rdev->family == CHIP_RV100) ||
1376 (rdev->family == CHIP_RS100) ||
1377 (rdev->family == CHIP_RS200)) {
1378 tmp = RREG32(RADEON_MEM_CNTL);
1379 if (tmp & RV100_HALF_MODE) {
1380 rdev->mc.vram_width = 32;
1381 } else {
1382 rdev->mc.vram_width = 64;
1383 }
1384 if (rdev->flags & RADEON_SINGLE_CRTC) {
1385 rdev->mc.vram_width /= 4;
1386 rdev->mc.vram_is_ddr = true;
1387 }
1388 } else if (rdev->family <= CHIP_RV280) {
1389 tmp = RREG32(RADEON_MEM_CNTL);
1390 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
1391 rdev->mc.vram_width = 128;
1392 } else {
1393 rdev->mc.vram_width = 64;
1394 }
1395 } else {
1396 /* newer IGPs */
1397 rdev->mc.vram_width = 128;
1398 }
1399}
1400
2a0f8918 1401static u32 r100_get_accessible_vram(struct radeon_device *rdev)
771fe6b9 1402{
2a0f8918
DA		 1403 u32 aper_size;
1404 u8 byte;
1405
1406 aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
1407
1408 /* Set HDP_APER_CNTL only on cards that are known not to be broken,
1409 * that is has the 2nd generation multifunction PCI interface
1410 */
1411 if (rdev->family == CHIP_RV280 ||
1412 rdev->family >= CHIP_RV350) {
1413 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
1414 ~RADEON_HDP_APER_CNTL);
1415 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
1416 return aper_size * 2;
1417 }
1418
1419 /* Older cards have all sorts of funny issues to deal with. First
1420 * check if it's a multifunction card by reading the PCI config
1421 * header type... Limit those to one aperture size
1422 */
1423 pci_read_config_byte(rdev->pdev, 0xe, &byte);
1424 if (byte & 0x80) {
1425 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
1426 DRM_INFO("Limiting VRAM to one aperture\n");
1427 return aper_size;
1428 }
1429
1430 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
1431 * have set it up. We don't write this as it's broken on some ASICs but
1432 * we expect the BIOS to have done the right thing (might be too optimistic...)
1433 */
1434 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
1435 return aper_size * 2;
1436 return aper_size;
1437}
1438
1439void r100_vram_init_sizes(struct radeon_device *rdev)
1440{
1441 u64 config_aper_size;
1442 u32 accessible;
1443
1444 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
771fe6b9
JG		 1445
1446 if (rdev->flags & RADEON_IS_IGP) {
1447 uint32_t tom;
1448 /* read NB_TOM to get the amount of ram stolen for the GPU */
1449 tom = RREG32(RADEON_NB_TOM);
1450 rdev->mc.vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
3e43d821
DA		 1451 /* for IGPs we need to keep VRAM where it was put by the BIOS */
1452 rdev->mc.vram_location = (tom & 0xffff) << 16;
771fe6b9
JG		 1453 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.vram_size);
1454 } else {
1455 rdev->mc.vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
1456 /* Some production boards of m6 will report 0
1457 * if it's 8 MB
1458 */
1459 if (rdev->mc.vram_size == 0) {
1460 rdev->mc.vram_size = 8192 * 1024;
1461 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.vram_size);
1462 }
3e43d821
DA		 1463 /* let driver place VRAM */
1464 rdev->mc.vram_location = 0xFFFFFFFFUL;
2a0f8918
DA		 1465 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
1466 * Novell bug 204882 + along with lots of ubuntu ones */
1467 if (config_aper_size > rdev->mc.vram_size)
1468 rdev->mc.vram_size = config_aper_size;
771fe6b9
JG		 1469 }
1470
2a0f8918
DA		 1471 /* work out accessible VRAM */
1472 accessible = r100_get_accessible_vram(rdev);
1473
771fe6b9
JG		 1474 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
1475 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
2a0f8918
DA		 1476
1477 if (accessible > rdev->mc.aper_size)
1478 accessible = rdev->mc.aper_size;
1479
1480 if (rdev->mc.vram_size > rdev->mc.aper_size)
1481 rdev->mc.vram_size = rdev->mc.aper_size;
1482}
1483
1484void r100_vram_info(struct radeon_device *rdev)
1485{
1486 r100_vram_get_type(rdev);
1487
1488 r100_vram_init_sizes(rdev);
771fe6b9
JG		 1489}
1490
1491
1492/*
1493 * Indirect registers accessor
1494 */
1495void r100_pll_errata_after_index(struct radeon_device *rdev)
1496{
1497 if (!(rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS)) {
1498 return;
1499 }
1500 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
1501 (void)RREG32(RADEON_CRTC_GEN_CNTL);
1502}
1503
1504static void r100_pll_errata_after_data(struct radeon_device *rdev)
1505{
1506 /* This workarounds is necessary on RV100, RS100 and RS200 chips
1507 * or the chip could hang on a subsequent access
1508 */
1509 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
1510 udelay(5000);
1511 }
1512
1513 /* This function is required to workaround a hardware bug in some (all?)
1514 * revisions of the R300. This workaround should be called after every
1515 * CLOCK_CNTL_INDEX register access. If not, register reads afterward
1516 * may not be correct.
1517 */
1518 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
1519 uint32_t save, tmp;
1520
1521 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
1522 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
1523 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
1524 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
1525 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
1526 }
1527}
1528
1529uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
1530{
1531 uint32_t data;
1532
1533 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
1534 r100_pll_errata_after_index(rdev);
1535 data = RREG32(RADEON_CLOCK_CNTL_DATA);
1536 r100_pll_errata_after_data(rdev);
1537 return data;
1538}
1539
1540void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1541{
1542 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
1543 r100_pll_errata_after_index(rdev);
1544 WREG32(RADEON_CLOCK_CNTL_DATA, v);
1545 r100_pll_errata_after_data(rdev);
1546}
1547
1548uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
1549{
1550 if (reg < 0x10000)
1551 return readl(((void __iomem *)rdev->rmmio) + reg);
1552 else {
1553 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
1554 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
1555 }
1556}
1557
1558void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1559{
1560 if (reg < 0x10000)
1561 writel(v, ((void __iomem *)rdev->rmmio) + reg);
1562 else {
1563 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
1564 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
1565 }
1566}
1567
068a117c
JG		 1568int r100_init(struct radeon_device *rdev)
1569{
1570 return 0;
1571}
1572
771fe6b9
JG		 1573/*
1574 * Debugfs info
1575 */
1576#if defined(CONFIG_DEBUG_FS)
1577static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
1578{
1579 struct drm_info_node *node = (struct drm_info_node *) m->private;
1580 struct drm_device *dev = node->minor->dev;
1581 struct radeon_device *rdev = dev->dev_private;
1582 uint32_t reg, value;
1583 unsigned i;
1584
1585 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
1586 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
1587 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
1588 for (i = 0; i < 64; i++) {
1589 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
1590 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
1591 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
1592 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
1593 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
1594 }
1595 return 0;
1596}
1597
1598static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
1599{
1600 struct drm_info_node *node = (struct drm_info_node *) m->private;
1601 struct drm_device *dev = node->minor->dev;
1602 struct radeon_device *rdev = dev->dev_private;
1603 uint32_t rdp, wdp;
1604 unsigned count, i, j;
1605
1606 radeon_ring_free_size(rdev);
1607 rdp = RREG32(RADEON_CP_RB_RPTR);
1608 wdp = RREG32(RADEON_CP_RB_WPTR);
1609 count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
1610 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
1611 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
1612 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
1613 seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
1614 seq_printf(m, "%u dwords in ring\n", count);
1615 for (j = 0; j <= count; j++) {
1616 i = (rdp + j) & rdev->cp.ptr_mask;
1617 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
1618 }
1619 return 0;
1620}
1621
1622
1623static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
1624{
1625 struct drm_info_node *node = (struct drm_info_node *) m->private;
1626 struct drm_device *dev = node->minor->dev;
1627 struct radeon_device *rdev = dev->dev_private;
1628 uint32_t csq_stat, csq2_stat, tmp;
1629 unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
1630 unsigned i;
1631
1632 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
1633 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
1634 csq_stat = RREG32(RADEON_CP_CSQ_STAT);
1635 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
1636 r_rptr = (csq_stat >> 0) & 0x3ff;
1637 r_wptr = (csq_stat >> 10) & 0x3ff;
1638 ib1_rptr = (csq_stat >> 20) & 0x3ff;
1639 ib1_wptr = (csq2_stat >> 0) & 0x3ff;
1640 ib2_rptr = (csq2_stat >> 10) & 0x3ff;
1641 ib2_wptr = (csq2_stat >> 20) & 0x3ff;
1642 seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
1643 seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
1644 seq_printf(m, "Ring rptr %u\n", r_rptr);
1645 seq_printf(m, "Ring wptr %u\n", r_wptr);
1646 seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
1647 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
1648 seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
1649 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
1650 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
1651 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
1652 seq_printf(m, "Ring fifo:\n");
1653 for (i = 0; i < 256; i++) {
1654 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
1655 tmp = RREG32(RADEON_CP_CSQ_DATA);
1656 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
1657 }
1658 seq_printf(m, "Indirect1 fifo:\n");
1659 for (i = 256; i <= 512; i++) {
1660 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
1661 tmp = RREG32(RADEON_CP_CSQ_DATA);
1662 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
1663 }
1664 seq_printf(m, "Indirect2 fifo:\n");
1665 for (i = 640; i < ib1_wptr; i++) {
1666 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
1667 tmp = RREG32(RADEON_CP_CSQ_DATA);
1668 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
1669 }
1670 return 0;
1671}
1672
1673static int r100_debugfs_mc_info(struct seq_file *m, void *data)
1674{
1675 struct drm_info_node *node = (struct drm_info_node *) m->private;
1676 struct drm_device *dev = node->minor->dev;
1677 struct radeon_device *rdev = dev->dev_private;
1678 uint32_t tmp;
1679
1680 tmp = RREG32(RADEON_CONFIG_MEMSIZE);
1681 seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
1682 tmp = RREG32(RADEON_MC_FB_LOCATION);
1683 seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
1684 tmp = RREG32(RADEON_BUS_CNTL);
1685 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
1686 tmp = RREG32(RADEON_MC_AGP_LOCATION);
1687 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
1688 tmp = RREG32(RADEON_AGP_BASE);
1689 seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
1690 tmp = RREG32(RADEON_HOST_PATH_CNTL);
1691 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
1692 tmp = RREG32(0x01D0);
1693 seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
1694 tmp = RREG32(RADEON_AIC_LO_ADDR);
1695 seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
1696 tmp = RREG32(RADEON_AIC_HI_ADDR);
1697 seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
1698 tmp = RREG32(0x01E4);
1699 seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
1700 return 0;
1701}
1702
1703static struct drm_info_list r100_debugfs_rbbm_list[] = {
1704 {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
1705};
1706
1707static struct drm_info_list r100_debugfs_cp_list[] = {
1708 {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
1709 {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
1710};
1711
1712static struct drm_info_list r100_debugfs_mc_info_list[] = {
1713 {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
1714};
1715#endif
1716
1717int r100_debugfs_rbbm_init(struct radeon_device *rdev)
1718{
1719#if defined(CONFIG_DEBUG_FS)
1720 return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
1721#else
1722 return 0;
1723#endif
1724}
1725
1726int r100_debugfs_cp_init(struct radeon_device *rdev)
1727{
1728#if defined(CONFIG_DEBUG_FS)
1729 return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
1730#else
1731 return 0;
1732#endif
1733}
1734
1735int r100_debugfs_mc_info_init(struct radeon_device *rdev)
1736{
1737#if defined(CONFIG_DEBUG_FS)
1738 return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
1739#else
1740 return 0;
1741#endif
1742}
e024e110
DA		 1743
1744int r100_set_surface_reg(struct radeon_device *rdev, int reg,
1745 uint32_t tiling_flags, uint32_t pitch,
1746 uint32_t offset, uint32_t obj_size)
1747{
1748 int surf_index = reg * 16;
1749 int flags = 0;
1750
1751 /* r100/r200 divide by 16 */
1752 if (rdev->family < CHIP_R300)
1753 flags = pitch / 16;
1754 else
1755 flags = pitch / 8;
1756
1757 if (rdev->family <= CHIP_RS200) {
1758 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
1759 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
1760 flags |= RADEON_SURF_TILE_COLOR_BOTH;
1761 if (tiling_flags & RADEON_TILING_MACRO)
1762 flags |= RADEON_SURF_TILE_COLOR_MACRO;
1763 } else if (rdev->family <= CHIP_RV280) {
1764 if (tiling_flags & (RADEON_TILING_MACRO))
1765 flags |= R200_SURF_TILE_COLOR_MACRO;
1766 if (tiling_flags & RADEON_TILING_MICRO)
1767 flags |= R200_SURF_TILE_COLOR_MICRO;
1768 } else {
1769 if (tiling_flags & RADEON_TILING_MACRO)
1770 flags |= R300_SURF_TILE_MACRO;
1771 if (tiling_flags & RADEON_TILING_MICRO)
1772 flags |= R300_SURF_TILE_MICRO;
1773 }
1774
1775 DRM_DEBUG("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
1776 WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
1777 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
1778 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
1779 return 0;
1780}
1781
1782void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
1783{
1784 int surf_index = reg * 16;
1785 WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
1786}
kernel source for telekom puls (alcatel/mediatek)