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KVM: nVMX: Document 'nested' parameter
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
313a3dc7 29
18068523 30#include <linux/clocksource.h>
4d5c5d0f 31#include <linux/interrupt.h>
313a3dc7
CO		 32#include <linux/kvm.h>
33#include <linux/fs.h>
34#include <linux/vmalloc.h>
5fb76f9b 35#include <linux/module.h>
0de10343 36#include <linux/mman.h>
2bacc55c 37#include <linux/highmem.h>
19de40a8 38#include <linux/iommu.h>
62c476c7 39#include <linux/intel-iommu.h>
c8076604 40#include <linux/cpufreq.h>
18863bdd 41#include <linux/user-return-notifier.h>
a983fb23 42#include <linux/srcu.h>
5a0e3ad6 43#include <linux/slab.h>
ff9d07a0 44#include <linux/perf_event.h>
7bee342a 45#include <linux/uaccess.h>
af585b92 46#include <linux/hash.h>
aec51dc4 47#include <trace/events/kvm.h>
2ed152af 48
229456fc
MT		 49#define CREATE_TRACE_POINTS
50#include "trace.h"
043405e1 51
24f1e32c 52#include <asm/debugreg.h>
d825ed0a 53#include <asm/msr.h>
a5f61300 54#include <asm/desc.h>
0bed3b56 55#include <asm/mtrr.h>
890ca9ae 56#include <asm/mce.h>
7cf30855 57#include <asm/i387.h>
98918833 58#include <asm/xcr.h>
1d5f066e 59#include <asm/pvclock.h>
217fc9cf 60#include <asm/div64.h>
043405e1 61
313a3dc7 62#define MAX_IO_MSRS 256
890ca9ae 63#define KVM_MAX_MCE_BANKS 32
5854dbca 64#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 65
0f65dd70
AK		 66#define emul_to_vcpu(ctxt) \
67 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
68
50a37eb4
JR		 69/* EFER defaults:
70 * - enable syscall per default because its emulated by KVM
71 * - enable LME and LMA per default on 64 bit KVM
72 */
73#ifdef CONFIG_X86_64
1260edbe
LJ		 74static
75u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 76#else
1260edbe 77static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 78#endif
313a3dc7 79
ba1389b7
AK		 80#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
81#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 82
cb142eb7 83static void update_cr8_intercept(struct kvm_vcpu *vcpu);
674eea0f
AK		 84static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
85 struct kvm_cpuid_entry2 __user *entries);
86
97896d04 87struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 88EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 89
ed85c068
AP		 90int ignore_msrs = 0;
91module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
92
92a1f12d
JR		 93bool kvm_has_tsc_control;
94EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
95u32 kvm_max_guest_tsc_khz;
96EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
97
18863bdd
AK		 98#define KVM_NR_SHARED_MSRS 16
99
100struct kvm_shared_msrs_global {
101 int nr;
2bf78fa7 102 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 103};
104
105struct kvm_shared_msrs {
106 struct user_return_notifier urn;
107 bool registered;
2bf78fa7
SY		 108 struct kvm_shared_msr_values {
109 u64 host;
110 u64 curr;
111 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 112};
113
114static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
115static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
116
417bc304 117struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 118 { "pf_fixed", VCPU_STAT(pf_fixed) },
119 { "pf_guest", VCPU_STAT(pf_guest) },
120 { "tlb_flush", VCPU_STAT(tlb_flush) },
121 { "invlpg", VCPU_STAT(invlpg) },
122 { "exits", VCPU_STAT(exits) },
123 { "io_exits", VCPU_STAT(io_exits) },
124 { "mmio_exits", VCPU_STAT(mmio_exits) },
125 { "signal_exits", VCPU_STAT(signal_exits) },
126 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 127 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 128 { "halt_exits", VCPU_STAT(halt_exits) },
129 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 130 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 131 { "request_irq", VCPU_STAT(request_irq_exits) },
132 { "irq_exits", VCPU_STAT(irq_exits) },
133 { "host_state_reload", VCPU_STAT(host_state_reload) },
134 { "efer_reload", VCPU_STAT(efer_reload) },
135 { "fpu_reload", VCPU_STAT(fpu_reload) },
136 { "insn_emulation", VCPU_STAT(insn_emulation) },
137 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 138 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 139 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 140 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
141 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
142 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
143 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
144 { "mmu_flooded", VM_STAT(mmu_flooded) },
145 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 146 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 147 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 148 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 149 { "largepages", VM_STAT(lpages) },
417bc304
HB		 150 { NULL }
151};
152
2acf923e
DC		 153u64 __read_mostly host_xcr0;
154
d6aa1000
AK		 155int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
156
af585b92
GN		 157static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
158{
159 int i;
160 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
161 vcpu->arch.apf.gfns[i] = ~0;
162}
163
18863bdd
AK		 164static void kvm_on_user_return(struct user_return_notifier *urn)
165{
166 unsigned slot;
18863bdd
AK		 167 struct kvm_shared_msrs *locals
168 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 169 struct kvm_shared_msr_values *values;
18863bdd
AK		 170
171 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 172 values = &locals->values[slot];
173 if (values->host != values->curr) {
174 wrmsrl(shared_msrs_global.msrs[slot], values->host);
175 values->curr = values->host;
18863bdd
AK		 176 }
177 }
178 locals->registered = false;
179 user_return_notifier_unregister(urn);
180}
181
2bf78fa7 182static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 183{
2bf78fa7 184 struct kvm_shared_msrs *smsr;
18863bdd
AK		 185 u64 value;
186
2bf78fa7
SY		 187 smsr = &__get_cpu_var(shared_msrs);
188 /* only read, and nobody should modify it at this time,
189 * so don't need lock */
190 if (slot >= shared_msrs_global.nr) {
191 printk(KERN_ERR "kvm: invalid MSR slot!");
192 return;
193 }
194 rdmsrl_safe(msr, &value);
195 smsr->values[slot].host = value;
196 smsr->values[slot].curr = value;
197}
198
199void kvm_define_shared_msr(unsigned slot, u32 msr)
200{
18863bdd
AK		 201 if (slot >= shared_msrs_global.nr)
202 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 203 shared_msrs_global.msrs[slot] = msr;
204 /* we need ensured the shared_msr_global have been updated */
205 smp_wmb();
18863bdd
AK		 206}
207EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
208
209static void kvm_shared_msr_cpu_online(void)
210{
211 unsigned i;
18863bdd
AK		 212
213 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 214 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 215}
216
d5696725 217void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 218{
219 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
220
2bf78fa7 221 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 222 return;
2bf78fa7
SY		 223 smsr->values[slot].curr = value;
224 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 225 if (!smsr->registered) {
226 smsr->urn.on_user_return = kvm_on_user_return;
227 user_return_notifier_register(&smsr->urn);
228 smsr->registered = true;
229 }
230}
231EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
232
3548bab5
AK		 233static void drop_user_return_notifiers(void *ignore)
234{
235 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
236
237 if (smsr->registered)
238 kvm_on_user_return(&smsr->urn);
239}
240
6866b83e
CO		 241u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
242{
243 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 244 return vcpu->arch.apic_base;
6866b83e 245 else
ad312c7c 246 return vcpu->arch.apic_base;
6866b83e
CO		 247}
248EXPORT_SYMBOL_GPL(kvm_get_apic_base);
249
250void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
251{
252 /* TODO: reserve bits check */
253 if (irqchip_in_kernel(vcpu->kvm))
254 kvm_lapic_set_base(vcpu, data);
255 else
ad312c7c 256 vcpu->arch.apic_base = data;
6866b83e
CO		 257}
258EXPORT_SYMBOL_GPL(kvm_set_apic_base);
259
3fd28fce
ED		 260#define EXCPT_BENIGN 0
261#define EXCPT_CONTRIBUTORY 1
262#define EXCPT_PF 2
263
264static int exception_class(int vector)
265{
266 switch (vector) {
267 case PF_VECTOR:
268 return EXCPT_PF;
269 case DE_VECTOR:
270 case TS_VECTOR:
271 case NP_VECTOR:
272 case SS_VECTOR:
273 case GP_VECTOR:
274 return EXCPT_CONTRIBUTORY;
275 default:
276 break;
277 }
278 return EXCPT_BENIGN;
279}
280
281static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 282 unsigned nr, bool has_error, u32 error_code,
283 bool reinject)
3fd28fce
ED		 284{
285 u32 prev_nr;
286 int class1, class2;
287
3842d135
AK		 288 kvm_make_request(KVM_REQ_EVENT, vcpu);
289
3fd28fce
ED		 290 if (!vcpu->arch.exception.pending) {
291 queue:
292 vcpu->arch.exception.pending = true;
293 vcpu->arch.exception.has_error_code = has_error;
294 vcpu->arch.exception.nr = nr;
295 vcpu->arch.exception.error_code = error_code;
3f0fd292 296 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 297 return;
298 }
299
300 /* to check exception */
301 prev_nr = vcpu->arch.exception.nr;
302 if (prev_nr == DF_VECTOR) {
303 /* triple fault -> shutdown */
a8eeb04a 304 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 305 return;
306 }
307 class1 = exception_class(prev_nr);
308 class2 = exception_class(nr);
309 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
310 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
311 /* generate double fault per SDM Table 5-5 */
312 vcpu->arch.exception.pending = true;
313 vcpu->arch.exception.has_error_code = true;
314 vcpu->arch.exception.nr = DF_VECTOR;
315 vcpu->arch.exception.error_code = 0;
316 } else
317 /* replace previous exception with a new one in a hope
318 that instruction re-execution will regenerate lost
319 exception */
320 goto queue;
321}
322
298101da
AK		 323void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
324{
ce7ddec4 325 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 326}
327EXPORT_SYMBOL_GPL(kvm_queue_exception);
328
ce7ddec4
JR		 329void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
330{
331 kvm_multiple_exception(vcpu, nr, false, 0, true);
332}
333EXPORT_SYMBOL_GPL(kvm_requeue_exception);
334
db8fcefa 335void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 336{
db8fcefa
AP		 337 if (err)
338 kvm_inject_gp(vcpu, 0);
339 else
340 kvm_x86_ops->skip_emulated_instruction(vcpu);
341}
342EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 343
6389ee94 344void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 345{
346 ++vcpu->stat.pf_guest;
6389ee94
AK		 347 vcpu->arch.cr2 = fault->address;
348 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 349}
27d6c865 350EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 351
6389ee94 352void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 353{
6389ee94
AK		 354 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
355 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 356 else
6389ee94 357 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
d4f8cf66
JR		 358}
359
3419ffc8
SY		 360void kvm_inject_nmi(struct kvm_vcpu *vcpu)
361{
3842d135 362 kvm_make_request(KVM_REQ_EVENT, vcpu);
c761e586 363 vcpu->arch.nmi_pending = 1;
3419ffc8
SY		 364}
365EXPORT_SYMBOL_GPL(kvm_inject_nmi);
366
298101da
AK		 367void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
368{
ce7ddec4 369 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 370}
371EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
372
ce7ddec4
JR		 373void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
374{
375 kvm_multiple_exception(vcpu, nr, true, error_code, true);
376}
377EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
378
0a79b009
AK		 379/*
380 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
381 * a #GP and return false.
382 */
383bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 384{
0a79b009
AK		 385 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
386 return true;
387 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
388 return false;
298101da 389}
0a79b009 390EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 391
ec92fe44
JR		 392/*
393 * This function will be used to read from the physical memory of the currently
394 * running guest. The difference to kvm_read_guest_page is that this function
395 * can read from guest physical or from the guest's guest physical memory.
396 */
397int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
398 gfn_t ngfn, void *data, int offset, int len,
399 u32 access)
400{
401 gfn_t real_gfn;
402 gpa_t ngpa;
403
404 ngpa = gfn_to_gpa(ngfn);
405 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
406 if (real_gfn == UNMAPPED_GVA)
407 return -EFAULT;
408
409 real_gfn = gpa_to_gfn(real_gfn);
410
411 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
412}
413EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
414
3d06b8bf
JR		 415int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
416 void *data, int offset, int len, u32 access)
417{
418 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
419 data, offset, len, access);
420}
421
a03490ed
CO		 422/*
423 * Load the pae pdptrs. Return true is they are all valid.
424 */
ff03a073 425int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 426{
427 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
428 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
429 int i;
430 int ret;
ff03a073 431 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 432
ff03a073
JR		 433 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
434 offset * sizeof(u64), sizeof(pdpte),
435 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 436 if (ret < 0) {
437 ret = 0;
438 goto out;
439 }
440 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 441 if (is_present_gpte(pdpte[i]) &&
20c466b5 442 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 443 ret = 0;
444 goto out;
445 }
446 }
447 ret = 1;
448
ff03a073 449 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 450 __set_bit(VCPU_EXREG_PDPTR,
451 (unsigned long *)&vcpu->arch.regs_avail);
452 __set_bit(VCPU_EXREG_PDPTR,
453 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 454out:
a03490ed
CO		 455
456 return ret;
457}
cc4b6871 458EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 459
d835dfec
AK		 460static bool pdptrs_changed(struct kvm_vcpu *vcpu)
461{
ff03a073 462 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 463 bool changed = true;
3d06b8bf
JR		 464 int offset;
465 gfn_t gfn;
d835dfec
AK		 466 int r;
467
468 if (is_long_mode(vcpu) || !is_pae(vcpu))
469 return false;
470
6de4f3ad
AK		 471 if (!test_bit(VCPU_EXREG_PDPTR,
472 (unsigned long *)&vcpu->arch.regs_avail))
473 return true;
474
9f8fe504
AK		 475 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
476 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 477 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
478 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 479 if (r < 0)
480 goto out;
ff03a073 481 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 482out:
d835dfec
AK		 483
484 return changed;
485}
486
49a9b07e 487int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 488{
aad82703
SY		 489 unsigned long old_cr0 = kvm_read_cr0(vcpu);
490 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
491 X86_CR0_CD | X86_CR0_NW;
492
f9a48e6a
AK		 493 cr0 |= X86_CR0_ET;
494
ab344828 495#ifdef CONFIG_X86_64
0f12244f
GN		 496 if (cr0 & 0xffffffff00000000UL)
497 return 1;
ab344828
GN		 498#endif
499
500 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 501
0f12244f
GN		 502 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
503 return 1;
a03490ed 504
0f12244f
GN		 505 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
506 return 1;
a03490ed
CO		 507
508 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
509#ifdef CONFIG_X86_64
f6801dff 510 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 511 int cs_db, cs_l;
512
0f12244f
GN		 513 if (!is_pae(vcpu))
514 return 1;
a03490ed 515 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 516 if (cs_l)
517 return 1;
a03490ed
CO		 518 } else
519#endif
ff03a073 520 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 521 kvm_read_cr3(vcpu)))
0f12244f 522 return 1;
a03490ed
CO		 523 }
524
525 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 526
d170c419 527 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 528 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 529 kvm_async_pf_hash_reset(vcpu);
530 }
e5f3f027 531
aad82703
SY		 532 if ((cr0 ^ old_cr0) & update_bits)
533 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 534 return 0;
535}
2d3ad1f4 536EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 537
2d3ad1f4 538void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 539{
49a9b07e 540 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 541}
2d3ad1f4 542EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 543
2acf923e
DC		 544int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
545{
546 u64 xcr0;
547
548 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
549 if (index != XCR_XFEATURE_ENABLED_MASK)
550 return 1;
551 xcr0 = xcr;
552 if (kvm_x86_ops->get_cpl(vcpu) != 0)
553 return 1;
554 if (!(xcr0 & XSTATE_FP))
555 return 1;
556 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
557 return 1;
558 if (xcr0 & ~host_xcr0)
559 return 1;
560 vcpu->arch.xcr0 = xcr0;
561 vcpu->guest_xcr0_loaded = 0;
562 return 0;
563}
564
565int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
566{
567 if (__kvm_set_xcr(vcpu, index, xcr)) {
568 kvm_inject_gp(vcpu, 0);
569 return 1;
570 }
571 return 0;
572}
573EXPORT_SYMBOL_GPL(kvm_set_xcr);
574
575static bool guest_cpuid_has_xsave(struct kvm_vcpu *vcpu)
576{
577 struct kvm_cpuid_entry2 *best;
578
579 best = kvm_find_cpuid_entry(vcpu, 1, 0);
580 return best && (best->ecx & bit(X86_FEATURE_XSAVE));
581}
582
c68b734f
YW		 583static bool guest_cpuid_has_smep(struct kvm_vcpu *vcpu)
584{
585 struct kvm_cpuid_entry2 *best;
586
587 best = kvm_find_cpuid_entry(vcpu, 7, 0);
588 return best && (best->ebx & bit(X86_FEATURE_SMEP));
589}
590
74dc2b4f
YW		 591static bool guest_cpuid_has_fsgsbase(struct kvm_vcpu *vcpu)
592{
593 struct kvm_cpuid_entry2 *best;
594
595 best = kvm_find_cpuid_entry(vcpu, 7, 0);
596 return best && (best->ebx & bit(X86_FEATURE_FSGSBASE));
597}
598
2acf923e
DC		 599static void update_cpuid(struct kvm_vcpu *vcpu)
600{
601 struct kvm_cpuid_entry2 *best;
602
603 best = kvm_find_cpuid_entry(vcpu, 1, 0);
604 if (!best)
605 return;
606
607 /* Update OSXSAVE bit */
608 if (cpu_has_xsave && best->function == 0x1) {
609 best->ecx &= ~(bit(X86_FEATURE_OSXSAVE));
610 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE))
611 best->ecx |= bit(X86_FEATURE_OSXSAVE);
612 }
613}
614
a83b29c6 615int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 616{
fc78f519 617 unsigned long old_cr4 = kvm_read_cr4(vcpu);
c68b734f
YW		 618 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
619 X86_CR4_PAE | X86_CR4_SMEP;
0f12244f
GN		 620 if (cr4 & CR4_RESERVED_BITS)
621 return 1;
a03490ed 622
2acf923e
DC		 623 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
624 return 1;
625
c68b734f
YW		 626 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
627 return 1;
628
74dc2b4f
YW		 629 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_RDWRGSFS))
630 return 1;
631
a03490ed 632 if (is_long_mode(vcpu)) {
0f12244f
GN		 633 if (!(cr4 & X86_CR4_PAE))
634 return 1;
a2edf57f
AK		 635 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
636 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 637 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
638 kvm_read_cr3(vcpu)))
0f12244f
GN		 639 return 1;
640
5e1746d6 641 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 642 return 1;
a03490ed 643
aad82703
SY		 644 if ((cr4 ^ old_cr4) & pdptr_bits)
645 kvm_mmu_reset_context(vcpu);
0f12244f 646
2acf923e
DC		 647 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
648 update_cpuid(vcpu);
649
0f12244f
GN		 650 return 0;
651}
2d3ad1f4 652EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 653
2390218b 654int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 655{
9f8fe504 656 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 657 kvm_mmu_sync_roots(vcpu);
d835dfec 658 kvm_mmu_flush_tlb(vcpu);
0f12244f 659 return 0;
d835dfec
AK		 660 }
661
a03490ed 662 if (is_long_mode(vcpu)) {
0f12244f
GN		 663 if (cr3 & CR3_L_MODE_RESERVED_BITS)
664 return 1;
a03490ed
CO		 665 } else {
666 if (is_pae(vcpu)) {
0f12244f
GN		 667 if (cr3 & CR3_PAE_RESERVED_BITS)
668 return 1;
ff03a073
JR		 669 if (is_paging(vcpu) &&
670 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
0f12244f 671 return 1;
a03490ed
CO		 672 }
673 /*
674 * We don't check reserved bits in nonpae mode, because
675 * this isn't enforced, and VMware depends on this.
676 */
677 }
678
a03490ed
CO		 679 /*
680 * Does the new cr3 value map to physical memory? (Note, we
681 * catch an invalid cr3 even in real-mode, because it would
682 * cause trouble later on when we turn on paging anyway.)
683 *
684 * A real CPU would silently accept an invalid cr3 and would
685 * attempt to use it - with largely undefined (and often hard
686 * to debug) behavior on the guest side.
687 */
688 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
0f12244f
GN		 689 return 1;
690 vcpu->arch.cr3 = cr3;
aff48baa 691 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
0f12244f
GN		 692 vcpu->arch.mmu.new_cr3(vcpu);
693 return 0;
694}
2d3ad1f4 695EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 696
eea1cff9 697int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 698{
0f12244f
GN		 699 if (cr8 & CR8_RESERVED_BITS)
700 return 1;
a03490ed
CO		 701 if (irqchip_in_kernel(vcpu->kvm))
702 kvm_lapic_set_tpr(vcpu, cr8);
703 else
ad312c7c 704 vcpu->arch.cr8 = cr8;
0f12244f
GN		 705 return 0;
706}
2d3ad1f4 707EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 708
2d3ad1f4 709unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 710{
711 if (irqchip_in_kernel(vcpu->kvm))
712 return kvm_lapic_get_cr8(vcpu);
713 else
ad312c7c 714 return vcpu->arch.cr8;
a03490ed 715}
2d3ad1f4 716EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 717
338dbc97 718static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 719{
720 switch (dr) {
721 case 0 ... 3:
722 vcpu->arch.db[dr] = val;
723 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
724 vcpu->arch.eff_db[dr] = val;
725 break;
726 case 4:
338dbc97
GN		 727 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
728 return 1; /* #UD */
020df079
GN		 729 /* fall through */
730 case 6:
338dbc97
GN		 731 if (val & 0xffffffff00000000ULL)
732 return -1; /* #GP */
020df079
GN		 733 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
734 break;
735 case 5:
338dbc97
GN		 736 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
737 return 1; /* #UD */
020df079
GN		 738 /* fall through */
739 default: /* 7 */
338dbc97
GN		 740 if (val & 0xffffffff00000000ULL)
741 return -1; /* #GP */
020df079
GN		 742 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
743 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
744 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
745 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
746 }
747 break;
748 }
749
750 return 0;
751}
338dbc97
GN		 752
753int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
754{
755 int res;
756
757 res = __kvm_set_dr(vcpu, dr, val);
758 if (res > 0)
759 kvm_queue_exception(vcpu, UD_VECTOR);
760 else if (res < 0)
761 kvm_inject_gp(vcpu, 0);
762
763 return res;
764}
020df079
GN		 765EXPORT_SYMBOL_GPL(kvm_set_dr);
766
338dbc97 767static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 768{
769 switch (dr) {
770 case 0 ... 3:
771 *val = vcpu->arch.db[dr];
772 break;
773 case 4:
338dbc97 774 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 775 return 1;
020df079
GN		 776 /* fall through */
777 case 6:
778 *val = vcpu->arch.dr6;
779 break;
780 case 5:
338dbc97 781 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 782 return 1;
020df079
GN		 783 /* fall through */
784 default: /* 7 */
785 *val = vcpu->arch.dr7;
786 break;
787 }
788
789 return 0;
790}
338dbc97
GN		 791
792int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
793{
794 if (_kvm_get_dr(vcpu, dr, val)) {
795 kvm_queue_exception(vcpu, UD_VECTOR);
796 return 1;
797 }
798 return 0;
799}
020df079
GN		 800EXPORT_SYMBOL_GPL(kvm_get_dr);
801
043405e1
CO		 802/*
803 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
804 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
805 *
806 * This list is modified at module load time to reflect the
e3267cbb
GC		 807 * capabilities of the host cpu. This capabilities test skips MSRs that are
808 * kvm-specific. Those are put in the beginning of the list.
043405e1 809 */
e3267cbb 810
c9aaa895 811#define KVM_SAVE_MSRS_BEGIN 9
043405e1 812static u32 msrs_to_save[] = {
e3267cbb 813 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 814 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 815 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
c9aaa895 816 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
043405e1 817 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 818 MSR_STAR,
043405e1
CO		 819#ifdef CONFIG_X86_64
820 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
821#endif
e90aa41e 822 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 823};
824
825static unsigned num_msrs_to_save;
826
827static u32 emulated_msrs[] = {
828 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 829 MSR_IA32_MCG_STATUS,
830 MSR_IA32_MCG_CTL,
043405e1
CO		 831};
832
b69e8cae 833static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 834{
aad82703
SY		 835 u64 old_efer = vcpu->arch.efer;
836
b69e8cae
RJ		 837 if (efer & efer_reserved_bits)
838 return 1;
15c4a640
CO		 839
840 if (is_paging(vcpu)
b69e8cae
RJ		 841 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
842 return 1;
15c4a640 843
1b2fd70c
AG		 844 if (efer & EFER_FFXSR) {
845 struct kvm_cpuid_entry2 *feat;
846
847 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 848 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
849 return 1;
1b2fd70c
AG		 850 }
851
d8017474
AG		 852 if (efer & EFER_SVME) {
853 struct kvm_cpuid_entry2 *feat;
854
855 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 856 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
857 return 1;
d8017474
AG		 858 }
859
15c4a640 860 efer &= ~EFER_LMA;
f6801dff 861 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 862
a3d204e2
SY		 863 kvm_x86_ops->set_efer(vcpu, efer);
864
9645bb56 865 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
b69e8cae 866
aad82703
SY		 867 /* Update reserved bits */
868 if ((efer ^ old_efer) & EFER_NX)
869 kvm_mmu_reset_context(vcpu);
870
b69e8cae 871 return 0;
15c4a640
CO		 872}
873
f2b4b7dd
JR		 874void kvm_enable_efer_bits(u64 mask)
875{
876 efer_reserved_bits &= ~mask;
877}
878EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
879
880
15c4a640
CO		 881/*
882 * Writes msr value into into the appropriate "register".
883 * Returns 0 on success, non-0 otherwise.
884 * Assumes vcpu_load() was already called.
885 */
886int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
887{
888 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
889}
890
313a3dc7
CO		 891/*
892 * Adapt set_msr() to msr_io()'s calling convention
893 */
894static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
895{
896 return kvm_set_msr(vcpu, index, *data);
897}
898
18068523
GOC		 899static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
900{
9ed3c444
AK		 901 int version;
902 int r;
50d0a0f9 903 struct pvclock_wall_clock wc;
923de3cf 904 struct timespec boot;
18068523
GOC		 905
906 if (!wall_clock)
907 return;
908
9ed3c444
AK		 909 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
910 if (r)
911 return;
912
913 if (version & 1)
914 ++version; /* first time write, random junk */
915
916 ++version;
18068523 917
18068523
GOC		 918 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
919
50d0a0f9
GH		 920 /*
921 * The guest calculates current wall clock time by adding
34c238a1 922 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 923 * wall clock specified here. guest system time equals host
924 * system time for us, thus we must fill in host boot time here.
925 */
923de3cf 926 getboottime(&boot);
50d0a0f9
GH		 927
928 wc.sec = boot.tv_sec;
929 wc.nsec = boot.tv_nsec;
930 wc.version = version;
18068523
GOC		 931
932 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
933
934 version++;
935 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 936}
937
50d0a0f9
GH		 938static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
939{
940 uint32_t quotient, remainder;
941
942 /* Don't try to replace with do_div(), this one calculates
943 * "(dividend << 32) / divisor" */
944 __asm__ ( "divl %4"
945 : "=a" (quotient), "=d" (remainder)
946 : "0" (0), "1" (dividend), "r" (divisor) );
947 return quotient;
948}
949
5f4e3f88
ZA		 950static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
951 s8 *pshift, u32 *pmultiplier)
50d0a0f9 952{
5f4e3f88 953 uint64_t scaled64;
50d0a0f9
GH		 954 int32_t shift = 0;
955 uint64_t tps64;
956 uint32_t tps32;
957
5f4e3f88
ZA		 958 tps64 = base_khz * 1000LL;
959 scaled64 = scaled_khz * 1000LL;
50933623 960 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 961 tps64 >>= 1;
962 shift--;
963 }
964
965 tps32 = (uint32_t)tps64;
50933623
JK		 966 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
967 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 968 scaled64 >>= 1;
969 else
970 tps32 <<= 1;
50d0a0f9
GH		 971 shift++;
972 }
973
5f4e3f88
ZA		 974 *pshift = shift;
975 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 976
5f4e3f88
ZA		 977 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
978 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 979}
980
759379dd
ZA		 981static inline u64 get_kernel_ns(void)
982{
983 struct timespec ts;
984
985 WARN_ON(preemptible());
986 ktime_get_ts(&ts);
987 monotonic_to_bootbased(&ts);
988 return timespec_to_ns(&ts);
50d0a0f9
GH		 989}
990
c8076604 991static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 992unsigned long max_tsc_khz;
c8076604 993
8cfdc000
ZA		 994static inline int kvm_tsc_changes_freq(void)
995{
996 int cpu = get_cpu();
997 int ret = !boot_cpu_has(X86_FEATURE_CONSTANT_TSC) &&
998 cpufreq_quick_get(cpu) != 0;
999 put_cpu();
1000 return ret;
1001}
1002
1e993611
JR		 1003static u64 vcpu_tsc_khz(struct kvm_vcpu *vcpu)
1004{
1005 if (vcpu->arch.virtual_tsc_khz)
1006 return vcpu->arch.virtual_tsc_khz;
1007 else
1008 return __this_cpu_read(cpu_tsc_khz);
1009}
1010
857e4099 1011static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
759379dd 1012{
217fc9cf
AK		 1013 u64 ret;
1014
759379dd
ZA		 1015 WARN_ON(preemptible());
1016 if (kvm_tsc_changes_freq())
1017 printk_once(KERN_WARNING
1018 "kvm: unreliable cycle conversion on adjustable rate TSC\n");
857e4099 1019 ret = nsec * vcpu_tsc_khz(vcpu);
217fc9cf
AK		 1020 do_div(ret, USEC_PER_SEC);
1021 return ret;
759379dd
ZA		 1022}
1023
1e993611 1024static void kvm_init_tsc_catchup(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
c285545f
ZA		 1025{
1026 /* Compute a scale to convert nanoseconds in TSC cycles */
1027 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
1e993611
JR		 1028 &vcpu->arch.tsc_catchup_shift,
1029 &vcpu->arch.tsc_catchup_mult);
c285545f
ZA		 1030}
1031
1032static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1033{
1034 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.last_tsc_nsec,
1e993611
JR		 1035 vcpu->arch.tsc_catchup_mult,
1036 vcpu->arch.tsc_catchup_shift);
c285545f
ZA		 1037 tsc += vcpu->arch.last_tsc_write;
1038 return tsc;
1039}
1040
99e3e30a
ZA		 1041void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
1042{
1043 struct kvm *kvm = vcpu->kvm;
f38e098f 1044 u64 offset, ns, elapsed;
99e3e30a 1045 unsigned long flags;
46543ba4 1046 s64 sdiff;
99e3e30a 1047
038f8c11 1048 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1049 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1050 ns = get_kernel_ns();
f38e098f 1051 elapsed = ns - kvm->arch.last_tsc_nsec;
46543ba4
ZA		 1052 sdiff = data - kvm->arch.last_tsc_write;
1053 if (sdiff < 0)
1054 sdiff = -sdiff;
f38e098f
ZA		 1055
1056 /*
46543ba4 1057 * Special case: close write to TSC within 5 seconds of
f38e098f 1058 * another CPU is interpreted as an attempt to synchronize
0d2eb44f 1059 * The 5 seconds is to accommodate host load / swapping as
46543ba4 1060 * well as any reset of TSC during the boot process.
f38e098f
ZA		 1061 *
1062 * In that case, for a reliable TSC, we can match TSC offsets,
46543ba4 1063 * or make a best guest using elapsed value.
f38e098f 1064 */
857e4099 1065 if (sdiff < nsec_to_cycles(vcpu, 5ULL * NSEC_PER_SEC) &&
46543ba4 1066 elapsed < 5ULL * NSEC_PER_SEC) {
f38e098f
ZA		 1067 if (!check_tsc_unstable()) {
1068 offset = kvm->arch.last_tsc_offset;
1069 pr_debug("kvm: matched tsc offset for %llu\n", data);
1070 } else {
857e4099 1071 u64 delta = nsec_to_cycles(vcpu, elapsed);
759379dd
ZA		 1072 offset += delta;
1073 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f
ZA		 1074 }
1075 ns = kvm->arch.last_tsc_nsec;
1076 }
1077 kvm->arch.last_tsc_nsec = ns;
1078 kvm->arch.last_tsc_write = data;
1079 kvm->arch.last_tsc_offset = offset;
99e3e30a 1080 kvm_x86_ops->write_tsc_offset(vcpu, offset);
038f8c11 1081 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
99e3e30a
ZA		 1082
1083 /* Reset of TSC must disable overshoot protection below */
1084 vcpu->arch.hv_clock.tsc_timestamp = 0;
c285545f
ZA		 1085 vcpu->arch.last_tsc_write = data;
1086 vcpu->arch.last_tsc_nsec = ns;
99e3e30a
ZA		 1087}
1088EXPORT_SYMBOL_GPL(kvm_write_tsc);
1089
34c238a1 1090static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1091{
18068523
GOC		 1092 unsigned long flags;
1093 struct kvm_vcpu_arch *vcpu = &v->arch;
1094 void *shared_kaddr;
463656c0 1095 unsigned long this_tsc_khz;
1d5f066e
ZA		 1096 s64 kernel_ns, max_kernel_ns;
1097 u64 tsc_timestamp;
18068523 1098
18068523
GOC		 1099 /* Keep irq disabled to prevent changes to the clock */
1100 local_irq_save(flags);
1d5f066e 1101 kvm_get_msr(v, MSR_IA32_TSC, &tsc_timestamp);
759379dd 1102 kernel_ns = get_kernel_ns();
1e993611 1103 this_tsc_khz = vcpu_tsc_khz(v);
8cfdc000 1104 if (unlikely(this_tsc_khz == 0)) {
c285545f 1105 local_irq_restore(flags);
34c238a1 1106 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
8cfdc000
ZA		 1107 return 1;
1108 }
18068523 1109
c285545f
ZA		 1110 /*
1111 * We may have to catch up the TSC to match elapsed wall clock
1112 * time for two reasons, even if kvmclock is used.
1113 * 1) CPU could have been running below the maximum TSC rate
1114 * 2) Broken TSC compensation resets the base at each VCPU
1115 * entry to avoid unknown leaps of TSC even when running
1116 * again on the same CPU. This may cause apparent elapsed
1117 * time to disappear, and the guest to stand still or run
1118 * very slowly.
1119 */
1120 if (vcpu->tsc_catchup) {
1121 u64 tsc = compute_guest_tsc(v, kernel_ns);
1122 if (tsc > tsc_timestamp) {
1123 kvm_x86_ops->adjust_tsc_offset(v, tsc - tsc_timestamp);
1124 tsc_timestamp = tsc;
1125 }
50d0a0f9
GH		 1126 }
1127
18068523
GOC		 1128 local_irq_restore(flags);
1129
c285545f
ZA		 1130 if (!vcpu->time_page)
1131 return 0;
18068523 1132
1d5f066e
ZA		 1133 /*
1134 * Time as measured by the TSC may go backwards when resetting the base
1135 * tsc_timestamp. The reason for this is that the TSC resolution is
1136 * higher than the resolution of the other clock scales. Thus, many
1137 * possible measurments of the TSC correspond to one measurement of any
1138 * other clock, and so a spread of values is possible. This is not a
1139 * problem for the computation of the nanosecond clock; with TSC rates
1140 * around 1GHZ, there can only be a few cycles which correspond to one
1141 * nanosecond value, and any path through this code will inevitably
1142 * take longer than that. However, with the kernel_ns value itself,
1143 * the precision may be much lower, down to HZ granularity. If the
1144 * first sampling of TSC against kernel_ns ends in the low part of the
1145 * range, and the second in the high end of the range, we can get:
1146 *
1147 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1148 *
1149 * As the sampling errors potentially range in the thousands of cycles,
1150 * it is possible such a time value has already been observed by the
1151 * guest. To protect against this, we must compute the system time as
1152 * observed by the guest and ensure the new system time is greater.
1153 */
1154 max_kernel_ns = 0;
1155 if (vcpu->hv_clock.tsc_timestamp && vcpu->last_guest_tsc) {
1156 max_kernel_ns = vcpu->last_guest_tsc -
1157 vcpu->hv_clock.tsc_timestamp;
1158 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1159 vcpu->hv_clock.tsc_to_system_mul,
1160 vcpu->hv_clock.tsc_shift);
1161 max_kernel_ns += vcpu->last_kernel_ns;
1162 }
afbcf7ab 1163
e48672fa 1164 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1165 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1166 &vcpu->hv_clock.tsc_shift,
1167 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1168 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1169 }
1170
1d5f066e
ZA		 1171 if (max_kernel_ns > kernel_ns)
1172 kernel_ns = max_kernel_ns;
1173
8cfdc000 1174 /* With all the info we got, fill in the values */
1d5f066e 1175 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1176 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1d5f066e 1177 vcpu->last_kernel_ns = kernel_ns;
28e4639a 1178 vcpu->last_guest_tsc = tsc_timestamp;
371bcf64
GC		 1179 vcpu->hv_clock.flags = 0;
1180
18068523
GOC		 1181 /*
1182 * The interface expects us to write an even number signaling that the
1183 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1184 * state, we just increase by 2 at the end.
18068523 1185 */
50d0a0f9 1186 vcpu->hv_clock.version += 2;
18068523
GOC		 1187
1188 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
1189
1190 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 1191 sizeof(vcpu->hv_clock));
18068523
GOC		 1192
1193 kunmap_atomic(shared_kaddr, KM_USER0);
1194
1195 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
8cfdc000 1196 return 0;
c8076604
GH		 1197}
1198
9ba075a6
AK		 1199static bool msr_mtrr_valid(unsigned msr)
1200{
1201 switch (msr) {
1202 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1203 case MSR_MTRRfix64K_00000:
1204 case MSR_MTRRfix16K_80000:
1205 case MSR_MTRRfix16K_A0000:
1206 case MSR_MTRRfix4K_C0000:
1207 case MSR_MTRRfix4K_C8000:
1208 case MSR_MTRRfix4K_D0000:
1209 case MSR_MTRRfix4K_D8000:
1210 case MSR_MTRRfix4K_E0000:
1211 case MSR_MTRRfix4K_E8000:
1212 case MSR_MTRRfix4K_F0000:
1213 case MSR_MTRRfix4K_F8000:
1214 case MSR_MTRRdefType:
1215 case MSR_IA32_CR_PAT:
1216 return true;
1217 case 0x2f8:
1218 return true;
1219 }
1220 return false;
1221}
1222
d6289b93
MT		 1223static bool valid_pat_type(unsigned t)
1224{
1225 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1226}
1227
1228static bool valid_mtrr_type(unsigned t)
1229{
1230 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1231}
1232
1233static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1234{
1235 int i;
1236
1237 if (!msr_mtrr_valid(msr))
1238 return false;
1239
1240 if (msr == MSR_IA32_CR_PAT) {
1241 for (i = 0; i < 8; i++)
1242 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1243 return false;
1244 return true;
1245 } else if (msr == MSR_MTRRdefType) {
1246 if (data & ~0xcff)
1247 return false;
1248 return valid_mtrr_type(data & 0xff);
1249 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1250 for (i = 0; i < 8 ; i++)
1251 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1252 return false;
1253 return true;
1254 }
1255
1256 /* variable MTRRs */
1257 return valid_mtrr_type(data & 0xff);
1258}
1259
9ba075a6
AK		 1260static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1261{
0bed3b56
SY		 1262 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1263
d6289b93 1264 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1265 return 1;
1266
0bed3b56
SY		 1267 if (msr == MSR_MTRRdefType) {
1268 vcpu->arch.mtrr_state.def_type = data;
1269 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1270 } else if (msr == MSR_MTRRfix64K_00000)
1271 p[0] = data;
1272 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1273 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1274 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1275 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1276 else if (msr == MSR_IA32_CR_PAT)
1277 vcpu->arch.pat = data;
1278 else { /* Variable MTRRs */
1279 int idx, is_mtrr_mask;
1280 u64 *pt;
1281
1282 idx = (msr - 0x200) / 2;
1283 is_mtrr_mask = msr - 0x200 - 2 * idx;
1284 if (!is_mtrr_mask)
1285 pt =
1286 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1287 else
1288 pt =
1289 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1290 *pt = data;
1291 }
1292
1293 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1294 return 0;
1295}
15c4a640 1296
890ca9ae 1297static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1298{
890ca9ae
HY		 1299 u64 mcg_cap = vcpu->arch.mcg_cap;
1300 unsigned bank_num = mcg_cap & 0xff;
1301
15c4a640 1302 switch (msr) {
15c4a640 1303 case MSR_IA32_MCG_STATUS:
890ca9ae 1304 vcpu->arch.mcg_status = data;
15c4a640 1305 break;
c7ac679c 1306 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1307 if (!(mcg_cap & MCG_CTL_P))
1308 return 1;
1309 if (data != 0 && data != ~(u64)0)
1310 return -1;
1311 vcpu->arch.mcg_ctl = data;
1312 break;
1313 default:
1314 if (msr >= MSR_IA32_MC0_CTL &&
1315 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1316 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1317 /* only 0 or all 1s can be written to IA32_MCi_CTL
1318 * some Linux kernels though clear bit 10 in bank 4 to
1319 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1320 * this to avoid an uncatched #GP in the guest
1321 */
890ca9ae 1322 if ((offset & 0x3) == 0 &&
114be429 1323 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1324 return -1;
1325 vcpu->arch.mce_banks[offset] = data;
1326 break;
1327 }
1328 return 1;
1329 }
1330 return 0;
1331}
1332
ffde22ac
ES		 1333static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1334{
1335 struct kvm *kvm = vcpu->kvm;
1336 int lm = is_long_mode(vcpu);
1337 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1338 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1339 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1340 : kvm->arch.xen_hvm_config.blob_size_32;
1341 u32 page_num = data & ~PAGE_MASK;
1342 u64 page_addr = data & PAGE_MASK;
1343 u8 *page;
1344 int r;
1345
1346 r = -E2BIG;
1347 if (page_num >= blob_size)
1348 goto out;
1349 r = -ENOMEM;
1350 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
1351 if (!page)
1352 goto out;
1353 r = -EFAULT;
1354 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
1355 goto out_free;
1356 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1357 goto out_free;
1358 r = 0;
1359out_free:
1360 kfree(page);
1361out:
1362 return r;
1363}
1364
55cd8e5a
GN		 1365static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1366{
1367 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1368}
1369
1370static bool kvm_hv_msr_partition_wide(u32 msr)
1371{
1372 bool r = false;
1373 switch (msr) {
1374 case HV_X64_MSR_GUEST_OS_ID:
1375 case HV_X64_MSR_HYPERCALL:
1376 r = true;
1377 break;
1378 }
1379
1380 return r;
1381}
1382
1383static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1384{
1385 struct kvm *kvm = vcpu->kvm;
1386
1387 switch (msr) {
1388 case HV_X64_MSR_GUEST_OS_ID:
1389 kvm->arch.hv_guest_os_id = data;
1390 /* setting guest os id to zero disables hypercall page */
1391 if (!kvm->arch.hv_guest_os_id)
1392 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1393 break;
1394 case HV_X64_MSR_HYPERCALL: {
1395 u64 gfn;
1396 unsigned long addr;
1397 u8 instructions[4];
1398
1399 /* if guest os id is not set hypercall should remain disabled */
1400 if (!kvm->arch.hv_guest_os_id)
1401 break;
1402 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1403 kvm->arch.hv_hypercall = data;
1404 break;
1405 }
1406 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1407 addr = gfn_to_hva(kvm, gfn);
1408 if (kvm_is_error_hva(addr))
1409 return 1;
1410 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1411 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1412 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1413 return 1;
1414 kvm->arch.hv_hypercall = data;
1415 break;
1416 }
1417 default:
1418 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1419 "data 0x%llx\n", msr, data);
1420 return 1;
1421 }
1422 return 0;
1423}
1424
1425static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1426{
10388a07
GN		 1427 switch (msr) {
1428 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1429 unsigned long addr;
55cd8e5a 1430
10388a07
GN		 1431 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1432 vcpu->arch.hv_vapic = data;
1433 break;
1434 }
1435 addr = gfn_to_hva(vcpu->kvm, data >>
1436 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1437 if (kvm_is_error_hva(addr))
1438 return 1;
8b0cedff 1439 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 1440 return 1;
1441 vcpu->arch.hv_vapic = data;
1442 break;
1443 }
1444 case HV_X64_MSR_EOI:
1445 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1446 case HV_X64_MSR_ICR:
1447 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1448 case HV_X64_MSR_TPR:
1449 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1450 default:
1451 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1452 "data 0x%llx\n", msr, data);
1453 return 1;
1454 }
1455
1456 return 0;
55cd8e5a
GN		 1457}
1458
344d9588
GN		 1459static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1460{
1461 gpa_t gpa = data & ~0x3f;
1462
6adba527
GN		 1463 /* Bits 2:5 are resrved, Should be zero */
1464 if (data & 0x3c)
344d9588
GN		 1465 return 1;
1466
1467 vcpu->arch.apf.msr_val = data;
1468
1469 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1470 kvm_clear_async_pf_completion_queue(vcpu);
1471 kvm_async_pf_hash_reset(vcpu);
1472 return 0;
1473 }
1474
1475 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa))
1476 return 1;
1477
6adba527 1478 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1479 kvm_async_pf_wakeup_all(vcpu);
1480 return 0;
1481}
1482
12f9a48f
GC		 1483static void kvmclock_reset(struct kvm_vcpu *vcpu)
1484{
1485 if (vcpu->arch.time_page) {
1486 kvm_release_page_dirty(vcpu->arch.time_page);
1487 vcpu->arch.time_page = NULL;
1488 }
1489}
1490
c9aaa895
GC		 1491static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1492{
1493 u64 delta;
1494
1495 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1496 return;
1497
1498 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1499 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1500 vcpu->arch.st.accum_steal = delta;
1501}
1502
1503static void record_steal_time(struct kvm_vcpu *vcpu)
1504{
1505 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1506 return;
1507
1508 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1509 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1510 return;
1511
1512 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1513 vcpu->arch.st.steal.version += 2;
1514 vcpu->arch.st.accum_steal = 0;
1515
1516 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1517 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1518}
1519
15c4a640
CO		 1520int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1521{
1522 switch (msr) {
15c4a640 1523 case MSR_EFER:
b69e8cae 1524 return set_efer(vcpu, data);
8f1589d9
AP		 1525 case MSR_K7_HWCR:
1526 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1527 data &= ~(u64)0x100; /* ignore ignne emulation enable */
8f1589d9
AP		 1528 if (data != 0) {
1529 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1530 data);
1531 return 1;
1532 }
15c4a640 1533 break;
f7c6d140
AP		 1534 case MSR_FAM10H_MMIO_CONF_BASE:
1535 if (data != 0) {
1536 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1537 "0x%llx\n", data);
1538 return 1;
1539 }
15c4a640 1540 break;
c323c0e5 1541 case MSR_AMD64_NB_CFG:
c7ac679c 1542 break;
b5e2fec0
AG		 1543 case MSR_IA32_DEBUGCTLMSR:
1544 if (!data) {
1545 /* We support the non-activated case already */
1546 break;
1547 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1548 /* Values other than LBR and BTF are vendor-specific,
1549 thus reserved and should throw a #GP */
1550 return 1;
1551 }
1552 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1553 __func__, data);
1554 break;
15c4a640
CO		 1555 case MSR_IA32_UCODE_REV:
1556 case MSR_IA32_UCODE_WRITE:
61a6bd67 1557 case MSR_VM_HSAVE_PA:
6098ca93 1558 case MSR_AMD64_PATCH_LOADER:
15c4a640 1559 break;
9ba075a6
AK		 1560 case 0x200 ... 0x2ff:
1561 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1562 case MSR_IA32_APICBASE:
1563 kvm_set_apic_base(vcpu, data);
1564 break;
0105d1a5
GN		 1565 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1566 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 1567 case MSR_IA32_MISC_ENABLE:
ad312c7c 1568 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1569 break;
11c6bffa 1570 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1571 case MSR_KVM_WALL_CLOCK:
1572 vcpu->kvm->arch.wall_clock = data;
1573 kvm_write_wall_clock(vcpu->kvm, data);
1574 break;
11c6bffa 1575 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 1576 case MSR_KVM_SYSTEM_TIME: {
12f9a48f 1577 kvmclock_reset(vcpu);
18068523
GOC		 1578
1579 vcpu->arch.time = data;
c285545f 1580 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
18068523
GOC		 1581
1582 /* we verify if the enable bit is set... */
1583 if (!(data & 1))
1584 break;
1585
1586 /* ...but clean it before doing the actual write */
1587 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1588
18068523
GOC		 1589 vcpu->arch.time_page =
1590 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1591
1592 if (is_error_page(vcpu->arch.time_page)) {
1593 kvm_release_page_clean(vcpu->arch.time_page);
1594 vcpu->arch.time_page = NULL;
1595 }
18068523
GOC		 1596 break;
1597 }
344d9588
GN		 1598 case MSR_KVM_ASYNC_PF_EN:
1599 if (kvm_pv_enable_async_pf(vcpu, data))
1600 return 1;
1601 break;
c9aaa895
GC		 1602 case MSR_KVM_STEAL_TIME:
1603
1604 if (unlikely(!sched_info_on()))
1605 return 1;
1606
1607 if (data & KVM_STEAL_RESERVED_MASK)
1608 return 1;
1609
1610 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
1611 data & KVM_STEAL_VALID_BITS))
1612 return 1;
1613
1614 vcpu->arch.st.msr_val = data;
1615
1616 if (!(data & KVM_MSR_ENABLED))
1617 break;
1618
1619 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1620
1621 preempt_disable();
1622 accumulate_steal_time(vcpu);
1623 preempt_enable();
1624
1625 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
1626
1627 break;
1628
890ca9ae
HY		 1629 case MSR_IA32_MCG_CTL:
1630 case MSR_IA32_MCG_STATUS:
1631 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1632 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1633
1634 /* Performance counters are not protected by a CPUID bit,
1635 * so we should check all of them in the generic path for the sake of
1636 * cross vendor migration.
1637 * Writing a zero into the event select MSRs disables them,
1638 * which we perfectly emulate ;-). Any other value should be at least
1639 * reported, some guests depend on them.
1640 */
1641 case MSR_P6_EVNTSEL0:
1642 case MSR_P6_EVNTSEL1:
1643 case MSR_K7_EVNTSEL0:
1644 case MSR_K7_EVNTSEL1:
1645 case MSR_K7_EVNTSEL2:
1646 case MSR_K7_EVNTSEL3:
1647 if (data != 0)
1648 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1649 "0x%x data 0x%llx\n", msr, data);
1650 break;
1651 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1652 * so we ignore writes to make it happy.
1653 */
1654 case MSR_P6_PERFCTR0:
1655 case MSR_P6_PERFCTR1:
1656 case MSR_K7_PERFCTR0:
1657 case MSR_K7_PERFCTR1:
1658 case MSR_K7_PERFCTR2:
1659 case MSR_K7_PERFCTR3:
1660 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1661 "0x%x data 0x%llx\n", msr, data);
1662 break;
84e0cefa
JS		 1663 case MSR_K7_CLK_CTL:
1664 /*
1665 * Ignore all writes to this no longer documented MSR.
1666 * Writes are only relevant for old K7 processors,
1667 * all pre-dating SVM, but a recommended workaround from
1668 * AMD for these chips. It is possible to speicify the
1669 * affected processor models on the command line, hence
1670 * the need to ignore the workaround.
1671 */
1672 break;
55cd8e5a
GN		 1673 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1674 if (kvm_hv_msr_partition_wide(msr)) {
1675 int r;
1676 mutex_lock(&vcpu->kvm->lock);
1677 r = set_msr_hyperv_pw(vcpu, msr, data);
1678 mutex_unlock(&vcpu->kvm->lock);
1679 return r;
1680 } else
1681 return set_msr_hyperv(vcpu, msr, data);
1682 break;
91c9c3ed 1683 case MSR_IA32_BBL_CR_CTL3:
1684 /* Drop writes to this legacy MSR -- see rdmsr
1685 * counterpart for further detail.
1686 */
1687 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
1688 break;
15c4a640 1689 default:
ffde22ac
ES		 1690 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1691 return xen_hvm_config(vcpu, data);
ed85c068
AP		 1692 if (!ignore_msrs) {
1693 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1694 msr, data);
1695 return 1;
1696 } else {
1697 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1698 msr, data);
1699 break;
1700 }
15c4a640
CO		 1701 }
1702 return 0;
1703}
1704EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1705
1706
1707/*
1708 * Reads an msr value (of 'msr_index') into 'pdata'.
1709 * Returns 0 on success, non-0 otherwise.
1710 * Assumes vcpu_load() was already called.
1711 */
1712int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1713{
1714 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1715}
1716
9ba075a6
AK		 1717static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1718{
0bed3b56
SY		 1719 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1720
9ba075a6
AK		 1721 if (!msr_mtrr_valid(msr))
1722 return 1;
1723
0bed3b56
SY		 1724 if (msr == MSR_MTRRdefType)
1725 *pdata = vcpu->arch.mtrr_state.def_type +
1726 (vcpu->arch.mtrr_state.enabled << 10);
1727 else if (msr == MSR_MTRRfix64K_00000)
1728 *pdata = p[0];
1729 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1730 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1731 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1732 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1733 else if (msr == MSR_IA32_CR_PAT)
1734 *pdata = vcpu->arch.pat;
1735 else { /* Variable MTRRs */
1736 int idx, is_mtrr_mask;
1737 u64 *pt;
1738
1739 idx = (msr - 0x200) / 2;
1740 is_mtrr_mask = msr - 0x200 - 2 * idx;
1741 if (!is_mtrr_mask)
1742 pt =
1743 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1744 else
1745 pt =
1746 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1747 *pdata = *pt;
1748 }
1749
9ba075a6
AK		 1750 return 0;
1751}
1752
890ca9ae 1753static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1754{
1755 u64 data;
890ca9ae
HY		 1756 u64 mcg_cap = vcpu->arch.mcg_cap;
1757 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1758
1759 switch (msr) {
15c4a640
CO		 1760 case MSR_IA32_P5_MC_ADDR:
1761 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1762 data = 0;
1763 break;
15c4a640 1764 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1765 data = vcpu->arch.mcg_cap;
1766 break;
c7ac679c 1767 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1768 if (!(mcg_cap & MCG_CTL_P))
1769 return 1;
1770 data = vcpu->arch.mcg_ctl;
1771 break;
1772 case MSR_IA32_MCG_STATUS:
1773 data = vcpu->arch.mcg_status;
1774 break;
1775 default:
1776 if (msr >= MSR_IA32_MC0_CTL &&
1777 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1778 u32 offset = msr - MSR_IA32_MC0_CTL;
1779 data = vcpu->arch.mce_banks[offset];
1780 break;
1781 }
1782 return 1;
1783 }
1784 *pdata = data;
1785 return 0;
1786}
1787
55cd8e5a
GN		 1788static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1789{
1790 u64 data = 0;
1791 struct kvm *kvm = vcpu->kvm;
1792
1793 switch (msr) {
1794 case HV_X64_MSR_GUEST_OS_ID:
1795 data = kvm->arch.hv_guest_os_id;
1796 break;
1797 case HV_X64_MSR_HYPERCALL:
1798 data = kvm->arch.hv_hypercall;
1799 break;
1800 default:
1801 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1802 return 1;
1803 }
1804
1805 *pdata = data;
1806 return 0;
1807}
1808
1809static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1810{
1811 u64 data = 0;
1812
1813 switch (msr) {
1814 case HV_X64_MSR_VP_INDEX: {
1815 int r;
1816 struct kvm_vcpu *v;
1817 kvm_for_each_vcpu(r, v, vcpu->kvm)
1818 if (v == vcpu)
1819 data = r;
1820 break;
1821 }
10388a07
GN		 1822 case HV_X64_MSR_EOI:
1823 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1824 case HV_X64_MSR_ICR:
1825 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1826 case HV_X64_MSR_TPR:
1827 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 1828 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 1829 data = vcpu->arch.hv_vapic;
1830 break;
55cd8e5a
GN		 1831 default:
1832 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1833 return 1;
1834 }
1835 *pdata = data;
1836 return 0;
1837}
1838
890ca9ae
HY		 1839int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1840{
1841 u64 data;
1842
1843 switch (msr) {
890ca9ae 1844 case MSR_IA32_PLATFORM_ID:
15c4a640 1845 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1846 case MSR_IA32_DEBUGCTLMSR:
1847 case MSR_IA32_LASTBRANCHFROMIP:
1848 case MSR_IA32_LASTBRANCHTOIP:
1849 case MSR_IA32_LASTINTFROMIP:
1850 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1851 case MSR_K8_SYSCFG:
1852 case MSR_K7_HWCR:
61a6bd67 1853 case MSR_VM_HSAVE_PA:
1f3ee616
AS		 1854 case MSR_P6_PERFCTR0:
1855 case MSR_P6_PERFCTR1:
7fe29e0f
AS		 1856 case MSR_P6_EVNTSEL0:
1857 case MSR_P6_EVNTSEL1:
9e699624 1858 case MSR_K7_EVNTSEL0:
1f3ee616 1859 case MSR_K7_PERFCTR0:
1fdbd48c 1860 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1861 case MSR_AMD64_NB_CFG:
f7c6d140 1862 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1863 data = 0;
1864 break;
742bc670
MT		 1865 case MSR_IA32_UCODE_REV:
1866 data = 0x100000000ULL;
1867 break;
9ba075a6
AK		 1868 case MSR_MTRRcap:
1869 data = 0x500 | KVM_NR_VAR_MTRR;
1870 break;
1871 case 0x200 ... 0x2ff:
1872 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1873 case 0xcd: /* fsb frequency */
1874 data = 3;
1875 break;
7b914098
JS		 1876 /*
1877 * MSR_EBC_FREQUENCY_ID
1878 * Conservative value valid for even the basic CPU models.
1879 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
1880 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
1881 * and 266MHz for model 3, or 4. Set Core Clock
1882 * Frequency to System Bus Frequency Ratio to 1 (bits
1883 * 31:24) even though these are only valid for CPU
1884 * models > 2, however guests may end up dividing or
1885 * multiplying by zero otherwise.
1886 */
1887 case MSR_EBC_FREQUENCY_ID:
1888 data = 1 << 24;
1889 break;
15c4a640
CO		 1890 case MSR_IA32_APICBASE:
1891 data = kvm_get_apic_base(vcpu);
1892 break;
0105d1a5
GN		 1893 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1894 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1895 break;
15c4a640 1896 case MSR_IA32_MISC_ENABLE:
ad312c7c 1897 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1898 break;
847f0ad8
AG		 1899 case MSR_IA32_PERF_STATUS:
1900 /* TSC increment by tick */
1901 data = 1000ULL;
1902 /* CPU multiplier */
1903 data |= (((uint64_t)4ULL) << 40);
1904 break;
15c4a640 1905 case MSR_EFER:
f6801dff 1906 data = vcpu->arch.efer;
15c4a640 1907 break;
18068523 1908 case MSR_KVM_WALL_CLOCK:
11c6bffa 1909 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1910 data = vcpu->kvm->arch.wall_clock;
1911 break;
1912 case MSR_KVM_SYSTEM_TIME:
11c6bffa 1913 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1914 data = vcpu->arch.time;
1915 break;
344d9588
GN		 1916 case MSR_KVM_ASYNC_PF_EN:
1917 data = vcpu->arch.apf.msr_val;
1918 break;
c9aaa895
GC		 1919 case MSR_KVM_STEAL_TIME:
1920 data = vcpu->arch.st.msr_val;
1921 break;
890ca9ae
HY		 1922 case MSR_IA32_P5_MC_ADDR:
1923 case MSR_IA32_P5_MC_TYPE:
1924 case MSR_IA32_MCG_CAP:
1925 case MSR_IA32_MCG_CTL:
1926 case MSR_IA32_MCG_STATUS:
1927 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1928 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 1929 case MSR_K7_CLK_CTL:
1930 /*
1931 * Provide expected ramp-up count for K7. All other
1932 * are set to zero, indicating minimum divisors for
1933 * every field.
1934 *
1935 * This prevents guest kernels on AMD host with CPU
1936 * type 6, model 8 and higher from exploding due to
1937 * the rdmsr failing.
1938 */
1939 data = 0x20000000;
1940 break;
55cd8e5a
GN		 1941 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1942 if (kvm_hv_msr_partition_wide(msr)) {
1943 int r;
1944 mutex_lock(&vcpu->kvm->lock);
1945 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1946 mutex_unlock(&vcpu->kvm->lock);
1947 return r;
1948 } else
1949 return get_msr_hyperv(vcpu, msr, pdata);
1950 break;
91c9c3ed 1951 case MSR_IA32_BBL_CR_CTL3:
1952 /* This legacy MSR exists but isn't fully documented in current
1953 * silicon. It is however accessed by winxp in very narrow
1954 * scenarios where it sets bit #19, itself documented as
1955 * a "reserved" bit. Best effort attempt to source coherent
1956 * read data here should the balance of the register be
1957 * interpreted by the guest:
1958 *
1959 * L2 cache control register 3: 64GB range, 256KB size,
1960 * enabled, latency 0x1, configured
1961 */
1962 data = 0xbe702111;
1963 break;
15c4a640 1964 default:
ed85c068
AP		 1965 if (!ignore_msrs) {
1966 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1967 return 1;
1968 } else {
1969 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1970 data = 0;
1971 }
1972 break;
15c4a640
CO		 1973 }
1974 *pdata = data;
1975 return 0;
1976}
1977EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1978
313a3dc7
CO		 1979/*
1980 * Read or write a bunch of msrs. All parameters are kernel addresses.
1981 *
1982 * @return number of msrs set successfully.
1983 */
1984static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1985 struct kvm_msr_entry *entries,
1986 int (*do_msr)(struct kvm_vcpu *vcpu,
1987 unsigned index, u64 *data))
1988{
f656ce01 1989 int i, idx;
313a3dc7 1990
f656ce01 1991 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 1992 for (i = 0; i < msrs->nmsrs; ++i)
1993 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1994 break;
f656ce01 1995 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 1996
313a3dc7
CO		 1997 return i;
1998}
1999
2000/*
2001 * Read or write a bunch of msrs. Parameters are user addresses.
2002 *
2003 * @return number of msrs set successfully.
2004 */
2005static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2006 int (*do_msr)(struct kvm_vcpu *vcpu,
2007 unsigned index, u64 *data),
2008 int writeback)
2009{
2010 struct kvm_msrs msrs;
2011 struct kvm_msr_entry *entries;
2012 int r, n;
2013 unsigned size;
2014
2015 r = -EFAULT;
2016 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2017 goto out;
2018
2019 r = -E2BIG;
2020 if (msrs.nmsrs >= MAX_IO_MSRS)
2021 goto out;
2022
2023 r = -ENOMEM;
2024 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
7a73c028 2025 entries = kmalloc(size, GFP_KERNEL);
313a3dc7
CO		 2026 if (!entries)
2027 goto out;
2028
2029 r = -EFAULT;
2030 if (copy_from_user(entries, user_msrs->entries, size))
2031 goto out_free;
2032
2033 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2034 if (r < 0)
2035 goto out_free;
2036
2037 r = -EFAULT;
2038 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2039 goto out_free;
2040
2041 r = n;
2042
2043out_free:
7a73c028 2044 kfree(entries);
313a3dc7
CO		 2045out:
2046 return r;
2047}
2048
018d00d2
ZX		 2049int kvm_dev_ioctl_check_extension(long ext)
2050{
2051 int r;
2052
2053 switch (ext) {
2054 case KVM_CAP_IRQCHIP:
2055 case KVM_CAP_HLT:
2056 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2057 case KVM_CAP_SET_TSS_ADDR:
07716717 2058 case KVM_CAP_EXT_CPUID:
c8076604 2059 case KVM_CAP_CLOCKSOURCE:
7837699f 2060 case KVM_CAP_PIT:
a28e4f5a 2061 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2062 case KVM_CAP_MP_STATE:
ed848624 2063 case KVM_CAP_SYNC_MMU:
a355c85c 2064 case KVM_CAP_USER_NMI:
52d939a0 2065 case KVM_CAP_REINJECT_CONTROL:
4925663a 2066 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 2067 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 2068 case KVM_CAP_IRQFD:
d34e6b17 2069 case KVM_CAP_IOEVENTFD:
c5ff41ce 2070 case KVM_CAP_PIT2:
e9f42757 2071 case KVM_CAP_PIT_STATE2:
b927a3ce 2072 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2073 case KVM_CAP_XEN_HVM:
afbcf7ab 2074 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2075 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2076 case KVM_CAP_HYPERV:
10388a07 2077 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2078 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2079 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2080 case KVM_CAP_DEBUGREGS:
d2be1651 2081 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2082 case KVM_CAP_XSAVE:
344d9588 2083 case KVM_CAP_ASYNC_PF:
92a1f12d 2084 case KVM_CAP_GET_TSC_KHZ:
018d00d2
ZX		 2085 r = 1;
2086 break;
542472b5
LV		 2087 case KVM_CAP_COALESCED_MMIO:
2088 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2089 break;
774ead3a
AK		 2090 case KVM_CAP_VAPIC:
2091 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2092 break;
f725230a 2093 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2094 r = KVM_SOFT_MAX_VCPUS;
2095 break;
2096 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2097 r = KVM_MAX_VCPUS;
2098 break;
a988b910
AK		 2099 case KVM_CAP_NR_MEMSLOTS:
2100 r = KVM_MEMORY_SLOTS;
2101 break;
a68a6a72
MT		 2102 case KVM_CAP_PV_MMU: /* obsolete */
2103 r = 0;
2f333bcb 2104 break;
62c476c7 2105 case KVM_CAP_IOMMU:
19de40a8 2106 r = iommu_found();
62c476c7 2107 break;
890ca9ae
HY		 2108 case KVM_CAP_MCE:
2109 r = KVM_MAX_MCE_BANKS;
2110 break;
2d5b5a66
SY		 2111 case KVM_CAP_XCRS:
2112 r = cpu_has_xsave;
2113 break;
92a1f12d
JR		 2114 case KVM_CAP_TSC_CONTROL:
2115 r = kvm_has_tsc_control;
2116 break;
018d00d2
ZX		 2117 default:
2118 r = 0;
2119 break;
2120 }
2121 return r;
2122
2123}
2124
043405e1
CO		 2125long kvm_arch_dev_ioctl(struct file *filp,
2126 unsigned int ioctl, unsigned long arg)
2127{
2128 void __user *argp = (void __user *)arg;
2129 long r;
2130
2131 switch (ioctl) {
2132 case KVM_GET_MSR_INDEX_LIST: {
2133 struct kvm_msr_list __user *user_msr_list = argp;
2134 struct kvm_msr_list msr_list;
2135 unsigned n;
2136
2137 r = -EFAULT;
2138 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2139 goto out;
2140 n = msr_list.nmsrs;
2141 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2142 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2143 goto out;
2144 r = -E2BIG;
e125e7b6 2145 if (n < msr_list.nmsrs)
043405e1
CO		 2146 goto out;
2147 r = -EFAULT;
2148 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2149 num_msrs_to_save * sizeof(u32)))
2150 goto out;
e125e7b6 2151 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2152 &emulated_msrs,
2153 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2154 goto out;
2155 r = 0;
2156 break;
2157 }
674eea0f
AK		 2158 case KVM_GET_SUPPORTED_CPUID: {
2159 struct kvm_cpuid2 __user *cpuid_arg = argp;
2160 struct kvm_cpuid2 cpuid;
2161
2162 r = -EFAULT;
2163 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2164 goto out;
2165 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 2166 cpuid_arg->entries);
674eea0f
AK		 2167 if (r)
2168 goto out;
2169
2170 r = -EFAULT;
2171 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2172 goto out;
2173 r = 0;
2174 break;
2175 }
890ca9ae
HY		 2176 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2177 u64 mce_cap;
2178
2179 mce_cap = KVM_MCE_CAP_SUPPORTED;
2180 r = -EFAULT;
2181 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2182 goto out;
2183 r = 0;
2184 break;
2185 }
043405e1
CO		 2186 default:
2187 r = -EINVAL;
2188 }
2189out:
2190 return r;
2191}
2192
f5f48ee1
SY		 2193static void wbinvd_ipi(void *garbage)
2194{
2195 wbinvd();
2196}
2197
2198static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2199{
2200 return vcpu->kvm->arch.iommu_domain &&
2201 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2202}
2203
313a3dc7
CO		 2204void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2205{
f5f48ee1
SY		 2206 /* Address WBINVD may be executed by guest */
2207 if (need_emulate_wbinvd(vcpu)) {
2208 if (kvm_x86_ops->has_wbinvd_exit())
2209 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2210 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2211 smp_call_function_single(vcpu->cpu,
2212 wbinvd_ipi, NULL, 1);
2213 }
2214
313a3dc7 2215 kvm_x86_ops->vcpu_load(vcpu, cpu);
48434c20 2216 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
e48672fa 2217 /* Make sure TSC doesn't go backwards */
8f6055cb
JR		 2218 s64 tsc_delta;
2219 u64 tsc;
2220
2221 kvm_get_msr(vcpu, MSR_IA32_TSC, &tsc);
2222 tsc_delta = !vcpu->arch.last_guest_tsc ? 0 :
2223 tsc - vcpu->arch.last_guest_tsc;
2224
e48672fa
ZA		 2225 if (tsc_delta < 0)
2226 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2227 if (check_tsc_unstable()) {
e48672fa 2228 kvm_x86_ops->adjust_tsc_offset(vcpu, -tsc_delta);
c285545f 2229 vcpu->arch.tsc_catchup = 1;
c285545f 2230 }
1aa8ceef 2231 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2232 if (vcpu->cpu != cpu)
2233 kvm_migrate_timers(vcpu);
e48672fa 2234 vcpu->cpu = cpu;
6b7d7e76 2235 }
c9aaa895
GC		 2236
2237 accumulate_steal_time(vcpu);
2238 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2239}
2240
2241void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2242{
02daab21 2243 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2244 kvm_put_guest_fpu(vcpu);
7c4c0f4f 2245 kvm_get_msr(vcpu, MSR_IA32_TSC, &vcpu->arch.last_guest_tsc);
313a3dc7
CO		 2246}
2247
07716717 2248static int is_efer_nx(void)
313a3dc7 2249{
e286e86e 2250 unsigned long long efer = 0;
313a3dc7 2251
e286e86e 2252 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 2253 return efer & EFER_NX;
2254}
2255
2256static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
2257{
2258 int i;
2259 struct kvm_cpuid_entry2 *e, *entry;
2260
313a3dc7 2261 entry = NULL;
ad312c7c
ZX		 2262 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
2263 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 2264 if (e->function == 0x80000001) {
2265 entry = e;
2266 break;
2267 }
2268 }
07716717 2269 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 2270 entry->edx &= ~(1 << 20);
2271 printk(KERN_INFO "kvm: guest NX capability removed\n");
2272 }
2273}
2274
07716717 2275/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 2276static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
2277 struct kvm_cpuid *cpuid,
2278 struct kvm_cpuid_entry __user *entries)
07716717
DK		 2279{
2280 int r, i;
2281 struct kvm_cpuid_entry *cpuid_entries;
2282
2283 r = -E2BIG;
2284 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2285 goto out;
2286 r = -ENOMEM;
2287 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
2288 if (!cpuid_entries)
2289 goto out;
2290 r = -EFAULT;
2291 if (copy_from_user(cpuid_entries, entries,
2292 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
2293 goto out_free;
2294 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 2295 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
2296 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
2297 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
2298 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
2299 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
2300 vcpu->arch.cpuid_entries[i].index = 0;
2301 vcpu->arch.cpuid_entries[i].flags = 0;
2302 vcpu->arch.cpuid_entries[i].padding[0] = 0;
2303 vcpu->arch.cpuid_entries[i].padding[1] = 0;
2304 vcpu->arch.cpuid_entries[i].padding[2] = 0;
2305 }
2306 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 2307 cpuid_fix_nx_cap(vcpu);
2308 r = 0;
fc61b800 2309 kvm_apic_set_version(vcpu);
0e851880 2310 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 2311 update_cpuid(vcpu);
07716717
DK		 2312
2313out_free:
2314 vfree(cpuid_entries);
2315out:
2316 return r;
2317}
2318
2319static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 2320 struct kvm_cpuid2 *cpuid,
2321 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 2322{
2323 int r;
2324
2325 r = -E2BIG;
2326 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2327 goto out;
2328 r = -EFAULT;
ad312c7c 2329 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 2330 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 2331 goto out;
ad312c7c 2332 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 2333 kvm_apic_set_version(vcpu);
0e851880 2334 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 2335 update_cpuid(vcpu);
313a3dc7
CO		 2336 return 0;
2337
2338out:
2339 return r;
2340}
2341
07716717 2342static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 2343 struct kvm_cpuid2 *cpuid,
2344 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2345{
2346 int r;
2347
2348 r = -E2BIG;
ad312c7c 2349 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 2350 goto out;
2351 r = -EFAULT;
ad312c7c 2352 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 2353 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2354 goto out;
2355 return 0;
2356
2357out:
ad312c7c 2358 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 2359 return r;
2360}
2361
945ee35e
AK		 2362static void cpuid_mask(u32 *word, int wordnum)
2363{
2364 *word &= boot_cpu_data.x86_capability[wordnum];
2365}
2366
07716717 2367static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 2368 u32 index)
07716717
DK		 2369{
2370 entry->function = function;
2371 entry->index = index;
2372 cpuid_count(entry->function, entry->index,
19355475 2373 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 2374 entry->flags = 0;
2375}
2376
24c82e57
AK		 2377static bool supported_xcr0_bit(unsigned bit)
2378{
2379 u64 mask = ((u64)1 << bit);
2380
2381 return mask & (XSTATE_FP | XSTATE_SSE | XSTATE_YMM) & host_xcr0;
2382}
2383
7faa4ee1
AK		 2384#define F(x) bit(X86_FEATURE_##x)
2385
07716717
DK		 2386static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
2387 u32 index, int *nent, int maxnent)
2388{
7faa4ee1 2389 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 2390#ifdef CONFIG_X86_64
17cc3935
SY		 2391 unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
2392 ? F(GBPAGES) : 0;
7faa4ee1
AK		 2393 unsigned f_lm = F(LM);
2394#else
17cc3935 2395 unsigned f_gbpages = 0;
7faa4ee1 2396 unsigned f_lm = 0;
07716717 2397#endif
4e47c7a6 2398 unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
7faa4ee1
AK		 2399
2400 /* cpuid 1.edx */
2401 const u32 kvm_supported_word0_x86_features =
2402 F(FPU) | F(VME) | F(DE) | F(PSE) |
2403 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2404 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
2405 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2406 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
2407 0 /* Reserved, DS, ACPI */ | F(MMX) |
2408 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
2409 0 /* HTT, TM, Reserved, PBE */;
2410 /* cpuid 0x80000001.edx */
2411 const u32 kvm_supported_word1_x86_features =
2412 F(FPU) | F(VME) | F(DE) | F(PSE) |
2413 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2414 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
2415 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2416 F(PAT) | F(PSE36) | 0 /* Reserved */ |
2417 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
4e47c7a6 2418 F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
7faa4ee1
AK		 2419 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
2420 /* cpuid 1.ecx */
2421 const u32 kvm_supported_word4_x86_features =
6c3f6041 2422 F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ |
d149c731
AK		 2423 0 /* DS-CPL, VMX, SMX, EST */ |
2424 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
2425 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
2426 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 2427 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
6d886fd0 2428 0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) |
4a00efdf 2429 F(F16C) | F(RDRAND);
7faa4ee1 2430 /* cpuid 0x80000001.ecx */
07716717 2431 const u32 kvm_supported_word6_x86_features =
4c62a2dc 2432 F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ |
7faa4ee1 2433 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
7ef8aa72 2434 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(XOP) |
6d886fd0 2435 0 /* SKINIT, WDT, LWP */ | F(FMA4) | F(TBM);
07716717 2436
4429d5dc
B		 2437 /* cpuid 0xC0000001.edx */
2438 const u32 kvm_supported_word5_x86_features =
2439 F(XSTORE) | F(XSTORE_EN) | F(XCRYPT) | F(XCRYPT_EN) |
2440 F(ACE2) | F(ACE2_EN) | F(PHE) | F(PHE_EN) |
2441 F(PMM) | F(PMM_EN);
2442
611c120f
YW		 2443 /* cpuid 7.0.ebx */
2444 const u32 kvm_supported_word9_x86_features =
a01c8f9b 2445 F(SMEP) | F(FSGSBASE) | F(ERMS);
611c120f 2446
19355475 2447 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 2448 get_cpu();
2449 do_cpuid_1_ent(entry, function, index);
2450 ++*nent;
2451
2452 switch (function) {
2453 case 0:
2acf923e 2454 entry->eax = min(entry->eax, (u32)0xd);
07716717
DK		 2455 break;
2456 case 1:
2457 entry->edx &= kvm_supported_word0_x86_features;
945ee35e 2458 cpuid_mask(&entry->edx, 0);
7faa4ee1 2459 entry->ecx &= kvm_supported_word4_x86_features;
945ee35e 2460 cpuid_mask(&entry->ecx, 4);
0d1de2d9
GN		 2461 /* we support x2apic emulation even if host does not support
2462 * it since we emulate x2apic in software */
2463 entry->ecx |= F(X2APIC);
07716717
DK		 2464 break;
2465 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
2466 * may return different values. This forces us to get_cpu() before
2467 * issuing the first command, and also to emulate this annoying behavior
2468 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
2469 case 2: {
2470 int t, times = entry->eax & 0xff;
2471
2472 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 2473 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 2474 for (t = 1; t < times && *nent < maxnent; ++t) {
2475 do_cpuid_1_ent(&entry[t], function, 0);
2476 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
2477 ++*nent;
2478 }
2479 break;
2480 }
611c120f 2481 /* function 4 has additional index. */
07716717 2482 case 4: {
14af3f3c 2483 int i, cache_type;
07716717
DK		 2484
2485 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2486 /* read more entries until cache_type is zero */
14af3f3c
HH		 2487 for (i = 1; *nent < maxnent; ++i) {
2488 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 2489 if (!cache_type)
2490 break;
14af3f3c
HH		 2491 do_cpuid_1_ent(&entry[i], function, i);
2492 entry[i].flags |=
07716717
DK		 2493 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2494 ++*nent;
2495 }
2496 break;
2497 }
611c120f
YW		 2498 case 7: {
2499 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2500 /* Mask ebx against host capbability word 9 */
2501 if (index == 0) {
2502 entry->ebx &= kvm_supported_word9_x86_features;
2503 cpuid_mask(&entry->ebx, 9);
2504 } else
2505 entry->ebx = 0;
2506 entry->eax = 0;
2507 entry->ecx = 0;
2508 entry->edx = 0;
2509 break;
2510 }
24c82e57
AK		 2511 case 9:
2512 break;
611c120f 2513 /* function 0xb has additional index. */
07716717 2514 case 0xb: {
14af3f3c 2515 int i, level_type;
07716717
DK		 2516
2517 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2518 /* read more entries until level_type is zero */
14af3f3c 2519 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 2520 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 2521 if (!level_type)
2522 break;
14af3f3c
HH		 2523 do_cpuid_1_ent(&entry[i], function, i);
2524 entry[i].flags |=
07716717
DK		 2525 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2526 ++*nent;
2527 }
2528 break;
2529 }
2acf923e 2530 case 0xd: {
02668b06 2531 int idx, i;
2acf923e
DC		 2532
2533 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
02668b06
AP		 2534 for (idx = 1, i = 1; *nent < maxnent && idx < 64; ++idx) {
2535 do_cpuid_1_ent(&entry[i], function, idx);
2536 if (entry[i].eax == 0 || !supported_xcr0_bit(idx))
20800bc9 2537 continue;
2acf923e
DC		 2538 entry[i].flags |=
2539 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2540 ++*nent;
02668b06 2541 ++i;
2acf923e
DC		 2542 }
2543 break;
2544 }
84478c82
GC		 2545 case KVM_CPUID_SIGNATURE: {
2546 char signature[12] = "KVMKVMKVM\0\0";
2547 u32 *sigptr = (u32 *)signature;
2548 entry->eax = 0;
2549 entry->ebx = sigptr[0];
2550 entry->ecx = sigptr[1];
2551 entry->edx = sigptr[2];
2552 break;
2553 }
2554 case KVM_CPUID_FEATURES:
2555 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) |
2556 (1 << KVM_FEATURE_NOP_IO_DELAY) |
371bcf64 2557 (1 << KVM_FEATURE_CLOCKSOURCE2) |
32918924 2558 (1 << KVM_FEATURE_ASYNC_PF) |
371bcf64 2559 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
c9aaa895
GC		 2560
2561 if (sched_info_on())
2562 entry->eax |= (1 << KVM_FEATURE_STEAL_TIME);
2563
84478c82
GC		 2564 entry->ebx = 0;
2565 entry->ecx = 0;
2566 entry->edx = 0;
2567 break;
07716717
DK		 2568 case 0x80000000:
2569 entry->eax = min(entry->eax, 0x8000001a);
2570 break;
2571 case 0x80000001:
2572 entry->edx &= kvm_supported_word1_x86_features;
945ee35e 2573 cpuid_mask(&entry->edx, 1);
07716717 2574 entry->ecx &= kvm_supported_word6_x86_features;
945ee35e 2575 cpuid_mask(&entry->ecx, 6);
07716717 2576 break;
24c82e57
AK		 2577 case 0x80000008: {
2578 unsigned g_phys_as = (entry->eax >> 16) & 0xff;
2579 unsigned virt_as = max((entry->eax >> 8) & 0xff, 48U);
2580 unsigned phys_as = entry->eax & 0xff;
2581
2582 if (!g_phys_as)
2583 g_phys_as = phys_as;
2584 entry->eax = g_phys_as | (virt_as << 8);
2585 entry->ebx = entry->edx = 0;
2586 break;
2587 }
2588 case 0x80000019:
2589 entry->ecx = entry->edx = 0;
2590 break;
2591 case 0x8000001a:
2592 break;
2593 case 0x8000001d:
2594 break;
4429d5dc
B		 2595 /*Add support for Centaur's CPUID instruction*/
2596 case 0xC0000000:
2597 /*Just support up to 0xC0000004 now*/
2598 entry->eax = min(entry->eax, 0xC0000004);
2599 break;
2600 case 0xC0000001:
2601 entry->edx &= kvm_supported_word5_x86_features;
2602 cpuid_mask(&entry->edx, 5);
2603 break;
24c82e57
AK		 2604 case 3: /* Processor serial number */
2605 case 5: /* MONITOR/MWAIT */
2606 case 6: /* Thermal management */
2607 case 0xA: /* Architectural Performance Monitoring */
2608 case 0x80000007: /* Advanced power management */
4429d5dc
B		 2609 case 0xC0000002:
2610 case 0xC0000003:
2611 case 0xC0000004:
24c82e57
AK		 2612 default:
2613 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
4429d5dc 2614 break;
07716717 2615 }
d4330ef2
JR		 2616
2617 kvm_x86_ops->set_supported_cpuid(function, entry);
2618
07716717
DK		 2619 put_cpu();
2620}
2621
7faa4ee1
AK		 2622#undef F
2623
674eea0f 2624static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 2625 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2626{
2627 struct kvm_cpuid_entry2 *cpuid_entries;
2628 int limit, nent = 0, r = -E2BIG;
2629 u32 func;
2630
2631 if (cpuid->nent < 1)
2632 goto out;
6a544355
AK		 2633 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2634 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
07716717
DK		 2635 r = -ENOMEM;
2636 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
2637 if (!cpuid_entries)
2638 goto out;
2639
2640 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
2641 limit = cpuid_entries[0].eax;
2642 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
2643 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2644 &nent, cpuid->nent);
07716717
DK		 2645 r = -E2BIG;
2646 if (nent >= cpuid->nent)
2647 goto out_free;
2648
2649 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
2650 limit = cpuid_entries[nent - 1].eax;
2651 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
2652 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2653 &nent, cpuid->nent);
84478c82
GC		 2654
2655
2656
2657 r = -E2BIG;
2658 if (nent >= cpuid->nent)
2659 goto out_free;
2660
4429d5dc
B		 2661 /* Add support for Centaur's CPUID instruction. */
2662 if (boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR) {
2663 do_cpuid_ent(&cpuid_entries[nent], 0xC0000000, 0,
2664 &nent, cpuid->nent);
2665
2666 r = -E2BIG;
2667 if (nent >= cpuid->nent)
2668 goto out_free;
2669
2670 limit = cpuid_entries[nent - 1].eax;
2671 for (func = 0xC0000001;
2672 func <= limit && nent < cpuid->nent; ++func)
2673 do_cpuid_ent(&cpuid_entries[nent], func, 0,
2674 &nent, cpuid->nent);
2675
2676 r = -E2BIG;
2677 if (nent >= cpuid->nent)
2678 goto out_free;
2679 }
2680
84478c82
GC		 2681 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_SIGNATURE, 0, &nent,
2682 cpuid->nent);
2683
2684 r = -E2BIG;
2685 if (nent >= cpuid->nent)
2686 goto out_free;
2687
2688 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_FEATURES, 0, &nent,
2689 cpuid->nent);
2690
cb007648
MM		 2691 r = -E2BIG;
2692 if (nent >= cpuid->nent)
2693 goto out_free;
2694
07716717
DK		 2695 r = -EFAULT;
2696 if (copy_to_user(entries, cpuid_entries,
19355475 2697 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2698 goto out_free;
2699 cpuid->nent = nent;
2700 r = 0;
2701
2702out_free:
2703 vfree(cpuid_entries);
2704out:
2705 return r;
2706}
2707
313a3dc7
CO		 2708static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2709 struct kvm_lapic_state *s)
2710{
ad312c7c 2711 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2712
2713 return 0;
2714}
2715
2716static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2717 struct kvm_lapic_state *s)
2718{
ad312c7c 2719 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 2720 kvm_apic_post_state_restore(vcpu);
cb142eb7 2721 update_cr8_intercept(vcpu);
313a3dc7
CO		 2722
2723 return 0;
2724}
2725
f77bc6a4
ZX		 2726static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2727 struct kvm_interrupt *irq)
2728{
2729 if (irq->irq < 0 || irq->irq >= 256)
2730 return -EINVAL;
2731 if (irqchip_in_kernel(vcpu->kvm))
2732 return -ENXIO;
f77bc6a4 2733
66fd3f7f 2734 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2735 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2736
f77bc6a4
ZX		 2737 return 0;
2738}
2739
c4abb7c9
JK		 2740static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2741{
c4abb7c9 2742 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2743
2744 return 0;
2745}
2746
b209749f
AK		 2747static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2748 struct kvm_tpr_access_ctl *tac)
2749{
2750 if (tac->flags)
2751 return -EINVAL;
2752 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2753 return 0;
2754}
2755
890ca9ae
HY		 2756static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2757 u64 mcg_cap)
2758{
2759 int r;
2760 unsigned bank_num = mcg_cap & 0xff, bank;
2761
2762 r = -EINVAL;
a9e38c3e 2763 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2764 goto out;
2765 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2766 goto out;
2767 r = 0;
2768 vcpu->arch.mcg_cap = mcg_cap;
2769 /* Init IA32_MCG_CTL to all 1s */
2770 if (mcg_cap & MCG_CTL_P)
2771 vcpu->arch.mcg_ctl = ~(u64)0;
2772 /* Init IA32_MCi_CTL to all 1s */
2773 for (bank = 0; bank < bank_num; bank++)
2774 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2775out:
2776 return r;
2777}
2778
2779static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2780 struct kvm_x86_mce *mce)
2781{
2782 u64 mcg_cap = vcpu->arch.mcg_cap;
2783 unsigned bank_num = mcg_cap & 0xff;
2784 u64 *banks = vcpu->arch.mce_banks;
2785
2786 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2787 return -EINVAL;
2788 /*
2789 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2790 * reporting is disabled
2791 */
2792 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2793 vcpu->arch.mcg_ctl != ~(u64)0)
2794 return 0;
2795 banks += 4 * mce->bank;
2796 /*
2797 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2798 * reporting is disabled for the bank
2799 */
2800 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2801 return 0;
2802 if (mce->status & MCI_STATUS_UC) {
2803 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2804 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2805 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2806 return 0;
2807 }
2808 if (banks[1] & MCI_STATUS_VAL)
2809 mce->status |= MCI_STATUS_OVER;
2810 banks[2] = mce->addr;
2811 banks[3] = mce->misc;
2812 vcpu->arch.mcg_status = mce->mcg_status;
2813 banks[1] = mce->status;
2814 kvm_queue_exception(vcpu, MC_VECTOR);
2815 } else if (!(banks[1] & MCI_STATUS_VAL)
2816 || !(banks[1] & MCI_STATUS_UC)) {
2817 if (banks[1] & MCI_STATUS_VAL)
2818 mce->status |= MCI_STATUS_OVER;
2819 banks[2] = mce->addr;
2820 banks[3] = mce->misc;
2821 banks[1] = mce->status;
2822 } else
2823 banks[1] |= MCI_STATUS_OVER;
2824 return 0;
2825}
2826
3cfc3092
JK		 2827static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2828 struct kvm_vcpu_events *events)
2829{
03b82a30
JK		 2830 events->exception.injected =
2831 vcpu->arch.exception.pending &&
2832 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2833 events->exception.nr = vcpu->arch.exception.nr;
2834 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2835 events->exception.pad = 0;
3cfc3092
JK		 2836 events->exception.error_code = vcpu->arch.exception.error_code;
2837
03b82a30
JK		 2838 events->interrupt.injected =
2839 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2840 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2841 events->interrupt.soft = 0;
48005f64
JK		 2842 events->interrupt.shadow =
2843 kvm_x86_ops->get_interrupt_shadow(vcpu,
2844 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2845
2846 events->nmi.injected = vcpu->arch.nmi_injected;
2847 events->nmi.pending = vcpu->arch.nmi_pending;
2848 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2849 events->nmi.pad = 0;
3cfc3092
JK		 2850
2851 events->sipi_vector = vcpu->arch.sipi_vector;
2852
dab4b911 2853 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2854 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2855 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 2856 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2857}
2858
2859static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2860 struct kvm_vcpu_events *events)
2861{
dab4b911 2862 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2863 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2864 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2865 return -EINVAL;
2866
3cfc3092
JK		 2867 vcpu->arch.exception.pending = events->exception.injected;
2868 vcpu->arch.exception.nr = events->exception.nr;
2869 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2870 vcpu->arch.exception.error_code = events->exception.error_code;
2871
2872 vcpu->arch.interrupt.pending = events->interrupt.injected;
2873 vcpu->arch.interrupt.nr = events->interrupt.nr;
2874 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2875 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2876 kvm_x86_ops->set_interrupt_shadow(vcpu,
2877 events->interrupt.shadow);
3cfc3092
JK		 2878
2879 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2880 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2881 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2882 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2883
dab4b911
JK		 2884 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2885 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092 2886
3842d135
AK		 2887 kvm_make_request(KVM_REQ_EVENT, vcpu);
2888
3cfc3092
JK		 2889 return 0;
2890}
2891
a1efbe77
JK		 2892static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2893 struct kvm_debugregs *dbgregs)
2894{
a1efbe77
JK		 2895 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2896 dbgregs->dr6 = vcpu->arch.dr6;
2897 dbgregs->dr7 = vcpu->arch.dr7;
2898 dbgregs->flags = 0;
97e69aa6 2899 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 2900}
2901
2902static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2903 struct kvm_debugregs *dbgregs)
2904{
2905 if (dbgregs->flags)
2906 return -EINVAL;
2907
a1efbe77
JK		 2908 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2909 vcpu->arch.dr6 = dbgregs->dr6;
2910 vcpu->arch.dr7 = dbgregs->dr7;
2911
a1efbe77
JK		 2912 return 0;
2913}
2914
2d5b5a66
SY		 2915static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2916 struct kvm_xsave *guest_xsave)
2917{
2918 if (cpu_has_xsave)
2919 memcpy(guest_xsave->region,
2920 &vcpu->arch.guest_fpu.state->xsave,
f45755b8 2921 xstate_size);
2d5b5a66
SY		 2922 else {
2923 memcpy(guest_xsave->region,
2924 &vcpu->arch.guest_fpu.state->fxsave,
2925 sizeof(struct i387_fxsave_struct));
2926 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2927 XSTATE_FPSSE;
2928 }
2929}
2930
2931static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2932 struct kvm_xsave *guest_xsave)
2933{
2934 u64 xstate_bv =
2935 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2936
2937 if (cpu_has_xsave)
2938 memcpy(&vcpu->arch.guest_fpu.state->xsave,
f45755b8 2939 guest_xsave->region, xstate_size);
2d5b5a66
SY		 2940 else {
2941 if (xstate_bv & ~XSTATE_FPSSE)
2942 return -EINVAL;
2943 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2944 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2945 }
2946 return 0;
2947}
2948
2949static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2950 struct kvm_xcrs *guest_xcrs)
2951{
2952 if (!cpu_has_xsave) {
2953 guest_xcrs->nr_xcrs = 0;
2954 return;
2955 }
2956
2957 guest_xcrs->nr_xcrs = 1;
2958 guest_xcrs->flags = 0;
2959 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2960 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2961}
2962
2963static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2964 struct kvm_xcrs *guest_xcrs)
2965{
2966 int i, r = 0;
2967
2968 if (!cpu_has_xsave)
2969 return -EINVAL;
2970
2971 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2972 return -EINVAL;
2973
2974 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2975 /* Only support XCR0 currently */
2976 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2977 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2978 guest_xcrs->xcrs[0].value);
2979 break;
2980 }
2981 if (r)
2982 r = -EINVAL;
2983 return r;
2984}
2985
313a3dc7
CO		 2986long kvm_arch_vcpu_ioctl(struct file *filp,
2987 unsigned int ioctl, unsigned long arg)
2988{
2989 struct kvm_vcpu *vcpu = filp->private_data;
2990 void __user *argp = (void __user *)arg;
2991 int r;
d1ac91d8
AK		 2992 union {
2993 struct kvm_lapic_state *lapic;
2994 struct kvm_xsave *xsave;
2995 struct kvm_xcrs *xcrs;
2996 void *buffer;
2997 } u;
2998
2999 u.buffer = NULL;
313a3dc7
CO		 3000 switch (ioctl) {
3001 case KVM_GET_LAPIC: {
2204ae3c
MT		 3002 r = -EINVAL;
3003 if (!vcpu->arch.apic)
3004 goto out;
d1ac91d8 3005 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3006
b772ff36 3007 r = -ENOMEM;
d1ac91d8 3008 if (!u.lapic)
b772ff36 3009 goto out;
d1ac91d8 3010 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3011 if (r)
3012 goto out;
3013 r = -EFAULT;
d1ac91d8 3014 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3015 goto out;
3016 r = 0;
3017 break;
3018 }
3019 case KVM_SET_LAPIC: {
2204ae3c
MT		 3020 r = -EINVAL;
3021 if (!vcpu->arch.apic)
3022 goto out;
d1ac91d8 3023 u.lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
b772ff36 3024 r = -ENOMEM;
d1ac91d8 3025 if (!u.lapic)
b772ff36 3026 goto out;
313a3dc7 3027 r = -EFAULT;
d1ac91d8 3028 if (copy_from_user(u.lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 3029 goto out;
d1ac91d8 3030 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3031 if (r)
3032 goto out;
3033 r = 0;
3034 break;
3035 }
f77bc6a4
ZX		 3036 case KVM_INTERRUPT: {
3037 struct kvm_interrupt irq;
3038
3039 r = -EFAULT;
3040 if (copy_from_user(&irq, argp, sizeof irq))
3041 goto out;
3042 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3043 if (r)
3044 goto out;
3045 r = 0;
3046 break;
3047 }
c4abb7c9
JK		 3048 case KVM_NMI: {
3049 r = kvm_vcpu_ioctl_nmi(vcpu);
3050 if (r)
3051 goto out;
3052 r = 0;
3053 break;
3054 }
313a3dc7
CO		 3055 case KVM_SET_CPUID: {
3056 struct kvm_cpuid __user *cpuid_arg = argp;
3057 struct kvm_cpuid cpuid;
3058
3059 r = -EFAULT;
3060 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3061 goto out;
3062 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3063 if (r)
3064 goto out;
3065 break;
3066 }
07716717
DK		 3067 case KVM_SET_CPUID2: {
3068 struct kvm_cpuid2 __user *cpuid_arg = argp;
3069 struct kvm_cpuid2 cpuid;
3070
3071 r = -EFAULT;
3072 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3073 goto out;
3074 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3075 cpuid_arg->entries);
07716717
DK		 3076 if (r)
3077 goto out;
3078 break;
3079 }
3080 case KVM_GET_CPUID2: {
3081 struct kvm_cpuid2 __user *cpuid_arg = argp;
3082 struct kvm_cpuid2 cpuid;
3083
3084 r = -EFAULT;
3085 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3086 goto out;
3087 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3088 cpuid_arg->entries);
07716717
DK		 3089 if (r)
3090 goto out;
3091 r = -EFAULT;
3092 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3093 goto out;
3094 r = 0;
3095 break;
3096 }
313a3dc7
CO		 3097 case KVM_GET_MSRS:
3098 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3099 break;
3100 case KVM_SET_MSRS:
3101 r = msr_io(vcpu, argp, do_set_msr, 0);
3102 break;
b209749f
AK		 3103 case KVM_TPR_ACCESS_REPORTING: {
3104 struct kvm_tpr_access_ctl tac;
3105
3106 r = -EFAULT;
3107 if (copy_from_user(&tac, argp, sizeof tac))
3108 goto out;
3109 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3110 if (r)
3111 goto out;
3112 r = -EFAULT;
3113 if (copy_to_user(argp, &tac, sizeof tac))
3114 goto out;
3115 r = 0;
3116 break;
3117 };
b93463aa
AK		 3118 case KVM_SET_VAPIC_ADDR: {
3119 struct kvm_vapic_addr va;
3120
3121 r = -EINVAL;
3122 if (!irqchip_in_kernel(vcpu->kvm))
3123 goto out;
3124 r = -EFAULT;
3125 if (copy_from_user(&va, argp, sizeof va))
3126 goto out;
3127 r = 0;
3128 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3129 break;
3130 }
890ca9ae
HY		 3131 case KVM_X86_SETUP_MCE: {
3132 u64 mcg_cap;
3133
3134 r = -EFAULT;
3135 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3136 goto out;
3137 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3138 break;
3139 }
3140 case KVM_X86_SET_MCE: {
3141 struct kvm_x86_mce mce;
3142
3143 r = -EFAULT;
3144 if (copy_from_user(&mce, argp, sizeof mce))
3145 goto out;
3146 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3147 break;
3148 }
3cfc3092
JK		 3149 case KVM_GET_VCPU_EVENTS: {
3150 struct kvm_vcpu_events events;
3151
3152 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3153
3154 r = -EFAULT;
3155 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3156 break;
3157 r = 0;
3158 break;
3159 }
3160 case KVM_SET_VCPU_EVENTS: {
3161 struct kvm_vcpu_events events;
3162
3163 r = -EFAULT;
3164 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3165 break;
3166
3167 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3168 break;
3169 }
a1efbe77
JK		 3170 case KVM_GET_DEBUGREGS: {
3171 struct kvm_debugregs dbgregs;
3172
3173 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3174
3175 r = -EFAULT;
3176 if (copy_to_user(argp, &dbgregs,
3177 sizeof(struct kvm_debugregs)))
3178 break;
3179 r = 0;
3180 break;
3181 }
3182 case KVM_SET_DEBUGREGS: {
3183 struct kvm_debugregs dbgregs;
3184
3185 r = -EFAULT;
3186 if (copy_from_user(&dbgregs, argp,
3187 sizeof(struct kvm_debugregs)))
3188 break;
3189
3190 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3191 break;
3192 }
2d5b5a66 3193 case KVM_GET_XSAVE: {
d1ac91d8 3194 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3195 r = -ENOMEM;
d1ac91d8 3196 if (!u.xsave)
2d5b5a66
SY		 3197 break;
3198
d1ac91d8 3199 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3200
3201 r = -EFAULT;
d1ac91d8 3202 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3203 break;
3204 r = 0;
3205 break;
3206 }
3207 case KVM_SET_XSAVE: {
d1ac91d8 3208 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3209 r = -ENOMEM;
d1ac91d8 3210 if (!u.xsave)
2d5b5a66
SY		 3211 break;
3212
3213 r = -EFAULT;
d1ac91d8 3214 if (copy_from_user(u.xsave, argp, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3215 break;
3216
d1ac91d8 3217 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3218 break;
3219 }
3220 case KVM_GET_XCRS: {
d1ac91d8 3221 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3222 r = -ENOMEM;
d1ac91d8 3223 if (!u.xcrs)
2d5b5a66
SY		 3224 break;
3225
d1ac91d8 3226 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3227
3228 r = -EFAULT;
d1ac91d8 3229 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3230 sizeof(struct kvm_xcrs)))
3231 break;
3232 r = 0;
3233 break;
3234 }
3235 case KVM_SET_XCRS: {
d1ac91d8 3236 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3237 r = -ENOMEM;
d1ac91d8 3238 if (!u.xcrs)
2d5b5a66
SY		 3239 break;
3240
3241 r = -EFAULT;
d1ac91d8 3242 if (copy_from_user(u.xcrs, argp,
2d5b5a66
SY		 3243 sizeof(struct kvm_xcrs)))
3244 break;
3245
d1ac91d8 3246 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3247 break;
3248 }
92a1f12d
JR		 3249 case KVM_SET_TSC_KHZ: {
3250 u32 user_tsc_khz;
3251
3252 r = -EINVAL;
3253 if (!kvm_has_tsc_control)
3254 break;
3255
3256 user_tsc_khz = (u32)arg;
3257
3258 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3259 goto out;
3260
3261 kvm_x86_ops->set_tsc_khz(vcpu, user_tsc_khz);
3262
3263 r = 0;
3264 goto out;
3265 }
3266 case KVM_GET_TSC_KHZ: {
3267 r = -EIO;
3268 if (check_tsc_unstable())
3269 goto out;
3270
3271 r = vcpu_tsc_khz(vcpu);
3272
3273 goto out;
3274 }
313a3dc7
CO		 3275 default:
3276 r = -EINVAL;
3277 }
3278out:
d1ac91d8 3279 kfree(u.buffer);
313a3dc7
CO		 3280 return r;
3281}
3282
1fe779f8
CO		 3283static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3284{
3285 int ret;
3286
3287 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3288 return -1;
3289 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3290 return ret;
3291}
3292
b927a3ce
SY		 3293static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3294 u64 ident_addr)
3295{
3296 kvm->arch.ept_identity_map_addr = ident_addr;
3297 return 0;
3298}
3299
1fe779f8
CO		 3300static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3301 u32 kvm_nr_mmu_pages)
3302{
3303 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3304 return -EINVAL;
3305
79fac95e 3306 mutex_lock(&kvm->slots_lock);
7c8a83b7 3307 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 3308
3309 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3310 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3311
7c8a83b7 3312 spin_unlock(&kvm->mmu_lock);
79fac95e 3313 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3314 return 0;
3315}
3316
3317static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3318{
39de71ec 3319 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3320}
3321
1fe779f8
CO		 3322static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3323{
3324 int r;
3325
3326 r = 0;
3327 switch (chip->chip_id) {
3328 case KVM_IRQCHIP_PIC_MASTER:
3329 memcpy(&chip->chip.pic,
3330 &pic_irqchip(kvm)->pics[0],
3331 sizeof(struct kvm_pic_state));
3332 break;
3333 case KVM_IRQCHIP_PIC_SLAVE:
3334 memcpy(&chip->chip.pic,
3335 &pic_irqchip(kvm)->pics[1],
3336 sizeof(struct kvm_pic_state));
3337 break;
3338 case KVM_IRQCHIP_IOAPIC:
eba0226b 3339 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3340 break;
3341 default:
3342 r = -EINVAL;
3343 break;
3344 }
3345 return r;
3346}
3347
3348static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3349{
3350 int r;
3351
3352 r = 0;
3353 switch (chip->chip_id) {
3354 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3355 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3356 memcpy(&pic_irqchip(kvm)->pics[0],
3357 &chip->chip.pic,
3358 sizeof(struct kvm_pic_state));
f4f51050 3359 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3360 break;
3361 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3362 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3363 memcpy(&pic_irqchip(kvm)->pics[1],
3364 &chip->chip.pic,
3365 sizeof(struct kvm_pic_state));
f4f51050 3366 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3367 break;
3368 case KVM_IRQCHIP_IOAPIC:
eba0226b 3369 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3370 break;
3371 default:
3372 r = -EINVAL;
3373 break;
3374 }
3375 kvm_pic_update_irq(pic_irqchip(kvm));
3376 return r;
3377}
3378
e0f63cb9
SY		 3379static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3380{
3381 int r = 0;
3382
894a9c55 3383 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3384 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3385 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3386 return r;
3387}
3388
3389static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3390{
3391 int r = 0;
3392
894a9c55 3393 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3394 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3395 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3396 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3397 return r;
3398}
3399
3400static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3401{
3402 int r = 0;
3403
3404 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3405 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3406 sizeof(ps->channels));
3407 ps->flags = kvm->arch.vpit->pit_state.flags;
3408 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3409 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3410 return r;
3411}
3412
3413static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3414{
3415 int r = 0, start = 0;
3416 u32 prev_legacy, cur_legacy;
3417 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3418 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3419 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3420 if (!prev_legacy && cur_legacy)
3421 start = 1;
3422 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3423 sizeof(kvm->arch.vpit->pit_state.channels));
3424 kvm->arch.vpit->pit_state.flags = ps->flags;
3425 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3426 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3427 return r;
3428}
3429
52d939a0
MT		 3430static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3431 struct kvm_reinject_control *control)
3432{
3433 if (!kvm->arch.vpit)
3434 return -ENXIO;
894a9c55 3435 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 3436 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 3437 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3438 return 0;
3439}
3440
5bb064dc
ZX		 3441/*
3442 * Get (and clear) the dirty memory log for a memory slot.
3443 */
3444int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
3445 struct kvm_dirty_log *log)
3446{
87bf6e7d 3447 int r, i;
5bb064dc 3448 struct kvm_memory_slot *memslot;
87bf6e7d 3449 unsigned long n;
b050b015 3450 unsigned long is_dirty = 0;
5bb064dc 3451
79fac95e 3452 mutex_lock(&kvm->slots_lock);
5bb064dc 3453
b050b015
MT		 3454 r = -EINVAL;
3455 if (log->slot >= KVM_MEMORY_SLOTS)
3456 goto out;
3457
3458 memslot = &kvm->memslots->memslots[log->slot];
3459 r = -ENOENT;
3460 if (!memslot->dirty_bitmap)
3461 goto out;
3462
87bf6e7d 3463 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3464
b050b015
MT		 3465 for (i = 0; !is_dirty && i < n/sizeof(long); i++)
3466 is_dirty = memslot->dirty_bitmap[i];
5bb064dc
ZX		 3467
3468 /* If nothing is dirty, don't bother messing with page tables. */
3469 if (is_dirty) {
b050b015 3470 struct kvm_memslots *slots, *old_slots;
914ebccd 3471 unsigned long *dirty_bitmap;
b050b015 3472
515a0127
TY		 3473 dirty_bitmap = memslot->dirty_bitmap_head;
3474 if (memslot->dirty_bitmap == dirty_bitmap)
3475 dirty_bitmap += n / sizeof(long);
914ebccd 3476 memset(dirty_bitmap, 0, n);
b050b015 3477
914ebccd
TY		 3478 r = -ENOMEM;
3479 slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
515a0127 3480 if (!slots)
914ebccd 3481 goto out;
b050b015
MT		 3482 memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
3483 slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
49c7754c 3484 slots->generation++;
b050b015
MT		 3485
3486 old_slots = kvm->memslots;
3487 rcu_assign_pointer(kvm->memslots, slots);
3488 synchronize_srcu_expedited(&kvm->srcu);
3489 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
3490 kfree(old_slots);
914ebccd 3491
edde99ce
MT		 3492 spin_lock(&kvm->mmu_lock);
3493 kvm_mmu_slot_remove_write_access(kvm, log->slot);
3494 spin_unlock(&kvm->mmu_lock);
3495
914ebccd 3496 r = -EFAULT;
515a0127 3497 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n))
914ebccd 3498 goto out;
914ebccd
TY		 3499 } else {
3500 r = -EFAULT;
3501 if (clear_user(log->dirty_bitmap, n))
3502 goto out;
5bb064dc 3503 }
b050b015 3504
5bb064dc
ZX		 3505 r = 0;
3506out:
79fac95e 3507 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3508 return r;
3509}
3510
1fe779f8
CO		 3511long kvm_arch_vm_ioctl(struct file *filp,
3512 unsigned int ioctl, unsigned long arg)
3513{
3514 struct kvm *kvm = filp->private_data;
3515 void __user *argp = (void __user *)arg;
367e1319 3516 int r = -ENOTTY;
f0d66275
DH		 3517 /*
3518 * This union makes it completely explicit to gcc-3.x
3519 * that these two variables' stack usage should be
3520 * combined, not added together.
3521 */
3522 union {
3523 struct kvm_pit_state ps;
e9f42757 3524 struct kvm_pit_state2 ps2;
c5ff41ce 3525 struct kvm_pit_config pit_config;
f0d66275 3526 } u;
1fe779f8
CO		 3527
3528 switch (ioctl) {
3529 case KVM_SET_TSS_ADDR:
3530 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3531 if (r < 0)
3532 goto out;
3533 break;
b927a3ce
SY		 3534 case KVM_SET_IDENTITY_MAP_ADDR: {
3535 u64 ident_addr;
3536
3537 r = -EFAULT;
3538 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3539 goto out;
3540 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3541 if (r < 0)
3542 goto out;
3543 break;
3544 }
1fe779f8
CO		 3545 case KVM_SET_NR_MMU_PAGES:
3546 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3547 if (r)
3548 goto out;
3549 break;
3550 case KVM_GET_NR_MMU_PAGES:
3551 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3552 break;
3ddea128
MT		 3553 case KVM_CREATE_IRQCHIP: {
3554 struct kvm_pic *vpic;
3555
3556 mutex_lock(&kvm->lock);
3557 r = -EEXIST;
3558 if (kvm->arch.vpic)
3559 goto create_irqchip_unlock;
1fe779f8 3560 r = -ENOMEM;
3ddea128
MT		 3561 vpic = kvm_create_pic(kvm);
3562 if (vpic) {
1fe779f8
CO		 3563 r = kvm_ioapic_init(kvm);
3564 if (r) {
175504cd 3565 mutex_lock(&kvm->slots_lock);
72bb2fcd 3566 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3567 &vpic->dev_master);
3568 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3569 &vpic->dev_slave);
3570 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3571 &vpic->dev_eclr);
175504cd 3572 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3573 kfree(vpic);
3574 goto create_irqchip_unlock;
1fe779f8
CO		 3575 }
3576 } else
3ddea128
MT		 3577 goto create_irqchip_unlock;
3578 smp_wmb();
3579 kvm->arch.vpic = vpic;
3580 smp_wmb();
399ec807
AK		 3581 r = kvm_setup_default_irq_routing(kvm);
3582 if (r) {
175504cd 3583 mutex_lock(&kvm->slots_lock);
3ddea128 3584 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3585 kvm_ioapic_destroy(kvm);
3586 kvm_destroy_pic(kvm);
3ddea128 3587 mutex_unlock(&kvm->irq_lock);
175504cd 3588 mutex_unlock(&kvm->slots_lock);
399ec807 3589 }
3ddea128
MT		 3590 create_irqchip_unlock:
3591 mutex_unlock(&kvm->lock);
1fe779f8 3592 break;
3ddea128 3593 }
7837699f 3594 case KVM_CREATE_PIT:
c5ff41ce
JK		 3595 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3596 goto create_pit;
3597 case KVM_CREATE_PIT2:
3598 r = -EFAULT;
3599 if (copy_from_user(&u.pit_config, argp,
3600 sizeof(struct kvm_pit_config)))
3601 goto out;
3602 create_pit:
79fac95e 3603 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3604 r = -EEXIST;
3605 if (kvm->arch.vpit)
3606 goto create_pit_unlock;
7837699f 3607 r = -ENOMEM;
c5ff41ce 3608 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3609 if (kvm->arch.vpit)
3610 r = 0;
269e05e4 3611 create_pit_unlock:
79fac95e 3612 mutex_unlock(&kvm->slots_lock);
7837699f 3613 break;
4925663a 3614 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 3615 case KVM_IRQ_LINE: {
3616 struct kvm_irq_level irq_event;
3617
3618 r = -EFAULT;
3619 if (copy_from_user(&irq_event, argp, sizeof irq_event))
3620 goto out;
160d2f6c 3621 r = -ENXIO;
1fe779f8 3622 if (irqchip_in_kernel(kvm)) {
4925663a 3623 __s32 status;
4925663a
GN		 3624 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3625 irq_event.irq, irq_event.level);
4925663a 3626 if (ioctl == KVM_IRQ_LINE_STATUS) {
160d2f6c 3627 r = -EFAULT;
4925663a
GN		 3628 irq_event.status = status;
3629 if (copy_to_user(argp, &irq_event,
3630 sizeof irq_event))
3631 goto out;
3632 }
1fe779f8
CO		 3633 r = 0;
3634 }
3635 break;
3636 }
3637 case KVM_GET_IRQCHIP: {
3638 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3639 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3640
f0d66275
DH		 3641 r = -ENOMEM;
3642 if (!chip)
1fe779f8 3643 goto out;
f0d66275
DH		 3644 r = -EFAULT;
3645 if (copy_from_user(chip, argp, sizeof *chip))
3646 goto get_irqchip_out;
1fe779f8
CO		 3647 r = -ENXIO;
3648 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3649 goto get_irqchip_out;
3650 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3651 if (r)
f0d66275 3652 goto get_irqchip_out;
1fe779f8 3653 r = -EFAULT;
f0d66275
DH		 3654 if (copy_to_user(argp, chip, sizeof *chip))
3655 goto get_irqchip_out;
1fe779f8 3656 r = 0;
f0d66275
DH		 3657 get_irqchip_out:
3658 kfree(chip);
3659 if (r)
3660 goto out;
1fe779f8
CO		 3661 break;
3662 }
3663 case KVM_SET_IRQCHIP: {
3664 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3665 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3666
f0d66275
DH		 3667 r = -ENOMEM;
3668 if (!chip)
1fe779f8 3669 goto out;
f0d66275
DH		 3670 r = -EFAULT;
3671 if (copy_from_user(chip, argp, sizeof *chip))
3672 goto set_irqchip_out;
1fe779f8
CO		 3673 r = -ENXIO;
3674 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3675 goto set_irqchip_out;
3676 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3677 if (r)
f0d66275 3678 goto set_irqchip_out;
1fe779f8 3679 r = 0;
f0d66275
DH		 3680 set_irqchip_out:
3681 kfree(chip);
3682 if (r)
3683 goto out;
1fe779f8
CO		 3684 break;
3685 }
e0f63cb9 3686 case KVM_GET_PIT: {
e0f63cb9 3687 r = -EFAULT;
f0d66275 3688 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3689 goto out;
3690 r = -ENXIO;
3691 if (!kvm->arch.vpit)
3692 goto out;
f0d66275 3693 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3694 if (r)
3695 goto out;
3696 r = -EFAULT;
f0d66275 3697 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3698 goto out;
3699 r = 0;
3700 break;
3701 }
3702 case KVM_SET_PIT: {
e0f63cb9 3703 r = -EFAULT;
f0d66275 3704 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3705 goto out;
3706 r = -ENXIO;
3707 if (!kvm->arch.vpit)
3708 goto out;
f0d66275 3709 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3710 if (r)
3711 goto out;
3712 r = 0;
3713 break;
3714 }
e9f42757
BK		 3715 case KVM_GET_PIT2: {
3716 r = -ENXIO;
3717 if (!kvm->arch.vpit)
3718 goto out;
3719 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3720 if (r)
3721 goto out;
3722 r = -EFAULT;
3723 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3724 goto out;
3725 r = 0;
3726 break;
3727 }
3728 case KVM_SET_PIT2: {
3729 r = -EFAULT;
3730 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3731 goto out;
3732 r = -ENXIO;
3733 if (!kvm->arch.vpit)
3734 goto out;
3735 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3736 if (r)
3737 goto out;
3738 r = 0;
3739 break;
3740 }
52d939a0
MT		 3741 case KVM_REINJECT_CONTROL: {
3742 struct kvm_reinject_control control;
3743 r = -EFAULT;
3744 if (copy_from_user(&control, argp, sizeof(control)))
3745 goto out;
3746 r = kvm_vm_ioctl_reinject(kvm, &control);
3747 if (r)
3748 goto out;
3749 r = 0;
3750 break;
3751 }
ffde22ac
ES		 3752 case KVM_XEN_HVM_CONFIG: {
3753 r = -EFAULT;
3754 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3755 sizeof(struct kvm_xen_hvm_config)))
3756 goto out;
3757 r = -EINVAL;
3758 if (kvm->arch.xen_hvm_config.flags)
3759 goto out;
3760 r = 0;
3761 break;
3762 }
afbcf7ab 3763 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3764 struct kvm_clock_data user_ns;
3765 u64 now_ns;
3766 s64 delta;
3767
3768 r = -EFAULT;
3769 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3770 goto out;
3771
3772 r = -EINVAL;
3773 if (user_ns.flags)
3774 goto out;
3775
3776 r = 0;
395c6b0a 3777 local_irq_disable();
759379dd 3778 now_ns = get_kernel_ns();
afbcf7ab 3779 delta = user_ns.clock - now_ns;
395c6b0a 3780 local_irq_enable();
afbcf7ab
GC		 3781 kvm->arch.kvmclock_offset = delta;
3782 break;
3783 }
3784 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3785 struct kvm_clock_data user_ns;
3786 u64 now_ns;
3787
395c6b0a 3788 local_irq_disable();
759379dd 3789 now_ns = get_kernel_ns();
afbcf7ab 3790 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3791 local_irq_enable();
afbcf7ab 3792 user_ns.flags = 0;
97e69aa6 3793 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3794
3795 r = -EFAULT;
3796 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3797 goto out;
3798 r = 0;
3799 break;
3800 }
3801
1fe779f8
CO		 3802 default:
3803 ;
3804 }
3805out:
3806 return r;
3807}
3808
a16b043c 3809static void kvm_init_msr_list(void)
043405e1
CO		 3810{
3811 u32 dummy[2];
3812 unsigned i, j;
3813
e3267cbb
GC		 3814 /* skip the first msrs in the list. KVM-specific */
3815 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3816 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3817 continue;
3818 if (j < i)
3819 msrs_to_save[j] = msrs_to_save[i];
3820 j++;
3821 }
3822 num_msrs_to_save = j;
3823}
3824
bda9020e
MT		 3825static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3826 const void *v)
bbd9b64e 3827{
70252a10
AK		 3828 int handled = 0;
3829 int n;
3830
3831 do {
3832 n = min(len, 8);
3833 if (!(vcpu->arch.apic &&
3834 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3835 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3836 break;
3837 handled += n;
3838 addr += n;
3839 len -= n;
3840 v += n;
3841 } while (len);
bbd9b64e 3842
70252a10 3843 return handled;
bbd9b64e
CO		 3844}
3845
bda9020e 3846static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3847{
70252a10
AK		 3848 int handled = 0;
3849 int n;
3850
3851 do {
3852 n = min(len, 8);
3853 if (!(vcpu->arch.apic &&
3854 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3855 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3856 break;
3857 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3858 handled += n;
3859 addr += n;
3860 len -= n;
3861 v += n;
3862 } while (len);
bbd9b64e 3863
70252a10 3864 return handled;
bbd9b64e
CO		 3865}
3866
2dafc6c2
GN		 3867static void kvm_set_segment(struct kvm_vcpu *vcpu,
3868 struct kvm_segment *var, int seg)
3869{
3870 kvm_x86_ops->set_segment(vcpu, var, seg);
3871}
3872
3873void kvm_get_segment(struct kvm_vcpu *vcpu,
3874 struct kvm_segment *var, int seg)
3875{
3876 kvm_x86_ops->get_segment(vcpu, var, seg);
3877}
3878
c30a358d
JR		 3879static gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3880{
3881 return gpa;
3882}
3883
02f59dc9
JR		 3884static gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3885{
3886 gpa_t t_gpa;
ab9ae313 3887 struct x86_exception exception;
02f59dc9
JR		 3888
3889 BUG_ON(!mmu_is_nested(vcpu));
3890
3891 /* NPT walks are always user-walks */
3892 access |= PFERR_USER_MASK;
ab9ae313 3893 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
02f59dc9
JR		 3894
3895 return t_gpa;
3896}
3897
ab9ae313
AK		 3898gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3899 struct x86_exception *exception)
1871c602
GN		 3900{
3901 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 3902 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3903}
3904
ab9ae313
AK		 3905 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3906 struct x86_exception *exception)
1871c602
GN		 3907{
3908 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3909 access |= PFERR_FETCH_MASK;
ab9ae313 3910 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3911}
3912
ab9ae313
AK		 3913gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3914 struct x86_exception *exception)
1871c602
GN		 3915{
3916 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3917 access |= PFERR_WRITE_MASK;
ab9ae313 3918 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3919}
3920
3921/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 3922gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3923 struct x86_exception *exception)
1871c602 3924{
ab9ae313 3925 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 3926}
3927
3928static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3929 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 3930 struct x86_exception *exception)
bbd9b64e
CO		 3931{
3932 void *data = val;
10589a46 3933 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3934
3935 while (bytes) {
14dfe855 3936 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 3937 exception);
bbd9b64e 3938 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3939 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3940 int ret;
3941
bcc55cba 3942 if (gpa == UNMAPPED_GVA)
ab9ae313 3943 return X86EMUL_PROPAGATE_FAULT;
77c2002e 3944 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3945 if (ret < 0) {
c3cd7ffa 3946 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3947 goto out;
3948 }
bbd9b64e 3949
77c2002e
IE		 3950 bytes -= toread;
3951 data += toread;
3952 addr += toread;
bbd9b64e 3953 }
10589a46 3954out:
10589a46 3955 return r;
bbd9b64e 3956}
77c2002e 3957
1871c602 3958/* used for instruction fetching */
0f65dd70
AK		 3959static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
3960 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3961 struct x86_exception *exception)
1871c602 3962{
0f65dd70 3963 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3964 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3965
1871c602 3966 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
bcc55cba
AK		 3967 access | PFERR_FETCH_MASK,
3968 exception);
1871c602
GN		 3969}
3970
064aea77 3971int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 3972 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3973 struct x86_exception *exception)
1871c602 3974{
0f65dd70 3975 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3976 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3977
1871c602 3978 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 3979 exception);
1871c602 3980}
064aea77 3981EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 3982
0f65dd70
AK		 3983static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3984 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3985 struct x86_exception *exception)
1871c602 3986{
0f65dd70 3987 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 3988 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 3989}
3990
6a4d7550 3991int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 3992 gva_t addr, void *val,
2dafc6c2 3993 unsigned int bytes,
bcc55cba 3994 struct x86_exception *exception)
77c2002e 3995{
0f65dd70 3996 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 3997 void *data = val;
3998 int r = X86EMUL_CONTINUE;
3999
4000 while (bytes) {
14dfe855
JR		 4001 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4002 PFERR_WRITE_MASK,
ab9ae313 4003 exception);
77c2002e
IE		 4004 unsigned offset = addr & (PAGE_SIZE-1);
4005 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4006 int ret;
4007
bcc55cba 4008 if (gpa == UNMAPPED_GVA)
ab9ae313 4009 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 4010 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4011 if (ret < 0) {
c3cd7ffa 4012 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4013 goto out;
4014 }
4015
4016 bytes -= towrite;
4017 data += towrite;
4018 addr += towrite;
4019 }
4020out:
4021 return r;
4022}
6a4d7550 4023EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4024
af7cc7d1
XG		 4025static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4026 gpa_t *gpa, struct x86_exception *exception,
4027 bool write)
4028{
4029 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4030
bebb106a
XG		 4031 if (vcpu_match_mmio_gva(vcpu, gva) &&
4032 check_write_user_access(vcpu, write, access,
4033 vcpu->arch.access)) {
4034 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4035 (gva & (PAGE_SIZE - 1));
4f022648 4036 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4037 return 1;
4038 }
4039
af7cc7d1
XG		 4040 if (write)
4041 access |= PFERR_WRITE_MASK;
4042
4043 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4044
4045 if (*gpa == UNMAPPED_GVA)
4046 return -1;
4047
4048 /* For APIC access vmexit */
4049 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4050 return 1;
4051
4f022648
XG		 4052 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4053 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4054 return 1;
4f022648 4055 }
bebb106a 4056
af7cc7d1
XG		 4057 return 0;
4058}
4059
3200f405 4060int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4061 const void *val, int bytes)
bbd9b64e
CO		 4062{
4063 int ret;
4064
4065 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 4066 if (ret < 0)
bbd9b64e 4067 return 0;
ad218f85 4068 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 4069 return 1;
4070}
4071
77d197b2
XG		 4072struct read_write_emulator_ops {
4073 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4074 int bytes);
4075 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4076 void *val, int bytes);
4077 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4078 int bytes, void *val);
4079 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4080 void *val, int bytes);
4081 bool write;
4082};
4083
4084static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4085{
4086 if (vcpu->mmio_read_completed) {
4087 memcpy(val, vcpu->mmio_data, bytes);
4088 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
4089 vcpu->mmio_phys_addr, *(u64 *)val);
4090 vcpu->mmio_read_completed = 0;
4091 return 1;
4092 }
4093
4094 return 0;
4095}
4096
4097static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4098 void *val, int bytes)
4099{
4100 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4101}
4102
4103static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4104 void *val, int bytes)
4105{
4106 return emulator_write_phys(vcpu, gpa, val, bytes);
4107}
4108
4109static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4110{
4111 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4112 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4113}
4114
4115static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4116 void *val, int bytes)
4117{
4118 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4119 return X86EMUL_IO_NEEDED;
4120}
4121
4122static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4123 void *val, int bytes)
4124{
4125 memcpy(vcpu->mmio_data, val, bytes);
4126 memcpy(vcpu->run->mmio.data, vcpu->mmio_data, 8);
4127 return X86EMUL_CONTINUE;
4128}
4129
4130static struct read_write_emulator_ops read_emultor = {
4131 .read_write_prepare = read_prepare,
4132 .read_write_emulate = read_emulate,
4133 .read_write_mmio = vcpu_mmio_read,
4134 .read_write_exit_mmio = read_exit_mmio,
4135};
4136
4137static struct read_write_emulator_ops write_emultor = {
4138 .read_write_emulate = write_emulate,
4139 .read_write_mmio = write_mmio,
4140 .read_write_exit_mmio = write_exit_mmio,
4141 .write = true,
4142};
4143
22388a3c
XG		 4144static int emulator_read_write_onepage(unsigned long addr, void *val,
4145 unsigned int bytes,
4146 struct x86_exception *exception,
4147 struct kvm_vcpu *vcpu,
4148 struct read_write_emulator_ops *ops)
bbd9b64e 4149{
af7cc7d1
XG		 4150 gpa_t gpa;
4151 int handled, ret;
22388a3c
XG		 4152 bool write = ops->write;
4153
4154 if (ops->read_write_prepare &&
4155 ops->read_write_prepare(vcpu, val, bytes))
4156 return X86EMUL_CONTINUE;
10589a46 4157
22388a3c 4158 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4159
af7cc7d1 4160 if (ret < 0)
bbd9b64e 4161 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4162
4163 /* For APIC access vmexit */
af7cc7d1 4164 if (ret)
bbd9b64e
CO		 4165 goto mmio;
4166
22388a3c 4167 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4168 return X86EMUL_CONTINUE;
4169
4170mmio:
4171 /*
4172 * Is this MMIO handled locally?
4173 */
22388a3c 4174 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4175 if (handled == bytes)
bbd9b64e 4176 return X86EMUL_CONTINUE;
bbd9b64e 4177
70252a10
AK		 4178 gpa += handled;
4179 bytes -= handled;
4180 val += handled;
4181
bbd9b64e 4182 vcpu->mmio_needed = 1;
411c35b7
GN		 4183 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4184 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
cef4dea0
AK		 4185 vcpu->mmio_size = bytes;
4186 vcpu->run->mmio.len = min(vcpu->mmio_size, 8);
22388a3c 4187 vcpu->run->mmio.is_write = vcpu->mmio_is_write = write;
cef4dea0 4188 vcpu->mmio_index = 0;
bbd9b64e 4189
22388a3c 4190 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4191}
4192
22388a3c
XG		 4193int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4194 void *val, unsigned int bytes,
4195 struct x86_exception *exception,
4196 struct read_write_emulator_ops *ops)
bbd9b64e 4197{
0f65dd70
AK		 4198 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4199
bbd9b64e
CO		 4200 /* Crossing a page boundary? */
4201 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
4202 int rc, now;
4203
4204 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4205 rc = emulator_read_write_onepage(addr, val, now, exception,
4206 vcpu, ops);
4207
bbd9b64e
CO		 4208 if (rc != X86EMUL_CONTINUE)
4209 return rc;
4210 addr += now;
4211 val += now;
4212 bytes -= now;
4213 }
22388a3c
XG		 4214
4215 return emulator_read_write_onepage(addr, val, bytes, exception,
4216 vcpu, ops);
4217}
4218
4219static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4220 unsigned long addr,
4221 void *val,
4222 unsigned int bytes,
4223 struct x86_exception *exception)
4224{
4225 return emulator_read_write(ctxt, addr, val, bytes,
4226 exception, &read_emultor);
4227}
4228
4229int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4230 unsigned long addr,
4231 const void *val,
4232 unsigned int bytes,
4233 struct x86_exception *exception)
4234{
4235 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4236 exception, &write_emultor);
bbd9b64e 4237}
bbd9b64e 4238
daea3e73
AK		 4239#define CMPXCHG_TYPE(t, ptr, old, new) \
4240 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4241
4242#ifdef CONFIG_X86_64
4243# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4244#else
4245# define CMPXCHG64(ptr, old, new) \
9749a6c0 4246 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4247#endif
4248
0f65dd70
AK		 4249static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4250 unsigned long addr,
bbd9b64e
CO		 4251 const void *old,
4252 const void *new,
4253 unsigned int bytes,
0f65dd70 4254 struct x86_exception *exception)
bbd9b64e 4255{
0f65dd70 4256 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4257 gpa_t gpa;
4258 struct page *page;
4259 char *kaddr;
4260 bool exchanged;
2bacc55c 4261
daea3e73
AK		 4262 /* guests cmpxchg8b have to be emulated atomically */
4263 if (bytes > 8 || (bytes & (bytes - 1)))
4264 goto emul_write;
10589a46 4265
daea3e73 4266 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4267
daea3e73
AK		 4268 if (gpa == UNMAPPED_GVA ||
4269 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4270 goto emul_write;
2bacc55c 4271
daea3e73
AK		 4272 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4273 goto emul_write;
72dc67a6 4274
daea3e73 4275 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
c19b8bd6
WY		 4276 if (is_error_page(page)) {
4277 kvm_release_page_clean(page);
4278 goto emul_write;
4279 }
72dc67a6 4280
daea3e73
AK		 4281 kaddr = kmap_atomic(page, KM_USER0);
4282 kaddr += offset_in_page(gpa);
4283 switch (bytes) {
4284 case 1:
4285 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4286 break;
4287 case 2:
4288 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4289 break;
4290 case 4:
4291 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4292 break;
4293 case 8:
4294 exchanged = CMPXCHG64(kaddr, old, new);
4295 break;
4296 default:
4297 BUG();
2bacc55c 4298 }
daea3e73
AK		 4299 kunmap_atomic(kaddr, KM_USER0);
4300 kvm_release_page_dirty(page);
4301
4302 if (!exchanged)
4303 return X86EMUL_CMPXCHG_FAILED;
4304
8f6abd06
GN		 4305 kvm_mmu_pte_write(vcpu, gpa, new, bytes, 1);
4306
4307 return X86EMUL_CONTINUE;
4a5f48f6 4308
3200f405 4309emul_write:
daea3e73 4310 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4311
0f65dd70 4312 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4313}
4314
cf8f70bf
GN		 4315static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4316{
4317 /* TODO: String I/O for in kernel device */
4318 int r;
4319
4320 if (vcpu->arch.pio.in)
4321 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4322 vcpu->arch.pio.size, pd);
4323 else
4324 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4325 vcpu->arch.pio.port, vcpu->arch.pio.size,
4326 pd);
4327 return r;
4328}
4329
4330
ca1d4a9e
AK		 4331static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4332 int size, unsigned short port, void *val,
4333 unsigned int count)
cf8f70bf 4334{
ca1d4a9e
AK		 4335 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4336
7972995b 4337 if (vcpu->arch.pio.count)
cf8f70bf
GN		 4338 goto data_avail;
4339
61cfab2e 4340 trace_kvm_pio(0, port, size, count);
cf8f70bf
GN		 4341
4342 vcpu->arch.pio.port = port;
4343 vcpu->arch.pio.in = 1;
7972995b 4344 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4345 vcpu->arch.pio.size = size;
4346
4347 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4348 data_avail:
4349 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 4350 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4351 return 1;
4352 }
4353
4354 vcpu->run->exit_reason = KVM_EXIT_IO;
4355 vcpu->run->io.direction = KVM_EXIT_IO_IN;
4356 vcpu->run->io.size = size;
4357 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4358 vcpu->run->io.count = count;
4359 vcpu->run->io.port = port;
4360
4361 return 0;
4362}
4363
ca1d4a9e
AK		 4364static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4365 int size, unsigned short port,
4366 const void *val, unsigned int count)
cf8f70bf 4367{
ca1d4a9e
AK		 4368 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4369
61cfab2e 4370 trace_kvm_pio(1, port, size, count);
cf8f70bf
GN		 4371
4372 vcpu->arch.pio.port = port;
4373 vcpu->arch.pio.in = 0;
7972995b 4374 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4375 vcpu->arch.pio.size = size;
4376
4377 memcpy(vcpu->arch.pio_data, val, size * count);
4378
4379 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4380 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4381 return 1;
4382 }
4383
4384 vcpu->run->exit_reason = KVM_EXIT_IO;
4385 vcpu->run->io.direction = KVM_EXIT_IO_OUT;
4386 vcpu->run->io.size = size;
4387 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4388 vcpu->run->io.count = count;
4389 vcpu->run->io.port = port;
4390
4391 return 0;
4392}
4393
bbd9b64e
CO		 4394static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4395{
4396 return kvm_x86_ops->get_segment_base(vcpu, seg);
4397}
4398
3cb16fe7 4399static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4400{
3cb16fe7 4401 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4402}
4403
f5f48ee1
SY		 4404int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4405{
4406 if (!need_emulate_wbinvd(vcpu))
4407 return X86EMUL_CONTINUE;
4408
4409 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4410 int cpu = get_cpu();
4411
4412 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4413 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4414 wbinvd_ipi, NULL, 1);
2eec7343 4415 put_cpu();
f5f48ee1 4416 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4417 } else
4418 wbinvd();
f5f48ee1
SY		 4419 return X86EMUL_CONTINUE;
4420}
4421EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4422
bcaf5cc5
AK		 4423static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4424{
4425 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4426}
4427
717746e3 4428int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
bbd9b64e 4429{
717746e3 4430 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4431}
4432
717746e3 4433int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
bbd9b64e 4434{
338dbc97 4435
717746e3 4436 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4437}
4438
52a46617 4439static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4440{
52a46617 4441 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4442}
4443
717746e3 4444static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4445{
717746e3 4446 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4447 unsigned long value;
4448
4449 switch (cr) {
4450 case 0:
4451 value = kvm_read_cr0(vcpu);
4452 break;
4453 case 2:
4454 value = vcpu->arch.cr2;
4455 break;
4456 case 3:
9f8fe504 4457 value = kvm_read_cr3(vcpu);
52a46617
GN		 4458 break;
4459 case 4:
4460 value = kvm_read_cr4(vcpu);
4461 break;
4462 case 8:
4463 value = kvm_get_cr8(vcpu);
4464 break;
4465 default:
4466 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
4467 return 0;
4468 }
4469
4470 return value;
4471}
4472
717746e3 4473static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4474{
717746e3 4475 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4476 int res = 0;
4477
52a46617
GN		 4478 switch (cr) {
4479 case 0:
49a9b07e 4480 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4481 break;
4482 case 2:
4483 vcpu->arch.cr2 = val;
4484 break;
4485 case 3:
2390218b 4486 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4487 break;
4488 case 4:
a83b29c6 4489 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4490 break;
4491 case 8:
eea1cff9 4492 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4493 break;
4494 default:
4495 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
0f12244f 4496 res = -1;
52a46617 4497 }
0f12244f
GN		 4498
4499 return res;
52a46617
GN		 4500}
4501
717746e3 4502static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4503{
717746e3 4504 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4505}
4506
4bff1e86 4507static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4508{
4bff1e86 4509 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4510}
4511
4bff1e86 4512static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4513{
4bff1e86 4514 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4515}
4516
1ac9d0cf
AK		 4517static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4518{
4519 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4520}
4521
4522static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4523{
4524 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4525}
4526
4bff1e86
AK		 4527static unsigned long emulator_get_cached_segment_base(
4528 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4529{
4bff1e86 4530 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4531}
4532
1aa36616
AK		 4533static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4534 struct desc_struct *desc, u32 *base3,
4535 int seg)
2dafc6c2
GN		 4536{
4537 struct kvm_segment var;
4538
4bff1e86 4539 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4540 *selector = var.selector;
2dafc6c2
GN		 4541
4542 if (var.unusable)
4543 return false;
4544
4545 if (var.g)
4546 var.limit >>= 12;
4547 set_desc_limit(desc, var.limit);
4548 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4549#ifdef CONFIG_X86_64
4550 if (base3)
4551 *base3 = var.base >> 32;
4552#endif
2dafc6c2
GN		 4553 desc->type = var.type;
4554 desc->s = var.s;
4555 desc->dpl = var.dpl;
4556 desc->p = var.present;
4557 desc->avl = var.avl;
4558 desc->l = var.l;
4559 desc->d = var.db;
4560 desc->g = var.g;
4561
4562 return true;
4563}
4564
1aa36616
AK		 4565static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4566 struct desc_struct *desc, u32 base3,
4567 int seg)
2dafc6c2 4568{
4bff1e86 4569 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4570 struct kvm_segment var;
4571
1aa36616 4572 var.selector = selector;
2dafc6c2 4573 var.base = get_desc_base(desc);
5601d05b
GN		 4574#ifdef CONFIG_X86_64
4575 var.base |= ((u64)base3) << 32;
4576#endif
2dafc6c2
GN		 4577 var.limit = get_desc_limit(desc);
4578 if (desc->g)
4579 var.limit = (var.limit << 12) | 0xfff;
4580 var.type = desc->type;
4581 var.present = desc->p;
4582 var.dpl = desc->dpl;
4583 var.db = desc->d;
4584 var.s = desc->s;
4585 var.l = desc->l;
4586 var.g = desc->g;
4587 var.avl = desc->avl;
4588 var.present = desc->p;
4589 var.unusable = !var.present;
4590 var.padding = 0;
4591
4592 kvm_set_segment(vcpu, &var, seg);
4593 return;
4594}
4595
717746e3
AK		 4596static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4597 u32 msr_index, u64 *pdata)
4598{
4599 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4600}
4601
4602static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4603 u32 msr_index, u64 data)
4604{
4605 return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
4606}
4607
6c3287f7
AK		 4608static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4609{
4610 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4611}
4612
5037f6f3
AK		 4613static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4614{
4615 preempt_disable();
5197b808 4616 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4617 /*
4618 * CR0.TS may reference the host fpu state, not the guest fpu state,
4619 * so it may be clear at this point.
4620 */
4621 clts();
4622}
4623
4624static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4625{
4626 preempt_enable();
4627}
4628
2953538e 4629static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4630 struct x86_instruction_info *info,
c4f035c6
AK		 4631 enum x86_intercept_stage stage)
4632{
2953538e 4633 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4634}
4635
14af3f3c 4636static struct x86_emulate_ops emulate_ops = {
1871c602 4637 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4638 .write_std = kvm_write_guest_virt_system,
1871c602 4639 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4640 .read_emulated = emulator_read_emulated,
4641 .write_emulated = emulator_write_emulated,
4642 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4643 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4644 .pio_in_emulated = emulator_pio_in_emulated,
4645 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4646 .get_segment = emulator_get_segment,
4647 .set_segment = emulator_set_segment,
5951c442 4648 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4649 .get_gdt = emulator_get_gdt,
160ce1f1 4650 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4651 .set_gdt = emulator_set_gdt,
4652 .set_idt = emulator_set_idt,
52a46617
GN		 4653 .get_cr = emulator_get_cr,
4654 .set_cr = emulator_set_cr,
9c537244 4655 .cpl = emulator_get_cpl,
35aa5375
GN		 4656 .get_dr = emulator_get_dr,
4657 .set_dr = emulator_set_dr,
717746e3
AK		 4658 .set_msr = emulator_set_msr,
4659 .get_msr = emulator_get_msr,
6c3287f7 4660 .halt = emulator_halt,
bcaf5cc5 4661 .wbinvd = emulator_wbinvd,
d6aa1000 4662 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4663 .get_fpu = emulator_get_fpu,
4664 .put_fpu = emulator_put_fpu,
c4f035c6 4665 .intercept = emulator_intercept,
bbd9b64e
CO		 4666};
4667
5fdbf976
MT		 4668static void cache_all_regs(struct kvm_vcpu *vcpu)
4669{
4670 kvm_register_read(vcpu, VCPU_REGS_RAX);
4671 kvm_register_read(vcpu, VCPU_REGS_RSP);
4672 kvm_register_read(vcpu, VCPU_REGS_RIP);
4673 vcpu->arch.regs_dirty = ~0;
4674}
4675
95cb2295
GN		 4676static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4677{
4678 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4679 /*
4680 * an sti; sti; sequence only disable interrupts for the first
4681 * instruction. So, if the last instruction, be it emulated or
4682 * not, left the system with the INT_STI flag enabled, it
4683 * means that the last instruction is an sti. We should not
4684 * leave the flag on in this case. The same goes for mov ss
4685 */
4686 if (!(int_shadow & mask))
4687 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4688}
4689
54b8486f
GN		 4690static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4691{
4692 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4693 if (ctxt->exception.vector == PF_VECTOR)
6389ee94 4694 kvm_propagate_fault(vcpu, &ctxt->exception);
da9cb575
AK		 4695 else if (ctxt->exception.error_code_valid)
4696 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4697 ctxt->exception.error_code);
54b8486f 4698 else
da9cb575 4699 kvm_queue_exception(vcpu, ctxt->exception.vector);
54b8486f
GN		 4700}
4701
9dac77fa 4702static void init_decode_cache(struct x86_emulate_ctxt *ctxt,
b5c9ff73
TY		 4703 const unsigned long *regs)
4704{
9dac77fa
AK		 4705 memset(&ctxt->twobyte, 0,
4706 (void *)&ctxt->regs - (void *)&ctxt->twobyte);
4707 memcpy(ctxt->regs, regs, sizeof(ctxt->regs));
b5c9ff73 4708
9dac77fa
AK		 4709 ctxt->fetch.start = 0;
4710 ctxt->fetch.end = 0;
4711 ctxt->io_read.pos = 0;
4712 ctxt->io_read.end = 0;
4713 ctxt->mem_read.pos = 0;
4714 ctxt->mem_read.end = 0;
b5c9ff73
TY		 4715}
4716
8ec4722d
MG		 4717static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4718{
adf52235 4719 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4720 int cs_db, cs_l;
4721
2aab2c5b
GN		 4722 /*
4723 * TODO: fix emulate.c to use guest_read/write_register
4724 * instead of direct ->regs accesses, can save hundred cycles
4725 * on Intel for instructions that don't read/change RSP, for
4726 * for example.
4727 */
8ec4722d
MG		 4728 cache_all_regs(vcpu);
4729
4730 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4731
adf52235
TY		 4732 ctxt->eflags = kvm_get_rflags(vcpu);
4733 ctxt->eip = kvm_rip_read(vcpu);
4734 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4735 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4736 cs_l ? X86EMUL_MODE_PROT64 :
4737 cs_db ? X86EMUL_MODE_PROT32 :
4738 X86EMUL_MODE_PROT16;
4739 ctxt->guest_mode = is_guest_mode(vcpu);
4740
9dac77fa 4741 init_decode_cache(ctxt, vcpu->arch.regs);
7ae441ea 4742 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4743}
4744
71f9833b 4745int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 4746{
9d74191a 4747 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 4748 int ret;
4749
4750 init_emulate_ctxt(vcpu);
4751
9dac77fa
AK		 4752 ctxt->op_bytes = 2;
4753 ctxt->ad_bytes = 2;
4754 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 4755 ret = emulate_int_real(ctxt, irq);
63995653
MG		 4756
4757 if (ret != X86EMUL_CONTINUE)
4758 return EMULATE_FAIL;
4759
9dac77fa
AK		 4760 ctxt->eip = ctxt->_eip;
4761 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
9d74191a
TY		 4762 kvm_rip_write(vcpu, ctxt->eip);
4763 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 4764
4765 if (irq == NMI_VECTOR)
4766 vcpu->arch.nmi_pending = false;
4767 else
4768 vcpu->arch.interrupt.pending = false;
4769
4770 return EMULATE_DONE;
4771}
4772EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4773
6d77dbfc
GN		 4774static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4775{
fc3a9157
JR		 4776 int r = EMULATE_DONE;
4777
6d77dbfc
GN		 4778 ++vcpu->stat.insn_emulation_fail;
4779 trace_kvm_emulate_insn_failed(vcpu);
fc3a9157
JR		 4780 if (!is_guest_mode(vcpu)) {
4781 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4782 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4783 vcpu->run->internal.ndata = 0;
4784 r = EMULATE_FAIL;
4785 }
6d77dbfc 4786 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4787
4788 return r;
6d77dbfc
GN		 4789}
4790
a6f177ef
GN		 4791static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
4792{
4793 gpa_t gpa;
4794
68be0803
GN		 4795 if (tdp_enabled)
4796 return false;
4797
a6f177ef
GN		 4798 /*
4799 * if emulation was due to access to shadowed page table
4800 * and it failed try to unshadow page and re-entetr the
4801 * guest to let CPU execute the instruction.
4802 */
4803 if (kvm_mmu_unprotect_page_virt(vcpu, gva))
4804 return true;
4805
4806 gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
4807
4808 if (gpa == UNMAPPED_GVA)
4809 return true; /* let cpu generate fault */
4810
4811 if (!kvm_is_error_hva(gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT)))
4812 return true;
4813
4814 return false;
4815}
4816
51d8b661
AP		 4817int x86_emulate_instruction(struct kvm_vcpu *vcpu,
4818 unsigned long cr2,
dc25e89e
AP		 4819 int emulation_type,
4820 void *insn,
4821 int insn_len)
bbd9b64e 4822{
95cb2295 4823 int r;
9d74191a 4824 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 4825 bool writeback = true;
bbd9b64e 4826
26eef70c 4827 kvm_clear_exception_queue(vcpu);
8d7d8102 4828
571008da 4829 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 4830 init_emulate_ctxt(vcpu);
9d74191a
TY		 4831 ctxt->interruptibility = 0;
4832 ctxt->have_exception = false;
4833 ctxt->perm_ok = false;
bbd9b64e 4834
9d74191a 4835 ctxt->only_vendor_specific_insn
4005996e
AK		 4836 = emulation_type & EMULTYPE_TRAP_UD;
4837
9d74191a 4838 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 4839
e46479f8 4840 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 4841 ++vcpu->stat.insn_emulation;
1d2887e2 4842 if (r != EMULATION_OK) {
4005996e
AK		 4843 if (emulation_type & EMULTYPE_TRAP_UD)
4844 return EMULATE_FAIL;
a6f177ef 4845 if (reexecute_instruction(vcpu, cr2))
bbd9b64e 4846 return EMULATE_DONE;
6d77dbfc
GN		 4847 if (emulation_type & EMULTYPE_SKIP)
4848 return EMULATE_FAIL;
4849 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4850 }
4851 }
4852
ba8afb6b 4853 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 4854 kvm_rip_write(vcpu, ctxt->_eip);
ba8afb6b
GN		 4855 return EMULATE_DONE;
4856 }
4857
7ae441ea 4858 /* this is needed for vmware backdoor interface to work since it
4d2179e1 4859 changes registers values during IO operation */
7ae441ea
GN		 4860 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
4861 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
9dac77fa 4862 memcpy(ctxt->regs, vcpu->arch.regs, sizeof ctxt->regs);
7ae441ea 4863 }
4d2179e1 4864
5cd21917 4865restart:
9d74191a 4866 r = x86_emulate_insn(ctxt);
bbd9b64e 4867
775fde86
JR		 4868 if (r == EMULATION_INTERCEPTED)
4869 return EMULATE_DONE;
4870
d2ddd1c4 4871 if (r == EMULATION_FAILED) {
a6f177ef 4872 if (reexecute_instruction(vcpu, cr2))
c3cd7ffa
GN		 4873 return EMULATE_DONE;
4874
6d77dbfc 4875 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4876 }
4877
9d74191a 4878 if (ctxt->have_exception) {
54b8486f 4879 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 4880 r = EMULATE_DONE;
4881 } else if (vcpu->arch.pio.count) {
3457e419
GN		 4882 if (!vcpu->arch.pio.in)
4883 vcpu->arch.pio.count = 0;
7ae441ea
GN		 4884 else
4885 writeback = false;
e85d28f8 4886 r = EMULATE_DO_MMIO;
7ae441ea
GN		 4887 } else if (vcpu->mmio_needed) {
4888 if (!vcpu->mmio_is_write)
4889 writeback = false;
e85d28f8 4890 r = EMULATE_DO_MMIO;
7ae441ea 4891 } else if (r == EMULATION_RESTART)
5cd21917 4892 goto restart;
d2ddd1c4
GN		 4893 else
4894 r = EMULATE_DONE;
f850e2e6 4895
7ae441ea 4896 if (writeback) {
9d74191a
TY		 4897 toggle_interruptibility(vcpu, ctxt->interruptibility);
4898 kvm_set_rflags(vcpu, ctxt->eflags);
7ae441ea 4899 kvm_make_request(KVM_REQ_EVENT, vcpu);
9dac77fa 4900 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
7ae441ea 4901 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 4902 kvm_rip_write(vcpu, ctxt->eip);
7ae441ea
GN		 4903 } else
4904 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 4905
4906 return r;
de7d789a 4907}
51d8b661 4908EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 4909
cf8f70bf 4910int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 4911{
cf8f70bf 4912 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 4913 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
4914 size, port, &val, 1);
cf8f70bf 4915 /* do not return to emulator after return from userspace */
7972995b 4916 vcpu->arch.pio.count = 0;
de7d789a
CO		 4917 return ret;
4918}
cf8f70bf 4919EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 4920
8cfdc000
ZA		 4921static void tsc_bad(void *info)
4922{
0a3aee0d 4923 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 4924}
4925
4926static void tsc_khz_changed(void *data)
c8076604 4927{
8cfdc000
ZA		 4928 struct cpufreq_freqs *freq = data;
4929 unsigned long khz = 0;
4930
4931 if (data)
4932 khz = freq->new;
4933 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4934 khz = cpufreq_quick_get(raw_smp_processor_id());
4935 if (!khz)
4936 khz = tsc_khz;
0a3aee0d 4937 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 4938}
4939
c8076604
GH		 4940static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4941 void *data)
4942{
4943 struct cpufreq_freqs *freq = data;
4944 struct kvm *kvm;
4945 struct kvm_vcpu *vcpu;
4946 int i, send_ipi = 0;
4947
8cfdc000
ZA		 4948 /*
4949 * We allow guests to temporarily run on slowing clocks,
4950 * provided we notify them after, or to run on accelerating
4951 * clocks, provided we notify them before. Thus time never
4952 * goes backwards.
4953 *
4954 * However, we have a problem. We can't atomically update
4955 * the frequency of a given CPU from this function; it is
4956 * merely a notifier, which can be called from any CPU.
4957 * Changing the TSC frequency at arbitrary points in time
4958 * requires a recomputation of local variables related to
4959 * the TSC for each VCPU. We must flag these local variables
4960 * to be updated and be sure the update takes place with the
4961 * new frequency before any guests proceed.
4962 *
4963 * Unfortunately, the combination of hotplug CPU and frequency
4964 * change creates an intractable locking scenario; the order
4965 * of when these callouts happen is undefined with respect to
4966 * CPU hotplug, and they can race with each other. As such,
4967 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
4968 * undefined; you can actually have a CPU frequency change take
4969 * place in between the computation of X and the setting of the
4970 * variable. To protect against this problem, all updates of
4971 * the per_cpu tsc_khz variable are done in an interrupt
4972 * protected IPI, and all callers wishing to update the value
4973 * must wait for a synchronous IPI to complete (which is trivial
4974 * if the caller is on the CPU already). This establishes the
4975 * necessary total order on variable updates.
4976 *
4977 * Note that because a guest time update may take place
4978 * anytime after the setting of the VCPU's request bit, the
4979 * correct TSC value must be set before the request. However,
4980 * to ensure the update actually makes it to any guest which
4981 * starts running in hardware virtualization between the set
4982 * and the acquisition of the spinlock, we must also ping the
4983 * CPU after setting the request bit.
4984 *
4985 */
4986
c8076604
GH		 4987 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
4988 return 0;
4989 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
4990 return 0;
8cfdc000
ZA		 4991
4992 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 4993
e935b837 4994 raw_spin_lock(&kvm_lock);
c8076604 4995 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 4996 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 4997 if (vcpu->cpu != freq->cpu)
4998 continue;
c285545f 4999 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5000 if (vcpu->cpu != smp_processor_id())
8cfdc000 5001 send_ipi = 1;
c8076604
GH		 5002 }
5003 }
e935b837 5004 raw_spin_unlock(&kvm_lock);
c8076604
GH		 5005
5006 if (freq->old < freq->new && send_ipi) {
5007 /*
5008 * We upscale the frequency. Must make the guest
5009 * doesn't see old kvmclock values while running with
5010 * the new frequency, otherwise we risk the guest sees
5011 * time go backwards.
5012 *
5013 * In case we update the frequency for another cpu
5014 * (which might be in guest context) send an interrupt
5015 * to kick the cpu out of guest context. Next time
5016 * guest context is entered kvmclock will be updated,
5017 * so the guest will not see stale values.
5018 */
8cfdc000 5019 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5020 }
5021 return 0;
5022}
5023
5024static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5025 .notifier_call = kvmclock_cpufreq_notifier
5026};
5027
5028static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5029 unsigned long action, void *hcpu)
5030{
5031 unsigned int cpu = (unsigned long)hcpu;
5032
5033 switch (action) {
5034 case CPU_ONLINE:
5035 case CPU_DOWN_FAILED:
5036 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5037 break;
5038 case CPU_DOWN_PREPARE:
5039 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5040 break;
5041 }
5042 return NOTIFY_OK;
5043}
5044
5045static struct notifier_block kvmclock_cpu_notifier_block = {
5046 .notifier_call = kvmclock_cpu_notifier,
5047 .priority = -INT_MAX
c8076604
GH		 5048};
5049
b820cc0c
ZA		 5050static void kvm_timer_init(void)
5051{
5052 int cpu;
5053
c285545f 5054 max_tsc_khz = tsc_khz;
8cfdc000 5055 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 5056 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5057#ifdef CONFIG_CPU_FREQ
5058 struct cpufreq_policy policy;
5059 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5060 cpu = get_cpu();
5061 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5062 if (policy.cpuinfo.max_freq)
5063 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5064 put_cpu();
c285545f 5065#endif
b820cc0c
ZA		 5066 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5067 CPUFREQ_TRANSITION_NOTIFIER);
5068 }
c285545f 5069 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5070 for_each_online_cpu(cpu)
5071 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 5072}
5073
ff9d07a0
ZY		 5074static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5075
5076static int kvm_is_in_guest(void)
5077{
5078 return percpu_read(current_vcpu) != NULL;
5079}
5080
5081static int kvm_is_user_mode(void)
5082{
5083 int user_mode = 3;
dcf46b94 5084
ff9d07a0
ZY		 5085 if (percpu_read(current_vcpu))
5086 user_mode = kvm_x86_ops->get_cpl(percpu_read(current_vcpu));
dcf46b94 5087
ff9d07a0
ZY		 5088 return user_mode != 0;
5089}
5090
5091static unsigned long kvm_get_guest_ip(void)
5092{
5093 unsigned long ip = 0;
dcf46b94 5094
ff9d07a0
ZY		 5095 if (percpu_read(current_vcpu))
5096 ip = kvm_rip_read(percpu_read(current_vcpu));
dcf46b94 5097
ff9d07a0
ZY		 5098 return ip;
5099}
5100
5101static struct perf_guest_info_callbacks kvm_guest_cbs = {
5102 .is_in_guest = kvm_is_in_guest,
5103 .is_user_mode = kvm_is_user_mode,
5104 .get_guest_ip = kvm_get_guest_ip,
5105};
5106
5107void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5108{
5109 percpu_write(current_vcpu, vcpu);
5110}
5111EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5112
5113void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5114{
5115 percpu_write(current_vcpu, NULL);
5116}
5117EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5118
ce88decf
XG		 5119static void kvm_set_mmio_spte_mask(void)
5120{
5121 u64 mask;
5122 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5123
5124 /*
5125 * Set the reserved bits and the present bit of an paging-structure
5126 * entry to generate page fault with PFER.RSV = 1.
5127 */
5128 mask = ((1ull << (62 - maxphyaddr + 1)) - 1) << maxphyaddr;
5129 mask |= 1ull;
5130
5131#ifdef CONFIG_X86_64
5132 /*
5133 * If reserved bit is not supported, clear the present bit to disable
5134 * mmio page fault.
5135 */
5136 if (maxphyaddr == 52)
5137 mask &= ~1ull;
5138#endif
5139
5140 kvm_mmu_set_mmio_spte_mask(mask);
5141}
5142
f8c16bba 5143int kvm_arch_init(void *opaque)
043405e1 5144{
b820cc0c 5145 int r;
f8c16bba
ZX		 5146 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
5147
f8c16bba
ZX		 5148 if (kvm_x86_ops) {
5149 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5150 r = -EEXIST;
5151 goto out;
f8c16bba
ZX		 5152 }
5153
5154 if (!ops->cpu_has_kvm_support()) {
5155 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5156 r = -EOPNOTSUPP;
5157 goto out;
f8c16bba
ZX		 5158 }
5159 if (ops->disabled_by_bios()) {
5160 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5161 r = -EOPNOTSUPP;
5162 goto out;
f8c16bba
ZX		 5163 }
5164
97db56ce
AK		 5165 r = kvm_mmu_module_init();
5166 if (r)
5167 goto out;
5168
ce88decf 5169 kvm_set_mmio_spte_mask();
97db56ce
AK		 5170 kvm_init_msr_list();
5171
f8c16bba 5172 kvm_x86_ops = ops;
7b52345e 5173 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5174 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5175
b820cc0c 5176 kvm_timer_init();
c8076604 5177
ff9d07a0
ZY		 5178 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5179
2acf923e
DC		 5180 if (cpu_has_xsave)
5181 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5182
f8c16bba 5183 return 0;
56c6d28a
ZX		 5184
5185out:
56c6d28a 5186 return r;
043405e1 5187}
8776e519 5188
f8c16bba
ZX		 5189void kvm_arch_exit(void)
5190{
ff9d07a0
ZY		 5191 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5192
888d256e
JK		 5193 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5194 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5195 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5196 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
f8c16bba 5197 kvm_x86_ops = NULL;
56c6d28a
ZX		 5198 kvm_mmu_module_exit();
5199}
f8c16bba 5200
8776e519
HB		 5201int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5202{
5203 ++vcpu->stat.halt_exits;
5204 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 5205 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5206 return 1;
5207 } else {
5208 vcpu->run->exit_reason = KVM_EXIT_HLT;
5209 return 0;
5210 }
5211}
5212EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5213
2f333bcb
MT		 5214static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
5215 unsigned long a1)
5216{
5217 if (is_long_mode(vcpu))
5218 return a0;
5219 else
5220 return a0 | ((gpa_t)a1 << 32);
5221}
5222
55cd8e5a
GN		 5223int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5224{
5225 u64 param, ingpa, outgpa, ret;
5226 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5227 bool fast, longmode;
5228 int cs_db, cs_l;
5229
5230 /*
5231 * hypercall generates UD from non zero cpl and real mode
5232 * per HYPER-V spec
5233 */
3eeb3288 5234 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 5235 kvm_queue_exception(vcpu, UD_VECTOR);
5236 return 0;
5237 }
5238
5239 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5240 longmode = is_long_mode(vcpu) && cs_l == 1;
5241
5242 if (!longmode) {
ccd46936
GN		 5243 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5244 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5245 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5246 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5247 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5248 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 5249 }
5250#ifdef CONFIG_X86_64
5251 else {
5252 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5253 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5254 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5255 }
5256#endif
5257
5258 code = param & 0xffff;
5259 fast = (param >> 16) & 0x1;
5260 rep_cnt = (param >> 32) & 0xfff;
5261 rep_idx = (param >> 48) & 0xfff;
5262
5263 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5264
c25bc163
GN		 5265 switch (code) {
5266 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5267 kvm_vcpu_on_spin(vcpu);
5268 break;
5269 default:
5270 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5271 break;
5272 }
55cd8e5a
GN		 5273
5274 ret = res | (((u64)rep_done & 0xfff) << 32);
5275 if (longmode) {
5276 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5277 } else {
5278 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5279 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5280 }
5281
5282 return 1;
5283}
5284
8776e519
HB		 5285int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5286{
5287 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 5288 int r = 1;
8776e519 5289
55cd8e5a
GN		 5290 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5291 return kvm_hv_hypercall(vcpu);
5292
5fdbf976
MT		 5293 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5294 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5295 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5296 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5297 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5298
229456fc 5299 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5300
8776e519
HB		 5301 if (!is_long_mode(vcpu)) {
5302 nr &= 0xFFFFFFFF;
5303 a0 &= 0xFFFFFFFF;
5304 a1 &= 0xFFFFFFFF;
5305 a2 &= 0xFFFFFFFF;
5306 a3 &= 0xFFFFFFFF;
5307 }
5308
07708c4a
JK		 5309 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5310 ret = -KVM_EPERM;
5311 goto out;
5312 }
5313
8776e519 5314 switch (nr) {
b93463aa
AK		 5315 case KVM_HC_VAPIC_POLL_IRQ:
5316 ret = 0;
5317 break;
2f333bcb
MT		 5318 case KVM_HC_MMU_OP:
5319 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
5320 break;
8776e519
HB		 5321 default:
5322 ret = -KVM_ENOSYS;
5323 break;
5324 }
07708c4a 5325out:
5fdbf976 5326 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5327 ++vcpu->stat.hypercalls;
2f333bcb 5328 return r;
8776e519
HB		 5329}
5330EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5331
d6aa1000 5332int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5333{
d6aa1000 5334 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5335 char instruction[3];
5fdbf976 5336 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5337
8776e519
HB		 5338 /*
5339 * Blow out the MMU to ensure that no other VCPU has an active mapping
5340 * to ensure that the updated hypercall appears atomically across all
5341 * VCPUs.
5342 */
5343 kvm_mmu_zap_all(vcpu->kvm);
5344
8776e519 5345 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5346
9d74191a 5347 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5348}
5349
07716717
DK		 5350static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
5351{
ad312c7c
ZX		 5352 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
5353 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 5354
5355 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
5356 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 5357 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 5358 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 5359 if (ej->function == e->function) {
5360 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
5361 return j;
5362 }
5363 }
5364 return 0; /* silence gcc, even though control never reaches here */
5365}
5366
5367/* find an entry with matching function, matching index (if needed), and that
5368 * should be read next (if it's stateful) */
5369static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
5370 u32 function, u32 index)
5371{
5372 if (e->function != function)
5373 return 0;
5374 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
5375 return 0;
5376 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 5377 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 5378 return 0;
5379 return 1;
5380}
5381
d8017474
AG		 5382struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
5383 u32 function, u32 index)
8776e519
HB		 5384{
5385 int i;
d8017474 5386 struct kvm_cpuid_entry2 *best = NULL;
8776e519 5387
ad312c7c 5388 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 5389 struct kvm_cpuid_entry2 *e;
5390
ad312c7c 5391 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 5392 if (is_matching_cpuid_entry(e, function, index)) {
5393 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
5394 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 5395 best = e;
5396 break;
5397 }
8776e519 5398 }
d8017474
AG		 5399 return best;
5400}
0e851880 5401EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
d8017474 5402
82725b20
DE		 5403int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
5404{
5405 struct kvm_cpuid_entry2 *best;
5406
f7a71197
AK		 5407 best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0);
5408 if (!best || best->eax < 0x80000008)
5409 goto not_found;
82725b20
DE		 5410 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
5411 if (best)
5412 return best->eax & 0xff;
f7a71197 5413not_found:
82725b20
DE		 5414 return 36;
5415}
5416
bd22f5cf
AP		 5417/*
5418 * If no match is found, check whether we exceed the vCPU's limit
5419 * and return the content of the highest valid _standard_ leaf instead.
5420 * This is to satisfy the CPUID specification.
5421 */
5422static struct kvm_cpuid_entry2* check_cpuid_limit(struct kvm_vcpu *vcpu,
5423 u32 function, u32 index)
5424{
5425 struct kvm_cpuid_entry2 *maxlevel;
5426
5427 maxlevel = kvm_find_cpuid_entry(vcpu, function & 0x80000000, 0);
5428 if (!maxlevel || maxlevel->eax >= function)
5429 return NULL;
5430 if (function & 0x80000000) {
5431 maxlevel = kvm_find_cpuid_entry(vcpu, 0, 0);
5432 if (!maxlevel)
5433 return NULL;
5434 }
5435 return kvm_find_cpuid_entry(vcpu, maxlevel->eax, index);
5436}
5437
d8017474
AG		 5438void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
5439{
5440 u32 function, index;
5441 struct kvm_cpuid_entry2 *best;
5442
5443 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
5444 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5445 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
5446 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
5447 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
5448 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
5449 best = kvm_find_cpuid_entry(vcpu, function, index);
bd22f5cf
AP		 5450
5451 if (!best)
5452 best = check_cpuid_limit(vcpu, function, index);
5453
8776e519 5454 if (best) {
5fdbf976
MT		 5455 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
5456 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
5457 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
5458 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 5459 }
8776e519 5460 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 5461 trace_kvm_cpuid(function,
5462 kvm_register_read(vcpu, VCPU_REGS_RAX),
5463 kvm_register_read(vcpu, VCPU_REGS_RBX),
5464 kvm_register_read(vcpu, VCPU_REGS_RCX),
5465 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 5466}
5467EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 5468
b6c7a5dc
HB		 5469/*
5470 * Check if userspace requested an interrupt window, and that the
5471 * interrupt window is open.
5472 *
5473 * No need to exit to userspace if we already have an interrupt queued.
5474 */
851ba692 5475static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5476{
8061823a 5477 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5478 vcpu->run->request_interrupt_window &&
5df56646 5479 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5480}
5481
851ba692 5482static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5483{
851ba692
AK		 5484 struct kvm_run *kvm_run = vcpu->run;
5485
91586a3b 5486 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5487 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5488 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5489 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5490 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5491 else
b6c7a5dc 5492 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5493 kvm_arch_interrupt_allowed(vcpu) &&
5494 !kvm_cpu_has_interrupt(vcpu) &&
5495 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5496}
5497
b93463aa
AK		 5498static void vapic_enter(struct kvm_vcpu *vcpu)
5499{
5500 struct kvm_lapic *apic = vcpu->arch.apic;
5501 struct page *page;
5502
5503 if (!apic || !apic->vapic_addr)
5504 return;
5505
5506 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 5507
5508 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 5509}
5510
5511static void vapic_exit(struct kvm_vcpu *vcpu)
5512{
5513 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 5514 int idx;
b93463aa
AK		 5515
5516 if (!apic || !apic->vapic_addr)
5517 return;
5518
f656ce01 5519 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 5520 kvm_release_page_dirty(apic->vapic_page);
5521 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 5522 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 5523}
5524
95ba8273
GN		 5525static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5526{
5527 int max_irr, tpr;
5528
5529 if (!kvm_x86_ops->update_cr8_intercept)
5530 return;
5531
88c808fd
AK		 5532 if (!vcpu->arch.apic)
5533 return;
5534
8db3baa2
GN		 5535 if (!vcpu->arch.apic->vapic_addr)
5536 max_irr = kvm_lapic_find_highest_irr(vcpu);
5537 else
5538 max_irr = -1;
95ba8273
GN		 5539
5540 if (max_irr != -1)
5541 max_irr >>= 4;
5542
5543 tpr = kvm_lapic_get_cr8(vcpu);
5544
5545 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5546}
5547
851ba692 5548static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 5549{
5550 /* try to reinject previous events if any */
b59bb7bd 5551 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5552 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5553 vcpu->arch.exception.has_error_code,
5554 vcpu->arch.exception.error_code);
b59bb7bd
GN		 5555 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5556 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5557 vcpu->arch.exception.error_code,
5558 vcpu->arch.exception.reinject);
b59bb7bd
GN		 5559 return;
5560 }
5561
95ba8273
GN		 5562 if (vcpu->arch.nmi_injected) {
5563 kvm_x86_ops->set_nmi(vcpu);
5564 return;
5565 }
5566
5567 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5568 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5569 return;
5570 }
5571
5572 /* try to inject new event if pending */
5573 if (vcpu->arch.nmi_pending) {
5574 if (kvm_x86_ops->nmi_allowed(vcpu)) {
5575 vcpu->arch.nmi_pending = false;
5576 vcpu->arch.nmi_injected = true;
5577 kvm_x86_ops->set_nmi(vcpu);
5578 }
5579 } else if (kvm_cpu_has_interrupt(vcpu)) {
5580 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5581 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5582 false);
5583 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5584 }
5585 }
5586}
5587
2acf923e
DC		 5588static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
5589{
5590 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
5591 !vcpu->guest_xcr0_loaded) {
5592 /* kvm_set_xcr() also depends on this */
5593 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
5594 vcpu->guest_xcr0_loaded = 1;
5595 }
5596}
5597
5598static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
5599{
5600 if (vcpu->guest_xcr0_loaded) {
5601 if (vcpu->arch.xcr0 != host_xcr0)
5602 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
5603 vcpu->guest_xcr0_loaded = 0;
5604 }
5605}
5606
851ba692 5607static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5608{
5609 int r;
1499e54a 5610 bool nmi_pending;
6a8b1d13 5611 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5612 vcpu->run->request_interrupt_window;
b6c7a5dc 5613
3e007509 5614 if (vcpu->requests) {
a8eeb04a 5615 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5616 kvm_mmu_unload(vcpu);
a8eeb04a 5617 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5618 __kvm_migrate_timers(vcpu);
34c238a1
ZA		 5619 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5620 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 5621 if (unlikely(r))
5622 goto out;
5623 }
a8eeb04a 5624 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5625 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5626 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5627 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5628 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5629 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5630 r = 0;
5631 goto out;
5632 }
a8eeb04a 5633 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5634 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5635 r = 0;
5636 goto out;
5637 }
a8eeb04a 5638 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5639 vcpu->fpu_active = 0;
5640 kvm_x86_ops->fpu_deactivate(vcpu);
5641 }
af585b92
GN		 5642 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5643 /* Page is swapped out. Do synthetic halt */
5644 vcpu->arch.apf.halted = true;
5645 r = 1;
5646 goto out;
5647 }
c9aaa895
GC		 5648 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5649 record_steal_time(vcpu);
5650
2f52d58c 5651 }
b93463aa 5652
3e007509
AK		 5653 r = kvm_mmu_reload(vcpu);
5654 if (unlikely(r))
5655 goto out;
5656
1499e54a
GN		 5657 /*
5658 * An NMI can be injected between local nmi_pending read and
5659 * vcpu->arch.nmi_pending read inside inject_pending_event().
5660 * But in that case, KVM_REQ_EVENT will be set, which makes
5661 * the race described above benign.
5662 */
5663 nmi_pending = ACCESS_ONCE(vcpu->arch.nmi_pending);
5664
b463a6f7
AK		 5665 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5666 inject_pending_event(vcpu);
5667
5668 /* enable NMI/IRQ window open exits if needed */
1499e54a 5669 if (nmi_pending)
b463a6f7
AK		 5670 kvm_x86_ops->enable_nmi_window(vcpu);
5671 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
5672 kvm_x86_ops->enable_irq_window(vcpu);
5673
5674 if (kvm_lapic_enabled(vcpu)) {
5675 update_cr8_intercept(vcpu);
5676 kvm_lapic_sync_to_vapic(vcpu);
5677 }
5678 }
5679
b6c7a5dc
HB		 5680 preempt_disable();
5681
5682 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 5683 if (vcpu->fpu_active)
5684 kvm_load_guest_fpu(vcpu);
2acf923e 5685 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 5686
6b7e2d09
XG		 5687 vcpu->mode = IN_GUEST_MODE;
5688
5689 /* We should set ->mode before check ->requests,
5690 * see the comment in make_all_cpus_request.
5691 */
5692 smp_mb();
b6c7a5dc 5693
d94e1dc9 5694 local_irq_disable();
32f88400 5695
6b7e2d09 5696 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 5697 || need_resched() || signal_pending(current)) {
6b7e2d09 5698 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5699 smp_wmb();
6c142801
AK		 5700 local_irq_enable();
5701 preempt_enable();
b463a6f7 5702 kvm_x86_ops->cancel_injection(vcpu);
6c142801
AK		 5703 r = 1;
5704 goto out;
5705 }
5706
f656ce01 5707 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 5708
b6c7a5dc
HB		 5709 kvm_guest_enter();
5710
42dbaa5a 5711 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 5712 set_debugreg(0, 7);
5713 set_debugreg(vcpu->arch.eff_db[0], 0);
5714 set_debugreg(vcpu->arch.eff_db[1], 1);
5715 set_debugreg(vcpu->arch.eff_db[2], 2);
5716 set_debugreg(vcpu->arch.eff_db[3], 3);
5717 }
b6c7a5dc 5718
229456fc 5719 trace_kvm_entry(vcpu->vcpu_id);
851ba692 5720 kvm_x86_ops->run(vcpu);
b6c7a5dc 5721
24f1e32c
FW		 5722 /*
5723 * If the guest has used debug registers, at least dr7
5724 * will be disabled while returning to the host.
5725 * If we don't have active breakpoints in the host, we don't
5726 * care about the messed up debug address registers. But if
5727 * we have some of them active, restore the old state.
5728 */
59d8eb53 5729 if (hw_breakpoint_active())
24f1e32c 5730 hw_breakpoint_restore();
42dbaa5a 5731
1d5f066e
ZA		 5732 kvm_get_msr(vcpu, MSR_IA32_TSC, &vcpu->arch.last_guest_tsc);
5733
6b7e2d09 5734 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5735 smp_wmb();
b6c7a5dc
HB		 5736 local_irq_enable();
5737
5738 ++vcpu->stat.exits;
5739
5740 /*
5741 * We must have an instruction between local_irq_enable() and
5742 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5743 * the interrupt shadow. The stat.exits increment will do nicely.
5744 * But we need to prevent reordering, hence this barrier():
5745 */
5746 barrier();
5747
5748 kvm_guest_exit();
5749
5750 preempt_enable();
5751
f656ce01 5752 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 5753
b6c7a5dc
HB		 5754 /*
5755 * Profile KVM exit RIPs:
5756 */
5757 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 5758 unsigned long rip = kvm_rip_read(vcpu);
5759 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 5760 }
5761
298101da 5762
b93463aa
AK		 5763 kvm_lapic_sync_from_vapic(vcpu);
5764
851ba692 5765 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 5766out:
5767 return r;
5768}
b6c7a5dc 5769
09cec754 5770
851ba692 5771static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 5772{
5773 int r;
f656ce01 5774 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 5775
5776 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 5777 pr_debug("vcpu %d received sipi with vector # %x\n",
5778 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 5779 kvm_lapic_reset(vcpu);
5f179287 5780 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 5781 if (r)
5782 return r;
5783 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 5784 }
5785
f656ce01 5786 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 5787 vapic_enter(vcpu);
5788
5789 r = 1;
5790 while (r > 0) {
af585b92
GN		 5791 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
5792 !vcpu->arch.apf.halted)
851ba692 5793 r = vcpu_enter_guest(vcpu);
d7690175 5794 else {
f656ce01 5795 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 5796 kvm_vcpu_block(vcpu);
f656ce01 5797 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
a8eeb04a 5798 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
09cec754
GN		 5799 {
5800 switch(vcpu->arch.mp_state) {
5801 case KVM_MP_STATE_HALTED:
d7690175 5802 vcpu->arch.mp_state =
09cec754
GN		 5803 KVM_MP_STATE_RUNNABLE;
5804 case KVM_MP_STATE_RUNNABLE:
af585b92 5805 vcpu->arch.apf.halted = false;
09cec754
GN		 5806 break;
5807 case KVM_MP_STATE_SIPI_RECEIVED:
5808 default:
5809 r = -EINTR;
5810 break;
5811 }
5812 }
d7690175
MT		 5813 }
5814
09cec754
GN		 5815 if (r <= 0)
5816 break;
5817
5818 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5819 if (kvm_cpu_has_pending_timer(vcpu))
5820 kvm_inject_pending_timer_irqs(vcpu);
5821
851ba692 5822 if (dm_request_for_irq_injection(vcpu)) {
09cec754 5823 r = -EINTR;
851ba692 5824 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5825 ++vcpu->stat.request_irq_exits;
5826 }
af585b92
GN		 5827
5828 kvm_check_async_pf_completion(vcpu);
5829
09cec754
GN		 5830 if (signal_pending(current)) {
5831 r = -EINTR;
851ba692 5832 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5833 ++vcpu->stat.signal_exits;
5834 }
5835 if (need_resched()) {
f656ce01 5836 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 5837 kvm_resched(vcpu);
f656ce01 5838 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 5839 }
b6c7a5dc
HB		 5840 }
5841
f656ce01 5842 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 5843
b93463aa
AK		 5844 vapic_exit(vcpu);
5845
b6c7a5dc
HB		 5846 return r;
5847}
5848
5287f194
AK		 5849static int complete_mmio(struct kvm_vcpu *vcpu)
5850{
5851 struct kvm_run *run = vcpu->run;
5852 int r;
5853
5854 if (!(vcpu->arch.pio.count || vcpu->mmio_needed))
5855 return 1;
5856
5857 if (vcpu->mmio_needed) {
5287f194 5858 vcpu->mmio_needed = 0;
cef4dea0 5859 if (!vcpu->mmio_is_write)
0004c7c2
GN		 5860 memcpy(vcpu->mmio_data + vcpu->mmio_index,
5861 run->mmio.data, 8);
cef4dea0
AK		 5862 vcpu->mmio_index += 8;
5863 if (vcpu->mmio_index < vcpu->mmio_size) {
5864 run->exit_reason = KVM_EXIT_MMIO;
5865 run->mmio.phys_addr = vcpu->mmio_phys_addr + vcpu->mmio_index;
5866 memcpy(run->mmio.data, vcpu->mmio_data + vcpu->mmio_index, 8);
5867 run->mmio.len = min(vcpu->mmio_size - vcpu->mmio_index, 8);
5868 run->mmio.is_write = vcpu->mmio_is_write;
5869 vcpu->mmio_needed = 1;
5870 return 0;
5871 }
5872 if (vcpu->mmio_is_write)
5873 return 1;
5874 vcpu->mmio_read_completed = 1;
5287f194
AK		 5875 }
5876 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5877 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
5878 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5879 if (r != EMULATE_DONE)
5880 return 0;
5881 return 1;
5882}
5883
b6c7a5dc
HB		 5884int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
5885{
5886 int r;
5887 sigset_t sigsaved;
5888
e5c30142
AK		 5889 if (!tsk_used_math(current) && init_fpu(current))
5890 return -ENOMEM;
5891
ac9f6dc0
AK		 5892 if (vcpu->sigset_active)
5893 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
5894
a4535290 5895 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 5896 kvm_vcpu_block(vcpu);
d7690175 5897 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 5898 r = -EAGAIN;
5899 goto out;
b6c7a5dc
HB		 5900 }
5901
b6c7a5dc 5902 /* re-sync apic's tpr */
eea1cff9
AP		 5903 if (!irqchip_in_kernel(vcpu->kvm)) {
5904 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
5905 r = -EINVAL;
5906 goto out;
5907 }
5908 }
b6c7a5dc 5909
5287f194
AK		 5910 r = complete_mmio(vcpu);
5911 if (r <= 0)
5912 goto out;
5913
5fdbf976
MT		 5914 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
5915 kvm_register_write(vcpu, VCPU_REGS_RAX,
5916 kvm_run->hypercall.ret);
b6c7a5dc 5917
851ba692 5918 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 5919
5920out:
f1d86e46 5921 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 5922 if (vcpu->sigset_active)
5923 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
5924
b6c7a5dc
HB		 5925 return r;
5926}
5927
5928int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5929{
7ae441ea
GN		 5930 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
5931 /*
5932 * We are here if userspace calls get_regs() in the middle of
5933 * instruction emulation. Registers state needs to be copied
5934 * back from emulation context to vcpu. Usrapace shouldn't do
5935 * that usually, but some bad designed PV devices (vmware
5936 * backdoor interface) need this to work
5937 */
9dac77fa
AK		 5938 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5939 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
7ae441ea
GN		 5940 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5941 }
5fdbf976
MT		 5942 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5943 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5944 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5945 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5946 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
5947 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
5948 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5949 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 5950#ifdef CONFIG_X86_64
5fdbf976
MT		 5951 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
5952 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
5953 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
5954 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
5955 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
5956 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
5957 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
5958 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 5959#endif
5960
5fdbf976 5961 regs->rip = kvm_rip_read(vcpu);
91586a3b 5962 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 5963
b6c7a5dc
HB		 5964 return 0;
5965}
5966
5967int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5968{
7ae441ea
GN		 5969 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
5970 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5971
5fdbf976
MT		 5972 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
5973 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
5974 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
5975 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
5976 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
5977 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
5978 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
5979 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 5980#ifdef CONFIG_X86_64
5fdbf976
MT		 5981 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
5982 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
5983 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
5984 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
5985 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
5986 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
5987 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
5988 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 5989#endif
5990
5fdbf976 5991 kvm_rip_write(vcpu, regs->rip);
91586a3b 5992 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 5993
b4f14abd
JK		 5994 vcpu->arch.exception.pending = false;
5995
3842d135
AK		 5996 kvm_make_request(KVM_REQ_EVENT, vcpu);
5997
b6c7a5dc
HB		 5998 return 0;
5999}
6000
b6c7a5dc
HB		 6001void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6002{
6003 struct kvm_segment cs;
6004
3e6e0aab 6005 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6006 *db = cs.db;
6007 *l = cs.l;
6008}
6009EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6010
6011int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6012 struct kvm_sregs *sregs)
6013{
89a27f4d 6014 struct desc_ptr dt;
b6c7a5dc 6015
3e6e0aab
GT		 6016 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6017 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6018 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6019 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6020 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6021 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6022
3e6e0aab
GT		 6023 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6024 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6025
6026 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6027 sregs->idt.limit = dt.size;
6028 sregs->idt.base = dt.address;
b6c7a5dc 6029 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6030 sregs->gdt.limit = dt.size;
6031 sregs->gdt.base = dt.address;
b6c7a5dc 6032
4d4ec087 6033 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6034 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6035 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6036 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6037 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6038 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6039 sregs->apic_base = kvm_get_apic_base(vcpu);
6040
923c61bb 6041 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6042
36752c9b 6043 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6044 set_bit(vcpu->arch.interrupt.nr,
6045 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6046
b6c7a5dc
HB		 6047 return 0;
6048}
6049
62d9f0db
MT		 6050int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6051 struct kvm_mp_state *mp_state)
6052{
62d9f0db 6053 mp_state->mp_state = vcpu->arch.mp_state;
62d9f0db
MT		 6054 return 0;
6055}
6056
6057int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6058 struct kvm_mp_state *mp_state)
6059{
62d9f0db 6060 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6061 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6062 return 0;
6063}
6064
e269fb21
JK		 6065int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason,
6066 bool has_error_code, u32 error_code)
b6c7a5dc 6067{
9d74191a 6068 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6069 int ret;
e01c2426 6070
8ec4722d 6071 init_emulate_ctxt(vcpu);
c697518a 6072
9d74191a
TY		 6073 ret = emulator_task_switch(ctxt, tss_selector, reason,
6074 has_error_code, error_code);
c697518a 6075
c697518a 6076 if (ret)
19d04437 6077 return EMULATE_FAIL;
37817f29 6078
9dac77fa 6079 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
9d74191a
TY		 6080 kvm_rip_write(vcpu, ctxt->eip);
6081 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6082 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6083 return EMULATE_DONE;
37817f29
IE		 6084}
6085EXPORT_SYMBOL_GPL(kvm_task_switch);
6086
b6c7a5dc
HB		 6087int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6088 struct kvm_sregs *sregs)
6089{
6090 int mmu_reset_needed = 0;
63f42e02 6091 int pending_vec, max_bits, idx;
89a27f4d 6092 struct desc_ptr dt;
b6c7a5dc 6093
89a27f4d
GN		 6094 dt.size = sregs->idt.limit;
6095 dt.address = sregs->idt.base;
b6c7a5dc 6096 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 6097 dt.size = sregs->gdt.limit;
6098 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 6099 kvm_x86_ops->set_gdt(vcpu, &dt);
6100
ad312c7c 6101 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 6102 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 6103 vcpu->arch.cr3 = sregs->cr3;
aff48baa 6104 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 6105
2d3ad1f4 6106 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 6107
f6801dff 6108 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 6109 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 6110 kvm_set_apic_base(vcpu, sregs->apic_base);
6111
4d4ec087 6112 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 6113 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 6114 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 6115
fc78f519 6116 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 6117 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c
SY		 6118 if (sregs->cr4 & X86_CR4_OSXSAVE)
6119 update_cpuid(vcpu);
63f42e02
XG		 6120
6121 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 6122 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 6123 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 6124 mmu_reset_needed = 1;
6125 }
63f42e02 6126 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 6127
6128 if (mmu_reset_needed)
6129 kvm_mmu_reset_context(vcpu);
6130
923c61bb
GN		 6131 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
6132 pending_vec = find_first_bit(
6133 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6134 if (pending_vec < max_bits) {
66fd3f7f 6135 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 6136 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 6137 }
6138
3e6e0aab
GT		 6139 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6140 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6141 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6142 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6143 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6144 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6145
3e6e0aab
GT		 6146 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6147 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 6148
5f0269f5
ME		 6149 update_cr8_intercept(vcpu);
6150
9c3e4aab 6151 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 6152 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 6153 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 6154 !is_protmode(vcpu))
9c3e4aab
MT		 6155 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6156
3842d135
AK		 6157 kvm_make_request(KVM_REQ_EVENT, vcpu);
6158
b6c7a5dc
HB		 6159 return 0;
6160}
6161
d0bfb940
JK		 6162int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6163 struct kvm_guest_debug *dbg)
b6c7a5dc 6164{
355be0b9 6165 unsigned long rflags;
ae675ef0 6166 int i, r;
b6c7a5dc 6167
4f926bf2
JK		 6168 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6169 r = -EBUSY;
6170 if (vcpu->arch.exception.pending)
2122ff5e 6171 goto out;
4f926bf2
JK		 6172 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6173 kvm_queue_exception(vcpu, DB_VECTOR);
6174 else
6175 kvm_queue_exception(vcpu, BP_VECTOR);
6176 }
6177
91586a3b
JK		 6178 /*
6179 * Read rflags as long as potentially injected trace flags are still
6180 * filtered out.
6181 */
6182 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 6183
6184 vcpu->guest_debug = dbg->control;
6185 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6186 vcpu->guest_debug = 0;
6187
6188 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 6189 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6190 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
6191 vcpu->arch.switch_db_regs =
6192 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
6193 } else {
6194 for (i = 0; i < KVM_NR_DB_REGS; i++)
6195 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6196 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
6197 }
6198
f92653ee
JK		 6199 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6200 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6201 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 6202
91586a3b
JK		 6203 /*
6204 * Trigger an rflags update that will inject or remove the trace
6205 * flags.
6206 */
6207 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 6208
355be0b9 6209 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 6210
4f926bf2 6211 r = 0;
d0bfb940 6212
2122ff5e 6213out:
b6c7a5dc
HB		 6214
6215 return r;
6216}
6217
8b006791
ZX		 6218/*
6219 * Translate a guest virtual address to a guest physical address.
6220 */
6221int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6222 struct kvm_translation *tr)
6223{
6224 unsigned long vaddr = tr->linear_address;
6225 gpa_t gpa;
f656ce01 6226 int idx;
8b006791 6227
f656ce01 6228 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 6229 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 6230 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 6231 tr->physical_address = gpa;
6232 tr->valid = gpa != UNMAPPED_GVA;
6233 tr->writeable = 1;
6234 tr->usermode = 0;
8b006791
ZX		 6235
6236 return 0;
6237}
6238
d0752060
HB		 6239int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6240{
98918833
SY		 6241 struct i387_fxsave_struct *fxsave =
6242 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6243
d0752060
HB		 6244 memcpy(fpu->fpr, fxsave->st_space, 128);
6245 fpu->fcw = fxsave->cwd;
6246 fpu->fsw = fxsave->swd;
6247 fpu->ftwx = fxsave->twd;
6248 fpu->last_opcode = fxsave->fop;
6249 fpu->last_ip = fxsave->rip;
6250 fpu->last_dp = fxsave->rdp;
6251 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6252
d0752060
HB		 6253 return 0;
6254}
6255
6256int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6257{
98918833
SY		 6258 struct i387_fxsave_struct *fxsave =
6259 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6260
d0752060
HB		 6261 memcpy(fxsave->st_space, fpu->fpr, 128);
6262 fxsave->cwd = fpu->fcw;
6263 fxsave->swd = fpu->fsw;
6264 fxsave->twd = fpu->ftwx;
6265 fxsave->fop = fpu->last_opcode;
6266 fxsave->rip = fpu->last_ip;
6267 fxsave->rdp = fpu->last_dp;
6268 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6269
d0752060
HB		 6270 return 0;
6271}
6272
10ab25cd 6273int fx_init(struct kvm_vcpu *vcpu)
d0752060 6274{
10ab25cd
JK		 6275 int err;
6276
6277 err = fpu_alloc(&vcpu->arch.guest_fpu);
6278 if (err)
6279 return err;
6280
98918833 6281 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 6282
2acf923e
DC		 6283 /*
6284 * Ensure guest xcr0 is valid for loading
6285 */
6286 vcpu->arch.xcr0 = XSTATE_FP;
6287
ad312c7c 6288 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 6289
6290 return 0;
d0752060
HB		 6291}
6292EXPORT_SYMBOL_GPL(fx_init);
6293
98918833
SY		 6294static void fx_free(struct kvm_vcpu *vcpu)
6295{
6296 fpu_free(&vcpu->arch.guest_fpu);
6297}
6298
d0752060
HB		 6299void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6300{
2608d7a1 6301 if (vcpu->guest_fpu_loaded)
d0752060
HB		 6302 return;
6303
2acf923e
DC		 6304 /*
6305 * Restore all possible states in the guest,
6306 * and assume host would use all available bits.
6307 * Guest xcr0 would be loaded later.
6308 */
6309 kvm_put_guest_xcr0(vcpu);
d0752060 6310 vcpu->guest_fpu_loaded = 1;
7cf30855 6311 unlazy_fpu(current);
98918833 6312 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 6313 trace_kvm_fpu(1);
d0752060 6314}
d0752060
HB		 6315
6316void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6317{
2acf923e
DC		 6318 kvm_put_guest_xcr0(vcpu);
6319
d0752060
HB		 6320 if (!vcpu->guest_fpu_loaded)
6321 return;
6322
6323 vcpu->guest_fpu_loaded = 0;
98918833 6324 fpu_save_init(&vcpu->arch.guest_fpu);
f096ed85 6325 ++vcpu->stat.fpu_reload;
a8eeb04a 6326 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 6327 trace_kvm_fpu(0);
d0752060 6328}
e9b11c17
ZX		 6329
6330void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6331{
12f9a48f 6332 kvmclock_reset(vcpu);
7f1ea208 6333
f5f48ee1 6334 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 6335 fx_free(vcpu);
e9b11c17
ZX		 6336 kvm_x86_ops->vcpu_free(vcpu);
6337}
6338
6339struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6340 unsigned int id)
6341{
6755bae8
ZA		 6342 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6343 printk_once(KERN_WARNING
6344 "kvm: SMP vm created on host with unstable TSC; "
6345 "guest TSC will not be reliable\n");
26e5215f
AK		 6346 return kvm_x86_ops->vcpu_create(kvm, id);
6347}
e9b11c17 6348
26e5215f
AK		 6349int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6350{
6351 int r;
e9b11c17 6352
0bed3b56 6353 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 6354 vcpu_load(vcpu);
6355 r = kvm_arch_vcpu_reset(vcpu);
6356 if (r == 0)
6357 r = kvm_mmu_setup(vcpu);
6358 vcpu_put(vcpu);
e9b11c17 6359
26e5215f 6360 return r;
e9b11c17
ZX		 6361}
6362
d40ccc62 6363void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 6364{
344d9588
GN		 6365 vcpu->arch.apf.msr_val = 0;
6366
e9b11c17
ZX		 6367 vcpu_load(vcpu);
6368 kvm_mmu_unload(vcpu);
6369 vcpu_put(vcpu);
6370
98918833 6371 fx_free(vcpu);
e9b11c17
ZX		 6372 kvm_x86_ops->vcpu_free(vcpu);
6373}
6374
6375int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
6376{
448fa4a9
JK		 6377 vcpu->arch.nmi_pending = false;
6378 vcpu->arch.nmi_injected = false;
6379
42dbaa5a
JK		 6380 vcpu->arch.switch_db_regs = 0;
6381 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6382 vcpu->arch.dr6 = DR6_FIXED_1;
6383 vcpu->arch.dr7 = DR7_FIXED_1;
6384
3842d135 6385 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 6386 vcpu->arch.apf.msr_val = 0;
c9aaa895 6387 vcpu->arch.st.msr_val = 0;
3842d135 6388
12f9a48f
GC		 6389 kvmclock_reset(vcpu);
6390
af585b92
GN		 6391 kvm_clear_async_pf_completion_queue(vcpu);
6392 kvm_async_pf_hash_reset(vcpu);
6393 vcpu->arch.apf.halted = false;
3842d135 6394
e9b11c17
ZX		 6395 return kvm_x86_ops->vcpu_reset(vcpu);
6396}
6397
10474ae8 6398int kvm_arch_hardware_enable(void *garbage)
e9b11c17 6399{
ca84d1a2
ZA		 6400 struct kvm *kvm;
6401 struct kvm_vcpu *vcpu;
6402 int i;
18863bdd
AK		 6403
6404 kvm_shared_msr_cpu_online();
ca84d1a2
ZA		 6405 list_for_each_entry(kvm, &vm_list, vm_list)
6406 kvm_for_each_vcpu(i, vcpu, kvm)
6407 if (vcpu->cpu == smp_processor_id())
c285545f 6408 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
10474ae8 6409 return kvm_x86_ops->hardware_enable(garbage);
e9b11c17
ZX		 6410}
6411
6412void kvm_arch_hardware_disable(void *garbage)
6413{
6414 kvm_x86_ops->hardware_disable(garbage);
3548bab5 6415 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 6416}
6417
6418int kvm_arch_hardware_setup(void)
6419{
6420 return kvm_x86_ops->hardware_setup();
6421}
6422
6423void kvm_arch_hardware_unsetup(void)
6424{
6425 kvm_x86_ops->hardware_unsetup();
6426}
6427
6428void kvm_arch_check_processor_compat(void *rtn)
6429{
6430 kvm_x86_ops->check_processor_compatibility(rtn);
6431}
6432
6433int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6434{
6435 struct page *page;
6436 struct kvm *kvm;
6437 int r;
6438
6439 BUG_ON(vcpu->kvm == NULL);
6440 kvm = vcpu->kvm;
6441
9aabc88f 6442 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
14dfe855 6443 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
ad312c7c 6444 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c30a358d 6445 vcpu->arch.mmu.translate_gpa = translate_gpa;
02f59dc9 6446 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
c5af89b6 6447 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 6448 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 6449 else
a4535290 6450 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 6451
6452 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6453 if (!page) {
6454 r = -ENOMEM;
6455 goto fail;
6456 }
ad312c7c 6457 vcpu->arch.pio_data = page_address(page);
e9b11c17 6458
1e993611 6459 kvm_init_tsc_catchup(vcpu, max_tsc_khz);
c285545f 6460
e9b11c17
ZX		 6461 r = kvm_mmu_create(vcpu);
6462 if (r < 0)
6463 goto fail_free_pio_data;
6464
6465 if (irqchip_in_kernel(kvm)) {
6466 r = kvm_create_lapic(vcpu);
6467 if (r < 0)
6468 goto fail_mmu_destroy;
6469 }
6470
890ca9ae
HY		 6471 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6472 GFP_KERNEL);
6473 if (!vcpu->arch.mce_banks) {
6474 r = -ENOMEM;
443c39bc 6475 goto fail_free_lapic;
890ca9ae
HY		 6476 }
6477 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6478
f5f48ee1
SY		 6479 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
6480 goto fail_free_mce_banks;
6481
af585b92
GN		 6482 kvm_async_pf_hash_reset(vcpu);
6483
e9b11c17 6484 return 0;
f5f48ee1
SY		 6485fail_free_mce_banks:
6486 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 6487fail_free_lapic:
6488 kvm_free_lapic(vcpu);
e9b11c17
ZX		 6489fail_mmu_destroy:
6490 kvm_mmu_destroy(vcpu);
6491fail_free_pio_data:
ad312c7c 6492 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 6493fail:
6494 return r;
6495}
6496
6497void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6498{
f656ce01
MT		 6499 int idx;
6500
36cb93fd 6501 kfree(vcpu->arch.mce_banks);
e9b11c17 6502 kvm_free_lapic(vcpu);
f656ce01 6503 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 6504 kvm_mmu_destroy(vcpu);
f656ce01 6505 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 6506 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 6507}
d19a9cd2 6508
d89f5eff 6509int kvm_arch_init_vm(struct kvm *kvm)
d19a9cd2 6510{
f05e70ac 6511 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 6512 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 6513
5550af4d
SY		 6514 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
6515 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
6516
038f8c11 6517 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
53f658b3 6518
d89f5eff 6519 return 0;
d19a9cd2
ZX		 6520}
6521
6522static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
6523{
6524 vcpu_load(vcpu);
6525 kvm_mmu_unload(vcpu);
6526 vcpu_put(vcpu);
6527}
6528
6529static void kvm_free_vcpus(struct kvm *kvm)
6530{
6531 unsigned int i;
988a2cae 6532 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 6533
6534 /*
6535 * Unpin any mmu pages first.
6536 */
af585b92
GN		 6537 kvm_for_each_vcpu(i, vcpu, kvm) {
6538 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 6539 kvm_unload_vcpu_mmu(vcpu);
af585b92 6540 }
988a2cae
GN		 6541 kvm_for_each_vcpu(i, vcpu, kvm)
6542 kvm_arch_vcpu_free(vcpu);
6543
6544 mutex_lock(&kvm->lock);
6545 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
6546 kvm->vcpus[i] = NULL;
d19a9cd2 6547
988a2cae
GN		 6548 atomic_set(&kvm->online_vcpus, 0);
6549 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 6550}
6551
ad8ba2cd
SY		 6552void kvm_arch_sync_events(struct kvm *kvm)
6553{
ba4cef31 6554 kvm_free_all_assigned_devices(kvm);
aea924f6 6555 kvm_free_pit(kvm);
ad8ba2cd
SY		 6556}
6557
d19a9cd2
ZX		 6558void kvm_arch_destroy_vm(struct kvm *kvm)
6559{
6eb55818 6560 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 6561 kfree(kvm->arch.vpic);
6562 kfree(kvm->arch.vioapic);
d19a9cd2 6563 kvm_free_vcpus(kvm);
3d45830c
AK		 6564 if (kvm->arch.apic_access_page)
6565 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 6566 if (kvm->arch.ept_identity_pagetable)
6567 put_page(kvm->arch.ept_identity_pagetable);
d19a9cd2 6568}
0de10343 6569
f7784b8e
MT		 6570int kvm_arch_prepare_memory_region(struct kvm *kvm,
6571 struct kvm_memory_slot *memslot,
0de10343 6572 struct kvm_memory_slot old,
f7784b8e 6573 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 6574 int user_alloc)
6575{
f7784b8e 6576 int npages = memslot->npages;
7ac77099
AK		 6577 int map_flags = MAP_PRIVATE | MAP_ANONYMOUS;
6578
6579 /* Prevent internal slot pages from being moved by fork()/COW. */
6580 if (memslot->id >= KVM_MEMORY_SLOTS)
6581 map_flags = MAP_SHARED | MAP_ANONYMOUS;
0de10343
ZX		 6582
6583 /*To keep backward compatibility with older userspace,
6584 *x86 needs to hanlde !user_alloc case.
6585 */
6586 if (!user_alloc) {
6587 if (npages && !old.rmap) {
604b38ac
AA		 6588 unsigned long userspace_addr;
6589
72dc67a6 6590 down_write(&current->mm->mmap_sem);
604b38ac
AA		 6591 userspace_addr = do_mmap(NULL, 0,
6592 npages * PAGE_SIZE,
6593 PROT_READ | PROT_WRITE,
7ac77099 6594 map_flags,
604b38ac 6595 0);
72dc67a6 6596 up_write(&current->mm->mmap_sem);
0de10343 6597
604b38ac
AA		 6598 if (IS_ERR((void *)userspace_addr))
6599 return PTR_ERR((void *)userspace_addr);
6600
604b38ac 6601 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 6602 }
6603 }
6604
f7784b8e
MT		 6605
6606 return 0;
6607}
6608
6609void kvm_arch_commit_memory_region(struct kvm *kvm,
6610 struct kvm_userspace_memory_region *mem,
6611 struct kvm_memory_slot old,
6612 int user_alloc)
6613{
6614
48c0e4e9 6615 int nr_mmu_pages = 0, npages = mem->memory_size >> PAGE_SHIFT;
f7784b8e
MT		 6616
6617 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
6618 int ret;
6619
6620 down_write(&current->mm->mmap_sem);
6621 ret = do_munmap(current->mm, old.userspace_addr,
6622 old.npages * PAGE_SIZE);
6623 up_write(&current->mm->mmap_sem);
6624 if (ret < 0)
6625 printk(KERN_WARNING
6626 "kvm_vm_ioctl_set_memory_region: "
6627 "failed to munmap memory\n");
6628 }
6629
48c0e4e9
XG		 6630 if (!kvm->arch.n_requested_mmu_pages)
6631 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
6632
7c8a83b7 6633 spin_lock(&kvm->mmu_lock);
48c0e4e9 6634 if (nr_mmu_pages)
0de10343 6635 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
0de10343 6636 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 6637 spin_unlock(&kvm->mmu_lock);
0de10343 6638}
1d737c8a 6639
34d4cb8f
MT		 6640void kvm_arch_flush_shadow(struct kvm *kvm)
6641{
6642 kvm_mmu_zap_all(kvm);
8986ecc0 6643 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 6644}
6645
1d737c8a
ZX		 6646int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
6647{
af585b92
GN		 6648 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6649 !vcpu->arch.apf.halted)
6650 || !list_empty_careful(&vcpu->async_pf.done)
a1b37100
GN		 6651 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
6652 || vcpu->arch.nmi_pending ||
6653 (kvm_arch_interrupt_allowed(vcpu) &&
6654 kvm_cpu_has_interrupt(vcpu));
1d737c8a 6655}
5736199a 6656
5736199a
ZX		 6657void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
6658{
32f88400
MT		 6659 int me;
6660 int cpu = vcpu->cpu;
5736199a
ZX		 6661
6662 if (waitqueue_active(&vcpu->wq)) {
6663 wake_up_interruptible(&vcpu->wq);
6664 ++vcpu->stat.halt_wakeup;
6665 }
32f88400
MT		 6666
6667 me = get_cpu();
6668 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
6b7e2d09 6669 if (kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE)
32f88400 6670 smp_send_reschedule(cpu);
e9571ed5 6671 put_cpu();
5736199a 6672}
78646121
GN		 6673
6674int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
6675{
6676 return kvm_x86_ops->interrupt_allowed(vcpu);
6677}
229456fc 6678
f92653ee
JK		 6679bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
6680{
6681 unsigned long current_rip = kvm_rip_read(vcpu) +
6682 get_segment_base(vcpu, VCPU_SREG_CS);
6683
6684 return current_rip == linear_rip;
6685}
6686EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
6687
94fe45da
JK		 6688unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
6689{
6690 unsigned long rflags;
6691
6692 rflags = kvm_x86_ops->get_rflags(vcpu);
6693 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 6694 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 6695 return rflags;
6696}
6697EXPORT_SYMBOL_GPL(kvm_get_rflags);
6698
6699void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
6700{
6701 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 6702 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 6703 rflags |= X86_EFLAGS_TF;
94fe45da 6704 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 6705 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 6706}
6707EXPORT_SYMBOL_GPL(kvm_set_rflags);
6708
56028d08
GN		 6709void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
6710{
6711 int r;
6712
fb67e14f 6713 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
c4806acd 6714 is_error_page(work->page))
56028d08
GN		 6715 return;
6716
6717 r = kvm_mmu_reload(vcpu);
6718 if (unlikely(r))
6719 return;
6720
fb67e14f
XG		 6721 if (!vcpu->arch.mmu.direct_map &&
6722 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
6723 return;
6724
56028d08
GN		 6725 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
6726}
6727
af585b92
GN		 6728static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
6729{
6730 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
6731}
6732
6733static inline u32 kvm_async_pf_next_probe(u32 key)
6734{
6735 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
6736}
6737
6738static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6739{
6740 u32 key = kvm_async_pf_hash_fn(gfn);
6741
6742 while (vcpu->arch.apf.gfns[key] != ~0)
6743 key = kvm_async_pf_next_probe(key);
6744
6745 vcpu->arch.apf.gfns[key] = gfn;
6746}
6747
6748static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
6749{
6750 int i;
6751 u32 key = kvm_async_pf_hash_fn(gfn);
6752
6753 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 6754 (vcpu->arch.apf.gfns[key] != gfn &&
6755 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 6756 key = kvm_async_pf_next_probe(key);
6757
6758 return key;
6759}
6760
6761bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6762{
6763 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
6764}
6765
6766static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6767{
6768 u32 i, j, k;
6769
6770 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
6771 while (true) {
6772 vcpu->arch.apf.gfns[i] = ~0;
6773 do {
6774 j = kvm_async_pf_next_probe(j);
6775 if (vcpu->arch.apf.gfns[j] == ~0)
6776 return;
6777 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
6778 /*
6779 * k lies cyclically in ]i,j]
6780 * | i.k.j |
6781 * |....j i.k.| or |.k..j i...|
6782 */
6783 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
6784 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
6785 i = j;
6786 }
6787}
6788
7c90705b
GN		 6789static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
6790{
6791
6792 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
6793 sizeof(val));
6794}
6795
af585b92
GN		 6796void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
6797 struct kvm_async_pf *work)
6798{
6389ee94
AK		 6799 struct x86_exception fault;
6800
7c90705b 6801 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 6802 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 6803
6804 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 6805 (vcpu->arch.apf.send_user_only &&
6806 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 6807 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
6808 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 6809 fault.vector = PF_VECTOR;
6810 fault.error_code_valid = true;
6811 fault.error_code = 0;
6812 fault.nested_page_fault = false;
6813 fault.address = work->arch.token;
6814 kvm_inject_page_fault(vcpu, &fault);
7c90705b 6815 }
af585b92
GN		 6816}
6817
6818void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
6819 struct kvm_async_pf *work)
6820{
6389ee94
AK		 6821 struct x86_exception fault;
6822
7c90705b
GN		 6823 trace_kvm_async_pf_ready(work->arch.token, work->gva);
6824 if (is_error_page(work->page))
6825 work->arch.token = ~0; /* broadcast wakeup */
6826 else
6827 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
6828
6829 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
6830 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 6831 fault.vector = PF_VECTOR;
6832 fault.error_code_valid = true;
6833 fault.error_code = 0;
6834 fault.nested_page_fault = false;
6835 fault.address = work->arch.token;
6836 kvm_inject_page_fault(vcpu, &fault);
7c90705b 6837 }
e6d53e3b 6838 vcpu->arch.apf.halted = false;
7c90705b
GN		 6839}
6840
6841bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
6842{
6843 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
6844 return true;
6845 else
6846 return !kvm_event_needs_reinjection(vcpu) &&
6847 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 6848}
6849
229456fc
MT		 6850EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
6851EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
6852EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
6853EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
6854EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 6855EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 6856EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 6857EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 6858EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 6859EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 6860EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 6861EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
kernel source for telekom puls (alcatel/mediatek)