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KVM: Remove RDWRGSFS bit from CR4_RESERVED_BITS
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
313a3dc7 29
18068523 30#include <linux/clocksource.h>
4d5c5d0f 31#include <linux/interrupt.h>
313a3dc7
CO		 32#include <linux/kvm.h>
33#include <linux/fs.h>
34#include <linux/vmalloc.h>
5fb76f9b 35#include <linux/module.h>
0de10343 36#include <linux/mman.h>
2bacc55c 37#include <linux/highmem.h>
19de40a8 38#include <linux/iommu.h>
62c476c7 39#include <linux/intel-iommu.h>
c8076604 40#include <linux/cpufreq.h>
18863bdd 41#include <linux/user-return-notifier.h>
a983fb23 42#include <linux/srcu.h>
5a0e3ad6 43#include <linux/slab.h>
ff9d07a0 44#include <linux/perf_event.h>
7bee342a 45#include <linux/uaccess.h>
af585b92 46#include <linux/hash.h>
aec51dc4 47#include <trace/events/kvm.h>
2ed152af 48
229456fc
MT		 49#define CREATE_TRACE_POINTS
50#include "trace.h"
043405e1 51
24f1e32c 52#include <asm/debugreg.h>
d825ed0a 53#include <asm/msr.h>
a5f61300 54#include <asm/desc.h>
0bed3b56 55#include <asm/mtrr.h>
890ca9ae 56#include <asm/mce.h>
7cf30855 57#include <asm/i387.h>
98918833 58#include <asm/xcr.h>
1d5f066e 59#include <asm/pvclock.h>
217fc9cf 60#include <asm/div64.h>
043405e1 61
313a3dc7 62#define MAX_IO_MSRS 256
890ca9ae 63#define KVM_MAX_MCE_BANKS 32
5854dbca 64#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 65
0f65dd70
AK		 66#define emul_to_vcpu(ctxt) \
67 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
68
50a37eb4
JR		 69/* EFER defaults:
70 * - enable syscall per default because its emulated by KVM
71 * - enable LME and LMA per default on 64 bit KVM
72 */
73#ifdef CONFIG_X86_64
1260edbe
LJ		 74static
75u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 76#else
1260edbe 77static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 78#endif
313a3dc7 79
ba1389b7
AK		 80#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
81#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 82
cb142eb7 83static void update_cr8_intercept(struct kvm_vcpu *vcpu);
674eea0f
AK		 84static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
85 struct kvm_cpuid_entry2 __user *entries);
86
97896d04 87struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 88EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 89
ed85c068
AP		 90int ignore_msrs = 0;
91module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
92
92a1f12d
JR		 93bool kvm_has_tsc_control;
94EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
95u32 kvm_max_guest_tsc_khz;
96EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
97
18863bdd
AK		 98#define KVM_NR_SHARED_MSRS 16
99
100struct kvm_shared_msrs_global {
101 int nr;
2bf78fa7 102 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 103};
104
105struct kvm_shared_msrs {
106 struct user_return_notifier urn;
107 bool registered;
2bf78fa7
SY		 108 struct kvm_shared_msr_values {
109 u64 host;
110 u64 curr;
111 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 112};
113
114static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
115static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
116
417bc304 117struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 118 { "pf_fixed", VCPU_STAT(pf_fixed) },
119 { "pf_guest", VCPU_STAT(pf_guest) },
120 { "tlb_flush", VCPU_STAT(tlb_flush) },
121 { "invlpg", VCPU_STAT(invlpg) },
122 { "exits", VCPU_STAT(exits) },
123 { "io_exits", VCPU_STAT(io_exits) },
124 { "mmio_exits", VCPU_STAT(mmio_exits) },
125 { "signal_exits", VCPU_STAT(signal_exits) },
126 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 127 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 128 { "halt_exits", VCPU_STAT(halt_exits) },
129 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 130 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 131 { "request_irq", VCPU_STAT(request_irq_exits) },
132 { "irq_exits", VCPU_STAT(irq_exits) },
133 { "host_state_reload", VCPU_STAT(host_state_reload) },
134 { "efer_reload", VCPU_STAT(efer_reload) },
135 { "fpu_reload", VCPU_STAT(fpu_reload) },
136 { "insn_emulation", VCPU_STAT(insn_emulation) },
137 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 138 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 139 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 140 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
141 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
142 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
143 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
144 { "mmu_flooded", VM_STAT(mmu_flooded) },
145 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 146 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 147 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 148 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 149 { "largepages", VM_STAT(lpages) },
417bc304
HB		 150 { NULL }
151};
152
2acf923e
DC		 153u64 __read_mostly host_xcr0;
154
d6aa1000
AK		 155int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
156
af585b92
GN		 157static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
158{
159 int i;
160 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
161 vcpu->arch.apf.gfns[i] = ~0;
162}
163
18863bdd
AK		 164static void kvm_on_user_return(struct user_return_notifier *urn)
165{
166 unsigned slot;
18863bdd
AK		 167 struct kvm_shared_msrs *locals
168 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 169 struct kvm_shared_msr_values *values;
18863bdd
AK		 170
171 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 172 values = &locals->values[slot];
173 if (values->host != values->curr) {
174 wrmsrl(shared_msrs_global.msrs[slot], values->host);
175 values->curr = values->host;
18863bdd
AK		 176 }
177 }
178 locals->registered = false;
179 user_return_notifier_unregister(urn);
180}
181
2bf78fa7 182static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 183{
2bf78fa7 184 struct kvm_shared_msrs *smsr;
18863bdd
AK		 185 u64 value;
186
2bf78fa7
SY		 187 smsr = &__get_cpu_var(shared_msrs);
188 /* only read, and nobody should modify it at this time,
189 * so don't need lock */
190 if (slot >= shared_msrs_global.nr) {
191 printk(KERN_ERR "kvm: invalid MSR slot!");
192 return;
193 }
194 rdmsrl_safe(msr, &value);
195 smsr->values[slot].host = value;
196 smsr->values[slot].curr = value;
197}
198
199void kvm_define_shared_msr(unsigned slot, u32 msr)
200{
18863bdd
AK		 201 if (slot >= shared_msrs_global.nr)
202 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 203 shared_msrs_global.msrs[slot] = msr;
204 /* we need ensured the shared_msr_global have been updated */
205 smp_wmb();
18863bdd
AK		 206}
207EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
208
209static void kvm_shared_msr_cpu_online(void)
210{
211 unsigned i;
18863bdd
AK		 212
213 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 214 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 215}
216
d5696725 217void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 218{
219 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
220
2bf78fa7 221 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 222 return;
2bf78fa7
SY		 223 smsr->values[slot].curr = value;
224 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 225 if (!smsr->registered) {
226 smsr->urn.on_user_return = kvm_on_user_return;
227 user_return_notifier_register(&smsr->urn);
228 smsr->registered = true;
229 }
230}
231EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
232
3548bab5
AK		 233static void drop_user_return_notifiers(void *ignore)
234{
235 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
236
237 if (smsr->registered)
238 kvm_on_user_return(&smsr->urn);
239}
240
6866b83e
CO		 241u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
242{
243 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 244 return vcpu->arch.apic_base;
6866b83e 245 else
ad312c7c 246 return vcpu->arch.apic_base;
6866b83e
CO		 247}
248EXPORT_SYMBOL_GPL(kvm_get_apic_base);
249
250void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
251{
252 /* TODO: reserve bits check */
253 if (irqchip_in_kernel(vcpu->kvm))
254 kvm_lapic_set_base(vcpu, data);
255 else
ad312c7c 256 vcpu->arch.apic_base = data;
6866b83e
CO		 257}
258EXPORT_SYMBOL_GPL(kvm_set_apic_base);
259
3fd28fce
ED		 260#define EXCPT_BENIGN 0
261#define EXCPT_CONTRIBUTORY 1
262#define EXCPT_PF 2
263
264static int exception_class(int vector)
265{
266 switch (vector) {
267 case PF_VECTOR:
268 return EXCPT_PF;
269 case DE_VECTOR:
270 case TS_VECTOR:
271 case NP_VECTOR:
272 case SS_VECTOR:
273 case GP_VECTOR:
274 return EXCPT_CONTRIBUTORY;
275 default:
276 break;
277 }
278 return EXCPT_BENIGN;
279}
280
281static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 282 unsigned nr, bool has_error, u32 error_code,
283 bool reinject)
3fd28fce
ED		 284{
285 u32 prev_nr;
286 int class1, class2;
287
3842d135
AK		 288 kvm_make_request(KVM_REQ_EVENT, vcpu);
289
3fd28fce
ED		 290 if (!vcpu->arch.exception.pending) {
291 queue:
292 vcpu->arch.exception.pending = true;
293 vcpu->arch.exception.has_error_code = has_error;
294 vcpu->arch.exception.nr = nr;
295 vcpu->arch.exception.error_code = error_code;
3f0fd292 296 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 297 return;
298 }
299
300 /* to check exception */
301 prev_nr = vcpu->arch.exception.nr;
302 if (prev_nr == DF_VECTOR) {
303 /* triple fault -> shutdown */
a8eeb04a 304 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 305 return;
306 }
307 class1 = exception_class(prev_nr);
308 class2 = exception_class(nr);
309 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
310 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
311 /* generate double fault per SDM Table 5-5 */
312 vcpu->arch.exception.pending = true;
313 vcpu->arch.exception.has_error_code = true;
314 vcpu->arch.exception.nr = DF_VECTOR;
315 vcpu->arch.exception.error_code = 0;
316 } else
317 /* replace previous exception with a new one in a hope
318 that instruction re-execution will regenerate lost
319 exception */
320 goto queue;
321}
322
298101da
AK		 323void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
324{
ce7ddec4 325 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 326}
327EXPORT_SYMBOL_GPL(kvm_queue_exception);
328
ce7ddec4
JR		 329void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
330{
331 kvm_multiple_exception(vcpu, nr, false, 0, true);
332}
333EXPORT_SYMBOL_GPL(kvm_requeue_exception);
334
db8fcefa 335void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 336{
db8fcefa
AP		 337 if (err)
338 kvm_inject_gp(vcpu, 0);
339 else
340 kvm_x86_ops->skip_emulated_instruction(vcpu);
341}
342EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 343
6389ee94 344void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 345{
346 ++vcpu->stat.pf_guest;
6389ee94
AK		 347 vcpu->arch.cr2 = fault->address;
348 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 349}
27d6c865 350EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 351
6389ee94 352void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 353{
6389ee94
AK		 354 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
355 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 356 else
6389ee94 357 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
d4f8cf66
JR		 358}
359
3419ffc8
SY		 360void kvm_inject_nmi(struct kvm_vcpu *vcpu)
361{
3842d135 362 kvm_make_request(KVM_REQ_EVENT, vcpu);
c761e586 363 vcpu->arch.nmi_pending = 1;
3419ffc8
SY		 364}
365EXPORT_SYMBOL_GPL(kvm_inject_nmi);
366
298101da
AK		 367void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
368{
ce7ddec4 369 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 370}
371EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
372
ce7ddec4
JR		 373void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
374{
375 kvm_multiple_exception(vcpu, nr, true, error_code, true);
376}
377EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
378
0a79b009
AK		 379/*
380 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
381 * a #GP and return false.
382 */
383bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 384{
0a79b009
AK		 385 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
386 return true;
387 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
388 return false;
298101da 389}
0a79b009 390EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 391
ec92fe44
JR		 392/*
393 * This function will be used to read from the physical memory of the currently
394 * running guest. The difference to kvm_read_guest_page is that this function
395 * can read from guest physical or from the guest's guest physical memory.
396 */
397int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
398 gfn_t ngfn, void *data, int offset, int len,
399 u32 access)
400{
401 gfn_t real_gfn;
402 gpa_t ngpa;
403
404 ngpa = gfn_to_gpa(ngfn);
405 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
406 if (real_gfn == UNMAPPED_GVA)
407 return -EFAULT;
408
409 real_gfn = gpa_to_gfn(real_gfn);
410
411 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
412}
413EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
414
3d06b8bf
JR		 415int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
416 void *data, int offset, int len, u32 access)
417{
418 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
419 data, offset, len, access);
420}
421
a03490ed
CO		 422/*
423 * Load the pae pdptrs. Return true is they are all valid.
424 */
ff03a073 425int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 426{
427 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
428 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
429 int i;
430 int ret;
ff03a073 431 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 432
ff03a073
JR		 433 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
434 offset * sizeof(u64), sizeof(pdpte),
435 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 436 if (ret < 0) {
437 ret = 0;
438 goto out;
439 }
440 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 441 if (is_present_gpte(pdpte[i]) &&
20c466b5 442 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 443 ret = 0;
444 goto out;
445 }
446 }
447 ret = 1;
448
ff03a073 449 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 450 __set_bit(VCPU_EXREG_PDPTR,
451 (unsigned long *)&vcpu->arch.regs_avail);
452 __set_bit(VCPU_EXREG_PDPTR,
453 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 454out:
a03490ed
CO		 455
456 return ret;
457}
cc4b6871 458EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 459
d835dfec
AK		 460static bool pdptrs_changed(struct kvm_vcpu *vcpu)
461{
ff03a073 462 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 463 bool changed = true;
3d06b8bf
JR		 464 int offset;
465 gfn_t gfn;
d835dfec
AK		 466 int r;
467
468 if (is_long_mode(vcpu) || !is_pae(vcpu))
469 return false;
470
6de4f3ad
AK		 471 if (!test_bit(VCPU_EXREG_PDPTR,
472 (unsigned long *)&vcpu->arch.regs_avail))
473 return true;
474
9f8fe504
AK		 475 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
476 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 477 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
478 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 479 if (r < 0)
480 goto out;
ff03a073 481 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 482out:
d835dfec
AK		 483
484 return changed;
485}
486
49a9b07e 487int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 488{
aad82703
SY		 489 unsigned long old_cr0 = kvm_read_cr0(vcpu);
490 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
491 X86_CR0_CD | X86_CR0_NW;
492
f9a48e6a
AK		 493 cr0 |= X86_CR0_ET;
494
ab344828 495#ifdef CONFIG_X86_64
0f12244f
GN		 496 if (cr0 & 0xffffffff00000000UL)
497 return 1;
ab344828
GN		 498#endif
499
500 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 501
0f12244f
GN		 502 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
503 return 1;
a03490ed 504
0f12244f
GN		 505 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
506 return 1;
a03490ed
CO		 507
508 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
509#ifdef CONFIG_X86_64
f6801dff 510 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 511 int cs_db, cs_l;
512
0f12244f
GN		 513 if (!is_pae(vcpu))
514 return 1;
a03490ed 515 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 516 if (cs_l)
517 return 1;
a03490ed
CO		 518 } else
519#endif
ff03a073 520 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 521 kvm_read_cr3(vcpu)))
0f12244f 522 return 1;
a03490ed
CO		 523 }
524
525 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 526
d170c419 527 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 528 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 529 kvm_async_pf_hash_reset(vcpu);
530 }
e5f3f027 531
aad82703
SY		 532 if ((cr0 ^ old_cr0) & update_bits)
533 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 534 return 0;
535}
2d3ad1f4 536EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 537
2d3ad1f4 538void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 539{
49a9b07e 540 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 541}
2d3ad1f4 542EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 543
2acf923e
DC		 544int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
545{
546 u64 xcr0;
547
548 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
549 if (index != XCR_XFEATURE_ENABLED_MASK)
550 return 1;
551 xcr0 = xcr;
552 if (kvm_x86_ops->get_cpl(vcpu) != 0)
553 return 1;
554 if (!(xcr0 & XSTATE_FP))
555 return 1;
556 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
557 return 1;
558 if (xcr0 & ~host_xcr0)
559 return 1;
560 vcpu->arch.xcr0 = xcr0;
561 vcpu->guest_xcr0_loaded = 0;
562 return 0;
563}
564
565int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
566{
567 if (__kvm_set_xcr(vcpu, index, xcr)) {
568 kvm_inject_gp(vcpu, 0);
569 return 1;
570 }
571 return 0;
572}
573EXPORT_SYMBOL_GPL(kvm_set_xcr);
574
575static bool guest_cpuid_has_xsave(struct kvm_vcpu *vcpu)
576{
577 struct kvm_cpuid_entry2 *best;
578
579 best = kvm_find_cpuid_entry(vcpu, 1, 0);
580 return best && (best->ecx & bit(X86_FEATURE_XSAVE));
581}
582
c68b734f
YW		 583static bool guest_cpuid_has_smep(struct kvm_vcpu *vcpu)
584{
585 struct kvm_cpuid_entry2 *best;
586
587 best = kvm_find_cpuid_entry(vcpu, 7, 0);
588 return best && (best->ebx & bit(X86_FEATURE_SMEP));
589}
590
2acf923e
DC		 591static void update_cpuid(struct kvm_vcpu *vcpu)
592{
593 struct kvm_cpuid_entry2 *best;
594
595 best = kvm_find_cpuid_entry(vcpu, 1, 0);
596 if (!best)
597 return;
598
599 /* Update OSXSAVE bit */
600 if (cpu_has_xsave && best->function == 0x1) {
601 best->ecx &= ~(bit(X86_FEATURE_OSXSAVE));
602 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE))
603 best->ecx |= bit(X86_FEATURE_OSXSAVE);
604 }
605}
606
a83b29c6 607int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 608{
fc78f519 609 unsigned long old_cr4 = kvm_read_cr4(vcpu);
c68b734f
YW		 610 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
611 X86_CR4_PAE | X86_CR4_SMEP;
0f12244f
GN		 612 if (cr4 & CR4_RESERVED_BITS)
613 return 1;
a03490ed 614
2acf923e
DC		 615 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
616 return 1;
617
c68b734f
YW		 618 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
619 return 1;
620
a03490ed 621 if (is_long_mode(vcpu)) {
0f12244f
GN		 622 if (!(cr4 & X86_CR4_PAE))
623 return 1;
a2edf57f
AK		 624 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
625 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 626 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
627 kvm_read_cr3(vcpu)))
0f12244f
GN		 628 return 1;
629
5e1746d6 630 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 631 return 1;
a03490ed 632
aad82703
SY		 633 if ((cr4 ^ old_cr4) & pdptr_bits)
634 kvm_mmu_reset_context(vcpu);
0f12244f 635
2acf923e
DC		 636 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
637 update_cpuid(vcpu);
638
0f12244f
GN		 639 return 0;
640}
2d3ad1f4 641EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 642
2390218b 643int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 644{
9f8fe504 645 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 646 kvm_mmu_sync_roots(vcpu);
d835dfec 647 kvm_mmu_flush_tlb(vcpu);
0f12244f 648 return 0;
d835dfec
AK		 649 }
650
a03490ed 651 if (is_long_mode(vcpu)) {
0f12244f
GN		 652 if (cr3 & CR3_L_MODE_RESERVED_BITS)
653 return 1;
a03490ed
CO		 654 } else {
655 if (is_pae(vcpu)) {
0f12244f
GN		 656 if (cr3 & CR3_PAE_RESERVED_BITS)
657 return 1;
ff03a073
JR		 658 if (is_paging(vcpu) &&
659 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
0f12244f 660 return 1;
a03490ed
CO		 661 }
662 /*
663 * We don't check reserved bits in nonpae mode, because
664 * this isn't enforced, and VMware depends on this.
665 */
666 }
667
a03490ed
CO		 668 /*
669 * Does the new cr3 value map to physical memory? (Note, we
670 * catch an invalid cr3 even in real-mode, because it would
671 * cause trouble later on when we turn on paging anyway.)
672 *
673 * A real CPU would silently accept an invalid cr3 and would
674 * attempt to use it - with largely undefined (and often hard
675 * to debug) behavior on the guest side.
676 */
677 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
0f12244f
GN		 678 return 1;
679 vcpu->arch.cr3 = cr3;
aff48baa 680 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
0f12244f
GN		 681 vcpu->arch.mmu.new_cr3(vcpu);
682 return 0;
683}
2d3ad1f4 684EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 685
eea1cff9 686int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 687{
0f12244f
GN		 688 if (cr8 & CR8_RESERVED_BITS)
689 return 1;
a03490ed
CO		 690 if (irqchip_in_kernel(vcpu->kvm))
691 kvm_lapic_set_tpr(vcpu, cr8);
692 else
ad312c7c 693 vcpu->arch.cr8 = cr8;
0f12244f
GN		 694 return 0;
695}
2d3ad1f4 696EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 697
2d3ad1f4 698unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 699{
700 if (irqchip_in_kernel(vcpu->kvm))
701 return kvm_lapic_get_cr8(vcpu);
702 else
ad312c7c 703 return vcpu->arch.cr8;
a03490ed 704}
2d3ad1f4 705EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 706
338dbc97 707static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 708{
709 switch (dr) {
710 case 0 ... 3:
711 vcpu->arch.db[dr] = val;
712 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
713 vcpu->arch.eff_db[dr] = val;
714 break;
715 case 4:
338dbc97
GN		 716 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
717 return 1; /* #UD */
020df079
GN		 718 /* fall through */
719 case 6:
338dbc97
GN		 720 if (val & 0xffffffff00000000ULL)
721 return -1; /* #GP */
020df079
GN		 722 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
723 break;
724 case 5:
338dbc97
GN		 725 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
726 return 1; /* #UD */
020df079
GN		 727 /* fall through */
728 default: /* 7 */
338dbc97
GN		 729 if (val & 0xffffffff00000000ULL)
730 return -1; /* #GP */
020df079
GN		 731 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
732 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
733 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
734 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
735 }
736 break;
737 }
738
739 return 0;
740}
338dbc97
GN		 741
742int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
743{
744 int res;
745
746 res = __kvm_set_dr(vcpu, dr, val);
747 if (res > 0)
748 kvm_queue_exception(vcpu, UD_VECTOR);
749 else if (res < 0)
750 kvm_inject_gp(vcpu, 0);
751
752 return res;
753}
020df079
GN		 754EXPORT_SYMBOL_GPL(kvm_set_dr);
755
338dbc97 756static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 757{
758 switch (dr) {
759 case 0 ... 3:
760 *val = vcpu->arch.db[dr];
761 break;
762 case 4:
338dbc97 763 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 764 return 1;
020df079
GN		 765 /* fall through */
766 case 6:
767 *val = vcpu->arch.dr6;
768 break;
769 case 5:
338dbc97 770 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 771 return 1;
020df079
GN		 772 /* fall through */
773 default: /* 7 */
774 *val = vcpu->arch.dr7;
775 break;
776 }
777
778 return 0;
779}
338dbc97
GN		 780
781int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
782{
783 if (_kvm_get_dr(vcpu, dr, val)) {
784 kvm_queue_exception(vcpu, UD_VECTOR);
785 return 1;
786 }
787 return 0;
788}
020df079
GN		 789EXPORT_SYMBOL_GPL(kvm_get_dr);
790
043405e1
CO		 791/*
792 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
793 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
794 *
795 * This list is modified at module load time to reflect the
e3267cbb
GC		 796 * capabilities of the host cpu. This capabilities test skips MSRs that are
797 * kvm-specific. Those are put in the beginning of the list.
043405e1 798 */
e3267cbb 799
344d9588 800#define KVM_SAVE_MSRS_BEGIN 8
043405e1 801static u32 msrs_to_save[] = {
e3267cbb 802 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 803 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 804 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
344d9588 805 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN,
043405e1 806 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 807 MSR_STAR,
043405e1
CO		 808#ifdef CONFIG_X86_64
809 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
810#endif
e90aa41e 811 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 812};
813
814static unsigned num_msrs_to_save;
815
816static u32 emulated_msrs[] = {
817 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 818 MSR_IA32_MCG_STATUS,
819 MSR_IA32_MCG_CTL,
043405e1
CO		 820};
821
b69e8cae 822static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 823{
aad82703
SY		 824 u64 old_efer = vcpu->arch.efer;
825
b69e8cae
RJ		 826 if (efer & efer_reserved_bits)
827 return 1;
15c4a640
CO		 828
829 if (is_paging(vcpu)
b69e8cae
RJ		 830 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
831 return 1;
15c4a640 832
1b2fd70c
AG		 833 if (efer & EFER_FFXSR) {
834 struct kvm_cpuid_entry2 *feat;
835
836 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 837 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
838 return 1;
1b2fd70c
AG		 839 }
840
d8017474
AG		 841 if (efer & EFER_SVME) {
842 struct kvm_cpuid_entry2 *feat;
843
844 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 845 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
846 return 1;
d8017474
AG		 847 }
848
15c4a640 849 efer &= ~EFER_LMA;
f6801dff 850 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 851
a3d204e2
SY		 852 kvm_x86_ops->set_efer(vcpu, efer);
853
9645bb56 854 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
b69e8cae 855
aad82703
SY		 856 /* Update reserved bits */
857 if ((efer ^ old_efer) & EFER_NX)
858 kvm_mmu_reset_context(vcpu);
859
b69e8cae 860 return 0;
15c4a640
CO		 861}
862
f2b4b7dd
JR		 863void kvm_enable_efer_bits(u64 mask)
864{
865 efer_reserved_bits &= ~mask;
866}
867EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
868
869
15c4a640
CO		 870/*
871 * Writes msr value into into the appropriate "register".
872 * Returns 0 on success, non-0 otherwise.
873 * Assumes vcpu_load() was already called.
874 */
875int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
876{
877 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
878}
879
313a3dc7
CO		 880/*
881 * Adapt set_msr() to msr_io()'s calling convention
882 */
883static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
884{
885 return kvm_set_msr(vcpu, index, *data);
886}
887
18068523
GOC		 888static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
889{
9ed3c444
AK		 890 int version;
891 int r;
50d0a0f9 892 struct pvclock_wall_clock wc;
923de3cf 893 struct timespec boot;
18068523
GOC		 894
895 if (!wall_clock)
896 return;
897
9ed3c444
AK		 898 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
899 if (r)
900 return;
901
902 if (version & 1)
903 ++version; /* first time write, random junk */
904
905 ++version;
18068523 906
18068523
GOC		 907 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
908
50d0a0f9
GH		 909 /*
910 * The guest calculates current wall clock time by adding
34c238a1 911 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 912 * wall clock specified here. guest system time equals host
913 * system time for us, thus we must fill in host boot time here.
914 */
923de3cf 915 getboottime(&boot);
50d0a0f9
GH		 916
917 wc.sec = boot.tv_sec;
918 wc.nsec = boot.tv_nsec;
919 wc.version = version;
18068523
GOC		 920
921 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
922
923 version++;
924 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 925}
926
50d0a0f9
GH		 927static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
928{
929 uint32_t quotient, remainder;
930
931 /* Don't try to replace with do_div(), this one calculates
932 * "(dividend << 32) / divisor" */
933 __asm__ ( "divl %4"
934 : "=a" (quotient), "=d" (remainder)
935 : "0" (0), "1" (dividend), "r" (divisor) );
936 return quotient;
937}
938
5f4e3f88
ZA		 939static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
940 s8 *pshift, u32 *pmultiplier)
50d0a0f9 941{
5f4e3f88 942 uint64_t scaled64;
50d0a0f9
GH		 943 int32_t shift = 0;
944 uint64_t tps64;
945 uint32_t tps32;
946
5f4e3f88
ZA		 947 tps64 = base_khz * 1000LL;
948 scaled64 = scaled_khz * 1000LL;
50933623 949 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 950 tps64 >>= 1;
951 shift--;
952 }
953
954 tps32 = (uint32_t)tps64;
50933623
JK		 955 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
956 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 957 scaled64 >>= 1;
958 else
959 tps32 <<= 1;
50d0a0f9
GH		 960 shift++;
961 }
962
5f4e3f88
ZA		 963 *pshift = shift;
964 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 965
5f4e3f88
ZA		 966 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
967 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 968}
969
759379dd
ZA		 970static inline u64 get_kernel_ns(void)
971{
972 struct timespec ts;
973
974 WARN_ON(preemptible());
975 ktime_get_ts(&ts);
976 monotonic_to_bootbased(&ts);
977 return timespec_to_ns(&ts);
50d0a0f9
GH		 978}
979
c8076604 980static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 981unsigned long max_tsc_khz;
c8076604 982
8cfdc000
ZA		 983static inline int kvm_tsc_changes_freq(void)
984{
985 int cpu = get_cpu();
986 int ret = !boot_cpu_has(X86_FEATURE_CONSTANT_TSC) &&
987 cpufreq_quick_get(cpu) != 0;
988 put_cpu();
989 return ret;
990}
991
1e993611
JR		 992static u64 vcpu_tsc_khz(struct kvm_vcpu *vcpu)
993{
994 if (vcpu->arch.virtual_tsc_khz)
995 return vcpu->arch.virtual_tsc_khz;
996 else
997 return __this_cpu_read(cpu_tsc_khz);
998}
999
857e4099 1000static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
759379dd 1001{
217fc9cf
AK		 1002 u64 ret;
1003
759379dd
ZA		 1004 WARN_ON(preemptible());
1005 if (kvm_tsc_changes_freq())
1006 printk_once(KERN_WARNING
1007 "kvm: unreliable cycle conversion on adjustable rate TSC\n");
857e4099 1008 ret = nsec * vcpu_tsc_khz(vcpu);
217fc9cf
AK		 1009 do_div(ret, USEC_PER_SEC);
1010 return ret;
759379dd
ZA		 1011}
1012
1e993611 1013static void kvm_init_tsc_catchup(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
c285545f
ZA		 1014{
1015 /* Compute a scale to convert nanoseconds in TSC cycles */
1016 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
1e993611
JR		 1017 &vcpu->arch.tsc_catchup_shift,
1018 &vcpu->arch.tsc_catchup_mult);
c285545f
ZA		 1019}
1020
1021static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1022{
1023 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.last_tsc_nsec,
1e993611
JR		 1024 vcpu->arch.tsc_catchup_mult,
1025 vcpu->arch.tsc_catchup_shift);
c285545f
ZA		 1026 tsc += vcpu->arch.last_tsc_write;
1027 return tsc;
1028}
1029
99e3e30a
ZA		 1030void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
1031{
1032 struct kvm *kvm = vcpu->kvm;
f38e098f 1033 u64 offset, ns, elapsed;
99e3e30a 1034 unsigned long flags;
46543ba4 1035 s64 sdiff;
99e3e30a 1036
038f8c11 1037 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1038 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1039 ns = get_kernel_ns();
f38e098f 1040 elapsed = ns - kvm->arch.last_tsc_nsec;
46543ba4
ZA		 1041 sdiff = data - kvm->arch.last_tsc_write;
1042 if (sdiff < 0)
1043 sdiff = -sdiff;
f38e098f
ZA		 1044
1045 /*
46543ba4 1046 * Special case: close write to TSC within 5 seconds of
f38e098f 1047 * another CPU is interpreted as an attempt to synchronize
0d2eb44f 1048 * The 5 seconds is to accommodate host load / swapping as
46543ba4 1049 * well as any reset of TSC during the boot process.
f38e098f
ZA		 1050 *
1051 * In that case, for a reliable TSC, we can match TSC offsets,
46543ba4 1052 * or make a best guest using elapsed value.
f38e098f 1053 */
857e4099 1054 if (sdiff < nsec_to_cycles(vcpu, 5ULL * NSEC_PER_SEC) &&
46543ba4 1055 elapsed < 5ULL * NSEC_PER_SEC) {
f38e098f
ZA		 1056 if (!check_tsc_unstable()) {
1057 offset = kvm->arch.last_tsc_offset;
1058 pr_debug("kvm: matched tsc offset for %llu\n", data);
1059 } else {
857e4099 1060 u64 delta = nsec_to_cycles(vcpu, elapsed);
759379dd
ZA		 1061 offset += delta;
1062 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f
ZA		 1063 }
1064 ns = kvm->arch.last_tsc_nsec;
1065 }
1066 kvm->arch.last_tsc_nsec = ns;
1067 kvm->arch.last_tsc_write = data;
1068 kvm->arch.last_tsc_offset = offset;
99e3e30a 1069 kvm_x86_ops->write_tsc_offset(vcpu, offset);
038f8c11 1070 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
99e3e30a
ZA		 1071
1072 /* Reset of TSC must disable overshoot protection below */
1073 vcpu->arch.hv_clock.tsc_timestamp = 0;
c285545f
ZA		 1074 vcpu->arch.last_tsc_write = data;
1075 vcpu->arch.last_tsc_nsec = ns;
99e3e30a
ZA		 1076}
1077EXPORT_SYMBOL_GPL(kvm_write_tsc);
1078
34c238a1 1079static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1080{
18068523
GOC		 1081 unsigned long flags;
1082 struct kvm_vcpu_arch *vcpu = &v->arch;
1083 void *shared_kaddr;
463656c0 1084 unsigned long this_tsc_khz;
1d5f066e
ZA		 1085 s64 kernel_ns, max_kernel_ns;
1086 u64 tsc_timestamp;
18068523 1087
18068523
GOC		 1088 /* Keep irq disabled to prevent changes to the clock */
1089 local_irq_save(flags);
1d5f066e 1090 kvm_get_msr(v, MSR_IA32_TSC, &tsc_timestamp);
759379dd 1091 kernel_ns = get_kernel_ns();
1e993611 1092 this_tsc_khz = vcpu_tsc_khz(v);
8cfdc000 1093 if (unlikely(this_tsc_khz == 0)) {
c285545f 1094 local_irq_restore(flags);
34c238a1 1095 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
8cfdc000
ZA		 1096 return 1;
1097 }
18068523 1098
c285545f
ZA		 1099 /*
1100 * We may have to catch up the TSC to match elapsed wall clock
1101 * time for two reasons, even if kvmclock is used.
1102 * 1) CPU could have been running below the maximum TSC rate
1103 * 2) Broken TSC compensation resets the base at each VCPU
1104 * entry to avoid unknown leaps of TSC even when running
1105 * again on the same CPU. This may cause apparent elapsed
1106 * time to disappear, and the guest to stand still or run
1107 * very slowly.
1108 */
1109 if (vcpu->tsc_catchup) {
1110 u64 tsc = compute_guest_tsc(v, kernel_ns);
1111 if (tsc > tsc_timestamp) {
1112 kvm_x86_ops->adjust_tsc_offset(v, tsc - tsc_timestamp);
1113 tsc_timestamp = tsc;
1114 }
50d0a0f9
GH		 1115 }
1116
18068523
GOC		 1117 local_irq_restore(flags);
1118
c285545f
ZA		 1119 if (!vcpu->time_page)
1120 return 0;
18068523 1121
1d5f066e
ZA		 1122 /*
1123 * Time as measured by the TSC may go backwards when resetting the base
1124 * tsc_timestamp. The reason for this is that the TSC resolution is
1125 * higher than the resolution of the other clock scales. Thus, many
1126 * possible measurments of the TSC correspond to one measurement of any
1127 * other clock, and so a spread of values is possible. This is not a
1128 * problem for the computation of the nanosecond clock; with TSC rates
1129 * around 1GHZ, there can only be a few cycles which correspond to one
1130 * nanosecond value, and any path through this code will inevitably
1131 * take longer than that. However, with the kernel_ns value itself,
1132 * the precision may be much lower, down to HZ granularity. If the
1133 * first sampling of TSC against kernel_ns ends in the low part of the
1134 * range, and the second in the high end of the range, we can get:
1135 *
1136 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1137 *
1138 * As the sampling errors potentially range in the thousands of cycles,
1139 * it is possible such a time value has already been observed by the
1140 * guest. To protect against this, we must compute the system time as
1141 * observed by the guest and ensure the new system time is greater.
1142 */
1143 max_kernel_ns = 0;
1144 if (vcpu->hv_clock.tsc_timestamp && vcpu->last_guest_tsc) {
1145 max_kernel_ns = vcpu->last_guest_tsc -
1146 vcpu->hv_clock.tsc_timestamp;
1147 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1148 vcpu->hv_clock.tsc_to_system_mul,
1149 vcpu->hv_clock.tsc_shift);
1150 max_kernel_ns += vcpu->last_kernel_ns;
1151 }
afbcf7ab 1152
e48672fa 1153 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1154 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1155 &vcpu->hv_clock.tsc_shift,
1156 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1157 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1158 }
1159
1d5f066e
ZA		 1160 if (max_kernel_ns > kernel_ns)
1161 kernel_ns = max_kernel_ns;
1162
8cfdc000 1163 /* With all the info we got, fill in the values */
1d5f066e 1164 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1165 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1d5f066e 1166 vcpu->last_kernel_ns = kernel_ns;
28e4639a 1167 vcpu->last_guest_tsc = tsc_timestamp;
371bcf64
GC		 1168 vcpu->hv_clock.flags = 0;
1169
18068523
GOC		 1170 /*
1171 * The interface expects us to write an even number signaling that the
1172 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1173 * state, we just increase by 2 at the end.
18068523 1174 */
50d0a0f9 1175 vcpu->hv_clock.version += 2;
18068523
GOC		 1176
1177 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
1178
1179 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 1180 sizeof(vcpu->hv_clock));
18068523
GOC		 1181
1182 kunmap_atomic(shared_kaddr, KM_USER0);
1183
1184 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
8cfdc000 1185 return 0;
c8076604
GH		 1186}
1187
9ba075a6
AK		 1188static bool msr_mtrr_valid(unsigned msr)
1189{
1190 switch (msr) {
1191 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1192 case MSR_MTRRfix64K_00000:
1193 case MSR_MTRRfix16K_80000:
1194 case MSR_MTRRfix16K_A0000:
1195 case MSR_MTRRfix4K_C0000:
1196 case MSR_MTRRfix4K_C8000:
1197 case MSR_MTRRfix4K_D0000:
1198 case MSR_MTRRfix4K_D8000:
1199 case MSR_MTRRfix4K_E0000:
1200 case MSR_MTRRfix4K_E8000:
1201 case MSR_MTRRfix4K_F0000:
1202 case MSR_MTRRfix4K_F8000:
1203 case MSR_MTRRdefType:
1204 case MSR_IA32_CR_PAT:
1205 return true;
1206 case 0x2f8:
1207 return true;
1208 }
1209 return false;
1210}
1211
d6289b93
MT		 1212static bool valid_pat_type(unsigned t)
1213{
1214 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1215}
1216
1217static bool valid_mtrr_type(unsigned t)
1218{
1219 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1220}
1221
1222static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1223{
1224 int i;
1225
1226 if (!msr_mtrr_valid(msr))
1227 return false;
1228
1229 if (msr == MSR_IA32_CR_PAT) {
1230 for (i = 0; i < 8; i++)
1231 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1232 return false;
1233 return true;
1234 } else if (msr == MSR_MTRRdefType) {
1235 if (data & ~0xcff)
1236 return false;
1237 return valid_mtrr_type(data & 0xff);
1238 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1239 for (i = 0; i < 8 ; i++)
1240 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1241 return false;
1242 return true;
1243 }
1244
1245 /* variable MTRRs */
1246 return valid_mtrr_type(data & 0xff);
1247}
1248
9ba075a6
AK		 1249static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1250{
0bed3b56
SY		 1251 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1252
d6289b93 1253 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1254 return 1;
1255
0bed3b56
SY		 1256 if (msr == MSR_MTRRdefType) {
1257 vcpu->arch.mtrr_state.def_type = data;
1258 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1259 } else if (msr == MSR_MTRRfix64K_00000)
1260 p[0] = data;
1261 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1262 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1263 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1264 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1265 else if (msr == MSR_IA32_CR_PAT)
1266 vcpu->arch.pat = data;
1267 else { /* Variable MTRRs */
1268 int idx, is_mtrr_mask;
1269 u64 *pt;
1270
1271 idx = (msr - 0x200) / 2;
1272 is_mtrr_mask = msr - 0x200 - 2 * idx;
1273 if (!is_mtrr_mask)
1274 pt =
1275 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1276 else
1277 pt =
1278 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1279 *pt = data;
1280 }
1281
1282 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1283 return 0;
1284}
15c4a640 1285
890ca9ae 1286static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1287{
890ca9ae
HY		 1288 u64 mcg_cap = vcpu->arch.mcg_cap;
1289 unsigned bank_num = mcg_cap & 0xff;
1290
15c4a640 1291 switch (msr) {
15c4a640 1292 case MSR_IA32_MCG_STATUS:
890ca9ae 1293 vcpu->arch.mcg_status = data;
15c4a640 1294 break;
c7ac679c 1295 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1296 if (!(mcg_cap & MCG_CTL_P))
1297 return 1;
1298 if (data != 0 && data != ~(u64)0)
1299 return -1;
1300 vcpu->arch.mcg_ctl = data;
1301 break;
1302 default:
1303 if (msr >= MSR_IA32_MC0_CTL &&
1304 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1305 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1306 /* only 0 or all 1s can be written to IA32_MCi_CTL
1307 * some Linux kernels though clear bit 10 in bank 4 to
1308 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1309 * this to avoid an uncatched #GP in the guest
1310 */
890ca9ae 1311 if ((offset & 0x3) == 0 &&
114be429 1312 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1313 return -1;
1314 vcpu->arch.mce_banks[offset] = data;
1315 break;
1316 }
1317 return 1;
1318 }
1319 return 0;
1320}
1321
ffde22ac
ES		 1322static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1323{
1324 struct kvm *kvm = vcpu->kvm;
1325 int lm = is_long_mode(vcpu);
1326 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1327 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1328 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1329 : kvm->arch.xen_hvm_config.blob_size_32;
1330 u32 page_num = data & ~PAGE_MASK;
1331 u64 page_addr = data & PAGE_MASK;
1332 u8 *page;
1333 int r;
1334
1335 r = -E2BIG;
1336 if (page_num >= blob_size)
1337 goto out;
1338 r = -ENOMEM;
1339 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
1340 if (!page)
1341 goto out;
1342 r = -EFAULT;
1343 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
1344 goto out_free;
1345 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1346 goto out_free;
1347 r = 0;
1348out_free:
1349 kfree(page);
1350out:
1351 return r;
1352}
1353
55cd8e5a
GN		 1354static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1355{
1356 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1357}
1358
1359static bool kvm_hv_msr_partition_wide(u32 msr)
1360{
1361 bool r = false;
1362 switch (msr) {
1363 case HV_X64_MSR_GUEST_OS_ID:
1364 case HV_X64_MSR_HYPERCALL:
1365 r = true;
1366 break;
1367 }
1368
1369 return r;
1370}
1371
1372static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1373{
1374 struct kvm *kvm = vcpu->kvm;
1375
1376 switch (msr) {
1377 case HV_X64_MSR_GUEST_OS_ID:
1378 kvm->arch.hv_guest_os_id = data;
1379 /* setting guest os id to zero disables hypercall page */
1380 if (!kvm->arch.hv_guest_os_id)
1381 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1382 break;
1383 case HV_X64_MSR_HYPERCALL: {
1384 u64 gfn;
1385 unsigned long addr;
1386 u8 instructions[4];
1387
1388 /* if guest os id is not set hypercall should remain disabled */
1389 if (!kvm->arch.hv_guest_os_id)
1390 break;
1391 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1392 kvm->arch.hv_hypercall = data;
1393 break;
1394 }
1395 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1396 addr = gfn_to_hva(kvm, gfn);
1397 if (kvm_is_error_hva(addr))
1398 return 1;
1399 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1400 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1401 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1402 return 1;
1403 kvm->arch.hv_hypercall = data;
1404 break;
1405 }
1406 default:
1407 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1408 "data 0x%llx\n", msr, data);
1409 return 1;
1410 }
1411 return 0;
1412}
1413
1414static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1415{
10388a07
GN		 1416 switch (msr) {
1417 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1418 unsigned long addr;
55cd8e5a 1419
10388a07
GN		 1420 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1421 vcpu->arch.hv_vapic = data;
1422 break;
1423 }
1424 addr = gfn_to_hva(vcpu->kvm, data >>
1425 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1426 if (kvm_is_error_hva(addr))
1427 return 1;
8b0cedff 1428 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 1429 return 1;
1430 vcpu->arch.hv_vapic = data;
1431 break;
1432 }
1433 case HV_X64_MSR_EOI:
1434 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1435 case HV_X64_MSR_ICR:
1436 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1437 case HV_X64_MSR_TPR:
1438 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1439 default:
1440 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1441 "data 0x%llx\n", msr, data);
1442 return 1;
1443 }
1444
1445 return 0;
55cd8e5a
GN		 1446}
1447
344d9588
GN		 1448static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1449{
1450 gpa_t gpa = data & ~0x3f;
1451
6adba527
GN		 1452 /* Bits 2:5 are resrved, Should be zero */
1453 if (data & 0x3c)
344d9588
GN		 1454 return 1;
1455
1456 vcpu->arch.apf.msr_val = data;
1457
1458 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1459 kvm_clear_async_pf_completion_queue(vcpu);
1460 kvm_async_pf_hash_reset(vcpu);
1461 return 0;
1462 }
1463
1464 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa))
1465 return 1;
1466
6adba527 1467 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1468 kvm_async_pf_wakeup_all(vcpu);
1469 return 0;
1470}
1471
12f9a48f
GC		 1472static void kvmclock_reset(struct kvm_vcpu *vcpu)
1473{
1474 if (vcpu->arch.time_page) {
1475 kvm_release_page_dirty(vcpu->arch.time_page);
1476 vcpu->arch.time_page = NULL;
1477 }
1478}
1479
15c4a640
CO		 1480int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1481{
1482 switch (msr) {
15c4a640 1483 case MSR_EFER:
b69e8cae 1484 return set_efer(vcpu, data);
8f1589d9
AP		 1485 case MSR_K7_HWCR:
1486 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1487 data &= ~(u64)0x100; /* ignore ignne emulation enable */
8f1589d9
AP		 1488 if (data != 0) {
1489 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1490 data);
1491 return 1;
1492 }
15c4a640 1493 break;
f7c6d140
AP		 1494 case MSR_FAM10H_MMIO_CONF_BASE:
1495 if (data != 0) {
1496 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1497 "0x%llx\n", data);
1498 return 1;
1499 }
15c4a640 1500 break;
c323c0e5 1501 case MSR_AMD64_NB_CFG:
c7ac679c 1502 break;
b5e2fec0
AG		 1503 case MSR_IA32_DEBUGCTLMSR:
1504 if (!data) {
1505 /* We support the non-activated case already */
1506 break;
1507 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1508 /* Values other than LBR and BTF are vendor-specific,
1509 thus reserved and should throw a #GP */
1510 return 1;
1511 }
1512 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1513 __func__, data);
1514 break;
15c4a640
CO		 1515 case MSR_IA32_UCODE_REV:
1516 case MSR_IA32_UCODE_WRITE:
61a6bd67 1517 case MSR_VM_HSAVE_PA:
6098ca93 1518 case MSR_AMD64_PATCH_LOADER:
15c4a640 1519 break;
9ba075a6
AK		 1520 case 0x200 ... 0x2ff:
1521 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1522 case MSR_IA32_APICBASE:
1523 kvm_set_apic_base(vcpu, data);
1524 break;
0105d1a5
GN		 1525 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1526 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 1527 case MSR_IA32_MISC_ENABLE:
ad312c7c 1528 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1529 break;
11c6bffa 1530 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1531 case MSR_KVM_WALL_CLOCK:
1532 vcpu->kvm->arch.wall_clock = data;
1533 kvm_write_wall_clock(vcpu->kvm, data);
1534 break;
11c6bffa 1535 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 1536 case MSR_KVM_SYSTEM_TIME: {
12f9a48f 1537 kvmclock_reset(vcpu);
18068523
GOC		 1538
1539 vcpu->arch.time = data;
c285545f 1540 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
18068523
GOC		 1541
1542 /* we verify if the enable bit is set... */
1543 if (!(data & 1))
1544 break;
1545
1546 /* ...but clean it before doing the actual write */
1547 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1548
18068523
GOC		 1549 vcpu->arch.time_page =
1550 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1551
1552 if (is_error_page(vcpu->arch.time_page)) {
1553 kvm_release_page_clean(vcpu->arch.time_page);
1554 vcpu->arch.time_page = NULL;
1555 }
18068523
GOC		 1556 break;
1557 }
344d9588
GN		 1558 case MSR_KVM_ASYNC_PF_EN:
1559 if (kvm_pv_enable_async_pf(vcpu, data))
1560 return 1;
1561 break;
890ca9ae
HY		 1562 case MSR_IA32_MCG_CTL:
1563 case MSR_IA32_MCG_STATUS:
1564 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1565 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1566
1567 /* Performance counters are not protected by a CPUID bit,
1568 * so we should check all of them in the generic path for the sake of
1569 * cross vendor migration.
1570 * Writing a zero into the event select MSRs disables them,
1571 * which we perfectly emulate ;-). Any other value should be at least
1572 * reported, some guests depend on them.
1573 */
1574 case MSR_P6_EVNTSEL0:
1575 case MSR_P6_EVNTSEL1:
1576 case MSR_K7_EVNTSEL0:
1577 case MSR_K7_EVNTSEL1:
1578 case MSR_K7_EVNTSEL2:
1579 case MSR_K7_EVNTSEL3:
1580 if (data != 0)
1581 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1582 "0x%x data 0x%llx\n", msr, data);
1583 break;
1584 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1585 * so we ignore writes to make it happy.
1586 */
1587 case MSR_P6_PERFCTR0:
1588 case MSR_P6_PERFCTR1:
1589 case MSR_K7_PERFCTR0:
1590 case MSR_K7_PERFCTR1:
1591 case MSR_K7_PERFCTR2:
1592 case MSR_K7_PERFCTR3:
1593 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1594 "0x%x data 0x%llx\n", msr, data);
1595 break;
84e0cefa
JS		 1596 case MSR_K7_CLK_CTL:
1597 /*
1598 * Ignore all writes to this no longer documented MSR.
1599 * Writes are only relevant for old K7 processors,
1600 * all pre-dating SVM, but a recommended workaround from
1601 * AMD for these chips. It is possible to speicify the
1602 * affected processor models on the command line, hence
1603 * the need to ignore the workaround.
1604 */
1605 break;
55cd8e5a
GN		 1606 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1607 if (kvm_hv_msr_partition_wide(msr)) {
1608 int r;
1609 mutex_lock(&vcpu->kvm->lock);
1610 r = set_msr_hyperv_pw(vcpu, msr, data);
1611 mutex_unlock(&vcpu->kvm->lock);
1612 return r;
1613 } else
1614 return set_msr_hyperv(vcpu, msr, data);
1615 break;
91c9c3ed 1616 case MSR_IA32_BBL_CR_CTL3:
1617 /* Drop writes to this legacy MSR -- see rdmsr
1618 * counterpart for further detail.
1619 */
1620 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
1621 break;
15c4a640 1622 default:
ffde22ac
ES		 1623 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1624 return xen_hvm_config(vcpu, data);
ed85c068
AP		 1625 if (!ignore_msrs) {
1626 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1627 msr, data);
1628 return 1;
1629 } else {
1630 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1631 msr, data);
1632 break;
1633 }
15c4a640
CO		 1634 }
1635 return 0;
1636}
1637EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1638
1639
1640/*
1641 * Reads an msr value (of 'msr_index') into 'pdata'.
1642 * Returns 0 on success, non-0 otherwise.
1643 * Assumes vcpu_load() was already called.
1644 */
1645int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1646{
1647 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1648}
1649
9ba075a6
AK		 1650static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1651{
0bed3b56
SY		 1652 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1653
9ba075a6
AK		 1654 if (!msr_mtrr_valid(msr))
1655 return 1;
1656
0bed3b56
SY		 1657 if (msr == MSR_MTRRdefType)
1658 *pdata = vcpu->arch.mtrr_state.def_type +
1659 (vcpu->arch.mtrr_state.enabled << 10);
1660 else if (msr == MSR_MTRRfix64K_00000)
1661 *pdata = p[0];
1662 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1663 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1664 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1665 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1666 else if (msr == MSR_IA32_CR_PAT)
1667 *pdata = vcpu->arch.pat;
1668 else { /* Variable MTRRs */
1669 int idx, is_mtrr_mask;
1670 u64 *pt;
1671
1672 idx = (msr - 0x200) / 2;
1673 is_mtrr_mask = msr - 0x200 - 2 * idx;
1674 if (!is_mtrr_mask)
1675 pt =
1676 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1677 else
1678 pt =
1679 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1680 *pdata = *pt;
1681 }
1682
9ba075a6
AK		 1683 return 0;
1684}
1685
890ca9ae 1686static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1687{
1688 u64 data;
890ca9ae
HY		 1689 u64 mcg_cap = vcpu->arch.mcg_cap;
1690 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1691
1692 switch (msr) {
15c4a640
CO		 1693 case MSR_IA32_P5_MC_ADDR:
1694 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1695 data = 0;
1696 break;
15c4a640 1697 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1698 data = vcpu->arch.mcg_cap;
1699 break;
c7ac679c 1700 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1701 if (!(mcg_cap & MCG_CTL_P))
1702 return 1;
1703 data = vcpu->arch.mcg_ctl;
1704 break;
1705 case MSR_IA32_MCG_STATUS:
1706 data = vcpu->arch.mcg_status;
1707 break;
1708 default:
1709 if (msr >= MSR_IA32_MC0_CTL &&
1710 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1711 u32 offset = msr - MSR_IA32_MC0_CTL;
1712 data = vcpu->arch.mce_banks[offset];
1713 break;
1714 }
1715 return 1;
1716 }
1717 *pdata = data;
1718 return 0;
1719}
1720
55cd8e5a
GN		 1721static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1722{
1723 u64 data = 0;
1724 struct kvm *kvm = vcpu->kvm;
1725
1726 switch (msr) {
1727 case HV_X64_MSR_GUEST_OS_ID:
1728 data = kvm->arch.hv_guest_os_id;
1729 break;
1730 case HV_X64_MSR_HYPERCALL:
1731 data = kvm->arch.hv_hypercall;
1732 break;
1733 default:
1734 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1735 return 1;
1736 }
1737
1738 *pdata = data;
1739 return 0;
1740}
1741
1742static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1743{
1744 u64 data = 0;
1745
1746 switch (msr) {
1747 case HV_X64_MSR_VP_INDEX: {
1748 int r;
1749 struct kvm_vcpu *v;
1750 kvm_for_each_vcpu(r, v, vcpu->kvm)
1751 if (v == vcpu)
1752 data = r;
1753 break;
1754 }
10388a07
GN		 1755 case HV_X64_MSR_EOI:
1756 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1757 case HV_X64_MSR_ICR:
1758 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1759 case HV_X64_MSR_TPR:
1760 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
55cd8e5a
GN		 1761 default:
1762 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1763 return 1;
1764 }
1765 *pdata = data;
1766 return 0;
1767}
1768
890ca9ae
HY		 1769int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1770{
1771 u64 data;
1772
1773 switch (msr) {
890ca9ae 1774 case MSR_IA32_PLATFORM_ID:
15c4a640 1775 case MSR_IA32_UCODE_REV:
15c4a640 1776 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1777 case MSR_IA32_DEBUGCTLMSR:
1778 case MSR_IA32_LASTBRANCHFROMIP:
1779 case MSR_IA32_LASTBRANCHTOIP:
1780 case MSR_IA32_LASTINTFROMIP:
1781 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1782 case MSR_K8_SYSCFG:
1783 case MSR_K7_HWCR:
61a6bd67 1784 case MSR_VM_HSAVE_PA:
1f3ee616
AS		 1785 case MSR_P6_PERFCTR0:
1786 case MSR_P6_PERFCTR1:
7fe29e0f
AS		 1787 case MSR_P6_EVNTSEL0:
1788 case MSR_P6_EVNTSEL1:
9e699624 1789 case MSR_K7_EVNTSEL0:
1f3ee616 1790 case MSR_K7_PERFCTR0:
1fdbd48c 1791 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1792 case MSR_AMD64_NB_CFG:
f7c6d140 1793 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1794 data = 0;
1795 break;
9ba075a6
AK		 1796 case MSR_MTRRcap:
1797 data = 0x500 | KVM_NR_VAR_MTRR;
1798 break;
1799 case 0x200 ... 0x2ff:
1800 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1801 case 0xcd: /* fsb frequency */
1802 data = 3;
1803 break;
7b914098
JS		 1804 /*
1805 * MSR_EBC_FREQUENCY_ID
1806 * Conservative value valid for even the basic CPU models.
1807 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
1808 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
1809 * and 266MHz for model 3, or 4. Set Core Clock
1810 * Frequency to System Bus Frequency Ratio to 1 (bits
1811 * 31:24) even though these are only valid for CPU
1812 * models > 2, however guests may end up dividing or
1813 * multiplying by zero otherwise.
1814 */
1815 case MSR_EBC_FREQUENCY_ID:
1816 data = 1 << 24;
1817 break;
15c4a640
CO		 1818 case MSR_IA32_APICBASE:
1819 data = kvm_get_apic_base(vcpu);
1820 break;
0105d1a5
GN		 1821 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1822 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1823 break;
15c4a640 1824 case MSR_IA32_MISC_ENABLE:
ad312c7c 1825 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1826 break;
847f0ad8
AG		 1827 case MSR_IA32_PERF_STATUS:
1828 /* TSC increment by tick */
1829 data = 1000ULL;
1830 /* CPU multiplier */
1831 data |= (((uint64_t)4ULL) << 40);
1832 break;
15c4a640 1833 case MSR_EFER:
f6801dff 1834 data = vcpu->arch.efer;
15c4a640 1835 break;
18068523 1836 case MSR_KVM_WALL_CLOCK:
11c6bffa 1837 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1838 data = vcpu->kvm->arch.wall_clock;
1839 break;
1840 case MSR_KVM_SYSTEM_TIME:
11c6bffa 1841 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1842 data = vcpu->arch.time;
1843 break;
344d9588
GN		 1844 case MSR_KVM_ASYNC_PF_EN:
1845 data = vcpu->arch.apf.msr_val;
1846 break;
890ca9ae
HY		 1847 case MSR_IA32_P5_MC_ADDR:
1848 case MSR_IA32_P5_MC_TYPE:
1849 case MSR_IA32_MCG_CAP:
1850 case MSR_IA32_MCG_CTL:
1851 case MSR_IA32_MCG_STATUS:
1852 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1853 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 1854 case MSR_K7_CLK_CTL:
1855 /*
1856 * Provide expected ramp-up count for K7. All other
1857 * are set to zero, indicating minimum divisors for
1858 * every field.
1859 *
1860 * This prevents guest kernels on AMD host with CPU
1861 * type 6, model 8 and higher from exploding due to
1862 * the rdmsr failing.
1863 */
1864 data = 0x20000000;
1865 break;
55cd8e5a
GN		 1866 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1867 if (kvm_hv_msr_partition_wide(msr)) {
1868 int r;
1869 mutex_lock(&vcpu->kvm->lock);
1870 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1871 mutex_unlock(&vcpu->kvm->lock);
1872 return r;
1873 } else
1874 return get_msr_hyperv(vcpu, msr, pdata);
1875 break;
91c9c3ed 1876 case MSR_IA32_BBL_CR_CTL3:
1877 /* This legacy MSR exists but isn't fully documented in current
1878 * silicon. It is however accessed by winxp in very narrow
1879 * scenarios where it sets bit #19, itself documented as
1880 * a "reserved" bit. Best effort attempt to source coherent
1881 * read data here should the balance of the register be
1882 * interpreted by the guest:
1883 *
1884 * L2 cache control register 3: 64GB range, 256KB size,
1885 * enabled, latency 0x1, configured
1886 */
1887 data = 0xbe702111;
1888 break;
15c4a640 1889 default:
ed85c068
AP		 1890 if (!ignore_msrs) {
1891 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1892 return 1;
1893 } else {
1894 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1895 data = 0;
1896 }
1897 break;
15c4a640
CO		 1898 }
1899 *pdata = data;
1900 return 0;
1901}
1902EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1903
313a3dc7
CO		 1904/*
1905 * Read or write a bunch of msrs. All parameters are kernel addresses.
1906 *
1907 * @return number of msrs set successfully.
1908 */
1909static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1910 struct kvm_msr_entry *entries,
1911 int (*do_msr)(struct kvm_vcpu *vcpu,
1912 unsigned index, u64 *data))
1913{
f656ce01 1914 int i, idx;
313a3dc7 1915
f656ce01 1916 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 1917 for (i = 0; i < msrs->nmsrs; ++i)
1918 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1919 break;
f656ce01 1920 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 1921
313a3dc7
CO		 1922 return i;
1923}
1924
1925/*
1926 * Read or write a bunch of msrs. Parameters are user addresses.
1927 *
1928 * @return number of msrs set successfully.
1929 */
1930static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1931 int (*do_msr)(struct kvm_vcpu *vcpu,
1932 unsigned index, u64 *data),
1933 int writeback)
1934{
1935 struct kvm_msrs msrs;
1936 struct kvm_msr_entry *entries;
1937 int r, n;
1938 unsigned size;
1939
1940 r = -EFAULT;
1941 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1942 goto out;
1943
1944 r = -E2BIG;
1945 if (msrs.nmsrs >= MAX_IO_MSRS)
1946 goto out;
1947
1948 r = -ENOMEM;
1949 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
7a73c028 1950 entries = kmalloc(size, GFP_KERNEL);
313a3dc7
CO		 1951 if (!entries)
1952 goto out;
1953
1954 r = -EFAULT;
1955 if (copy_from_user(entries, user_msrs->entries, size))
1956 goto out_free;
1957
1958 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1959 if (r < 0)
1960 goto out_free;
1961
1962 r = -EFAULT;
1963 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1964 goto out_free;
1965
1966 r = n;
1967
1968out_free:
7a73c028 1969 kfree(entries);
313a3dc7
CO		 1970out:
1971 return r;
1972}
1973
018d00d2
ZX		 1974int kvm_dev_ioctl_check_extension(long ext)
1975{
1976 int r;
1977
1978 switch (ext) {
1979 case KVM_CAP_IRQCHIP:
1980 case KVM_CAP_HLT:
1981 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1982 case KVM_CAP_SET_TSS_ADDR:
07716717 1983 case KVM_CAP_EXT_CPUID:
c8076604 1984 case KVM_CAP_CLOCKSOURCE:
7837699f 1985 case KVM_CAP_PIT:
a28e4f5a 1986 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1987 case KVM_CAP_MP_STATE:
ed848624 1988 case KVM_CAP_SYNC_MMU:
a355c85c 1989 case KVM_CAP_USER_NMI:
52d939a0 1990 case KVM_CAP_REINJECT_CONTROL:
4925663a 1991 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1992 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1993 case KVM_CAP_IRQFD:
d34e6b17 1994 case KVM_CAP_IOEVENTFD:
c5ff41ce 1995 case KVM_CAP_PIT2:
e9f42757 1996 case KVM_CAP_PIT_STATE2:
b927a3ce 1997 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 1998 case KVM_CAP_XEN_HVM:
afbcf7ab 1999 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2000 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2001 case KVM_CAP_HYPERV:
10388a07 2002 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2003 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2004 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2005 case KVM_CAP_DEBUGREGS:
d2be1651 2006 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2007 case KVM_CAP_XSAVE:
344d9588 2008 case KVM_CAP_ASYNC_PF:
92a1f12d 2009 case KVM_CAP_GET_TSC_KHZ:
018d00d2
ZX		 2010 r = 1;
2011 break;
542472b5
LV		 2012 case KVM_CAP_COALESCED_MMIO:
2013 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2014 break;
774ead3a
AK		 2015 case KVM_CAP_VAPIC:
2016 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2017 break;
f725230a
AK		 2018 case KVM_CAP_NR_VCPUS:
2019 r = KVM_MAX_VCPUS;
2020 break;
a988b910
AK		 2021 case KVM_CAP_NR_MEMSLOTS:
2022 r = KVM_MEMORY_SLOTS;
2023 break;
a68a6a72
MT		 2024 case KVM_CAP_PV_MMU: /* obsolete */
2025 r = 0;
2f333bcb 2026 break;
62c476c7 2027 case KVM_CAP_IOMMU:
19de40a8 2028 r = iommu_found();
62c476c7 2029 break;
890ca9ae
HY		 2030 case KVM_CAP_MCE:
2031 r = KVM_MAX_MCE_BANKS;
2032 break;
2d5b5a66
SY		 2033 case KVM_CAP_XCRS:
2034 r = cpu_has_xsave;
2035 break;
92a1f12d
JR		 2036 case KVM_CAP_TSC_CONTROL:
2037 r = kvm_has_tsc_control;
2038 break;
018d00d2
ZX		 2039 default:
2040 r = 0;
2041 break;
2042 }
2043 return r;
2044
2045}
2046
043405e1
CO		 2047long kvm_arch_dev_ioctl(struct file *filp,
2048 unsigned int ioctl, unsigned long arg)
2049{
2050 void __user *argp = (void __user *)arg;
2051 long r;
2052
2053 switch (ioctl) {
2054 case KVM_GET_MSR_INDEX_LIST: {
2055 struct kvm_msr_list __user *user_msr_list = argp;
2056 struct kvm_msr_list msr_list;
2057 unsigned n;
2058
2059 r = -EFAULT;
2060 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2061 goto out;
2062 n = msr_list.nmsrs;
2063 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2064 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2065 goto out;
2066 r = -E2BIG;
e125e7b6 2067 if (n < msr_list.nmsrs)
043405e1
CO		 2068 goto out;
2069 r = -EFAULT;
2070 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2071 num_msrs_to_save * sizeof(u32)))
2072 goto out;
e125e7b6 2073 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2074 &emulated_msrs,
2075 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2076 goto out;
2077 r = 0;
2078 break;
2079 }
674eea0f
AK		 2080 case KVM_GET_SUPPORTED_CPUID: {
2081 struct kvm_cpuid2 __user *cpuid_arg = argp;
2082 struct kvm_cpuid2 cpuid;
2083
2084 r = -EFAULT;
2085 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2086 goto out;
2087 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 2088 cpuid_arg->entries);
674eea0f
AK		 2089 if (r)
2090 goto out;
2091
2092 r = -EFAULT;
2093 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2094 goto out;
2095 r = 0;
2096 break;
2097 }
890ca9ae
HY		 2098 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2099 u64 mce_cap;
2100
2101 mce_cap = KVM_MCE_CAP_SUPPORTED;
2102 r = -EFAULT;
2103 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2104 goto out;
2105 r = 0;
2106 break;
2107 }
043405e1
CO		 2108 default:
2109 r = -EINVAL;
2110 }
2111out:
2112 return r;
2113}
2114
f5f48ee1
SY		 2115static void wbinvd_ipi(void *garbage)
2116{
2117 wbinvd();
2118}
2119
2120static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2121{
2122 return vcpu->kvm->arch.iommu_domain &&
2123 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2124}
2125
313a3dc7
CO		 2126void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2127{
f5f48ee1
SY		 2128 /* Address WBINVD may be executed by guest */
2129 if (need_emulate_wbinvd(vcpu)) {
2130 if (kvm_x86_ops->has_wbinvd_exit())
2131 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2132 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2133 smp_call_function_single(vcpu->cpu,
2134 wbinvd_ipi, NULL, 1);
2135 }
2136
313a3dc7 2137 kvm_x86_ops->vcpu_load(vcpu, cpu);
48434c20 2138 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
e48672fa 2139 /* Make sure TSC doesn't go backwards */
8f6055cb
JR		 2140 s64 tsc_delta;
2141 u64 tsc;
2142
2143 kvm_get_msr(vcpu, MSR_IA32_TSC, &tsc);
2144 tsc_delta = !vcpu->arch.last_guest_tsc ? 0 :
2145 tsc - vcpu->arch.last_guest_tsc;
2146
e48672fa
ZA		 2147 if (tsc_delta < 0)
2148 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2149 if (check_tsc_unstable()) {
e48672fa 2150 kvm_x86_ops->adjust_tsc_offset(vcpu, -tsc_delta);
c285545f 2151 vcpu->arch.tsc_catchup = 1;
c285545f 2152 }
1aa8ceef 2153 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2154 if (vcpu->cpu != cpu)
2155 kvm_migrate_timers(vcpu);
e48672fa 2156 vcpu->cpu = cpu;
6b7d7e76 2157 }
313a3dc7
CO		 2158}
2159
2160void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2161{
02daab21 2162 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2163 kvm_put_guest_fpu(vcpu);
7c4c0f4f 2164 kvm_get_msr(vcpu, MSR_IA32_TSC, &vcpu->arch.last_guest_tsc);
313a3dc7
CO		 2165}
2166
07716717 2167static int is_efer_nx(void)
313a3dc7 2168{
e286e86e 2169 unsigned long long efer = 0;
313a3dc7 2170
e286e86e 2171 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 2172 return efer & EFER_NX;
2173}
2174
2175static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
2176{
2177 int i;
2178 struct kvm_cpuid_entry2 *e, *entry;
2179
313a3dc7 2180 entry = NULL;
ad312c7c
ZX		 2181 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
2182 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 2183 if (e->function == 0x80000001) {
2184 entry = e;
2185 break;
2186 }
2187 }
07716717 2188 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 2189 entry->edx &= ~(1 << 20);
2190 printk(KERN_INFO "kvm: guest NX capability removed\n");
2191 }
2192}
2193
07716717 2194/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 2195static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
2196 struct kvm_cpuid *cpuid,
2197 struct kvm_cpuid_entry __user *entries)
07716717
DK		 2198{
2199 int r, i;
2200 struct kvm_cpuid_entry *cpuid_entries;
2201
2202 r = -E2BIG;
2203 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2204 goto out;
2205 r = -ENOMEM;
2206 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
2207 if (!cpuid_entries)
2208 goto out;
2209 r = -EFAULT;
2210 if (copy_from_user(cpuid_entries, entries,
2211 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
2212 goto out_free;
2213 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 2214 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
2215 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
2216 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
2217 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
2218 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
2219 vcpu->arch.cpuid_entries[i].index = 0;
2220 vcpu->arch.cpuid_entries[i].flags = 0;
2221 vcpu->arch.cpuid_entries[i].padding[0] = 0;
2222 vcpu->arch.cpuid_entries[i].padding[1] = 0;
2223 vcpu->arch.cpuid_entries[i].padding[2] = 0;
2224 }
2225 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 2226 cpuid_fix_nx_cap(vcpu);
2227 r = 0;
fc61b800 2228 kvm_apic_set_version(vcpu);
0e851880 2229 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 2230 update_cpuid(vcpu);
07716717
DK		 2231
2232out_free:
2233 vfree(cpuid_entries);
2234out:
2235 return r;
2236}
2237
2238static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 2239 struct kvm_cpuid2 *cpuid,
2240 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 2241{
2242 int r;
2243
2244 r = -E2BIG;
2245 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2246 goto out;
2247 r = -EFAULT;
ad312c7c 2248 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 2249 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 2250 goto out;
ad312c7c 2251 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 2252 kvm_apic_set_version(vcpu);
0e851880 2253 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 2254 update_cpuid(vcpu);
313a3dc7
CO		 2255 return 0;
2256
2257out:
2258 return r;
2259}
2260
07716717 2261static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 2262 struct kvm_cpuid2 *cpuid,
2263 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2264{
2265 int r;
2266
2267 r = -E2BIG;
ad312c7c 2268 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 2269 goto out;
2270 r = -EFAULT;
ad312c7c 2271 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 2272 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2273 goto out;
2274 return 0;
2275
2276out:
ad312c7c 2277 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 2278 return r;
2279}
2280
945ee35e
AK		 2281static void cpuid_mask(u32 *word, int wordnum)
2282{
2283 *word &= boot_cpu_data.x86_capability[wordnum];
2284}
2285
07716717 2286static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 2287 u32 index)
07716717
DK		 2288{
2289 entry->function = function;
2290 entry->index = index;
2291 cpuid_count(entry->function, entry->index,
19355475 2292 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 2293 entry->flags = 0;
2294}
2295
24c82e57
AK		 2296static bool supported_xcr0_bit(unsigned bit)
2297{
2298 u64 mask = ((u64)1 << bit);
2299
2300 return mask & (XSTATE_FP | XSTATE_SSE | XSTATE_YMM) & host_xcr0;
2301}
2302
7faa4ee1
AK		 2303#define F(x) bit(X86_FEATURE_##x)
2304
07716717
DK		 2305static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
2306 u32 index, int *nent, int maxnent)
2307{
7faa4ee1 2308 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 2309#ifdef CONFIG_X86_64
17cc3935
SY		 2310 unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
2311 ? F(GBPAGES) : 0;
7faa4ee1
AK		 2312 unsigned f_lm = F(LM);
2313#else
17cc3935 2314 unsigned f_gbpages = 0;
7faa4ee1 2315 unsigned f_lm = 0;
07716717 2316#endif
4e47c7a6 2317 unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
7faa4ee1
AK		 2318
2319 /* cpuid 1.edx */
2320 const u32 kvm_supported_word0_x86_features =
2321 F(FPU) | F(VME) | F(DE) | F(PSE) |
2322 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2323 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
2324 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2325 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
2326 0 /* Reserved, DS, ACPI */ | F(MMX) |
2327 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
2328 0 /* HTT, TM, Reserved, PBE */;
2329 /* cpuid 0x80000001.edx */
2330 const u32 kvm_supported_word1_x86_features =
2331 F(FPU) | F(VME) | F(DE) | F(PSE) |
2332 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2333 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
2334 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2335 F(PAT) | F(PSE36) | 0 /* Reserved */ |
2336 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
4e47c7a6 2337 F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
7faa4ee1
AK		 2338 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
2339 /* cpuid 1.ecx */
2340 const u32 kvm_supported_word4_x86_features =
6c3f6041 2341 F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ |
d149c731
AK		 2342 0 /* DS-CPL, VMX, SMX, EST */ |
2343 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
2344 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
2345 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 2346 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
6d886fd0 2347 0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) |
4a00efdf 2348 F(F16C) | F(RDRAND);
7faa4ee1 2349 /* cpuid 0x80000001.ecx */
07716717 2350 const u32 kvm_supported_word6_x86_features =
4c62a2dc 2351 F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ |
7faa4ee1 2352 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
7ef8aa72 2353 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(XOP) |
6d886fd0 2354 0 /* SKINIT, WDT, LWP */ | F(FMA4) | F(TBM);
07716717 2355
4429d5dc
B		 2356 /* cpuid 0xC0000001.edx */
2357 const u32 kvm_supported_word5_x86_features =
2358 F(XSTORE) | F(XSTORE_EN) | F(XCRYPT) | F(XCRYPT_EN) |
2359 F(ACE2) | F(ACE2_EN) | F(PHE) | F(PHE_EN) |
2360 F(PMM) | F(PMM_EN);
2361
611c120f
YW		 2362 /* cpuid 7.0.ebx */
2363 const u32 kvm_supported_word9_x86_features =
2364 F(SMEP);
2365
19355475 2366 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 2367 get_cpu();
2368 do_cpuid_1_ent(entry, function, index);
2369 ++*nent;
2370
2371 switch (function) {
2372 case 0:
2acf923e 2373 entry->eax = min(entry->eax, (u32)0xd);
07716717
DK		 2374 break;
2375 case 1:
2376 entry->edx &= kvm_supported_word0_x86_features;
945ee35e 2377 cpuid_mask(&entry->edx, 0);
7faa4ee1 2378 entry->ecx &= kvm_supported_word4_x86_features;
945ee35e 2379 cpuid_mask(&entry->ecx, 4);
0d1de2d9
GN		 2380 /* we support x2apic emulation even if host does not support
2381 * it since we emulate x2apic in software */
2382 entry->ecx |= F(X2APIC);
07716717
DK		 2383 break;
2384 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
2385 * may return different values. This forces us to get_cpu() before
2386 * issuing the first command, and also to emulate this annoying behavior
2387 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
2388 case 2: {
2389 int t, times = entry->eax & 0xff;
2390
2391 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 2392 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 2393 for (t = 1; t < times && *nent < maxnent; ++t) {
2394 do_cpuid_1_ent(&entry[t], function, 0);
2395 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
2396 ++*nent;
2397 }
2398 break;
2399 }
611c120f 2400 /* function 4 has additional index. */
07716717 2401 case 4: {
14af3f3c 2402 int i, cache_type;
07716717
DK		 2403
2404 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2405 /* read more entries until cache_type is zero */
14af3f3c
HH		 2406 for (i = 1; *nent < maxnent; ++i) {
2407 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 2408 if (!cache_type)
2409 break;
14af3f3c
HH		 2410 do_cpuid_1_ent(&entry[i], function, i);
2411 entry[i].flags |=
07716717
DK		 2412 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2413 ++*nent;
2414 }
2415 break;
2416 }
611c120f
YW		 2417 case 7: {
2418 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2419 /* Mask ebx against host capbability word 9 */
2420 if (index == 0) {
2421 entry->ebx &= kvm_supported_word9_x86_features;
2422 cpuid_mask(&entry->ebx, 9);
2423 } else
2424 entry->ebx = 0;
2425 entry->eax = 0;
2426 entry->ecx = 0;
2427 entry->edx = 0;
2428 break;
2429 }
24c82e57
AK		 2430 case 9:
2431 break;
611c120f 2432 /* function 0xb has additional index. */
07716717 2433 case 0xb: {
14af3f3c 2434 int i, level_type;
07716717
DK		 2435
2436 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2437 /* read more entries until level_type is zero */
14af3f3c 2438 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 2439 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 2440 if (!level_type)
2441 break;
14af3f3c
HH		 2442 do_cpuid_1_ent(&entry[i], function, i);
2443 entry[i].flags |=
07716717
DK		 2444 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2445 ++*nent;
2446 }
2447 break;
2448 }
2acf923e 2449 case 0xd: {
02668b06 2450 int idx, i;
2acf923e
DC		 2451
2452 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
02668b06
AP		 2453 for (idx = 1, i = 1; *nent < maxnent && idx < 64; ++idx) {
2454 do_cpuid_1_ent(&entry[i], function, idx);
2455 if (entry[i].eax == 0 || !supported_xcr0_bit(idx))
20800bc9 2456 continue;
2acf923e
DC		 2457 entry[i].flags |=
2458 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2459 ++*nent;
02668b06 2460 ++i;
2acf923e
DC		 2461 }
2462 break;
2463 }
84478c82
GC		 2464 case KVM_CPUID_SIGNATURE: {
2465 char signature[12] = "KVMKVMKVM\0\0";
2466 u32 *sigptr = (u32 *)signature;
2467 entry->eax = 0;
2468 entry->ebx = sigptr[0];
2469 entry->ecx = sigptr[1];
2470 entry->edx = sigptr[2];
2471 break;
2472 }
2473 case KVM_CPUID_FEATURES:
2474 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) |
2475 (1 << KVM_FEATURE_NOP_IO_DELAY) |
371bcf64 2476 (1 << KVM_FEATURE_CLOCKSOURCE2) |
32918924 2477 (1 << KVM_FEATURE_ASYNC_PF) |
371bcf64 2478 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
84478c82
GC		 2479 entry->ebx = 0;
2480 entry->ecx = 0;
2481 entry->edx = 0;
2482 break;
07716717
DK		 2483 case 0x80000000:
2484 entry->eax = min(entry->eax, 0x8000001a);
2485 break;
2486 case 0x80000001:
2487 entry->edx &= kvm_supported_word1_x86_features;
945ee35e 2488 cpuid_mask(&entry->edx, 1);
07716717 2489 entry->ecx &= kvm_supported_word6_x86_features;
945ee35e 2490 cpuid_mask(&entry->ecx, 6);
07716717 2491 break;
24c82e57
AK		 2492 case 0x80000008: {
2493 unsigned g_phys_as = (entry->eax >> 16) & 0xff;
2494 unsigned virt_as = max((entry->eax >> 8) & 0xff, 48U);
2495 unsigned phys_as = entry->eax & 0xff;
2496
2497 if (!g_phys_as)
2498 g_phys_as = phys_as;
2499 entry->eax = g_phys_as | (virt_as << 8);
2500 entry->ebx = entry->edx = 0;
2501 break;
2502 }
2503 case 0x80000019:
2504 entry->ecx = entry->edx = 0;
2505 break;
2506 case 0x8000001a:
2507 break;
2508 case 0x8000001d:
2509 break;
4429d5dc
B		 2510 /*Add support for Centaur's CPUID instruction*/
2511 case 0xC0000000:
2512 /*Just support up to 0xC0000004 now*/
2513 entry->eax = min(entry->eax, 0xC0000004);
2514 break;
2515 case 0xC0000001:
2516 entry->edx &= kvm_supported_word5_x86_features;
2517 cpuid_mask(&entry->edx, 5);
2518 break;
24c82e57
AK		 2519 case 3: /* Processor serial number */
2520 case 5: /* MONITOR/MWAIT */
2521 case 6: /* Thermal management */
2522 case 0xA: /* Architectural Performance Monitoring */
2523 case 0x80000007: /* Advanced power management */
4429d5dc
B		 2524 case 0xC0000002:
2525 case 0xC0000003:
2526 case 0xC0000004:
24c82e57
AK		 2527 default:
2528 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
4429d5dc 2529 break;
07716717 2530 }
d4330ef2
JR		 2531
2532 kvm_x86_ops->set_supported_cpuid(function, entry);
2533
07716717
DK		 2534 put_cpu();
2535}
2536
7faa4ee1
AK		 2537#undef F
2538
674eea0f 2539static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 2540 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2541{
2542 struct kvm_cpuid_entry2 *cpuid_entries;
2543 int limit, nent = 0, r = -E2BIG;
2544 u32 func;
2545
2546 if (cpuid->nent < 1)
2547 goto out;
6a544355
AK		 2548 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2549 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
07716717
DK		 2550 r = -ENOMEM;
2551 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
2552 if (!cpuid_entries)
2553 goto out;
2554
2555 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
2556 limit = cpuid_entries[0].eax;
2557 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
2558 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2559 &nent, cpuid->nent);
07716717
DK		 2560 r = -E2BIG;
2561 if (nent >= cpuid->nent)
2562 goto out_free;
2563
2564 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
2565 limit = cpuid_entries[nent - 1].eax;
2566 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
2567 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2568 &nent, cpuid->nent);
84478c82
GC		 2569
2570
2571
2572 r = -E2BIG;
2573 if (nent >= cpuid->nent)
2574 goto out_free;
2575
4429d5dc
B		 2576 /* Add support for Centaur's CPUID instruction. */
2577 if (boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR) {
2578 do_cpuid_ent(&cpuid_entries[nent], 0xC0000000, 0,
2579 &nent, cpuid->nent);
2580
2581 r = -E2BIG;
2582 if (nent >= cpuid->nent)
2583 goto out_free;
2584
2585 limit = cpuid_entries[nent - 1].eax;
2586 for (func = 0xC0000001;
2587 func <= limit && nent < cpuid->nent; ++func)
2588 do_cpuid_ent(&cpuid_entries[nent], func, 0,
2589 &nent, cpuid->nent);
2590
2591 r = -E2BIG;
2592 if (nent >= cpuid->nent)
2593 goto out_free;
2594 }
2595
84478c82
GC		 2596 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_SIGNATURE, 0, &nent,
2597 cpuid->nent);
2598
2599 r = -E2BIG;
2600 if (nent >= cpuid->nent)
2601 goto out_free;
2602
2603 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_FEATURES, 0, &nent,
2604 cpuid->nent);
2605
cb007648
MM		 2606 r = -E2BIG;
2607 if (nent >= cpuid->nent)
2608 goto out_free;
2609
07716717
DK		 2610 r = -EFAULT;
2611 if (copy_to_user(entries, cpuid_entries,
19355475 2612 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2613 goto out_free;
2614 cpuid->nent = nent;
2615 r = 0;
2616
2617out_free:
2618 vfree(cpuid_entries);
2619out:
2620 return r;
2621}
2622
313a3dc7
CO		 2623static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2624 struct kvm_lapic_state *s)
2625{
ad312c7c 2626 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2627
2628 return 0;
2629}
2630
2631static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2632 struct kvm_lapic_state *s)
2633{
ad312c7c 2634 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 2635 kvm_apic_post_state_restore(vcpu);
cb142eb7 2636 update_cr8_intercept(vcpu);
313a3dc7
CO		 2637
2638 return 0;
2639}
2640
f77bc6a4
ZX		 2641static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2642 struct kvm_interrupt *irq)
2643{
2644 if (irq->irq < 0 || irq->irq >= 256)
2645 return -EINVAL;
2646 if (irqchip_in_kernel(vcpu->kvm))
2647 return -ENXIO;
f77bc6a4 2648
66fd3f7f 2649 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2650 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2651
f77bc6a4
ZX		 2652 return 0;
2653}
2654
c4abb7c9
JK		 2655static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2656{
c4abb7c9 2657 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2658
2659 return 0;
2660}
2661
b209749f
AK		 2662static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2663 struct kvm_tpr_access_ctl *tac)
2664{
2665 if (tac->flags)
2666 return -EINVAL;
2667 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2668 return 0;
2669}
2670
890ca9ae
HY		 2671static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2672 u64 mcg_cap)
2673{
2674 int r;
2675 unsigned bank_num = mcg_cap & 0xff, bank;
2676
2677 r = -EINVAL;
a9e38c3e 2678 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2679 goto out;
2680 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2681 goto out;
2682 r = 0;
2683 vcpu->arch.mcg_cap = mcg_cap;
2684 /* Init IA32_MCG_CTL to all 1s */
2685 if (mcg_cap & MCG_CTL_P)
2686 vcpu->arch.mcg_ctl = ~(u64)0;
2687 /* Init IA32_MCi_CTL to all 1s */
2688 for (bank = 0; bank < bank_num; bank++)
2689 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2690out:
2691 return r;
2692}
2693
2694static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2695 struct kvm_x86_mce *mce)
2696{
2697 u64 mcg_cap = vcpu->arch.mcg_cap;
2698 unsigned bank_num = mcg_cap & 0xff;
2699 u64 *banks = vcpu->arch.mce_banks;
2700
2701 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2702 return -EINVAL;
2703 /*
2704 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2705 * reporting is disabled
2706 */
2707 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2708 vcpu->arch.mcg_ctl != ~(u64)0)
2709 return 0;
2710 banks += 4 * mce->bank;
2711 /*
2712 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2713 * reporting is disabled for the bank
2714 */
2715 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2716 return 0;
2717 if (mce->status & MCI_STATUS_UC) {
2718 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2719 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2720 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2721 return 0;
2722 }
2723 if (banks[1] & MCI_STATUS_VAL)
2724 mce->status |= MCI_STATUS_OVER;
2725 banks[2] = mce->addr;
2726 banks[3] = mce->misc;
2727 vcpu->arch.mcg_status = mce->mcg_status;
2728 banks[1] = mce->status;
2729 kvm_queue_exception(vcpu, MC_VECTOR);
2730 } else if (!(banks[1] & MCI_STATUS_VAL)
2731 || !(banks[1] & MCI_STATUS_UC)) {
2732 if (banks[1] & MCI_STATUS_VAL)
2733 mce->status |= MCI_STATUS_OVER;
2734 banks[2] = mce->addr;
2735 banks[3] = mce->misc;
2736 banks[1] = mce->status;
2737 } else
2738 banks[1] |= MCI_STATUS_OVER;
2739 return 0;
2740}
2741
3cfc3092
JK		 2742static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2743 struct kvm_vcpu_events *events)
2744{
03b82a30
JK		 2745 events->exception.injected =
2746 vcpu->arch.exception.pending &&
2747 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2748 events->exception.nr = vcpu->arch.exception.nr;
2749 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2750 events->exception.pad = 0;
3cfc3092
JK		 2751 events->exception.error_code = vcpu->arch.exception.error_code;
2752
03b82a30
JK		 2753 events->interrupt.injected =
2754 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2755 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2756 events->interrupt.soft = 0;
48005f64
JK		 2757 events->interrupt.shadow =
2758 kvm_x86_ops->get_interrupt_shadow(vcpu,
2759 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2760
2761 events->nmi.injected = vcpu->arch.nmi_injected;
2762 events->nmi.pending = vcpu->arch.nmi_pending;
2763 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2764 events->nmi.pad = 0;
3cfc3092
JK		 2765
2766 events->sipi_vector = vcpu->arch.sipi_vector;
2767
dab4b911 2768 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2769 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2770 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 2771 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2772}
2773
2774static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2775 struct kvm_vcpu_events *events)
2776{
dab4b911 2777 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2778 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2779 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2780 return -EINVAL;
2781
3cfc3092
JK		 2782 vcpu->arch.exception.pending = events->exception.injected;
2783 vcpu->arch.exception.nr = events->exception.nr;
2784 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2785 vcpu->arch.exception.error_code = events->exception.error_code;
2786
2787 vcpu->arch.interrupt.pending = events->interrupt.injected;
2788 vcpu->arch.interrupt.nr = events->interrupt.nr;
2789 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2790 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2791 kvm_x86_ops->set_interrupt_shadow(vcpu,
2792 events->interrupt.shadow);
3cfc3092
JK		 2793
2794 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2795 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2796 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2797 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2798
dab4b911
JK		 2799 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2800 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092 2801
3842d135
AK		 2802 kvm_make_request(KVM_REQ_EVENT, vcpu);
2803
3cfc3092
JK		 2804 return 0;
2805}
2806
a1efbe77
JK		 2807static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2808 struct kvm_debugregs *dbgregs)
2809{
a1efbe77
JK		 2810 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2811 dbgregs->dr6 = vcpu->arch.dr6;
2812 dbgregs->dr7 = vcpu->arch.dr7;
2813 dbgregs->flags = 0;
97e69aa6 2814 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 2815}
2816
2817static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2818 struct kvm_debugregs *dbgregs)
2819{
2820 if (dbgregs->flags)
2821 return -EINVAL;
2822
a1efbe77
JK		 2823 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2824 vcpu->arch.dr6 = dbgregs->dr6;
2825 vcpu->arch.dr7 = dbgregs->dr7;
2826
a1efbe77
JK		 2827 return 0;
2828}
2829
2d5b5a66
SY		 2830static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2831 struct kvm_xsave *guest_xsave)
2832{
2833 if (cpu_has_xsave)
2834 memcpy(guest_xsave->region,
2835 &vcpu->arch.guest_fpu.state->xsave,
f45755b8 2836 xstate_size);
2d5b5a66
SY		 2837 else {
2838 memcpy(guest_xsave->region,
2839 &vcpu->arch.guest_fpu.state->fxsave,
2840 sizeof(struct i387_fxsave_struct));
2841 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2842 XSTATE_FPSSE;
2843 }
2844}
2845
2846static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2847 struct kvm_xsave *guest_xsave)
2848{
2849 u64 xstate_bv =
2850 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2851
2852 if (cpu_has_xsave)
2853 memcpy(&vcpu->arch.guest_fpu.state->xsave,
f45755b8 2854 guest_xsave->region, xstate_size);
2d5b5a66
SY		 2855 else {
2856 if (xstate_bv & ~XSTATE_FPSSE)
2857 return -EINVAL;
2858 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2859 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2860 }
2861 return 0;
2862}
2863
2864static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2865 struct kvm_xcrs *guest_xcrs)
2866{
2867 if (!cpu_has_xsave) {
2868 guest_xcrs->nr_xcrs = 0;
2869 return;
2870 }
2871
2872 guest_xcrs->nr_xcrs = 1;
2873 guest_xcrs->flags = 0;
2874 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2875 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2876}
2877
2878static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2879 struct kvm_xcrs *guest_xcrs)
2880{
2881 int i, r = 0;
2882
2883 if (!cpu_has_xsave)
2884 return -EINVAL;
2885
2886 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2887 return -EINVAL;
2888
2889 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2890 /* Only support XCR0 currently */
2891 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2892 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2893 guest_xcrs->xcrs[0].value);
2894 break;
2895 }
2896 if (r)
2897 r = -EINVAL;
2898 return r;
2899}
2900
313a3dc7
CO		 2901long kvm_arch_vcpu_ioctl(struct file *filp,
2902 unsigned int ioctl, unsigned long arg)
2903{
2904 struct kvm_vcpu *vcpu = filp->private_data;
2905 void __user *argp = (void __user *)arg;
2906 int r;
d1ac91d8
AK		 2907 union {
2908 struct kvm_lapic_state *lapic;
2909 struct kvm_xsave *xsave;
2910 struct kvm_xcrs *xcrs;
2911 void *buffer;
2912 } u;
2913
2914 u.buffer = NULL;
313a3dc7
CO		 2915 switch (ioctl) {
2916 case KVM_GET_LAPIC: {
2204ae3c
MT		 2917 r = -EINVAL;
2918 if (!vcpu->arch.apic)
2919 goto out;
d1ac91d8 2920 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2921
b772ff36 2922 r = -ENOMEM;
d1ac91d8 2923 if (!u.lapic)
b772ff36 2924 goto out;
d1ac91d8 2925 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 2926 if (r)
2927 goto out;
2928 r = -EFAULT;
d1ac91d8 2929 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2930 goto out;
2931 r = 0;
2932 break;
2933 }
2934 case KVM_SET_LAPIC: {
2204ae3c
MT		 2935 r = -EINVAL;
2936 if (!vcpu->arch.apic)
2937 goto out;
d1ac91d8 2938 u.lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
b772ff36 2939 r = -ENOMEM;
d1ac91d8 2940 if (!u.lapic)
b772ff36 2941 goto out;
313a3dc7 2942 r = -EFAULT;
d1ac91d8 2943 if (copy_from_user(u.lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 2944 goto out;
d1ac91d8 2945 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 2946 if (r)
2947 goto out;
2948 r = 0;
2949 break;
2950 }
f77bc6a4
ZX		 2951 case KVM_INTERRUPT: {
2952 struct kvm_interrupt irq;
2953
2954 r = -EFAULT;
2955 if (copy_from_user(&irq, argp, sizeof irq))
2956 goto out;
2957 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2958 if (r)
2959 goto out;
2960 r = 0;
2961 break;
2962 }
c4abb7c9
JK		 2963 case KVM_NMI: {
2964 r = kvm_vcpu_ioctl_nmi(vcpu);
2965 if (r)
2966 goto out;
2967 r = 0;
2968 break;
2969 }
313a3dc7
CO		 2970 case KVM_SET_CPUID: {
2971 struct kvm_cpuid __user *cpuid_arg = argp;
2972 struct kvm_cpuid cpuid;
2973
2974 r = -EFAULT;
2975 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2976 goto out;
2977 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2978 if (r)
2979 goto out;
2980 break;
2981 }
07716717
DK		 2982 case KVM_SET_CPUID2: {
2983 struct kvm_cpuid2 __user *cpuid_arg = argp;
2984 struct kvm_cpuid2 cpuid;
2985
2986 r = -EFAULT;
2987 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2988 goto out;
2989 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2990 cpuid_arg->entries);
07716717
DK		 2991 if (r)
2992 goto out;
2993 break;
2994 }
2995 case KVM_GET_CPUID2: {
2996 struct kvm_cpuid2 __user *cpuid_arg = argp;
2997 struct kvm_cpuid2 cpuid;
2998
2999 r = -EFAULT;
3000 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3001 goto out;
3002 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3003 cpuid_arg->entries);
07716717
DK		 3004 if (r)
3005 goto out;
3006 r = -EFAULT;
3007 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3008 goto out;
3009 r = 0;
3010 break;
3011 }
313a3dc7
CO		 3012 case KVM_GET_MSRS:
3013 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3014 break;
3015 case KVM_SET_MSRS:
3016 r = msr_io(vcpu, argp, do_set_msr, 0);
3017 break;
b209749f
AK		 3018 case KVM_TPR_ACCESS_REPORTING: {
3019 struct kvm_tpr_access_ctl tac;
3020
3021 r = -EFAULT;
3022 if (copy_from_user(&tac, argp, sizeof tac))
3023 goto out;
3024 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3025 if (r)
3026 goto out;
3027 r = -EFAULT;
3028 if (copy_to_user(argp, &tac, sizeof tac))
3029 goto out;
3030 r = 0;
3031 break;
3032 };
b93463aa
AK		 3033 case KVM_SET_VAPIC_ADDR: {
3034 struct kvm_vapic_addr va;
3035
3036 r = -EINVAL;
3037 if (!irqchip_in_kernel(vcpu->kvm))
3038 goto out;
3039 r = -EFAULT;
3040 if (copy_from_user(&va, argp, sizeof va))
3041 goto out;
3042 r = 0;
3043 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3044 break;
3045 }
890ca9ae
HY		 3046 case KVM_X86_SETUP_MCE: {
3047 u64 mcg_cap;
3048
3049 r = -EFAULT;
3050 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3051 goto out;
3052 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3053 break;
3054 }
3055 case KVM_X86_SET_MCE: {
3056 struct kvm_x86_mce mce;
3057
3058 r = -EFAULT;
3059 if (copy_from_user(&mce, argp, sizeof mce))
3060 goto out;
3061 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3062 break;
3063 }
3cfc3092
JK		 3064 case KVM_GET_VCPU_EVENTS: {
3065 struct kvm_vcpu_events events;
3066
3067 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3068
3069 r = -EFAULT;
3070 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3071 break;
3072 r = 0;
3073 break;
3074 }
3075 case KVM_SET_VCPU_EVENTS: {
3076 struct kvm_vcpu_events events;
3077
3078 r = -EFAULT;
3079 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3080 break;
3081
3082 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3083 break;
3084 }
a1efbe77
JK		 3085 case KVM_GET_DEBUGREGS: {
3086 struct kvm_debugregs dbgregs;
3087
3088 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3089
3090 r = -EFAULT;
3091 if (copy_to_user(argp, &dbgregs,
3092 sizeof(struct kvm_debugregs)))
3093 break;
3094 r = 0;
3095 break;
3096 }
3097 case KVM_SET_DEBUGREGS: {
3098 struct kvm_debugregs dbgregs;
3099
3100 r = -EFAULT;
3101 if (copy_from_user(&dbgregs, argp,
3102 sizeof(struct kvm_debugregs)))
3103 break;
3104
3105 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3106 break;
3107 }
2d5b5a66 3108 case KVM_GET_XSAVE: {
d1ac91d8 3109 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3110 r = -ENOMEM;
d1ac91d8 3111 if (!u.xsave)
2d5b5a66
SY		 3112 break;
3113
d1ac91d8 3114 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3115
3116 r = -EFAULT;
d1ac91d8 3117 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3118 break;
3119 r = 0;
3120 break;
3121 }
3122 case KVM_SET_XSAVE: {
d1ac91d8 3123 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3124 r = -ENOMEM;
d1ac91d8 3125 if (!u.xsave)
2d5b5a66
SY		 3126 break;
3127
3128 r = -EFAULT;
d1ac91d8 3129 if (copy_from_user(u.xsave, argp, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3130 break;
3131
d1ac91d8 3132 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3133 break;
3134 }
3135 case KVM_GET_XCRS: {
d1ac91d8 3136 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3137 r = -ENOMEM;
d1ac91d8 3138 if (!u.xcrs)
2d5b5a66
SY		 3139 break;
3140
d1ac91d8 3141 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3142
3143 r = -EFAULT;
d1ac91d8 3144 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3145 sizeof(struct kvm_xcrs)))
3146 break;
3147 r = 0;
3148 break;
3149 }
3150 case KVM_SET_XCRS: {
d1ac91d8 3151 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3152 r = -ENOMEM;
d1ac91d8 3153 if (!u.xcrs)
2d5b5a66
SY		 3154 break;
3155
3156 r = -EFAULT;
d1ac91d8 3157 if (copy_from_user(u.xcrs, argp,
2d5b5a66
SY		 3158 sizeof(struct kvm_xcrs)))
3159 break;
3160
d1ac91d8 3161 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3162 break;
3163 }
92a1f12d
JR		 3164 case KVM_SET_TSC_KHZ: {
3165 u32 user_tsc_khz;
3166
3167 r = -EINVAL;
3168 if (!kvm_has_tsc_control)
3169 break;
3170
3171 user_tsc_khz = (u32)arg;
3172
3173 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3174 goto out;
3175
3176 kvm_x86_ops->set_tsc_khz(vcpu, user_tsc_khz);
3177
3178 r = 0;
3179 goto out;
3180 }
3181 case KVM_GET_TSC_KHZ: {
3182 r = -EIO;
3183 if (check_tsc_unstable())
3184 goto out;
3185
3186 r = vcpu_tsc_khz(vcpu);
3187
3188 goto out;
3189 }
313a3dc7
CO		 3190 default:
3191 r = -EINVAL;
3192 }
3193out:
d1ac91d8 3194 kfree(u.buffer);
313a3dc7
CO		 3195 return r;
3196}
3197
1fe779f8
CO		 3198static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3199{
3200 int ret;
3201
3202 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3203 return -1;
3204 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3205 return ret;
3206}
3207
b927a3ce
SY		 3208static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3209 u64 ident_addr)
3210{
3211 kvm->arch.ept_identity_map_addr = ident_addr;
3212 return 0;
3213}
3214
1fe779f8
CO		 3215static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3216 u32 kvm_nr_mmu_pages)
3217{
3218 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3219 return -EINVAL;
3220
79fac95e 3221 mutex_lock(&kvm->slots_lock);
7c8a83b7 3222 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 3223
3224 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3225 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3226
7c8a83b7 3227 spin_unlock(&kvm->mmu_lock);
79fac95e 3228 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3229 return 0;
3230}
3231
3232static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3233{
39de71ec 3234 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3235}
3236
1fe779f8
CO		 3237static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3238{
3239 int r;
3240
3241 r = 0;
3242 switch (chip->chip_id) {
3243 case KVM_IRQCHIP_PIC_MASTER:
3244 memcpy(&chip->chip.pic,
3245 &pic_irqchip(kvm)->pics[0],
3246 sizeof(struct kvm_pic_state));
3247 break;
3248 case KVM_IRQCHIP_PIC_SLAVE:
3249 memcpy(&chip->chip.pic,
3250 &pic_irqchip(kvm)->pics[1],
3251 sizeof(struct kvm_pic_state));
3252 break;
3253 case KVM_IRQCHIP_IOAPIC:
eba0226b 3254 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3255 break;
3256 default:
3257 r = -EINVAL;
3258 break;
3259 }
3260 return r;
3261}
3262
3263static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3264{
3265 int r;
3266
3267 r = 0;
3268 switch (chip->chip_id) {
3269 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3270 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3271 memcpy(&pic_irqchip(kvm)->pics[0],
3272 &chip->chip.pic,
3273 sizeof(struct kvm_pic_state));
f4f51050 3274 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3275 break;
3276 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3277 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3278 memcpy(&pic_irqchip(kvm)->pics[1],
3279 &chip->chip.pic,
3280 sizeof(struct kvm_pic_state));
f4f51050 3281 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3282 break;
3283 case KVM_IRQCHIP_IOAPIC:
eba0226b 3284 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3285 break;
3286 default:
3287 r = -EINVAL;
3288 break;
3289 }
3290 kvm_pic_update_irq(pic_irqchip(kvm));
3291 return r;
3292}
3293
e0f63cb9
SY		 3294static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3295{
3296 int r = 0;
3297
894a9c55 3298 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3299 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3300 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3301 return r;
3302}
3303
3304static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3305{
3306 int r = 0;
3307
894a9c55 3308 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3309 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3310 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3311 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3312 return r;
3313}
3314
3315static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3316{
3317 int r = 0;
3318
3319 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3320 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3321 sizeof(ps->channels));
3322 ps->flags = kvm->arch.vpit->pit_state.flags;
3323 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3324 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3325 return r;
3326}
3327
3328static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3329{
3330 int r = 0, start = 0;
3331 u32 prev_legacy, cur_legacy;
3332 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3333 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3334 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3335 if (!prev_legacy && cur_legacy)
3336 start = 1;
3337 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3338 sizeof(kvm->arch.vpit->pit_state.channels));
3339 kvm->arch.vpit->pit_state.flags = ps->flags;
3340 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3341 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3342 return r;
3343}
3344
52d939a0
MT		 3345static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3346 struct kvm_reinject_control *control)
3347{
3348 if (!kvm->arch.vpit)
3349 return -ENXIO;
894a9c55 3350 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 3351 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 3352 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3353 return 0;
3354}
3355
5bb064dc
ZX		 3356/*
3357 * Get (and clear) the dirty memory log for a memory slot.
3358 */
3359int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
3360 struct kvm_dirty_log *log)
3361{
87bf6e7d 3362 int r, i;
5bb064dc 3363 struct kvm_memory_slot *memslot;
87bf6e7d 3364 unsigned long n;
b050b015 3365 unsigned long is_dirty = 0;
5bb064dc 3366
79fac95e 3367 mutex_lock(&kvm->slots_lock);
5bb064dc 3368
b050b015
MT		 3369 r = -EINVAL;
3370 if (log->slot >= KVM_MEMORY_SLOTS)
3371 goto out;
3372
3373 memslot = &kvm->memslots->memslots[log->slot];
3374 r = -ENOENT;
3375 if (!memslot->dirty_bitmap)
3376 goto out;
3377
87bf6e7d 3378 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3379
b050b015
MT		 3380 for (i = 0; !is_dirty && i < n/sizeof(long); i++)
3381 is_dirty = memslot->dirty_bitmap[i];
5bb064dc
ZX		 3382
3383 /* If nothing is dirty, don't bother messing with page tables. */
3384 if (is_dirty) {
b050b015 3385 struct kvm_memslots *slots, *old_slots;
914ebccd 3386 unsigned long *dirty_bitmap;
b050b015 3387
515a0127
TY		 3388 dirty_bitmap = memslot->dirty_bitmap_head;
3389 if (memslot->dirty_bitmap == dirty_bitmap)
3390 dirty_bitmap += n / sizeof(long);
914ebccd 3391 memset(dirty_bitmap, 0, n);
b050b015 3392
914ebccd
TY		 3393 r = -ENOMEM;
3394 slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
515a0127 3395 if (!slots)
914ebccd 3396 goto out;
b050b015
MT		 3397 memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
3398 slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
49c7754c 3399 slots->generation++;
b050b015
MT		 3400
3401 old_slots = kvm->memslots;
3402 rcu_assign_pointer(kvm->memslots, slots);
3403 synchronize_srcu_expedited(&kvm->srcu);
3404 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
3405 kfree(old_slots);
914ebccd 3406
edde99ce
MT		 3407 spin_lock(&kvm->mmu_lock);
3408 kvm_mmu_slot_remove_write_access(kvm, log->slot);
3409 spin_unlock(&kvm->mmu_lock);
3410
914ebccd 3411 r = -EFAULT;
515a0127 3412 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n))
914ebccd 3413 goto out;
914ebccd
TY		 3414 } else {
3415 r = -EFAULT;
3416 if (clear_user(log->dirty_bitmap, n))
3417 goto out;
5bb064dc 3418 }
b050b015 3419
5bb064dc
ZX		 3420 r = 0;
3421out:
79fac95e 3422 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3423 return r;
3424}
3425
1fe779f8
CO		 3426long kvm_arch_vm_ioctl(struct file *filp,
3427 unsigned int ioctl, unsigned long arg)
3428{
3429 struct kvm *kvm = filp->private_data;
3430 void __user *argp = (void __user *)arg;
367e1319 3431 int r = -ENOTTY;
f0d66275
DH		 3432 /*
3433 * This union makes it completely explicit to gcc-3.x
3434 * that these two variables' stack usage should be
3435 * combined, not added together.
3436 */
3437 union {
3438 struct kvm_pit_state ps;
e9f42757 3439 struct kvm_pit_state2 ps2;
c5ff41ce 3440 struct kvm_pit_config pit_config;
f0d66275 3441 } u;
1fe779f8
CO		 3442
3443 switch (ioctl) {
3444 case KVM_SET_TSS_ADDR:
3445 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3446 if (r < 0)
3447 goto out;
3448 break;
b927a3ce
SY		 3449 case KVM_SET_IDENTITY_MAP_ADDR: {
3450 u64 ident_addr;
3451
3452 r = -EFAULT;
3453 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3454 goto out;
3455 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3456 if (r < 0)
3457 goto out;
3458 break;
3459 }
1fe779f8
CO		 3460 case KVM_SET_NR_MMU_PAGES:
3461 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3462 if (r)
3463 goto out;
3464 break;
3465 case KVM_GET_NR_MMU_PAGES:
3466 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3467 break;
3ddea128
MT		 3468 case KVM_CREATE_IRQCHIP: {
3469 struct kvm_pic *vpic;
3470
3471 mutex_lock(&kvm->lock);
3472 r = -EEXIST;
3473 if (kvm->arch.vpic)
3474 goto create_irqchip_unlock;
1fe779f8 3475 r = -ENOMEM;
3ddea128
MT		 3476 vpic = kvm_create_pic(kvm);
3477 if (vpic) {
1fe779f8
CO		 3478 r = kvm_ioapic_init(kvm);
3479 if (r) {
175504cd 3480 mutex_lock(&kvm->slots_lock);
72bb2fcd
WY		 3481 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3482 &vpic->dev);
175504cd 3483 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3484 kfree(vpic);
3485 goto create_irqchip_unlock;
1fe779f8
CO		 3486 }
3487 } else
3ddea128
MT		 3488 goto create_irqchip_unlock;
3489 smp_wmb();
3490 kvm->arch.vpic = vpic;
3491 smp_wmb();
399ec807
AK		 3492 r = kvm_setup_default_irq_routing(kvm);
3493 if (r) {
175504cd 3494 mutex_lock(&kvm->slots_lock);
3ddea128 3495 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3496 kvm_ioapic_destroy(kvm);
3497 kvm_destroy_pic(kvm);
3ddea128 3498 mutex_unlock(&kvm->irq_lock);
175504cd 3499 mutex_unlock(&kvm->slots_lock);
399ec807 3500 }
3ddea128
MT		 3501 create_irqchip_unlock:
3502 mutex_unlock(&kvm->lock);
1fe779f8 3503 break;
3ddea128 3504 }
7837699f 3505 case KVM_CREATE_PIT:
c5ff41ce
JK		 3506 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3507 goto create_pit;
3508 case KVM_CREATE_PIT2:
3509 r = -EFAULT;
3510 if (copy_from_user(&u.pit_config, argp,
3511 sizeof(struct kvm_pit_config)))
3512 goto out;
3513 create_pit:
79fac95e 3514 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3515 r = -EEXIST;
3516 if (kvm->arch.vpit)
3517 goto create_pit_unlock;
7837699f 3518 r = -ENOMEM;
c5ff41ce 3519 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3520 if (kvm->arch.vpit)
3521 r = 0;
269e05e4 3522 create_pit_unlock:
79fac95e 3523 mutex_unlock(&kvm->slots_lock);
7837699f 3524 break;
4925663a 3525 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 3526 case KVM_IRQ_LINE: {
3527 struct kvm_irq_level irq_event;
3528
3529 r = -EFAULT;
3530 if (copy_from_user(&irq_event, argp, sizeof irq_event))
3531 goto out;
160d2f6c 3532 r = -ENXIO;
1fe779f8 3533 if (irqchip_in_kernel(kvm)) {
4925663a 3534 __s32 status;
4925663a
GN		 3535 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3536 irq_event.irq, irq_event.level);
4925663a 3537 if (ioctl == KVM_IRQ_LINE_STATUS) {
160d2f6c 3538 r = -EFAULT;
4925663a
GN		 3539 irq_event.status = status;
3540 if (copy_to_user(argp, &irq_event,
3541 sizeof irq_event))
3542 goto out;
3543 }
1fe779f8
CO		 3544 r = 0;
3545 }
3546 break;
3547 }
3548 case KVM_GET_IRQCHIP: {
3549 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3550 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3551
f0d66275
DH		 3552 r = -ENOMEM;
3553 if (!chip)
1fe779f8 3554 goto out;
f0d66275
DH		 3555 r = -EFAULT;
3556 if (copy_from_user(chip, argp, sizeof *chip))
3557 goto get_irqchip_out;
1fe779f8
CO		 3558 r = -ENXIO;
3559 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3560 goto get_irqchip_out;
3561 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3562 if (r)
f0d66275 3563 goto get_irqchip_out;
1fe779f8 3564 r = -EFAULT;
f0d66275
DH		 3565 if (copy_to_user(argp, chip, sizeof *chip))
3566 goto get_irqchip_out;
1fe779f8 3567 r = 0;
f0d66275
DH		 3568 get_irqchip_out:
3569 kfree(chip);
3570 if (r)
3571 goto out;
1fe779f8
CO		 3572 break;
3573 }
3574 case KVM_SET_IRQCHIP: {
3575 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3576 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3577
f0d66275
DH		 3578 r = -ENOMEM;
3579 if (!chip)
1fe779f8 3580 goto out;
f0d66275
DH		 3581 r = -EFAULT;
3582 if (copy_from_user(chip, argp, sizeof *chip))
3583 goto set_irqchip_out;
1fe779f8
CO		 3584 r = -ENXIO;
3585 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3586 goto set_irqchip_out;
3587 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3588 if (r)
f0d66275 3589 goto set_irqchip_out;
1fe779f8 3590 r = 0;
f0d66275
DH		 3591 set_irqchip_out:
3592 kfree(chip);
3593 if (r)
3594 goto out;
1fe779f8
CO		 3595 break;
3596 }
e0f63cb9 3597 case KVM_GET_PIT: {
e0f63cb9 3598 r = -EFAULT;
f0d66275 3599 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3600 goto out;
3601 r = -ENXIO;
3602 if (!kvm->arch.vpit)
3603 goto out;
f0d66275 3604 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3605 if (r)
3606 goto out;
3607 r = -EFAULT;
f0d66275 3608 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3609 goto out;
3610 r = 0;
3611 break;
3612 }
3613 case KVM_SET_PIT: {
e0f63cb9 3614 r = -EFAULT;
f0d66275 3615 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3616 goto out;
3617 r = -ENXIO;
3618 if (!kvm->arch.vpit)
3619 goto out;
f0d66275 3620 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3621 if (r)
3622 goto out;
3623 r = 0;
3624 break;
3625 }
e9f42757
BK		 3626 case KVM_GET_PIT2: {
3627 r = -ENXIO;
3628 if (!kvm->arch.vpit)
3629 goto out;
3630 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3631 if (r)
3632 goto out;
3633 r = -EFAULT;
3634 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3635 goto out;
3636 r = 0;
3637 break;
3638 }
3639 case KVM_SET_PIT2: {
3640 r = -EFAULT;
3641 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3642 goto out;
3643 r = -ENXIO;
3644 if (!kvm->arch.vpit)
3645 goto out;
3646 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3647 if (r)
3648 goto out;
3649 r = 0;
3650 break;
3651 }
52d939a0
MT		 3652 case KVM_REINJECT_CONTROL: {
3653 struct kvm_reinject_control control;
3654 r = -EFAULT;
3655 if (copy_from_user(&control, argp, sizeof(control)))
3656 goto out;
3657 r = kvm_vm_ioctl_reinject(kvm, &control);
3658 if (r)
3659 goto out;
3660 r = 0;
3661 break;
3662 }
ffde22ac
ES		 3663 case KVM_XEN_HVM_CONFIG: {
3664 r = -EFAULT;
3665 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3666 sizeof(struct kvm_xen_hvm_config)))
3667 goto out;
3668 r = -EINVAL;
3669 if (kvm->arch.xen_hvm_config.flags)
3670 goto out;
3671 r = 0;
3672 break;
3673 }
afbcf7ab 3674 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3675 struct kvm_clock_data user_ns;
3676 u64 now_ns;
3677 s64 delta;
3678
3679 r = -EFAULT;
3680 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3681 goto out;
3682
3683 r = -EINVAL;
3684 if (user_ns.flags)
3685 goto out;
3686
3687 r = 0;
395c6b0a 3688 local_irq_disable();
759379dd 3689 now_ns = get_kernel_ns();
afbcf7ab 3690 delta = user_ns.clock - now_ns;
395c6b0a 3691 local_irq_enable();
afbcf7ab
GC		 3692 kvm->arch.kvmclock_offset = delta;
3693 break;
3694 }
3695 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3696 struct kvm_clock_data user_ns;
3697 u64 now_ns;
3698
395c6b0a 3699 local_irq_disable();
759379dd 3700 now_ns = get_kernel_ns();
afbcf7ab 3701 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3702 local_irq_enable();
afbcf7ab 3703 user_ns.flags = 0;
97e69aa6 3704 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3705
3706 r = -EFAULT;
3707 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3708 goto out;
3709 r = 0;
3710 break;
3711 }
3712
1fe779f8
CO		 3713 default:
3714 ;
3715 }
3716out:
3717 return r;
3718}
3719
a16b043c 3720static void kvm_init_msr_list(void)
043405e1
CO		 3721{
3722 u32 dummy[2];
3723 unsigned i, j;
3724
e3267cbb
GC		 3725 /* skip the first msrs in the list. KVM-specific */
3726 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3727 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3728 continue;
3729 if (j < i)
3730 msrs_to_save[j] = msrs_to_save[i];
3731 j++;
3732 }
3733 num_msrs_to_save = j;
3734}
3735
bda9020e
MT		 3736static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3737 const void *v)
bbd9b64e 3738{
70252a10
AK		 3739 int handled = 0;
3740 int n;
3741
3742 do {
3743 n = min(len, 8);
3744 if (!(vcpu->arch.apic &&
3745 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3746 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3747 break;
3748 handled += n;
3749 addr += n;
3750 len -= n;
3751 v += n;
3752 } while (len);
bbd9b64e 3753
70252a10 3754 return handled;
bbd9b64e
CO		 3755}
3756
bda9020e 3757static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3758{
70252a10
AK		 3759 int handled = 0;
3760 int n;
3761
3762 do {
3763 n = min(len, 8);
3764 if (!(vcpu->arch.apic &&
3765 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3766 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3767 break;
3768 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3769 handled += n;
3770 addr += n;
3771 len -= n;
3772 v += n;
3773 } while (len);
bbd9b64e 3774
70252a10 3775 return handled;
bbd9b64e
CO		 3776}
3777
2dafc6c2
GN		 3778static void kvm_set_segment(struct kvm_vcpu *vcpu,
3779 struct kvm_segment *var, int seg)
3780{
3781 kvm_x86_ops->set_segment(vcpu, var, seg);
3782}
3783
3784void kvm_get_segment(struct kvm_vcpu *vcpu,
3785 struct kvm_segment *var, int seg)
3786{
3787 kvm_x86_ops->get_segment(vcpu, var, seg);
3788}
3789
c30a358d
JR		 3790static gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3791{
3792 return gpa;
3793}
3794
02f59dc9
JR		 3795static gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3796{
3797 gpa_t t_gpa;
ab9ae313 3798 struct x86_exception exception;
02f59dc9
JR		 3799
3800 BUG_ON(!mmu_is_nested(vcpu));
3801
3802 /* NPT walks are always user-walks */
3803 access |= PFERR_USER_MASK;
ab9ae313 3804 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
02f59dc9
JR		 3805
3806 return t_gpa;
3807}
3808
ab9ae313
AK		 3809gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3810 struct x86_exception *exception)
1871c602
GN		 3811{
3812 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 3813 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3814}
3815
ab9ae313
AK		 3816 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3817 struct x86_exception *exception)
1871c602
GN		 3818{
3819 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3820 access |= PFERR_FETCH_MASK;
ab9ae313 3821 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3822}
3823
ab9ae313
AK		 3824gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3825 struct x86_exception *exception)
1871c602
GN		 3826{
3827 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3828 access |= PFERR_WRITE_MASK;
ab9ae313 3829 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3830}
3831
3832/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 3833gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3834 struct x86_exception *exception)
1871c602 3835{
ab9ae313 3836 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 3837}
3838
3839static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3840 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 3841 struct x86_exception *exception)
bbd9b64e
CO		 3842{
3843 void *data = val;
10589a46 3844 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3845
3846 while (bytes) {
14dfe855 3847 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 3848 exception);
bbd9b64e 3849 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3850 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3851 int ret;
3852
bcc55cba 3853 if (gpa == UNMAPPED_GVA)
ab9ae313 3854 return X86EMUL_PROPAGATE_FAULT;
77c2002e 3855 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3856 if (ret < 0) {
c3cd7ffa 3857 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3858 goto out;
3859 }
bbd9b64e 3860
77c2002e
IE		 3861 bytes -= toread;
3862 data += toread;
3863 addr += toread;
bbd9b64e 3864 }
10589a46 3865out:
10589a46 3866 return r;
bbd9b64e 3867}
77c2002e 3868
1871c602 3869/* used for instruction fetching */
0f65dd70
AK		 3870static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
3871 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3872 struct x86_exception *exception)
1871c602 3873{
0f65dd70 3874 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3875 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3876
1871c602 3877 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
bcc55cba
AK		 3878 access | PFERR_FETCH_MASK,
3879 exception);
1871c602
GN		 3880}
3881
064aea77 3882int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 3883 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3884 struct x86_exception *exception)
1871c602 3885{
0f65dd70 3886 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3887 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3888
1871c602 3889 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 3890 exception);
1871c602 3891}
064aea77 3892EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 3893
0f65dd70
AK		 3894static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3895 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3896 struct x86_exception *exception)
1871c602 3897{
0f65dd70 3898 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 3899 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 3900}
3901
6a4d7550 3902int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 3903 gva_t addr, void *val,
2dafc6c2 3904 unsigned int bytes,
bcc55cba 3905 struct x86_exception *exception)
77c2002e 3906{
0f65dd70 3907 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 3908 void *data = val;
3909 int r = X86EMUL_CONTINUE;
3910
3911 while (bytes) {
14dfe855
JR		 3912 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3913 PFERR_WRITE_MASK,
ab9ae313 3914 exception);
77c2002e
IE		 3915 unsigned offset = addr & (PAGE_SIZE-1);
3916 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3917 int ret;
3918
bcc55cba 3919 if (gpa == UNMAPPED_GVA)
ab9ae313 3920 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 3921 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3922 if (ret < 0) {
c3cd7ffa 3923 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 3924 goto out;
3925 }
3926
3927 bytes -= towrite;
3928 data += towrite;
3929 addr += towrite;
3930 }
3931out:
3932 return r;
3933}
6a4d7550 3934EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 3935
0f65dd70
AK		 3936static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
3937 unsigned long addr,
bbd9b64e
CO		 3938 void *val,
3939 unsigned int bytes,
0f65dd70 3940 struct x86_exception *exception)
bbd9b64e 3941{
0f65dd70 3942 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bbd9b64e 3943 gpa_t gpa;
70252a10 3944 int handled;
bbd9b64e
CO		 3945
3946 if (vcpu->mmio_read_completed) {
3947 memcpy(val, vcpu->mmio_data, bytes);
aec51dc4
AK		 3948 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3949 vcpu->mmio_phys_addr, *(u64 *)val);
bbd9b64e
CO		 3950 vcpu->mmio_read_completed = 0;
3951 return X86EMUL_CONTINUE;
3952 }
3953
ab9ae313 3954 gpa = kvm_mmu_gva_to_gpa_read(vcpu, addr, exception);
1871c602 3955
8fe681e9 3956 if (gpa == UNMAPPED_GVA)
1871c602 3957 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3958
3959 /* For APIC access vmexit */
3960 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3961 goto mmio;
3962
0f65dd70 3963 if (kvm_read_guest_virt(ctxt, addr, val, bytes, exception)
bcc55cba 3964 == X86EMUL_CONTINUE)
bbd9b64e 3965 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3966
3967mmio:
3968 /*
3969 * Is this MMIO handled locally?
3970 */
70252a10
AK		 3971 handled = vcpu_mmio_read(vcpu, gpa, bytes, val);
3972
3973 if (handled == bytes)
bbd9b64e 3974 return X86EMUL_CONTINUE;
70252a10
AK		 3975
3976 gpa += handled;
3977 bytes -= handled;
3978 val += handled;
aec51dc4
AK		 3979
3980 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
bbd9b64e
CO		 3981
3982 vcpu->mmio_needed = 1;
411c35b7
GN		 3983 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3984 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
cef4dea0
AK		 3985 vcpu->mmio_size = bytes;
3986 vcpu->run->mmio.len = min(vcpu->mmio_size, 8);
411c35b7 3987 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 0;
cef4dea0 3988 vcpu->mmio_index = 0;
bbd9b64e 3989
c3cd7ffa 3990 return X86EMUL_IO_NEEDED;
bbd9b64e
CO		 3991}
3992
3200f405 3993int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 3994 const void *val, int bytes)
bbd9b64e
CO		 3995{
3996 int ret;
3997
3998 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3999 if (ret < 0)
bbd9b64e 4000 return 0;
ad218f85 4001 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 4002 return 1;
4003}
4004
4005static int emulator_write_emulated_onepage(unsigned long addr,
4006 const void *val,
4007 unsigned int bytes,
bcc55cba 4008 struct x86_exception *exception,
bbd9b64e
CO		 4009 struct kvm_vcpu *vcpu)
4010{
10589a46 4011 gpa_t gpa;
70252a10 4012 int handled;
10589a46 4013
ab9ae313 4014 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, exception);
bbd9b64e 4015
8fe681e9 4016 if (gpa == UNMAPPED_GVA)
bbd9b64e 4017 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4018
4019 /* For APIC access vmexit */
4020 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4021 goto mmio;
4022
4023 if (emulator_write_phys(vcpu, gpa, val, bytes))
4024 return X86EMUL_CONTINUE;
4025
4026mmio:
aec51dc4 4027 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 4028 /*
4029 * Is this MMIO handled locally?
4030 */
70252a10
AK		 4031 handled = vcpu_mmio_write(vcpu, gpa, bytes, val);
4032 if (handled == bytes)
bbd9b64e 4033 return X86EMUL_CONTINUE;
bbd9b64e 4034
70252a10
AK		 4035 gpa += handled;
4036 bytes -= handled;
4037 val += handled;
4038
bbd9b64e 4039 vcpu->mmio_needed = 1;
cef4dea0 4040 memcpy(vcpu->mmio_data, val, bytes);
411c35b7
GN		 4041 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4042 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
cef4dea0
AK		 4043 vcpu->mmio_size = bytes;
4044 vcpu->run->mmio.len = min(vcpu->mmio_size, 8);
411c35b7 4045 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 1;
cef4dea0
AK		 4046 memcpy(vcpu->run->mmio.data, vcpu->mmio_data, 8);
4047 vcpu->mmio_index = 0;
bbd9b64e
CO		 4048
4049 return X86EMUL_CONTINUE;
4050}
4051
0f65dd70
AK		 4052int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4053 unsigned long addr,
8f6abd06
GN		 4054 const void *val,
4055 unsigned int bytes,
0f65dd70 4056 struct x86_exception *exception)
bbd9b64e 4057{
0f65dd70
AK		 4058 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4059
bbd9b64e
CO		 4060 /* Crossing a page boundary? */
4061 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
4062 int rc, now;
4063
4064 now = -addr & ~PAGE_MASK;
bcc55cba 4065 rc = emulator_write_emulated_onepage(addr, val, now, exception,
8fe681e9 4066 vcpu);
bbd9b64e
CO		 4067 if (rc != X86EMUL_CONTINUE)
4068 return rc;
4069 addr += now;
4070 val += now;
4071 bytes -= now;
4072 }
bcc55cba 4073 return emulator_write_emulated_onepage(addr, val, bytes, exception,
8fe681e9 4074 vcpu);
bbd9b64e 4075}
bbd9b64e 4076
daea3e73
AK		 4077#define CMPXCHG_TYPE(t, ptr, old, new) \
4078 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4079
4080#ifdef CONFIG_X86_64
4081# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4082#else
4083# define CMPXCHG64(ptr, old, new) \
9749a6c0 4084 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4085#endif
4086
0f65dd70
AK		 4087static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4088 unsigned long addr,
bbd9b64e
CO		 4089 const void *old,
4090 const void *new,
4091 unsigned int bytes,
0f65dd70 4092 struct x86_exception *exception)
bbd9b64e 4093{
0f65dd70 4094 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4095 gpa_t gpa;
4096 struct page *page;
4097 char *kaddr;
4098 bool exchanged;
2bacc55c 4099
daea3e73
AK		 4100 /* guests cmpxchg8b have to be emulated atomically */
4101 if (bytes > 8 || (bytes & (bytes - 1)))
4102 goto emul_write;
10589a46 4103
daea3e73 4104 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4105
daea3e73
AK		 4106 if (gpa == UNMAPPED_GVA ||
4107 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4108 goto emul_write;
2bacc55c 4109
daea3e73
AK		 4110 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4111 goto emul_write;
72dc67a6 4112
daea3e73 4113 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
c19b8bd6
WY		 4114 if (is_error_page(page)) {
4115 kvm_release_page_clean(page);
4116 goto emul_write;
4117 }
72dc67a6 4118
daea3e73
AK		 4119 kaddr = kmap_atomic(page, KM_USER0);
4120 kaddr += offset_in_page(gpa);
4121 switch (bytes) {
4122 case 1:
4123 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4124 break;
4125 case 2:
4126 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4127 break;
4128 case 4:
4129 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4130 break;
4131 case 8:
4132 exchanged = CMPXCHG64(kaddr, old, new);
4133 break;
4134 default:
4135 BUG();
2bacc55c 4136 }
daea3e73
AK		 4137 kunmap_atomic(kaddr, KM_USER0);
4138 kvm_release_page_dirty(page);
4139
4140 if (!exchanged)
4141 return X86EMUL_CMPXCHG_FAILED;
4142
8f6abd06
GN		 4143 kvm_mmu_pte_write(vcpu, gpa, new, bytes, 1);
4144
4145 return X86EMUL_CONTINUE;
4a5f48f6 4146
3200f405 4147emul_write:
daea3e73 4148 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4149
0f65dd70 4150 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4151}
4152
cf8f70bf
GN		 4153static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4154{
4155 /* TODO: String I/O for in kernel device */
4156 int r;
4157
4158 if (vcpu->arch.pio.in)
4159 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4160 vcpu->arch.pio.size, pd);
4161 else
4162 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4163 vcpu->arch.pio.port, vcpu->arch.pio.size,
4164 pd);
4165 return r;
4166}
4167
4168
ca1d4a9e
AK		 4169static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4170 int size, unsigned short port, void *val,
4171 unsigned int count)
cf8f70bf 4172{
ca1d4a9e
AK		 4173 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4174
7972995b 4175 if (vcpu->arch.pio.count)
cf8f70bf
GN		 4176 goto data_avail;
4177
61cfab2e 4178 trace_kvm_pio(0, port, size, count);
cf8f70bf
GN		 4179
4180 vcpu->arch.pio.port = port;
4181 vcpu->arch.pio.in = 1;
7972995b 4182 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4183 vcpu->arch.pio.size = size;
4184
4185 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4186 data_avail:
4187 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 4188 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4189 return 1;
4190 }
4191
4192 vcpu->run->exit_reason = KVM_EXIT_IO;
4193 vcpu->run->io.direction = KVM_EXIT_IO_IN;
4194 vcpu->run->io.size = size;
4195 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4196 vcpu->run->io.count = count;
4197 vcpu->run->io.port = port;
4198
4199 return 0;
4200}
4201
ca1d4a9e
AK		 4202static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4203 int size, unsigned short port,
4204 const void *val, unsigned int count)
cf8f70bf 4205{
ca1d4a9e
AK		 4206 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4207
61cfab2e 4208 trace_kvm_pio(1, port, size, count);
cf8f70bf
GN		 4209
4210 vcpu->arch.pio.port = port;
4211 vcpu->arch.pio.in = 0;
7972995b 4212 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4213 vcpu->arch.pio.size = size;
4214
4215 memcpy(vcpu->arch.pio_data, val, size * count);
4216
4217 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4218 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4219 return 1;
4220 }
4221
4222 vcpu->run->exit_reason = KVM_EXIT_IO;
4223 vcpu->run->io.direction = KVM_EXIT_IO_OUT;
4224 vcpu->run->io.size = size;
4225 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4226 vcpu->run->io.count = count;
4227 vcpu->run->io.port = port;
4228
4229 return 0;
4230}
4231
bbd9b64e
CO		 4232static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4233{
4234 return kvm_x86_ops->get_segment_base(vcpu, seg);
4235}
4236
3cb16fe7 4237static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4238{
3cb16fe7 4239 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4240}
4241
f5f48ee1
SY		 4242int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4243{
4244 if (!need_emulate_wbinvd(vcpu))
4245 return X86EMUL_CONTINUE;
4246
4247 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4248 int cpu = get_cpu();
4249
4250 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4251 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4252 wbinvd_ipi, NULL, 1);
2eec7343 4253 put_cpu();
f5f48ee1 4254 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4255 } else
4256 wbinvd();
f5f48ee1
SY		 4257 return X86EMUL_CONTINUE;
4258}
4259EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4260
bcaf5cc5
AK		 4261static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4262{
4263 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4264}
4265
717746e3 4266int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
bbd9b64e 4267{
717746e3 4268 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4269}
4270
717746e3 4271int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
bbd9b64e 4272{
338dbc97 4273
717746e3 4274 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4275}
4276
52a46617 4277static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4278{
52a46617 4279 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4280}
4281
717746e3 4282static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4283{
717746e3 4284 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4285 unsigned long value;
4286
4287 switch (cr) {
4288 case 0:
4289 value = kvm_read_cr0(vcpu);
4290 break;
4291 case 2:
4292 value = vcpu->arch.cr2;
4293 break;
4294 case 3:
9f8fe504 4295 value = kvm_read_cr3(vcpu);
52a46617
GN		 4296 break;
4297 case 4:
4298 value = kvm_read_cr4(vcpu);
4299 break;
4300 case 8:
4301 value = kvm_get_cr8(vcpu);
4302 break;
4303 default:
4304 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
4305 return 0;
4306 }
4307
4308 return value;
4309}
4310
717746e3 4311static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4312{
717746e3 4313 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4314 int res = 0;
4315
52a46617
GN		 4316 switch (cr) {
4317 case 0:
49a9b07e 4318 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4319 break;
4320 case 2:
4321 vcpu->arch.cr2 = val;
4322 break;
4323 case 3:
2390218b 4324 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4325 break;
4326 case 4:
a83b29c6 4327 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4328 break;
4329 case 8:
eea1cff9 4330 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4331 break;
4332 default:
4333 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
0f12244f 4334 res = -1;
52a46617 4335 }
0f12244f
GN		 4336
4337 return res;
52a46617
GN		 4338}
4339
717746e3 4340static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4341{
717746e3 4342 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4343}
4344
4bff1e86 4345static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4346{
4bff1e86 4347 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4348}
4349
4bff1e86 4350static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4351{
4bff1e86 4352 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4353}
4354
1ac9d0cf
AK		 4355static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4356{
4357 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4358}
4359
4360static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4361{
4362 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4363}
4364
4bff1e86
AK		 4365static unsigned long emulator_get_cached_segment_base(
4366 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4367{
4bff1e86 4368 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4369}
4370
1aa36616
AK		 4371static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4372 struct desc_struct *desc, u32 *base3,
4373 int seg)
2dafc6c2
GN		 4374{
4375 struct kvm_segment var;
4376
4bff1e86 4377 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4378 *selector = var.selector;
2dafc6c2
GN		 4379
4380 if (var.unusable)
4381 return false;
4382
4383 if (var.g)
4384 var.limit >>= 12;
4385 set_desc_limit(desc, var.limit);
4386 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4387#ifdef CONFIG_X86_64
4388 if (base3)
4389 *base3 = var.base >> 32;
4390#endif
2dafc6c2
GN		 4391 desc->type = var.type;
4392 desc->s = var.s;
4393 desc->dpl = var.dpl;
4394 desc->p = var.present;
4395 desc->avl = var.avl;
4396 desc->l = var.l;
4397 desc->d = var.db;
4398 desc->g = var.g;
4399
4400 return true;
4401}
4402
1aa36616
AK		 4403static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4404 struct desc_struct *desc, u32 base3,
4405 int seg)
2dafc6c2 4406{
4bff1e86 4407 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4408 struct kvm_segment var;
4409
1aa36616 4410 var.selector = selector;
2dafc6c2 4411 var.base = get_desc_base(desc);
5601d05b
GN		 4412#ifdef CONFIG_X86_64
4413 var.base |= ((u64)base3) << 32;
4414#endif
2dafc6c2
GN		 4415 var.limit = get_desc_limit(desc);
4416 if (desc->g)
4417 var.limit = (var.limit << 12) | 0xfff;
4418 var.type = desc->type;
4419 var.present = desc->p;
4420 var.dpl = desc->dpl;
4421 var.db = desc->d;
4422 var.s = desc->s;
4423 var.l = desc->l;
4424 var.g = desc->g;
4425 var.avl = desc->avl;
4426 var.present = desc->p;
4427 var.unusable = !var.present;
4428 var.padding = 0;
4429
4430 kvm_set_segment(vcpu, &var, seg);
4431 return;
4432}
4433
717746e3
AK		 4434static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4435 u32 msr_index, u64 *pdata)
4436{
4437 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4438}
4439
4440static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4441 u32 msr_index, u64 data)
4442{
4443 return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
4444}
4445
6c3287f7
AK		 4446static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4447{
4448 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4449}
4450
5037f6f3
AK		 4451static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4452{
4453 preempt_disable();
5197b808 4454 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4455 /*
4456 * CR0.TS may reference the host fpu state, not the guest fpu state,
4457 * so it may be clear at this point.
4458 */
4459 clts();
4460}
4461
4462static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4463{
4464 preempt_enable();
4465}
4466
2953538e 4467static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4468 struct x86_instruction_info *info,
c4f035c6
AK		 4469 enum x86_intercept_stage stage)
4470{
2953538e 4471 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4472}
4473
14af3f3c 4474static struct x86_emulate_ops emulate_ops = {
1871c602 4475 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4476 .write_std = kvm_write_guest_virt_system,
1871c602 4477 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4478 .read_emulated = emulator_read_emulated,
4479 .write_emulated = emulator_write_emulated,
4480 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4481 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4482 .pio_in_emulated = emulator_pio_in_emulated,
4483 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4484 .get_segment = emulator_get_segment,
4485 .set_segment = emulator_set_segment,
5951c442 4486 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4487 .get_gdt = emulator_get_gdt,
160ce1f1 4488 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4489 .set_gdt = emulator_set_gdt,
4490 .set_idt = emulator_set_idt,
52a46617
GN		 4491 .get_cr = emulator_get_cr,
4492 .set_cr = emulator_set_cr,
9c537244 4493 .cpl = emulator_get_cpl,
35aa5375
GN		 4494 .get_dr = emulator_get_dr,
4495 .set_dr = emulator_set_dr,
717746e3
AK		 4496 .set_msr = emulator_set_msr,
4497 .get_msr = emulator_get_msr,
6c3287f7 4498 .halt = emulator_halt,
bcaf5cc5 4499 .wbinvd = emulator_wbinvd,
d6aa1000 4500 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4501 .get_fpu = emulator_get_fpu,
4502 .put_fpu = emulator_put_fpu,
c4f035c6 4503 .intercept = emulator_intercept,
bbd9b64e
CO		 4504};
4505
5fdbf976
MT		 4506static void cache_all_regs(struct kvm_vcpu *vcpu)
4507{
4508 kvm_register_read(vcpu, VCPU_REGS_RAX);
4509 kvm_register_read(vcpu, VCPU_REGS_RSP);
4510 kvm_register_read(vcpu, VCPU_REGS_RIP);
4511 vcpu->arch.regs_dirty = ~0;
4512}
4513
95cb2295
GN		 4514static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4515{
4516 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4517 /*
4518 * an sti; sti; sequence only disable interrupts for the first
4519 * instruction. So, if the last instruction, be it emulated or
4520 * not, left the system with the INT_STI flag enabled, it
4521 * means that the last instruction is an sti. We should not
4522 * leave the flag on in this case. The same goes for mov ss
4523 */
4524 if (!(int_shadow & mask))
4525 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4526}
4527
54b8486f
GN		 4528static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4529{
4530 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4531 if (ctxt->exception.vector == PF_VECTOR)
6389ee94 4532 kvm_propagate_fault(vcpu, &ctxt->exception);
da9cb575
AK		 4533 else if (ctxt->exception.error_code_valid)
4534 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4535 ctxt->exception.error_code);
54b8486f 4536 else
da9cb575 4537 kvm_queue_exception(vcpu, ctxt->exception.vector);
54b8486f
GN		 4538}
4539
9dac77fa 4540static void init_decode_cache(struct x86_emulate_ctxt *ctxt,
b5c9ff73
TY		 4541 const unsigned long *regs)
4542{
9dac77fa
AK		 4543 memset(&ctxt->twobyte, 0,
4544 (void *)&ctxt->regs - (void *)&ctxt->twobyte);
4545 memcpy(ctxt->regs, regs, sizeof(ctxt->regs));
b5c9ff73 4546
9dac77fa
AK		 4547 ctxt->fetch.start = 0;
4548 ctxt->fetch.end = 0;
4549 ctxt->io_read.pos = 0;
4550 ctxt->io_read.end = 0;
4551 ctxt->mem_read.pos = 0;
4552 ctxt->mem_read.end = 0;
b5c9ff73
TY		 4553}
4554
8ec4722d
MG		 4555static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4556{
adf52235 4557 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4558 int cs_db, cs_l;
4559
2aab2c5b
GN		 4560 /*
4561 * TODO: fix emulate.c to use guest_read/write_register
4562 * instead of direct ->regs accesses, can save hundred cycles
4563 * on Intel for instructions that don't read/change RSP, for
4564 * for example.
4565 */
8ec4722d
MG		 4566 cache_all_regs(vcpu);
4567
4568 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4569
adf52235
TY		 4570 ctxt->eflags = kvm_get_rflags(vcpu);
4571 ctxt->eip = kvm_rip_read(vcpu);
4572 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4573 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4574 cs_l ? X86EMUL_MODE_PROT64 :
4575 cs_db ? X86EMUL_MODE_PROT32 :
4576 X86EMUL_MODE_PROT16;
4577 ctxt->guest_mode = is_guest_mode(vcpu);
4578
9dac77fa 4579 init_decode_cache(ctxt, vcpu->arch.regs);
7ae441ea 4580 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4581}
4582
71f9833b 4583int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 4584{
9d74191a 4585 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 4586 int ret;
4587
4588 init_emulate_ctxt(vcpu);
4589
9dac77fa
AK		 4590 ctxt->op_bytes = 2;
4591 ctxt->ad_bytes = 2;
4592 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 4593 ret = emulate_int_real(ctxt, irq);
63995653
MG		 4594
4595 if (ret != X86EMUL_CONTINUE)
4596 return EMULATE_FAIL;
4597
9dac77fa
AK		 4598 ctxt->eip = ctxt->_eip;
4599 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
9d74191a
TY		 4600 kvm_rip_write(vcpu, ctxt->eip);
4601 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 4602
4603 if (irq == NMI_VECTOR)
4604 vcpu->arch.nmi_pending = false;
4605 else
4606 vcpu->arch.interrupt.pending = false;
4607
4608 return EMULATE_DONE;
4609}
4610EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4611
6d77dbfc
GN		 4612static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4613{
fc3a9157
JR		 4614 int r = EMULATE_DONE;
4615
6d77dbfc
GN		 4616 ++vcpu->stat.insn_emulation_fail;
4617 trace_kvm_emulate_insn_failed(vcpu);
fc3a9157
JR		 4618 if (!is_guest_mode(vcpu)) {
4619 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4620 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4621 vcpu->run->internal.ndata = 0;
4622 r = EMULATE_FAIL;
4623 }
6d77dbfc 4624 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4625
4626 return r;
6d77dbfc
GN		 4627}
4628
a6f177ef
GN		 4629static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
4630{
4631 gpa_t gpa;
4632
68be0803
GN		 4633 if (tdp_enabled)
4634 return false;
4635
a6f177ef
GN		 4636 /*
4637 * if emulation was due to access to shadowed page table
4638 * and it failed try to unshadow page and re-entetr the
4639 * guest to let CPU execute the instruction.
4640 */
4641 if (kvm_mmu_unprotect_page_virt(vcpu, gva))
4642 return true;
4643
4644 gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
4645
4646 if (gpa == UNMAPPED_GVA)
4647 return true; /* let cpu generate fault */
4648
4649 if (!kvm_is_error_hva(gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT)))
4650 return true;
4651
4652 return false;
4653}
4654
51d8b661
AP		 4655int x86_emulate_instruction(struct kvm_vcpu *vcpu,
4656 unsigned long cr2,
dc25e89e
AP		 4657 int emulation_type,
4658 void *insn,
4659 int insn_len)
bbd9b64e 4660{
95cb2295 4661 int r;
9d74191a 4662 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 4663 bool writeback = true;
bbd9b64e 4664
26eef70c 4665 kvm_clear_exception_queue(vcpu);
8d7d8102 4666
571008da 4667 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 4668 init_emulate_ctxt(vcpu);
9d74191a
TY		 4669 ctxt->interruptibility = 0;
4670 ctxt->have_exception = false;
4671 ctxt->perm_ok = false;
bbd9b64e 4672
9d74191a 4673 ctxt->only_vendor_specific_insn
4005996e
AK		 4674 = emulation_type & EMULTYPE_TRAP_UD;
4675
9d74191a 4676 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 4677
e46479f8 4678 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 4679 ++vcpu->stat.insn_emulation;
bbd9b64e 4680 if (r) {
4005996e
AK		 4681 if (emulation_type & EMULTYPE_TRAP_UD)
4682 return EMULATE_FAIL;
a6f177ef 4683 if (reexecute_instruction(vcpu, cr2))
bbd9b64e 4684 return EMULATE_DONE;
6d77dbfc
GN		 4685 if (emulation_type & EMULTYPE_SKIP)
4686 return EMULATE_FAIL;
4687 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4688 }
4689 }
4690
ba8afb6b 4691 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 4692 kvm_rip_write(vcpu, ctxt->_eip);
ba8afb6b
GN		 4693 return EMULATE_DONE;
4694 }
4695
7ae441ea 4696 /* this is needed for vmware backdoor interface to work since it
4d2179e1 4697 changes registers values during IO operation */
7ae441ea
GN		 4698 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
4699 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
9dac77fa 4700 memcpy(ctxt->regs, vcpu->arch.regs, sizeof ctxt->regs);
7ae441ea 4701 }
4d2179e1 4702
5cd21917 4703restart:
9d74191a 4704 r = x86_emulate_insn(ctxt);
bbd9b64e 4705
775fde86
JR		 4706 if (r == EMULATION_INTERCEPTED)
4707 return EMULATE_DONE;
4708
d2ddd1c4 4709 if (r == EMULATION_FAILED) {
a6f177ef 4710 if (reexecute_instruction(vcpu, cr2))
c3cd7ffa
GN		 4711 return EMULATE_DONE;
4712
6d77dbfc 4713 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4714 }
4715
9d74191a 4716 if (ctxt->have_exception) {
54b8486f 4717 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 4718 r = EMULATE_DONE;
4719 } else if (vcpu->arch.pio.count) {
3457e419
GN		 4720 if (!vcpu->arch.pio.in)
4721 vcpu->arch.pio.count = 0;
7ae441ea
GN		 4722 else
4723 writeback = false;
e85d28f8 4724 r = EMULATE_DO_MMIO;
7ae441ea
GN		 4725 } else if (vcpu->mmio_needed) {
4726 if (!vcpu->mmio_is_write)
4727 writeback = false;
e85d28f8 4728 r = EMULATE_DO_MMIO;
7ae441ea 4729 } else if (r == EMULATION_RESTART)
5cd21917 4730 goto restart;
d2ddd1c4
GN		 4731 else
4732 r = EMULATE_DONE;
f850e2e6 4733
7ae441ea 4734 if (writeback) {
9d74191a
TY		 4735 toggle_interruptibility(vcpu, ctxt->interruptibility);
4736 kvm_set_rflags(vcpu, ctxt->eflags);
7ae441ea 4737 kvm_make_request(KVM_REQ_EVENT, vcpu);
9dac77fa 4738 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
7ae441ea 4739 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 4740 kvm_rip_write(vcpu, ctxt->eip);
7ae441ea
GN		 4741 } else
4742 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 4743
4744 return r;
de7d789a 4745}
51d8b661 4746EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 4747
cf8f70bf 4748int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 4749{
cf8f70bf 4750 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 4751 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
4752 size, port, &val, 1);
cf8f70bf 4753 /* do not return to emulator after return from userspace */
7972995b 4754 vcpu->arch.pio.count = 0;
de7d789a
CO		 4755 return ret;
4756}
cf8f70bf 4757EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 4758
8cfdc000
ZA		 4759static void tsc_bad(void *info)
4760{
0a3aee0d 4761 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 4762}
4763
4764static void tsc_khz_changed(void *data)
c8076604 4765{
8cfdc000
ZA		 4766 struct cpufreq_freqs *freq = data;
4767 unsigned long khz = 0;
4768
4769 if (data)
4770 khz = freq->new;
4771 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4772 khz = cpufreq_quick_get(raw_smp_processor_id());
4773 if (!khz)
4774 khz = tsc_khz;
0a3aee0d 4775 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 4776}
4777
c8076604
GH		 4778static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4779 void *data)
4780{
4781 struct cpufreq_freqs *freq = data;
4782 struct kvm *kvm;
4783 struct kvm_vcpu *vcpu;
4784 int i, send_ipi = 0;
4785
8cfdc000
ZA		 4786 /*
4787 * We allow guests to temporarily run on slowing clocks,
4788 * provided we notify them after, or to run on accelerating
4789 * clocks, provided we notify them before. Thus time never
4790 * goes backwards.
4791 *
4792 * However, we have a problem. We can't atomically update
4793 * the frequency of a given CPU from this function; it is
4794 * merely a notifier, which can be called from any CPU.
4795 * Changing the TSC frequency at arbitrary points in time
4796 * requires a recomputation of local variables related to
4797 * the TSC for each VCPU. We must flag these local variables
4798 * to be updated and be sure the update takes place with the
4799 * new frequency before any guests proceed.
4800 *
4801 * Unfortunately, the combination of hotplug CPU and frequency
4802 * change creates an intractable locking scenario; the order
4803 * of when these callouts happen is undefined with respect to
4804 * CPU hotplug, and they can race with each other. As such,
4805 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
4806 * undefined; you can actually have a CPU frequency change take
4807 * place in between the computation of X and the setting of the
4808 * variable. To protect against this problem, all updates of
4809 * the per_cpu tsc_khz variable are done in an interrupt
4810 * protected IPI, and all callers wishing to update the value
4811 * must wait for a synchronous IPI to complete (which is trivial
4812 * if the caller is on the CPU already). This establishes the
4813 * necessary total order on variable updates.
4814 *
4815 * Note that because a guest time update may take place
4816 * anytime after the setting of the VCPU's request bit, the
4817 * correct TSC value must be set before the request. However,
4818 * to ensure the update actually makes it to any guest which
4819 * starts running in hardware virtualization between the set
4820 * and the acquisition of the spinlock, we must also ping the
4821 * CPU after setting the request bit.
4822 *
4823 */
4824
c8076604
GH		 4825 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
4826 return 0;
4827 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
4828 return 0;
8cfdc000
ZA		 4829
4830 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 4831
e935b837 4832 raw_spin_lock(&kvm_lock);
c8076604 4833 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 4834 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 4835 if (vcpu->cpu != freq->cpu)
4836 continue;
c285545f 4837 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 4838 if (vcpu->cpu != smp_processor_id())
8cfdc000 4839 send_ipi = 1;
c8076604
GH		 4840 }
4841 }
e935b837 4842 raw_spin_unlock(&kvm_lock);
c8076604
GH		 4843
4844 if (freq->old < freq->new && send_ipi) {
4845 /*
4846 * We upscale the frequency. Must make the guest
4847 * doesn't see old kvmclock values while running with
4848 * the new frequency, otherwise we risk the guest sees
4849 * time go backwards.
4850 *
4851 * In case we update the frequency for another cpu
4852 * (which might be in guest context) send an interrupt
4853 * to kick the cpu out of guest context. Next time
4854 * guest context is entered kvmclock will be updated,
4855 * so the guest will not see stale values.
4856 */
8cfdc000 4857 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 4858 }
4859 return 0;
4860}
4861
4862static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 4863 .notifier_call = kvmclock_cpufreq_notifier
4864};
4865
4866static int kvmclock_cpu_notifier(struct notifier_block *nfb,
4867 unsigned long action, void *hcpu)
4868{
4869 unsigned int cpu = (unsigned long)hcpu;
4870
4871 switch (action) {
4872 case CPU_ONLINE:
4873 case CPU_DOWN_FAILED:
4874 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4875 break;
4876 case CPU_DOWN_PREPARE:
4877 smp_call_function_single(cpu, tsc_bad, NULL, 1);
4878 break;
4879 }
4880 return NOTIFY_OK;
4881}
4882
4883static struct notifier_block kvmclock_cpu_notifier_block = {
4884 .notifier_call = kvmclock_cpu_notifier,
4885 .priority = -INT_MAX
c8076604
GH		 4886};
4887
b820cc0c
ZA		 4888static void kvm_timer_init(void)
4889{
4890 int cpu;
4891
c285545f 4892 max_tsc_khz = tsc_khz;
8cfdc000 4893 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 4894 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 4895#ifdef CONFIG_CPU_FREQ
4896 struct cpufreq_policy policy;
4897 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 4898 cpu = get_cpu();
4899 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 4900 if (policy.cpuinfo.max_freq)
4901 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 4902 put_cpu();
c285545f 4903#endif
b820cc0c
ZA		 4904 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4905 CPUFREQ_TRANSITION_NOTIFIER);
4906 }
c285545f 4907 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 4908 for_each_online_cpu(cpu)
4909 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 4910}
4911
ff9d07a0
ZY		 4912static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
4913
4914static int kvm_is_in_guest(void)
4915{
4916 return percpu_read(current_vcpu) != NULL;
4917}
4918
4919static int kvm_is_user_mode(void)
4920{
4921 int user_mode = 3;
dcf46b94 4922
ff9d07a0
ZY		 4923 if (percpu_read(current_vcpu))
4924 user_mode = kvm_x86_ops->get_cpl(percpu_read(current_vcpu));
dcf46b94 4925
ff9d07a0
ZY		 4926 return user_mode != 0;
4927}
4928
4929static unsigned long kvm_get_guest_ip(void)
4930{
4931 unsigned long ip = 0;
dcf46b94 4932
ff9d07a0
ZY		 4933 if (percpu_read(current_vcpu))
4934 ip = kvm_rip_read(percpu_read(current_vcpu));
dcf46b94 4935
ff9d07a0
ZY		 4936 return ip;
4937}
4938
4939static struct perf_guest_info_callbacks kvm_guest_cbs = {
4940 .is_in_guest = kvm_is_in_guest,
4941 .is_user_mode = kvm_is_user_mode,
4942 .get_guest_ip = kvm_get_guest_ip,
4943};
4944
4945void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4946{
4947 percpu_write(current_vcpu, vcpu);
4948}
4949EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4950
4951void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4952{
4953 percpu_write(current_vcpu, NULL);
4954}
4955EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4956
f8c16bba 4957int kvm_arch_init(void *opaque)
043405e1 4958{
b820cc0c 4959 int r;
f8c16bba
ZX		 4960 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4961
f8c16bba
ZX		 4962 if (kvm_x86_ops) {
4963 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 4964 r = -EEXIST;
4965 goto out;
f8c16bba
ZX		 4966 }
4967
4968 if (!ops->cpu_has_kvm_support()) {
4969 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 4970 r = -EOPNOTSUPP;
4971 goto out;
f8c16bba
ZX		 4972 }
4973 if (ops->disabled_by_bios()) {
4974 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 4975 r = -EOPNOTSUPP;
4976 goto out;
f8c16bba
ZX		 4977 }
4978
97db56ce
AK		 4979 r = kvm_mmu_module_init();
4980 if (r)
4981 goto out;
4982
4983 kvm_init_msr_list();
4984
f8c16bba 4985 kvm_x86_ops = ops;
56c6d28a 4986 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e 4987 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 4988 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 4989
b820cc0c 4990 kvm_timer_init();
c8076604 4991
ff9d07a0
ZY		 4992 perf_register_guest_info_callbacks(&kvm_guest_cbs);
4993
2acf923e
DC		 4994 if (cpu_has_xsave)
4995 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
4996
f8c16bba 4997 return 0;
56c6d28a
ZX		 4998
4999out:
56c6d28a 5000 return r;
043405e1 5001}
8776e519 5002
f8c16bba
ZX		 5003void kvm_arch_exit(void)
5004{
ff9d07a0
ZY		 5005 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5006
888d256e
JK		 5007 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5008 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5009 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5010 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
f8c16bba 5011 kvm_x86_ops = NULL;
56c6d28a
ZX		 5012 kvm_mmu_module_exit();
5013}
f8c16bba 5014
8776e519
HB		 5015int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5016{
5017 ++vcpu->stat.halt_exits;
5018 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 5019 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5020 return 1;
5021 } else {
5022 vcpu->run->exit_reason = KVM_EXIT_HLT;
5023 return 0;
5024 }
5025}
5026EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5027
2f333bcb
MT		 5028static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
5029 unsigned long a1)
5030{
5031 if (is_long_mode(vcpu))
5032 return a0;
5033 else
5034 return a0 | ((gpa_t)a1 << 32);
5035}
5036
55cd8e5a
GN		 5037int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5038{
5039 u64 param, ingpa, outgpa, ret;
5040 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5041 bool fast, longmode;
5042 int cs_db, cs_l;
5043
5044 /*
5045 * hypercall generates UD from non zero cpl and real mode
5046 * per HYPER-V spec
5047 */
3eeb3288 5048 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 5049 kvm_queue_exception(vcpu, UD_VECTOR);
5050 return 0;
5051 }
5052
5053 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5054 longmode = is_long_mode(vcpu) && cs_l == 1;
5055
5056 if (!longmode) {
ccd46936
GN		 5057 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5058 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5059 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5060 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5061 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5062 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 5063 }
5064#ifdef CONFIG_X86_64
5065 else {
5066 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5067 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5068 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5069 }
5070#endif
5071
5072 code = param & 0xffff;
5073 fast = (param >> 16) & 0x1;
5074 rep_cnt = (param >> 32) & 0xfff;
5075 rep_idx = (param >> 48) & 0xfff;
5076
5077 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5078
c25bc163
GN		 5079 switch (code) {
5080 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5081 kvm_vcpu_on_spin(vcpu);
5082 break;
5083 default:
5084 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5085 break;
5086 }
55cd8e5a
GN		 5087
5088 ret = res | (((u64)rep_done & 0xfff) << 32);
5089 if (longmode) {
5090 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5091 } else {
5092 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5093 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5094 }
5095
5096 return 1;
5097}
5098
8776e519
HB		 5099int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5100{
5101 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 5102 int r = 1;
8776e519 5103
55cd8e5a
GN		 5104 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5105 return kvm_hv_hypercall(vcpu);
5106
5fdbf976
MT		 5107 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5108 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5109 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5110 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5111 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5112
229456fc 5113 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5114
8776e519
HB		 5115 if (!is_long_mode(vcpu)) {
5116 nr &= 0xFFFFFFFF;
5117 a0 &= 0xFFFFFFFF;
5118 a1 &= 0xFFFFFFFF;
5119 a2 &= 0xFFFFFFFF;
5120 a3 &= 0xFFFFFFFF;
5121 }
5122
07708c4a
JK		 5123 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5124 ret = -KVM_EPERM;
5125 goto out;
5126 }
5127
8776e519 5128 switch (nr) {
b93463aa
AK		 5129 case KVM_HC_VAPIC_POLL_IRQ:
5130 ret = 0;
5131 break;
2f333bcb
MT		 5132 case KVM_HC_MMU_OP:
5133 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
5134 break;
8776e519
HB		 5135 default:
5136 ret = -KVM_ENOSYS;
5137 break;
5138 }
07708c4a 5139out:
5fdbf976 5140 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5141 ++vcpu->stat.hypercalls;
2f333bcb 5142 return r;
8776e519
HB		 5143}
5144EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5145
d6aa1000 5146int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5147{
d6aa1000 5148 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5149 char instruction[3];
5fdbf976 5150 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5151
8776e519
HB		 5152 /*
5153 * Blow out the MMU to ensure that no other VCPU has an active mapping
5154 * to ensure that the updated hypercall appears atomically across all
5155 * VCPUs.
5156 */
5157 kvm_mmu_zap_all(vcpu->kvm);
5158
8776e519 5159 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5160
9d74191a 5161 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5162}
5163
07716717
DK		 5164static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
5165{
ad312c7c
ZX		 5166 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
5167 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 5168
5169 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
5170 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 5171 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 5172 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 5173 if (ej->function == e->function) {
5174 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
5175 return j;
5176 }
5177 }
5178 return 0; /* silence gcc, even though control never reaches here */
5179}
5180
5181/* find an entry with matching function, matching index (if needed), and that
5182 * should be read next (if it's stateful) */
5183static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
5184 u32 function, u32 index)
5185{
5186 if (e->function != function)
5187 return 0;
5188 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
5189 return 0;
5190 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 5191 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 5192 return 0;
5193 return 1;
5194}
5195
d8017474
AG		 5196struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
5197 u32 function, u32 index)
8776e519
HB		 5198{
5199 int i;
d8017474 5200 struct kvm_cpuid_entry2 *best = NULL;
8776e519 5201
ad312c7c 5202 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 5203 struct kvm_cpuid_entry2 *e;
5204
ad312c7c 5205 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 5206 if (is_matching_cpuid_entry(e, function, index)) {
5207 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
5208 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 5209 best = e;
5210 break;
5211 }
8776e519 5212 }
d8017474
AG		 5213 return best;
5214}
0e851880 5215EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
d8017474 5216
82725b20
DE		 5217int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
5218{
5219 struct kvm_cpuid_entry2 *best;
5220
f7a71197
AK		 5221 best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0);
5222 if (!best || best->eax < 0x80000008)
5223 goto not_found;
82725b20
DE		 5224 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
5225 if (best)
5226 return best->eax & 0xff;
f7a71197 5227not_found:
82725b20
DE		 5228 return 36;
5229}
5230
bd22f5cf
AP		 5231/*
5232 * If no match is found, check whether we exceed the vCPU's limit
5233 * and return the content of the highest valid _standard_ leaf instead.
5234 * This is to satisfy the CPUID specification.
5235 */
5236static struct kvm_cpuid_entry2* check_cpuid_limit(struct kvm_vcpu *vcpu,
5237 u32 function, u32 index)
5238{
5239 struct kvm_cpuid_entry2 *maxlevel;
5240
5241 maxlevel = kvm_find_cpuid_entry(vcpu, function & 0x80000000, 0);
5242 if (!maxlevel || maxlevel->eax >= function)
5243 return NULL;
5244 if (function & 0x80000000) {
5245 maxlevel = kvm_find_cpuid_entry(vcpu, 0, 0);
5246 if (!maxlevel)
5247 return NULL;
5248 }
5249 return kvm_find_cpuid_entry(vcpu, maxlevel->eax, index);
5250}
5251
d8017474
AG		 5252void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
5253{
5254 u32 function, index;
5255 struct kvm_cpuid_entry2 *best;
5256
5257 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
5258 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5259 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
5260 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
5261 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
5262 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
5263 best = kvm_find_cpuid_entry(vcpu, function, index);
bd22f5cf
AP		 5264
5265 if (!best)
5266 best = check_cpuid_limit(vcpu, function, index);
5267
8776e519 5268 if (best) {
5fdbf976
MT		 5269 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
5270 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
5271 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
5272 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 5273 }
8776e519 5274 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 5275 trace_kvm_cpuid(function,
5276 kvm_register_read(vcpu, VCPU_REGS_RAX),
5277 kvm_register_read(vcpu, VCPU_REGS_RBX),
5278 kvm_register_read(vcpu, VCPU_REGS_RCX),
5279 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 5280}
5281EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 5282
b6c7a5dc
HB		 5283/*
5284 * Check if userspace requested an interrupt window, and that the
5285 * interrupt window is open.
5286 *
5287 * No need to exit to userspace if we already have an interrupt queued.
5288 */
851ba692 5289static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5290{
8061823a 5291 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5292 vcpu->run->request_interrupt_window &&
5df56646 5293 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5294}
5295
851ba692 5296static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5297{
851ba692
AK		 5298 struct kvm_run *kvm_run = vcpu->run;
5299
91586a3b 5300 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5301 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5302 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5303 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5304 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5305 else
b6c7a5dc 5306 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5307 kvm_arch_interrupt_allowed(vcpu) &&
5308 !kvm_cpu_has_interrupt(vcpu) &&
5309 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5310}
5311
b93463aa
AK		 5312static void vapic_enter(struct kvm_vcpu *vcpu)
5313{
5314 struct kvm_lapic *apic = vcpu->arch.apic;
5315 struct page *page;
5316
5317 if (!apic || !apic->vapic_addr)
5318 return;
5319
5320 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 5321
5322 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 5323}
5324
5325static void vapic_exit(struct kvm_vcpu *vcpu)
5326{
5327 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 5328 int idx;
b93463aa
AK		 5329
5330 if (!apic || !apic->vapic_addr)
5331 return;
5332
f656ce01 5333 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 5334 kvm_release_page_dirty(apic->vapic_page);
5335 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 5336 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 5337}
5338
95ba8273
GN		 5339static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5340{
5341 int max_irr, tpr;
5342
5343 if (!kvm_x86_ops->update_cr8_intercept)
5344 return;
5345
88c808fd
AK		 5346 if (!vcpu->arch.apic)
5347 return;
5348
8db3baa2
GN		 5349 if (!vcpu->arch.apic->vapic_addr)
5350 max_irr = kvm_lapic_find_highest_irr(vcpu);
5351 else
5352 max_irr = -1;
95ba8273
GN		 5353
5354 if (max_irr != -1)
5355 max_irr >>= 4;
5356
5357 tpr = kvm_lapic_get_cr8(vcpu);
5358
5359 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5360}
5361
851ba692 5362static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 5363{
5364 /* try to reinject previous events if any */
b59bb7bd 5365 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5366 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5367 vcpu->arch.exception.has_error_code,
5368 vcpu->arch.exception.error_code);
b59bb7bd
GN		 5369 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5370 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5371 vcpu->arch.exception.error_code,
5372 vcpu->arch.exception.reinject);
b59bb7bd
GN		 5373 return;
5374 }
5375
95ba8273
GN		 5376 if (vcpu->arch.nmi_injected) {
5377 kvm_x86_ops->set_nmi(vcpu);
5378 return;
5379 }
5380
5381 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5382 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5383 return;
5384 }
5385
5386 /* try to inject new event if pending */
5387 if (vcpu->arch.nmi_pending) {
5388 if (kvm_x86_ops->nmi_allowed(vcpu)) {
5389 vcpu->arch.nmi_pending = false;
5390 vcpu->arch.nmi_injected = true;
5391 kvm_x86_ops->set_nmi(vcpu);
5392 }
5393 } else if (kvm_cpu_has_interrupt(vcpu)) {
5394 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5395 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5396 false);
5397 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5398 }
5399 }
5400}
5401
2acf923e
DC		 5402static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
5403{
5404 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
5405 !vcpu->guest_xcr0_loaded) {
5406 /* kvm_set_xcr() also depends on this */
5407 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
5408 vcpu->guest_xcr0_loaded = 1;
5409 }
5410}
5411
5412static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
5413{
5414 if (vcpu->guest_xcr0_loaded) {
5415 if (vcpu->arch.xcr0 != host_xcr0)
5416 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
5417 vcpu->guest_xcr0_loaded = 0;
5418 }
5419}
5420
851ba692 5421static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5422{
5423 int r;
1499e54a 5424 bool nmi_pending;
6a8b1d13 5425 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5426 vcpu->run->request_interrupt_window;
b6c7a5dc 5427
3e007509 5428 if (vcpu->requests) {
a8eeb04a 5429 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5430 kvm_mmu_unload(vcpu);
a8eeb04a 5431 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5432 __kvm_migrate_timers(vcpu);
34c238a1
ZA		 5433 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5434 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 5435 if (unlikely(r))
5436 goto out;
5437 }
a8eeb04a 5438 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5439 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5440 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5441 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5442 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5443 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5444 r = 0;
5445 goto out;
5446 }
a8eeb04a 5447 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5448 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5449 r = 0;
5450 goto out;
5451 }
a8eeb04a 5452 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5453 vcpu->fpu_active = 0;
5454 kvm_x86_ops->fpu_deactivate(vcpu);
5455 }
af585b92
GN		 5456 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5457 /* Page is swapped out. Do synthetic halt */
5458 vcpu->arch.apf.halted = true;
5459 r = 1;
5460 goto out;
5461 }
2f52d58c 5462 }
b93463aa 5463
3e007509
AK		 5464 r = kvm_mmu_reload(vcpu);
5465 if (unlikely(r))
5466 goto out;
5467
1499e54a
GN		 5468 /*
5469 * An NMI can be injected between local nmi_pending read and
5470 * vcpu->arch.nmi_pending read inside inject_pending_event().
5471 * But in that case, KVM_REQ_EVENT will be set, which makes
5472 * the race described above benign.
5473 */
5474 nmi_pending = ACCESS_ONCE(vcpu->arch.nmi_pending);
5475
b463a6f7
AK		 5476 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5477 inject_pending_event(vcpu);
5478
5479 /* enable NMI/IRQ window open exits if needed */
1499e54a 5480 if (nmi_pending)
b463a6f7
AK		 5481 kvm_x86_ops->enable_nmi_window(vcpu);
5482 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
5483 kvm_x86_ops->enable_irq_window(vcpu);
5484
5485 if (kvm_lapic_enabled(vcpu)) {
5486 update_cr8_intercept(vcpu);
5487 kvm_lapic_sync_to_vapic(vcpu);
5488 }
5489 }
5490
b6c7a5dc
HB		 5491 preempt_disable();
5492
5493 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 5494 if (vcpu->fpu_active)
5495 kvm_load_guest_fpu(vcpu);
2acf923e 5496 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 5497
6b7e2d09
XG		 5498 vcpu->mode = IN_GUEST_MODE;
5499
5500 /* We should set ->mode before check ->requests,
5501 * see the comment in make_all_cpus_request.
5502 */
5503 smp_mb();
b6c7a5dc 5504
d94e1dc9 5505 local_irq_disable();
32f88400 5506
6b7e2d09 5507 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 5508 || need_resched() || signal_pending(current)) {
6b7e2d09 5509 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5510 smp_wmb();
6c142801
AK		 5511 local_irq_enable();
5512 preempt_enable();
b463a6f7 5513 kvm_x86_ops->cancel_injection(vcpu);
6c142801
AK		 5514 r = 1;
5515 goto out;
5516 }
5517
f656ce01 5518 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 5519
b6c7a5dc
HB		 5520 kvm_guest_enter();
5521
42dbaa5a 5522 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 5523 set_debugreg(0, 7);
5524 set_debugreg(vcpu->arch.eff_db[0], 0);
5525 set_debugreg(vcpu->arch.eff_db[1], 1);
5526 set_debugreg(vcpu->arch.eff_db[2], 2);
5527 set_debugreg(vcpu->arch.eff_db[3], 3);
5528 }
b6c7a5dc 5529
229456fc 5530 trace_kvm_entry(vcpu->vcpu_id);
851ba692 5531 kvm_x86_ops->run(vcpu);
b6c7a5dc 5532
24f1e32c
FW		 5533 /*
5534 * If the guest has used debug registers, at least dr7
5535 * will be disabled while returning to the host.
5536 * If we don't have active breakpoints in the host, we don't
5537 * care about the messed up debug address registers. But if
5538 * we have some of them active, restore the old state.
5539 */
59d8eb53 5540 if (hw_breakpoint_active())
24f1e32c 5541 hw_breakpoint_restore();
42dbaa5a 5542
1d5f066e
ZA		 5543 kvm_get_msr(vcpu, MSR_IA32_TSC, &vcpu->arch.last_guest_tsc);
5544
6b7e2d09 5545 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5546 smp_wmb();
b6c7a5dc
HB		 5547 local_irq_enable();
5548
5549 ++vcpu->stat.exits;
5550
5551 /*
5552 * We must have an instruction between local_irq_enable() and
5553 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5554 * the interrupt shadow. The stat.exits increment will do nicely.
5555 * But we need to prevent reordering, hence this barrier():
5556 */
5557 barrier();
5558
5559 kvm_guest_exit();
5560
5561 preempt_enable();
5562
f656ce01 5563 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 5564
b6c7a5dc
HB		 5565 /*
5566 * Profile KVM exit RIPs:
5567 */
5568 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 5569 unsigned long rip = kvm_rip_read(vcpu);
5570 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 5571 }
5572
298101da 5573
b93463aa
AK		 5574 kvm_lapic_sync_from_vapic(vcpu);
5575
851ba692 5576 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 5577out:
5578 return r;
5579}
b6c7a5dc 5580
09cec754 5581
851ba692 5582static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 5583{
5584 int r;
f656ce01 5585 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 5586
5587 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 5588 pr_debug("vcpu %d received sipi with vector # %x\n",
5589 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 5590 kvm_lapic_reset(vcpu);
5f179287 5591 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 5592 if (r)
5593 return r;
5594 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 5595 }
5596
f656ce01 5597 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 5598 vapic_enter(vcpu);
5599
5600 r = 1;
5601 while (r > 0) {
af585b92
GN		 5602 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
5603 !vcpu->arch.apf.halted)
851ba692 5604 r = vcpu_enter_guest(vcpu);
d7690175 5605 else {
f656ce01 5606 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 5607 kvm_vcpu_block(vcpu);
f656ce01 5608 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
a8eeb04a 5609 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
09cec754
GN		 5610 {
5611 switch(vcpu->arch.mp_state) {
5612 case KVM_MP_STATE_HALTED:
d7690175 5613 vcpu->arch.mp_state =
09cec754
GN		 5614 KVM_MP_STATE_RUNNABLE;
5615 case KVM_MP_STATE_RUNNABLE:
af585b92 5616 vcpu->arch.apf.halted = false;
09cec754
GN		 5617 break;
5618 case KVM_MP_STATE_SIPI_RECEIVED:
5619 default:
5620 r = -EINTR;
5621 break;
5622 }
5623 }
d7690175
MT		 5624 }
5625
09cec754
GN		 5626 if (r <= 0)
5627 break;
5628
5629 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5630 if (kvm_cpu_has_pending_timer(vcpu))
5631 kvm_inject_pending_timer_irqs(vcpu);
5632
851ba692 5633 if (dm_request_for_irq_injection(vcpu)) {
09cec754 5634 r = -EINTR;
851ba692 5635 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5636 ++vcpu->stat.request_irq_exits;
5637 }
af585b92
GN		 5638
5639 kvm_check_async_pf_completion(vcpu);
5640
09cec754
GN		 5641 if (signal_pending(current)) {
5642 r = -EINTR;
851ba692 5643 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5644 ++vcpu->stat.signal_exits;
5645 }
5646 if (need_resched()) {
f656ce01 5647 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 5648 kvm_resched(vcpu);
f656ce01 5649 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 5650 }
b6c7a5dc
HB		 5651 }
5652
f656ce01 5653 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 5654
b93463aa
AK		 5655 vapic_exit(vcpu);
5656
b6c7a5dc
HB		 5657 return r;
5658}
5659
5287f194
AK		 5660static int complete_mmio(struct kvm_vcpu *vcpu)
5661{
5662 struct kvm_run *run = vcpu->run;
5663 int r;
5664
5665 if (!(vcpu->arch.pio.count || vcpu->mmio_needed))
5666 return 1;
5667
5668 if (vcpu->mmio_needed) {
5287f194 5669 vcpu->mmio_needed = 0;
cef4dea0 5670 if (!vcpu->mmio_is_write)
0004c7c2
GN		 5671 memcpy(vcpu->mmio_data + vcpu->mmio_index,
5672 run->mmio.data, 8);
cef4dea0
AK		 5673 vcpu->mmio_index += 8;
5674 if (vcpu->mmio_index < vcpu->mmio_size) {
5675 run->exit_reason = KVM_EXIT_MMIO;
5676 run->mmio.phys_addr = vcpu->mmio_phys_addr + vcpu->mmio_index;
5677 memcpy(run->mmio.data, vcpu->mmio_data + vcpu->mmio_index, 8);
5678 run->mmio.len = min(vcpu->mmio_size - vcpu->mmio_index, 8);
5679 run->mmio.is_write = vcpu->mmio_is_write;
5680 vcpu->mmio_needed = 1;
5681 return 0;
5682 }
5683 if (vcpu->mmio_is_write)
5684 return 1;
5685 vcpu->mmio_read_completed = 1;
5287f194
AK		 5686 }
5687 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5688 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
5689 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5690 if (r != EMULATE_DONE)
5691 return 0;
5692 return 1;
5693}
5694
b6c7a5dc
HB		 5695int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
5696{
5697 int r;
5698 sigset_t sigsaved;
5699
e5c30142
AK		 5700 if (!tsk_used_math(current) && init_fpu(current))
5701 return -ENOMEM;
5702
ac9f6dc0
AK		 5703 if (vcpu->sigset_active)
5704 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
5705
a4535290 5706 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 5707 kvm_vcpu_block(vcpu);
d7690175 5708 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 5709 r = -EAGAIN;
5710 goto out;
b6c7a5dc
HB		 5711 }
5712
b6c7a5dc 5713 /* re-sync apic's tpr */
eea1cff9
AP		 5714 if (!irqchip_in_kernel(vcpu->kvm)) {
5715 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
5716 r = -EINVAL;
5717 goto out;
5718 }
5719 }
b6c7a5dc 5720
5287f194
AK		 5721 r = complete_mmio(vcpu);
5722 if (r <= 0)
5723 goto out;
5724
5fdbf976
MT		 5725 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
5726 kvm_register_write(vcpu, VCPU_REGS_RAX,
5727 kvm_run->hypercall.ret);
b6c7a5dc 5728
851ba692 5729 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 5730
5731out:
f1d86e46 5732 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 5733 if (vcpu->sigset_active)
5734 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
5735
b6c7a5dc
HB		 5736 return r;
5737}
5738
5739int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5740{
7ae441ea
GN		 5741 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
5742 /*
5743 * We are here if userspace calls get_regs() in the middle of
5744 * instruction emulation. Registers state needs to be copied
5745 * back from emulation context to vcpu. Usrapace shouldn't do
5746 * that usually, but some bad designed PV devices (vmware
5747 * backdoor interface) need this to work
5748 */
9dac77fa
AK		 5749 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5750 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
7ae441ea
GN		 5751 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5752 }
5fdbf976
MT		 5753 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5754 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5755 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5756 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5757 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
5758 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
5759 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5760 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 5761#ifdef CONFIG_X86_64
5fdbf976
MT		 5762 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
5763 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
5764 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
5765 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
5766 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
5767 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
5768 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
5769 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 5770#endif
5771
5fdbf976 5772 regs->rip = kvm_rip_read(vcpu);
91586a3b 5773 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 5774
b6c7a5dc
HB		 5775 return 0;
5776}
5777
5778int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5779{
7ae441ea
GN		 5780 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
5781 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5782
5fdbf976
MT		 5783 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
5784 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
5785 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
5786 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
5787 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
5788 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
5789 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
5790 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 5791#ifdef CONFIG_X86_64
5fdbf976
MT		 5792 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
5793 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
5794 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
5795 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
5796 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
5797 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
5798 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
5799 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 5800#endif
5801
5fdbf976 5802 kvm_rip_write(vcpu, regs->rip);
91586a3b 5803 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 5804
b4f14abd
JK		 5805 vcpu->arch.exception.pending = false;
5806
3842d135
AK		 5807 kvm_make_request(KVM_REQ_EVENT, vcpu);
5808
b6c7a5dc
HB		 5809 return 0;
5810}
5811
b6c7a5dc
HB		 5812void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5813{
5814 struct kvm_segment cs;
5815
3e6e0aab 5816 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 5817 *db = cs.db;
5818 *l = cs.l;
5819}
5820EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
5821
5822int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
5823 struct kvm_sregs *sregs)
5824{
89a27f4d 5825 struct desc_ptr dt;
b6c7a5dc 5826
3e6e0aab
GT		 5827 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5828 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5829 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5830 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5831 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5832 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5833
3e6e0aab
GT		 5834 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5835 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 5836
5837 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 5838 sregs->idt.limit = dt.size;
5839 sregs->idt.base = dt.address;
b6c7a5dc 5840 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 5841 sregs->gdt.limit = dt.size;
5842 sregs->gdt.base = dt.address;
b6c7a5dc 5843
4d4ec087 5844 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 5845 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 5846 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 5847 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 5848 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 5849 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 5850 sregs->apic_base = kvm_get_apic_base(vcpu);
5851
923c61bb 5852 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 5853
36752c9b 5854 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 5855 set_bit(vcpu->arch.interrupt.nr,
5856 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 5857
b6c7a5dc
HB		 5858 return 0;
5859}
5860
62d9f0db
MT		 5861int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
5862 struct kvm_mp_state *mp_state)
5863{
62d9f0db 5864 mp_state->mp_state = vcpu->arch.mp_state;
62d9f0db
MT		 5865 return 0;
5866}
5867
5868int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
5869 struct kvm_mp_state *mp_state)
5870{
62d9f0db 5871 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 5872 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 5873 return 0;
5874}
5875
e269fb21
JK		 5876int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason,
5877 bool has_error_code, u32 error_code)
b6c7a5dc 5878{
9d74191a 5879 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 5880 int ret;
e01c2426 5881
8ec4722d 5882 init_emulate_ctxt(vcpu);
c697518a 5883
9d74191a
TY		 5884 ret = emulator_task_switch(ctxt, tss_selector, reason,
5885 has_error_code, error_code);
c697518a 5886
c697518a 5887 if (ret)
19d04437 5888 return EMULATE_FAIL;
37817f29 5889
9dac77fa 5890 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
9d74191a
TY		 5891 kvm_rip_write(vcpu, ctxt->eip);
5892 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 5893 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 5894 return EMULATE_DONE;
37817f29
IE		 5895}
5896EXPORT_SYMBOL_GPL(kvm_task_switch);
5897
b6c7a5dc
HB		 5898int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5899 struct kvm_sregs *sregs)
5900{
5901 int mmu_reset_needed = 0;
63f42e02 5902 int pending_vec, max_bits, idx;
89a27f4d 5903 struct desc_ptr dt;
b6c7a5dc 5904
89a27f4d
GN		 5905 dt.size = sregs->idt.limit;
5906 dt.address = sregs->idt.base;
b6c7a5dc 5907 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 5908 dt.size = sregs->gdt.limit;
5909 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 5910 kvm_x86_ops->set_gdt(vcpu, &dt);
5911
ad312c7c 5912 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 5913 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 5914 vcpu->arch.cr3 = sregs->cr3;
aff48baa 5915 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 5916
2d3ad1f4 5917 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 5918
f6801dff 5919 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 5920 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 5921 kvm_set_apic_base(vcpu, sregs->apic_base);
5922
4d4ec087 5923 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 5924 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 5925 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 5926
fc78f519 5927 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 5928 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c
SY		 5929 if (sregs->cr4 & X86_CR4_OSXSAVE)
5930 update_cpuid(vcpu);
63f42e02
XG		 5931
5932 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 5933 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 5934 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 5935 mmu_reset_needed = 1;
5936 }
63f42e02 5937 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 5938
5939 if (mmu_reset_needed)
5940 kvm_mmu_reset_context(vcpu);
5941
923c61bb
GN		 5942 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5943 pending_vec = find_first_bit(
5944 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5945 if (pending_vec < max_bits) {
66fd3f7f 5946 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 5947 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 5948 }
5949
3e6e0aab
GT		 5950 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5951 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5952 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5953 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5954 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5955 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5956
3e6e0aab
GT		 5957 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5958 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 5959
5f0269f5
ME		 5960 update_cr8_intercept(vcpu);
5961
9c3e4aab 5962 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 5963 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 5964 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 5965 !is_protmode(vcpu))
9c3e4aab
MT		 5966 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5967
3842d135
AK		 5968 kvm_make_request(KVM_REQ_EVENT, vcpu);
5969
b6c7a5dc
HB		 5970 return 0;
5971}
5972
d0bfb940
JK		 5973int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5974 struct kvm_guest_debug *dbg)
b6c7a5dc 5975{
355be0b9 5976 unsigned long rflags;
ae675ef0 5977 int i, r;
b6c7a5dc 5978
4f926bf2
JK		 5979 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5980 r = -EBUSY;
5981 if (vcpu->arch.exception.pending)
2122ff5e 5982 goto out;
4f926bf2
JK		 5983 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5984 kvm_queue_exception(vcpu, DB_VECTOR);
5985 else
5986 kvm_queue_exception(vcpu, BP_VECTOR);
5987 }
5988
91586a3b
JK		 5989 /*
5990 * Read rflags as long as potentially injected trace flags are still
5991 * filtered out.
5992 */
5993 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 5994
5995 vcpu->guest_debug = dbg->control;
5996 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5997 vcpu->guest_debug = 0;
5998
5999 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 6000 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6001 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
6002 vcpu->arch.switch_db_regs =
6003 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
6004 } else {
6005 for (i = 0; i < KVM_NR_DB_REGS; i++)
6006 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6007 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
6008 }
6009
f92653ee
JK		 6010 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6011 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6012 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 6013
91586a3b
JK		 6014 /*
6015 * Trigger an rflags update that will inject or remove the trace
6016 * flags.
6017 */
6018 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 6019
355be0b9 6020 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 6021
4f926bf2 6022 r = 0;
d0bfb940 6023
2122ff5e 6024out:
b6c7a5dc
HB		 6025
6026 return r;
6027}
6028
8b006791
ZX		 6029/*
6030 * Translate a guest virtual address to a guest physical address.
6031 */
6032int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6033 struct kvm_translation *tr)
6034{
6035 unsigned long vaddr = tr->linear_address;
6036 gpa_t gpa;
f656ce01 6037 int idx;
8b006791 6038
f656ce01 6039 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 6040 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 6041 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 6042 tr->physical_address = gpa;
6043 tr->valid = gpa != UNMAPPED_GVA;
6044 tr->writeable = 1;
6045 tr->usermode = 0;
8b006791
ZX		 6046
6047 return 0;
6048}
6049
d0752060
HB		 6050int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6051{
98918833
SY		 6052 struct i387_fxsave_struct *fxsave =
6053 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6054
d0752060
HB		 6055 memcpy(fpu->fpr, fxsave->st_space, 128);
6056 fpu->fcw = fxsave->cwd;
6057 fpu->fsw = fxsave->swd;
6058 fpu->ftwx = fxsave->twd;
6059 fpu->last_opcode = fxsave->fop;
6060 fpu->last_ip = fxsave->rip;
6061 fpu->last_dp = fxsave->rdp;
6062 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6063
d0752060
HB		 6064 return 0;
6065}
6066
6067int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6068{
98918833
SY		 6069 struct i387_fxsave_struct *fxsave =
6070 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6071
d0752060
HB		 6072 memcpy(fxsave->st_space, fpu->fpr, 128);
6073 fxsave->cwd = fpu->fcw;
6074 fxsave->swd = fpu->fsw;
6075 fxsave->twd = fpu->ftwx;
6076 fxsave->fop = fpu->last_opcode;
6077 fxsave->rip = fpu->last_ip;
6078 fxsave->rdp = fpu->last_dp;
6079 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6080
d0752060
HB		 6081 return 0;
6082}
6083
10ab25cd 6084int fx_init(struct kvm_vcpu *vcpu)
d0752060 6085{
10ab25cd
JK		 6086 int err;
6087
6088 err = fpu_alloc(&vcpu->arch.guest_fpu);
6089 if (err)
6090 return err;
6091
98918833 6092 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 6093
2acf923e
DC		 6094 /*
6095 * Ensure guest xcr0 is valid for loading
6096 */
6097 vcpu->arch.xcr0 = XSTATE_FP;
6098
ad312c7c 6099 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 6100
6101 return 0;
d0752060
HB		 6102}
6103EXPORT_SYMBOL_GPL(fx_init);
6104
98918833
SY		 6105static void fx_free(struct kvm_vcpu *vcpu)
6106{
6107 fpu_free(&vcpu->arch.guest_fpu);
6108}
6109
d0752060
HB		 6110void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6111{
2608d7a1 6112 if (vcpu->guest_fpu_loaded)
d0752060
HB		 6113 return;
6114
2acf923e
DC		 6115 /*
6116 * Restore all possible states in the guest,
6117 * and assume host would use all available bits.
6118 * Guest xcr0 would be loaded later.
6119 */
6120 kvm_put_guest_xcr0(vcpu);
d0752060 6121 vcpu->guest_fpu_loaded = 1;
7cf30855 6122 unlazy_fpu(current);
98918833 6123 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 6124 trace_kvm_fpu(1);
d0752060 6125}
d0752060
HB		 6126
6127void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6128{
2acf923e
DC		 6129 kvm_put_guest_xcr0(vcpu);
6130
d0752060
HB		 6131 if (!vcpu->guest_fpu_loaded)
6132 return;
6133
6134 vcpu->guest_fpu_loaded = 0;
98918833 6135 fpu_save_init(&vcpu->arch.guest_fpu);
f096ed85 6136 ++vcpu->stat.fpu_reload;
a8eeb04a 6137 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 6138 trace_kvm_fpu(0);
d0752060 6139}
e9b11c17
ZX		 6140
6141void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6142{
12f9a48f 6143 kvmclock_reset(vcpu);
7f1ea208 6144
f5f48ee1 6145 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 6146 fx_free(vcpu);
e9b11c17
ZX		 6147 kvm_x86_ops->vcpu_free(vcpu);
6148}
6149
6150struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6151 unsigned int id)
6152{
6755bae8
ZA		 6153 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6154 printk_once(KERN_WARNING
6155 "kvm: SMP vm created on host with unstable TSC; "
6156 "guest TSC will not be reliable\n");
26e5215f
AK		 6157 return kvm_x86_ops->vcpu_create(kvm, id);
6158}
e9b11c17 6159
26e5215f
AK		 6160int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6161{
6162 int r;
e9b11c17 6163
0bed3b56 6164 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 6165 vcpu_load(vcpu);
6166 r = kvm_arch_vcpu_reset(vcpu);
6167 if (r == 0)
6168 r = kvm_mmu_setup(vcpu);
6169 vcpu_put(vcpu);
e9b11c17 6170
26e5215f 6171 return r;
e9b11c17
ZX		 6172}
6173
d40ccc62 6174void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 6175{
344d9588
GN		 6176 vcpu->arch.apf.msr_val = 0;
6177
e9b11c17
ZX		 6178 vcpu_load(vcpu);
6179 kvm_mmu_unload(vcpu);
6180 vcpu_put(vcpu);
6181
98918833 6182 fx_free(vcpu);
e9b11c17
ZX		 6183 kvm_x86_ops->vcpu_free(vcpu);
6184}
6185
6186int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
6187{
448fa4a9
JK		 6188 vcpu->arch.nmi_pending = false;
6189 vcpu->arch.nmi_injected = false;
6190
42dbaa5a
JK		 6191 vcpu->arch.switch_db_regs = 0;
6192 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6193 vcpu->arch.dr6 = DR6_FIXED_1;
6194 vcpu->arch.dr7 = DR7_FIXED_1;
6195
3842d135 6196 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 6197 vcpu->arch.apf.msr_val = 0;
3842d135 6198
12f9a48f
GC		 6199 kvmclock_reset(vcpu);
6200
af585b92
GN		 6201 kvm_clear_async_pf_completion_queue(vcpu);
6202 kvm_async_pf_hash_reset(vcpu);
6203 vcpu->arch.apf.halted = false;
3842d135 6204
e9b11c17
ZX		 6205 return kvm_x86_ops->vcpu_reset(vcpu);
6206}
6207
10474ae8 6208int kvm_arch_hardware_enable(void *garbage)
e9b11c17 6209{
ca84d1a2
ZA		 6210 struct kvm *kvm;
6211 struct kvm_vcpu *vcpu;
6212 int i;
18863bdd
AK		 6213
6214 kvm_shared_msr_cpu_online();
ca84d1a2
ZA		 6215 list_for_each_entry(kvm, &vm_list, vm_list)
6216 kvm_for_each_vcpu(i, vcpu, kvm)
6217 if (vcpu->cpu == smp_processor_id())
c285545f 6218 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
10474ae8 6219 return kvm_x86_ops->hardware_enable(garbage);
e9b11c17
ZX		 6220}
6221
6222void kvm_arch_hardware_disable(void *garbage)
6223{
6224 kvm_x86_ops->hardware_disable(garbage);
3548bab5 6225 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 6226}
6227
6228int kvm_arch_hardware_setup(void)
6229{
6230 return kvm_x86_ops->hardware_setup();
6231}
6232
6233void kvm_arch_hardware_unsetup(void)
6234{
6235 kvm_x86_ops->hardware_unsetup();
6236}
6237
6238void kvm_arch_check_processor_compat(void *rtn)
6239{
6240 kvm_x86_ops->check_processor_compatibility(rtn);
6241}
6242
6243int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6244{
6245 struct page *page;
6246 struct kvm *kvm;
6247 int r;
6248
6249 BUG_ON(vcpu->kvm == NULL);
6250 kvm = vcpu->kvm;
6251
9aabc88f 6252 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
14dfe855 6253 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
ad312c7c 6254 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c30a358d 6255 vcpu->arch.mmu.translate_gpa = translate_gpa;
02f59dc9 6256 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
c5af89b6 6257 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 6258 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 6259 else
a4535290 6260 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 6261
6262 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6263 if (!page) {
6264 r = -ENOMEM;
6265 goto fail;
6266 }
ad312c7c 6267 vcpu->arch.pio_data = page_address(page);
e9b11c17 6268
1e993611 6269 kvm_init_tsc_catchup(vcpu, max_tsc_khz);
c285545f 6270
e9b11c17
ZX		 6271 r = kvm_mmu_create(vcpu);
6272 if (r < 0)
6273 goto fail_free_pio_data;
6274
6275 if (irqchip_in_kernel(kvm)) {
6276 r = kvm_create_lapic(vcpu);
6277 if (r < 0)
6278 goto fail_mmu_destroy;
6279 }
6280
890ca9ae
HY		 6281 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6282 GFP_KERNEL);
6283 if (!vcpu->arch.mce_banks) {
6284 r = -ENOMEM;
443c39bc 6285 goto fail_free_lapic;
890ca9ae
HY		 6286 }
6287 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6288
f5f48ee1
SY		 6289 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
6290 goto fail_free_mce_banks;
6291
af585b92
GN		 6292 kvm_async_pf_hash_reset(vcpu);
6293
e9b11c17 6294 return 0;
f5f48ee1
SY		 6295fail_free_mce_banks:
6296 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 6297fail_free_lapic:
6298 kvm_free_lapic(vcpu);
e9b11c17
ZX		 6299fail_mmu_destroy:
6300 kvm_mmu_destroy(vcpu);
6301fail_free_pio_data:
ad312c7c 6302 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 6303fail:
6304 return r;
6305}
6306
6307void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6308{
f656ce01
MT		 6309 int idx;
6310
36cb93fd 6311 kfree(vcpu->arch.mce_banks);
e9b11c17 6312 kvm_free_lapic(vcpu);
f656ce01 6313 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 6314 kvm_mmu_destroy(vcpu);
f656ce01 6315 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 6316 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 6317}
d19a9cd2 6318
d89f5eff 6319int kvm_arch_init_vm(struct kvm *kvm)
d19a9cd2 6320{
f05e70ac 6321 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 6322 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 6323
5550af4d
SY		 6324 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
6325 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
6326
038f8c11 6327 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
53f658b3 6328
d89f5eff 6329 return 0;
d19a9cd2
ZX		 6330}
6331
6332static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
6333{
6334 vcpu_load(vcpu);
6335 kvm_mmu_unload(vcpu);
6336 vcpu_put(vcpu);
6337}
6338
6339static void kvm_free_vcpus(struct kvm *kvm)
6340{
6341 unsigned int i;
988a2cae 6342 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 6343
6344 /*
6345 * Unpin any mmu pages first.
6346 */
af585b92
GN		 6347 kvm_for_each_vcpu(i, vcpu, kvm) {
6348 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 6349 kvm_unload_vcpu_mmu(vcpu);
af585b92 6350 }
988a2cae
GN		 6351 kvm_for_each_vcpu(i, vcpu, kvm)
6352 kvm_arch_vcpu_free(vcpu);
6353
6354 mutex_lock(&kvm->lock);
6355 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
6356 kvm->vcpus[i] = NULL;
d19a9cd2 6357
988a2cae
GN		 6358 atomic_set(&kvm->online_vcpus, 0);
6359 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 6360}
6361
ad8ba2cd
SY		 6362void kvm_arch_sync_events(struct kvm *kvm)
6363{
ba4cef31 6364 kvm_free_all_assigned_devices(kvm);
aea924f6 6365 kvm_free_pit(kvm);
ad8ba2cd
SY		 6366}
6367
d19a9cd2
ZX		 6368void kvm_arch_destroy_vm(struct kvm *kvm)
6369{
6eb55818 6370 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 6371 kfree(kvm->arch.vpic);
6372 kfree(kvm->arch.vioapic);
d19a9cd2 6373 kvm_free_vcpus(kvm);
3d45830c
AK		 6374 if (kvm->arch.apic_access_page)
6375 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 6376 if (kvm->arch.ept_identity_pagetable)
6377 put_page(kvm->arch.ept_identity_pagetable);
d19a9cd2 6378}
0de10343 6379
f7784b8e
MT		 6380int kvm_arch_prepare_memory_region(struct kvm *kvm,
6381 struct kvm_memory_slot *memslot,
0de10343 6382 struct kvm_memory_slot old,
f7784b8e 6383 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 6384 int user_alloc)
6385{
f7784b8e 6386 int npages = memslot->npages;
7ac77099
AK		 6387 int map_flags = MAP_PRIVATE | MAP_ANONYMOUS;
6388
6389 /* Prevent internal slot pages from being moved by fork()/COW. */
6390 if (memslot->id >= KVM_MEMORY_SLOTS)
6391 map_flags = MAP_SHARED | MAP_ANONYMOUS;
0de10343
ZX		 6392
6393 /*To keep backward compatibility with older userspace,
6394 *x86 needs to hanlde !user_alloc case.
6395 */
6396 if (!user_alloc) {
6397 if (npages && !old.rmap) {
604b38ac
AA		 6398 unsigned long userspace_addr;
6399
72dc67a6 6400 down_write(&current->mm->mmap_sem);
604b38ac
AA		 6401 userspace_addr = do_mmap(NULL, 0,
6402 npages * PAGE_SIZE,
6403 PROT_READ | PROT_WRITE,
7ac77099 6404 map_flags,
604b38ac 6405 0);
72dc67a6 6406 up_write(&current->mm->mmap_sem);
0de10343 6407
604b38ac
AA		 6408 if (IS_ERR((void *)userspace_addr))
6409 return PTR_ERR((void *)userspace_addr);
6410
604b38ac 6411 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 6412 }
6413 }
6414
f7784b8e
MT		 6415
6416 return 0;
6417}
6418
6419void kvm_arch_commit_memory_region(struct kvm *kvm,
6420 struct kvm_userspace_memory_region *mem,
6421 struct kvm_memory_slot old,
6422 int user_alloc)
6423{
6424
48c0e4e9 6425 int nr_mmu_pages = 0, npages = mem->memory_size >> PAGE_SHIFT;
f7784b8e
MT		 6426
6427 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
6428 int ret;
6429
6430 down_write(&current->mm->mmap_sem);
6431 ret = do_munmap(current->mm, old.userspace_addr,
6432 old.npages * PAGE_SIZE);
6433 up_write(&current->mm->mmap_sem);
6434 if (ret < 0)
6435 printk(KERN_WARNING
6436 "kvm_vm_ioctl_set_memory_region: "
6437 "failed to munmap memory\n");
6438 }
6439
48c0e4e9
XG		 6440 if (!kvm->arch.n_requested_mmu_pages)
6441 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
6442
7c8a83b7 6443 spin_lock(&kvm->mmu_lock);
48c0e4e9 6444 if (nr_mmu_pages)
0de10343 6445 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
0de10343 6446 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 6447 spin_unlock(&kvm->mmu_lock);
0de10343 6448}
1d737c8a 6449
34d4cb8f
MT		 6450void kvm_arch_flush_shadow(struct kvm *kvm)
6451{
6452 kvm_mmu_zap_all(kvm);
8986ecc0 6453 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 6454}
6455
1d737c8a
ZX		 6456int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
6457{
af585b92
GN		 6458 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6459 !vcpu->arch.apf.halted)
6460 || !list_empty_careful(&vcpu->async_pf.done)
a1b37100
GN		 6461 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
6462 || vcpu->arch.nmi_pending ||
6463 (kvm_arch_interrupt_allowed(vcpu) &&
6464 kvm_cpu_has_interrupt(vcpu));
1d737c8a 6465}
5736199a 6466
5736199a
ZX		 6467void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
6468{
32f88400
MT		 6469 int me;
6470 int cpu = vcpu->cpu;
5736199a
ZX		 6471
6472 if (waitqueue_active(&vcpu->wq)) {
6473 wake_up_interruptible(&vcpu->wq);
6474 ++vcpu->stat.halt_wakeup;
6475 }
32f88400
MT		 6476
6477 me = get_cpu();
6478 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
6b7e2d09 6479 if (kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE)
32f88400 6480 smp_send_reschedule(cpu);
e9571ed5 6481 put_cpu();
5736199a 6482}
78646121
GN		 6483
6484int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
6485{
6486 return kvm_x86_ops->interrupt_allowed(vcpu);
6487}
229456fc 6488
f92653ee
JK		 6489bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
6490{
6491 unsigned long current_rip = kvm_rip_read(vcpu) +
6492 get_segment_base(vcpu, VCPU_SREG_CS);
6493
6494 return current_rip == linear_rip;
6495}
6496EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
6497
94fe45da
JK		 6498unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
6499{
6500 unsigned long rflags;
6501
6502 rflags = kvm_x86_ops->get_rflags(vcpu);
6503 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 6504 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 6505 return rflags;
6506}
6507EXPORT_SYMBOL_GPL(kvm_get_rflags);
6508
6509void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
6510{
6511 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 6512 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 6513 rflags |= X86_EFLAGS_TF;
94fe45da 6514 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 6515 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 6516}
6517EXPORT_SYMBOL_GPL(kvm_set_rflags);
6518
56028d08
GN		 6519void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
6520{
6521 int r;
6522
fb67e14f 6523 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
c4806acd 6524 is_error_page(work->page))
56028d08
GN		 6525 return;
6526
6527 r = kvm_mmu_reload(vcpu);
6528 if (unlikely(r))
6529 return;
6530
fb67e14f
XG		 6531 if (!vcpu->arch.mmu.direct_map &&
6532 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
6533 return;
6534
56028d08
GN		 6535 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
6536}
6537
af585b92
GN		 6538static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
6539{
6540 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
6541}
6542
6543static inline u32 kvm_async_pf_next_probe(u32 key)
6544{
6545 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
6546}
6547
6548static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6549{
6550 u32 key = kvm_async_pf_hash_fn(gfn);
6551
6552 while (vcpu->arch.apf.gfns[key] != ~0)
6553 key = kvm_async_pf_next_probe(key);
6554
6555 vcpu->arch.apf.gfns[key] = gfn;
6556}
6557
6558static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
6559{
6560 int i;
6561 u32 key = kvm_async_pf_hash_fn(gfn);
6562
6563 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 6564 (vcpu->arch.apf.gfns[key] != gfn &&
6565 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 6566 key = kvm_async_pf_next_probe(key);
6567
6568 return key;
6569}
6570
6571bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6572{
6573 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
6574}
6575
6576static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6577{
6578 u32 i, j, k;
6579
6580 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
6581 while (true) {
6582 vcpu->arch.apf.gfns[i] = ~0;
6583 do {
6584 j = kvm_async_pf_next_probe(j);
6585 if (vcpu->arch.apf.gfns[j] == ~0)
6586 return;
6587 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
6588 /*
6589 * k lies cyclically in ]i,j]
6590 * | i.k.j |
6591 * |....j i.k.| or |.k..j i...|
6592 */
6593 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
6594 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
6595 i = j;
6596 }
6597}
6598
7c90705b
GN		 6599static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
6600{
6601
6602 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
6603 sizeof(val));
6604}
6605
af585b92
GN		 6606void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
6607 struct kvm_async_pf *work)
6608{
6389ee94
AK		 6609 struct x86_exception fault;
6610
7c90705b 6611 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 6612 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 6613
6614 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 6615 (vcpu->arch.apf.send_user_only &&
6616 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 6617 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
6618 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 6619 fault.vector = PF_VECTOR;
6620 fault.error_code_valid = true;
6621 fault.error_code = 0;
6622 fault.nested_page_fault = false;
6623 fault.address = work->arch.token;
6624 kvm_inject_page_fault(vcpu, &fault);
7c90705b 6625 }
af585b92
GN		 6626}
6627
6628void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
6629 struct kvm_async_pf *work)
6630{
6389ee94
AK		 6631 struct x86_exception fault;
6632
7c90705b
GN		 6633 trace_kvm_async_pf_ready(work->arch.token, work->gva);
6634 if (is_error_page(work->page))
6635 work->arch.token = ~0; /* broadcast wakeup */
6636 else
6637 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
6638
6639 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
6640 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 6641 fault.vector = PF_VECTOR;
6642 fault.error_code_valid = true;
6643 fault.error_code = 0;
6644 fault.nested_page_fault = false;
6645 fault.address = work->arch.token;
6646 kvm_inject_page_fault(vcpu, &fault);
7c90705b 6647 }
e6d53e3b 6648 vcpu->arch.apf.halted = false;
7c90705b
GN		 6649}
6650
6651bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
6652{
6653 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
6654 return true;
6655 else
6656 return !kvm_event_needs_reinjection(vcpu) &&
6657 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 6658}
6659
229456fc
MT		 6660EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
6661EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
6662EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
6663EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
6664EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 6665EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 6666EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 6667EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 6668EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 6669EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 6670EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 6671EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
kernel source for telekom puls (alcatel/mediatek)