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KVM: Fix KVM_ASSIGN_SET_MSIX_ENTRY documentation
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
313a3dc7 29
18068523 30#include <linux/clocksource.h>
4d5c5d0f 31#include <linux/interrupt.h>
313a3dc7
CO		 32#include <linux/kvm.h>
33#include <linux/fs.h>
34#include <linux/vmalloc.h>
5fb76f9b 35#include <linux/module.h>
0de10343 36#include <linux/mman.h>
2bacc55c 37#include <linux/highmem.h>
19de40a8 38#include <linux/iommu.h>
62c476c7 39#include <linux/intel-iommu.h>
c8076604 40#include <linux/cpufreq.h>
18863bdd 41#include <linux/user-return-notifier.h>
a983fb23 42#include <linux/srcu.h>
5a0e3ad6 43#include <linux/slab.h>
ff9d07a0 44#include <linux/perf_event.h>
7bee342a 45#include <linux/uaccess.h>
af585b92 46#include <linux/hash.h>
aec51dc4 47#include <trace/events/kvm.h>
2ed152af 48
229456fc
MT		 49#define CREATE_TRACE_POINTS
50#include "trace.h"
043405e1 51
24f1e32c 52#include <asm/debugreg.h>
d825ed0a 53#include <asm/msr.h>
a5f61300 54#include <asm/desc.h>
0bed3b56 55#include <asm/mtrr.h>
890ca9ae 56#include <asm/mce.h>
7cf30855 57#include <asm/i387.h>
98918833 58#include <asm/xcr.h>
1d5f066e 59#include <asm/pvclock.h>
217fc9cf 60#include <asm/div64.h>
043405e1 61
313a3dc7 62#define MAX_IO_MSRS 256
890ca9ae 63#define KVM_MAX_MCE_BANKS 32
5854dbca 64#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 65
0f65dd70
AK		 66#define emul_to_vcpu(ctxt) \
67 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
68
50a37eb4
JR		 69/* EFER defaults:
70 * - enable syscall per default because its emulated by KVM
71 * - enable LME and LMA per default on 64 bit KVM
72 */
73#ifdef CONFIG_X86_64
1260edbe
LJ		 74static
75u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 76#else
1260edbe 77static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 78#endif
313a3dc7 79
ba1389b7
AK		 80#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
81#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 82
cb142eb7 83static void update_cr8_intercept(struct kvm_vcpu *vcpu);
674eea0f
AK		 84static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
85 struct kvm_cpuid_entry2 __user *entries);
86
97896d04 87struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 88EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 89
ed85c068
AP		 90int ignore_msrs = 0;
91module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
92
92a1f12d
JR		 93bool kvm_has_tsc_control;
94EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
95u32 kvm_max_guest_tsc_khz;
96EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
97
18863bdd
AK		 98#define KVM_NR_SHARED_MSRS 16
99
100struct kvm_shared_msrs_global {
101 int nr;
2bf78fa7 102 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 103};
104
105struct kvm_shared_msrs {
106 struct user_return_notifier urn;
107 bool registered;
2bf78fa7
SY		 108 struct kvm_shared_msr_values {
109 u64 host;
110 u64 curr;
111 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 112};
113
114static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
115static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
116
417bc304 117struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 118 { "pf_fixed", VCPU_STAT(pf_fixed) },
119 { "pf_guest", VCPU_STAT(pf_guest) },
120 { "tlb_flush", VCPU_STAT(tlb_flush) },
121 { "invlpg", VCPU_STAT(invlpg) },
122 { "exits", VCPU_STAT(exits) },
123 { "io_exits", VCPU_STAT(io_exits) },
124 { "mmio_exits", VCPU_STAT(mmio_exits) },
125 { "signal_exits", VCPU_STAT(signal_exits) },
126 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 127 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 128 { "halt_exits", VCPU_STAT(halt_exits) },
129 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 130 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 131 { "request_irq", VCPU_STAT(request_irq_exits) },
132 { "irq_exits", VCPU_STAT(irq_exits) },
133 { "host_state_reload", VCPU_STAT(host_state_reload) },
134 { "efer_reload", VCPU_STAT(efer_reload) },
135 { "fpu_reload", VCPU_STAT(fpu_reload) },
136 { "insn_emulation", VCPU_STAT(insn_emulation) },
137 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 138 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 139 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 140 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
141 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
142 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
143 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
144 { "mmu_flooded", VM_STAT(mmu_flooded) },
145 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 146 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 147 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 148 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 149 { "largepages", VM_STAT(lpages) },
417bc304
HB		 150 { NULL }
151};
152
2acf923e
DC		 153u64 __read_mostly host_xcr0;
154
d6aa1000
AK		 155int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
156
af585b92
GN		 157static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
158{
159 int i;
160 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
161 vcpu->arch.apf.gfns[i] = ~0;
162}
163
18863bdd
AK		 164static void kvm_on_user_return(struct user_return_notifier *urn)
165{
166 unsigned slot;
18863bdd
AK		 167 struct kvm_shared_msrs *locals
168 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 169 struct kvm_shared_msr_values *values;
18863bdd
AK		 170
171 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 172 values = &locals->values[slot];
173 if (values->host != values->curr) {
174 wrmsrl(shared_msrs_global.msrs[slot], values->host);
175 values->curr = values->host;
18863bdd
AK		 176 }
177 }
178 locals->registered = false;
179 user_return_notifier_unregister(urn);
180}
181
2bf78fa7 182static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 183{
2bf78fa7 184 struct kvm_shared_msrs *smsr;
18863bdd
AK		 185 u64 value;
186
2bf78fa7
SY		 187 smsr = &__get_cpu_var(shared_msrs);
188 /* only read, and nobody should modify it at this time,
189 * so don't need lock */
190 if (slot >= shared_msrs_global.nr) {
191 printk(KERN_ERR "kvm: invalid MSR slot!");
192 return;
193 }
194 rdmsrl_safe(msr, &value);
195 smsr->values[slot].host = value;
196 smsr->values[slot].curr = value;
197}
198
199void kvm_define_shared_msr(unsigned slot, u32 msr)
200{
18863bdd
AK		 201 if (slot >= shared_msrs_global.nr)
202 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 203 shared_msrs_global.msrs[slot] = msr;
204 /* we need ensured the shared_msr_global have been updated */
205 smp_wmb();
18863bdd
AK		 206}
207EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
208
209static void kvm_shared_msr_cpu_online(void)
210{
211 unsigned i;
18863bdd
AK		 212
213 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 214 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 215}
216
d5696725 217void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 218{
219 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
220
2bf78fa7 221 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 222 return;
2bf78fa7
SY		 223 smsr->values[slot].curr = value;
224 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 225 if (!smsr->registered) {
226 smsr->urn.on_user_return = kvm_on_user_return;
227 user_return_notifier_register(&smsr->urn);
228 smsr->registered = true;
229 }
230}
231EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
232
3548bab5
AK		 233static void drop_user_return_notifiers(void *ignore)
234{
235 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
236
237 if (smsr->registered)
238 kvm_on_user_return(&smsr->urn);
239}
240
6866b83e
CO		 241u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
242{
243 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 244 return vcpu->arch.apic_base;
6866b83e 245 else
ad312c7c 246 return vcpu->arch.apic_base;
6866b83e
CO		 247}
248EXPORT_SYMBOL_GPL(kvm_get_apic_base);
249
250void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
251{
252 /* TODO: reserve bits check */
253 if (irqchip_in_kernel(vcpu->kvm))
254 kvm_lapic_set_base(vcpu, data);
255 else
ad312c7c 256 vcpu->arch.apic_base = data;
6866b83e
CO		 257}
258EXPORT_SYMBOL_GPL(kvm_set_apic_base);
259
3fd28fce
ED		 260#define EXCPT_BENIGN 0
261#define EXCPT_CONTRIBUTORY 1
262#define EXCPT_PF 2
263
264static int exception_class(int vector)
265{
266 switch (vector) {
267 case PF_VECTOR:
268 return EXCPT_PF;
269 case DE_VECTOR:
270 case TS_VECTOR:
271 case NP_VECTOR:
272 case SS_VECTOR:
273 case GP_VECTOR:
274 return EXCPT_CONTRIBUTORY;
275 default:
276 break;
277 }
278 return EXCPT_BENIGN;
279}
280
281static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 282 unsigned nr, bool has_error, u32 error_code,
283 bool reinject)
3fd28fce
ED		 284{
285 u32 prev_nr;
286 int class1, class2;
287
3842d135
AK		 288 kvm_make_request(KVM_REQ_EVENT, vcpu);
289
3fd28fce
ED		 290 if (!vcpu->arch.exception.pending) {
291 queue:
292 vcpu->arch.exception.pending = true;
293 vcpu->arch.exception.has_error_code = has_error;
294 vcpu->arch.exception.nr = nr;
295 vcpu->arch.exception.error_code = error_code;
3f0fd292 296 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 297 return;
298 }
299
300 /* to check exception */
301 prev_nr = vcpu->arch.exception.nr;
302 if (prev_nr == DF_VECTOR) {
303 /* triple fault -> shutdown */
a8eeb04a 304 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 305 return;
306 }
307 class1 = exception_class(prev_nr);
308 class2 = exception_class(nr);
309 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
310 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
311 /* generate double fault per SDM Table 5-5 */
312 vcpu->arch.exception.pending = true;
313 vcpu->arch.exception.has_error_code = true;
314 vcpu->arch.exception.nr = DF_VECTOR;
315 vcpu->arch.exception.error_code = 0;
316 } else
317 /* replace previous exception with a new one in a hope
318 that instruction re-execution will regenerate lost
319 exception */
320 goto queue;
321}
322
298101da
AK		 323void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
324{
ce7ddec4 325 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 326}
327EXPORT_SYMBOL_GPL(kvm_queue_exception);
328
ce7ddec4
JR		 329void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
330{
331 kvm_multiple_exception(vcpu, nr, false, 0, true);
332}
333EXPORT_SYMBOL_GPL(kvm_requeue_exception);
334
db8fcefa 335void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 336{
db8fcefa
AP		 337 if (err)
338 kvm_inject_gp(vcpu, 0);
339 else
340 kvm_x86_ops->skip_emulated_instruction(vcpu);
341}
342EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 343
6389ee94 344void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 345{
346 ++vcpu->stat.pf_guest;
6389ee94
AK		 347 vcpu->arch.cr2 = fault->address;
348 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 349}
27d6c865 350EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 351
6389ee94 352void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 353{
6389ee94
AK		 354 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
355 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 356 else
6389ee94 357 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
d4f8cf66
JR		 358}
359
3419ffc8
SY		 360void kvm_inject_nmi(struct kvm_vcpu *vcpu)
361{
3842d135 362 kvm_make_request(KVM_REQ_EVENT, vcpu);
c761e586 363 vcpu->arch.nmi_pending = 1;
3419ffc8
SY		 364}
365EXPORT_SYMBOL_GPL(kvm_inject_nmi);
366
298101da
AK		 367void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
368{
ce7ddec4 369 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 370}
371EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
372
ce7ddec4
JR		 373void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
374{
375 kvm_multiple_exception(vcpu, nr, true, error_code, true);
376}
377EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
378
0a79b009
AK		 379/*
380 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
381 * a #GP and return false.
382 */
383bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 384{
0a79b009
AK		 385 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
386 return true;
387 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
388 return false;
298101da 389}
0a79b009 390EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 391
ec92fe44
JR		 392/*
393 * This function will be used to read from the physical memory of the currently
394 * running guest. The difference to kvm_read_guest_page is that this function
395 * can read from guest physical or from the guest's guest physical memory.
396 */
397int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
398 gfn_t ngfn, void *data, int offset, int len,
399 u32 access)
400{
401 gfn_t real_gfn;
402 gpa_t ngpa;
403
404 ngpa = gfn_to_gpa(ngfn);
405 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
406 if (real_gfn == UNMAPPED_GVA)
407 return -EFAULT;
408
409 real_gfn = gpa_to_gfn(real_gfn);
410
411 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
412}
413EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
414
3d06b8bf
JR		 415int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
416 void *data, int offset, int len, u32 access)
417{
418 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
419 data, offset, len, access);
420}
421
a03490ed
CO		 422/*
423 * Load the pae pdptrs. Return true is they are all valid.
424 */
ff03a073 425int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 426{
427 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
428 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
429 int i;
430 int ret;
ff03a073 431 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 432
ff03a073
JR		 433 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
434 offset * sizeof(u64), sizeof(pdpte),
435 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 436 if (ret < 0) {
437 ret = 0;
438 goto out;
439 }
440 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 441 if (is_present_gpte(pdpte[i]) &&
20c466b5 442 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 443 ret = 0;
444 goto out;
445 }
446 }
447 ret = 1;
448
ff03a073 449 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 450 __set_bit(VCPU_EXREG_PDPTR,
451 (unsigned long *)&vcpu->arch.regs_avail);
452 __set_bit(VCPU_EXREG_PDPTR,
453 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 454out:
a03490ed
CO		 455
456 return ret;
457}
cc4b6871 458EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 459
d835dfec
AK		 460static bool pdptrs_changed(struct kvm_vcpu *vcpu)
461{
ff03a073 462 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 463 bool changed = true;
3d06b8bf
JR		 464 int offset;
465 gfn_t gfn;
d835dfec
AK		 466 int r;
467
468 if (is_long_mode(vcpu) || !is_pae(vcpu))
469 return false;
470
6de4f3ad
AK		 471 if (!test_bit(VCPU_EXREG_PDPTR,
472 (unsigned long *)&vcpu->arch.regs_avail))
473 return true;
474
9f8fe504
AK		 475 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
476 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 477 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
478 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 479 if (r < 0)
480 goto out;
ff03a073 481 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 482out:
d835dfec
AK		 483
484 return changed;
485}
486
49a9b07e 487int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 488{
aad82703
SY		 489 unsigned long old_cr0 = kvm_read_cr0(vcpu);
490 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
491 X86_CR0_CD | X86_CR0_NW;
492
f9a48e6a
AK		 493 cr0 |= X86_CR0_ET;
494
ab344828 495#ifdef CONFIG_X86_64
0f12244f
GN		 496 if (cr0 & 0xffffffff00000000UL)
497 return 1;
ab344828
GN		 498#endif
499
500 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 501
0f12244f
GN		 502 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
503 return 1;
a03490ed 504
0f12244f
GN		 505 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
506 return 1;
a03490ed
CO		 507
508 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
509#ifdef CONFIG_X86_64
f6801dff 510 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 511 int cs_db, cs_l;
512
0f12244f
GN		 513 if (!is_pae(vcpu))
514 return 1;
a03490ed 515 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 516 if (cs_l)
517 return 1;
a03490ed
CO		 518 } else
519#endif
ff03a073 520 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 521 kvm_read_cr3(vcpu)))
0f12244f 522 return 1;
a03490ed
CO		 523 }
524
525 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 526
d170c419 527 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 528 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 529 kvm_async_pf_hash_reset(vcpu);
530 }
e5f3f027 531
aad82703
SY		 532 if ((cr0 ^ old_cr0) & update_bits)
533 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 534 return 0;
535}
2d3ad1f4 536EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 537
2d3ad1f4 538void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 539{
49a9b07e 540 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 541}
2d3ad1f4 542EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 543
2acf923e
DC		 544int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
545{
546 u64 xcr0;
547
548 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
549 if (index != XCR_XFEATURE_ENABLED_MASK)
550 return 1;
551 xcr0 = xcr;
552 if (kvm_x86_ops->get_cpl(vcpu) != 0)
553 return 1;
554 if (!(xcr0 & XSTATE_FP))
555 return 1;
556 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
557 return 1;
558 if (xcr0 & ~host_xcr0)
559 return 1;
560 vcpu->arch.xcr0 = xcr0;
561 vcpu->guest_xcr0_loaded = 0;
562 return 0;
563}
564
565int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
566{
567 if (__kvm_set_xcr(vcpu, index, xcr)) {
568 kvm_inject_gp(vcpu, 0);
569 return 1;
570 }
571 return 0;
572}
573EXPORT_SYMBOL_GPL(kvm_set_xcr);
574
575static bool guest_cpuid_has_xsave(struct kvm_vcpu *vcpu)
576{
577 struct kvm_cpuid_entry2 *best;
578
579 best = kvm_find_cpuid_entry(vcpu, 1, 0);
580 return best && (best->ecx & bit(X86_FEATURE_XSAVE));
581}
582
c68b734f
YW		 583static bool guest_cpuid_has_smep(struct kvm_vcpu *vcpu)
584{
585 struct kvm_cpuid_entry2 *best;
586
587 best = kvm_find_cpuid_entry(vcpu, 7, 0);
588 return best && (best->ebx & bit(X86_FEATURE_SMEP));
589}
590
2acf923e
DC		 591static void update_cpuid(struct kvm_vcpu *vcpu)
592{
593 struct kvm_cpuid_entry2 *best;
594
595 best = kvm_find_cpuid_entry(vcpu, 1, 0);
596 if (!best)
597 return;
598
599 /* Update OSXSAVE bit */
600 if (cpu_has_xsave && best->function == 0x1) {
601 best->ecx &= ~(bit(X86_FEATURE_OSXSAVE));
602 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE))
603 best->ecx |= bit(X86_FEATURE_OSXSAVE);
604 }
605}
606
a83b29c6 607int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 608{
fc78f519 609 unsigned long old_cr4 = kvm_read_cr4(vcpu);
c68b734f
YW		 610 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
611 X86_CR4_PAE | X86_CR4_SMEP;
0f12244f
GN		 612 if (cr4 & CR4_RESERVED_BITS)
613 return 1;
a03490ed 614
2acf923e
DC		 615 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
616 return 1;
617
c68b734f
YW		 618 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
619 return 1;
620
a03490ed 621 if (is_long_mode(vcpu)) {
0f12244f
GN		 622 if (!(cr4 & X86_CR4_PAE))
623 return 1;
a2edf57f
AK		 624 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
625 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 626 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
627 kvm_read_cr3(vcpu)))
0f12244f
GN		 628 return 1;
629
5e1746d6 630 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 631 return 1;
a03490ed 632
aad82703
SY		 633 if ((cr4 ^ old_cr4) & pdptr_bits)
634 kvm_mmu_reset_context(vcpu);
0f12244f 635
2acf923e
DC		 636 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
637 update_cpuid(vcpu);
638
0f12244f
GN		 639 return 0;
640}
2d3ad1f4 641EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 642
2390218b 643int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 644{
9f8fe504 645 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 646 kvm_mmu_sync_roots(vcpu);
d835dfec 647 kvm_mmu_flush_tlb(vcpu);
0f12244f 648 return 0;
d835dfec
AK		 649 }
650
a03490ed 651 if (is_long_mode(vcpu)) {
0f12244f
GN		 652 if (cr3 & CR3_L_MODE_RESERVED_BITS)
653 return 1;
a03490ed
CO		 654 } else {
655 if (is_pae(vcpu)) {
0f12244f
GN		 656 if (cr3 & CR3_PAE_RESERVED_BITS)
657 return 1;
ff03a073
JR		 658 if (is_paging(vcpu) &&
659 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
0f12244f 660 return 1;
a03490ed
CO		 661 }
662 /*
663 * We don't check reserved bits in nonpae mode, because
664 * this isn't enforced, and VMware depends on this.
665 */
666 }
667
a03490ed
CO		 668 /*
669 * Does the new cr3 value map to physical memory? (Note, we
670 * catch an invalid cr3 even in real-mode, because it would
671 * cause trouble later on when we turn on paging anyway.)
672 *
673 * A real CPU would silently accept an invalid cr3 and would
674 * attempt to use it - with largely undefined (and often hard
675 * to debug) behavior on the guest side.
676 */
677 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
0f12244f
GN		 678 return 1;
679 vcpu->arch.cr3 = cr3;
aff48baa 680 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
0f12244f
GN		 681 vcpu->arch.mmu.new_cr3(vcpu);
682 return 0;
683}
2d3ad1f4 684EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 685
eea1cff9 686int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 687{
0f12244f
GN		 688 if (cr8 & CR8_RESERVED_BITS)
689 return 1;
a03490ed
CO		 690 if (irqchip_in_kernel(vcpu->kvm))
691 kvm_lapic_set_tpr(vcpu, cr8);
692 else
ad312c7c 693 vcpu->arch.cr8 = cr8;
0f12244f
GN		 694 return 0;
695}
2d3ad1f4 696EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 697
2d3ad1f4 698unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 699{
700 if (irqchip_in_kernel(vcpu->kvm))
701 return kvm_lapic_get_cr8(vcpu);
702 else
ad312c7c 703 return vcpu->arch.cr8;
a03490ed 704}
2d3ad1f4 705EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 706
338dbc97 707static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 708{
709 switch (dr) {
710 case 0 ... 3:
711 vcpu->arch.db[dr] = val;
712 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
713 vcpu->arch.eff_db[dr] = val;
714 break;
715 case 4:
338dbc97
GN		 716 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
717 return 1; /* #UD */
020df079
GN		 718 /* fall through */
719 case 6:
338dbc97
GN		 720 if (val & 0xffffffff00000000ULL)
721 return -1; /* #GP */
020df079
GN		 722 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
723 break;
724 case 5:
338dbc97
GN		 725 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
726 return 1; /* #UD */
020df079
GN		 727 /* fall through */
728 default: /* 7 */
338dbc97
GN		 729 if (val & 0xffffffff00000000ULL)
730 return -1; /* #GP */
020df079
GN		 731 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
732 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
733 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
734 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
735 }
736 break;
737 }
738
739 return 0;
740}
338dbc97
GN		 741
742int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
743{
744 int res;
745
746 res = __kvm_set_dr(vcpu, dr, val);
747 if (res > 0)
748 kvm_queue_exception(vcpu, UD_VECTOR);
749 else if (res < 0)
750 kvm_inject_gp(vcpu, 0);
751
752 return res;
753}
020df079
GN		 754EXPORT_SYMBOL_GPL(kvm_set_dr);
755
338dbc97 756static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 757{
758 switch (dr) {
759 case 0 ... 3:
760 *val = vcpu->arch.db[dr];
761 break;
762 case 4:
338dbc97 763 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 764 return 1;
020df079
GN		 765 /* fall through */
766 case 6:
767 *val = vcpu->arch.dr6;
768 break;
769 case 5:
338dbc97 770 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 771 return 1;
020df079
GN		 772 /* fall through */
773 default: /* 7 */
774 *val = vcpu->arch.dr7;
775 break;
776 }
777
778 return 0;
779}
338dbc97
GN		 780
781int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
782{
783 if (_kvm_get_dr(vcpu, dr, val)) {
784 kvm_queue_exception(vcpu, UD_VECTOR);
785 return 1;
786 }
787 return 0;
788}
020df079
GN		 789EXPORT_SYMBOL_GPL(kvm_get_dr);
790
043405e1
CO		 791/*
792 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
793 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
794 *
795 * This list is modified at module load time to reflect the
e3267cbb
GC		 796 * capabilities of the host cpu. This capabilities test skips MSRs that are
797 * kvm-specific. Those are put in the beginning of the list.
043405e1 798 */
e3267cbb 799
344d9588 800#define KVM_SAVE_MSRS_BEGIN 8
043405e1 801static u32 msrs_to_save[] = {
e3267cbb 802 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 803 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 804 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
344d9588 805 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN,
043405e1 806 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 807 MSR_STAR,
043405e1
CO		 808#ifdef CONFIG_X86_64
809 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
810#endif
e90aa41e 811 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 812};
813
814static unsigned num_msrs_to_save;
815
816static u32 emulated_msrs[] = {
817 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 818 MSR_IA32_MCG_STATUS,
819 MSR_IA32_MCG_CTL,
043405e1
CO		 820};
821
b69e8cae 822static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 823{
aad82703
SY		 824 u64 old_efer = vcpu->arch.efer;
825
b69e8cae
RJ		 826 if (efer & efer_reserved_bits)
827 return 1;
15c4a640
CO		 828
829 if (is_paging(vcpu)
b69e8cae
RJ		 830 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
831 return 1;
15c4a640 832
1b2fd70c
AG		 833 if (efer & EFER_FFXSR) {
834 struct kvm_cpuid_entry2 *feat;
835
836 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 837 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
838 return 1;
1b2fd70c
AG		 839 }
840
d8017474
AG		 841 if (efer & EFER_SVME) {
842 struct kvm_cpuid_entry2 *feat;
843
844 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 845 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
846 return 1;
d8017474
AG		 847 }
848
15c4a640 849 efer &= ~EFER_LMA;
f6801dff 850 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 851
a3d204e2
SY		 852 kvm_x86_ops->set_efer(vcpu, efer);
853
9645bb56 854 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
b69e8cae 855
aad82703
SY		 856 /* Update reserved bits */
857 if ((efer ^ old_efer) & EFER_NX)
858 kvm_mmu_reset_context(vcpu);
859
b69e8cae 860 return 0;
15c4a640
CO		 861}
862
f2b4b7dd
JR		 863void kvm_enable_efer_bits(u64 mask)
864{
865 efer_reserved_bits &= ~mask;
866}
867EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
868
869
15c4a640
CO		 870/*
871 * Writes msr value into into the appropriate "register".
872 * Returns 0 on success, non-0 otherwise.
873 * Assumes vcpu_load() was already called.
874 */
875int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
876{
877 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
878}
879
313a3dc7
CO		 880/*
881 * Adapt set_msr() to msr_io()'s calling convention
882 */
883static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
884{
885 return kvm_set_msr(vcpu, index, *data);
886}
887
18068523
GOC		 888static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
889{
9ed3c444
AK		 890 int version;
891 int r;
50d0a0f9 892 struct pvclock_wall_clock wc;
923de3cf 893 struct timespec boot;
18068523
GOC		 894
895 if (!wall_clock)
896 return;
897
9ed3c444
AK		 898 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
899 if (r)
900 return;
901
902 if (version & 1)
903 ++version; /* first time write, random junk */
904
905 ++version;
18068523 906
18068523
GOC		 907 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
908
50d0a0f9
GH		 909 /*
910 * The guest calculates current wall clock time by adding
34c238a1 911 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 912 * wall clock specified here. guest system time equals host
913 * system time for us, thus we must fill in host boot time here.
914 */
923de3cf 915 getboottime(&boot);
50d0a0f9
GH		 916
917 wc.sec = boot.tv_sec;
918 wc.nsec = boot.tv_nsec;
919 wc.version = version;
18068523
GOC		 920
921 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
922
923 version++;
924 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 925}
926
50d0a0f9
GH		 927static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
928{
929 uint32_t quotient, remainder;
930
931 /* Don't try to replace with do_div(), this one calculates
932 * "(dividend << 32) / divisor" */
933 __asm__ ( "divl %4"
934 : "=a" (quotient), "=d" (remainder)
935 : "0" (0), "1" (dividend), "r" (divisor) );
936 return quotient;
937}
938
5f4e3f88
ZA		 939static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
940 s8 *pshift, u32 *pmultiplier)
50d0a0f9 941{
5f4e3f88 942 uint64_t scaled64;
50d0a0f9
GH		 943 int32_t shift = 0;
944 uint64_t tps64;
945 uint32_t tps32;
946
5f4e3f88
ZA		 947 tps64 = base_khz * 1000LL;
948 scaled64 = scaled_khz * 1000LL;
50933623 949 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 950 tps64 >>= 1;
951 shift--;
952 }
953
954 tps32 = (uint32_t)tps64;
50933623
JK		 955 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
956 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 957 scaled64 >>= 1;
958 else
959 tps32 <<= 1;
50d0a0f9
GH		 960 shift++;
961 }
962
5f4e3f88
ZA		 963 *pshift = shift;
964 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 965
5f4e3f88
ZA		 966 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
967 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 968}
969
759379dd
ZA		 970static inline u64 get_kernel_ns(void)
971{
972 struct timespec ts;
973
974 WARN_ON(preemptible());
975 ktime_get_ts(&ts);
976 monotonic_to_bootbased(&ts);
977 return timespec_to_ns(&ts);
50d0a0f9
GH		 978}
979
c8076604 980static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 981unsigned long max_tsc_khz;
c8076604 982
8cfdc000
ZA		 983static inline int kvm_tsc_changes_freq(void)
984{
985 int cpu = get_cpu();
986 int ret = !boot_cpu_has(X86_FEATURE_CONSTANT_TSC) &&
987 cpufreq_quick_get(cpu) != 0;
988 put_cpu();
989 return ret;
990}
991
1e993611
JR		 992static u64 vcpu_tsc_khz(struct kvm_vcpu *vcpu)
993{
994 if (vcpu->arch.virtual_tsc_khz)
995 return vcpu->arch.virtual_tsc_khz;
996 else
997 return __this_cpu_read(cpu_tsc_khz);
998}
999
857e4099 1000static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
759379dd 1001{
217fc9cf
AK		 1002 u64 ret;
1003
759379dd
ZA		 1004 WARN_ON(preemptible());
1005 if (kvm_tsc_changes_freq())
1006 printk_once(KERN_WARNING
1007 "kvm: unreliable cycle conversion on adjustable rate TSC\n");
857e4099 1008 ret = nsec * vcpu_tsc_khz(vcpu);
217fc9cf
AK		 1009 do_div(ret, USEC_PER_SEC);
1010 return ret;
759379dd
ZA		 1011}
1012
1e993611 1013static void kvm_init_tsc_catchup(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
c285545f
ZA		 1014{
1015 /* Compute a scale to convert nanoseconds in TSC cycles */
1016 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
1e993611
JR		 1017 &vcpu->arch.tsc_catchup_shift,
1018 &vcpu->arch.tsc_catchup_mult);
c285545f
ZA		 1019}
1020
1021static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1022{
1023 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.last_tsc_nsec,
1e993611
JR		 1024 vcpu->arch.tsc_catchup_mult,
1025 vcpu->arch.tsc_catchup_shift);
c285545f
ZA		 1026 tsc += vcpu->arch.last_tsc_write;
1027 return tsc;
1028}
1029
99e3e30a
ZA		 1030void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
1031{
1032 struct kvm *kvm = vcpu->kvm;
f38e098f 1033 u64 offset, ns, elapsed;
99e3e30a 1034 unsigned long flags;
46543ba4 1035 s64 sdiff;
99e3e30a 1036
038f8c11 1037 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1038 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1039 ns = get_kernel_ns();
f38e098f 1040 elapsed = ns - kvm->arch.last_tsc_nsec;
46543ba4
ZA		 1041 sdiff = data - kvm->arch.last_tsc_write;
1042 if (sdiff < 0)
1043 sdiff = -sdiff;
f38e098f
ZA		 1044
1045 /*
46543ba4 1046 * Special case: close write to TSC within 5 seconds of
f38e098f 1047 * another CPU is interpreted as an attempt to synchronize
0d2eb44f 1048 * The 5 seconds is to accommodate host load / swapping as
46543ba4 1049 * well as any reset of TSC during the boot process.
f38e098f
ZA		 1050 *
1051 * In that case, for a reliable TSC, we can match TSC offsets,
46543ba4 1052 * or make a best guest using elapsed value.
f38e098f 1053 */
857e4099 1054 if (sdiff < nsec_to_cycles(vcpu, 5ULL * NSEC_PER_SEC) &&
46543ba4 1055 elapsed < 5ULL * NSEC_PER_SEC) {
f38e098f
ZA		 1056 if (!check_tsc_unstable()) {
1057 offset = kvm->arch.last_tsc_offset;
1058 pr_debug("kvm: matched tsc offset for %llu\n", data);
1059 } else {
857e4099 1060 u64 delta = nsec_to_cycles(vcpu, elapsed);
759379dd
ZA		 1061 offset += delta;
1062 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f
ZA		 1063 }
1064 ns = kvm->arch.last_tsc_nsec;
1065 }
1066 kvm->arch.last_tsc_nsec = ns;
1067 kvm->arch.last_tsc_write = data;
1068 kvm->arch.last_tsc_offset = offset;
99e3e30a 1069 kvm_x86_ops->write_tsc_offset(vcpu, offset);
038f8c11 1070 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
99e3e30a
ZA		 1071
1072 /* Reset of TSC must disable overshoot protection below */
1073 vcpu->arch.hv_clock.tsc_timestamp = 0;
c285545f
ZA		 1074 vcpu->arch.last_tsc_write = data;
1075 vcpu->arch.last_tsc_nsec = ns;
99e3e30a
ZA		 1076}
1077EXPORT_SYMBOL_GPL(kvm_write_tsc);
1078
34c238a1 1079static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1080{
18068523
GOC		 1081 unsigned long flags;
1082 struct kvm_vcpu_arch *vcpu = &v->arch;
1083 void *shared_kaddr;
463656c0 1084 unsigned long this_tsc_khz;
1d5f066e
ZA		 1085 s64 kernel_ns, max_kernel_ns;
1086 u64 tsc_timestamp;
18068523 1087
18068523
GOC		 1088 /* Keep irq disabled to prevent changes to the clock */
1089 local_irq_save(flags);
1d5f066e 1090 kvm_get_msr(v, MSR_IA32_TSC, &tsc_timestamp);
759379dd 1091 kernel_ns = get_kernel_ns();
1e993611 1092 this_tsc_khz = vcpu_tsc_khz(v);
8cfdc000 1093 if (unlikely(this_tsc_khz == 0)) {
c285545f 1094 local_irq_restore(flags);
34c238a1 1095 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
8cfdc000
ZA		 1096 return 1;
1097 }
18068523 1098
c285545f
ZA		 1099 /*
1100 * We may have to catch up the TSC to match elapsed wall clock
1101 * time for two reasons, even if kvmclock is used.
1102 * 1) CPU could have been running below the maximum TSC rate
1103 * 2) Broken TSC compensation resets the base at each VCPU
1104 * entry to avoid unknown leaps of TSC even when running
1105 * again on the same CPU. This may cause apparent elapsed
1106 * time to disappear, and the guest to stand still or run
1107 * very slowly.
1108 */
1109 if (vcpu->tsc_catchup) {
1110 u64 tsc = compute_guest_tsc(v, kernel_ns);
1111 if (tsc > tsc_timestamp) {
1112 kvm_x86_ops->adjust_tsc_offset(v, tsc - tsc_timestamp);
1113 tsc_timestamp = tsc;
1114 }
50d0a0f9
GH		 1115 }
1116
18068523
GOC		 1117 local_irq_restore(flags);
1118
c285545f
ZA		 1119 if (!vcpu->time_page)
1120 return 0;
18068523 1121
1d5f066e
ZA		 1122 /*
1123 * Time as measured by the TSC may go backwards when resetting the base
1124 * tsc_timestamp. The reason for this is that the TSC resolution is
1125 * higher than the resolution of the other clock scales. Thus, many
1126 * possible measurments of the TSC correspond to one measurement of any
1127 * other clock, and so a spread of values is possible. This is not a
1128 * problem for the computation of the nanosecond clock; with TSC rates
1129 * around 1GHZ, there can only be a few cycles which correspond to one
1130 * nanosecond value, and any path through this code will inevitably
1131 * take longer than that. However, with the kernel_ns value itself,
1132 * the precision may be much lower, down to HZ granularity. If the
1133 * first sampling of TSC against kernel_ns ends in the low part of the
1134 * range, and the second in the high end of the range, we can get:
1135 *
1136 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1137 *
1138 * As the sampling errors potentially range in the thousands of cycles,
1139 * it is possible such a time value has already been observed by the
1140 * guest. To protect against this, we must compute the system time as
1141 * observed by the guest and ensure the new system time is greater.
1142 */
1143 max_kernel_ns = 0;
1144 if (vcpu->hv_clock.tsc_timestamp && vcpu->last_guest_tsc) {
1145 max_kernel_ns = vcpu->last_guest_tsc -
1146 vcpu->hv_clock.tsc_timestamp;
1147 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1148 vcpu->hv_clock.tsc_to_system_mul,
1149 vcpu->hv_clock.tsc_shift);
1150 max_kernel_ns += vcpu->last_kernel_ns;
1151 }
afbcf7ab 1152
e48672fa 1153 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1154 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1155 &vcpu->hv_clock.tsc_shift,
1156 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1157 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1158 }
1159
1d5f066e
ZA		 1160 if (max_kernel_ns > kernel_ns)
1161 kernel_ns = max_kernel_ns;
1162
8cfdc000 1163 /* With all the info we got, fill in the values */
1d5f066e 1164 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1165 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1d5f066e 1166 vcpu->last_kernel_ns = kernel_ns;
28e4639a 1167 vcpu->last_guest_tsc = tsc_timestamp;
371bcf64
GC		 1168 vcpu->hv_clock.flags = 0;
1169
18068523
GOC		 1170 /*
1171 * The interface expects us to write an even number signaling that the
1172 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1173 * state, we just increase by 2 at the end.
18068523 1174 */
50d0a0f9 1175 vcpu->hv_clock.version += 2;
18068523
GOC		 1176
1177 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
1178
1179 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 1180 sizeof(vcpu->hv_clock));
18068523
GOC		 1181
1182 kunmap_atomic(shared_kaddr, KM_USER0);
1183
1184 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
8cfdc000 1185 return 0;
c8076604
GH		 1186}
1187
9ba075a6
AK		 1188static bool msr_mtrr_valid(unsigned msr)
1189{
1190 switch (msr) {
1191 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1192 case MSR_MTRRfix64K_00000:
1193 case MSR_MTRRfix16K_80000:
1194 case MSR_MTRRfix16K_A0000:
1195 case MSR_MTRRfix4K_C0000:
1196 case MSR_MTRRfix4K_C8000:
1197 case MSR_MTRRfix4K_D0000:
1198 case MSR_MTRRfix4K_D8000:
1199 case MSR_MTRRfix4K_E0000:
1200 case MSR_MTRRfix4K_E8000:
1201 case MSR_MTRRfix4K_F0000:
1202 case MSR_MTRRfix4K_F8000:
1203 case MSR_MTRRdefType:
1204 case MSR_IA32_CR_PAT:
1205 return true;
1206 case 0x2f8:
1207 return true;
1208 }
1209 return false;
1210}
1211
d6289b93
MT		 1212static bool valid_pat_type(unsigned t)
1213{
1214 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1215}
1216
1217static bool valid_mtrr_type(unsigned t)
1218{
1219 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1220}
1221
1222static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1223{
1224 int i;
1225
1226 if (!msr_mtrr_valid(msr))
1227 return false;
1228
1229 if (msr == MSR_IA32_CR_PAT) {
1230 for (i = 0; i < 8; i++)
1231 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1232 return false;
1233 return true;
1234 } else if (msr == MSR_MTRRdefType) {
1235 if (data & ~0xcff)
1236 return false;
1237 return valid_mtrr_type(data & 0xff);
1238 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1239 for (i = 0; i < 8 ; i++)
1240 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1241 return false;
1242 return true;
1243 }
1244
1245 /* variable MTRRs */
1246 return valid_mtrr_type(data & 0xff);
1247}
1248
9ba075a6
AK		 1249static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1250{
0bed3b56
SY		 1251 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1252
d6289b93 1253 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1254 return 1;
1255
0bed3b56
SY		 1256 if (msr == MSR_MTRRdefType) {
1257 vcpu->arch.mtrr_state.def_type = data;
1258 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1259 } else if (msr == MSR_MTRRfix64K_00000)
1260 p[0] = data;
1261 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1262 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1263 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1264 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1265 else if (msr == MSR_IA32_CR_PAT)
1266 vcpu->arch.pat = data;
1267 else { /* Variable MTRRs */
1268 int idx, is_mtrr_mask;
1269 u64 *pt;
1270
1271 idx = (msr - 0x200) / 2;
1272 is_mtrr_mask = msr - 0x200 - 2 * idx;
1273 if (!is_mtrr_mask)
1274 pt =
1275 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1276 else
1277 pt =
1278 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1279 *pt = data;
1280 }
1281
1282 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1283 return 0;
1284}
15c4a640 1285
890ca9ae 1286static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1287{
890ca9ae
HY		 1288 u64 mcg_cap = vcpu->arch.mcg_cap;
1289 unsigned bank_num = mcg_cap & 0xff;
1290
15c4a640 1291 switch (msr) {
15c4a640 1292 case MSR_IA32_MCG_STATUS:
890ca9ae 1293 vcpu->arch.mcg_status = data;
15c4a640 1294 break;
c7ac679c 1295 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1296 if (!(mcg_cap & MCG_CTL_P))
1297 return 1;
1298 if (data != 0 && data != ~(u64)0)
1299 return -1;
1300 vcpu->arch.mcg_ctl = data;
1301 break;
1302 default:
1303 if (msr >= MSR_IA32_MC0_CTL &&
1304 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1305 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1306 /* only 0 or all 1s can be written to IA32_MCi_CTL
1307 * some Linux kernels though clear bit 10 in bank 4 to
1308 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1309 * this to avoid an uncatched #GP in the guest
1310 */
890ca9ae 1311 if ((offset & 0x3) == 0 &&
114be429 1312 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1313 return -1;
1314 vcpu->arch.mce_banks[offset] = data;
1315 break;
1316 }
1317 return 1;
1318 }
1319 return 0;
1320}
1321
ffde22ac
ES		 1322static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1323{
1324 struct kvm *kvm = vcpu->kvm;
1325 int lm = is_long_mode(vcpu);
1326 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1327 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1328 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1329 : kvm->arch.xen_hvm_config.blob_size_32;
1330 u32 page_num = data & ~PAGE_MASK;
1331 u64 page_addr = data & PAGE_MASK;
1332 u8 *page;
1333 int r;
1334
1335 r = -E2BIG;
1336 if (page_num >= blob_size)
1337 goto out;
1338 r = -ENOMEM;
1339 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
1340 if (!page)
1341 goto out;
1342 r = -EFAULT;
1343 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
1344 goto out_free;
1345 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1346 goto out_free;
1347 r = 0;
1348out_free:
1349 kfree(page);
1350out:
1351 return r;
1352}
1353
55cd8e5a
GN		 1354static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1355{
1356 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1357}
1358
1359static bool kvm_hv_msr_partition_wide(u32 msr)
1360{
1361 bool r = false;
1362 switch (msr) {
1363 case HV_X64_MSR_GUEST_OS_ID:
1364 case HV_X64_MSR_HYPERCALL:
1365 r = true;
1366 break;
1367 }
1368
1369 return r;
1370}
1371
1372static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1373{
1374 struct kvm *kvm = vcpu->kvm;
1375
1376 switch (msr) {
1377 case HV_X64_MSR_GUEST_OS_ID:
1378 kvm->arch.hv_guest_os_id = data;
1379 /* setting guest os id to zero disables hypercall page */
1380 if (!kvm->arch.hv_guest_os_id)
1381 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1382 break;
1383 case HV_X64_MSR_HYPERCALL: {
1384 u64 gfn;
1385 unsigned long addr;
1386 u8 instructions[4];
1387
1388 /* if guest os id is not set hypercall should remain disabled */
1389 if (!kvm->arch.hv_guest_os_id)
1390 break;
1391 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1392 kvm->arch.hv_hypercall = data;
1393 break;
1394 }
1395 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1396 addr = gfn_to_hva(kvm, gfn);
1397 if (kvm_is_error_hva(addr))
1398 return 1;
1399 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1400 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1401 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1402 return 1;
1403 kvm->arch.hv_hypercall = data;
1404 break;
1405 }
1406 default:
1407 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1408 "data 0x%llx\n", msr, data);
1409 return 1;
1410 }
1411 return 0;
1412}
1413
1414static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1415{
10388a07
GN		 1416 switch (msr) {
1417 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1418 unsigned long addr;
55cd8e5a 1419
10388a07
GN		 1420 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1421 vcpu->arch.hv_vapic = data;
1422 break;
1423 }
1424 addr = gfn_to_hva(vcpu->kvm, data >>
1425 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1426 if (kvm_is_error_hva(addr))
1427 return 1;
8b0cedff 1428 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 1429 return 1;
1430 vcpu->arch.hv_vapic = data;
1431 break;
1432 }
1433 case HV_X64_MSR_EOI:
1434 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1435 case HV_X64_MSR_ICR:
1436 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1437 case HV_X64_MSR_TPR:
1438 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1439 default:
1440 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1441 "data 0x%llx\n", msr, data);
1442 return 1;
1443 }
1444
1445 return 0;
55cd8e5a
GN		 1446}
1447
344d9588
GN		 1448static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1449{
1450 gpa_t gpa = data & ~0x3f;
1451
6adba527
GN		 1452 /* Bits 2:5 are resrved, Should be zero */
1453 if (data & 0x3c)
344d9588
GN		 1454 return 1;
1455
1456 vcpu->arch.apf.msr_val = data;
1457
1458 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1459 kvm_clear_async_pf_completion_queue(vcpu);
1460 kvm_async_pf_hash_reset(vcpu);
1461 return 0;
1462 }
1463
1464 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa))
1465 return 1;
1466
6adba527 1467 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1468 kvm_async_pf_wakeup_all(vcpu);
1469 return 0;
1470}
1471
12f9a48f
GC		 1472static void kvmclock_reset(struct kvm_vcpu *vcpu)
1473{
1474 if (vcpu->arch.time_page) {
1475 kvm_release_page_dirty(vcpu->arch.time_page);
1476 vcpu->arch.time_page = NULL;
1477 }
1478}
1479
15c4a640
CO		 1480int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1481{
1482 switch (msr) {
15c4a640 1483 case MSR_EFER:
b69e8cae 1484 return set_efer(vcpu, data);
8f1589d9
AP		 1485 case MSR_K7_HWCR:
1486 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1487 data &= ~(u64)0x100; /* ignore ignne emulation enable */
8f1589d9
AP		 1488 if (data != 0) {
1489 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1490 data);
1491 return 1;
1492 }
15c4a640 1493 break;
f7c6d140
AP		 1494 case MSR_FAM10H_MMIO_CONF_BASE:
1495 if (data != 0) {
1496 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1497 "0x%llx\n", data);
1498 return 1;
1499 }
15c4a640 1500 break;
c323c0e5 1501 case MSR_AMD64_NB_CFG:
c7ac679c 1502 break;
b5e2fec0
AG		 1503 case MSR_IA32_DEBUGCTLMSR:
1504 if (!data) {
1505 /* We support the non-activated case already */
1506 break;
1507 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1508 /* Values other than LBR and BTF are vendor-specific,
1509 thus reserved and should throw a #GP */
1510 return 1;
1511 }
1512 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1513 __func__, data);
1514 break;
15c4a640
CO		 1515 case MSR_IA32_UCODE_REV:
1516 case MSR_IA32_UCODE_WRITE:
61a6bd67 1517 case MSR_VM_HSAVE_PA:
6098ca93 1518 case MSR_AMD64_PATCH_LOADER:
15c4a640 1519 break;
9ba075a6
AK		 1520 case 0x200 ... 0x2ff:
1521 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1522 case MSR_IA32_APICBASE:
1523 kvm_set_apic_base(vcpu, data);
1524 break;
0105d1a5
GN		 1525 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1526 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 1527 case MSR_IA32_MISC_ENABLE:
ad312c7c 1528 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1529 break;
11c6bffa 1530 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1531 case MSR_KVM_WALL_CLOCK:
1532 vcpu->kvm->arch.wall_clock = data;
1533 kvm_write_wall_clock(vcpu->kvm, data);
1534 break;
11c6bffa 1535 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 1536 case MSR_KVM_SYSTEM_TIME: {
12f9a48f 1537 kvmclock_reset(vcpu);
18068523
GOC		 1538
1539 vcpu->arch.time = data;
c285545f 1540 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
18068523
GOC		 1541
1542 /* we verify if the enable bit is set... */
1543 if (!(data & 1))
1544 break;
1545
1546 /* ...but clean it before doing the actual write */
1547 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1548
18068523
GOC		 1549 vcpu->arch.time_page =
1550 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1551
1552 if (is_error_page(vcpu->arch.time_page)) {
1553 kvm_release_page_clean(vcpu->arch.time_page);
1554 vcpu->arch.time_page = NULL;
1555 }
18068523
GOC		 1556 break;
1557 }
344d9588
GN		 1558 case MSR_KVM_ASYNC_PF_EN:
1559 if (kvm_pv_enable_async_pf(vcpu, data))
1560 return 1;
1561 break;
890ca9ae
HY		 1562 case MSR_IA32_MCG_CTL:
1563 case MSR_IA32_MCG_STATUS:
1564 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1565 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1566
1567 /* Performance counters are not protected by a CPUID bit,
1568 * so we should check all of them in the generic path for the sake of
1569 * cross vendor migration.
1570 * Writing a zero into the event select MSRs disables them,
1571 * which we perfectly emulate ;-). Any other value should be at least
1572 * reported, some guests depend on them.
1573 */
1574 case MSR_P6_EVNTSEL0:
1575 case MSR_P6_EVNTSEL1:
1576 case MSR_K7_EVNTSEL0:
1577 case MSR_K7_EVNTSEL1:
1578 case MSR_K7_EVNTSEL2:
1579 case MSR_K7_EVNTSEL3:
1580 if (data != 0)
1581 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1582 "0x%x data 0x%llx\n", msr, data);
1583 break;
1584 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1585 * so we ignore writes to make it happy.
1586 */
1587 case MSR_P6_PERFCTR0:
1588 case MSR_P6_PERFCTR1:
1589 case MSR_K7_PERFCTR0:
1590 case MSR_K7_PERFCTR1:
1591 case MSR_K7_PERFCTR2:
1592 case MSR_K7_PERFCTR3:
1593 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1594 "0x%x data 0x%llx\n", msr, data);
1595 break;
84e0cefa
JS		 1596 case MSR_K7_CLK_CTL:
1597 /*
1598 * Ignore all writes to this no longer documented MSR.
1599 * Writes are only relevant for old K7 processors,
1600 * all pre-dating SVM, but a recommended workaround from
1601 * AMD for these chips. It is possible to speicify the
1602 * affected processor models on the command line, hence
1603 * the need to ignore the workaround.
1604 */
1605 break;
55cd8e5a
GN		 1606 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1607 if (kvm_hv_msr_partition_wide(msr)) {
1608 int r;
1609 mutex_lock(&vcpu->kvm->lock);
1610 r = set_msr_hyperv_pw(vcpu, msr, data);
1611 mutex_unlock(&vcpu->kvm->lock);
1612 return r;
1613 } else
1614 return set_msr_hyperv(vcpu, msr, data);
1615 break;
91c9c3ed 1616 case MSR_IA32_BBL_CR_CTL3:
1617 /* Drop writes to this legacy MSR -- see rdmsr
1618 * counterpart for further detail.
1619 */
1620 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
1621 break;
15c4a640 1622 default:
ffde22ac
ES		 1623 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1624 return xen_hvm_config(vcpu, data);
ed85c068
AP		 1625 if (!ignore_msrs) {
1626 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1627 msr, data);
1628 return 1;
1629 } else {
1630 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1631 msr, data);
1632 break;
1633 }
15c4a640
CO		 1634 }
1635 return 0;
1636}
1637EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1638
1639
1640/*
1641 * Reads an msr value (of 'msr_index') into 'pdata'.
1642 * Returns 0 on success, non-0 otherwise.
1643 * Assumes vcpu_load() was already called.
1644 */
1645int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1646{
1647 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1648}
1649
9ba075a6
AK		 1650static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1651{
0bed3b56
SY		 1652 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1653
9ba075a6
AK		 1654 if (!msr_mtrr_valid(msr))
1655 return 1;
1656
0bed3b56
SY		 1657 if (msr == MSR_MTRRdefType)
1658 *pdata = vcpu->arch.mtrr_state.def_type +
1659 (vcpu->arch.mtrr_state.enabled << 10);
1660 else if (msr == MSR_MTRRfix64K_00000)
1661 *pdata = p[0];
1662 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1663 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1664 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1665 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1666 else if (msr == MSR_IA32_CR_PAT)
1667 *pdata = vcpu->arch.pat;
1668 else { /* Variable MTRRs */
1669 int idx, is_mtrr_mask;
1670 u64 *pt;
1671
1672 idx = (msr - 0x200) / 2;
1673 is_mtrr_mask = msr - 0x200 - 2 * idx;
1674 if (!is_mtrr_mask)
1675 pt =
1676 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1677 else
1678 pt =
1679 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1680 *pdata = *pt;
1681 }
1682
9ba075a6
AK		 1683 return 0;
1684}
1685
890ca9ae 1686static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1687{
1688 u64 data;
890ca9ae
HY		 1689 u64 mcg_cap = vcpu->arch.mcg_cap;
1690 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1691
1692 switch (msr) {
15c4a640
CO		 1693 case MSR_IA32_P5_MC_ADDR:
1694 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1695 data = 0;
1696 break;
15c4a640 1697 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1698 data = vcpu->arch.mcg_cap;
1699 break;
c7ac679c 1700 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1701 if (!(mcg_cap & MCG_CTL_P))
1702 return 1;
1703 data = vcpu->arch.mcg_ctl;
1704 break;
1705 case MSR_IA32_MCG_STATUS:
1706 data = vcpu->arch.mcg_status;
1707 break;
1708 default:
1709 if (msr >= MSR_IA32_MC0_CTL &&
1710 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1711 u32 offset = msr - MSR_IA32_MC0_CTL;
1712 data = vcpu->arch.mce_banks[offset];
1713 break;
1714 }
1715 return 1;
1716 }
1717 *pdata = data;
1718 return 0;
1719}
1720
55cd8e5a
GN		 1721static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1722{
1723 u64 data = 0;
1724 struct kvm *kvm = vcpu->kvm;
1725
1726 switch (msr) {
1727 case HV_X64_MSR_GUEST_OS_ID:
1728 data = kvm->arch.hv_guest_os_id;
1729 break;
1730 case HV_X64_MSR_HYPERCALL:
1731 data = kvm->arch.hv_hypercall;
1732 break;
1733 default:
1734 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1735 return 1;
1736 }
1737
1738 *pdata = data;
1739 return 0;
1740}
1741
1742static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1743{
1744 u64 data = 0;
1745
1746 switch (msr) {
1747 case HV_X64_MSR_VP_INDEX: {
1748 int r;
1749 struct kvm_vcpu *v;
1750 kvm_for_each_vcpu(r, v, vcpu->kvm)
1751 if (v == vcpu)
1752 data = r;
1753 break;
1754 }
10388a07
GN		 1755 case HV_X64_MSR_EOI:
1756 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1757 case HV_X64_MSR_ICR:
1758 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1759 case HV_X64_MSR_TPR:
1760 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
55cd8e5a
GN		 1761 default:
1762 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1763 return 1;
1764 }
1765 *pdata = data;
1766 return 0;
1767}
1768
890ca9ae
HY		 1769int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1770{
1771 u64 data;
1772
1773 switch (msr) {
890ca9ae 1774 case MSR_IA32_PLATFORM_ID:
15c4a640 1775 case MSR_IA32_UCODE_REV:
15c4a640 1776 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1777 case MSR_IA32_DEBUGCTLMSR:
1778 case MSR_IA32_LASTBRANCHFROMIP:
1779 case MSR_IA32_LASTBRANCHTOIP:
1780 case MSR_IA32_LASTINTFROMIP:
1781 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1782 case MSR_K8_SYSCFG:
1783 case MSR_K7_HWCR:
61a6bd67 1784 case MSR_VM_HSAVE_PA:
1f3ee616
AS		 1785 case MSR_P6_PERFCTR0:
1786 case MSR_P6_PERFCTR1:
7fe29e0f
AS		 1787 case MSR_P6_EVNTSEL0:
1788 case MSR_P6_EVNTSEL1:
9e699624 1789 case MSR_K7_EVNTSEL0:
1f3ee616 1790 case MSR_K7_PERFCTR0:
1fdbd48c 1791 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1792 case MSR_AMD64_NB_CFG:
f7c6d140 1793 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1794 data = 0;
1795 break;
9ba075a6
AK		 1796 case MSR_MTRRcap:
1797 data = 0x500 | KVM_NR_VAR_MTRR;
1798 break;
1799 case 0x200 ... 0x2ff:
1800 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1801 case 0xcd: /* fsb frequency */
1802 data = 3;
1803 break;
7b914098
JS		 1804 /*
1805 * MSR_EBC_FREQUENCY_ID
1806 * Conservative value valid for even the basic CPU models.
1807 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
1808 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
1809 * and 266MHz for model 3, or 4. Set Core Clock
1810 * Frequency to System Bus Frequency Ratio to 1 (bits
1811 * 31:24) even though these are only valid for CPU
1812 * models > 2, however guests may end up dividing or
1813 * multiplying by zero otherwise.
1814 */
1815 case MSR_EBC_FREQUENCY_ID:
1816 data = 1 << 24;
1817 break;
15c4a640
CO		 1818 case MSR_IA32_APICBASE:
1819 data = kvm_get_apic_base(vcpu);
1820 break;
0105d1a5
GN		 1821 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1822 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1823 break;
15c4a640 1824 case MSR_IA32_MISC_ENABLE:
ad312c7c 1825 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1826 break;
847f0ad8
AG		 1827 case MSR_IA32_PERF_STATUS:
1828 /* TSC increment by tick */
1829 data = 1000ULL;
1830 /* CPU multiplier */
1831 data |= (((uint64_t)4ULL) << 40);
1832 break;
15c4a640 1833 case MSR_EFER:
f6801dff 1834 data = vcpu->arch.efer;
15c4a640 1835 break;
18068523 1836 case MSR_KVM_WALL_CLOCK:
11c6bffa 1837 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1838 data = vcpu->kvm->arch.wall_clock;
1839 break;
1840 case MSR_KVM_SYSTEM_TIME:
11c6bffa 1841 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1842 data = vcpu->arch.time;
1843 break;
344d9588
GN		 1844 case MSR_KVM_ASYNC_PF_EN:
1845 data = vcpu->arch.apf.msr_val;
1846 break;
890ca9ae
HY		 1847 case MSR_IA32_P5_MC_ADDR:
1848 case MSR_IA32_P5_MC_TYPE:
1849 case MSR_IA32_MCG_CAP:
1850 case MSR_IA32_MCG_CTL:
1851 case MSR_IA32_MCG_STATUS:
1852 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1853 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 1854 case MSR_K7_CLK_CTL:
1855 /*
1856 * Provide expected ramp-up count for K7. All other
1857 * are set to zero, indicating minimum divisors for
1858 * every field.
1859 *
1860 * This prevents guest kernels on AMD host with CPU
1861 * type 6, model 8 and higher from exploding due to
1862 * the rdmsr failing.
1863 */
1864 data = 0x20000000;
1865 break;
55cd8e5a
GN		 1866 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1867 if (kvm_hv_msr_partition_wide(msr)) {
1868 int r;
1869 mutex_lock(&vcpu->kvm->lock);
1870 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1871 mutex_unlock(&vcpu->kvm->lock);
1872 return r;
1873 } else
1874 return get_msr_hyperv(vcpu, msr, pdata);
1875 break;
91c9c3ed 1876 case MSR_IA32_BBL_CR_CTL3:
1877 /* This legacy MSR exists but isn't fully documented in current
1878 * silicon. It is however accessed by winxp in very narrow
1879 * scenarios where it sets bit #19, itself documented as
1880 * a "reserved" bit. Best effort attempt to source coherent
1881 * read data here should the balance of the register be
1882 * interpreted by the guest:
1883 *
1884 * L2 cache control register 3: 64GB range, 256KB size,
1885 * enabled, latency 0x1, configured
1886 */
1887 data = 0xbe702111;
1888 break;
15c4a640 1889 default:
ed85c068
AP		 1890 if (!ignore_msrs) {
1891 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1892 return 1;
1893 } else {
1894 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1895 data = 0;
1896 }
1897 break;
15c4a640
CO		 1898 }
1899 *pdata = data;
1900 return 0;
1901}
1902EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1903
313a3dc7
CO		 1904/*
1905 * Read or write a bunch of msrs. All parameters are kernel addresses.
1906 *
1907 * @return number of msrs set successfully.
1908 */
1909static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1910 struct kvm_msr_entry *entries,
1911 int (*do_msr)(struct kvm_vcpu *vcpu,
1912 unsigned index, u64 *data))
1913{
f656ce01 1914 int i, idx;
313a3dc7 1915
f656ce01 1916 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 1917 for (i = 0; i < msrs->nmsrs; ++i)
1918 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1919 break;
f656ce01 1920 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 1921
313a3dc7
CO		 1922 return i;
1923}
1924
1925/*
1926 * Read or write a bunch of msrs. Parameters are user addresses.
1927 *
1928 * @return number of msrs set successfully.
1929 */
1930static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1931 int (*do_msr)(struct kvm_vcpu *vcpu,
1932 unsigned index, u64 *data),
1933 int writeback)
1934{
1935 struct kvm_msrs msrs;
1936 struct kvm_msr_entry *entries;
1937 int r, n;
1938 unsigned size;
1939
1940 r = -EFAULT;
1941 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1942 goto out;
1943
1944 r = -E2BIG;
1945 if (msrs.nmsrs >= MAX_IO_MSRS)
1946 goto out;
1947
1948 r = -ENOMEM;
1949 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
7a73c028 1950 entries = kmalloc(size, GFP_KERNEL);
313a3dc7
CO		 1951 if (!entries)
1952 goto out;
1953
1954 r = -EFAULT;
1955 if (copy_from_user(entries, user_msrs->entries, size))
1956 goto out_free;
1957
1958 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1959 if (r < 0)
1960 goto out_free;
1961
1962 r = -EFAULT;
1963 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1964 goto out_free;
1965
1966 r = n;
1967
1968out_free:
7a73c028 1969 kfree(entries);
313a3dc7
CO		 1970out:
1971 return r;
1972}
1973
018d00d2
ZX		 1974int kvm_dev_ioctl_check_extension(long ext)
1975{
1976 int r;
1977
1978 switch (ext) {
1979 case KVM_CAP_IRQCHIP:
1980 case KVM_CAP_HLT:
1981 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1982 case KVM_CAP_SET_TSS_ADDR:
07716717 1983 case KVM_CAP_EXT_CPUID:
c8076604 1984 case KVM_CAP_CLOCKSOURCE:
7837699f 1985 case KVM_CAP_PIT:
a28e4f5a 1986 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1987 case KVM_CAP_MP_STATE:
ed848624 1988 case KVM_CAP_SYNC_MMU:
a355c85c 1989 case KVM_CAP_USER_NMI:
52d939a0 1990 case KVM_CAP_REINJECT_CONTROL:
4925663a 1991 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1992 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1993 case KVM_CAP_IRQFD:
d34e6b17 1994 case KVM_CAP_IOEVENTFD:
c5ff41ce 1995 case KVM_CAP_PIT2:
e9f42757 1996 case KVM_CAP_PIT_STATE2:
b927a3ce 1997 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 1998 case KVM_CAP_XEN_HVM:
afbcf7ab 1999 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2000 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2001 case KVM_CAP_HYPERV:
10388a07 2002 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2003 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2004 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2005 case KVM_CAP_DEBUGREGS:
d2be1651 2006 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2007 case KVM_CAP_XSAVE:
344d9588 2008 case KVM_CAP_ASYNC_PF:
92a1f12d 2009 case KVM_CAP_GET_TSC_KHZ:
018d00d2
ZX		 2010 r = 1;
2011 break;
542472b5
LV		 2012 case KVM_CAP_COALESCED_MMIO:
2013 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2014 break;
774ead3a
AK		 2015 case KVM_CAP_VAPIC:
2016 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2017 break;
f725230a
AK		 2018 case KVM_CAP_NR_VCPUS:
2019 r = KVM_MAX_VCPUS;
2020 break;
a988b910
AK		 2021 case KVM_CAP_NR_MEMSLOTS:
2022 r = KVM_MEMORY_SLOTS;
2023 break;
a68a6a72
MT		 2024 case KVM_CAP_PV_MMU: /* obsolete */
2025 r = 0;
2f333bcb 2026 break;
62c476c7 2027 case KVM_CAP_IOMMU:
19de40a8 2028 r = iommu_found();
62c476c7 2029 break;
890ca9ae
HY		 2030 case KVM_CAP_MCE:
2031 r = KVM_MAX_MCE_BANKS;
2032 break;
2d5b5a66
SY		 2033 case KVM_CAP_XCRS:
2034 r = cpu_has_xsave;
2035 break;
92a1f12d
JR		 2036 case KVM_CAP_TSC_CONTROL:
2037 r = kvm_has_tsc_control;
2038 break;
018d00d2
ZX		 2039 default:
2040 r = 0;
2041 break;
2042 }
2043 return r;
2044
2045}
2046
043405e1
CO		 2047long kvm_arch_dev_ioctl(struct file *filp,
2048 unsigned int ioctl, unsigned long arg)
2049{
2050 void __user *argp = (void __user *)arg;
2051 long r;
2052
2053 switch (ioctl) {
2054 case KVM_GET_MSR_INDEX_LIST: {
2055 struct kvm_msr_list __user *user_msr_list = argp;
2056 struct kvm_msr_list msr_list;
2057 unsigned n;
2058
2059 r = -EFAULT;
2060 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2061 goto out;
2062 n = msr_list.nmsrs;
2063 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2064 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2065 goto out;
2066 r = -E2BIG;
e125e7b6 2067 if (n < msr_list.nmsrs)
043405e1
CO		 2068 goto out;
2069 r = -EFAULT;
2070 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2071 num_msrs_to_save * sizeof(u32)))
2072 goto out;
e125e7b6 2073 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2074 &emulated_msrs,
2075 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2076 goto out;
2077 r = 0;
2078 break;
2079 }
674eea0f
AK		 2080 case KVM_GET_SUPPORTED_CPUID: {
2081 struct kvm_cpuid2 __user *cpuid_arg = argp;
2082 struct kvm_cpuid2 cpuid;
2083
2084 r = -EFAULT;
2085 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2086 goto out;
2087 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 2088 cpuid_arg->entries);
674eea0f
AK		 2089 if (r)
2090 goto out;
2091
2092 r = -EFAULT;
2093 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2094 goto out;
2095 r = 0;
2096 break;
2097 }
890ca9ae
HY		 2098 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2099 u64 mce_cap;
2100
2101 mce_cap = KVM_MCE_CAP_SUPPORTED;
2102 r = -EFAULT;
2103 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2104 goto out;
2105 r = 0;
2106 break;
2107 }
043405e1
CO		 2108 default:
2109 r = -EINVAL;
2110 }
2111out:
2112 return r;
2113}
2114
f5f48ee1
SY		 2115static void wbinvd_ipi(void *garbage)
2116{
2117 wbinvd();
2118}
2119
2120static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2121{
2122 return vcpu->kvm->arch.iommu_domain &&
2123 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2124}
2125
313a3dc7
CO		 2126void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2127{
f5f48ee1
SY		 2128 /* Address WBINVD may be executed by guest */
2129 if (need_emulate_wbinvd(vcpu)) {
2130 if (kvm_x86_ops->has_wbinvd_exit())
2131 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2132 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2133 smp_call_function_single(vcpu->cpu,
2134 wbinvd_ipi, NULL, 1);
2135 }
2136
313a3dc7 2137 kvm_x86_ops->vcpu_load(vcpu, cpu);
48434c20 2138 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
e48672fa 2139 /* Make sure TSC doesn't go backwards */
8f6055cb
JR		 2140 s64 tsc_delta;
2141 u64 tsc;
2142
2143 kvm_get_msr(vcpu, MSR_IA32_TSC, &tsc);
2144 tsc_delta = !vcpu->arch.last_guest_tsc ? 0 :
2145 tsc - vcpu->arch.last_guest_tsc;
2146
e48672fa
ZA		 2147 if (tsc_delta < 0)
2148 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2149 if (check_tsc_unstable()) {
e48672fa 2150 kvm_x86_ops->adjust_tsc_offset(vcpu, -tsc_delta);
c285545f 2151 vcpu->arch.tsc_catchup = 1;
c285545f 2152 }
1aa8ceef 2153 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2154 if (vcpu->cpu != cpu)
2155 kvm_migrate_timers(vcpu);
e48672fa 2156 vcpu->cpu = cpu;
6b7d7e76 2157 }
313a3dc7
CO		 2158}
2159
2160void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2161{
02daab21 2162 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2163 kvm_put_guest_fpu(vcpu);
7c4c0f4f 2164 kvm_get_msr(vcpu, MSR_IA32_TSC, &vcpu->arch.last_guest_tsc);
313a3dc7
CO		 2165}
2166
07716717 2167static int is_efer_nx(void)
313a3dc7 2168{
e286e86e 2169 unsigned long long efer = 0;
313a3dc7 2170
e286e86e 2171 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 2172 return efer & EFER_NX;
2173}
2174
2175static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
2176{
2177 int i;
2178 struct kvm_cpuid_entry2 *e, *entry;
2179
313a3dc7 2180 entry = NULL;
ad312c7c
ZX		 2181 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
2182 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 2183 if (e->function == 0x80000001) {
2184 entry = e;
2185 break;
2186 }
2187 }
07716717 2188 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 2189 entry->edx &= ~(1 << 20);
2190 printk(KERN_INFO "kvm: guest NX capability removed\n");
2191 }
2192}
2193
07716717 2194/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 2195static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
2196 struct kvm_cpuid *cpuid,
2197 struct kvm_cpuid_entry __user *entries)
07716717
DK		 2198{
2199 int r, i;
2200 struct kvm_cpuid_entry *cpuid_entries;
2201
2202 r = -E2BIG;
2203 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2204 goto out;
2205 r = -ENOMEM;
2206 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
2207 if (!cpuid_entries)
2208 goto out;
2209 r = -EFAULT;
2210 if (copy_from_user(cpuid_entries, entries,
2211 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
2212 goto out_free;
2213 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 2214 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
2215 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
2216 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
2217 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
2218 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
2219 vcpu->arch.cpuid_entries[i].index = 0;
2220 vcpu->arch.cpuid_entries[i].flags = 0;
2221 vcpu->arch.cpuid_entries[i].padding[0] = 0;
2222 vcpu->arch.cpuid_entries[i].padding[1] = 0;
2223 vcpu->arch.cpuid_entries[i].padding[2] = 0;
2224 }
2225 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 2226 cpuid_fix_nx_cap(vcpu);
2227 r = 0;
fc61b800 2228 kvm_apic_set_version(vcpu);
0e851880 2229 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 2230 update_cpuid(vcpu);
07716717
DK		 2231
2232out_free:
2233 vfree(cpuid_entries);
2234out:
2235 return r;
2236}
2237
2238static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 2239 struct kvm_cpuid2 *cpuid,
2240 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 2241{
2242 int r;
2243
2244 r = -E2BIG;
2245 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2246 goto out;
2247 r = -EFAULT;
ad312c7c 2248 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 2249 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 2250 goto out;
ad312c7c 2251 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 2252 kvm_apic_set_version(vcpu);
0e851880 2253 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 2254 update_cpuid(vcpu);
313a3dc7
CO		 2255 return 0;
2256
2257out:
2258 return r;
2259}
2260
07716717 2261static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 2262 struct kvm_cpuid2 *cpuid,
2263 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2264{
2265 int r;
2266
2267 r = -E2BIG;
ad312c7c 2268 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 2269 goto out;
2270 r = -EFAULT;
ad312c7c 2271 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 2272 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2273 goto out;
2274 return 0;
2275
2276out:
ad312c7c 2277 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 2278 return r;
2279}
2280
945ee35e
AK		 2281static void cpuid_mask(u32 *word, int wordnum)
2282{
2283 *word &= boot_cpu_data.x86_capability[wordnum];
2284}
2285
07716717 2286static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 2287 u32 index)
07716717
DK		 2288{
2289 entry->function = function;
2290 entry->index = index;
2291 cpuid_count(entry->function, entry->index,
19355475 2292 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 2293 entry->flags = 0;
2294}
2295
24c82e57
AK		 2296static bool supported_xcr0_bit(unsigned bit)
2297{
2298 u64 mask = ((u64)1 << bit);
2299
2300 return mask & (XSTATE_FP | XSTATE_SSE | XSTATE_YMM) & host_xcr0;
2301}
2302
7faa4ee1
AK		 2303#define F(x) bit(X86_FEATURE_##x)
2304
07716717
DK		 2305static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
2306 u32 index, int *nent, int maxnent)
2307{
7faa4ee1 2308 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 2309#ifdef CONFIG_X86_64
17cc3935
SY		 2310 unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
2311 ? F(GBPAGES) : 0;
7faa4ee1
AK		 2312 unsigned f_lm = F(LM);
2313#else
17cc3935 2314 unsigned f_gbpages = 0;
7faa4ee1 2315 unsigned f_lm = 0;
07716717 2316#endif
4e47c7a6 2317 unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
7faa4ee1
AK		 2318
2319 /* cpuid 1.edx */
2320 const u32 kvm_supported_word0_x86_features =
2321 F(FPU) | F(VME) | F(DE) | F(PSE) |
2322 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2323 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
2324 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2325 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
2326 0 /* Reserved, DS, ACPI */ | F(MMX) |
2327 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
2328 0 /* HTT, TM, Reserved, PBE */;
2329 /* cpuid 0x80000001.edx */
2330 const u32 kvm_supported_word1_x86_features =
2331 F(FPU) | F(VME) | F(DE) | F(PSE) |
2332 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2333 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
2334 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2335 F(PAT) | F(PSE36) | 0 /* Reserved */ |
2336 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
4e47c7a6 2337 F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
7faa4ee1
AK		 2338 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
2339 /* cpuid 1.ecx */
2340 const u32 kvm_supported_word4_x86_features =
6c3f6041 2341 F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ |
d149c731
AK		 2342 0 /* DS-CPL, VMX, SMX, EST */ |
2343 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
2344 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
2345 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 2346 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
6d886fd0
AP		 2347 0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) |
2348 F(F16C);
7faa4ee1 2349 /* cpuid 0x80000001.ecx */
07716717 2350 const u32 kvm_supported_word6_x86_features =
4c62a2dc 2351 F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ |
7faa4ee1 2352 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
7ef8aa72 2353 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(XOP) |
6d886fd0 2354 0 /* SKINIT, WDT, LWP */ | F(FMA4) | F(TBM);
07716717 2355
4429d5dc
B		 2356 /* cpuid 0xC0000001.edx */
2357 const u32 kvm_supported_word5_x86_features =
2358 F(XSTORE) | F(XSTORE_EN) | F(XCRYPT) | F(XCRYPT_EN) |
2359 F(ACE2) | F(ACE2_EN) | F(PHE) | F(PHE_EN) |
2360 F(PMM) | F(PMM_EN);
2361
611c120f
YW		 2362 /* cpuid 7.0.ebx */
2363 const u32 kvm_supported_word9_x86_features =
2364 F(SMEP);
2365
19355475 2366 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 2367 get_cpu();
2368 do_cpuid_1_ent(entry, function, index);
2369 ++*nent;
2370
2371 switch (function) {
2372 case 0:
2acf923e 2373 entry->eax = min(entry->eax, (u32)0xd);
07716717
DK		 2374 break;
2375 case 1:
2376 entry->edx &= kvm_supported_word0_x86_features;
945ee35e 2377 cpuid_mask(&entry->edx, 0);
7faa4ee1 2378 entry->ecx &= kvm_supported_word4_x86_features;
945ee35e 2379 cpuid_mask(&entry->ecx, 4);
0d1de2d9
GN		 2380 /* we support x2apic emulation even if host does not support
2381 * it since we emulate x2apic in software */
2382 entry->ecx |= F(X2APIC);
07716717
DK		 2383 break;
2384 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
2385 * may return different values. This forces us to get_cpu() before
2386 * issuing the first command, and also to emulate this annoying behavior
2387 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
2388 case 2: {
2389 int t, times = entry->eax & 0xff;
2390
2391 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 2392 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 2393 for (t = 1; t < times && *nent < maxnent; ++t) {
2394 do_cpuid_1_ent(&entry[t], function, 0);
2395 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
2396 ++*nent;
2397 }
2398 break;
2399 }
611c120f 2400 /* function 4 has additional index. */
07716717 2401 case 4: {
14af3f3c 2402 int i, cache_type;
07716717
DK		 2403
2404 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2405 /* read more entries until cache_type is zero */
14af3f3c
HH		 2406 for (i = 1; *nent < maxnent; ++i) {
2407 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 2408 if (!cache_type)
2409 break;
14af3f3c
HH		 2410 do_cpuid_1_ent(&entry[i], function, i);
2411 entry[i].flags |=
07716717
DK		 2412 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2413 ++*nent;
2414 }
2415 break;
2416 }
611c120f
YW		 2417 case 7: {
2418 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2419 /* Mask ebx against host capbability word 9 */
2420 if (index == 0) {
2421 entry->ebx &= kvm_supported_word9_x86_features;
2422 cpuid_mask(&entry->ebx, 9);
2423 } else
2424 entry->ebx = 0;
2425 entry->eax = 0;
2426 entry->ecx = 0;
2427 entry->edx = 0;
2428 break;
2429 }
24c82e57
AK		 2430 case 9:
2431 break;
611c120f 2432 /* function 0xb has additional index. */
07716717 2433 case 0xb: {
14af3f3c 2434 int i, level_type;
07716717
DK		 2435
2436 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2437 /* read more entries until level_type is zero */
14af3f3c 2438 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 2439 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 2440 if (!level_type)
2441 break;
14af3f3c
HH		 2442 do_cpuid_1_ent(&entry[i], function, i);
2443 entry[i].flags |=
07716717
DK		 2444 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2445 ++*nent;
2446 }
2447 break;
2448 }
2acf923e
DC		 2449 case 0xd: {
2450 int i;
2451
2452 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
20800bc9 2453 for (i = 1; *nent < maxnent && i < 64; ++i) {
24c82e57 2454 if (entry[i].eax == 0 || !supported_xcr0_bit(i))
20800bc9 2455 continue;
2acf923e
DC		 2456 do_cpuid_1_ent(&entry[i], function, i);
2457 entry[i].flags |=
2458 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2459 ++*nent;
2460 }
2461 break;
2462 }
84478c82
GC		 2463 case KVM_CPUID_SIGNATURE: {
2464 char signature[12] = "KVMKVMKVM\0\0";
2465 u32 *sigptr = (u32 *)signature;
2466 entry->eax = 0;
2467 entry->ebx = sigptr[0];
2468 entry->ecx = sigptr[1];
2469 entry->edx = sigptr[2];
2470 break;
2471 }
2472 case KVM_CPUID_FEATURES:
2473 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) |
2474 (1 << KVM_FEATURE_NOP_IO_DELAY) |
371bcf64 2475 (1 << KVM_FEATURE_CLOCKSOURCE2) |
32918924 2476 (1 << KVM_FEATURE_ASYNC_PF) |
371bcf64 2477 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
84478c82
GC		 2478 entry->ebx = 0;
2479 entry->ecx = 0;
2480 entry->edx = 0;
2481 break;
07716717
DK		 2482 case 0x80000000:
2483 entry->eax = min(entry->eax, 0x8000001a);
2484 break;
2485 case 0x80000001:
2486 entry->edx &= kvm_supported_word1_x86_features;
945ee35e 2487 cpuid_mask(&entry->edx, 1);
07716717 2488 entry->ecx &= kvm_supported_word6_x86_features;
945ee35e 2489 cpuid_mask(&entry->ecx, 6);
07716717 2490 break;
24c82e57
AK		 2491 case 0x80000008: {
2492 unsigned g_phys_as = (entry->eax >> 16) & 0xff;
2493 unsigned virt_as = max((entry->eax >> 8) & 0xff, 48U);
2494 unsigned phys_as = entry->eax & 0xff;
2495
2496 if (!g_phys_as)
2497 g_phys_as = phys_as;
2498 entry->eax = g_phys_as | (virt_as << 8);
2499 entry->ebx = entry->edx = 0;
2500 break;
2501 }
2502 case 0x80000019:
2503 entry->ecx = entry->edx = 0;
2504 break;
2505 case 0x8000001a:
2506 break;
2507 case 0x8000001d:
2508 break;
4429d5dc
B		 2509 /*Add support for Centaur's CPUID instruction*/
2510 case 0xC0000000:
2511 /*Just support up to 0xC0000004 now*/
2512 entry->eax = min(entry->eax, 0xC0000004);
2513 break;
2514 case 0xC0000001:
2515 entry->edx &= kvm_supported_word5_x86_features;
2516 cpuid_mask(&entry->edx, 5);
2517 break;
24c82e57
AK		 2518 case 3: /* Processor serial number */
2519 case 5: /* MONITOR/MWAIT */
2520 case 6: /* Thermal management */
2521 case 0xA: /* Architectural Performance Monitoring */
2522 case 0x80000007: /* Advanced power management */
4429d5dc
B		 2523 case 0xC0000002:
2524 case 0xC0000003:
2525 case 0xC0000004:
24c82e57
AK		 2526 default:
2527 entry->eax = entry->ebx = entry->ecx = entry->edx = 0;
4429d5dc 2528 break;
07716717 2529 }
d4330ef2
JR		 2530
2531 kvm_x86_ops->set_supported_cpuid(function, entry);
2532
07716717
DK		 2533 put_cpu();
2534}
2535
7faa4ee1
AK		 2536#undef F
2537
674eea0f 2538static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 2539 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2540{
2541 struct kvm_cpuid_entry2 *cpuid_entries;
2542 int limit, nent = 0, r = -E2BIG;
2543 u32 func;
2544
2545 if (cpuid->nent < 1)
2546 goto out;
6a544355
AK		 2547 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2548 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
07716717
DK		 2549 r = -ENOMEM;
2550 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
2551 if (!cpuid_entries)
2552 goto out;
2553
2554 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
2555 limit = cpuid_entries[0].eax;
2556 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
2557 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2558 &nent, cpuid->nent);
07716717
DK		 2559 r = -E2BIG;
2560 if (nent >= cpuid->nent)
2561 goto out_free;
2562
2563 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
2564 limit = cpuid_entries[nent - 1].eax;
2565 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
2566 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2567 &nent, cpuid->nent);
84478c82
GC		 2568
2569
2570
2571 r = -E2BIG;
2572 if (nent >= cpuid->nent)
2573 goto out_free;
2574
4429d5dc
B		 2575 /* Add support for Centaur's CPUID instruction. */
2576 if (boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR) {
2577 do_cpuid_ent(&cpuid_entries[nent], 0xC0000000, 0,
2578 &nent, cpuid->nent);
2579
2580 r = -E2BIG;
2581 if (nent >= cpuid->nent)
2582 goto out_free;
2583
2584 limit = cpuid_entries[nent - 1].eax;
2585 for (func = 0xC0000001;
2586 func <= limit && nent < cpuid->nent; ++func)
2587 do_cpuid_ent(&cpuid_entries[nent], func, 0,
2588 &nent, cpuid->nent);
2589
2590 r = -E2BIG;
2591 if (nent >= cpuid->nent)
2592 goto out_free;
2593 }
2594
84478c82
GC		 2595 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_SIGNATURE, 0, &nent,
2596 cpuid->nent);
2597
2598 r = -E2BIG;
2599 if (nent >= cpuid->nent)
2600 goto out_free;
2601
2602 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_FEATURES, 0, &nent,
2603 cpuid->nent);
2604
cb007648
MM		 2605 r = -E2BIG;
2606 if (nent >= cpuid->nent)
2607 goto out_free;
2608
07716717
DK		 2609 r = -EFAULT;
2610 if (copy_to_user(entries, cpuid_entries,
19355475 2611 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2612 goto out_free;
2613 cpuid->nent = nent;
2614 r = 0;
2615
2616out_free:
2617 vfree(cpuid_entries);
2618out:
2619 return r;
2620}
2621
313a3dc7
CO		 2622static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2623 struct kvm_lapic_state *s)
2624{
ad312c7c 2625 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2626
2627 return 0;
2628}
2629
2630static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2631 struct kvm_lapic_state *s)
2632{
ad312c7c 2633 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 2634 kvm_apic_post_state_restore(vcpu);
cb142eb7 2635 update_cr8_intercept(vcpu);
313a3dc7
CO		 2636
2637 return 0;
2638}
2639
f77bc6a4
ZX		 2640static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2641 struct kvm_interrupt *irq)
2642{
2643 if (irq->irq < 0 || irq->irq >= 256)
2644 return -EINVAL;
2645 if (irqchip_in_kernel(vcpu->kvm))
2646 return -ENXIO;
f77bc6a4 2647
66fd3f7f 2648 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2649 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2650
f77bc6a4
ZX		 2651 return 0;
2652}
2653
c4abb7c9
JK		 2654static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2655{
c4abb7c9 2656 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2657
2658 return 0;
2659}
2660
b209749f
AK		 2661static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2662 struct kvm_tpr_access_ctl *tac)
2663{
2664 if (tac->flags)
2665 return -EINVAL;
2666 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2667 return 0;
2668}
2669
890ca9ae
HY		 2670static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2671 u64 mcg_cap)
2672{
2673 int r;
2674 unsigned bank_num = mcg_cap & 0xff, bank;
2675
2676 r = -EINVAL;
a9e38c3e 2677 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2678 goto out;
2679 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2680 goto out;
2681 r = 0;
2682 vcpu->arch.mcg_cap = mcg_cap;
2683 /* Init IA32_MCG_CTL to all 1s */
2684 if (mcg_cap & MCG_CTL_P)
2685 vcpu->arch.mcg_ctl = ~(u64)0;
2686 /* Init IA32_MCi_CTL to all 1s */
2687 for (bank = 0; bank < bank_num; bank++)
2688 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2689out:
2690 return r;
2691}
2692
2693static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2694 struct kvm_x86_mce *mce)
2695{
2696 u64 mcg_cap = vcpu->arch.mcg_cap;
2697 unsigned bank_num = mcg_cap & 0xff;
2698 u64 *banks = vcpu->arch.mce_banks;
2699
2700 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2701 return -EINVAL;
2702 /*
2703 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2704 * reporting is disabled
2705 */
2706 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2707 vcpu->arch.mcg_ctl != ~(u64)0)
2708 return 0;
2709 banks += 4 * mce->bank;
2710 /*
2711 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2712 * reporting is disabled for the bank
2713 */
2714 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2715 return 0;
2716 if (mce->status & MCI_STATUS_UC) {
2717 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2718 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2719 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2720 return 0;
2721 }
2722 if (banks[1] & MCI_STATUS_VAL)
2723 mce->status |= MCI_STATUS_OVER;
2724 banks[2] = mce->addr;
2725 banks[3] = mce->misc;
2726 vcpu->arch.mcg_status = mce->mcg_status;
2727 banks[1] = mce->status;
2728 kvm_queue_exception(vcpu, MC_VECTOR);
2729 } else if (!(banks[1] & MCI_STATUS_VAL)
2730 || !(banks[1] & MCI_STATUS_UC)) {
2731 if (banks[1] & MCI_STATUS_VAL)
2732 mce->status |= MCI_STATUS_OVER;
2733 banks[2] = mce->addr;
2734 banks[3] = mce->misc;
2735 banks[1] = mce->status;
2736 } else
2737 banks[1] |= MCI_STATUS_OVER;
2738 return 0;
2739}
2740
3cfc3092
JK		 2741static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2742 struct kvm_vcpu_events *events)
2743{
03b82a30
JK		 2744 events->exception.injected =
2745 vcpu->arch.exception.pending &&
2746 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2747 events->exception.nr = vcpu->arch.exception.nr;
2748 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2749 events->exception.pad = 0;
3cfc3092
JK		 2750 events->exception.error_code = vcpu->arch.exception.error_code;
2751
03b82a30
JK		 2752 events->interrupt.injected =
2753 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2754 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2755 events->interrupt.soft = 0;
48005f64
JK		 2756 events->interrupt.shadow =
2757 kvm_x86_ops->get_interrupt_shadow(vcpu,
2758 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2759
2760 events->nmi.injected = vcpu->arch.nmi_injected;
2761 events->nmi.pending = vcpu->arch.nmi_pending;
2762 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2763 events->nmi.pad = 0;
3cfc3092
JK		 2764
2765 events->sipi_vector = vcpu->arch.sipi_vector;
2766
dab4b911 2767 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2768 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2769 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 2770 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2771}
2772
2773static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2774 struct kvm_vcpu_events *events)
2775{
dab4b911 2776 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2777 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2778 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2779 return -EINVAL;
2780
3cfc3092
JK		 2781 vcpu->arch.exception.pending = events->exception.injected;
2782 vcpu->arch.exception.nr = events->exception.nr;
2783 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2784 vcpu->arch.exception.error_code = events->exception.error_code;
2785
2786 vcpu->arch.interrupt.pending = events->interrupt.injected;
2787 vcpu->arch.interrupt.nr = events->interrupt.nr;
2788 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2789 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2790 kvm_x86_ops->set_interrupt_shadow(vcpu,
2791 events->interrupt.shadow);
3cfc3092
JK		 2792
2793 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2794 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2795 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2796 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2797
dab4b911
JK		 2798 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2799 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092 2800
3842d135
AK		 2801 kvm_make_request(KVM_REQ_EVENT, vcpu);
2802
3cfc3092
JK		 2803 return 0;
2804}
2805
a1efbe77
JK		 2806static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2807 struct kvm_debugregs *dbgregs)
2808{
a1efbe77
JK		 2809 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2810 dbgregs->dr6 = vcpu->arch.dr6;
2811 dbgregs->dr7 = vcpu->arch.dr7;
2812 dbgregs->flags = 0;
97e69aa6 2813 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 2814}
2815
2816static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2817 struct kvm_debugregs *dbgregs)
2818{
2819 if (dbgregs->flags)
2820 return -EINVAL;
2821
a1efbe77
JK		 2822 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2823 vcpu->arch.dr6 = dbgregs->dr6;
2824 vcpu->arch.dr7 = dbgregs->dr7;
2825
a1efbe77
JK		 2826 return 0;
2827}
2828
2d5b5a66
SY		 2829static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2830 struct kvm_xsave *guest_xsave)
2831{
2832 if (cpu_has_xsave)
2833 memcpy(guest_xsave->region,
2834 &vcpu->arch.guest_fpu.state->xsave,
f45755b8 2835 xstate_size);
2d5b5a66
SY		 2836 else {
2837 memcpy(guest_xsave->region,
2838 &vcpu->arch.guest_fpu.state->fxsave,
2839 sizeof(struct i387_fxsave_struct));
2840 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2841 XSTATE_FPSSE;
2842 }
2843}
2844
2845static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2846 struct kvm_xsave *guest_xsave)
2847{
2848 u64 xstate_bv =
2849 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2850
2851 if (cpu_has_xsave)
2852 memcpy(&vcpu->arch.guest_fpu.state->xsave,
f45755b8 2853 guest_xsave->region, xstate_size);
2d5b5a66
SY		 2854 else {
2855 if (xstate_bv & ~XSTATE_FPSSE)
2856 return -EINVAL;
2857 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2858 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2859 }
2860 return 0;
2861}
2862
2863static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2864 struct kvm_xcrs *guest_xcrs)
2865{
2866 if (!cpu_has_xsave) {
2867 guest_xcrs->nr_xcrs = 0;
2868 return;
2869 }
2870
2871 guest_xcrs->nr_xcrs = 1;
2872 guest_xcrs->flags = 0;
2873 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2874 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2875}
2876
2877static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2878 struct kvm_xcrs *guest_xcrs)
2879{
2880 int i, r = 0;
2881
2882 if (!cpu_has_xsave)
2883 return -EINVAL;
2884
2885 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2886 return -EINVAL;
2887
2888 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2889 /* Only support XCR0 currently */
2890 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2891 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2892 guest_xcrs->xcrs[0].value);
2893 break;
2894 }
2895 if (r)
2896 r = -EINVAL;
2897 return r;
2898}
2899
313a3dc7
CO		 2900long kvm_arch_vcpu_ioctl(struct file *filp,
2901 unsigned int ioctl, unsigned long arg)
2902{
2903 struct kvm_vcpu *vcpu = filp->private_data;
2904 void __user *argp = (void __user *)arg;
2905 int r;
d1ac91d8
AK		 2906 union {
2907 struct kvm_lapic_state *lapic;
2908 struct kvm_xsave *xsave;
2909 struct kvm_xcrs *xcrs;
2910 void *buffer;
2911 } u;
2912
2913 u.buffer = NULL;
313a3dc7
CO		 2914 switch (ioctl) {
2915 case KVM_GET_LAPIC: {
2204ae3c
MT		 2916 r = -EINVAL;
2917 if (!vcpu->arch.apic)
2918 goto out;
d1ac91d8 2919 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2920
b772ff36 2921 r = -ENOMEM;
d1ac91d8 2922 if (!u.lapic)
b772ff36 2923 goto out;
d1ac91d8 2924 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 2925 if (r)
2926 goto out;
2927 r = -EFAULT;
d1ac91d8 2928 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2929 goto out;
2930 r = 0;
2931 break;
2932 }
2933 case KVM_SET_LAPIC: {
2204ae3c
MT		 2934 r = -EINVAL;
2935 if (!vcpu->arch.apic)
2936 goto out;
d1ac91d8 2937 u.lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
b772ff36 2938 r = -ENOMEM;
d1ac91d8 2939 if (!u.lapic)
b772ff36 2940 goto out;
313a3dc7 2941 r = -EFAULT;
d1ac91d8 2942 if (copy_from_user(u.lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 2943 goto out;
d1ac91d8 2944 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 2945 if (r)
2946 goto out;
2947 r = 0;
2948 break;
2949 }
f77bc6a4
ZX		 2950 case KVM_INTERRUPT: {
2951 struct kvm_interrupt irq;
2952
2953 r = -EFAULT;
2954 if (copy_from_user(&irq, argp, sizeof irq))
2955 goto out;
2956 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2957 if (r)
2958 goto out;
2959 r = 0;
2960 break;
2961 }
c4abb7c9
JK		 2962 case KVM_NMI: {
2963 r = kvm_vcpu_ioctl_nmi(vcpu);
2964 if (r)
2965 goto out;
2966 r = 0;
2967 break;
2968 }
313a3dc7
CO		 2969 case KVM_SET_CPUID: {
2970 struct kvm_cpuid __user *cpuid_arg = argp;
2971 struct kvm_cpuid cpuid;
2972
2973 r = -EFAULT;
2974 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2975 goto out;
2976 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2977 if (r)
2978 goto out;
2979 break;
2980 }
07716717
DK		 2981 case KVM_SET_CPUID2: {
2982 struct kvm_cpuid2 __user *cpuid_arg = argp;
2983 struct kvm_cpuid2 cpuid;
2984
2985 r = -EFAULT;
2986 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2987 goto out;
2988 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2989 cpuid_arg->entries);
07716717
DK		 2990 if (r)
2991 goto out;
2992 break;
2993 }
2994 case KVM_GET_CPUID2: {
2995 struct kvm_cpuid2 __user *cpuid_arg = argp;
2996 struct kvm_cpuid2 cpuid;
2997
2998 r = -EFAULT;
2999 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3000 goto out;
3001 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3002 cpuid_arg->entries);
07716717
DK		 3003 if (r)
3004 goto out;
3005 r = -EFAULT;
3006 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3007 goto out;
3008 r = 0;
3009 break;
3010 }
313a3dc7
CO		 3011 case KVM_GET_MSRS:
3012 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3013 break;
3014 case KVM_SET_MSRS:
3015 r = msr_io(vcpu, argp, do_set_msr, 0);
3016 break;
b209749f
AK		 3017 case KVM_TPR_ACCESS_REPORTING: {
3018 struct kvm_tpr_access_ctl tac;
3019
3020 r = -EFAULT;
3021 if (copy_from_user(&tac, argp, sizeof tac))
3022 goto out;
3023 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3024 if (r)
3025 goto out;
3026 r = -EFAULT;
3027 if (copy_to_user(argp, &tac, sizeof tac))
3028 goto out;
3029 r = 0;
3030 break;
3031 };
b93463aa
AK		 3032 case KVM_SET_VAPIC_ADDR: {
3033 struct kvm_vapic_addr va;
3034
3035 r = -EINVAL;
3036 if (!irqchip_in_kernel(vcpu->kvm))
3037 goto out;
3038 r = -EFAULT;
3039 if (copy_from_user(&va, argp, sizeof va))
3040 goto out;
3041 r = 0;
3042 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3043 break;
3044 }
890ca9ae
HY		 3045 case KVM_X86_SETUP_MCE: {
3046 u64 mcg_cap;
3047
3048 r = -EFAULT;
3049 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3050 goto out;
3051 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3052 break;
3053 }
3054 case KVM_X86_SET_MCE: {
3055 struct kvm_x86_mce mce;
3056
3057 r = -EFAULT;
3058 if (copy_from_user(&mce, argp, sizeof mce))
3059 goto out;
3060 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3061 break;
3062 }
3cfc3092
JK		 3063 case KVM_GET_VCPU_EVENTS: {
3064 struct kvm_vcpu_events events;
3065
3066 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3067
3068 r = -EFAULT;
3069 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3070 break;
3071 r = 0;
3072 break;
3073 }
3074 case KVM_SET_VCPU_EVENTS: {
3075 struct kvm_vcpu_events events;
3076
3077 r = -EFAULT;
3078 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3079 break;
3080
3081 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3082 break;
3083 }
a1efbe77
JK		 3084 case KVM_GET_DEBUGREGS: {
3085 struct kvm_debugregs dbgregs;
3086
3087 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3088
3089 r = -EFAULT;
3090 if (copy_to_user(argp, &dbgregs,
3091 sizeof(struct kvm_debugregs)))
3092 break;
3093 r = 0;
3094 break;
3095 }
3096 case KVM_SET_DEBUGREGS: {
3097 struct kvm_debugregs dbgregs;
3098
3099 r = -EFAULT;
3100 if (copy_from_user(&dbgregs, argp,
3101 sizeof(struct kvm_debugregs)))
3102 break;
3103
3104 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3105 break;
3106 }
2d5b5a66 3107 case KVM_GET_XSAVE: {
d1ac91d8 3108 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3109 r = -ENOMEM;
d1ac91d8 3110 if (!u.xsave)
2d5b5a66
SY		 3111 break;
3112
d1ac91d8 3113 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3114
3115 r = -EFAULT;
d1ac91d8 3116 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3117 break;
3118 r = 0;
3119 break;
3120 }
3121 case KVM_SET_XSAVE: {
d1ac91d8 3122 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3123 r = -ENOMEM;
d1ac91d8 3124 if (!u.xsave)
2d5b5a66
SY		 3125 break;
3126
3127 r = -EFAULT;
d1ac91d8 3128 if (copy_from_user(u.xsave, argp, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3129 break;
3130
d1ac91d8 3131 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3132 break;
3133 }
3134 case KVM_GET_XCRS: {
d1ac91d8 3135 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3136 r = -ENOMEM;
d1ac91d8 3137 if (!u.xcrs)
2d5b5a66
SY		 3138 break;
3139
d1ac91d8 3140 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3141
3142 r = -EFAULT;
d1ac91d8 3143 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3144 sizeof(struct kvm_xcrs)))
3145 break;
3146 r = 0;
3147 break;
3148 }
3149 case KVM_SET_XCRS: {
d1ac91d8 3150 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3151 r = -ENOMEM;
d1ac91d8 3152 if (!u.xcrs)
2d5b5a66
SY		 3153 break;
3154
3155 r = -EFAULT;
d1ac91d8 3156 if (copy_from_user(u.xcrs, argp,
2d5b5a66
SY		 3157 sizeof(struct kvm_xcrs)))
3158 break;
3159
d1ac91d8 3160 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3161 break;
3162 }
92a1f12d
JR		 3163 case KVM_SET_TSC_KHZ: {
3164 u32 user_tsc_khz;
3165
3166 r = -EINVAL;
3167 if (!kvm_has_tsc_control)
3168 break;
3169
3170 user_tsc_khz = (u32)arg;
3171
3172 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3173 goto out;
3174
3175 kvm_x86_ops->set_tsc_khz(vcpu, user_tsc_khz);
3176
3177 r = 0;
3178 goto out;
3179 }
3180 case KVM_GET_TSC_KHZ: {
3181 r = -EIO;
3182 if (check_tsc_unstable())
3183 goto out;
3184
3185 r = vcpu_tsc_khz(vcpu);
3186
3187 goto out;
3188 }
313a3dc7
CO		 3189 default:
3190 r = -EINVAL;
3191 }
3192out:
d1ac91d8 3193 kfree(u.buffer);
313a3dc7
CO		 3194 return r;
3195}
3196
1fe779f8
CO		 3197static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3198{
3199 int ret;
3200
3201 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3202 return -1;
3203 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3204 return ret;
3205}
3206
b927a3ce
SY		 3207static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3208 u64 ident_addr)
3209{
3210 kvm->arch.ept_identity_map_addr = ident_addr;
3211 return 0;
3212}
3213
1fe779f8
CO		 3214static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3215 u32 kvm_nr_mmu_pages)
3216{
3217 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3218 return -EINVAL;
3219
79fac95e 3220 mutex_lock(&kvm->slots_lock);
7c8a83b7 3221 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 3222
3223 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3224 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3225
7c8a83b7 3226 spin_unlock(&kvm->mmu_lock);
79fac95e 3227 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3228 return 0;
3229}
3230
3231static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3232{
39de71ec 3233 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3234}
3235
1fe779f8
CO		 3236static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3237{
3238 int r;
3239
3240 r = 0;
3241 switch (chip->chip_id) {
3242 case KVM_IRQCHIP_PIC_MASTER:
3243 memcpy(&chip->chip.pic,
3244 &pic_irqchip(kvm)->pics[0],
3245 sizeof(struct kvm_pic_state));
3246 break;
3247 case KVM_IRQCHIP_PIC_SLAVE:
3248 memcpy(&chip->chip.pic,
3249 &pic_irqchip(kvm)->pics[1],
3250 sizeof(struct kvm_pic_state));
3251 break;
3252 case KVM_IRQCHIP_IOAPIC:
eba0226b 3253 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3254 break;
3255 default:
3256 r = -EINVAL;
3257 break;
3258 }
3259 return r;
3260}
3261
3262static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3263{
3264 int r;
3265
3266 r = 0;
3267 switch (chip->chip_id) {
3268 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3269 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3270 memcpy(&pic_irqchip(kvm)->pics[0],
3271 &chip->chip.pic,
3272 sizeof(struct kvm_pic_state));
f4f51050 3273 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3274 break;
3275 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3276 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3277 memcpy(&pic_irqchip(kvm)->pics[1],
3278 &chip->chip.pic,
3279 sizeof(struct kvm_pic_state));
f4f51050 3280 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3281 break;
3282 case KVM_IRQCHIP_IOAPIC:
eba0226b 3283 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3284 break;
3285 default:
3286 r = -EINVAL;
3287 break;
3288 }
3289 kvm_pic_update_irq(pic_irqchip(kvm));
3290 return r;
3291}
3292
e0f63cb9
SY		 3293static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3294{
3295 int r = 0;
3296
894a9c55 3297 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3298 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3299 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3300 return r;
3301}
3302
3303static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3304{
3305 int r = 0;
3306
894a9c55 3307 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3308 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3309 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3310 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3311 return r;
3312}
3313
3314static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3315{
3316 int r = 0;
3317
3318 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3319 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3320 sizeof(ps->channels));
3321 ps->flags = kvm->arch.vpit->pit_state.flags;
3322 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3323 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3324 return r;
3325}
3326
3327static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3328{
3329 int r = 0, start = 0;
3330 u32 prev_legacy, cur_legacy;
3331 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3332 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3333 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3334 if (!prev_legacy && cur_legacy)
3335 start = 1;
3336 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3337 sizeof(kvm->arch.vpit->pit_state.channels));
3338 kvm->arch.vpit->pit_state.flags = ps->flags;
3339 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3340 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3341 return r;
3342}
3343
52d939a0
MT		 3344static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3345 struct kvm_reinject_control *control)
3346{
3347 if (!kvm->arch.vpit)
3348 return -ENXIO;
894a9c55 3349 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 3350 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 3351 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3352 return 0;
3353}
3354
5bb064dc
ZX		 3355/*
3356 * Get (and clear) the dirty memory log for a memory slot.
3357 */
3358int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
3359 struct kvm_dirty_log *log)
3360{
87bf6e7d 3361 int r, i;
5bb064dc 3362 struct kvm_memory_slot *memslot;
87bf6e7d 3363 unsigned long n;
b050b015 3364 unsigned long is_dirty = 0;
5bb064dc 3365
79fac95e 3366 mutex_lock(&kvm->slots_lock);
5bb064dc 3367
b050b015
MT		 3368 r = -EINVAL;
3369 if (log->slot >= KVM_MEMORY_SLOTS)
3370 goto out;
3371
3372 memslot = &kvm->memslots->memslots[log->slot];
3373 r = -ENOENT;
3374 if (!memslot->dirty_bitmap)
3375 goto out;
3376
87bf6e7d 3377 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3378
b050b015
MT		 3379 for (i = 0; !is_dirty && i < n/sizeof(long); i++)
3380 is_dirty = memslot->dirty_bitmap[i];
5bb064dc
ZX		 3381
3382 /* If nothing is dirty, don't bother messing with page tables. */
3383 if (is_dirty) {
b050b015 3384 struct kvm_memslots *slots, *old_slots;
914ebccd 3385 unsigned long *dirty_bitmap;
b050b015 3386
515a0127
TY		 3387 dirty_bitmap = memslot->dirty_bitmap_head;
3388 if (memslot->dirty_bitmap == dirty_bitmap)
3389 dirty_bitmap += n / sizeof(long);
914ebccd 3390 memset(dirty_bitmap, 0, n);
b050b015 3391
914ebccd
TY		 3392 r = -ENOMEM;
3393 slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
515a0127 3394 if (!slots)
914ebccd 3395 goto out;
b050b015
MT		 3396 memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
3397 slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
49c7754c 3398 slots->generation++;
b050b015
MT		 3399
3400 old_slots = kvm->memslots;
3401 rcu_assign_pointer(kvm->memslots, slots);
3402 synchronize_srcu_expedited(&kvm->srcu);
3403 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
3404 kfree(old_slots);
914ebccd 3405
edde99ce
MT		 3406 spin_lock(&kvm->mmu_lock);
3407 kvm_mmu_slot_remove_write_access(kvm, log->slot);
3408 spin_unlock(&kvm->mmu_lock);
3409
914ebccd 3410 r = -EFAULT;
515a0127 3411 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n))
914ebccd 3412 goto out;
914ebccd
TY		 3413 } else {
3414 r = -EFAULT;
3415 if (clear_user(log->dirty_bitmap, n))
3416 goto out;
5bb064dc 3417 }
b050b015 3418
5bb064dc
ZX		 3419 r = 0;
3420out:
79fac95e 3421 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3422 return r;
3423}
3424
1fe779f8
CO		 3425long kvm_arch_vm_ioctl(struct file *filp,
3426 unsigned int ioctl, unsigned long arg)
3427{
3428 struct kvm *kvm = filp->private_data;
3429 void __user *argp = (void __user *)arg;
367e1319 3430 int r = -ENOTTY;
f0d66275
DH		 3431 /*
3432 * This union makes it completely explicit to gcc-3.x
3433 * that these two variables' stack usage should be
3434 * combined, not added together.
3435 */
3436 union {
3437 struct kvm_pit_state ps;
e9f42757 3438 struct kvm_pit_state2 ps2;
c5ff41ce 3439 struct kvm_pit_config pit_config;
f0d66275 3440 } u;
1fe779f8
CO		 3441
3442 switch (ioctl) {
3443 case KVM_SET_TSS_ADDR:
3444 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3445 if (r < 0)
3446 goto out;
3447 break;
b927a3ce
SY		 3448 case KVM_SET_IDENTITY_MAP_ADDR: {
3449 u64 ident_addr;
3450
3451 r = -EFAULT;
3452 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3453 goto out;
3454 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3455 if (r < 0)
3456 goto out;
3457 break;
3458 }
1fe779f8
CO		 3459 case KVM_SET_NR_MMU_PAGES:
3460 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3461 if (r)
3462 goto out;
3463 break;
3464 case KVM_GET_NR_MMU_PAGES:
3465 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3466 break;
3ddea128
MT		 3467 case KVM_CREATE_IRQCHIP: {
3468 struct kvm_pic *vpic;
3469
3470 mutex_lock(&kvm->lock);
3471 r = -EEXIST;
3472 if (kvm->arch.vpic)
3473 goto create_irqchip_unlock;
1fe779f8 3474 r = -ENOMEM;
3ddea128
MT		 3475 vpic = kvm_create_pic(kvm);
3476 if (vpic) {
1fe779f8
CO		 3477 r = kvm_ioapic_init(kvm);
3478 if (r) {
175504cd 3479 mutex_lock(&kvm->slots_lock);
72bb2fcd
WY		 3480 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3481 &vpic->dev);
175504cd 3482 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3483 kfree(vpic);
3484 goto create_irqchip_unlock;
1fe779f8
CO		 3485 }
3486 } else
3ddea128
MT		 3487 goto create_irqchip_unlock;
3488 smp_wmb();
3489 kvm->arch.vpic = vpic;
3490 smp_wmb();
399ec807
AK		 3491 r = kvm_setup_default_irq_routing(kvm);
3492 if (r) {
175504cd 3493 mutex_lock(&kvm->slots_lock);
3ddea128 3494 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3495 kvm_ioapic_destroy(kvm);
3496 kvm_destroy_pic(kvm);
3ddea128 3497 mutex_unlock(&kvm->irq_lock);
175504cd 3498 mutex_unlock(&kvm->slots_lock);
399ec807 3499 }
3ddea128
MT		 3500 create_irqchip_unlock:
3501 mutex_unlock(&kvm->lock);
1fe779f8 3502 break;
3ddea128 3503 }
7837699f 3504 case KVM_CREATE_PIT:
c5ff41ce
JK		 3505 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3506 goto create_pit;
3507 case KVM_CREATE_PIT2:
3508 r = -EFAULT;
3509 if (copy_from_user(&u.pit_config, argp,
3510 sizeof(struct kvm_pit_config)))
3511 goto out;
3512 create_pit:
79fac95e 3513 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3514 r = -EEXIST;
3515 if (kvm->arch.vpit)
3516 goto create_pit_unlock;
7837699f 3517 r = -ENOMEM;
c5ff41ce 3518 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3519 if (kvm->arch.vpit)
3520 r = 0;
269e05e4 3521 create_pit_unlock:
79fac95e 3522 mutex_unlock(&kvm->slots_lock);
7837699f 3523 break;
4925663a 3524 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 3525 case KVM_IRQ_LINE: {
3526 struct kvm_irq_level irq_event;
3527
3528 r = -EFAULT;
3529 if (copy_from_user(&irq_event, argp, sizeof irq_event))
3530 goto out;
160d2f6c 3531 r = -ENXIO;
1fe779f8 3532 if (irqchip_in_kernel(kvm)) {
4925663a 3533 __s32 status;
4925663a
GN		 3534 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3535 irq_event.irq, irq_event.level);
4925663a 3536 if (ioctl == KVM_IRQ_LINE_STATUS) {
160d2f6c 3537 r = -EFAULT;
4925663a
GN		 3538 irq_event.status = status;
3539 if (copy_to_user(argp, &irq_event,
3540 sizeof irq_event))
3541 goto out;
3542 }
1fe779f8
CO		 3543 r = 0;
3544 }
3545 break;
3546 }
3547 case KVM_GET_IRQCHIP: {
3548 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3549 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3550
f0d66275
DH		 3551 r = -ENOMEM;
3552 if (!chip)
1fe779f8 3553 goto out;
f0d66275
DH		 3554 r = -EFAULT;
3555 if (copy_from_user(chip, argp, sizeof *chip))
3556 goto get_irqchip_out;
1fe779f8
CO		 3557 r = -ENXIO;
3558 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3559 goto get_irqchip_out;
3560 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3561 if (r)
f0d66275 3562 goto get_irqchip_out;
1fe779f8 3563 r = -EFAULT;
f0d66275
DH		 3564 if (copy_to_user(argp, chip, sizeof *chip))
3565 goto get_irqchip_out;
1fe779f8 3566 r = 0;
f0d66275
DH		 3567 get_irqchip_out:
3568 kfree(chip);
3569 if (r)
3570 goto out;
1fe779f8
CO		 3571 break;
3572 }
3573 case KVM_SET_IRQCHIP: {
3574 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3575 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3576
f0d66275
DH		 3577 r = -ENOMEM;
3578 if (!chip)
1fe779f8 3579 goto out;
f0d66275
DH		 3580 r = -EFAULT;
3581 if (copy_from_user(chip, argp, sizeof *chip))
3582 goto set_irqchip_out;
1fe779f8
CO		 3583 r = -ENXIO;
3584 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3585 goto set_irqchip_out;
3586 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3587 if (r)
f0d66275 3588 goto set_irqchip_out;
1fe779f8 3589 r = 0;
f0d66275
DH		 3590 set_irqchip_out:
3591 kfree(chip);
3592 if (r)
3593 goto out;
1fe779f8
CO		 3594 break;
3595 }
e0f63cb9 3596 case KVM_GET_PIT: {
e0f63cb9 3597 r = -EFAULT;
f0d66275 3598 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3599 goto out;
3600 r = -ENXIO;
3601 if (!kvm->arch.vpit)
3602 goto out;
f0d66275 3603 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3604 if (r)
3605 goto out;
3606 r = -EFAULT;
f0d66275 3607 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3608 goto out;
3609 r = 0;
3610 break;
3611 }
3612 case KVM_SET_PIT: {
e0f63cb9 3613 r = -EFAULT;
f0d66275 3614 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3615 goto out;
3616 r = -ENXIO;
3617 if (!kvm->arch.vpit)
3618 goto out;
f0d66275 3619 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3620 if (r)
3621 goto out;
3622 r = 0;
3623 break;
3624 }
e9f42757
BK		 3625 case KVM_GET_PIT2: {
3626 r = -ENXIO;
3627 if (!kvm->arch.vpit)
3628 goto out;
3629 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3630 if (r)
3631 goto out;
3632 r = -EFAULT;
3633 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3634 goto out;
3635 r = 0;
3636 break;
3637 }
3638 case KVM_SET_PIT2: {
3639 r = -EFAULT;
3640 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3641 goto out;
3642 r = -ENXIO;
3643 if (!kvm->arch.vpit)
3644 goto out;
3645 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3646 if (r)
3647 goto out;
3648 r = 0;
3649 break;
3650 }
52d939a0
MT		 3651 case KVM_REINJECT_CONTROL: {
3652 struct kvm_reinject_control control;
3653 r = -EFAULT;
3654 if (copy_from_user(&control, argp, sizeof(control)))
3655 goto out;
3656 r = kvm_vm_ioctl_reinject(kvm, &control);
3657 if (r)
3658 goto out;
3659 r = 0;
3660 break;
3661 }
ffde22ac
ES		 3662 case KVM_XEN_HVM_CONFIG: {
3663 r = -EFAULT;
3664 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3665 sizeof(struct kvm_xen_hvm_config)))
3666 goto out;
3667 r = -EINVAL;
3668 if (kvm->arch.xen_hvm_config.flags)
3669 goto out;
3670 r = 0;
3671 break;
3672 }
afbcf7ab 3673 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3674 struct kvm_clock_data user_ns;
3675 u64 now_ns;
3676 s64 delta;
3677
3678 r = -EFAULT;
3679 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3680 goto out;
3681
3682 r = -EINVAL;
3683 if (user_ns.flags)
3684 goto out;
3685
3686 r = 0;
395c6b0a 3687 local_irq_disable();
759379dd 3688 now_ns = get_kernel_ns();
afbcf7ab 3689 delta = user_ns.clock - now_ns;
395c6b0a 3690 local_irq_enable();
afbcf7ab
GC		 3691 kvm->arch.kvmclock_offset = delta;
3692 break;
3693 }
3694 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3695 struct kvm_clock_data user_ns;
3696 u64 now_ns;
3697
395c6b0a 3698 local_irq_disable();
759379dd 3699 now_ns = get_kernel_ns();
afbcf7ab 3700 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3701 local_irq_enable();
afbcf7ab 3702 user_ns.flags = 0;
97e69aa6 3703 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3704
3705 r = -EFAULT;
3706 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3707 goto out;
3708 r = 0;
3709 break;
3710 }
3711
1fe779f8
CO		 3712 default:
3713 ;
3714 }
3715out:
3716 return r;
3717}
3718
a16b043c 3719static void kvm_init_msr_list(void)
043405e1
CO		 3720{
3721 u32 dummy[2];
3722 unsigned i, j;
3723
e3267cbb
GC		 3724 /* skip the first msrs in the list. KVM-specific */
3725 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3726 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3727 continue;
3728 if (j < i)
3729 msrs_to_save[j] = msrs_to_save[i];
3730 j++;
3731 }
3732 num_msrs_to_save = j;
3733}
3734
bda9020e
MT		 3735static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3736 const void *v)
bbd9b64e 3737{
70252a10
AK		 3738 int handled = 0;
3739 int n;
3740
3741 do {
3742 n = min(len, 8);
3743 if (!(vcpu->arch.apic &&
3744 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3745 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3746 break;
3747 handled += n;
3748 addr += n;
3749 len -= n;
3750 v += n;
3751 } while (len);
bbd9b64e 3752
70252a10 3753 return handled;
bbd9b64e
CO		 3754}
3755
bda9020e 3756static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3757{
70252a10
AK		 3758 int handled = 0;
3759 int n;
3760
3761 do {
3762 n = min(len, 8);
3763 if (!(vcpu->arch.apic &&
3764 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3765 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3766 break;
3767 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3768 handled += n;
3769 addr += n;
3770 len -= n;
3771 v += n;
3772 } while (len);
bbd9b64e 3773
70252a10 3774 return handled;
bbd9b64e
CO		 3775}
3776
2dafc6c2
GN		 3777static void kvm_set_segment(struct kvm_vcpu *vcpu,
3778 struct kvm_segment *var, int seg)
3779{
3780 kvm_x86_ops->set_segment(vcpu, var, seg);
3781}
3782
3783void kvm_get_segment(struct kvm_vcpu *vcpu,
3784 struct kvm_segment *var, int seg)
3785{
3786 kvm_x86_ops->get_segment(vcpu, var, seg);
3787}
3788
c30a358d
JR		 3789static gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3790{
3791 return gpa;
3792}
3793
02f59dc9
JR		 3794static gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3795{
3796 gpa_t t_gpa;
ab9ae313 3797 struct x86_exception exception;
02f59dc9
JR		 3798
3799 BUG_ON(!mmu_is_nested(vcpu));
3800
3801 /* NPT walks are always user-walks */
3802 access |= PFERR_USER_MASK;
ab9ae313 3803 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
02f59dc9
JR		 3804
3805 return t_gpa;
3806}
3807
ab9ae313
AK		 3808gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3809 struct x86_exception *exception)
1871c602
GN		 3810{
3811 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 3812 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3813}
3814
ab9ae313
AK		 3815 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3816 struct x86_exception *exception)
1871c602
GN		 3817{
3818 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3819 access |= PFERR_FETCH_MASK;
ab9ae313 3820 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3821}
3822
ab9ae313
AK		 3823gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3824 struct x86_exception *exception)
1871c602
GN		 3825{
3826 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3827 access |= PFERR_WRITE_MASK;
ab9ae313 3828 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3829}
3830
3831/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 3832gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3833 struct x86_exception *exception)
1871c602 3834{
ab9ae313 3835 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 3836}
3837
3838static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3839 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 3840 struct x86_exception *exception)
bbd9b64e
CO		 3841{
3842 void *data = val;
10589a46 3843 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3844
3845 while (bytes) {
14dfe855 3846 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 3847 exception);
bbd9b64e 3848 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3849 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3850 int ret;
3851
bcc55cba 3852 if (gpa == UNMAPPED_GVA)
ab9ae313 3853 return X86EMUL_PROPAGATE_FAULT;
77c2002e 3854 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3855 if (ret < 0) {
c3cd7ffa 3856 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3857 goto out;
3858 }
bbd9b64e 3859
77c2002e
IE		 3860 bytes -= toread;
3861 data += toread;
3862 addr += toread;
bbd9b64e 3863 }
10589a46 3864out:
10589a46 3865 return r;
bbd9b64e 3866}
77c2002e 3867
1871c602 3868/* used for instruction fetching */
0f65dd70
AK		 3869static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
3870 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3871 struct x86_exception *exception)
1871c602 3872{
0f65dd70 3873 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3874 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3875
1871c602 3876 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
bcc55cba
AK		 3877 access | PFERR_FETCH_MASK,
3878 exception);
1871c602
GN		 3879}
3880
064aea77 3881int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 3882 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3883 struct x86_exception *exception)
1871c602 3884{
0f65dd70 3885 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3886 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3887
1871c602 3888 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 3889 exception);
1871c602 3890}
064aea77 3891EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 3892
0f65dd70
AK		 3893static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3894 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3895 struct x86_exception *exception)
1871c602 3896{
0f65dd70 3897 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 3898 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 3899}
3900
6a4d7550 3901int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 3902 gva_t addr, void *val,
2dafc6c2 3903 unsigned int bytes,
bcc55cba 3904 struct x86_exception *exception)
77c2002e 3905{
0f65dd70 3906 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 3907 void *data = val;
3908 int r = X86EMUL_CONTINUE;
3909
3910 while (bytes) {
14dfe855
JR		 3911 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3912 PFERR_WRITE_MASK,
ab9ae313 3913 exception);
77c2002e
IE		 3914 unsigned offset = addr & (PAGE_SIZE-1);
3915 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3916 int ret;
3917
bcc55cba 3918 if (gpa == UNMAPPED_GVA)
ab9ae313 3919 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 3920 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3921 if (ret < 0) {
c3cd7ffa 3922 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 3923 goto out;
3924 }
3925
3926 bytes -= towrite;
3927 data += towrite;
3928 addr += towrite;
3929 }
3930out:
3931 return r;
3932}
6a4d7550 3933EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 3934
0f65dd70
AK		 3935static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
3936 unsigned long addr,
bbd9b64e
CO		 3937 void *val,
3938 unsigned int bytes,
0f65dd70 3939 struct x86_exception *exception)
bbd9b64e 3940{
0f65dd70 3941 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bbd9b64e 3942 gpa_t gpa;
70252a10 3943 int handled;
bbd9b64e
CO		 3944
3945 if (vcpu->mmio_read_completed) {
3946 memcpy(val, vcpu->mmio_data, bytes);
aec51dc4
AK		 3947 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3948 vcpu->mmio_phys_addr, *(u64 *)val);
bbd9b64e
CO		 3949 vcpu->mmio_read_completed = 0;
3950 return X86EMUL_CONTINUE;
3951 }
3952
ab9ae313 3953 gpa = kvm_mmu_gva_to_gpa_read(vcpu, addr, exception);
1871c602 3954
8fe681e9 3955 if (gpa == UNMAPPED_GVA)
1871c602 3956 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3957
3958 /* For APIC access vmexit */
3959 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3960 goto mmio;
3961
0f65dd70 3962 if (kvm_read_guest_virt(ctxt, addr, val, bytes, exception)
bcc55cba 3963 == X86EMUL_CONTINUE)
bbd9b64e 3964 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3965
3966mmio:
3967 /*
3968 * Is this MMIO handled locally?
3969 */
70252a10
AK		 3970 handled = vcpu_mmio_read(vcpu, gpa, bytes, val);
3971
3972 if (handled == bytes)
bbd9b64e 3973 return X86EMUL_CONTINUE;
70252a10
AK		 3974
3975 gpa += handled;
3976 bytes -= handled;
3977 val += handled;
aec51dc4
AK		 3978
3979 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
bbd9b64e
CO		 3980
3981 vcpu->mmio_needed = 1;
411c35b7
GN		 3982 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3983 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
cef4dea0
AK		 3984 vcpu->mmio_size = bytes;
3985 vcpu->run->mmio.len = min(vcpu->mmio_size, 8);
411c35b7 3986 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 0;
cef4dea0 3987 vcpu->mmio_index = 0;
bbd9b64e 3988
c3cd7ffa 3989 return X86EMUL_IO_NEEDED;
bbd9b64e
CO		 3990}
3991
3200f405 3992int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 3993 const void *val, int bytes)
bbd9b64e
CO		 3994{
3995 int ret;
3996
3997 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3998 if (ret < 0)
bbd9b64e 3999 return 0;
ad218f85 4000 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 4001 return 1;
4002}
4003
4004static int emulator_write_emulated_onepage(unsigned long addr,
4005 const void *val,
4006 unsigned int bytes,
bcc55cba 4007 struct x86_exception *exception,
bbd9b64e
CO		 4008 struct kvm_vcpu *vcpu)
4009{
10589a46 4010 gpa_t gpa;
70252a10 4011 int handled;
10589a46 4012
ab9ae313 4013 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, exception);
bbd9b64e 4014
8fe681e9 4015 if (gpa == UNMAPPED_GVA)
bbd9b64e 4016 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4017
4018 /* For APIC access vmexit */
4019 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4020 goto mmio;
4021
4022 if (emulator_write_phys(vcpu, gpa, val, bytes))
4023 return X86EMUL_CONTINUE;
4024
4025mmio:
aec51dc4 4026 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 4027 /*
4028 * Is this MMIO handled locally?
4029 */
70252a10
AK		 4030 handled = vcpu_mmio_write(vcpu, gpa, bytes, val);
4031 if (handled == bytes)
bbd9b64e 4032 return X86EMUL_CONTINUE;
bbd9b64e 4033
70252a10
AK		 4034 gpa += handled;
4035 bytes -= handled;
4036 val += handled;
4037
bbd9b64e 4038 vcpu->mmio_needed = 1;
cef4dea0 4039 memcpy(vcpu->mmio_data, val, bytes);
411c35b7
GN		 4040 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4041 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
cef4dea0
AK		 4042 vcpu->mmio_size = bytes;
4043 vcpu->run->mmio.len = min(vcpu->mmio_size, 8);
411c35b7 4044 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 1;
cef4dea0
AK		 4045 memcpy(vcpu->run->mmio.data, vcpu->mmio_data, 8);
4046 vcpu->mmio_index = 0;
bbd9b64e
CO		 4047
4048 return X86EMUL_CONTINUE;
4049}
4050
0f65dd70
AK		 4051int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4052 unsigned long addr,
8f6abd06
GN		 4053 const void *val,
4054 unsigned int bytes,
0f65dd70 4055 struct x86_exception *exception)
bbd9b64e 4056{
0f65dd70
AK		 4057 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4058
bbd9b64e
CO		 4059 /* Crossing a page boundary? */
4060 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
4061 int rc, now;
4062
4063 now = -addr & ~PAGE_MASK;
bcc55cba 4064 rc = emulator_write_emulated_onepage(addr, val, now, exception,
8fe681e9 4065 vcpu);
bbd9b64e
CO		 4066 if (rc != X86EMUL_CONTINUE)
4067 return rc;
4068 addr += now;
4069 val += now;
4070 bytes -= now;
4071 }
bcc55cba 4072 return emulator_write_emulated_onepage(addr, val, bytes, exception,
8fe681e9 4073 vcpu);
bbd9b64e 4074}
bbd9b64e 4075
daea3e73
AK		 4076#define CMPXCHG_TYPE(t, ptr, old, new) \
4077 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4078
4079#ifdef CONFIG_X86_64
4080# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4081#else
4082# define CMPXCHG64(ptr, old, new) \
9749a6c0 4083 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4084#endif
4085
0f65dd70
AK		 4086static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4087 unsigned long addr,
bbd9b64e
CO		 4088 const void *old,
4089 const void *new,
4090 unsigned int bytes,
0f65dd70 4091 struct x86_exception *exception)
bbd9b64e 4092{
0f65dd70 4093 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4094 gpa_t gpa;
4095 struct page *page;
4096 char *kaddr;
4097 bool exchanged;
2bacc55c 4098
daea3e73
AK		 4099 /* guests cmpxchg8b have to be emulated atomically */
4100 if (bytes > 8 || (bytes & (bytes - 1)))
4101 goto emul_write;
10589a46 4102
daea3e73 4103 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4104
daea3e73
AK		 4105 if (gpa == UNMAPPED_GVA ||
4106 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4107 goto emul_write;
2bacc55c 4108
daea3e73
AK		 4109 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4110 goto emul_write;
72dc67a6 4111
daea3e73 4112 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
c19b8bd6
WY		 4113 if (is_error_page(page)) {
4114 kvm_release_page_clean(page);
4115 goto emul_write;
4116 }
72dc67a6 4117
daea3e73
AK		 4118 kaddr = kmap_atomic(page, KM_USER0);
4119 kaddr += offset_in_page(gpa);
4120 switch (bytes) {
4121 case 1:
4122 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4123 break;
4124 case 2:
4125 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4126 break;
4127 case 4:
4128 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4129 break;
4130 case 8:
4131 exchanged = CMPXCHG64(kaddr, old, new);
4132 break;
4133 default:
4134 BUG();
2bacc55c 4135 }
daea3e73
AK		 4136 kunmap_atomic(kaddr, KM_USER0);
4137 kvm_release_page_dirty(page);
4138
4139 if (!exchanged)
4140 return X86EMUL_CMPXCHG_FAILED;
4141
8f6abd06
GN		 4142 kvm_mmu_pte_write(vcpu, gpa, new, bytes, 1);
4143
4144 return X86EMUL_CONTINUE;
4a5f48f6 4145
3200f405 4146emul_write:
daea3e73 4147 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4148
0f65dd70 4149 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4150}
4151
cf8f70bf
GN		 4152static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4153{
4154 /* TODO: String I/O for in kernel device */
4155 int r;
4156
4157 if (vcpu->arch.pio.in)
4158 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4159 vcpu->arch.pio.size, pd);
4160 else
4161 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4162 vcpu->arch.pio.port, vcpu->arch.pio.size,
4163 pd);
4164 return r;
4165}
4166
4167
ca1d4a9e
AK		 4168static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4169 int size, unsigned short port, void *val,
4170 unsigned int count)
cf8f70bf 4171{
ca1d4a9e
AK		 4172 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4173
7972995b 4174 if (vcpu->arch.pio.count)
cf8f70bf
GN		 4175 goto data_avail;
4176
61cfab2e 4177 trace_kvm_pio(0, port, size, count);
cf8f70bf
GN		 4178
4179 vcpu->arch.pio.port = port;
4180 vcpu->arch.pio.in = 1;
7972995b 4181 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4182 vcpu->arch.pio.size = size;
4183
4184 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4185 data_avail:
4186 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 4187 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4188 return 1;
4189 }
4190
4191 vcpu->run->exit_reason = KVM_EXIT_IO;
4192 vcpu->run->io.direction = KVM_EXIT_IO_IN;
4193 vcpu->run->io.size = size;
4194 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4195 vcpu->run->io.count = count;
4196 vcpu->run->io.port = port;
4197
4198 return 0;
4199}
4200
ca1d4a9e
AK		 4201static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4202 int size, unsigned short port,
4203 const void *val, unsigned int count)
cf8f70bf 4204{
ca1d4a9e
AK		 4205 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4206
61cfab2e 4207 trace_kvm_pio(1, port, size, count);
cf8f70bf
GN		 4208
4209 vcpu->arch.pio.port = port;
4210 vcpu->arch.pio.in = 0;
7972995b 4211 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4212 vcpu->arch.pio.size = size;
4213
4214 memcpy(vcpu->arch.pio_data, val, size * count);
4215
4216 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4217 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4218 return 1;
4219 }
4220
4221 vcpu->run->exit_reason = KVM_EXIT_IO;
4222 vcpu->run->io.direction = KVM_EXIT_IO_OUT;
4223 vcpu->run->io.size = size;
4224 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4225 vcpu->run->io.count = count;
4226 vcpu->run->io.port = port;
4227
4228 return 0;
4229}
4230
bbd9b64e
CO		 4231static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4232{
4233 return kvm_x86_ops->get_segment_base(vcpu, seg);
4234}
4235
3cb16fe7 4236static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4237{
3cb16fe7 4238 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4239}
4240
f5f48ee1
SY		 4241int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4242{
4243 if (!need_emulate_wbinvd(vcpu))
4244 return X86EMUL_CONTINUE;
4245
4246 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4247 int cpu = get_cpu();
4248
4249 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4250 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4251 wbinvd_ipi, NULL, 1);
2eec7343 4252 put_cpu();
f5f48ee1 4253 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4254 } else
4255 wbinvd();
f5f48ee1
SY		 4256 return X86EMUL_CONTINUE;
4257}
4258EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4259
bcaf5cc5
AK		 4260static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4261{
4262 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4263}
4264
717746e3 4265int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
bbd9b64e 4266{
717746e3 4267 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4268}
4269
717746e3 4270int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
bbd9b64e 4271{
338dbc97 4272
717746e3 4273 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4274}
4275
52a46617 4276static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4277{
52a46617 4278 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4279}
4280
717746e3 4281static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4282{
717746e3 4283 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4284 unsigned long value;
4285
4286 switch (cr) {
4287 case 0:
4288 value = kvm_read_cr0(vcpu);
4289 break;
4290 case 2:
4291 value = vcpu->arch.cr2;
4292 break;
4293 case 3:
9f8fe504 4294 value = kvm_read_cr3(vcpu);
52a46617
GN		 4295 break;
4296 case 4:
4297 value = kvm_read_cr4(vcpu);
4298 break;
4299 case 8:
4300 value = kvm_get_cr8(vcpu);
4301 break;
4302 default:
4303 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
4304 return 0;
4305 }
4306
4307 return value;
4308}
4309
717746e3 4310static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4311{
717746e3 4312 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4313 int res = 0;
4314
52a46617
GN		 4315 switch (cr) {
4316 case 0:
49a9b07e 4317 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4318 break;
4319 case 2:
4320 vcpu->arch.cr2 = val;
4321 break;
4322 case 3:
2390218b 4323 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4324 break;
4325 case 4:
a83b29c6 4326 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4327 break;
4328 case 8:
eea1cff9 4329 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4330 break;
4331 default:
4332 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
0f12244f 4333 res = -1;
52a46617 4334 }
0f12244f
GN		 4335
4336 return res;
52a46617
GN		 4337}
4338
717746e3 4339static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4340{
717746e3 4341 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4342}
4343
4bff1e86 4344static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4345{
4bff1e86 4346 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4347}
4348
4bff1e86 4349static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4350{
4bff1e86 4351 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4352}
4353
1ac9d0cf
AK		 4354static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4355{
4356 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4357}
4358
4359static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4360{
4361 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4362}
4363
4bff1e86
AK		 4364static unsigned long emulator_get_cached_segment_base(
4365 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4366{
4bff1e86 4367 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4368}
4369
1aa36616
AK		 4370static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4371 struct desc_struct *desc, u32 *base3,
4372 int seg)
2dafc6c2
GN		 4373{
4374 struct kvm_segment var;
4375
4bff1e86 4376 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4377 *selector = var.selector;
2dafc6c2
GN		 4378
4379 if (var.unusable)
4380 return false;
4381
4382 if (var.g)
4383 var.limit >>= 12;
4384 set_desc_limit(desc, var.limit);
4385 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4386#ifdef CONFIG_X86_64
4387 if (base3)
4388 *base3 = var.base >> 32;
4389#endif
2dafc6c2
GN		 4390 desc->type = var.type;
4391 desc->s = var.s;
4392 desc->dpl = var.dpl;
4393 desc->p = var.present;
4394 desc->avl = var.avl;
4395 desc->l = var.l;
4396 desc->d = var.db;
4397 desc->g = var.g;
4398
4399 return true;
4400}
4401
1aa36616
AK		 4402static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4403 struct desc_struct *desc, u32 base3,
4404 int seg)
2dafc6c2 4405{
4bff1e86 4406 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4407 struct kvm_segment var;
4408
1aa36616 4409 var.selector = selector;
2dafc6c2 4410 var.base = get_desc_base(desc);
5601d05b
GN		 4411#ifdef CONFIG_X86_64
4412 var.base |= ((u64)base3) << 32;
4413#endif
2dafc6c2
GN		 4414 var.limit = get_desc_limit(desc);
4415 if (desc->g)
4416 var.limit = (var.limit << 12) | 0xfff;
4417 var.type = desc->type;
4418 var.present = desc->p;
4419 var.dpl = desc->dpl;
4420 var.db = desc->d;
4421 var.s = desc->s;
4422 var.l = desc->l;
4423 var.g = desc->g;
4424 var.avl = desc->avl;
4425 var.present = desc->p;
4426 var.unusable = !var.present;
4427 var.padding = 0;
4428
4429 kvm_set_segment(vcpu, &var, seg);
4430 return;
4431}
4432
717746e3
AK		 4433static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4434 u32 msr_index, u64 *pdata)
4435{
4436 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4437}
4438
4439static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4440 u32 msr_index, u64 data)
4441{
4442 return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
4443}
4444
6c3287f7
AK		 4445static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4446{
4447 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4448}
4449
5037f6f3
AK		 4450static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4451{
4452 preempt_disable();
5197b808 4453 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4454 /*
4455 * CR0.TS may reference the host fpu state, not the guest fpu state,
4456 * so it may be clear at this point.
4457 */
4458 clts();
4459}
4460
4461static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4462{
4463 preempt_enable();
4464}
4465
2953538e 4466static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4467 struct x86_instruction_info *info,
c4f035c6
AK		 4468 enum x86_intercept_stage stage)
4469{
2953538e 4470 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4471}
4472
14af3f3c 4473static struct x86_emulate_ops emulate_ops = {
1871c602 4474 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4475 .write_std = kvm_write_guest_virt_system,
1871c602 4476 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4477 .read_emulated = emulator_read_emulated,
4478 .write_emulated = emulator_write_emulated,
4479 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4480 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4481 .pio_in_emulated = emulator_pio_in_emulated,
4482 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4483 .get_segment = emulator_get_segment,
4484 .set_segment = emulator_set_segment,
5951c442 4485 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4486 .get_gdt = emulator_get_gdt,
160ce1f1 4487 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4488 .set_gdt = emulator_set_gdt,
4489 .set_idt = emulator_set_idt,
52a46617
GN		 4490 .get_cr = emulator_get_cr,
4491 .set_cr = emulator_set_cr,
9c537244 4492 .cpl = emulator_get_cpl,
35aa5375
GN		 4493 .get_dr = emulator_get_dr,
4494 .set_dr = emulator_set_dr,
717746e3
AK		 4495 .set_msr = emulator_set_msr,
4496 .get_msr = emulator_get_msr,
6c3287f7 4497 .halt = emulator_halt,
bcaf5cc5 4498 .wbinvd = emulator_wbinvd,
d6aa1000 4499 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4500 .get_fpu = emulator_get_fpu,
4501 .put_fpu = emulator_put_fpu,
c4f035c6 4502 .intercept = emulator_intercept,
bbd9b64e
CO		 4503};
4504
5fdbf976
MT		 4505static void cache_all_regs(struct kvm_vcpu *vcpu)
4506{
4507 kvm_register_read(vcpu, VCPU_REGS_RAX);
4508 kvm_register_read(vcpu, VCPU_REGS_RSP);
4509 kvm_register_read(vcpu, VCPU_REGS_RIP);
4510 vcpu->arch.regs_dirty = ~0;
4511}
4512
95cb2295
GN		 4513static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4514{
4515 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4516 /*
4517 * an sti; sti; sequence only disable interrupts for the first
4518 * instruction. So, if the last instruction, be it emulated or
4519 * not, left the system with the INT_STI flag enabled, it
4520 * means that the last instruction is an sti. We should not
4521 * leave the flag on in this case. The same goes for mov ss
4522 */
4523 if (!(int_shadow & mask))
4524 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4525}
4526
54b8486f
GN		 4527static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4528{
4529 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4530 if (ctxt->exception.vector == PF_VECTOR)
6389ee94 4531 kvm_propagate_fault(vcpu, &ctxt->exception);
da9cb575
AK		 4532 else if (ctxt->exception.error_code_valid)
4533 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4534 ctxt->exception.error_code);
54b8486f 4535 else
da9cb575 4536 kvm_queue_exception(vcpu, ctxt->exception.vector);
54b8486f
GN		 4537}
4538
9dac77fa 4539static void init_decode_cache(struct x86_emulate_ctxt *ctxt,
b5c9ff73
TY		 4540 const unsigned long *regs)
4541{
9dac77fa
AK		 4542 memset(&ctxt->twobyte, 0,
4543 (void *)&ctxt->regs - (void *)&ctxt->twobyte);
4544 memcpy(ctxt->regs, regs, sizeof(ctxt->regs));
b5c9ff73 4545
9dac77fa
AK		 4546 ctxt->fetch.start = 0;
4547 ctxt->fetch.end = 0;
4548 ctxt->io_read.pos = 0;
4549 ctxt->io_read.end = 0;
4550 ctxt->mem_read.pos = 0;
4551 ctxt->mem_read.end = 0;
b5c9ff73
TY		 4552}
4553
8ec4722d
MG		 4554static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4555{
adf52235 4556 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4557 int cs_db, cs_l;
4558
2aab2c5b
GN		 4559 /*
4560 * TODO: fix emulate.c to use guest_read/write_register
4561 * instead of direct ->regs accesses, can save hundred cycles
4562 * on Intel for instructions that don't read/change RSP, for
4563 * for example.
4564 */
8ec4722d
MG		 4565 cache_all_regs(vcpu);
4566
4567 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4568
adf52235
TY		 4569 ctxt->eflags = kvm_get_rflags(vcpu);
4570 ctxt->eip = kvm_rip_read(vcpu);
4571 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4572 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4573 cs_l ? X86EMUL_MODE_PROT64 :
4574 cs_db ? X86EMUL_MODE_PROT32 :
4575 X86EMUL_MODE_PROT16;
4576 ctxt->guest_mode = is_guest_mode(vcpu);
4577
9dac77fa 4578 init_decode_cache(ctxt, vcpu->arch.regs);
7ae441ea 4579 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4580}
4581
71f9833b 4582int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 4583{
9d74191a 4584 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 4585 int ret;
4586
4587 init_emulate_ctxt(vcpu);
4588
9dac77fa
AK		 4589 ctxt->op_bytes = 2;
4590 ctxt->ad_bytes = 2;
4591 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 4592 ret = emulate_int_real(ctxt, irq);
63995653
MG		 4593
4594 if (ret != X86EMUL_CONTINUE)
4595 return EMULATE_FAIL;
4596
9dac77fa
AK		 4597 ctxt->eip = ctxt->_eip;
4598 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
9d74191a
TY		 4599 kvm_rip_write(vcpu, ctxt->eip);
4600 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 4601
4602 if (irq == NMI_VECTOR)
4603 vcpu->arch.nmi_pending = false;
4604 else
4605 vcpu->arch.interrupt.pending = false;
4606
4607 return EMULATE_DONE;
4608}
4609EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4610
6d77dbfc
GN		 4611static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4612{
fc3a9157
JR		 4613 int r = EMULATE_DONE;
4614
6d77dbfc
GN		 4615 ++vcpu->stat.insn_emulation_fail;
4616 trace_kvm_emulate_insn_failed(vcpu);
fc3a9157
JR		 4617 if (!is_guest_mode(vcpu)) {
4618 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4619 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4620 vcpu->run->internal.ndata = 0;
4621 r = EMULATE_FAIL;
4622 }
6d77dbfc 4623 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4624
4625 return r;
6d77dbfc
GN		 4626}
4627
a6f177ef
GN		 4628static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
4629{
4630 gpa_t gpa;
4631
68be0803
GN		 4632 if (tdp_enabled)
4633 return false;
4634
a6f177ef
GN		 4635 /*
4636 * if emulation was due to access to shadowed page table
4637 * and it failed try to unshadow page and re-entetr the
4638 * guest to let CPU execute the instruction.
4639 */
4640 if (kvm_mmu_unprotect_page_virt(vcpu, gva))
4641 return true;
4642
4643 gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
4644
4645 if (gpa == UNMAPPED_GVA)
4646 return true; /* let cpu generate fault */
4647
4648 if (!kvm_is_error_hva(gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT)))
4649 return true;
4650
4651 return false;
4652}
4653
51d8b661
AP		 4654int x86_emulate_instruction(struct kvm_vcpu *vcpu,
4655 unsigned long cr2,
dc25e89e
AP		 4656 int emulation_type,
4657 void *insn,
4658 int insn_len)
bbd9b64e 4659{
95cb2295 4660 int r;
9d74191a 4661 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 4662 bool writeback = true;
bbd9b64e 4663
26eef70c 4664 kvm_clear_exception_queue(vcpu);
8d7d8102 4665
571008da 4666 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 4667 init_emulate_ctxt(vcpu);
9d74191a
TY		 4668 ctxt->interruptibility = 0;
4669 ctxt->have_exception = false;
4670 ctxt->perm_ok = false;
bbd9b64e 4671
9d74191a 4672 ctxt->only_vendor_specific_insn
4005996e
AK		 4673 = emulation_type & EMULTYPE_TRAP_UD;
4674
9d74191a 4675 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 4676
e46479f8 4677 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 4678 ++vcpu->stat.insn_emulation;
bbd9b64e 4679 if (r) {
4005996e
AK		 4680 if (emulation_type & EMULTYPE_TRAP_UD)
4681 return EMULATE_FAIL;
a6f177ef 4682 if (reexecute_instruction(vcpu, cr2))
bbd9b64e 4683 return EMULATE_DONE;
6d77dbfc
GN		 4684 if (emulation_type & EMULTYPE_SKIP)
4685 return EMULATE_FAIL;
4686 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4687 }
4688 }
4689
ba8afb6b 4690 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 4691 kvm_rip_write(vcpu, ctxt->_eip);
ba8afb6b
GN		 4692 return EMULATE_DONE;
4693 }
4694
7ae441ea 4695 /* this is needed for vmware backdoor interface to work since it
4d2179e1 4696 changes registers values during IO operation */
7ae441ea
GN		 4697 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
4698 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
9dac77fa 4699 memcpy(ctxt->regs, vcpu->arch.regs, sizeof ctxt->regs);
7ae441ea 4700 }
4d2179e1 4701
5cd21917 4702restart:
9d74191a 4703 r = x86_emulate_insn(ctxt);
bbd9b64e 4704
775fde86
JR		 4705 if (r == EMULATION_INTERCEPTED)
4706 return EMULATE_DONE;
4707
d2ddd1c4 4708 if (r == EMULATION_FAILED) {
a6f177ef 4709 if (reexecute_instruction(vcpu, cr2))
c3cd7ffa
GN		 4710 return EMULATE_DONE;
4711
6d77dbfc 4712 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4713 }
4714
9d74191a 4715 if (ctxt->have_exception) {
54b8486f 4716 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 4717 r = EMULATE_DONE;
4718 } else if (vcpu->arch.pio.count) {
3457e419
GN		 4719 if (!vcpu->arch.pio.in)
4720 vcpu->arch.pio.count = 0;
7ae441ea
GN		 4721 else
4722 writeback = false;
e85d28f8 4723 r = EMULATE_DO_MMIO;
7ae441ea
GN		 4724 } else if (vcpu->mmio_needed) {
4725 if (!vcpu->mmio_is_write)
4726 writeback = false;
e85d28f8 4727 r = EMULATE_DO_MMIO;
7ae441ea 4728 } else if (r == EMULATION_RESTART)
5cd21917 4729 goto restart;
d2ddd1c4
GN		 4730 else
4731 r = EMULATE_DONE;
f850e2e6 4732
7ae441ea 4733 if (writeback) {
9d74191a
TY		 4734 toggle_interruptibility(vcpu, ctxt->interruptibility);
4735 kvm_set_rflags(vcpu, ctxt->eflags);
7ae441ea 4736 kvm_make_request(KVM_REQ_EVENT, vcpu);
9dac77fa 4737 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
7ae441ea 4738 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 4739 kvm_rip_write(vcpu, ctxt->eip);
7ae441ea
GN		 4740 } else
4741 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 4742
4743 return r;
de7d789a 4744}
51d8b661 4745EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 4746
cf8f70bf 4747int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 4748{
cf8f70bf 4749 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 4750 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
4751 size, port, &val, 1);
cf8f70bf 4752 /* do not return to emulator after return from userspace */
7972995b 4753 vcpu->arch.pio.count = 0;
de7d789a
CO		 4754 return ret;
4755}
cf8f70bf 4756EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 4757
8cfdc000
ZA		 4758static void tsc_bad(void *info)
4759{
0a3aee0d 4760 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 4761}
4762
4763static void tsc_khz_changed(void *data)
c8076604 4764{
8cfdc000
ZA		 4765 struct cpufreq_freqs *freq = data;
4766 unsigned long khz = 0;
4767
4768 if (data)
4769 khz = freq->new;
4770 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4771 khz = cpufreq_quick_get(raw_smp_processor_id());
4772 if (!khz)
4773 khz = tsc_khz;
0a3aee0d 4774 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 4775}
4776
c8076604
GH		 4777static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4778 void *data)
4779{
4780 struct cpufreq_freqs *freq = data;
4781 struct kvm *kvm;
4782 struct kvm_vcpu *vcpu;
4783 int i, send_ipi = 0;
4784
8cfdc000
ZA		 4785 /*
4786 * We allow guests to temporarily run on slowing clocks,
4787 * provided we notify them after, or to run on accelerating
4788 * clocks, provided we notify them before. Thus time never
4789 * goes backwards.
4790 *
4791 * However, we have a problem. We can't atomically update
4792 * the frequency of a given CPU from this function; it is
4793 * merely a notifier, which can be called from any CPU.
4794 * Changing the TSC frequency at arbitrary points in time
4795 * requires a recomputation of local variables related to
4796 * the TSC for each VCPU. We must flag these local variables
4797 * to be updated and be sure the update takes place with the
4798 * new frequency before any guests proceed.
4799 *
4800 * Unfortunately, the combination of hotplug CPU and frequency
4801 * change creates an intractable locking scenario; the order
4802 * of when these callouts happen is undefined with respect to
4803 * CPU hotplug, and they can race with each other. As such,
4804 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
4805 * undefined; you can actually have a CPU frequency change take
4806 * place in between the computation of X and the setting of the
4807 * variable. To protect against this problem, all updates of
4808 * the per_cpu tsc_khz variable are done in an interrupt
4809 * protected IPI, and all callers wishing to update the value
4810 * must wait for a synchronous IPI to complete (which is trivial
4811 * if the caller is on the CPU already). This establishes the
4812 * necessary total order on variable updates.
4813 *
4814 * Note that because a guest time update may take place
4815 * anytime after the setting of the VCPU's request bit, the
4816 * correct TSC value must be set before the request. However,
4817 * to ensure the update actually makes it to any guest which
4818 * starts running in hardware virtualization between the set
4819 * and the acquisition of the spinlock, we must also ping the
4820 * CPU after setting the request bit.
4821 *
4822 */
4823
c8076604
GH		 4824 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
4825 return 0;
4826 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
4827 return 0;
8cfdc000
ZA		 4828
4829 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 4830
e935b837 4831 raw_spin_lock(&kvm_lock);
c8076604 4832 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 4833 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 4834 if (vcpu->cpu != freq->cpu)
4835 continue;
c285545f 4836 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 4837 if (vcpu->cpu != smp_processor_id())
8cfdc000 4838 send_ipi = 1;
c8076604
GH		 4839 }
4840 }
e935b837 4841 raw_spin_unlock(&kvm_lock);
c8076604
GH		 4842
4843 if (freq->old < freq->new && send_ipi) {
4844 /*
4845 * We upscale the frequency. Must make the guest
4846 * doesn't see old kvmclock values while running with
4847 * the new frequency, otherwise we risk the guest sees
4848 * time go backwards.
4849 *
4850 * In case we update the frequency for another cpu
4851 * (which might be in guest context) send an interrupt
4852 * to kick the cpu out of guest context. Next time
4853 * guest context is entered kvmclock will be updated,
4854 * so the guest will not see stale values.
4855 */
8cfdc000 4856 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 4857 }
4858 return 0;
4859}
4860
4861static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 4862 .notifier_call = kvmclock_cpufreq_notifier
4863};
4864
4865static int kvmclock_cpu_notifier(struct notifier_block *nfb,
4866 unsigned long action, void *hcpu)
4867{
4868 unsigned int cpu = (unsigned long)hcpu;
4869
4870 switch (action) {
4871 case CPU_ONLINE:
4872 case CPU_DOWN_FAILED:
4873 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4874 break;
4875 case CPU_DOWN_PREPARE:
4876 smp_call_function_single(cpu, tsc_bad, NULL, 1);
4877 break;
4878 }
4879 return NOTIFY_OK;
4880}
4881
4882static struct notifier_block kvmclock_cpu_notifier_block = {
4883 .notifier_call = kvmclock_cpu_notifier,
4884 .priority = -INT_MAX
c8076604
GH		 4885};
4886
b820cc0c
ZA		 4887static void kvm_timer_init(void)
4888{
4889 int cpu;
4890
c285545f 4891 max_tsc_khz = tsc_khz;
8cfdc000 4892 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 4893 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 4894#ifdef CONFIG_CPU_FREQ
4895 struct cpufreq_policy policy;
4896 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 4897 cpu = get_cpu();
4898 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 4899 if (policy.cpuinfo.max_freq)
4900 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 4901 put_cpu();
c285545f 4902#endif
b820cc0c
ZA		 4903 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4904 CPUFREQ_TRANSITION_NOTIFIER);
4905 }
c285545f 4906 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 4907 for_each_online_cpu(cpu)
4908 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 4909}
4910
ff9d07a0
ZY		 4911static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
4912
4913static int kvm_is_in_guest(void)
4914{
4915 return percpu_read(current_vcpu) != NULL;
4916}
4917
4918static int kvm_is_user_mode(void)
4919{
4920 int user_mode = 3;
dcf46b94 4921
ff9d07a0
ZY		 4922 if (percpu_read(current_vcpu))
4923 user_mode = kvm_x86_ops->get_cpl(percpu_read(current_vcpu));
dcf46b94 4924
ff9d07a0
ZY		 4925 return user_mode != 0;
4926}
4927
4928static unsigned long kvm_get_guest_ip(void)
4929{
4930 unsigned long ip = 0;
dcf46b94 4931
ff9d07a0
ZY		 4932 if (percpu_read(current_vcpu))
4933 ip = kvm_rip_read(percpu_read(current_vcpu));
dcf46b94 4934
ff9d07a0
ZY		 4935 return ip;
4936}
4937
4938static struct perf_guest_info_callbacks kvm_guest_cbs = {
4939 .is_in_guest = kvm_is_in_guest,
4940 .is_user_mode = kvm_is_user_mode,
4941 .get_guest_ip = kvm_get_guest_ip,
4942};
4943
4944void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4945{
4946 percpu_write(current_vcpu, vcpu);
4947}
4948EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4949
4950void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4951{
4952 percpu_write(current_vcpu, NULL);
4953}
4954EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4955
f8c16bba 4956int kvm_arch_init(void *opaque)
043405e1 4957{
b820cc0c 4958 int r;
f8c16bba
ZX		 4959 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4960
f8c16bba
ZX		 4961 if (kvm_x86_ops) {
4962 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 4963 r = -EEXIST;
4964 goto out;
f8c16bba
ZX		 4965 }
4966
4967 if (!ops->cpu_has_kvm_support()) {
4968 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 4969 r = -EOPNOTSUPP;
4970 goto out;
f8c16bba
ZX		 4971 }
4972 if (ops->disabled_by_bios()) {
4973 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 4974 r = -EOPNOTSUPP;
4975 goto out;
f8c16bba
ZX		 4976 }
4977
97db56ce
AK		 4978 r = kvm_mmu_module_init();
4979 if (r)
4980 goto out;
4981
4982 kvm_init_msr_list();
4983
f8c16bba 4984 kvm_x86_ops = ops;
56c6d28a 4985 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e 4986 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 4987 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 4988
b820cc0c 4989 kvm_timer_init();
c8076604 4990
ff9d07a0
ZY		 4991 perf_register_guest_info_callbacks(&kvm_guest_cbs);
4992
2acf923e
DC		 4993 if (cpu_has_xsave)
4994 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
4995
f8c16bba 4996 return 0;
56c6d28a
ZX		 4997
4998out:
56c6d28a 4999 return r;
043405e1 5000}
8776e519 5001
f8c16bba
ZX		 5002void kvm_arch_exit(void)
5003{
ff9d07a0
ZY		 5004 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5005
888d256e
JK		 5006 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5007 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5008 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5009 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
f8c16bba 5010 kvm_x86_ops = NULL;
56c6d28a
ZX		 5011 kvm_mmu_module_exit();
5012}
f8c16bba 5013
8776e519
HB		 5014int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5015{
5016 ++vcpu->stat.halt_exits;
5017 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 5018 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5019 return 1;
5020 } else {
5021 vcpu->run->exit_reason = KVM_EXIT_HLT;
5022 return 0;
5023 }
5024}
5025EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5026
2f333bcb
MT		 5027static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
5028 unsigned long a1)
5029{
5030 if (is_long_mode(vcpu))
5031 return a0;
5032 else
5033 return a0 | ((gpa_t)a1 << 32);
5034}
5035
55cd8e5a
GN		 5036int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5037{
5038 u64 param, ingpa, outgpa, ret;
5039 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5040 bool fast, longmode;
5041 int cs_db, cs_l;
5042
5043 /*
5044 * hypercall generates UD from non zero cpl and real mode
5045 * per HYPER-V spec
5046 */
3eeb3288 5047 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 5048 kvm_queue_exception(vcpu, UD_VECTOR);
5049 return 0;
5050 }
5051
5052 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5053 longmode = is_long_mode(vcpu) && cs_l == 1;
5054
5055 if (!longmode) {
ccd46936
GN		 5056 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5057 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5058 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5059 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5060 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5061 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 5062 }
5063#ifdef CONFIG_X86_64
5064 else {
5065 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5066 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5067 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5068 }
5069#endif
5070
5071 code = param & 0xffff;
5072 fast = (param >> 16) & 0x1;
5073 rep_cnt = (param >> 32) & 0xfff;
5074 rep_idx = (param >> 48) & 0xfff;
5075
5076 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5077
c25bc163
GN		 5078 switch (code) {
5079 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5080 kvm_vcpu_on_spin(vcpu);
5081 break;
5082 default:
5083 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5084 break;
5085 }
55cd8e5a
GN		 5086
5087 ret = res | (((u64)rep_done & 0xfff) << 32);
5088 if (longmode) {
5089 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5090 } else {
5091 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5092 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5093 }
5094
5095 return 1;
5096}
5097
8776e519
HB		 5098int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5099{
5100 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 5101 int r = 1;
8776e519 5102
55cd8e5a
GN		 5103 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5104 return kvm_hv_hypercall(vcpu);
5105
5fdbf976
MT		 5106 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5107 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5108 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5109 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5110 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5111
229456fc 5112 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5113
8776e519
HB		 5114 if (!is_long_mode(vcpu)) {
5115 nr &= 0xFFFFFFFF;
5116 a0 &= 0xFFFFFFFF;
5117 a1 &= 0xFFFFFFFF;
5118 a2 &= 0xFFFFFFFF;
5119 a3 &= 0xFFFFFFFF;
5120 }
5121
07708c4a
JK		 5122 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5123 ret = -KVM_EPERM;
5124 goto out;
5125 }
5126
8776e519 5127 switch (nr) {
b93463aa
AK		 5128 case KVM_HC_VAPIC_POLL_IRQ:
5129 ret = 0;
5130 break;
2f333bcb
MT		 5131 case KVM_HC_MMU_OP:
5132 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
5133 break;
8776e519
HB		 5134 default:
5135 ret = -KVM_ENOSYS;
5136 break;
5137 }
07708c4a 5138out:
5fdbf976 5139 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5140 ++vcpu->stat.hypercalls;
2f333bcb 5141 return r;
8776e519
HB		 5142}
5143EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5144
d6aa1000 5145int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5146{
d6aa1000 5147 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5148 char instruction[3];
5fdbf976 5149 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5150
8776e519
HB		 5151 /*
5152 * Blow out the MMU to ensure that no other VCPU has an active mapping
5153 * to ensure that the updated hypercall appears atomically across all
5154 * VCPUs.
5155 */
5156 kvm_mmu_zap_all(vcpu->kvm);
5157
8776e519 5158 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5159
9d74191a 5160 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5161}
5162
07716717
DK		 5163static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
5164{
ad312c7c
ZX		 5165 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
5166 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 5167
5168 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
5169 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 5170 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 5171 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 5172 if (ej->function == e->function) {
5173 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
5174 return j;
5175 }
5176 }
5177 return 0; /* silence gcc, even though control never reaches here */
5178}
5179
5180/* find an entry with matching function, matching index (if needed), and that
5181 * should be read next (if it's stateful) */
5182static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
5183 u32 function, u32 index)
5184{
5185 if (e->function != function)
5186 return 0;
5187 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
5188 return 0;
5189 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 5190 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 5191 return 0;
5192 return 1;
5193}
5194
d8017474
AG		 5195struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
5196 u32 function, u32 index)
8776e519
HB		 5197{
5198 int i;
d8017474 5199 struct kvm_cpuid_entry2 *best = NULL;
8776e519 5200
ad312c7c 5201 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 5202 struct kvm_cpuid_entry2 *e;
5203
ad312c7c 5204 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 5205 if (is_matching_cpuid_entry(e, function, index)) {
5206 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
5207 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 5208 best = e;
5209 break;
5210 }
8776e519 5211 }
d8017474
AG		 5212 return best;
5213}
0e851880 5214EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
d8017474 5215
82725b20
DE		 5216int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
5217{
5218 struct kvm_cpuid_entry2 *best;
5219
f7a71197
AK		 5220 best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0);
5221 if (!best || best->eax < 0x80000008)
5222 goto not_found;
82725b20
DE		 5223 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
5224 if (best)
5225 return best->eax & 0xff;
f7a71197 5226not_found:
82725b20
DE		 5227 return 36;
5228}
5229
bd22f5cf
AP		 5230/*
5231 * If no match is found, check whether we exceed the vCPU's limit
5232 * and return the content of the highest valid _standard_ leaf instead.
5233 * This is to satisfy the CPUID specification.
5234 */
5235static struct kvm_cpuid_entry2* check_cpuid_limit(struct kvm_vcpu *vcpu,
5236 u32 function, u32 index)
5237{
5238 struct kvm_cpuid_entry2 *maxlevel;
5239
5240 maxlevel = kvm_find_cpuid_entry(vcpu, function & 0x80000000, 0);
5241 if (!maxlevel || maxlevel->eax >= function)
5242 return NULL;
5243 if (function & 0x80000000) {
5244 maxlevel = kvm_find_cpuid_entry(vcpu, 0, 0);
5245 if (!maxlevel)
5246 return NULL;
5247 }
5248 return kvm_find_cpuid_entry(vcpu, maxlevel->eax, index);
5249}
5250
d8017474
AG		 5251void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
5252{
5253 u32 function, index;
5254 struct kvm_cpuid_entry2 *best;
5255
5256 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
5257 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5258 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
5259 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
5260 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
5261 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
5262 best = kvm_find_cpuid_entry(vcpu, function, index);
bd22f5cf
AP		 5263
5264 if (!best)
5265 best = check_cpuid_limit(vcpu, function, index);
5266
8776e519 5267 if (best) {
5fdbf976
MT		 5268 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
5269 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
5270 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
5271 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 5272 }
8776e519 5273 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 5274 trace_kvm_cpuid(function,
5275 kvm_register_read(vcpu, VCPU_REGS_RAX),
5276 kvm_register_read(vcpu, VCPU_REGS_RBX),
5277 kvm_register_read(vcpu, VCPU_REGS_RCX),
5278 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 5279}
5280EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 5281
b6c7a5dc
HB		 5282/*
5283 * Check if userspace requested an interrupt window, and that the
5284 * interrupt window is open.
5285 *
5286 * No need to exit to userspace if we already have an interrupt queued.
5287 */
851ba692 5288static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5289{
8061823a 5290 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5291 vcpu->run->request_interrupt_window &&
5df56646 5292 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5293}
5294
851ba692 5295static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5296{
851ba692
AK		 5297 struct kvm_run *kvm_run = vcpu->run;
5298
91586a3b 5299 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5300 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5301 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5302 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5303 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5304 else
b6c7a5dc 5305 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5306 kvm_arch_interrupt_allowed(vcpu) &&
5307 !kvm_cpu_has_interrupt(vcpu) &&
5308 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5309}
5310
b93463aa
AK		 5311static void vapic_enter(struct kvm_vcpu *vcpu)
5312{
5313 struct kvm_lapic *apic = vcpu->arch.apic;
5314 struct page *page;
5315
5316 if (!apic || !apic->vapic_addr)
5317 return;
5318
5319 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 5320
5321 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 5322}
5323
5324static void vapic_exit(struct kvm_vcpu *vcpu)
5325{
5326 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 5327 int idx;
b93463aa
AK		 5328
5329 if (!apic || !apic->vapic_addr)
5330 return;
5331
f656ce01 5332 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 5333 kvm_release_page_dirty(apic->vapic_page);
5334 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 5335 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 5336}
5337
95ba8273
GN		 5338static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5339{
5340 int max_irr, tpr;
5341
5342 if (!kvm_x86_ops->update_cr8_intercept)
5343 return;
5344
88c808fd
AK		 5345 if (!vcpu->arch.apic)
5346 return;
5347
8db3baa2
GN		 5348 if (!vcpu->arch.apic->vapic_addr)
5349 max_irr = kvm_lapic_find_highest_irr(vcpu);
5350 else
5351 max_irr = -1;
95ba8273
GN		 5352
5353 if (max_irr != -1)
5354 max_irr >>= 4;
5355
5356 tpr = kvm_lapic_get_cr8(vcpu);
5357
5358 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5359}
5360
851ba692 5361static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 5362{
5363 /* try to reinject previous events if any */
b59bb7bd 5364 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5365 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5366 vcpu->arch.exception.has_error_code,
5367 vcpu->arch.exception.error_code);
b59bb7bd
GN		 5368 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5369 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5370 vcpu->arch.exception.error_code,
5371 vcpu->arch.exception.reinject);
b59bb7bd
GN		 5372 return;
5373 }
5374
95ba8273
GN		 5375 if (vcpu->arch.nmi_injected) {
5376 kvm_x86_ops->set_nmi(vcpu);
5377 return;
5378 }
5379
5380 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5381 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5382 return;
5383 }
5384
5385 /* try to inject new event if pending */
5386 if (vcpu->arch.nmi_pending) {
5387 if (kvm_x86_ops->nmi_allowed(vcpu)) {
5388 vcpu->arch.nmi_pending = false;
5389 vcpu->arch.nmi_injected = true;
5390 kvm_x86_ops->set_nmi(vcpu);
5391 }
5392 } else if (kvm_cpu_has_interrupt(vcpu)) {
5393 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5394 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5395 false);
5396 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5397 }
5398 }
5399}
5400
2acf923e
DC		 5401static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
5402{
5403 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
5404 !vcpu->guest_xcr0_loaded) {
5405 /* kvm_set_xcr() also depends on this */
5406 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
5407 vcpu->guest_xcr0_loaded = 1;
5408 }
5409}
5410
5411static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
5412{
5413 if (vcpu->guest_xcr0_loaded) {
5414 if (vcpu->arch.xcr0 != host_xcr0)
5415 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
5416 vcpu->guest_xcr0_loaded = 0;
5417 }
5418}
5419
851ba692 5420static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5421{
5422 int r;
1499e54a 5423 bool nmi_pending;
6a8b1d13 5424 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5425 vcpu->run->request_interrupt_window;
b6c7a5dc 5426
3e007509 5427 if (vcpu->requests) {
a8eeb04a 5428 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5429 kvm_mmu_unload(vcpu);
a8eeb04a 5430 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5431 __kvm_migrate_timers(vcpu);
34c238a1
ZA		 5432 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5433 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 5434 if (unlikely(r))
5435 goto out;
5436 }
a8eeb04a 5437 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5438 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5439 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5440 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5441 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5442 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5443 r = 0;
5444 goto out;
5445 }
a8eeb04a 5446 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5447 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5448 r = 0;
5449 goto out;
5450 }
a8eeb04a 5451 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5452 vcpu->fpu_active = 0;
5453 kvm_x86_ops->fpu_deactivate(vcpu);
5454 }
af585b92
GN		 5455 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5456 /* Page is swapped out. Do synthetic halt */
5457 vcpu->arch.apf.halted = true;
5458 r = 1;
5459 goto out;
5460 }
2f52d58c 5461 }
b93463aa 5462
3e007509
AK		 5463 r = kvm_mmu_reload(vcpu);
5464 if (unlikely(r))
5465 goto out;
5466
1499e54a
GN		 5467 /*
5468 * An NMI can be injected between local nmi_pending read and
5469 * vcpu->arch.nmi_pending read inside inject_pending_event().
5470 * But in that case, KVM_REQ_EVENT will be set, which makes
5471 * the race described above benign.
5472 */
5473 nmi_pending = ACCESS_ONCE(vcpu->arch.nmi_pending);
5474
b463a6f7
AK		 5475 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5476 inject_pending_event(vcpu);
5477
5478 /* enable NMI/IRQ window open exits if needed */
1499e54a 5479 if (nmi_pending)
b463a6f7
AK		 5480 kvm_x86_ops->enable_nmi_window(vcpu);
5481 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
5482 kvm_x86_ops->enable_irq_window(vcpu);
5483
5484 if (kvm_lapic_enabled(vcpu)) {
5485 update_cr8_intercept(vcpu);
5486 kvm_lapic_sync_to_vapic(vcpu);
5487 }
5488 }
5489
b6c7a5dc
HB		 5490 preempt_disable();
5491
5492 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 5493 if (vcpu->fpu_active)
5494 kvm_load_guest_fpu(vcpu);
2acf923e 5495 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 5496
6b7e2d09
XG		 5497 vcpu->mode = IN_GUEST_MODE;
5498
5499 /* We should set ->mode before check ->requests,
5500 * see the comment in make_all_cpus_request.
5501 */
5502 smp_mb();
b6c7a5dc 5503
d94e1dc9 5504 local_irq_disable();
32f88400 5505
6b7e2d09 5506 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 5507 || need_resched() || signal_pending(current)) {
6b7e2d09 5508 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5509 smp_wmb();
6c142801
AK		 5510 local_irq_enable();
5511 preempt_enable();
b463a6f7 5512 kvm_x86_ops->cancel_injection(vcpu);
6c142801
AK		 5513 r = 1;
5514 goto out;
5515 }
5516
f656ce01 5517 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 5518
b6c7a5dc
HB		 5519 kvm_guest_enter();
5520
42dbaa5a 5521 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 5522 set_debugreg(0, 7);
5523 set_debugreg(vcpu->arch.eff_db[0], 0);
5524 set_debugreg(vcpu->arch.eff_db[1], 1);
5525 set_debugreg(vcpu->arch.eff_db[2], 2);
5526 set_debugreg(vcpu->arch.eff_db[3], 3);
5527 }
b6c7a5dc 5528
229456fc 5529 trace_kvm_entry(vcpu->vcpu_id);
851ba692 5530 kvm_x86_ops->run(vcpu);
b6c7a5dc 5531
24f1e32c
FW		 5532 /*
5533 * If the guest has used debug registers, at least dr7
5534 * will be disabled while returning to the host.
5535 * If we don't have active breakpoints in the host, we don't
5536 * care about the messed up debug address registers. But if
5537 * we have some of them active, restore the old state.
5538 */
59d8eb53 5539 if (hw_breakpoint_active())
24f1e32c 5540 hw_breakpoint_restore();
42dbaa5a 5541
1d5f066e
ZA		 5542 kvm_get_msr(vcpu, MSR_IA32_TSC, &vcpu->arch.last_guest_tsc);
5543
6b7e2d09 5544 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5545 smp_wmb();
b6c7a5dc
HB		 5546 local_irq_enable();
5547
5548 ++vcpu->stat.exits;
5549
5550 /*
5551 * We must have an instruction between local_irq_enable() and
5552 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5553 * the interrupt shadow. The stat.exits increment will do nicely.
5554 * But we need to prevent reordering, hence this barrier():
5555 */
5556 barrier();
5557
5558 kvm_guest_exit();
5559
5560 preempt_enable();
5561
f656ce01 5562 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 5563
b6c7a5dc
HB		 5564 /*
5565 * Profile KVM exit RIPs:
5566 */
5567 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 5568 unsigned long rip = kvm_rip_read(vcpu);
5569 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 5570 }
5571
298101da 5572
b93463aa
AK		 5573 kvm_lapic_sync_from_vapic(vcpu);
5574
851ba692 5575 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 5576out:
5577 return r;
5578}
b6c7a5dc 5579
09cec754 5580
851ba692 5581static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 5582{
5583 int r;
f656ce01 5584 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 5585
5586 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 5587 pr_debug("vcpu %d received sipi with vector # %x\n",
5588 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 5589 kvm_lapic_reset(vcpu);
5f179287 5590 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 5591 if (r)
5592 return r;
5593 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 5594 }
5595
f656ce01 5596 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 5597 vapic_enter(vcpu);
5598
5599 r = 1;
5600 while (r > 0) {
af585b92
GN		 5601 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
5602 !vcpu->arch.apf.halted)
851ba692 5603 r = vcpu_enter_guest(vcpu);
d7690175 5604 else {
f656ce01 5605 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 5606 kvm_vcpu_block(vcpu);
f656ce01 5607 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
a8eeb04a 5608 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
09cec754
GN		 5609 {
5610 switch(vcpu->arch.mp_state) {
5611 case KVM_MP_STATE_HALTED:
d7690175 5612 vcpu->arch.mp_state =
09cec754
GN		 5613 KVM_MP_STATE_RUNNABLE;
5614 case KVM_MP_STATE_RUNNABLE:
af585b92 5615 vcpu->arch.apf.halted = false;
09cec754
GN		 5616 break;
5617 case KVM_MP_STATE_SIPI_RECEIVED:
5618 default:
5619 r = -EINTR;
5620 break;
5621 }
5622 }
d7690175
MT		 5623 }
5624
09cec754
GN		 5625 if (r <= 0)
5626 break;
5627
5628 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5629 if (kvm_cpu_has_pending_timer(vcpu))
5630 kvm_inject_pending_timer_irqs(vcpu);
5631
851ba692 5632 if (dm_request_for_irq_injection(vcpu)) {
09cec754 5633 r = -EINTR;
851ba692 5634 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5635 ++vcpu->stat.request_irq_exits;
5636 }
af585b92
GN		 5637
5638 kvm_check_async_pf_completion(vcpu);
5639
09cec754
GN		 5640 if (signal_pending(current)) {
5641 r = -EINTR;
851ba692 5642 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5643 ++vcpu->stat.signal_exits;
5644 }
5645 if (need_resched()) {
f656ce01 5646 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 5647 kvm_resched(vcpu);
f656ce01 5648 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 5649 }
b6c7a5dc
HB		 5650 }
5651
f656ce01 5652 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 5653
b93463aa
AK		 5654 vapic_exit(vcpu);
5655
b6c7a5dc
HB		 5656 return r;
5657}
5658
5287f194
AK		 5659static int complete_mmio(struct kvm_vcpu *vcpu)
5660{
5661 struct kvm_run *run = vcpu->run;
5662 int r;
5663
5664 if (!(vcpu->arch.pio.count || vcpu->mmio_needed))
5665 return 1;
5666
5667 if (vcpu->mmio_needed) {
5287f194 5668 vcpu->mmio_needed = 0;
cef4dea0 5669 if (!vcpu->mmio_is_write)
0004c7c2
GN		 5670 memcpy(vcpu->mmio_data + vcpu->mmio_index,
5671 run->mmio.data, 8);
cef4dea0
AK		 5672 vcpu->mmio_index += 8;
5673 if (vcpu->mmio_index < vcpu->mmio_size) {
5674 run->exit_reason = KVM_EXIT_MMIO;
5675 run->mmio.phys_addr = vcpu->mmio_phys_addr + vcpu->mmio_index;
5676 memcpy(run->mmio.data, vcpu->mmio_data + vcpu->mmio_index, 8);
5677 run->mmio.len = min(vcpu->mmio_size - vcpu->mmio_index, 8);
5678 run->mmio.is_write = vcpu->mmio_is_write;
5679 vcpu->mmio_needed = 1;
5680 return 0;
5681 }
5682 if (vcpu->mmio_is_write)
5683 return 1;
5684 vcpu->mmio_read_completed = 1;
5287f194
AK		 5685 }
5686 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5687 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
5688 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5689 if (r != EMULATE_DONE)
5690 return 0;
5691 return 1;
5692}
5693
b6c7a5dc
HB		 5694int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
5695{
5696 int r;
5697 sigset_t sigsaved;
5698
e5c30142
AK		 5699 if (!tsk_used_math(current) && init_fpu(current))
5700 return -ENOMEM;
5701
ac9f6dc0
AK		 5702 if (vcpu->sigset_active)
5703 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
5704
a4535290 5705 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 5706 kvm_vcpu_block(vcpu);
d7690175 5707 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 5708 r = -EAGAIN;
5709 goto out;
b6c7a5dc
HB		 5710 }
5711
b6c7a5dc 5712 /* re-sync apic's tpr */
eea1cff9
AP		 5713 if (!irqchip_in_kernel(vcpu->kvm)) {
5714 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
5715 r = -EINVAL;
5716 goto out;
5717 }
5718 }
b6c7a5dc 5719
5287f194
AK		 5720 r = complete_mmio(vcpu);
5721 if (r <= 0)
5722 goto out;
5723
5fdbf976
MT		 5724 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
5725 kvm_register_write(vcpu, VCPU_REGS_RAX,
5726 kvm_run->hypercall.ret);
b6c7a5dc 5727
851ba692 5728 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 5729
5730out:
f1d86e46 5731 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 5732 if (vcpu->sigset_active)
5733 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
5734
b6c7a5dc
HB		 5735 return r;
5736}
5737
5738int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5739{
7ae441ea
GN		 5740 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
5741 /*
5742 * We are here if userspace calls get_regs() in the middle of
5743 * instruction emulation. Registers state needs to be copied
5744 * back from emulation context to vcpu. Usrapace shouldn't do
5745 * that usually, but some bad designed PV devices (vmware
5746 * backdoor interface) need this to work
5747 */
9dac77fa
AK		 5748 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5749 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
7ae441ea
GN		 5750 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5751 }
5fdbf976
MT		 5752 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5753 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5754 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5755 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5756 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
5757 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
5758 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5759 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 5760#ifdef CONFIG_X86_64
5fdbf976
MT		 5761 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
5762 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
5763 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
5764 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
5765 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
5766 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
5767 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
5768 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 5769#endif
5770
5fdbf976 5771 regs->rip = kvm_rip_read(vcpu);
91586a3b 5772 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 5773
b6c7a5dc
HB		 5774 return 0;
5775}
5776
5777int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5778{
7ae441ea
GN		 5779 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
5780 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5781
5fdbf976
MT		 5782 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
5783 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
5784 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
5785 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
5786 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
5787 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
5788 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
5789 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 5790#ifdef CONFIG_X86_64
5fdbf976
MT		 5791 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
5792 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
5793 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
5794 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
5795 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
5796 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
5797 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
5798 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 5799#endif
5800
5fdbf976 5801 kvm_rip_write(vcpu, regs->rip);
91586a3b 5802 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 5803
b4f14abd
JK		 5804 vcpu->arch.exception.pending = false;
5805
3842d135
AK		 5806 kvm_make_request(KVM_REQ_EVENT, vcpu);
5807
b6c7a5dc
HB		 5808 return 0;
5809}
5810
b6c7a5dc
HB		 5811void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5812{
5813 struct kvm_segment cs;
5814
3e6e0aab 5815 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 5816 *db = cs.db;
5817 *l = cs.l;
5818}
5819EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
5820
5821int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
5822 struct kvm_sregs *sregs)
5823{
89a27f4d 5824 struct desc_ptr dt;
b6c7a5dc 5825
3e6e0aab
GT		 5826 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5827 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5828 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5829 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5830 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5831 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5832
3e6e0aab
GT		 5833 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5834 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 5835
5836 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 5837 sregs->idt.limit = dt.size;
5838 sregs->idt.base = dt.address;
b6c7a5dc 5839 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 5840 sregs->gdt.limit = dt.size;
5841 sregs->gdt.base = dt.address;
b6c7a5dc 5842
4d4ec087 5843 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 5844 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 5845 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 5846 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 5847 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 5848 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 5849 sregs->apic_base = kvm_get_apic_base(vcpu);
5850
923c61bb 5851 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 5852
36752c9b 5853 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 5854 set_bit(vcpu->arch.interrupt.nr,
5855 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 5856
b6c7a5dc
HB		 5857 return 0;
5858}
5859
62d9f0db
MT		 5860int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
5861 struct kvm_mp_state *mp_state)
5862{
62d9f0db 5863 mp_state->mp_state = vcpu->arch.mp_state;
62d9f0db
MT		 5864 return 0;
5865}
5866
5867int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
5868 struct kvm_mp_state *mp_state)
5869{
62d9f0db 5870 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 5871 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 5872 return 0;
5873}
5874
e269fb21
JK		 5875int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason,
5876 bool has_error_code, u32 error_code)
b6c7a5dc 5877{
9d74191a 5878 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 5879 int ret;
e01c2426 5880
8ec4722d 5881 init_emulate_ctxt(vcpu);
c697518a 5882
9d74191a
TY		 5883 ret = emulator_task_switch(ctxt, tss_selector, reason,
5884 has_error_code, error_code);
c697518a 5885
c697518a 5886 if (ret)
19d04437 5887 return EMULATE_FAIL;
37817f29 5888
9dac77fa 5889 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
9d74191a
TY		 5890 kvm_rip_write(vcpu, ctxt->eip);
5891 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 5892 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 5893 return EMULATE_DONE;
37817f29
IE		 5894}
5895EXPORT_SYMBOL_GPL(kvm_task_switch);
5896
b6c7a5dc
HB		 5897int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5898 struct kvm_sregs *sregs)
5899{
5900 int mmu_reset_needed = 0;
63f42e02 5901 int pending_vec, max_bits, idx;
89a27f4d 5902 struct desc_ptr dt;
b6c7a5dc 5903
89a27f4d
GN		 5904 dt.size = sregs->idt.limit;
5905 dt.address = sregs->idt.base;
b6c7a5dc 5906 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 5907 dt.size = sregs->gdt.limit;
5908 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 5909 kvm_x86_ops->set_gdt(vcpu, &dt);
5910
ad312c7c 5911 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 5912 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 5913 vcpu->arch.cr3 = sregs->cr3;
aff48baa 5914 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 5915
2d3ad1f4 5916 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 5917
f6801dff 5918 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 5919 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 5920 kvm_set_apic_base(vcpu, sregs->apic_base);
5921
4d4ec087 5922 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 5923 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 5924 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 5925
fc78f519 5926 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 5927 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c
SY		 5928 if (sregs->cr4 & X86_CR4_OSXSAVE)
5929 update_cpuid(vcpu);
63f42e02
XG		 5930
5931 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 5932 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 5933 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 5934 mmu_reset_needed = 1;
5935 }
63f42e02 5936 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 5937
5938 if (mmu_reset_needed)
5939 kvm_mmu_reset_context(vcpu);
5940
923c61bb
GN		 5941 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5942 pending_vec = find_first_bit(
5943 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5944 if (pending_vec < max_bits) {
66fd3f7f 5945 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 5946 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 5947 }
5948
3e6e0aab
GT		 5949 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5950 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5951 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5952 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5953 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5954 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5955
3e6e0aab
GT		 5956 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5957 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 5958
5f0269f5
ME		 5959 update_cr8_intercept(vcpu);
5960
9c3e4aab 5961 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 5962 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 5963 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 5964 !is_protmode(vcpu))
9c3e4aab
MT		 5965 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5966
3842d135
AK		 5967 kvm_make_request(KVM_REQ_EVENT, vcpu);
5968
b6c7a5dc
HB		 5969 return 0;
5970}
5971
d0bfb940
JK		 5972int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5973 struct kvm_guest_debug *dbg)
b6c7a5dc 5974{
355be0b9 5975 unsigned long rflags;
ae675ef0 5976 int i, r;
b6c7a5dc 5977
4f926bf2
JK		 5978 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5979 r = -EBUSY;
5980 if (vcpu->arch.exception.pending)
2122ff5e 5981 goto out;
4f926bf2
JK		 5982 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5983 kvm_queue_exception(vcpu, DB_VECTOR);
5984 else
5985 kvm_queue_exception(vcpu, BP_VECTOR);
5986 }
5987
91586a3b
JK		 5988 /*
5989 * Read rflags as long as potentially injected trace flags are still
5990 * filtered out.
5991 */
5992 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 5993
5994 vcpu->guest_debug = dbg->control;
5995 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5996 vcpu->guest_debug = 0;
5997
5998 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 5999 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6000 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
6001 vcpu->arch.switch_db_regs =
6002 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
6003 } else {
6004 for (i = 0; i < KVM_NR_DB_REGS; i++)
6005 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6006 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
6007 }
6008
f92653ee
JK		 6009 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6010 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6011 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 6012
91586a3b
JK		 6013 /*
6014 * Trigger an rflags update that will inject or remove the trace
6015 * flags.
6016 */
6017 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 6018
355be0b9 6019 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 6020
4f926bf2 6021 r = 0;
d0bfb940 6022
2122ff5e 6023out:
b6c7a5dc
HB		 6024
6025 return r;
6026}
6027
8b006791
ZX		 6028/*
6029 * Translate a guest virtual address to a guest physical address.
6030 */
6031int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6032 struct kvm_translation *tr)
6033{
6034 unsigned long vaddr = tr->linear_address;
6035 gpa_t gpa;
f656ce01 6036 int idx;
8b006791 6037
f656ce01 6038 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 6039 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 6040 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 6041 tr->physical_address = gpa;
6042 tr->valid = gpa != UNMAPPED_GVA;
6043 tr->writeable = 1;
6044 tr->usermode = 0;
8b006791
ZX		 6045
6046 return 0;
6047}
6048
d0752060
HB		 6049int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6050{
98918833
SY		 6051 struct i387_fxsave_struct *fxsave =
6052 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6053
d0752060
HB		 6054 memcpy(fpu->fpr, fxsave->st_space, 128);
6055 fpu->fcw = fxsave->cwd;
6056 fpu->fsw = fxsave->swd;
6057 fpu->ftwx = fxsave->twd;
6058 fpu->last_opcode = fxsave->fop;
6059 fpu->last_ip = fxsave->rip;
6060 fpu->last_dp = fxsave->rdp;
6061 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6062
d0752060
HB		 6063 return 0;
6064}
6065
6066int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6067{
98918833
SY		 6068 struct i387_fxsave_struct *fxsave =
6069 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6070
d0752060
HB		 6071 memcpy(fxsave->st_space, fpu->fpr, 128);
6072 fxsave->cwd = fpu->fcw;
6073 fxsave->swd = fpu->fsw;
6074 fxsave->twd = fpu->ftwx;
6075 fxsave->fop = fpu->last_opcode;
6076 fxsave->rip = fpu->last_ip;
6077 fxsave->rdp = fpu->last_dp;
6078 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6079
d0752060
HB		 6080 return 0;
6081}
6082
10ab25cd 6083int fx_init(struct kvm_vcpu *vcpu)
d0752060 6084{
10ab25cd
JK		 6085 int err;
6086
6087 err = fpu_alloc(&vcpu->arch.guest_fpu);
6088 if (err)
6089 return err;
6090
98918833 6091 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 6092
2acf923e
DC		 6093 /*
6094 * Ensure guest xcr0 is valid for loading
6095 */
6096 vcpu->arch.xcr0 = XSTATE_FP;
6097
ad312c7c 6098 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 6099
6100 return 0;
d0752060
HB		 6101}
6102EXPORT_SYMBOL_GPL(fx_init);
6103
98918833
SY		 6104static void fx_free(struct kvm_vcpu *vcpu)
6105{
6106 fpu_free(&vcpu->arch.guest_fpu);
6107}
6108
d0752060
HB		 6109void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6110{
2608d7a1 6111 if (vcpu->guest_fpu_loaded)
d0752060
HB		 6112 return;
6113
2acf923e
DC		 6114 /*
6115 * Restore all possible states in the guest,
6116 * and assume host would use all available bits.
6117 * Guest xcr0 would be loaded later.
6118 */
6119 kvm_put_guest_xcr0(vcpu);
d0752060 6120 vcpu->guest_fpu_loaded = 1;
7cf30855 6121 unlazy_fpu(current);
98918833 6122 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 6123 trace_kvm_fpu(1);
d0752060 6124}
d0752060
HB		 6125
6126void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6127{
2acf923e
DC		 6128 kvm_put_guest_xcr0(vcpu);
6129
d0752060
HB		 6130 if (!vcpu->guest_fpu_loaded)
6131 return;
6132
6133 vcpu->guest_fpu_loaded = 0;
98918833 6134 fpu_save_init(&vcpu->arch.guest_fpu);
f096ed85 6135 ++vcpu->stat.fpu_reload;
a8eeb04a 6136 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 6137 trace_kvm_fpu(0);
d0752060 6138}
e9b11c17
ZX		 6139
6140void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6141{
12f9a48f 6142 kvmclock_reset(vcpu);
7f1ea208 6143
f5f48ee1 6144 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 6145 fx_free(vcpu);
e9b11c17
ZX		 6146 kvm_x86_ops->vcpu_free(vcpu);
6147}
6148
6149struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6150 unsigned int id)
6151{
6755bae8
ZA		 6152 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6153 printk_once(KERN_WARNING
6154 "kvm: SMP vm created on host with unstable TSC; "
6155 "guest TSC will not be reliable\n");
26e5215f
AK		 6156 return kvm_x86_ops->vcpu_create(kvm, id);
6157}
e9b11c17 6158
26e5215f
AK		 6159int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6160{
6161 int r;
e9b11c17 6162
0bed3b56 6163 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 6164 vcpu_load(vcpu);
6165 r = kvm_arch_vcpu_reset(vcpu);
6166 if (r == 0)
6167 r = kvm_mmu_setup(vcpu);
6168 vcpu_put(vcpu);
e9b11c17 6169
26e5215f 6170 return r;
e9b11c17
ZX		 6171}
6172
d40ccc62 6173void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 6174{
344d9588
GN		 6175 vcpu->arch.apf.msr_val = 0;
6176
e9b11c17
ZX		 6177 vcpu_load(vcpu);
6178 kvm_mmu_unload(vcpu);
6179 vcpu_put(vcpu);
6180
98918833 6181 fx_free(vcpu);
e9b11c17
ZX		 6182 kvm_x86_ops->vcpu_free(vcpu);
6183}
6184
6185int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
6186{
448fa4a9
JK		 6187 vcpu->arch.nmi_pending = false;
6188 vcpu->arch.nmi_injected = false;
6189
42dbaa5a
JK		 6190 vcpu->arch.switch_db_regs = 0;
6191 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6192 vcpu->arch.dr6 = DR6_FIXED_1;
6193 vcpu->arch.dr7 = DR7_FIXED_1;
6194
3842d135 6195 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 6196 vcpu->arch.apf.msr_val = 0;
3842d135 6197
12f9a48f
GC		 6198 kvmclock_reset(vcpu);
6199
af585b92
GN		 6200 kvm_clear_async_pf_completion_queue(vcpu);
6201 kvm_async_pf_hash_reset(vcpu);
6202 vcpu->arch.apf.halted = false;
3842d135 6203
e9b11c17
ZX		 6204 return kvm_x86_ops->vcpu_reset(vcpu);
6205}
6206
10474ae8 6207int kvm_arch_hardware_enable(void *garbage)
e9b11c17 6208{
ca84d1a2
ZA		 6209 struct kvm *kvm;
6210 struct kvm_vcpu *vcpu;
6211 int i;
18863bdd
AK		 6212
6213 kvm_shared_msr_cpu_online();
ca84d1a2
ZA		 6214 list_for_each_entry(kvm, &vm_list, vm_list)
6215 kvm_for_each_vcpu(i, vcpu, kvm)
6216 if (vcpu->cpu == smp_processor_id())
c285545f 6217 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
10474ae8 6218 return kvm_x86_ops->hardware_enable(garbage);
e9b11c17
ZX		 6219}
6220
6221void kvm_arch_hardware_disable(void *garbage)
6222{
6223 kvm_x86_ops->hardware_disable(garbage);
3548bab5 6224 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 6225}
6226
6227int kvm_arch_hardware_setup(void)
6228{
6229 return kvm_x86_ops->hardware_setup();
6230}
6231
6232void kvm_arch_hardware_unsetup(void)
6233{
6234 kvm_x86_ops->hardware_unsetup();
6235}
6236
6237void kvm_arch_check_processor_compat(void *rtn)
6238{
6239 kvm_x86_ops->check_processor_compatibility(rtn);
6240}
6241
6242int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6243{
6244 struct page *page;
6245 struct kvm *kvm;
6246 int r;
6247
6248 BUG_ON(vcpu->kvm == NULL);
6249 kvm = vcpu->kvm;
6250
9aabc88f 6251 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
14dfe855 6252 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
ad312c7c 6253 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c30a358d 6254 vcpu->arch.mmu.translate_gpa = translate_gpa;
02f59dc9 6255 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
c5af89b6 6256 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 6257 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 6258 else
a4535290 6259 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 6260
6261 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6262 if (!page) {
6263 r = -ENOMEM;
6264 goto fail;
6265 }
ad312c7c 6266 vcpu->arch.pio_data = page_address(page);
e9b11c17 6267
1e993611 6268 kvm_init_tsc_catchup(vcpu, max_tsc_khz);
c285545f 6269
e9b11c17
ZX		 6270 r = kvm_mmu_create(vcpu);
6271 if (r < 0)
6272 goto fail_free_pio_data;
6273
6274 if (irqchip_in_kernel(kvm)) {
6275 r = kvm_create_lapic(vcpu);
6276 if (r < 0)
6277 goto fail_mmu_destroy;
6278 }
6279
890ca9ae
HY		 6280 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6281 GFP_KERNEL);
6282 if (!vcpu->arch.mce_banks) {
6283 r = -ENOMEM;
443c39bc 6284 goto fail_free_lapic;
890ca9ae
HY		 6285 }
6286 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6287
f5f48ee1
SY		 6288 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
6289 goto fail_free_mce_banks;
6290
af585b92
GN		 6291 kvm_async_pf_hash_reset(vcpu);
6292
e9b11c17 6293 return 0;
f5f48ee1
SY		 6294fail_free_mce_banks:
6295 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 6296fail_free_lapic:
6297 kvm_free_lapic(vcpu);
e9b11c17
ZX		 6298fail_mmu_destroy:
6299 kvm_mmu_destroy(vcpu);
6300fail_free_pio_data:
ad312c7c 6301 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 6302fail:
6303 return r;
6304}
6305
6306void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6307{
f656ce01
MT		 6308 int idx;
6309
36cb93fd 6310 kfree(vcpu->arch.mce_banks);
e9b11c17 6311 kvm_free_lapic(vcpu);
f656ce01 6312 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 6313 kvm_mmu_destroy(vcpu);
f656ce01 6314 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 6315 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 6316}
d19a9cd2 6317
d89f5eff 6318int kvm_arch_init_vm(struct kvm *kvm)
d19a9cd2 6319{
f05e70ac 6320 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 6321 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 6322
5550af4d
SY		 6323 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
6324 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
6325
038f8c11 6326 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
53f658b3 6327
d89f5eff 6328 return 0;
d19a9cd2
ZX		 6329}
6330
6331static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
6332{
6333 vcpu_load(vcpu);
6334 kvm_mmu_unload(vcpu);
6335 vcpu_put(vcpu);
6336}
6337
6338static void kvm_free_vcpus(struct kvm *kvm)
6339{
6340 unsigned int i;
988a2cae 6341 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 6342
6343 /*
6344 * Unpin any mmu pages first.
6345 */
af585b92
GN		 6346 kvm_for_each_vcpu(i, vcpu, kvm) {
6347 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 6348 kvm_unload_vcpu_mmu(vcpu);
af585b92 6349 }
988a2cae
GN		 6350 kvm_for_each_vcpu(i, vcpu, kvm)
6351 kvm_arch_vcpu_free(vcpu);
6352
6353 mutex_lock(&kvm->lock);
6354 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
6355 kvm->vcpus[i] = NULL;
d19a9cd2 6356
988a2cae
GN		 6357 atomic_set(&kvm->online_vcpus, 0);
6358 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 6359}
6360
ad8ba2cd
SY		 6361void kvm_arch_sync_events(struct kvm *kvm)
6362{
ba4cef31 6363 kvm_free_all_assigned_devices(kvm);
aea924f6 6364 kvm_free_pit(kvm);
ad8ba2cd
SY		 6365}
6366
d19a9cd2
ZX		 6367void kvm_arch_destroy_vm(struct kvm *kvm)
6368{
6eb55818 6369 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 6370 kfree(kvm->arch.vpic);
6371 kfree(kvm->arch.vioapic);
d19a9cd2 6372 kvm_free_vcpus(kvm);
3d45830c
AK		 6373 if (kvm->arch.apic_access_page)
6374 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 6375 if (kvm->arch.ept_identity_pagetable)
6376 put_page(kvm->arch.ept_identity_pagetable);
d19a9cd2 6377}
0de10343 6378
f7784b8e
MT		 6379int kvm_arch_prepare_memory_region(struct kvm *kvm,
6380 struct kvm_memory_slot *memslot,
0de10343 6381 struct kvm_memory_slot old,
f7784b8e 6382 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 6383 int user_alloc)
6384{
f7784b8e 6385 int npages = memslot->npages;
7ac77099
AK		 6386 int map_flags = MAP_PRIVATE | MAP_ANONYMOUS;
6387
6388 /* Prevent internal slot pages from being moved by fork()/COW. */
6389 if (memslot->id >= KVM_MEMORY_SLOTS)
6390 map_flags = MAP_SHARED | MAP_ANONYMOUS;
0de10343
ZX		 6391
6392 /*To keep backward compatibility with older userspace,
6393 *x86 needs to hanlde !user_alloc case.
6394 */
6395 if (!user_alloc) {
6396 if (npages && !old.rmap) {
604b38ac
AA		 6397 unsigned long userspace_addr;
6398
72dc67a6 6399 down_write(&current->mm->mmap_sem);
604b38ac
AA		 6400 userspace_addr = do_mmap(NULL, 0,
6401 npages * PAGE_SIZE,
6402 PROT_READ | PROT_WRITE,
7ac77099 6403 map_flags,
604b38ac 6404 0);
72dc67a6 6405 up_write(&current->mm->mmap_sem);
0de10343 6406
604b38ac
AA		 6407 if (IS_ERR((void *)userspace_addr))
6408 return PTR_ERR((void *)userspace_addr);
6409
604b38ac 6410 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 6411 }
6412 }
6413
f7784b8e
MT		 6414
6415 return 0;
6416}
6417
6418void kvm_arch_commit_memory_region(struct kvm *kvm,
6419 struct kvm_userspace_memory_region *mem,
6420 struct kvm_memory_slot old,
6421 int user_alloc)
6422{
6423
48c0e4e9 6424 int nr_mmu_pages = 0, npages = mem->memory_size >> PAGE_SHIFT;
f7784b8e
MT		 6425
6426 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
6427 int ret;
6428
6429 down_write(&current->mm->mmap_sem);
6430 ret = do_munmap(current->mm, old.userspace_addr,
6431 old.npages * PAGE_SIZE);
6432 up_write(&current->mm->mmap_sem);
6433 if (ret < 0)
6434 printk(KERN_WARNING
6435 "kvm_vm_ioctl_set_memory_region: "
6436 "failed to munmap memory\n");
6437 }
6438
48c0e4e9
XG		 6439 if (!kvm->arch.n_requested_mmu_pages)
6440 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
6441
7c8a83b7 6442 spin_lock(&kvm->mmu_lock);
48c0e4e9 6443 if (nr_mmu_pages)
0de10343 6444 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
0de10343 6445 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 6446 spin_unlock(&kvm->mmu_lock);
0de10343 6447}
1d737c8a 6448
34d4cb8f
MT		 6449void kvm_arch_flush_shadow(struct kvm *kvm)
6450{
6451 kvm_mmu_zap_all(kvm);
8986ecc0 6452 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 6453}
6454
1d737c8a
ZX		 6455int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
6456{
af585b92
GN		 6457 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6458 !vcpu->arch.apf.halted)
6459 || !list_empty_careful(&vcpu->async_pf.done)
a1b37100
GN		 6460 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
6461 || vcpu->arch.nmi_pending ||
6462 (kvm_arch_interrupt_allowed(vcpu) &&
6463 kvm_cpu_has_interrupt(vcpu));
1d737c8a 6464}
5736199a 6465
5736199a
ZX		 6466void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
6467{
32f88400
MT		 6468 int me;
6469 int cpu = vcpu->cpu;
5736199a
ZX		 6470
6471 if (waitqueue_active(&vcpu->wq)) {
6472 wake_up_interruptible(&vcpu->wq);
6473 ++vcpu->stat.halt_wakeup;
6474 }
32f88400
MT		 6475
6476 me = get_cpu();
6477 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
6b7e2d09 6478 if (kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE)
32f88400 6479 smp_send_reschedule(cpu);
e9571ed5 6480 put_cpu();
5736199a 6481}
78646121
GN		 6482
6483int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
6484{
6485 return kvm_x86_ops->interrupt_allowed(vcpu);
6486}
229456fc 6487
f92653ee
JK		 6488bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
6489{
6490 unsigned long current_rip = kvm_rip_read(vcpu) +
6491 get_segment_base(vcpu, VCPU_SREG_CS);
6492
6493 return current_rip == linear_rip;
6494}
6495EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
6496
94fe45da
JK		 6497unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
6498{
6499 unsigned long rflags;
6500
6501 rflags = kvm_x86_ops->get_rflags(vcpu);
6502 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 6503 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 6504 return rflags;
6505}
6506EXPORT_SYMBOL_GPL(kvm_get_rflags);
6507
6508void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
6509{
6510 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 6511 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 6512 rflags |= X86_EFLAGS_TF;
94fe45da 6513 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 6514 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 6515}
6516EXPORT_SYMBOL_GPL(kvm_set_rflags);
6517
56028d08
GN		 6518void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
6519{
6520 int r;
6521
fb67e14f 6522 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
c4806acd 6523 is_error_page(work->page))
56028d08
GN		 6524 return;
6525
6526 r = kvm_mmu_reload(vcpu);
6527 if (unlikely(r))
6528 return;
6529
fb67e14f
XG		 6530 if (!vcpu->arch.mmu.direct_map &&
6531 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
6532 return;
6533
56028d08
GN		 6534 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
6535}
6536
af585b92
GN		 6537static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
6538{
6539 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
6540}
6541
6542static inline u32 kvm_async_pf_next_probe(u32 key)
6543{
6544 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
6545}
6546
6547static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6548{
6549 u32 key = kvm_async_pf_hash_fn(gfn);
6550
6551 while (vcpu->arch.apf.gfns[key] != ~0)
6552 key = kvm_async_pf_next_probe(key);
6553
6554 vcpu->arch.apf.gfns[key] = gfn;
6555}
6556
6557static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
6558{
6559 int i;
6560 u32 key = kvm_async_pf_hash_fn(gfn);
6561
6562 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 6563 (vcpu->arch.apf.gfns[key] != gfn &&
6564 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 6565 key = kvm_async_pf_next_probe(key);
6566
6567 return key;
6568}
6569
6570bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6571{
6572 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
6573}
6574
6575static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6576{
6577 u32 i, j, k;
6578
6579 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
6580 while (true) {
6581 vcpu->arch.apf.gfns[i] = ~0;
6582 do {
6583 j = kvm_async_pf_next_probe(j);
6584 if (vcpu->arch.apf.gfns[j] == ~0)
6585 return;
6586 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
6587 /*
6588 * k lies cyclically in ]i,j]
6589 * | i.k.j |
6590 * |....j i.k.| or |.k..j i...|
6591 */
6592 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
6593 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
6594 i = j;
6595 }
6596}
6597
7c90705b
GN		 6598static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
6599{
6600
6601 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
6602 sizeof(val));
6603}
6604
af585b92
GN		 6605void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
6606 struct kvm_async_pf *work)
6607{
6389ee94
AK		 6608 struct x86_exception fault;
6609
7c90705b 6610 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 6611 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 6612
6613 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 6614 (vcpu->arch.apf.send_user_only &&
6615 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 6616 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
6617 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 6618 fault.vector = PF_VECTOR;
6619 fault.error_code_valid = true;
6620 fault.error_code = 0;
6621 fault.nested_page_fault = false;
6622 fault.address = work->arch.token;
6623 kvm_inject_page_fault(vcpu, &fault);
7c90705b 6624 }
af585b92
GN		 6625}
6626
6627void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
6628 struct kvm_async_pf *work)
6629{
6389ee94
AK		 6630 struct x86_exception fault;
6631
7c90705b
GN		 6632 trace_kvm_async_pf_ready(work->arch.token, work->gva);
6633 if (is_error_page(work->page))
6634 work->arch.token = ~0; /* broadcast wakeup */
6635 else
6636 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
6637
6638 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
6639 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 6640 fault.vector = PF_VECTOR;
6641 fault.error_code_valid = true;
6642 fault.error_code = 0;
6643 fault.nested_page_fault = false;
6644 fault.address = work->arch.token;
6645 kvm_inject_page_fault(vcpu, &fault);
7c90705b 6646 }
e6d53e3b 6647 vcpu->arch.apf.halted = false;
7c90705b
GN		 6648}
6649
6650bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
6651{
6652 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
6653 return true;
6654 else
6655 return !kvm_event_needs_reinjection(vcpu) &&
6656 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 6657}
6658
229456fc
MT		 6659EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
6660EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
6661EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
6662EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
6663EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 6664EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 6665EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 6666EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 6667EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 6668EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 6669EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 6670EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
kernel source for telekom puls (alcatel/mediatek)