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KVM: x86 emulator: Allow PM/VM86 switch during task switch
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
313a3dc7 30
18068523 31#include <linux/clocksource.h>
4d5c5d0f 32#include <linux/interrupt.h>
313a3dc7
CO		 33#include <linux/kvm.h>
34#include <linux/fs.h>
35#include <linux/vmalloc.h>
5fb76f9b 36#include <linux/module.h>
0de10343 37#include <linux/mman.h>
2bacc55c 38#include <linux/highmem.h>
19de40a8 39#include <linux/iommu.h>
62c476c7 40#include <linux/intel-iommu.h>
c8076604 41#include <linux/cpufreq.h>
18863bdd 42#include <linux/user-return-notifier.h>
a983fb23 43#include <linux/srcu.h>
5a0e3ad6 44#include <linux/slab.h>
ff9d07a0 45#include <linux/perf_event.h>
7bee342a 46#include <linux/uaccess.h>
af585b92 47#include <linux/hash.h>
a1b60c1c 48#include <linux/pci.h>
aec51dc4 49#include <trace/events/kvm.h>
2ed152af 50
229456fc
MT		 51#define CREATE_TRACE_POINTS
52#include "trace.h"
043405e1 53
24f1e32c 54#include <asm/debugreg.h>
d825ed0a 55#include <asm/msr.h>
a5f61300 56#include <asm/desc.h>
0bed3b56 57#include <asm/mtrr.h>
890ca9ae 58#include <asm/mce.h>
7cf30855 59#include <asm/i387.h>
98918833 60#include <asm/xcr.h>
1d5f066e 61#include <asm/pvclock.h>
217fc9cf 62#include <asm/div64.h>
043405e1 63
313a3dc7 64#define MAX_IO_MSRS 256
890ca9ae 65#define KVM_MAX_MCE_BANKS 32
5854dbca 66#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 67
0f65dd70
AK		 68#define emul_to_vcpu(ctxt) \
69 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
70
50a37eb4
JR		 71/* EFER defaults:
72 * - enable syscall per default because its emulated by KVM
73 * - enable LME and LMA per default on 64 bit KVM
74 */
75#ifdef CONFIG_X86_64
1260edbe
LJ		 76static
77u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 78#else
1260edbe 79static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 80#endif
313a3dc7 81
ba1389b7
AK		 82#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
83#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 84
cb142eb7 85static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 86static void process_nmi(struct kvm_vcpu *vcpu);
674eea0f 87
97896d04 88struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 89EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 90
476bc001
RR		 91static bool ignore_msrs = 0;
92module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 93
92a1f12d
JR		 94bool kvm_has_tsc_control;
95EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
96u32 kvm_max_guest_tsc_khz;
97EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
98
cc578287
ZA		 99/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
100static u32 tsc_tolerance_ppm = 250;
101module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
102
18863bdd
AK		 103#define KVM_NR_SHARED_MSRS 16
104
105struct kvm_shared_msrs_global {
106 int nr;
2bf78fa7 107 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 108};
109
110struct kvm_shared_msrs {
111 struct user_return_notifier urn;
112 bool registered;
2bf78fa7
SY		 113 struct kvm_shared_msr_values {
114 u64 host;
115 u64 curr;
116 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 117};
118
119static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
120static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
121
417bc304 122struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 123 { "pf_fixed", VCPU_STAT(pf_fixed) },
124 { "pf_guest", VCPU_STAT(pf_guest) },
125 { "tlb_flush", VCPU_STAT(tlb_flush) },
126 { "invlpg", VCPU_STAT(invlpg) },
127 { "exits", VCPU_STAT(exits) },
128 { "io_exits", VCPU_STAT(io_exits) },
129 { "mmio_exits", VCPU_STAT(mmio_exits) },
130 { "signal_exits", VCPU_STAT(signal_exits) },
131 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 132 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 133 { "halt_exits", VCPU_STAT(halt_exits) },
134 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 135 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 136 { "request_irq", VCPU_STAT(request_irq_exits) },
137 { "irq_exits", VCPU_STAT(irq_exits) },
138 { "host_state_reload", VCPU_STAT(host_state_reload) },
139 { "efer_reload", VCPU_STAT(efer_reload) },
140 { "fpu_reload", VCPU_STAT(fpu_reload) },
141 { "insn_emulation", VCPU_STAT(insn_emulation) },
142 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 143 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 144 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 145 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
146 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
147 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
148 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
149 { "mmu_flooded", VM_STAT(mmu_flooded) },
150 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 151 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 152 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 153 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 154 { "largepages", VM_STAT(lpages) },
417bc304
HB		 155 { NULL }
156};
157
2acf923e
DC		 158u64 __read_mostly host_xcr0;
159
d6aa1000
AK		 160int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
161
af585b92
GN		 162static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
163{
164 int i;
165 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
166 vcpu->arch.apf.gfns[i] = ~0;
167}
168
18863bdd
AK		 169static void kvm_on_user_return(struct user_return_notifier *urn)
170{
171 unsigned slot;
18863bdd
AK		 172 struct kvm_shared_msrs *locals
173 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 174 struct kvm_shared_msr_values *values;
18863bdd
AK		 175
176 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 177 values = &locals->values[slot];
178 if (values->host != values->curr) {
179 wrmsrl(shared_msrs_global.msrs[slot], values->host);
180 values->curr = values->host;
18863bdd
AK		 181 }
182 }
183 locals->registered = false;
184 user_return_notifier_unregister(urn);
185}
186
2bf78fa7 187static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 188{
2bf78fa7 189 struct kvm_shared_msrs *smsr;
18863bdd
AK		 190 u64 value;
191
2bf78fa7
SY		 192 smsr = &__get_cpu_var(shared_msrs);
193 /* only read, and nobody should modify it at this time,
194 * so don't need lock */
195 if (slot >= shared_msrs_global.nr) {
196 printk(KERN_ERR "kvm: invalid MSR slot!");
197 return;
198 }
199 rdmsrl_safe(msr, &value);
200 smsr->values[slot].host = value;
201 smsr->values[slot].curr = value;
202}
203
204void kvm_define_shared_msr(unsigned slot, u32 msr)
205{
18863bdd
AK		 206 if (slot >= shared_msrs_global.nr)
207 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 208 shared_msrs_global.msrs[slot] = msr;
209 /* we need ensured the shared_msr_global have been updated */
210 smp_wmb();
18863bdd
AK		 211}
212EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
213
214static void kvm_shared_msr_cpu_online(void)
215{
216 unsigned i;
18863bdd
AK		 217
218 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 219 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 220}
221
d5696725 222void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 223{
224 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
225
2bf78fa7 226 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 227 return;
2bf78fa7
SY		 228 smsr->values[slot].curr = value;
229 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 230 if (!smsr->registered) {
231 smsr->urn.on_user_return = kvm_on_user_return;
232 user_return_notifier_register(&smsr->urn);
233 smsr->registered = true;
234 }
235}
236EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
237
3548bab5
AK		 238static void drop_user_return_notifiers(void *ignore)
239{
240 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
241
242 if (smsr->registered)
243 kvm_on_user_return(&smsr->urn);
244}
245
6866b83e
CO		 246u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
247{
248 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 249 return vcpu->arch.apic_base;
6866b83e 250 else
ad312c7c 251 return vcpu->arch.apic_base;
6866b83e
CO		 252}
253EXPORT_SYMBOL_GPL(kvm_get_apic_base);
254
255void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
256{
257 /* TODO: reserve bits check */
258 if (irqchip_in_kernel(vcpu->kvm))
259 kvm_lapic_set_base(vcpu, data);
260 else
ad312c7c 261 vcpu->arch.apic_base = data;
6866b83e
CO		 262}
263EXPORT_SYMBOL_GPL(kvm_set_apic_base);
264
3fd28fce
ED		 265#define EXCPT_BENIGN 0
266#define EXCPT_CONTRIBUTORY 1
267#define EXCPT_PF 2
268
269static int exception_class(int vector)
270{
271 switch (vector) {
272 case PF_VECTOR:
273 return EXCPT_PF;
274 case DE_VECTOR:
275 case TS_VECTOR:
276 case NP_VECTOR:
277 case SS_VECTOR:
278 case GP_VECTOR:
279 return EXCPT_CONTRIBUTORY;
280 default:
281 break;
282 }
283 return EXCPT_BENIGN;
284}
285
286static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 287 unsigned nr, bool has_error, u32 error_code,
288 bool reinject)
3fd28fce
ED		 289{
290 u32 prev_nr;
291 int class1, class2;
292
3842d135
AK		 293 kvm_make_request(KVM_REQ_EVENT, vcpu);
294
3fd28fce
ED		 295 if (!vcpu->arch.exception.pending) {
296 queue:
297 vcpu->arch.exception.pending = true;
298 vcpu->arch.exception.has_error_code = has_error;
299 vcpu->arch.exception.nr = nr;
300 vcpu->arch.exception.error_code = error_code;
3f0fd292 301 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 302 return;
303 }
304
305 /* to check exception */
306 prev_nr = vcpu->arch.exception.nr;
307 if (prev_nr == DF_VECTOR) {
308 /* triple fault -> shutdown */
a8eeb04a 309 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 310 return;
311 }
312 class1 = exception_class(prev_nr);
313 class2 = exception_class(nr);
314 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
315 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
316 /* generate double fault per SDM Table 5-5 */
317 vcpu->arch.exception.pending = true;
318 vcpu->arch.exception.has_error_code = true;
319 vcpu->arch.exception.nr = DF_VECTOR;
320 vcpu->arch.exception.error_code = 0;
321 } else
322 /* replace previous exception with a new one in a hope
323 that instruction re-execution will regenerate lost
324 exception */
325 goto queue;
326}
327
298101da
AK		 328void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
329{
ce7ddec4 330 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 331}
332EXPORT_SYMBOL_GPL(kvm_queue_exception);
333
ce7ddec4
JR		 334void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
335{
336 kvm_multiple_exception(vcpu, nr, false, 0, true);
337}
338EXPORT_SYMBOL_GPL(kvm_requeue_exception);
339
db8fcefa 340void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 341{
db8fcefa
AP		 342 if (err)
343 kvm_inject_gp(vcpu, 0);
344 else
345 kvm_x86_ops->skip_emulated_instruction(vcpu);
346}
347EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 348
6389ee94 349void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 350{
351 ++vcpu->stat.pf_guest;
6389ee94
AK		 352 vcpu->arch.cr2 = fault->address;
353 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 354}
27d6c865 355EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 356
6389ee94 357void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 358{
6389ee94
AK		 359 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
360 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 361 else
6389ee94 362 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
d4f8cf66
JR		 363}
364
3419ffc8
SY		 365void kvm_inject_nmi(struct kvm_vcpu *vcpu)
366{
7460fb4a
AK		 367 atomic_inc(&vcpu->arch.nmi_queued);
368 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 369}
370EXPORT_SYMBOL_GPL(kvm_inject_nmi);
371
298101da
AK		 372void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
373{
ce7ddec4 374 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 375}
376EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
377
ce7ddec4
JR		 378void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
379{
380 kvm_multiple_exception(vcpu, nr, true, error_code, true);
381}
382EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
383
0a79b009
AK		 384/*
385 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
386 * a #GP and return false.
387 */
388bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 389{
0a79b009
AK		 390 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
391 return true;
392 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
393 return false;
298101da 394}
0a79b009 395EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 396
ec92fe44
JR		 397/*
398 * This function will be used to read from the physical memory of the currently
399 * running guest. The difference to kvm_read_guest_page is that this function
400 * can read from guest physical or from the guest's guest physical memory.
401 */
402int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
403 gfn_t ngfn, void *data, int offset, int len,
404 u32 access)
405{
406 gfn_t real_gfn;
407 gpa_t ngpa;
408
409 ngpa = gfn_to_gpa(ngfn);
410 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
411 if (real_gfn == UNMAPPED_GVA)
412 return -EFAULT;
413
414 real_gfn = gpa_to_gfn(real_gfn);
415
416 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
417}
418EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
419
3d06b8bf
JR		 420int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
421 void *data, int offset, int len, u32 access)
422{
423 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
424 data, offset, len, access);
425}
426
a03490ed
CO		 427/*
428 * Load the pae pdptrs. Return true is they are all valid.
429 */
ff03a073 430int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 431{
432 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
433 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
434 int i;
435 int ret;
ff03a073 436 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 437
ff03a073
JR		 438 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
439 offset * sizeof(u64), sizeof(pdpte),
440 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 441 if (ret < 0) {
442 ret = 0;
443 goto out;
444 }
445 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 446 if (is_present_gpte(pdpte[i]) &&
20c466b5 447 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 448 ret = 0;
449 goto out;
450 }
451 }
452 ret = 1;
453
ff03a073 454 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 455 __set_bit(VCPU_EXREG_PDPTR,
456 (unsigned long *)&vcpu->arch.regs_avail);
457 __set_bit(VCPU_EXREG_PDPTR,
458 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 459out:
a03490ed
CO		 460
461 return ret;
462}
cc4b6871 463EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 464
d835dfec
AK		 465static bool pdptrs_changed(struct kvm_vcpu *vcpu)
466{
ff03a073 467 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 468 bool changed = true;
3d06b8bf
JR		 469 int offset;
470 gfn_t gfn;
d835dfec
AK		 471 int r;
472
473 if (is_long_mode(vcpu) || !is_pae(vcpu))
474 return false;
475
6de4f3ad
AK		 476 if (!test_bit(VCPU_EXREG_PDPTR,
477 (unsigned long *)&vcpu->arch.regs_avail))
478 return true;
479
9f8fe504
AK		 480 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
481 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 482 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
483 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 484 if (r < 0)
485 goto out;
ff03a073 486 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 487out:
d835dfec
AK		 488
489 return changed;
490}
491
49a9b07e 492int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 493{
aad82703
SY		 494 unsigned long old_cr0 = kvm_read_cr0(vcpu);
495 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
496 X86_CR0_CD | X86_CR0_NW;
497
f9a48e6a
AK		 498 cr0 |= X86_CR0_ET;
499
ab344828 500#ifdef CONFIG_X86_64
0f12244f
GN		 501 if (cr0 & 0xffffffff00000000UL)
502 return 1;
ab344828
GN		 503#endif
504
505 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 506
0f12244f
GN		 507 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
508 return 1;
a03490ed 509
0f12244f
GN		 510 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
511 return 1;
a03490ed
CO		 512
513 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
514#ifdef CONFIG_X86_64
f6801dff 515 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 516 int cs_db, cs_l;
517
0f12244f
GN		 518 if (!is_pae(vcpu))
519 return 1;
a03490ed 520 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 521 if (cs_l)
522 return 1;
a03490ed
CO		 523 } else
524#endif
ff03a073 525 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 526 kvm_read_cr3(vcpu)))
0f12244f 527 return 1;
a03490ed
CO		 528 }
529
530 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 531
d170c419 532 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 533 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 534 kvm_async_pf_hash_reset(vcpu);
535 }
e5f3f027 536
aad82703
SY		 537 if ((cr0 ^ old_cr0) & update_bits)
538 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 539 return 0;
540}
2d3ad1f4 541EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 542
2d3ad1f4 543void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 544{
49a9b07e 545 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 546}
2d3ad1f4 547EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 548
2acf923e
DC		 549int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
550{
551 u64 xcr0;
552
553 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
554 if (index != XCR_XFEATURE_ENABLED_MASK)
555 return 1;
556 xcr0 = xcr;
557 if (kvm_x86_ops->get_cpl(vcpu) != 0)
558 return 1;
559 if (!(xcr0 & XSTATE_FP))
560 return 1;
561 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
562 return 1;
563 if (xcr0 & ~host_xcr0)
564 return 1;
565 vcpu->arch.xcr0 = xcr0;
566 vcpu->guest_xcr0_loaded = 0;
567 return 0;
568}
569
570int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
571{
572 if (__kvm_set_xcr(vcpu, index, xcr)) {
573 kvm_inject_gp(vcpu, 0);
574 return 1;
575 }
576 return 0;
577}
578EXPORT_SYMBOL_GPL(kvm_set_xcr);
579
a83b29c6 580int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 581{
fc78f519 582 unsigned long old_cr4 = kvm_read_cr4(vcpu);
c68b734f
YW		 583 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
584 X86_CR4_PAE | X86_CR4_SMEP;
0f12244f
GN		 585 if (cr4 & CR4_RESERVED_BITS)
586 return 1;
a03490ed 587
2acf923e
DC		 588 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
589 return 1;
590
c68b734f
YW		 591 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
592 return 1;
593
74dc2b4f
YW		 594 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_RDWRGSFS))
595 return 1;
596
a03490ed 597 if (is_long_mode(vcpu)) {
0f12244f
GN		 598 if (!(cr4 & X86_CR4_PAE))
599 return 1;
a2edf57f
AK		 600 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
601 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 602 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
603 kvm_read_cr3(vcpu)))
0f12244f
GN		 604 return 1;
605
5e1746d6 606 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 607 return 1;
a03490ed 608
aad82703
SY		 609 if ((cr4 ^ old_cr4) & pdptr_bits)
610 kvm_mmu_reset_context(vcpu);
0f12244f 611
2acf923e 612 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 613 kvm_update_cpuid(vcpu);
2acf923e 614
0f12244f
GN		 615 return 0;
616}
2d3ad1f4 617EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 618
2390218b 619int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 620{
9f8fe504 621 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 622 kvm_mmu_sync_roots(vcpu);
d835dfec 623 kvm_mmu_flush_tlb(vcpu);
0f12244f 624 return 0;
d835dfec
AK		 625 }
626
a03490ed 627 if (is_long_mode(vcpu)) {
0f12244f
GN		 628 if (cr3 & CR3_L_MODE_RESERVED_BITS)
629 return 1;
a03490ed
CO		 630 } else {
631 if (is_pae(vcpu)) {
0f12244f
GN		 632 if (cr3 & CR3_PAE_RESERVED_BITS)
633 return 1;
ff03a073
JR		 634 if (is_paging(vcpu) &&
635 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
0f12244f 636 return 1;
a03490ed
CO		 637 }
638 /*
639 * We don't check reserved bits in nonpae mode, because
640 * this isn't enforced, and VMware depends on this.
641 */
642 }
643
a03490ed
CO		 644 /*
645 * Does the new cr3 value map to physical memory? (Note, we
646 * catch an invalid cr3 even in real-mode, because it would
647 * cause trouble later on when we turn on paging anyway.)
648 *
649 * A real CPU would silently accept an invalid cr3 and would
650 * attempt to use it - with largely undefined (and often hard
651 * to debug) behavior on the guest side.
652 */
653 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
0f12244f
GN		 654 return 1;
655 vcpu->arch.cr3 = cr3;
aff48baa 656 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
0f12244f
GN		 657 vcpu->arch.mmu.new_cr3(vcpu);
658 return 0;
659}
2d3ad1f4 660EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 661
eea1cff9 662int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 663{
0f12244f
GN		 664 if (cr8 & CR8_RESERVED_BITS)
665 return 1;
a03490ed
CO		 666 if (irqchip_in_kernel(vcpu->kvm))
667 kvm_lapic_set_tpr(vcpu, cr8);
668 else
ad312c7c 669 vcpu->arch.cr8 = cr8;
0f12244f
GN		 670 return 0;
671}
2d3ad1f4 672EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 673
2d3ad1f4 674unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 675{
676 if (irqchip_in_kernel(vcpu->kvm))
677 return kvm_lapic_get_cr8(vcpu);
678 else
ad312c7c 679 return vcpu->arch.cr8;
a03490ed 680}
2d3ad1f4 681EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 682
338dbc97 683static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 684{
685 switch (dr) {
686 case 0 ... 3:
687 vcpu->arch.db[dr] = val;
688 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
689 vcpu->arch.eff_db[dr] = val;
690 break;
691 case 4:
338dbc97
GN		 692 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
693 return 1; /* #UD */
020df079
GN		 694 /* fall through */
695 case 6:
338dbc97
GN		 696 if (val & 0xffffffff00000000ULL)
697 return -1; /* #GP */
020df079
GN		 698 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
699 break;
700 case 5:
338dbc97
GN		 701 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
702 return 1; /* #UD */
020df079
GN		 703 /* fall through */
704 default: /* 7 */
338dbc97
GN		 705 if (val & 0xffffffff00000000ULL)
706 return -1; /* #GP */
020df079
GN		 707 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
708 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
709 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
710 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
711 }
712 break;
713 }
714
715 return 0;
716}
338dbc97
GN		 717
718int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
719{
720 int res;
721
722 res = __kvm_set_dr(vcpu, dr, val);
723 if (res > 0)
724 kvm_queue_exception(vcpu, UD_VECTOR);
725 else if (res < 0)
726 kvm_inject_gp(vcpu, 0);
727
728 return res;
729}
020df079
GN		 730EXPORT_SYMBOL_GPL(kvm_set_dr);
731
338dbc97 732static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 733{
734 switch (dr) {
735 case 0 ... 3:
736 *val = vcpu->arch.db[dr];
737 break;
738 case 4:
338dbc97 739 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 740 return 1;
020df079
GN		 741 /* fall through */
742 case 6:
743 *val = vcpu->arch.dr6;
744 break;
745 case 5:
338dbc97 746 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 747 return 1;
020df079
GN		 748 /* fall through */
749 default: /* 7 */
750 *val = vcpu->arch.dr7;
751 break;
752 }
753
754 return 0;
755}
338dbc97
GN		 756
757int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
758{
759 if (_kvm_get_dr(vcpu, dr, val)) {
760 kvm_queue_exception(vcpu, UD_VECTOR);
761 return 1;
762 }
763 return 0;
764}
020df079
GN		 765EXPORT_SYMBOL_GPL(kvm_get_dr);
766
022cd0e8
AK		 767bool kvm_rdpmc(struct kvm_vcpu *vcpu)
768{
769 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
770 u64 data;
771 int err;
772
773 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
774 if (err)
775 return err;
776 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
777 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
778 return err;
779}
780EXPORT_SYMBOL_GPL(kvm_rdpmc);
781
043405e1
CO		 782/*
783 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
784 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
785 *
786 * This list is modified at module load time to reflect the
e3267cbb
GC		 787 * capabilities of the host cpu. This capabilities test skips MSRs that are
788 * kvm-specific. Those are put in the beginning of the list.
043405e1 789 */
e3267cbb 790
c9aaa895 791#define KVM_SAVE_MSRS_BEGIN 9
043405e1 792static u32 msrs_to_save[] = {
e3267cbb 793 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 794 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 795 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
c9aaa895 796 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
043405e1 797 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 798 MSR_STAR,
043405e1
CO		 799#ifdef CONFIG_X86_64
800 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
801#endif
e90aa41e 802 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 803};
804
805static unsigned num_msrs_to_save;
806
807static u32 emulated_msrs[] = {
a3e06bbe 808 MSR_IA32_TSCDEADLINE,
043405e1 809 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 810 MSR_IA32_MCG_STATUS,
811 MSR_IA32_MCG_CTL,
043405e1
CO		 812};
813
b69e8cae 814static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 815{
aad82703
SY		 816 u64 old_efer = vcpu->arch.efer;
817
b69e8cae
RJ		 818 if (efer & efer_reserved_bits)
819 return 1;
15c4a640
CO		 820
821 if (is_paging(vcpu)
b69e8cae
RJ		 822 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
823 return 1;
15c4a640 824
1b2fd70c
AG		 825 if (efer & EFER_FFXSR) {
826 struct kvm_cpuid_entry2 *feat;
827
828 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 829 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
830 return 1;
1b2fd70c
AG		 831 }
832
d8017474
AG		 833 if (efer & EFER_SVME) {
834 struct kvm_cpuid_entry2 *feat;
835
836 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 837 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
838 return 1;
d8017474
AG		 839 }
840
15c4a640 841 efer &= ~EFER_LMA;
f6801dff 842 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 843
a3d204e2
SY		 844 kvm_x86_ops->set_efer(vcpu, efer);
845
9645bb56 846 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
b69e8cae 847
aad82703
SY		 848 /* Update reserved bits */
849 if ((efer ^ old_efer) & EFER_NX)
850 kvm_mmu_reset_context(vcpu);
851
b69e8cae 852 return 0;
15c4a640
CO		 853}
854
f2b4b7dd
JR		 855void kvm_enable_efer_bits(u64 mask)
856{
857 efer_reserved_bits &= ~mask;
858}
859EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
860
861
15c4a640
CO		 862/*
863 * Writes msr value into into the appropriate "register".
864 * Returns 0 on success, non-0 otherwise.
865 * Assumes vcpu_load() was already called.
866 */
867int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
868{
869 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
870}
871
313a3dc7
CO		 872/*
873 * Adapt set_msr() to msr_io()'s calling convention
874 */
875static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
876{
877 return kvm_set_msr(vcpu, index, *data);
878}
879
18068523
GOC		 880static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
881{
9ed3c444
AK		 882 int version;
883 int r;
50d0a0f9 884 struct pvclock_wall_clock wc;
923de3cf 885 struct timespec boot;
18068523
GOC		 886
887 if (!wall_clock)
888 return;
889
9ed3c444
AK		 890 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
891 if (r)
892 return;
893
894 if (version & 1)
895 ++version; /* first time write, random junk */
896
897 ++version;
18068523 898
18068523
GOC		 899 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
900
50d0a0f9
GH		 901 /*
902 * The guest calculates current wall clock time by adding
34c238a1 903 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 904 * wall clock specified here. guest system time equals host
905 * system time for us, thus we must fill in host boot time here.
906 */
923de3cf 907 getboottime(&boot);
50d0a0f9
GH		 908
909 wc.sec = boot.tv_sec;
910 wc.nsec = boot.tv_nsec;
911 wc.version = version;
18068523
GOC		 912
913 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
914
915 version++;
916 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 917}
918
50d0a0f9
GH		 919static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
920{
921 uint32_t quotient, remainder;
922
923 /* Don't try to replace with do_div(), this one calculates
924 * "(dividend << 32) / divisor" */
925 __asm__ ( "divl %4"
926 : "=a" (quotient), "=d" (remainder)
927 : "0" (0), "1" (dividend), "r" (divisor) );
928 return quotient;
929}
930
5f4e3f88
ZA		 931static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
932 s8 *pshift, u32 *pmultiplier)
50d0a0f9 933{
5f4e3f88 934 uint64_t scaled64;
50d0a0f9
GH		 935 int32_t shift = 0;
936 uint64_t tps64;
937 uint32_t tps32;
938
5f4e3f88
ZA		 939 tps64 = base_khz * 1000LL;
940 scaled64 = scaled_khz * 1000LL;
50933623 941 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 942 tps64 >>= 1;
943 shift--;
944 }
945
946 tps32 = (uint32_t)tps64;
50933623
JK		 947 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
948 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 949 scaled64 >>= 1;
950 else
951 tps32 <<= 1;
50d0a0f9
GH		 952 shift++;
953 }
954
5f4e3f88
ZA		 955 *pshift = shift;
956 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 957
5f4e3f88
ZA		 958 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
959 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 960}
961
759379dd
ZA		 962static inline u64 get_kernel_ns(void)
963{
964 struct timespec ts;
965
966 WARN_ON(preemptible());
967 ktime_get_ts(&ts);
968 monotonic_to_bootbased(&ts);
969 return timespec_to_ns(&ts);
50d0a0f9
GH		 970}
971
c8076604 972static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 973unsigned long max_tsc_khz;
c8076604 974
cc578287 975static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 976{
cc578287
ZA		 977 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
978 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 979}
980
cc578287 981static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 982{
cc578287
ZA		 983 u64 v = (u64)khz * (1000000 + ppm);
984 do_div(v, 1000000);
985 return v;
1e993611
JR		 986}
987
cc578287 988static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 989{
cc578287
ZA		 990 u32 thresh_lo, thresh_hi;
991 int use_scaling = 0;
217fc9cf 992
c285545f
ZA		 993 /* Compute a scale to convert nanoseconds in TSC cycles */
994 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 995 &vcpu->arch.virtual_tsc_shift,
996 &vcpu->arch.virtual_tsc_mult);
997 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
998
999 /*
1000 * Compute the variation in TSC rate which is acceptable
1001 * within the range of tolerance and decide if the
1002 * rate being applied is within that bounds of the hardware
1003 * rate. If so, no scaling or compensation need be done.
1004 */
1005 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1006 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1007 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1008 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1009 use_scaling = 1;
1010 }
1011 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1012}
1013
1014static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1015{
e26101b1 1016 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1017 vcpu->arch.virtual_tsc_mult,
1018 vcpu->arch.virtual_tsc_shift);
e26101b1 1019 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1020 return tsc;
1021}
1022
99e3e30a
ZA		 1023void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
1024{
1025 struct kvm *kvm = vcpu->kvm;
f38e098f 1026 u64 offset, ns, elapsed;
99e3e30a 1027 unsigned long flags;
5d3cb0f6 1028 s64 nsdiff;
99e3e30a 1029
038f8c11 1030 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1031 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1032 ns = get_kernel_ns();
f38e098f 1033 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6
ZA		 1034
1035 /* n.b - signed multiplication and division required */
1036 nsdiff = data - kvm->arch.last_tsc_write;
1037#ifdef CONFIG_X86_64
1038 nsdiff = (nsdiff * 1000) / vcpu->arch.virtual_tsc_khz;
1039#else
1040 /* do_div() only does unsigned */
1041 asm("idivl %2; xor %%edx, %%edx"
1042 : "=A"(nsdiff)
1043 : "A"(nsdiff * 1000), "rm"(vcpu->arch.virtual_tsc_khz));
1044#endif
1045 nsdiff -= elapsed;
1046 if (nsdiff < 0)
1047 nsdiff = -nsdiff;
f38e098f
ZA		 1048
1049 /*
5d3cb0f6
ZA		 1050 * Special case: TSC write with a small delta (1 second) of virtual
1051 * cycle time against real time is interpreted as an attempt to
1052 * synchronize the CPU.
1053 *
1054 * For a reliable TSC, we can match TSC offsets, and for an unstable
1055 * TSC, we add elapsed time in this computation. We could let the
1056 * compensation code attempt to catch up if we fall behind, but
1057 * it's better to try to match offsets from the beginning.
1058 */
1059 if (nsdiff < NSEC_PER_SEC &&
1060 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1061 if (!check_tsc_unstable()) {
e26101b1 1062 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1063 pr_debug("kvm: matched tsc offset for %llu\n", data);
1064 } else {
857e4099 1065 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1066 data += delta;
1067 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1068 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1069 }
e26101b1
ZA		 1070 } else {
1071 /*
1072 * We split periods of matched TSC writes into generations.
1073 * For each generation, we track the original measured
1074 * nanosecond time, offset, and write, so if TSCs are in
1075 * sync, we can match exact offset, and if not, we can match
1076 * exact software computaion in compute_guest_tsc()
1077 *
1078 * These values are tracked in kvm->arch.cur_xxx variables.
1079 */
1080 kvm->arch.cur_tsc_generation++;
1081 kvm->arch.cur_tsc_nsec = ns;
1082 kvm->arch.cur_tsc_write = data;
1083 kvm->arch.cur_tsc_offset = offset;
1084 pr_debug("kvm: new tsc generation %u, clock %llu\n",
1085 kvm->arch.cur_tsc_generation, data);
f38e098f 1086 }
e26101b1
ZA		 1087
1088 /*
1089 * We also track th most recent recorded KHZ, write and time to
1090 * allow the matching interval to be extended at each write.
1091 */
f38e098f
ZA		 1092 kvm->arch.last_tsc_nsec = ns;
1093 kvm->arch.last_tsc_write = data;
5d3cb0f6 1094 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a
ZA		 1095
1096 /* Reset of TSC must disable overshoot protection below */
1097 vcpu->arch.hv_clock.tsc_timestamp = 0;
b183aa58 1098 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1099
1100 /* Keep track of which generation this VCPU has synchronized to */
1101 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1102 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1103 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1104
1105 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1106 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
99e3e30a 1107}
e26101b1 1108
99e3e30a
ZA		 1109EXPORT_SYMBOL_GPL(kvm_write_tsc);
1110
34c238a1 1111static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1112{
18068523
GOC		 1113 unsigned long flags;
1114 struct kvm_vcpu_arch *vcpu = &v->arch;
1115 void *shared_kaddr;
463656c0 1116 unsigned long this_tsc_khz;
1d5f066e
ZA		 1117 s64 kernel_ns, max_kernel_ns;
1118 u64 tsc_timestamp;
18068523 1119
18068523
GOC		 1120 /* Keep irq disabled to prevent changes to the clock */
1121 local_irq_save(flags);
d5c1785d 1122 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v);
759379dd 1123 kernel_ns = get_kernel_ns();
cc578287 1124 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
8cfdc000 1125 if (unlikely(this_tsc_khz == 0)) {
c285545f 1126 local_irq_restore(flags);
34c238a1 1127 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
8cfdc000
ZA		 1128 return 1;
1129 }
18068523 1130
c285545f
ZA		 1131 /*
1132 * We may have to catch up the TSC to match elapsed wall clock
1133 * time for two reasons, even if kvmclock is used.
1134 * 1) CPU could have been running below the maximum TSC rate
1135 * 2) Broken TSC compensation resets the base at each VCPU
1136 * entry to avoid unknown leaps of TSC even when running
1137 * again on the same CPU. This may cause apparent elapsed
1138 * time to disappear, and the guest to stand still or run
1139 * very slowly.
1140 */
1141 if (vcpu->tsc_catchup) {
1142 u64 tsc = compute_guest_tsc(v, kernel_ns);
1143 if (tsc > tsc_timestamp) {
f1e2b260 1144 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1145 tsc_timestamp = tsc;
1146 }
50d0a0f9
GH		 1147 }
1148
18068523
GOC		 1149 local_irq_restore(flags);
1150
c285545f
ZA		 1151 if (!vcpu->time_page)
1152 return 0;
18068523 1153
1d5f066e
ZA		 1154 /*
1155 * Time as measured by the TSC may go backwards when resetting the base
1156 * tsc_timestamp. The reason for this is that the TSC resolution is
1157 * higher than the resolution of the other clock scales. Thus, many
1158 * possible measurments of the TSC correspond to one measurement of any
1159 * other clock, and so a spread of values is possible. This is not a
1160 * problem for the computation of the nanosecond clock; with TSC rates
1161 * around 1GHZ, there can only be a few cycles which correspond to one
1162 * nanosecond value, and any path through this code will inevitably
1163 * take longer than that. However, with the kernel_ns value itself,
1164 * the precision may be much lower, down to HZ granularity. If the
1165 * first sampling of TSC against kernel_ns ends in the low part of the
1166 * range, and the second in the high end of the range, we can get:
1167 *
1168 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1169 *
1170 * As the sampling errors potentially range in the thousands of cycles,
1171 * it is possible such a time value has already been observed by the
1172 * guest. To protect against this, we must compute the system time as
1173 * observed by the guest and ensure the new system time is greater.
1174 */
1175 max_kernel_ns = 0;
b183aa58 1176 if (vcpu->hv_clock.tsc_timestamp) {
1d5f066e
ZA		 1177 max_kernel_ns = vcpu->last_guest_tsc -
1178 vcpu->hv_clock.tsc_timestamp;
1179 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1180 vcpu->hv_clock.tsc_to_system_mul,
1181 vcpu->hv_clock.tsc_shift);
1182 max_kernel_ns += vcpu->last_kernel_ns;
1183 }
afbcf7ab 1184
e48672fa 1185 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1186 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1187 &vcpu->hv_clock.tsc_shift,
1188 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1189 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1190 }
1191
1d5f066e
ZA		 1192 if (max_kernel_ns > kernel_ns)
1193 kernel_ns = max_kernel_ns;
1194
8cfdc000 1195 /* With all the info we got, fill in the values */
1d5f066e 1196 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1197 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1d5f066e 1198 vcpu->last_kernel_ns = kernel_ns;
28e4639a 1199 vcpu->last_guest_tsc = tsc_timestamp;
371bcf64
GC		 1200 vcpu->hv_clock.flags = 0;
1201
18068523
GOC		 1202 /*
1203 * The interface expects us to write an even number signaling that the
1204 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1205 * state, we just increase by 2 at the end.
18068523 1206 */
50d0a0f9 1207 vcpu->hv_clock.version += 2;
18068523
GOC		 1208
1209 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
1210
1211 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 1212 sizeof(vcpu->hv_clock));
18068523
GOC		 1213
1214 kunmap_atomic(shared_kaddr, KM_USER0);
1215
1216 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
8cfdc000 1217 return 0;
c8076604
GH		 1218}
1219
9ba075a6
AK		 1220static bool msr_mtrr_valid(unsigned msr)
1221{
1222 switch (msr) {
1223 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1224 case MSR_MTRRfix64K_00000:
1225 case MSR_MTRRfix16K_80000:
1226 case MSR_MTRRfix16K_A0000:
1227 case MSR_MTRRfix4K_C0000:
1228 case MSR_MTRRfix4K_C8000:
1229 case MSR_MTRRfix4K_D0000:
1230 case MSR_MTRRfix4K_D8000:
1231 case MSR_MTRRfix4K_E0000:
1232 case MSR_MTRRfix4K_E8000:
1233 case MSR_MTRRfix4K_F0000:
1234 case MSR_MTRRfix4K_F8000:
1235 case MSR_MTRRdefType:
1236 case MSR_IA32_CR_PAT:
1237 return true;
1238 case 0x2f8:
1239 return true;
1240 }
1241 return false;
1242}
1243
d6289b93
MT		 1244static bool valid_pat_type(unsigned t)
1245{
1246 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1247}
1248
1249static bool valid_mtrr_type(unsigned t)
1250{
1251 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1252}
1253
1254static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1255{
1256 int i;
1257
1258 if (!msr_mtrr_valid(msr))
1259 return false;
1260
1261 if (msr == MSR_IA32_CR_PAT) {
1262 for (i = 0; i < 8; i++)
1263 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1264 return false;
1265 return true;
1266 } else if (msr == MSR_MTRRdefType) {
1267 if (data & ~0xcff)
1268 return false;
1269 return valid_mtrr_type(data & 0xff);
1270 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1271 for (i = 0; i < 8 ; i++)
1272 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1273 return false;
1274 return true;
1275 }
1276
1277 /* variable MTRRs */
1278 return valid_mtrr_type(data & 0xff);
1279}
1280
9ba075a6
AK		 1281static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1282{
0bed3b56
SY		 1283 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1284
d6289b93 1285 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1286 return 1;
1287
0bed3b56
SY		 1288 if (msr == MSR_MTRRdefType) {
1289 vcpu->arch.mtrr_state.def_type = data;
1290 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1291 } else if (msr == MSR_MTRRfix64K_00000)
1292 p[0] = data;
1293 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1294 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1295 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1296 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1297 else if (msr == MSR_IA32_CR_PAT)
1298 vcpu->arch.pat = data;
1299 else { /* Variable MTRRs */
1300 int idx, is_mtrr_mask;
1301 u64 *pt;
1302
1303 idx = (msr - 0x200) / 2;
1304 is_mtrr_mask = msr - 0x200 - 2 * idx;
1305 if (!is_mtrr_mask)
1306 pt =
1307 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1308 else
1309 pt =
1310 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1311 *pt = data;
1312 }
1313
1314 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1315 return 0;
1316}
15c4a640 1317
890ca9ae 1318static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1319{
890ca9ae
HY		 1320 u64 mcg_cap = vcpu->arch.mcg_cap;
1321 unsigned bank_num = mcg_cap & 0xff;
1322
15c4a640 1323 switch (msr) {
15c4a640 1324 case MSR_IA32_MCG_STATUS:
890ca9ae 1325 vcpu->arch.mcg_status = data;
15c4a640 1326 break;
c7ac679c 1327 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1328 if (!(mcg_cap & MCG_CTL_P))
1329 return 1;
1330 if (data != 0 && data != ~(u64)0)
1331 return -1;
1332 vcpu->arch.mcg_ctl = data;
1333 break;
1334 default:
1335 if (msr >= MSR_IA32_MC0_CTL &&
1336 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1337 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1338 /* only 0 or all 1s can be written to IA32_MCi_CTL
1339 * some Linux kernels though clear bit 10 in bank 4 to
1340 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1341 * this to avoid an uncatched #GP in the guest
1342 */
890ca9ae 1343 if ((offset & 0x3) == 0 &&
114be429 1344 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1345 return -1;
1346 vcpu->arch.mce_banks[offset] = data;
1347 break;
1348 }
1349 return 1;
1350 }
1351 return 0;
1352}
1353
ffde22ac
ES		 1354static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1355{
1356 struct kvm *kvm = vcpu->kvm;
1357 int lm = is_long_mode(vcpu);
1358 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1359 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1360 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1361 : kvm->arch.xen_hvm_config.blob_size_32;
1362 u32 page_num = data & ~PAGE_MASK;
1363 u64 page_addr = data & PAGE_MASK;
1364 u8 *page;
1365 int r;
1366
1367 r = -E2BIG;
1368 if (page_num >= blob_size)
1369 goto out;
1370 r = -ENOMEM;
ff5c2c03
SL		 1371 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1372 if (IS_ERR(page)) {
1373 r = PTR_ERR(page);
ffde22ac 1374 goto out;
ff5c2c03 1375 }
ffde22ac
ES		 1376 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1377 goto out_free;
1378 r = 0;
1379out_free:
1380 kfree(page);
1381out:
1382 return r;
1383}
1384
55cd8e5a
GN		 1385static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1386{
1387 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1388}
1389
1390static bool kvm_hv_msr_partition_wide(u32 msr)
1391{
1392 bool r = false;
1393 switch (msr) {
1394 case HV_X64_MSR_GUEST_OS_ID:
1395 case HV_X64_MSR_HYPERCALL:
1396 r = true;
1397 break;
1398 }
1399
1400 return r;
1401}
1402
1403static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1404{
1405 struct kvm *kvm = vcpu->kvm;
1406
1407 switch (msr) {
1408 case HV_X64_MSR_GUEST_OS_ID:
1409 kvm->arch.hv_guest_os_id = data;
1410 /* setting guest os id to zero disables hypercall page */
1411 if (!kvm->arch.hv_guest_os_id)
1412 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1413 break;
1414 case HV_X64_MSR_HYPERCALL: {
1415 u64 gfn;
1416 unsigned long addr;
1417 u8 instructions[4];
1418
1419 /* if guest os id is not set hypercall should remain disabled */
1420 if (!kvm->arch.hv_guest_os_id)
1421 break;
1422 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1423 kvm->arch.hv_hypercall = data;
1424 break;
1425 }
1426 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1427 addr = gfn_to_hva(kvm, gfn);
1428 if (kvm_is_error_hva(addr))
1429 return 1;
1430 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1431 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1432 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1433 return 1;
1434 kvm->arch.hv_hypercall = data;
1435 break;
1436 }
1437 default:
1438 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1439 "data 0x%llx\n", msr, data);
1440 return 1;
1441 }
1442 return 0;
1443}
1444
1445static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1446{
10388a07
GN		 1447 switch (msr) {
1448 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1449 unsigned long addr;
55cd8e5a 1450
10388a07
GN		 1451 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1452 vcpu->arch.hv_vapic = data;
1453 break;
1454 }
1455 addr = gfn_to_hva(vcpu->kvm, data >>
1456 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1457 if (kvm_is_error_hva(addr))
1458 return 1;
8b0cedff 1459 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 1460 return 1;
1461 vcpu->arch.hv_vapic = data;
1462 break;
1463 }
1464 case HV_X64_MSR_EOI:
1465 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1466 case HV_X64_MSR_ICR:
1467 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1468 case HV_X64_MSR_TPR:
1469 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1470 default:
1471 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1472 "data 0x%llx\n", msr, data);
1473 return 1;
1474 }
1475
1476 return 0;
55cd8e5a
GN		 1477}
1478
344d9588
GN		 1479static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1480{
1481 gpa_t gpa = data & ~0x3f;
1482
6adba527
GN		 1483 /* Bits 2:5 are resrved, Should be zero */
1484 if (data & 0x3c)
344d9588
GN		 1485 return 1;
1486
1487 vcpu->arch.apf.msr_val = data;
1488
1489 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1490 kvm_clear_async_pf_completion_queue(vcpu);
1491 kvm_async_pf_hash_reset(vcpu);
1492 return 0;
1493 }
1494
1495 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa))
1496 return 1;
1497
6adba527 1498 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1499 kvm_async_pf_wakeup_all(vcpu);
1500 return 0;
1501}
1502
12f9a48f
GC		 1503static void kvmclock_reset(struct kvm_vcpu *vcpu)
1504{
1505 if (vcpu->arch.time_page) {
1506 kvm_release_page_dirty(vcpu->arch.time_page);
1507 vcpu->arch.time_page = NULL;
1508 }
1509}
1510
c9aaa895
GC		 1511static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1512{
1513 u64 delta;
1514
1515 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1516 return;
1517
1518 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1519 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1520 vcpu->arch.st.accum_steal = delta;
1521}
1522
1523static void record_steal_time(struct kvm_vcpu *vcpu)
1524{
1525 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1526 return;
1527
1528 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1529 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1530 return;
1531
1532 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1533 vcpu->arch.st.steal.version += 2;
1534 vcpu->arch.st.accum_steal = 0;
1535
1536 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1537 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1538}
1539
15c4a640
CO		 1540int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1541{
5753785f
GN		 1542 bool pr = false;
1543
15c4a640 1544 switch (msr) {
15c4a640 1545 case MSR_EFER:
b69e8cae 1546 return set_efer(vcpu, data);
8f1589d9
AP		 1547 case MSR_K7_HWCR:
1548 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1549 data &= ~(u64)0x100; /* ignore ignne emulation enable */
8f1589d9
AP		 1550 if (data != 0) {
1551 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1552 data);
1553 return 1;
1554 }
15c4a640 1555 break;
f7c6d140
AP		 1556 case MSR_FAM10H_MMIO_CONF_BASE:
1557 if (data != 0) {
1558 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1559 "0x%llx\n", data);
1560 return 1;
1561 }
15c4a640 1562 break;
c323c0e5 1563 case MSR_AMD64_NB_CFG:
c7ac679c 1564 break;
b5e2fec0
AG		 1565 case MSR_IA32_DEBUGCTLMSR:
1566 if (!data) {
1567 /* We support the non-activated case already */
1568 break;
1569 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1570 /* Values other than LBR and BTF are vendor-specific,
1571 thus reserved and should throw a #GP */
1572 return 1;
1573 }
1574 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1575 __func__, data);
1576 break;
15c4a640
CO		 1577 case MSR_IA32_UCODE_REV:
1578 case MSR_IA32_UCODE_WRITE:
61a6bd67 1579 case MSR_VM_HSAVE_PA:
6098ca93 1580 case MSR_AMD64_PATCH_LOADER:
15c4a640 1581 break;
9ba075a6
AK		 1582 case 0x200 ... 0x2ff:
1583 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1584 case MSR_IA32_APICBASE:
1585 kvm_set_apic_base(vcpu, data);
1586 break;
0105d1a5
GN		 1587 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1588 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 1589 case MSR_IA32_TSCDEADLINE:
1590 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1591 break;
15c4a640 1592 case MSR_IA32_MISC_ENABLE:
ad312c7c 1593 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1594 break;
11c6bffa 1595 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1596 case MSR_KVM_WALL_CLOCK:
1597 vcpu->kvm->arch.wall_clock = data;
1598 kvm_write_wall_clock(vcpu->kvm, data);
1599 break;
11c6bffa 1600 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 1601 case MSR_KVM_SYSTEM_TIME: {
12f9a48f 1602 kvmclock_reset(vcpu);
18068523
GOC		 1603
1604 vcpu->arch.time = data;
c285545f 1605 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
18068523
GOC		 1606
1607 /* we verify if the enable bit is set... */
1608 if (!(data & 1))
1609 break;
1610
1611 /* ...but clean it before doing the actual write */
1612 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1613
18068523
GOC		 1614 vcpu->arch.time_page =
1615 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1616
1617 if (is_error_page(vcpu->arch.time_page)) {
1618 kvm_release_page_clean(vcpu->arch.time_page);
1619 vcpu->arch.time_page = NULL;
1620 }
18068523
GOC		 1621 break;
1622 }
344d9588
GN		 1623 case MSR_KVM_ASYNC_PF_EN:
1624 if (kvm_pv_enable_async_pf(vcpu, data))
1625 return 1;
1626 break;
c9aaa895
GC		 1627 case MSR_KVM_STEAL_TIME:
1628
1629 if (unlikely(!sched_info_on()))
1630 return 1;
1631
1632 if (data & KVM_STEAL_RESERVED_MASK)
1633 return 1;
1634
1635 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
1636 data & KVM_STEAL_VALID_BITS))
1637 return 1;
1638
1639 vcpu->arch.st.msr_val = data;
1640
1641 if (!(data & KVM_MSR_ENABLED))
1642 break;
1643
1644 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1645
1646 preempt_disable();
1647 accumulate_steal_time(vcpu);
1648 preempt_enable();
1649
1650 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
1651
1652 break;
1653
890ca9ae
HY		 1654 case MSR_IA32_MCG_CTL:
1655 case MSR_IA32_MCG_STATUS:
1656 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1657 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1658
1659 /* Performance counters are not protected by a CPUID bit,
1660 * so we should check all of them in the generic path for the sake of
1661 * cross vendor migration.
1662 * Writing a zero into the event select MSRs disables them,
1663 * which we perfectly emulate ;-). Any other value should be at least
1664 * reported, some guests depend on them.
1665 */
71db6023
AP		 1666 case MSR_K7_EVNTSEL0:
1667 case MSR_K7_EVNTSEL1:
1668 case MSR_K7_EVNTSEL2:
1669 case MSR_K7_EVNTSEL3:
1670 if (data != 0)
1671 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1672 "0x%x data 0x%llx\n", msr, data);
1673 break;
1674 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1675 * so we ignore writes to make it happy.
1676 */
71db6023
AP		 1677 case MSR_K7_PERFCTR0:
1678 case MSR_K7_PERFCTR1:
1679 case MSR_K7_PERFCTR2:
1680 case MSR_K7_PERFCTR3:
1681 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1682 "0x%x data 0x%llx\n", msr, data);
1683 break;
5753785f
GN		 1684 case MSR_P6_PERFCTR0:
1685 case MSR_P6_PERFCTR1:
1686 pr = true;
1687 case MSR_P6_EVNTSEL0:
1688 case MSR_P6_EVNTSEL1:
1689 if (kvm_pmu_msr(vcpu, msr))
1690 return kvm_pmu_set_msr(vcpu, msr, data);
1691
1692 if (pr || data != 0)
1693 pr_unimpl(vcpu, "disabled perfctr wrmsr: "
1694 "0x%x data 0x%llx\n", msr, data);
1695 break;
84e0cefa
JS		 1696 case MSR_K7_CLK_CTL:
1697 /*
1698 * Ignore all writes to this no longer documented MSR.
1699 * Writes are only relevant for old K7 processors,
1700 * all pre-dating SVM, but a recommended workaround from
1701 * AMD for these chips. It is possible to speicify the
1702 * affected processor models on the command line, hence
1703 * the need to ignore the workaround.
1704 */
1705 break;
55cd8e5a
GN		 1706 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1707 if (kvm_hv_msr_partition_wide(msr)) {
1708 int r;
1709 mutex_lock(&vcpu->kvm->lock);
1710 r = set_msr_hyperv_pw(vcpu, msr, data);
1711 mutex_unlock(&vcpu->kvm->lock);
1712 return r;
1713 } else
1714 return set_msr_hyperv(vcpu, msr, data);
1715 break;
91c9c3ed 1716 case MSR_IA32_BBL_CR_CTL3:
1717 /* Drop writes to this legacy MSR -- see rdmsr
1718 * counterpart for further detail.
1719 */
1720 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
1721 break;
2b036c6b
BO		 1722 case MSR_AMD64_OSVW_ID_LENGTH:
1723 if (!guest_cpuid_has_osvw(vcpu))
1724 return 1;
1725 vcpu->arch.osvw.length = data;
1726 break;
1727 case MSR_AMD64_OSVW_STATUS:
1728 if (!guest_cpuid_has_osvw(vcpu))
1729 return 1;
1730 vcpu->arch.osvw.status = data;
1731 break;
15c4a640 1732 default:
ffde22ac
ES		 1733 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1734 return xen_hvm_config(vcpu, data);
f5132b01
GN		 1735 if (kvm_pmu_msr(vcpu, msr))
1736 return kvm_pmu_set_msr(vcpu, msr, data);
ed85c068
AP		 1737 if (!ignore_msrs) {
1738 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1739 msr, data);
1740 return 1;
1741 } else {
1742 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1743 msr, data);
1744 break;
1745 }
15c4a640
CO		 1746 }
1747 return 0;
1748}
1749EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1750
1751
1752/*
1753 * Reads an msr value (of 'msr_index') into 'pdata'.
1754 * Returns 0 on success, non-0 otherwise.
1755 * Assumes vcpu_load() was already called.
1756 */
1757int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1758{
1759 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1760}
1761
9ba075a6
AK		 1762static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1763{
0bed3b56
SY		 1764 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1765
9ba075a6
AK		 1766 if (!msr_mtrr_valid(msr))
1767 return 1;
1768
0bed3b56
SY		 1769 if (msr == MSR_MTRRdefType)
1770 *pdata = vcpu->arch.mtrr_state.def_type +
1771 (vcpu->arch.mtrr_state.enabled << 10);
1772 else if (msr == MSR_MTRRfix64K_00000)
1773 *pdata = p[0];
1774 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1775 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1776 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1777 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1778 else if (msr == MSR_IA32_CR_PAT)
1779 *pdata = vcpu->arch.pat;
1780 else { /* Variable MTRRs */
1781 int idx, is_mtrr_mask;
1782 u64 *pt;
1783
1784 idx = (msr - 0x200) / 2;
1785 is_mtrr_mask = msr - 0x200 - 2 * idx;
1786 if (!is_mtrr_mask)
1787 pt =
1788 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1789 else
1790 pt =
1791 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1792 *pdata = *pt;
1793 }
1794
9ba075a6
AK		 1795 return 0;
1796}
1797
890ca9ae 1798static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1799{
1800 u64 data;
890ca9ae
HY		 1801 u64 mcg_cap = vcpu->arch.mcg_cap;
1802 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1803
1804 switch (msr) {
15c4a640
CO		 1805 case MSR_IA32_P5_MC_ADDR:
1806 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1807 data = 0;
1808 break;
15c4a640 1809 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1810 data = vcpu->arch.mcg_cap;
1811 break;
c7ac679c 1812 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1813 if (!(mcg_cap & MCG_CTL_P))
1814 return 1;
1815 data = vcpu->arch.mcg_ctl;
1816 break;
1817 case MSR_IA32_MCG_STATUS:
1818 data = vcpu->arch.mcg_status;
1819 break;
1820 default:
1821 if (msr >= MSR_IA32_MC0_CTL &&
1822 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1823 u32 offset = msr - MSR_IA32_MC0_CTL;
1824 data = vcpu->arch.mce_banks[offset];
1825 break;
1826 }
1827 return 1;
1828 }
1829 *pdata = data;
1830 return 0;
1831}
1832
55cd8e5a
GN		 1833static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1834{
1835 u64 data = 0;
1836 struct kvm *kvm = vcpu->kvm;
1837
1838 switch (msr) {
1839 case HV_X64_MSR_GUEST_OS_ID:
1840 data = kvm->arch.hv_guest_os_id;
1841 break;
1842 case HV_X64_MSR_HYPERCALL:
1843 data = kvm->arch.hv_hypercall;
1844 break;
1845 default:
1846 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1847 return 1;
1848 }
1849
1850 *pdata = data;
1851 return 0;
1852}
1853
1854static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1855{
1856 u64 data = 0;
1857
1858 switch (msr) {
1859 case HV_X64_MSR_VP_INDEX: {
1860 int r;
1861 struct kvm_vcpu *v;
1862 kvm_for_each_vcpu(r, v, vcpu->kvm)
1863 if (v == vcpu)
1864 data = r;
1865 break;
1866 }
10388a07
GN		 1867 case HV_X64_MSR_EOI:
1868 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1869 case HV_X64_MSR_ICR:
1870 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1871 case HV_X64_MSR_TPR:
1872 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 1873 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 1874 data = vcpu->arch.hv_vapic;
1875 break;
55cd8e5a
GN		 1876 default:
1877 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1878 return 1;
1879 }
1880 *pdata = data;
1881 return 0;
1882}
1883
890ca9ae
HY		 1884int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1885{
1886 u64 data;
1887
1888 switch (msr) {
890ca9ae 1889 case MSR_IA32_PLATFORM_ID:
15c4a640 1890 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1891 case MSR_IA32_DEBUGCTLMSR:
1892 case MSR_IA32_LASTBRANCHFROMIP:
1893 case MSR_IA32_LASTBRANCHTOIP:
1894 case MSR_IA32_LASTINTFROMIP:
1895 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1896 case MSR_K8_SYSCFG:
1897 case MSR_K7_HWCR:
61a6bd67 1898 case MSR_VM_HSAVE_PA:
9e699624 1899 case MSR_K7_EVNTSEL0:
1f3ee616 1900 case MSR_K7_PERFCTR0:
1fdbd48c 1901 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1902 case MSR_AMD64_NB_CFG:
f7c6d140 1903 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1904 data = 0;
1905 break;
5753785f
GN		 1906 case MSR_P6_PERFCTR0:
1907 case MSR_P6_PERFCTR1:
1908 case MSR_P6_EVNTSEL0:
1909 case MSR_P6_EVNTSEL1:
1910 if (kvm_pmu_msr(vcpu, msr))
1911 return kvm_pmu_get_msr(vcpu, msr, pdata);
1912 data = 0;
1913 break;
742bc670
MT		 1914 case MSR_IA32_UCODE_REV:
1915 data = 0x100000000ULL;
1916 break;
9ba075a6
AK		 1917 case MSR_MTRRcap:
1918 data = 0x500 | KVM_NR_VAR_MTRR;
1919 break;
1920 case 0x200 ... 0x2ff:
1921 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1922 case 0xcd: /* fsb frequency */
1923 data = 3;
1924 break;
7b914098
JS		 1925 /*
1926 * MSR_EBC_FREQUENCY_ID
1927 * Conservative value valid for even the basic CPU models.
1928 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
1929 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
1930 * and 266MHz for model 3, or 4. Set Core Clock
1931 * Frequency to System Bus Frequency Ratio to 1 (bits
1932 * 31:24) even though these are only valid for CPU
1933 * models > 2, however guests may end up dividing or
1934 * multiplying by zero otherwise.
1935 */
1936 case MSR_EBC_FREQUENCY_ID:
1937 data = 1 << 24;
1938 break;
15c4a640
CO		 1939 case MSR_IA32_APICBASE:
1940 data = kvm_get_apic_base(vcpu);
1941 break;
0105d1a5
GN		 1942 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1943 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1944 break;
a3e06bbe
LJ		 1945 case MSR_IA32_TSCDEADLINE:
1946 data = kvm_get_lapic_tscdeadline_msr(vcpu);
1947 break;
15c4a640 1948 case MSR_IA32_MISC_ENABLE:
ad312c7c 1949 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1950 break;
847f0ad8
AG		 1951 case MSR_IA32_PERF_STATUS:
1952 /* TSC increment by tick */
1953 data = 1000ULL;
1954 /* CPU multiplier */
1955 data |= (((uint64_t)4ULL) << 40);
1956 break;
15c4a640 1957 case MSR_EFER:
f6801dff 1958 data = vcpu->arch.efer;
15c4a640 1959 break;
18068523 1960 case MSR_KVM_WALL_CLOCK:
11c6bffa 1961 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1962 data = vcpu->kvm->arch.wall_clock;
1963 break;
1964 case MSR_KVM_SYSTEM_TIME:
11c6bffa 1965 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1966 data = vcpu->arch.time;
1967 break;
344d9588
GN		 1968 case MSR_KVM_ASYNC_PF_EN:
1969 data = vcpu->arch.apf.msr_val;
1970 break;
c9aaa895
GC		 1971 case MSR_KVM_STEAL_TIME:
1972 data = vcpu->arch.st.msr_val;
1973 break;
890ca9ae
HY		 1974 case MSR_IA32_P5_MC_ADDR:
1975 case MSR_IA32_P5_MC_TYPE:
1976 case MSR_IA32_MCG_CAP:
1977 case MSR_IA32_MCG_CTL:
1978 case MSR_IA32_MCG_STATUS:
1979 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1980 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 1981 case MSR_K7_CLK_CTL:
1982 /*
1983 * Provide expected ramp-up count for K7. All other
1984 * are set to zero, indicating minimum divisors for
1985 * every field.
1986 *
1987 * This prevents guest kernels on AMD host with CPU
1988 * type 6, model 8 and higher from exploding due to
1989 * the rdmsr failing.
1990 */
1991 data = 0x20000000;
1992 break;
55cd8e5a
GN		 1993 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1994 if (kvm_hv_msr_partition_wide(msr)) {
1995 int r;
1996 mutex_lock(&vcpu->kvm->lock);
1997 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1998 mutex_unlock(&vcpu->kvm->lock);
1999 return r;
2000 } else
2001 return get_msr_hyperv(vcpu, msr, pdata);
2002 break;
91c9c3ed 2003 case MSR_IA32_BBL_CR_CTL3:
2004 /* This legacy MSR exists but isn't fully documented in current
2005 * silicon. It is however accessed by winxp in very narrow
2006 * scenarios where it sets bit #19, itself documented as
2007 * a "reserved" bit. Best effort attempt to source coherent
2008 * read data here should the balance of the register be
2009 * interpreted by the guest:
2010 *
2011 * L2 cache control register 3: 64GB range, 256KB size,
2012 * enabled, latency 0x1, configured
2013 */
2014 data = 0xbe702111;
2015 break;
2b036c6b
BO		 2016 case MSR_AMD64_OSVW_ID_LENGTH:
2017 if (!guest_cpuid_has_osvw(vcpu))
2018 return 1;
2019 data = vcpu->arch.osvw.length;
2020 break;
2021 case MSR_AMD64_OSVW_STATUS:
2022 if (!guest_cpuid_has_osvw(vcpu))
2023 return 1;
2024 data = vcpu->arch.osvw.status;
2025 break;
15c4a640 2026 default:
f5132b01
GN		 2027 if (kvm_pmu_msr(vcpu, msr))
2028 return kvm_pmu_get_msr(vcpu, msr, pdata);
ed85c068
AP		 2029 if (!ignore_msrs) {
2030 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
2031 return 1;
2032 } else {
2033 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
2034 data = 0;
2035 }
2036 break;
15c4a640
CO		 2037 }
2038 *pdata = data;
2039 return 0;
2040}
2041EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2042
313a3dc7
CO		 2043/*
2044 * Read or write a bunch of msrs. All parameters are kernel addresses.
2045 *
2046 * @return number of msrs set successfully.
2047 */
2048static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2049 struct kvm_msr_entry *entries,
2050 int (*do_msr)(struct kvm_vcpu *vcpu,
2051 unsigned index, u64 *data))
2052{
f656ce01 2053 int i, idx;
313a3dc7 2054
f656ce01 2055 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2056 for (i = 0; i < msrs->nmsrs; ++i)
2057 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2058 break;
f656ce01 2059 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2060
313a3dc7
CO		 2061 return i;
2062}
2063
2064/*
2065 * Read or write a bunch of msrs. Parameters are user addresses.
2066 *
2067 * @return number of msrs set successfully.
2068 */
2069static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2070 int (*do_msr)(struct kvm_vcpu *vcpu,
2071 unsigned index, u64 *data),
2072 int writeback)
2073{
2074 struct kvm_msrs msrs;
2075 struct kvm_msr_entry *entries;
2076 int r, n;
2077 unsigned size;
2078
2079 r = -EFAULT;
2080 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2081 goto out;
2082
2083 r = -E2BIG;
2084 if (msrs.nmsrs >= MAX_IO_MSRS)
2085 goto out;
2086
313a3dc7 2087 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2088 entries = memdup_user(user_msrs->entries, size);
2089 if (IS_ERR(entries)) {
2090 r = PTR_ERR(entries);
313a3dc7 2091 goto out;
ff5c2c03 2092 }
313a3dc7
CO		 2093
2094 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2095 if (r < 0)
2096 goto out_free;
2097
2098 r = -EFAULT;
2099 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2100 goto out_free;
2101
2102 r = n;
2103
2104out_free:
7a73c028 2105 kfree(entries);
313a3dc7
CO		 2106out:
2107 return r;
2108}
2109
018d00d2
ZX		 2110int kvm_dev_ioctl_check_extension(long ext)
2111{
2112 int r;
2113
2114 switch (ext) {
2115 case KVM_CAP_IRQCHIP:
2116 case KVM_CAP_HLT:
2117 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2118 case KVM_CAP_SET_TSS_ADDR:
07716717 2119 case KVM_CAP_EXT_CPUID:
c8076604 2120 case KVM_CAP_CLOCKSOURCE:
7837699f 2121 case KVM_CAP_PIT:
a28e4f5a 2122 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2123 case KVM_CAP_MP_STATE:
ed848624 2124 case KVM_CAP_SYNC_MMU:
a355c85c 2125 case KVM_CAP_USER_NMI:
52d939a0 2126 case KVM_CAP_REINJECT_CONTROL:
4925663a 2127 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 2128 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 2129 case KVM_CAP_IRQFD:
d34e6b17 2130 case KVM_CAP_IOEVENTFD:
c5ff41ce 2131 case KVM_CAP_PIT2:
e9f42757 2132 case KVM_CAP_PIT_STATE2:
b927a3ce 2133 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2134 case KVM_CAP_XEN_HVM:
afbcf7ab 2135 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2136 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2137 case KVM_CAP_HYPERV:
10388a07 2138 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2139 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2140 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2141 case KVM_CAP_DEBUGREGS:
d2be1651 2142 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2143 case KVM_CAP_XSAVE:
344d9588 2144 case KVM_CAP_ASYNC_PF:
92a1f12d 2145 case KVM_CAP_GET_TSC_KHZ:
018d00d2
ZX		 2146 r = 1;
2147 break;
542472b5
LV		 2148 case KVM_CAP_COALESCED_MMIO:
2149 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2150 break;
774ead3a
AK		 2151 case KVM_CAP_VAPIC:
2152 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2153 break;
f725230a 2154 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2155 r = KVM_SOFT_MAX_VCPUS;
2156 break;
2157 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2158 r = KVM_MAX_VCPUS;
2159 break;
a988b910
AK		 2160 case KVM_CAP_NR_MEMSLOTS:
2161 r = KVM_MEMORY_SLOTS;
2162 break;
a68a6a72
MT		 2163 case KVM_CAP_PV_MMU: /* obsolete */
2164 r = 0;
2f333bcb 2165 break;
62c476c7 2166 case KVM_CAP_IOMMU:
a1b60c1c 2167 r = iommu_present(&pci_bus_type);
62c476c7 2168 break;
890ca9ae
HY		 2169 case KVM_CAP_MCE:
2170 r = KVM_MAX_MCE_BANKS;
2171 break;
2d5b5a66
SY		 2172 case KVM_CAP_XCRS:
2173 r = cpu_has_xsave;
2174 break;
92a1f12d
JR		 2175 case KVM_CAP_TSC_CONTROL:
2176 r = kvm_has_tsc_control;
2177 break;
4d25a066
JK		 2178 case KVM_CAP_TSC_DEADLINE_TIMER:
2179 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2180 break;
018d00d2
ZX		 2181 default:
2182 r = 0;
2183 break;
2184 }
2185 return r;
2186
2187}
2188
043405e1
CO		 2189long kvm_arch_dev_ioctl(struct file *filp,
2190 unsigned int ioctl, unsigned long arg)
2191{
2192 void __user *argp = (void __user *)arg;
2193 long r;
2194
2195 switch (ioctl) {
2196 case KVM_GET_MSR_INDEX_LIST: {
2197 struct kvm_msr_list __user *user_msr_list = argp;
2198 struct kvm_msr_list msr_list;
2199 unsigned n;
2200
2201 r = -EFAULT;
2202 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2203 goto out;
2204 n = msr_list.nmsrs;
2205 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2206 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2207 goto out;
2208 r = -E2BIG;
e125e7b6 2209 if (n < msr_list.nmsrs)
043405e1
CO		 2210 goto out;
2211 r = -EFAULT;
2212 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2213 num_msrs_to_save * sizeof(u32)))
2214 goto out;
e125e7b6 2215 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2216 &emulated_msrs,
2217 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2218 goto out;
2219 r = 0;
2220 break;
2221 }
674eea0f
AK		 2222 case KVM_GET_SUPPORTED_CPUID: {
2223 struct kvm_cpuid2 __user *cpuid_arg = argp;
2224 struct kvm_cpuid2 cpuid;
2225
2226 r = -EFAULT;
2227 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2228 goto out;
2229 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 2230 cpuid_arg->entries);
674eea0f
AK		 2231 if (r)
2232 goto out;
2233
2234 r = -EFAULT;
2235 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2236 goto out;
2237 r = 0;
2238 break;
2239 }
890ca9ae
HY		 2240 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2241 u64 mce_cap;
2242
2243 mce_cap = KVM_MCE_CAP_SUPPORTED;
2244 r = -EFAULT;
2245 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2246 goto out;
2247 r = 0;
2248 break;
2249 }
043405e1
CO		 2250 default:
2251 r = -EINVAL;
2252 }
2253out:
2254 return r;
2255}
2256
f5f48ee1
SY		 2257static void wbinvd_ipi(void *garbage)
2258{
2259 wbinvd();
2260}
2261
2262static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2263{
2264 return vcpu->kvm->arch.iommu_domain &&
2265 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2266}
2267
313a3dc7
CO		 2268void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2269{
f5f48ee1
SY		 2270 /* Address WBINVD may be executed by guest */
2271 if (need_emulate_wbinvd(vcpu)) {
2272 if (kvm_x86_ops->has_wbinvd_exit())
2273 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2274 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2275 smp_call_function_single(vcpu->cpu,
2276 wbinvd_ipi, NULL, 1);
2277 }
2278
313a3dc7 2279 kvm_x86_ops->vcpu_load(vcpu, cpu);
0dd6a6ed
ZA		 2280
2281 /* Apply any externally detected TSC adjustments (due to suspend) */
2282 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2283 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2284 vcpu->arch.tsc_offset_adjustment = 0;
2285 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2286 }
2287
48434c20 2288 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5
ZA		 2289 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2290 native_read_tsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2291 if (tsc_delta < 0)
2292 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2293 if (check_tsc_unstable()) {
b183aa58
ZA		 2294 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2295 vcpu->arch.last_guest_tsc);
2296 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2297 vcpu->arch.tsc_catchup = 1;
c285545f 2298 }
1aa8ceef 2299 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2300 if (vcpu->cpu != cpu)
2301 kvm_migrate_timers(vcpu);
e48672fa 2302 vcpu->cpu = cpu;
6b7d7e76 2303 }
c9aaa895
GC		 2304
2305 accumulate_steal_time(vcpu);
2306 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2307}
2308
2309void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2310{
02daab21 2311 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2312 kvm_put_guest_fpu(vcpu);
6f526ec5 2313 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2314}
2315
313a3dc7
CO		 2316static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2317 struct kvm_lapic_state *s)
2318{
ad312c7c 2319 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2320
2321 return 0;
2322}
2323
2324static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2325 struct kvm_lapic_state *s)
2326{
ad312c7c 2327 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 2328 kvm_apic_post_state_restore(vcpu);
cb142eb7 2329 update_cr8_intercept(vcpu);
313a3dc7
CO		 2330
2331 return 0;
2332}
2333
f77bc6a4
ZX		 2334static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2335 struct kvm_interrupt *irq)
2336{
2337 if (irq->irq < 0 || irq->irq >= 256)
2338 return -EINVAL;
2339 if (irqchip_in_kernel(vcpu->kvm))
2340 return -ENXIO;
f77bc6a4 2341
66fd3f7f 2342 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2343 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2344
f77bc6a4
ZX		 2345 return 0;
2346}
2347
c4abb7c9
JK		 2348static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2349{
c4abb7c9 2350 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2351
2352 return 0;
2353}
2354
b209749f
AK		 2355static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2356 struct kvm_tpr_access_ctl *tac)
2357{
2358 if (tac->flags)
2359 return -EINVAL;
2360 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2361 return 0;
2362}
2363
890ca9ae
HY		 2364static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2365 u64 mcg_cap)
2366{
2367 int r;
2368 unsigned bank_num = mcg_cap & 0xff, bank;
2369
2370 r = -EINVAL;
a9e38c3e 2371 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2372 goto out;
2373 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2374 goto out;
2375 r = 0;
2376 vcpu->arch.mcg_cap = mcg_cap;
2377 /* Init IA32_MCG_CTL to all 1s */
2378 if (mcg_cap & MCG_CTL_P)
2379 vcpu->arch.mcg_ctl = ~(u64)0;
2380 /* Init IA32_MCi_CTL to all 1s */
2381 for (bank = 0; bank < bank_num; bank++)
2382 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2383out:
2384 return r;
2385}
2386
2387static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2388 struct kvm_x86_mce *mce)
2389{
2390 u64 mcg_cap = vcpu->arch.mcg_cap;
2391 unsigned bank_num = mcg_cap & 0xff;
2392 u64 *banks = vcpu->arch.mce_banks;
2393
2394 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2395 return -EINVAL;
2396 /*
2397 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2398 * reporting is disabled
2399 */
2400 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2401 vcpu->arch.mcg_ctl != ~(u64)0)
2402 return 0;
2403 banks += 4 * mce->bank;
2404 /*
2405 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2406 * reporting is disabled for the bank
2407 */
2408 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2409 return 0;
2410 if (mce->status & MCI_STATUS_UC) {
2411 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2412 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2413 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2414 return 0;
2415 }
2416 if (banks[1] & MCI_STATUS_VAL)
2417 mce->status |= MCI_STATUS_OVER;
2418 banks[2] = mce->addr;
2419 banks[3] = mce->misc;
2420 vcpu->arch.mcg_status = mce->mcg_status;
2421 banks[1] = mce->status;
2422 kvm_queue_exception(vcpu, MC_VECTOR);
2423 } else if (!(banks[1] & MCI_STATUS_VAL)
2424 || !(banks[1] & MCI_STATUS_UC)) {
2425 if (banks[1] & MCI_STATUS_VAL)
2426 mce->status |= MCI_STATUS_OVER;
2427 banks[2] = mce->addr;
2428 banks[3] = mce->misc;
2429 banks[1] = mce->status;
2430 } else
2431 banks[1] |= MCI_STATUS_OVER;
2432 return 0;
2433}
2434
3cfc3092
JK		 2435static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2436 struct kvm_vcpu_events *events)
2437{
7460fb4a 2438 process_nmi(vcpu);
03b82a30
JK		 2439 events->exception.injected =
2440 vcpu->arch.exception.pending &&
2441 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2442 events->exception.nr = vcpu->arch.exception.nr;
2443 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2444 events->exception.pad = 0;
3cfc3092
JK		 2445 events->exception.error_code = vcpu->arch.exception.error_code;
2446
03b82a30
JK		 2447 events->interrupt.injected =
2448 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2449 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2450 events->interrupt.soft = 0;
48005f64
JK		 2451 events->interrupt.shadow =
2452 kvm_x86_ops->get_interrupt_shadow(vcpu,
2453 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2454
2455 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2456 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2457 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2458 events->nmi.pad = 0;
3cfc3092
JK		 2459
2460 events->sipi_vector = vcpu->arch.sipi_vector;
2461
dab4b911 2462 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2463 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2464 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 2465 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2466}
2467
2468static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2469 struct kvm_vcpu_events *events)
2470{
dab4b911 2471 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2472 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2473 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2474 return -EINVAL;
2475
7460fb4a 2476 process_nmi(vcpu);
3cfc3092
JK		 2477 vcpu->arch.exception.pending = events->exception.injected;
2478 vcpu->arch.exception.nr = events->exception.nr;
2479 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2480 vcpu->arch.exception.error_code = events->exception.error_code;
2481
2482 vcpu->arch.interrupt.pending = events->interrupt.injected;
2483 vcpu->arch.interrupt.nr = events->interrupt.nr;
2484 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2485 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2486 kvm_x86_ops->set_interrupt_shadow(vcpu,
2487 events->interrupt.shadow);
3cfc3092
JK		 2488
2489 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2490 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2491 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2492 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2493
dab4b911
JK		 2494 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2495 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092 2496
3842d135
AK		 2497 kvm_make_request(KVM_REQ_EVENT, vcpu);
2498
3cfc3092
JK		 2499 return 0;
2500}
2501
a1efbe77
JK		 2502static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2503 struct kvm_debugregs *dbgregs)
2504{
a1efbe77
JK		 2505 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2506 dbgregs->dr6 = vcpu->arch.dr6;
2507 dbgregs->dr7 = vcpu->arch.dr7;
2508 dbgregs->flags = 0;
97e69aa6 2509 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 2510}
2511
2512static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2513 struct kvm_debugregs *dbgregs)
2514{
2515 if (dbgregs->flags)
2516 return -EINVAL;
2517
a1efbe77
JK		 2518 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2519 vcpu->arch.dr6 = dbgregs->dr6;
2520 vcpu->arch.dr7 = dbgregs->dr7;
2521
a1efbe77
JK		 2522 return 0;
2523}
2524
2d5b5a66
SY		 2525static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2526 struct kvm_xsave *guest_xsave)
2527{
2528 if (cpu_has_xsave)
2529 memcpy(guest_xsave->region,
2530 &vcpu->arch.guest_fpu.state->xsave,
f45755b8 2531 xstate_size);
2d5b5a66
SY		 2532 else {
2533 memcpy(guest_xsave->region,
2534 &vcpu->arch.guest_fpu.state->fxsave,
2535 sizeof(struct i387_fxsave_struct));
2536 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2537 XSTATE_FPSSE;
2538 }
2539}
2540
2541static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2542 struct kvm_xsave *guest_xsave)
2543{
2544 u64 xstate_bv =
2545 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2546
2547 if (cpu_has_xsave)
2548 memcpy(&vcpu->arch.guest_fpu.state->xsave,
f45755b8 2549 guest_xsave->region, xstate_size);
2d5b5a66
SY		 2550 else {
2551 if (xstate_bv & ~XSTATE_FPSSE)
2552 return -EINVAL;
2553 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2554 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2555 }
2556 return 0;
2557}
2558
2559static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2560 struct kvm_xcrs *guest_xcrs)
2561{
2562 if (!cpu_has_xsave) {
2563 guest_xcrs->nr_xcrs = 0;
2564 return;
2565 }
2566
2567 guest_xcrs->nr_xcrs = 1;
2568 guest_xcrs->flags = 0;
2569 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2570 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2571}
2572
2573static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2574 struct kvm_xcrs *guest_xcrs)
2575{
2576 int i, r = 0;
2577
2578 if (!cpu_has_xsave)
2579 return -EINVAL;
2580
2581 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2582 return -EINVAL;
2583
2584 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2585 /* Only support XCR0 currently */
2586 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2587 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2588 guest_xcrs->xcrs[0].value);
2589 break;
2590 }
2591 if (r)
2592 r = -EINVAL;
2593 return r;
2594}
2595
313a3dc7
CO		 2596long kvm_arch_vcpu_ioctl(struct file *filp,
2597 unsigned int ioctl, unsigned long arg)
2598{
2599 struct kvm_vcpu *vcpu = filp->private_data;
2600 void __user *argp = (void __user *)arg;
2601 int r;
d1ac91d8
AK		 2602 union {
2603 struct kvm_lapic_state *lapic;
2604 struct kvm_xsave *xsave;
2605 struct kvm_xcrs *xcrs;
2606 void *buffer;
2607 } u;
2608
2609 u.buffer = NULL;
313a3dc7
CO		 2610 switch (ioctl) {
2611 case KVM_GET_LAPIC: {
2204ae3c
MT		 2612 r = -EINVAL;
2613 if (!vcpu->arch.apic)
2614 goto out;
d1ac91d8 2615 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2616
b772ff36 2617 r = -ENOMEM;
d1ac91d8 2618 if (!u.lapic)
b772ff36 2619 goto out;
d1ac91d8 2620 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 2621 if (r)
2622 goto out;
2623 r = -EFAULT;
d1ac91d8 2624 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2625 goto out;
2626 r = 0;
2627 break;
2628 }
2629 case KVM_SET_LAPIC: {
2204ae3c
MT		 2630 r = -EINVAL;
2631 if (!vcpu->arch.apic)
2632 goto out;
ff5c2c03
SL		 2633 u.lapic = memdup_user(argp, sizeof(*u.lapic));
2634 if (IS_ERR(u.lapic)) {
2635 r = PTR_ERR(u.lapic);
313a3dc7 2636 goto out;
ff5c2c03
SL		 2637 }
2638
d1ac91d8 2639 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 2640 if (r)
2641 goto out;
2642 r = 0;
2643 break;
2644 }
f77bc6a4
ZX		 2645 case KVM_INTERRUPT: {
2646 struct kvm_interrupt irq;
2647
2648 r = -EFAULT;
2649 if (copy_from_user(&irq, argp, sizeof irq))
2650 goto out;
2651 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2652 if (r)
2653 goto out;
2654 r = 0;
2655 break;
2656 }
c4abb7c9
JK		 2657 case KVM_NMI: {
2658 r = kvm_vcpu_ioctl_nmi(vcpu);
2659 if (r)
2660 goto out;
2661 r = 0;
2662 break;
2663 }
313a3dc7
CO		 2664 case KVM_SET_CPUID: {
2665 struct kvm_cpuid __user *cpuid_arg = argp;
2666 struct kvm_cpuid cpuid;
2667
2668 r = -EFAULT;
2669 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2670 goto out;
2671 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2672 if (r)
2673 goto out;
2674 break;
2675 }
07716717
DK		 2676 case KVM_SET_CPUID2: {
2677 struct kvm_cpuid2 __user *cpuid_arg = argp;
2678 struct kvm_cpuid2 cpuid;
2679
2680 r = -EFAULT;
2681 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2682 goto out;
2683 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2684 cpuid_arg->entries);
07716717
DK		 2685 if (r)
2686 goto out;
2687 break;
2688 }
2689 case KVM_GET_CPUID2: {
2690 struct kvm_cpuid2 __user *cpuid_arg = argp;
2691 struct kvm_cpuid2 cpuid;
2692
2693 r = -EFAULT;
2694 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2695 goto out;
2696 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2697 cpuid_arg->entries);
07716717
DK		 2698 if (r)
2699 goto out;
2700 r = -EFAULT;
2701 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2702 goto out;
2703 r = 0;
2704 break;
2705 }
313a3dc7
CO		 2706 case KVM_GET_MSRS:
2707 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2708 break;
2709 case KVM_SET_MSRS:
2710 r = msr_io(vcpu, argp, do_set_msr, 0);
2711 break;
b209749f
AK		 2712 case KVM_TPR_ACCESS_REPORTING: {
2713 struct kvm_tpr_access_ctl tac;
2714
2715 r = -EFAULT;
2716 if (copy_from_user(&tac, argp, sizeof tac))
2717 goto out;
2718 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2719 if (r)
2720 goto out;
2721 r = -EFAULT;
2722 if (copy_to_user(argp, &tac, sizeof tac))
2723 goto out;
2724 r = 0;
2725 break;
2726 };
b93463aa
AK		 2727 case KVM_SET_VAPIC_ADDR: {
2728 struct kvm_vapic_addr va;
2729
2730 r = -EINVAL;
2731 if (!irqchip_in_kernel(vcpu->kvm))
2732 goto out;
2733 r = -EFAULT;
2734 if (copy_from_user(&va, argp, sizeof va))
2735 goto out;
2736 r = 0;
2737 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2738 break;
2739 }
890ca9ae
HY		 2740 case KVM_X86_SETUP_MCE: {
2741 u64 mcg_cap;
2742
2743 r = -EFAULT;
2744 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2745 goto out;
2746 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2747 break;
2748 }
2749 case KVM_X86_SET_MCE: {
2750 struct kvm_x86_mce mce;
2751
2752 r = -EFAULT;
2753 if (copy_from_user(&mce, argp, sizeof mce))
2754 goto out;
2755 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2756 break;
2757 }
3cfc3092
JK		 2758 case KVM_GET_VCPU_EVENTS: {
2759 struct kvm_vcpu_events events;
2760
2761 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2762
2763 r = -EFAULT;
2764 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2765 break;
2766 r = 0;
2767 break;
2768 }
2769 case KVM_SET_VCPU_EVENTS: {
2770 struct kvm_vcpu_events events;
2771
2772 r = -EFAULT;
2773 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2774 break;
2775
2776 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2777 break;
2778 }
a1efbe77
JK		 2779 case KVM_GET_DEBUGREGS: {
2780 struct kvm_debugregs dbgregs;
2781
2782 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2783
2784 r = -EFAULT;
2785 if (copy_to_user(argp, &dbgregs,
2786 sizeof(struct kvm_debugregs)))
2787 break;
2788 r = 0;
2789 break;
2790 }
2791 case KVM_SET_DEBUGREGS: {
2792 struct kvm_debugregs dbgregs;
2793
2794 r = -EFAULT;
2795 if (copy_from_user(&dbgregs, argp,
2796 sizeof(struct kvm_debugregs)))
2797 break;
2798
2799 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2800 break;
2801 }
2d5b5a66 2802 case KVM_GET_XSAVE: {
d1ac91d8 2803 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 2804 r = -ENOMEM;
d1ac91d8 2805 if (!u.xsave)
2d5b5a66
SY		 2806 break;
2807
d1ac91d8 2808 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2809
2810 r = -EFAULT;
d1ac91d8 2811 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 2812 break;
2813 r = 0;
2814 break;
2815 }
2816 case KVM_SET_XSAVE: {
ff5c2c03
SL		 2817 u.xsave = memdup_user(argp, sizeof(*u.xsave));
2818 if (IS_ERR(u.xsave)) {
2819 r = PTR_ERR(u.xsave);
2820 goto out;
2821 }
2d5b5a66 2822
d1ac91d8 2823 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 2824 break;
2825 }
2826 case KVM_GET_XCRS: {
d1ac91d8 2827 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 2828 r = -ENOMEM;
d1ac91d8 2829 if (!u.xcrs)
2d5b5a66
SY		 2830 break;
2831
d1ac91d8 2832 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 2833
2834 r = -EFAULT;
d1ac91d8 2835 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 2836 sizeof(struct kvm_xcrs)))
2837 break;
2838 r = 0;
2839 break;
2840 }
2841 case KVM_SET_XCRS: {
ff5c2c03
SL		 2842 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
2843 if (IS_ERR(u.xcrs)) {
2844 r = PTR_ERR(u.xcrs);
2845 goto out;
2846 }
2d5b5a66 2847
d1ac91d8 2848 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 2849 break;
2850 }
92a1f12d
JR		 2851 case KVM_SET_TSC_KHZ: {
2852 u32 user_tsc_khz;
2853
2854 r = -EINVAL;
92a1f12d
JR		 2855 user_tsc_khz = (u32)arg;
2856
2857 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
2858 goto out;
2859
cc578287
ZA		 2860 if (user_tsc_khz == 0)
2861 user_tsc_khz = tsc_khz;
2862
2863 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 2864
2865 r = 0;
2866 goto out;
2867 }
2868 case KVM_GET_TSC_KHZ: {
cc578287 2869 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 2870 goto out;
2871 }
313a3dc7
CO		 2872 default:
2873 r = -EINVAL;
2874 }
2875out:
d1ac91d8 2876 kfree(u.buffer);
313a3dc7
CO		 2877 return r;
2878}
2879
5b1c1493
CO		 2880int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
2881{
2882 return VM_FAULT_SIGBUS;
2883}
2884
1fe779f8
CO		 2885static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
2886{
2887 int ret;
2888
2889 if (addr > (unsigned int)(-3 * PAGE_SIZE))
2890 return -1;
2891 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
2892 return ret;
2893}
2894
b927a3ce
SY		 2895static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
2896 u64 ident_addr)
2897{
2898 kvm->arch.ept_identity_map_addr = ident_addr;
2899 return 0;
2900}
2901
1fe779f8
CO		 2902static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
2903 u32 kvm_nr_mmu_pages)
2904{
2905 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
2906 return -EINVAL;
2907
79fac95e 2908 mutex_lock(&kvm->slots_lock);
7c8a83b7 2909 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 2910
2911 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 2912 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 2913
7c8a83b7 2914 spin_unlock(&kvm->mmu_lock);
79fac95e 2915 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 2916 return 0;
2917}
2918
2919static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
2920{
39de71ec 2921 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 2922}
2923
1fe779f8
CO		 2924static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2925{
2926 int r;
2927
2928 r = 0;
2929 switch (chip->chip_id) {
2930 case KVM_IRQCHIP_PIC_MASTER:
2931 memcpy(&chip->chip.pic,
2932 &pic_irqchip(kvm)->pics[0],
2933 sizeof(struct kvm_pic_state));
2934 break;
2935 case KVM_IRQCHIP_PIC_SLAVE:
2936 memcpy(&chip->chip.pic,
2937 &pic_irqchip(kvm)->pics[1],
2938 sizeof(struct kvm_pic_state));
2939 break;
2940 case KVM_IRQCHIP_IOAPIC:
eba0226b 2941 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2942 break;
2943 default:
2944 r = -EINVAL;
2945 break;
2946 }
2947 return r;
2948}
2949
2950static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2951{
2952 int r;
2953
2954 r = 0;
2955 switch (chip->chip_id) {
2956 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 2957 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2958 memcpy(&pic_irqchip(kvm)->pics[0],
2959 &chip->chip.pic,
2960 sizeof(struct kvm_pic_state));
f4f51050 2961 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2962 break;
2963 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 2964 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2965 memcpy(&pic_irqchip(kvm)->pics[1],
2966 &chip->chip.pic,
2967 sizeof(struct kvm_pic_state));
f4f51050 2968 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2969 break;
2970 case KVM_IRQCHIP_IOAPIC:
eba0226b 2971 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 2972 break;
2973 default:
2974 r = -EINVAL;
2975 break;
2976 }
2977 kvm_pic_update_irq(pic_irqchip(kvm));
2978 return r;
2979}
2980
e0f63cb9
SY		 2981static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2982{
2983 int r = 0;
2984
894a9c55 2985 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2986 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 2987 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2988 return r;
2989}
2990
2991static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2992{
2993 int r = 0;
2994
894a9c55 2995 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2996 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 2997 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
2998 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
2999 return r;
3000}
3001
3002static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3003{
3004 int r = 0;
3005
3006 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3007 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3008 sizeof(ps->channels));
3009 ps->flags = kvm->arch.vpit->pit_state.flags;
3010 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3011 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3012 return r;
3013}
3014
3015static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3016{
3017 int r = 0, start = 0;
3018 u32 prev_legacy, cur_legacy;
3019 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3020 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3021 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3022 if (!prev_legacy && cur_legacy)
3023 start = 1;
3024 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3025 sizeof(kvm->arch.vpit->pit_state.channels));
3026 kvm->arch.vpit->pit_state.flags = ps->flags;
3027 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3028 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3029 return r;
3030}
3031
52d939a0
MT		 3032static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3033 struct kvm_reinject_control *control)
3034{
3035 if (!kvm->arch.vpit)
3036 return -ENXIO;
894a9c55 3037 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 3038 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 3039 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3040 return 0;
3041}
3042
95d4c16c
TY		 3043/**
3044 * write_protect_slot - write protect a slot for dirty logging
3045 * @kvm: the kvm instance
3046 * @memslot: the slot we protect
3047 * @dirty_bitmap: the bitmap indicating which pages are dirty
3048 * @nr_dirty_pages: the number of dirty pages
3049 *
3050 * We have two ways to find all sptes to protect:
3051 * 1. Use kvm_mmu_slot_remove_write_access() which walks all shadow pages and
3052 * checks ones that have a spte mapping a page in the slot.
3053 * 2. Use kvm_mmu_rmap_write_protect() for each gfn found in the bitmap.
3054 *
3055 * Generally speaking, if there are not so many dirty pages compared to the
3056 * number of shadow pages, we should use the latter.
3057 *
3058 * Note that letting others write into a page marked dirty in the old bitmap
3059 * by using the remaining tlb entry is not a problem. That page will become
3060 * write protected again when we flush the tlb and then be reported dirty to
3061 * the user space by copying the old bitmap.
3062 */
3063static void write_protect_slot(struct kvm *kvm,
3064 struct kvm_memory_slot *memslot,
3065 unsigned long *dirty_bitmap,
3066 unsigned long nr_dirty_pages)
3067{
6dbf79e7
TY		 3068 spin_lock(&kvm->mmu_lock);
3069
95d4c16c
TY		 3070 /* Not many dirty pages compared to # of shadow pages. */
3071 if (nr_dirty_pages < kvm->arch.n_used_mmu_pages) {
3072 unsigned long gfn_offset;
3073
3074 for_each_set_bit(gfn_offset, dirty_bitmap, memslot->npages) {
3075 unsigned long gfn = memslot->base_gfn + gfn_offset;
3076
95d4c16c 3077 kvm_mmu_rmap_write_protect(kvm, gfn, memslot);
95d4c16c
TY		 3078 }
3079 kvm_flush_remote_tlbs(kvm);
6dbf79e7 3080 } else
95d4c16c 3081 kvm_mmu_slot_remove_write_access(kvm, memslot->id);
6dbf79e7
TY		 3082
3083 spin_unlock(&kvm->mmu_lock);
95d4c16c
TY		 3084}
3085
5bb064dc
ZX		 3086/*
3087 * Get (and clear) the dirty memory log for a memory slot.
3088 */
3089int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
3090 struct kvm_dirty_log *log)
3091{
7850ac54 3092 int r;
5bb064dc 3093 struct kvm_memory_slot *memslot;
95d4c16c 3094 unsigned long n, nr_dirty_pages;
5bb064dc 3095
79fac95e 3096 mutex_lock(&kvm->slots_lock);
5bb064dc 3097
b050b015
MT		 3098 r = -EINVAL;
3099 if (log->slot >= KVM_MEMORY_SLOTS)
3100 goto out;
3101
28a37544 3102 memslot = id_to_memslot(kvm->memslots, log->slot);
b050b015
MT		 3103 r = -ENOENT;
3104 if (!memslot->dirty_bitmap)
3105 goto out;
3106
87bf6e7d 3107 n = kvm_dirty_bitmap_bytes(memslot);
95d4c16c 3108 nr_dirty_pages = memslot->nr_dirty_pages;
b050b015 3109
5bb064dc 3110 /* If nothing is dirty, don't bother messing with page tables. */
95d4c16c 3111 if (nr_dirty_pages) {
b050b015 3112 struct kvm_memslots *slots, *old_slots;
28a37544 3113 unsigned long *dirty_bitmap, *dirty_bitmap_head;
b050b015 3114
28a37544
XG		 3115 dirty_bitmap = memslot->dirty_bitmap;
3116 dirty_bitmap_head = memslot->dirty_bitmap_head;
3117 if (dirty_bitmap == dirty_bitmap_head)
3118 dirty_bitmap_head += n / sizeof(long);
3119 memset(dirty_bitmap_head, 0, n);
b050b015 3120
914ebccd 3121 r = -ENOMEM;
cdfca7b3 3122 slots = kmemdup(kvm->memslots, sizeof(*kvm->memslots), GFP_KERNEL);
515a0127 3123 if (!slots)
914ebccd 3124 goto out;
cdfca7b3 3125
28a37544 3126 memslot = id_to_memslot(slots, log->slot);
95d4c16c 3127 memslot->nr_dirty_pages = 0;
28a37544 3128 memslot->dirty_bitmap = dirty_bitmap_head;
be593d62 3129 update_memslots(slots, NULL);
b050b015
MT		 3130
3131 old_slots = kvm->memslots;
3132 rcu_assign_pointer(kvm->memslots, slots);
3133 synchronize_srcu_expedited(&kvm->srcu);
b050b015 3134 kfree(old_slots);
914ebccd 3135
95d4c16c 3136 write_protect_slot(kvm, memslot, dirty_bitmap, nr_dirty_pages);
edde99ce 3137
914ebccd 3138 r = -EFAULT;
515a0127 3139 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n))
914ebccd 3140 goto out;
914ebccd
TY		 3141 } else {
3142 r = -EFAULT;
3143 if (clear_user(log->dirty_bitmap, n))
3144 goto out;
5bb064dc 3145 }
b050b015 3146
5bb064dc
ZX		 3147 r = 0;
3148out:
79fac95e 3149 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3150 return r;
3151}
3152
1fe779f8
CO		 3153long kvm_arch_vm_ioctl(struct file *filp,
3154 unsigned int ioctl, unsigned long arg)
3155{
3156 struct kvm *kvm = filp->private_data;
3157 void __user *argp = (void __user *)arg;
367e1319 3158 int r = -ENOTTY;
f0d66275
DH		 3159 /*
3160 * This union makes it completely explicit to gcc-3.x
3161 * that these two variables' stack usage should be
3162 * combined, not added together.
3163 */
3164 union {
3165 struct kvm_pit_state ps;
e9f42757 3166 struct kvm_pit_state2 ps2;
c5ff41ce 3167 struct kvm_pit_config pit_config;
f0d66275 3168 } u;
1fe779f8
CO		 3169
3170 switch (ioctl) {
3171 case KVM_SET_TSS_ADDR:
3172 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3173 if (r < 0)
3174 goto out;
3175 break;
b927a3ce
SY		 3176 case KVM_SET_IDENTITY_MAP_ADDR: {
3177 u64 ident_addr;
3178
3179 r = -EFAULT;
3180 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3181 goto out;
3182 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3183 if (r < 0)
3184 goto out;
3185 break;
3186 }
1fe779f8
CO		 3187 case KVM_SET_NR_MMU_PAGES:
3188 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3189 if (r)
3190 goto out;
3191 break;
3192 case KVM_GET_NR_MMU_PAGES:
3193 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3194 break;
3ddea128
MT		 3195 case KVM_CREATE_IRQCHIP: {
3196 struct kvm_pic *vpic;
3197
3198 mutex_lock(&kvm->lock);
3199 r = -EEXIST;
3200 if (kvm->arch.vpic)
3201 goto create_irqchip_unlock;
1fe779f8 3202 r = -ENOMEM;
3ddea128
MT		 3203 vpic = kvm_create_pic(kvm);
3204 if (vpic) {
1fe779f8
CO		 3205 r = kvm_ioapic_init(kvm);
3206 if (r) {
175504cd 3207 mutex_lock(&kvm->slots_lock);
72bb2fcd 3208 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3209 &vpic->dev_master);
3210 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3211 &vpic->dev_slave);
3212 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3213 &vpic->dev_eclr);
175504cd 3214 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3215 kfree(vpic);
3216 goto create_irqchip_unlock;
1fe779f8
CO		 3217 }
3218 } else
3ddea128
MT		 3219 goto create_irqchip_unlock;
3220 smp_wmb();
3221 kvm->arch.vpic = vpic;
3222 smp_wmb();
399ec807
AK		 3223 r = kvm_setup_default_irq_routing(kvm);
3224 if (r) {
175504cd 3225 mutex_lock(&kvm->slots_lock);
3ddea128 3226 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3227 kvm_ioapic_destroy(kvm);
3228 kvm_destroy_pic(kvm);
3ddea128 3229 mutex_unlock(&kvm->irq_lock);
175504cd 3230 mutex_unlock(&kvm->slots_lock);
399ec807 3231 }
3ddea128
MT		 3232 create_irqchip_unlock:
3233 mutex_unlock(&kvm->lock);
1fe779f8 3234 break;
3ddea128 3235 }
7837699f 3236 case KVM_CREATE_PIT:
c5ff41ce
JK		 3237 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3238 goto create_pit;
3239 case KVM_CREATE_PIT2:
3240 r = -EFAULT;
3241 if (copy_from_user(&u.pit_config, argp,
3242 sizeof(struct kvm_pit_config)))
3243 goto out;
3244 create_pit:
79fac95e 3245 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3246 r = -EEXIST;
3247 if (kvm->arch.vpit)
3248 goto create_pit_unlock;
7837699f 3249 r = -ENOMEM;
c5ff41ce 3250 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3251 if (kvm->arch.vpit)
3252 r = 0;
269e05e4 3253 create_pit_unlock:
79fac95e 3254 mutex_unlock(&kvm->slots_lock);
7837699f 3255 break;
4925663a 3256 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 3257 case KVM_IRQ_LINE: {
3258 struct kvm_irq_level irq_event;
3259
3260 r = -EFAULT;
3261 if (copy_from_user(&irq_event, argp, sizeof irq_event))
3262 goto out;
160d2f6c 3263 r = -ENXIO;
1fe779f8 3264 if (irqchip_in_kernel(kvm)) {
4925663a 3265 __s32 status;
4925663a
GN		 3266 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3267 irq_event.irq, irq_event.level);
4925663a 3268 if (ioctl == KVM_IRQ_LINE_STATUS) {
160d2f6c 3269 r = -EFAULT;
4925663a
GN		 3270 irq_event.status = status;
3271 if (copy_to_user(argp, &irq_event,
3272 sizeof irq_event))
3273 goto out;
3274 }
1fe779f8
CO		 3275 r = 0;
3276 }
3277 break;
3278 }
3279 case KVM_GET_IRQCHIP: {
3280 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3281 struct kvm_irqchip *chip;
1fe779f8 3282
ff5c2c03
SL		 3283 chip = memdup_user(argp, sizeof(*chip));
3284 if (IS_ERR(chip)) {
3285 r = PTR_ERR(chip);
1fe779f8 3286 goto out;
ff5c2c03
SL		 3287 }
3288
1fe779f8
CO		 3289 r = -ENXIO;
3290 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3291 goto get_irqchip_out;
3292 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3293 if (r)
f0d66275 3294 goto get_irqchip_out;
1fe779f8 3295 r = -EFAULT;
f0d66275
DH		 3296 if (copy_to_user(argp, chip, sizeof *chip))
3297 goto get_irqchip_out;
1fe779f8 3298 r = 0;
f0d66275
DH		 3299 get_irqchip_out:
3300 kfree(chip);
3301 if (r)
3302 goto out;
1fe779f8
CO		 3303 break;
3304 }
3305 case KVM_SET_IRQCHIP: {
3306 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3307 struct kvm_irqchip *chip;
1fe779f8 3308
ff5c2c03
SL		 3309 chip = memdup_user(argp, sizeof(*chip));
3310 if (IS_ERR(chip)) {
3311 r = PTR_ERR(chip);
1fe779f8 3312 goto out;
ff5c2c03
SL		 3313 }
3314
1fe779f8
CO		 3315 r = -ENXIO;
3316 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3317 goto set_irqchip_out;
3318 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3319 if (r)
f0d66275 3320 goto set_irqchip_out;
1fe779f8 3321 r = 0;
f0d66275
DH		 3322 set_irqchip_out:
3323 kfree(chip);
3324 if (r)
3325 goto out;
1fe779f8
CO		 3326 break;
3327 }
e0f63cb9 3328 case KVM_GET_PIT: {
e0f63cb9 3329 r = -EFAULT;
f0d66275 3330 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3331 goto out;
3332 r = -ENXIO;
3333 if (!kvm->arch.vpit)
3334 goto out;
f0d66275 3335 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3336 if (r)
3337 goto out;
3338 r = -EFAULT;
f0d66275 3339 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3340 goto out;
3341 r = 0;
3342 break;
3343 }
3344 case KVM_SET_PIT: {
e0f63cb9 3345 r = -EFAULT;
f0d66275 3346 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3347 goto out;
3348 r = -ENXIO;
3349 if (!kvm->arch.vpit)
3350 goto out;
f0d66275 3351 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3352 if (r)
3353 goto out;
3354 r = 0;
3355 break;
3356 }
e9f42757
BK		 3357 case KVM_GET_PIT2: {
3358 r = -ENXIO;
3359 if (!kvm->arch.vpit)
3360 goto out;
3361 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3362 if (r)
3363 goto out;
3364 r = -EFAULT;
3365 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3366 goto out;
3367 r = 0;
3368 break;
3369 }
3370 case KVM_SET_PIT2: {
3371 r = -EFAULT;
3372 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3373 goto out;
3374 r = -ENXIO;
3375 if (!kvm->arch.vpit)
3376 goto out;
3377 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3378 if (r)
3379 goto out;
3380 r = 0;
3381 break;
3382 }
52d939a0
MT		 3383 case KVM_REINJECT_CONTROL: {
3384 struct kvm_reinject_control control;
3385 r = -EFAULT;
3386 if (copy_from_user(&control, argp, sizeof(control)))
3387 goto out;
3388 r = kvm_vm_ioctl_reinject(kvm, &control);
3389 if (r)
3390 goto out;
3391 r = 0;
3392 break;
3393 }
ffde22ac
ES		 3394 case KVM_XEN_HVM_CONFIG: {
3395 r = -EFAULT;
3396 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3397 sizeof(struct kvm_xen_hvm_config)))
3398 goto out;
3399 r = -EINVAL;
3400 if (kvm->arch.xen_hvm_config.flags)
3401 goto out;
3402 r = 0;
3403 break;
3404 }
afbcf7ab 3405 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3406 struct kvm_clock_data user_ns;
3407 u64 now_ns;
3408 s64 delta;
3409
3410 r = -EFAULT;
3411 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3412 goto out;
3413
3414 r = -EINVAL;
3415 if (user_ns.flags)
3416 goto out;
3417
3418 r = 0;
395c6b0a 3419 local_irq_disable();
759379dd 3420 now_ns = get_kernel_ns();
afbcf7ab 3421 delta = user_ns.clock - now_ns;
395c6b0a 3422 local_irq_enable();
afbcf7ab
GC		 3423 kvm->arch.kvmclock_offset = delta;
3424 break;
3425 }
3426 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3427 struct kvm_clock_data user_ns;
3428 u64 now_ns;
3429
395c6b0a 3430 local_irq_disable();
759379dd 3431 now_ns = get_kernel_ns();
afbcf7ab 3432 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3433 local_irq_enable();
afbcf7ab 3434 user_ns.flags = 0;
97e69aa6 3435 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3436
3437 r = -EFAULT;
3438 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3439 goto out;
3440 r = 0;
3441 break;
3442 }
3443
1fe779f8
CO		 3444 default:
3445 ;
3446 }
3447out:
3448 return r;
3449}
3450
a16b043c 3451static void kvm_init_msr_list(void)
043405e1
CO		 3452{
3453 u32 dummy[2];
3454 unsigned i, j;
3455
e3267cbb
GC		 3456 /* skip the first msrs in the list. KVM-specific */
3457 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3458 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3459 continue;
3460 if (j < i)
3461 msrs_to_save[j] = msrs_to_save[i];
3462 j++;
3463 }
3464 num_msrs_to_save = j;
3465}
3466
bda9020e
MT		 3467static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3468 const void *v)
bbd9b64e 3469{
70252a10
AK		 3470 int handled = 0;
3471 int n;
3472
3473 do {
3474 n = min(len, 8);
3475 if (!(vcpu->arch.apic &&
3476 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3477 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3478 break;
3479 handled += n;
3480 addr += n;
3481 len -= n;
3482 v += n;
3483 } while (len);
bbd9b64e 3484
70252a10 3485 return handled;
bbd9b64e
CO		 3486}
3487
bda9020e 3488static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3489{
70252a10
AK		 3490 int handled = 0;
3491 int n;
3492
3493 do {
3494 n = min(len, 8);
3495 if (!(vcpu->arch.apic &&
3496 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3497 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3498 break;
3499 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3500 handled += n;
3501 addr += n;
3502 len -= n;
3503 v += n;
3504 } while (len);
bbd9b64e 3505
70252a10 3506 return handled;
bbd9b64e
CO		 3507}
3508
2dafc6c2
GN		 3509static void kvm_set_segment(struct kvm_vcpu *vcpu,
3510 struct kvm_segment *var, int seg)
3511{
3512 kvm_x86_ops->set_segment(vcpu, var, seg);
3513}
3514
3515void kvm_get_segment(struct kvm_vcpu *vcpu,
3516 struct kvm_segment *var, int seg)
3517{
3518 kvm_x86_ops->get_segment(vcpu, var, seg);
3519}
3520
e459e322 3521gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
02f59dc9
JR		 3522{
3523 gpa_t t_gpa;
ab9ae313 3524 struct x86_exception exception;
02f59dc9
JR		 3525
3526 BUG_ON(!mmu_is_nested(vcpu));
3527
3528 /* NPT walks are always user-walks */
3529 access |= PFERR_USER_MASK;
ab9ae313 3530 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
02f59dc9
JR		 3531
3532 return t_gpa;
3533}
3534
ab9ae313
AK		 3535gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3536 struct x86_exception *exception)
1871c602
GN		 3537{
3538 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 3539 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3540}
3541
ab9ae313
AK		 3542 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3543 struct x86_exception *exception)
1871c602
GN		 3544{
3545 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3546 access |= PFERR_FETCH_MASK;
ab9ae313 3547 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3548}
3549
ab9ae313
AK		 3550gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3551 struct x86_exception *exception)
1871c602
GN		 3552{
3553 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3554 access |= PFERR_WRITE_MASK;
ab9ae313 3555 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3556}
3557
3558/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 3559gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3560 struct x86_exception *exception)
1871c602 3561{
ab9ae313 3562 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 3563}
3564
3565static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3566 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 3567 struct x86_exception *exception)
bbd9b64e
CO		 3568{
3569 void *data = val;
10589a46 3570 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3571
3572 while (bytes) {
14dfe855 3573 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 3574 exception);
bbd9b64e 3575 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3576 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3577 int ret;
3578
bcc55cba 3579 if (gpa == UNMAPPED_GVA)
ab9ae313 3580 return X86EMUL_PROPAGATE_FAULT;
77c2002e 3581 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3582 if (ret < 0) {
c3cd7ffa 3583 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3584 goto out;
3585 }
bbd9b64e 3586
77c2002e
IE		 3587 bytes -= toread;
3588 data += toread;
3589 addr += toread;
bbd9b64e 3590 }
10589a46 3591out:
10589a46 3592 return r;
bbd9b64e 3593}
77c2002e 3594
1871c602 3595/* used for instruction fetching */
0f65dd70
AK		 3596static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
3597 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3598 struct x86_exception *exception)
1871c602 3599{
0f65dd70 3600 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3601 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3602
1871c602 3603 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
bcc55cba
AK		 3604 access | PFERR_FETCH_MASK,
3605 exception);
1871c602
GN		 3606}
3607
064aea77 3608int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 3609 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3610 struct x86_exception *exception)
1871c602 3611{
0f65dd70 3612 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3613 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3614
1871c602 3615 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 3616 exception);
1871c602 3617}
064aea77 3618EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 3619
0f65dd70
AK		 3620static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3621 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3622 struct x86_exception *exception)
1871c602 3623{
0f65dd70 3624 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 3625 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 3626}
3627
6a4d7550 3628int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 3629 gva_t addr, void *val,
2dafc6c2 3630 unsigned int bytes,
bcc55cba 3631 struct x86_exception *exception)
77c2002e 3632{
0f65dd70 3633 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 3634 void *data = val;
3635 int r = X86EMUL_CONTINUE;
3636
3637 while (bytes) {
14dfe855
JR		 3638 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3639 PFERR_WRITE_MASK,
ab9ae313 3640 exception);
77c2002e
IE		 3641 unsigned offset = addr & (PAGE_SIZE-1);
3642 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3643 int ret;
3644
bcc55cba 3645 if (gpa == UNMAPPED_GVA)
ab9ae313 3646 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 3647 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3648 if (ret < 0) {
c3cd7ffa 3649 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 3650 goto out;
3651 }
3652
3653 bytes -= towrite;
3654 data += towrite;
3655 addr += towrite;
3656 }
3657out:
3658 return r;
3659}
6a4d7550 3660EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 3661
af7cc7d1
XG		 3662static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
3663 gpa_t *gpa, struct x86_exception *exception,
3664 bool write)
3665{
3666 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3667
bebb106a
XG		 3668 if (vcpu_match_mmio_gva(vcpu, gva) &&
3669 check_write_user_access(vcpu, write, access,
3670 vcpu->arch.access)) {
3671 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
3672 (gva & (PAGE_SIZE - 1));
4f022648 3673 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 3674 return 1;
3675 }
3676
af7cc7d1
XG		 3677 if (write)
3678 access |= PFERR_WRITE_MASK;
3679
3680 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3681
3682 if (*gpa == UNMAPPED_GVA)
3683 return -1;
3684
3685 /* For APIC access vmexit */
3686 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3687 return 1;
3688
4f022648
XG		 3689 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
3690 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 3691 return 1;
4f022648 3692 }
bebb106a 3693
af7cc7d1
XG		 3694 return 0;
3695}
3696
3200f405 3697int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 3698 const void *val, int bytes)
bbd9b64e
CO		 3699{
3700 int ret;
3701
3702 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3703 if (ret < 0)
bbd9b64e 3704 return 0;
f57f2ef5 3705 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 3706 return 1;
3707}
3708
77d197b2
XG		 3709struct read_write_emulator_ops {
3710 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
3711 int bytes);
3712 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
3713 void *val, int bytes);
3714 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
3715 int bytes, void *val);
3716 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
3717 void *val, int bytes);
3718 bool write;
3719};
3720
3721static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
3722{
3723 if (vcpu->mmio_read_completed) {
3724 memcpy(val, vcpu->mmio_data, bytes);
3725 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3726 vcpu->mmio_phys_addr, *(u64 *)val);
3727 vcpu->mmio_read_completed = 0;
3728 return 1;
3729 }
3730
3731 return 0;
3732}
3733
3734static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
3735 void *val, int bytes)
3736{
3737 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
3738}
3739
3740static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
3741 void *val, int bytes)
3742{
3743 return emulator_write_phys(vcpu, gpa, val, bytes);
3744}
3745
3746static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
3747{
3748 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
3749 return vcpu_mmio_write(vcpu, gpa, bytes, val);
3750}
3751
3752static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
3753 void *val, int bytes)
3754{
3755 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
3756 return X86EMUL_IO_NEEDED;
3757}
3758
3759static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
3760 void *val, int bytes)
3761{
3762 memcpy(vcpu->mmio_data, val, bytes);
3763 memcpy(vcpu->run->mmio.data, vcpu->mmio_data, 8);
3764 return X86EMUL_CONTINUE;
3765}
3766
3767static struct read_write_emulator_ops read_emultor = {
3768 .read_write_prepare = read_prepare,
3769 .read_write_emulate = read_emulate,
3770 .read_write_mmio = vcpu_mmio_read,
3771 .read_write_exit_mmio = read_exit_mmio,
3772};
3773
3774static struct read_write_emulator_ops write_emultor = {
3775 .read_write_emulate = write_emulate,
3776 .read_write_mmio = write_mmio,
3777 .read_write_exit_mmio = write_exit_mmio,
3778 .write = true,
3779};
3780
22388a3c
XG		 3781static int emulator_read_write_onepage(unsigned long addr, void *val,
3782 unsigned int bytes,
3783 struct x86_exception *exception,
3784 struct kvm_vcpu *vcpu,
3785 struct read_write_emulator_ops *ops)
bbd9b64e 3786{
af7cc7d1
XG		 3787 gpa_t gpa;
3788 int handled, ret;
22388a3c
XG		 3789 bool write = ops->write;
3790
3791 if (ops->read_write_prepare &&
3792 ops->read_write_prepare(vcpu, val, bytes))
3793 return X86EMUL_CONTINUE;
10589a46 3794
22388a3c 3795 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 3796
af7cc7d1 3797 if (ret < 0)
bbd9b64e 3798 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3799
3800 /* For APIC access vmexit */
af7cc7d1 3801 if (ret)
bbd9b64e
CO		 3802 goto mmio;
3803
22388a3c 3804 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 3805 return X86EMUL_CONTINUE;
3806
3807mmio:
3808 /*
3809 * Is this MMIO handled locally?
3810 */
22388a3c 3811 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 3812 if (handled == bytes)
bbd9b64e 3813 return X86EMUL_CONTINUE;
bbd9b64e 3814
70252a10
AK		 3815 gpa += handled;
3816 bytes -= handled;
3817 val += handled;
3818
bbd9b64e 3819 vcpu->mmio_needed = 1;
411c35b7
GN		 3820 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3821 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
cef4dea0
AK		 3822 vcpu->mmio_size = bytes;
3823 vcpu->run->mmio.len = min(vcpu->mmio_size, 8);
22388a3c 3824 vcpu->run->mmio.is_write = vcpu->mmio_is_write = write;
cef4dea0 3825 vcpu->mmio_index = 0;
bbd9b64e 3826
22388a3c 3827 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
bbd9b64e
CO		 3828}
3829
22388a3c
XG		 3830int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
3831 void *val, unsigned int bytes,
3832 struct x86_exception *exception,
3833 struct read_write_emulator_ops *ops)
bbd9b64e 3834{
0f65dd70
AK		 3835 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3836
bbd9b64e
CO		 3837 /* Crossing a page boundary? */
3838 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3839 int rc, now;
3840
3841 now = -addr & ~PAGE_MASK;
22388a3c
XG		 3842 rc = emulator_read_write_onepage(addr, val, now, exception,
3843 vcpu, ops);
3844
bbd9b64e
CO		 3845 if (rc != X86EMUL_CONTINUE)
3846 return rc;
3847 addr += now;
3848 val += now;
3849 bytes -= now;
3850 }
22388a3c
XG		 3851
3852 return emulator_read_write_onepage(addr, val, bytes, exception,
3853 vcpu, ops);
3854}
3855
3856static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
3857 unsigned long addr,
3858 void *val,
3859 unsigned int bytes,
3860 struct x86_exception *exception)
3861{
3862 return emulator_read_write(ctxt, addr, val, bytes,
3863 exception, &read_emultor);
3864}
3865
3866int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
3867 unsigned long addr,
3868 const void *val,
3869 unsigned int bytes,
3870 struct x86_exception *exception)
3871{
3872 return emulator_read_write(ctxt, addr, (void *)val, bytes,
3873 exception, &write_emultor);
bbd9b64e 3874}
bbd9b64e 3875
daea3e73
AK		 3876#define CMPXCHG_TYPE(t, ptr, old, new) \
3877 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
3878
3879#ifdef CONFIG_X86_64
3880# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
3881#else
3882# define CMPXCHG64(ptr, old, new) \
9749a6c0 3883 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 3884#endif
3885
0f65dd70
AK		 3886static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
3887 unsigned long addr,
bbd9b64e
CO		 3888 const void *old,
3889 const void *new,
3890 unsigned int bytes,
0f65dd70 3891 struct x86_exception *exception)
bbd9b64e 3892{
0f65dd70 3893 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 3894 gpa_t gpa;
3895 struct page *page;
3896 char *kaddr;
3897 bool exchanged;
2bacc55c 3898
daea3e73
AK		 3899 /* guests cmpxchg8b have to be emulated atomically */
3900 if (bytes > 8 || (bytes & (bytes - 1)))
3901 goto emul_write;
10589a46 3902
daea3e73 3903 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 3904
daea3e73
AK		 3905 if (gpa == UNMAPPED_GVA ||
3906 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3907 goto emul_write;
2bacc55c 3908
daea3e73
AK		 3909 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3910 goto emul_write;
72dc67a6 3911
daea3e73 3912 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
c19b8bd6
WY		 3913 if (is_error_page(page)) {
3914 kvm_release_page_clean(page);
3915 goto emul_write;
3916 }
72dc67a6 3917
daea3e73
AK		 3918 kaddr = kmap_atomic(page, KM_USER0);
3919 kaddr += offset_in_page(gpa);
3920 switch (bytes) {
3921 case 1:
3922 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
3923 break;
3924 case 2:
3925 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
3926 break;
3927 case 4:
3928 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
3929 break;
3930 case 8:
3931 exchanged = CMPXCHG64(kaddr, old, new);
3932 break;
3933 default:
3934 BUG();
2bacc55c 3935 }
daea3e73
AK		 3936 kunmap_atomic(kaddr, KM_USER0);
3937 kvm_release_page_dirty(page);
3938
3939 if (!exchanged)
3940 return X86EMUL_CMPXCHG_FAILED;
3941
f57f2ef5 3942 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 3943
3944 return X86EMUL_CONTINUE;
4a5f48f6 3945
3200f405 3946emul_write:
daea3e73 3947 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 3948
0f65dd70 3949 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 3950}
3951
cf8f70bf
GN		 3952static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
3953{
3954 /* TODO: String I/O for in kernel device */
3955 int r;
3956
3957 if (vcpu->arch.pio.in)
3958 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
3959 vcpu->arch.pio.size, pd);
3960 else
3961 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
3962 vcpu->arch.pio.port, vcpu->arch.pio.size,
3963 pd);
3964 return r;
3965}
3966
6f6fbe98
XG		 3967static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
3968 unsigned short port, void *val,
3969 unsigned int count, bool in)
cf8f70bf 3970{
6f6fbe98 3971 trace_kvm_pio(!in, port, size, count);
cf8f70bf
GN		 3972
3973 vcpu->arch.pio.port = port;
6f6fbe98 3974 vcpu->arch.pio.in = in;
7972995b 3975 vcpu->arch.pio.count = count;
cf8f70bf
GN		 3976 vcpu->arch.pio.size = size;
3977
3978 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 3979 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 3980 return 1;
3981 }
3982
3983 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 3984 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 3985 vcpu->run->io.size = size;
3986 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
3987 vcpu->run->io.count = count;
3988 vcpu->run->io.port = port;
3989
3990 return 0;
3991}
3992
6f6fbe98
XG		 3993static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
3994 int size, unsigned short port, void *val,
3995 unsigned int count)
cf8f70bf 3996{
ca1d4a9e 3997 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 3998 int ret;
ca1d4a9e 3999
6f6fbe98
XG		 4000 if (vcpu->arch.pio.count)
4001 goto data_avail;
cf8f70bf 4002
6f6fbe98
XG		 4003 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4004 if (ret) {
4005data_avail:
4006 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 4007 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4008 return 1;
4009 }
4010
cf8f70bf
GN		 4011 return 0;
4012}
4013
6f6fbe98
XG		 4014static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4015 int size, unsigned short port,
4016 const void *val, unsigned int count)
4017{
4018 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4019
4020 memcpy(vcpu->arch.pio_data, val, size * count);
4021 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4022}
4023
bbd9b64e
CO		 4024static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4025{
4026 return kvm_x86_ops->get_segment_base(vcpu, seg);
4027}
4028
3cb16fe7 4029static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4030{
3cb16fe7 4031 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4032}
4033
f5f48ee1
SY		 4034int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4035{
4036 if (!need_emulate_wbinvd(vcpu))
4037 return X86EMUL_CONTINUE;
4038
4039 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4040 int cpu = get_cpu();
4041
4042 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4043 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4044 wbinvd_ipi, NULL, 1);
2eec7343 4045 put_cpu();
f5f48ee1 4046 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4047 } else
4048 wbinvd();
f5f48ee1
SY		 4049 return X86EMUL_CONTINUE;
4050}
4051EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4052
bcaf5cc5
AK		 4053static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4054{
4055 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4056}
4057
717746e3 4058int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
bbd9b64e 4059{
717746e3 4060 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4061}
4062
717746e3 4063int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
bbd9b64e 4064{
338dbc97 4065
717746e3 4066 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4067}
4068
52a46617 4069static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4070{
52a46617 4071 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4072}
4073
717746e3 4074static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4075{
717746e3 4076 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4077 unsigned long value;
4078
4079 switch (cr) {
4080 case 0:
4081 value = kvm_read_cr0(vcpu);
4082 break;
4083 case 2:
4084 value = vcpu->arch.cr2;
4085 break;
4086 case 3:
9f8fe504 4087 value = kvm_read_cr3(vcpu);
52a46617
GN		 4088 break;
4089 case 4:
4090 value = kvm_read_cr4(vcpu);
4091 break;
4092 case 8:
4093 value = kvm_get_cr8(vcpu);
4094 break;
4095 default:
4096 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
4097 return 0;
4098 }
4099
4100 return value;
4101}
4102
717746e3 4103static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4104{
717746e3 4105 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4106 int res = 0;
4107
52a46617
GN		 4108 switch (cr) {
4109 case 0:
49a9b07e 4110 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4111 break;
4112 case 2:
4113 vcpu->arch.cr2 = val;
4114 break;
4115 case 3:
2390218b 4116 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4117 break;
4118 case 4:
a83b29c6 4119 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4120 break;
4121 case 8:
eea1cff9 4122 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4123 break;
4124 default:
4125 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
0f12244f 4126 res = -1;
52a46617 4127 }
0f12244f
GN		 4128
4129 return res;
52a46617
GN		 4130}
4131
4cee4798
KW		 4132static void emulator_set_rflags(struct x86_emulate_ctxt *ctxt, ulong val)
4133{
4134 kvm_set_rflags(emul_to_vcpu(ctxt), val);
4135}
4136
717746e3 4137static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4138{
717746e3 4139 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4140}
4141
4bff1e86 4142static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4143{
4bff1e86 4144 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4145}
4146
4bff1e86 4147static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4148{
4bff1e86 4149 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4150}
4151
1ac9d0cf
AK		 4152static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4153{
4154 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4155}
4156
4157static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4158{
4159 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4160}
4161
4bff1e86
AK		 4162static unsigned long emulator_get_cached_segment_base(
4163 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4164{
4bff1e86 4165 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4166}
4167
1aa36616
AK		 4168static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4169 struct desc_struct *desc, u32 *base3,
4170 int seg)
2dafc6c2
GN		 4171{
4172 struct kvm_segment var;
4173
4bff1e86 4174 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4175 *selector = var.selector;
2dafc6c2
GN		 4176
4177 if (var.unusable)
4178 return false;
4179
4180 if (var.g)
4181 var.limit >>= 12;
4182 set_desc_limit(desc, var.limit);
4183 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4184#ifdef CONFIG_X86_64
4185 if (base3)
4186 *base3 = var.base >> 32;
4187#endif
2dafc6c2
GN		 4188 desc->type = var.type;
4189 desc->s = var.s;
4190 desc->dpl = var.dpl;
4191 desc->p = var.present;
4192 desc->avl = var.avl;
4193 desc->l = var.l;
4194 desc->d = var.db;
4195 desc->g = var.g;
4196
4197 return true;
4198}
4199
1aa36616
AK		 4200static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4201 struct desc_struct *desc, u32 base3,
4202 int seg)
2dafc6c2 4203{
4bff1e86 4204 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4205 struct kvm_segment var;
4206
1aa36616 4207 var.selector = selector;
2dafc6c2 4208 var.base = get_desc_base(desc);
5601d05b
GN		 4209#ifdef CONFIG_X86_64
4210 var.base |= ((u64)base3) << 32;
4211#endif
2dafc6c2
GN		 4212 var.limit = get_desc_limit(desc);
4213 if (desc->g)
4214 var.limit = (var.limit << 12) | 0xfff;
4215 var.type = desc->type;
4216 var.present = desc->p;
4217 var.dpl = desc->dpl;
4218 var.db = desc->d;
4219 var.s = desc->s;
4220 var.l = desc->l;
4221 var.g = desc->g;
4222 var.avl = desc->avl;
4223 var.present = desc->p;
4224 var.unusable = !var.present;
4225 var.padding = 0;
4226
4227 kvm_set_segment(vcpu, &var, seg);
4228 return;
4229}
4230
717746e3
AK		 4231static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4232 u32 msr_index, u64 *pdata)
4233{
4234 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4235}
4236
4237static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4238 u32 msr_index, u64 data)
4239{
4240 return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
4241}
4242
222d21aa
AK		 4243static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4244 u32 pmc, u64 *pdata)
4245{
4246 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4247}
4248
6c3287f7
AK		 4249static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4250{
4251 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4252}
4253
5037f6f3
AK		 4254static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4255{
4256 preempt_disable();
5197b808 4257 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4258 /*
4259 * CR0.TS may reference the host fpu state, not the guest fpu state,
4260 * so it may be clear at this point.
4261 */
4262 clts();
4263}
4264
4265static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4266{
4267 preempt_enable();
4268}
4269
2953538e 4270static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4271 struct x86_instruction_info *info,
c4f035c6
AK		 4272 enum x86_intercept_stage stage)
4273{
2953538e 4274 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4275}
4276
bdb42f5a
SB		 4277static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
4278 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4279{
4280 struct kvm_cpuid_entry2 *cpuid = NULL;
4281
4282 if (eax && ecx)
4283 cpuid = kvm_find_cpuid_entry(emul_to_vcpu(ctxt),
4284 *eax, *ecx);
4285
4286 if (cpuid) {
4287 *eax = cpuid->eax;
4288 *ecx = cpuid->ecx;
4289 if (ebx)
4290 *ebx = cpuid->ebx;
4291 if (edx)
4292 *edx = cpuid->edx;
4293 return true;
4294 }
4295
4296 return false;
4297}
4298
14af3f3c 4299static struct x86_emulate_ops emulate_ops = {
1871c602 4300 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4301 .write_std = kvm_write_guest_virt_system,
1871c602 4302 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4303 .read_emulated = emulator_read_emulated,
4304 .write_emulated = emulator_write_emulated,
4305 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4306 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4307 .pio_in_emulated = emulator_pio_in_emulated,
4308 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4309 .get_segment = emulator_get_segment,
4310 .set_segment = emulator_set_segment,
5951c442 4311 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4312 .get_gdt = emulator_get_gdt,
160ce1f1 4313 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4314 .set_gdt = emulator_set_gdt,
4315 .set_idt = emulator_set_idt,
52a46617
GN		 4316 .get_cr = emulator_get_cr,
4317 .set_cr = emulator_set_cr,
4cee4798 4318 .set_rflags = emulator_set_rflags,
9c537244 4319 .cpl = emulator_get_cpl,
35aa5375
GN		 4320 .get_dr = emulator_get_dr,
4321 .set_dr = emulator_set_dr,
717746e3
AK		 4322 .set_msr = emulator_set_msr,
4323 .get_msr = emulator_get_msr,
222d21aa 4324 .read_pmc = emulator_read_pmc,
6c3287f7 4325 .halt = emulator_halt,
bcaf5cc5 4326 .wbinvd = emulator_wbinvd,
d6aa1000 4327 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4328 .get_fpu = emulator_get_fpu,
4329 .put_fpu = emulator_put_fpu,
c4f035c6 4330 .intercept = emulator_intercept,
bdb42f5a 4331 .get_cpuid = emulator_get_cpuid,
bbd9b64e
CO		 4332};
4333
5fdbf976
MT		 4334static void cache_all_regs(struct kvm_vcpu *vcpu)
4335{
4336 kvm_register_read(vcpu, VCPU_REGS_RAX);
4337 kvm_register_read(vcpu, VCPU_REGS_RSP);
4338 kvm_register_read(vcpu, VCPU_REGS_RIP);
4339 vcpu->arch.regs_dirty = ~0;
4340}
4341
95cb2295
GN		 4342static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4343{
4344 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4345 /*
4346 * an sti; sti; sequence only disable interrupts for the first
4347 * instruction. So, if the last instruction, be it emulated or
4348 * not, left the system with the INT_STI flag enabled, it
4349 * means that the last instruction is an sti. We should not
4350 * leave the flag on in this case. The same goes for mov ss
4351 */
4352 if (!(int_shadow & mask))
4353 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4354}
4355
54b8486f
GN		 4356static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4357{
4358 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4359 if (ctxt->exception.vector == PF_VECTOR)
6389ee94 4360 kvm_propagate_fault(vcpu, &ctxt->exception);
da9cb575
AK		 4361 else if (ctxt->exception.error_code_valid)
4362 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4363 ctxt->exception.error_code);
54b8486f 4364 else
da9cb575 4365 kvm_queue_exception(vcpu, ctxt->exception.vector);
54b8486f
GN		 4366}
4367
9dac77fa 4368static void init_decode_cache(struct x86_emulate_ctxt *ctxt,
b5c9ff73
TY		 4369 const unsigned long *regs)
4370{
9dac77fa
AK		 4371 memset(&ctxt->twobyte, 0,
4372 (void *)&ctxt->regs - (void *)&ctxt->twobyte);
4373 memcpy(ctxt->regs, regs, sizeof(ctxt->regs));
b5c9ff73 4374
9dac77fa
AK		 4375 ctxt->fetch.start = 0;
4376 ctxt->fetch.end = 0;
4377 ctxt->io_read.pos = 0;
4378 ctxt->io_read.end = 0;
4379 ctxt->mem_read.pos = 0;
4380 ctxt->mem_read.end = 0;
b5c9ff73
TY		 4381}
4382
8ec4722d
MG		 4383static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4384{
adf52235 4385 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4386 int cs_db, cs_l;
4387
2aab2c5b
GN		 4388 /*
4389 * TODO: fix emulate.c to use guest_read/write_register
4390 * instead of direct ->regs accesses, can save hundred cycles
4391 * on Intel for instructions that don't read/change RSP, for
4392 * for example.
4393 */
8ec4722d
MG		 4394 cache_all_regs(vcpu);
4395
4396 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4397
adf52235
TY		 4398 ctxt->eflags = kvm_get_rflags(vcpu);
4399 ctxt->eip = kvm_rip_read(vcpu);
4400 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4401 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4402 cs_l ? X86EMUL_MODE_PROT64 :
4403 cs_db ? X86EMUL_MODE_PROT32 :
4404 X86EMUL_MODE_PROT16;
4405 ctxt->guest_mode = is_guest_mode(vcpu);
4406
9dac77fa 4407 init_decode_cache(ctxt, vcpu->arch.regs);
7ae441ea 4408 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4409}
4410
71f9833b 4411int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 4412{
9d74191a 4413 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 4414 int ret;
4415
4416 init_emulate_ctxt(vcpu);
4417
9dac77fa
AK		 4418 ctxt->op_bytes = 2;
4419 ctxt->ad_bytes = 2;
4420 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 4421 ret = emulate_int_real(ctxt, irq);
63995653
MG		 4422
4423 if (ret != X86EMUL_CONTINUE)
4424 return EMULATE_FAIL;
4425
9dac77fa
AK		 4426 ctxt->eip = ctxt->_eip;
4427 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
9d74191a
TY		 4428 kvm_rip_write(vcpu, ctxt->eip);
4429 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 4430
4431 if (irq == NMI_VECTOR)
7460fb4a 4432 vcpu->arch.nmi_pending = 0;
63995653
MG		 4433 else
4434 vcpu->arch.interrupt.pending = false;
4435
4436 return EMULATE_DONE;
4437}
4438EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4439
6d77dbfc
GN		 4440static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4441{
fc3a9157
JR		 4442 int r = EMULATE_DONE;
4443
6d77dbfc
GN		 4444 ++vcpu->stat.insn_emulation_fail;
4445 trace_kvm_emulate_insn_failed(vcpu);
fc3a9157
JR		 4446 if (!is_guest_mode(vcpu)) {
4447 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4448 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4449 vcpu->run->internal.ndata = 0;
4450 r = EMULATE_FAIL;
4451 }
6d77dbfc 4452 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4453
4454 return r;
6d77dbfc
GN		 4455}
4456
a6f177ef
GN		 4457static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
4458{
4459 gpa_t gpa;
4460
68be0803
GN		 4461 if (tdp_enabled)
4462 return false;
4463
a6f177ef
GN		 4464 /*
4465 * if emulation was due to access to shadowed page table
4466 * and it failed try to unshadow page and re-entetr the
4467 * guest to let CPU execute the instruction.
4468 */
4469 if (kvm_mmu_unprotect_page_virt(vcpu, gva))
4470 return true;
4471
4472 gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
4473
4474 if (gpa == UNMAPPED_GVA)
4475 return true; /* let cpu generate fault */
4476
4477 if (!kvm_is_error_hva(gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT)))
4478 return true;
4479
4480 return false;
4481}
4482
1cb3f3ae
XG		 4483static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
4484 unsigned long cr2, int emulation_type)
4485{
4486 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4487 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
4488
4489 last_retry_eip = vcpu->arch.last_retry_eip;
4490 last_retry_addr = vcpu->arch.last_retry_addr;
4491
4492 /*
4493 * If the emulation is caused by #PF and it is non-page_table
4494 * writing instruction, it means the VM-EXIT is caused by shadow
4495 * page protected, we can zap the shadow page and retry this
4496 * instruction directly.
4497 *
4498 * Note: if the guest uses a non-page-table modifying instruction
4499 * on the PDE that points to the instruction, then we will unmap
4500 * the instruction and go to an infinite loop. So, we cache the
4501 * last retried eip and the last fault address, if we meet the eip
4502 * and the address again, we can break out of the potential infinite
4503 * loop.
4504 */
4505 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
4506
4507 if (!(emulation_type & EMULTYPE_RETRY))
4508 return false;
4509
4510 if (x86_page_table_writing_insn(ctxt))
4511 return false;
4512
4513 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
4514 return false;
4515
4516 vcpu->arch.last_retry_eip = ctxt->eip;
4517 vcpu->arch.last_retry_addr = cr2;
4518
4519 if (!vcpu->arch.mmu.direct_map)
4520 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4521
4522 kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4523
4524 return true;
4525}
4526
51d8b661
AP		 4527int x86_emulate_instruction(struct kvm_vcpu *vcpu,
4528 unsigned long cr2,
dc25e89e
AP		 4529 int emulation_type,
4530 void *insn,
4531 int insn_len)
bbd9b64e 4532{
95cb2295 4533 int r;
9d74191a 4534 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 4535 bool writeback = true;
bbd9b64e 4536
26eef70c 4537 kvm_clear_exception_queue(vcpu);
8d7d8102 4538
571008da 4539 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 4540 init_emulate_ctxt(vcpu);
9d74191a
TY		 4541 ctxt->interruptibility = 0;
4542 ctxt->have_exception = false;
4543 ctxt->perm_ok = false;
bbd9b64e 4544
9d74191a 4545 ctxt->only_vendor_specific_insn
4005996e
AK		 4546 = emulation_type & EMULTYPE_TRAP_UD;
4547
9d74191a 4548 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 4549
e46479f8 4550 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 4551 ++vcpu->stat.insn_emulation;
1d2887e2 4552 if (r != EMULATION_OK) {
4005996e
AK		 4553 if (emulation_type & EMULTYPE_TRAP_UD)
4554 return EMULATE_FAIL;
a6f177ef 4555 if (reexecute_instruction(vcpu, cr2))
bbd9b64e 4556 return EMULATE_DONE;
6d77dbfc
GN		 4557 if (emulation_type & EMULTYPE_SKIP)
4558 return EMULATE_FAIL;
4559 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4560 }
4561 }
4562
ba8afb6b 4563 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 4564 kvm_rip_write(vcpu, ctxt->_eip);
ba8afb6b
GN		 4565 return EMULATE_DONE;
4566 }
4567
1cb3f3ae
XG		 4568 if (retry_instruction(ctxt, cr2, emulation_type))
4569 return EMULATE_DONE;
4570
7ae441ea 4571 /* this is needed for vmware backdoor interface to work since it
4d2179e1 4572 changes registers values during IO operation */
7ae441ea
GN		 4573 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
4574 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
9dac77fa 4575 memcpy(ctxt->regs, vcpu->arch.regs, sizeof ctxt->regs);
7ae441ea 4576 }
4d2179e1 4577
5cd21917 4578restart:
9d74191a 4579 r = x86_emulate_insn(ctxt);
bbd9b64e 4580
775fde86
JR		 4581 if (r == EMULATION_INTERCEPTED)
4582 return EMULATE_DONE;
4583
d2ddd1c4 4584 if (r == EMULATION_FAILED) {
a6f177ef 4585 if (reexecute_instruction(vcpu, cr2))
c3cd7ffa
GN		 4586 return EMULATE_DONE;
4587
6d77dbfc 4588 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4589 }
4590
9d74191a 4591 if (ctxt->have_exception) {
54b8486f 4592 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 4593 r = EMULATE_DONE;
4594 } else if (vcpu->arch.pio.count) {
3457e419
GN		 4595 if (!vcpu->arch.pio.in)
4596 vcpu->arch.pio.count = 0;
7ae441ea
GN		 4597 else
4598 writeback = false;
e85d28f8 4599 r = EMULATE_DO_MMIO;
7ae441ea
GN		 4600 } else if (vcpu->mmio_needed) {
4601 if (!vcpu->mmio_is_write)
4602 writeback = false;
e85d28f8 4603 r = EMULATE_DO_MMIO;
7ae441ea 4604 } else if (r == EMULATION_RESTART)
5cd21917 4605 goto restart;
d2ddd1c4
GN		 4606 else
4607 r = EMULATE_DONE;
f850e2e6 4608
7ae441ea 4609 if (writeback) {
9d74191a
TY		 4610 toggle_interruptibility(vcpu, ctxt->interruptibility);
4611 kvm_set_rflags(vcpu, ctxt->eflags);
7ae441ea 4612 kvm_make_request(KVM_REQ_EVENT, vcpu);
9dac77fa 4613 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
7ae441ea 4614 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 4615 kvm_rip_write(vcpu, ctxt->eip);
7ae441ea
GN		 4616 } else
4617 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 4618
4619 return r;
de7d789a 4620}
51d8b661 4621EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 4622
cf8f70bf 4623int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 4624{
cf8f70bf 4625 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 4626 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
4627 size, port, &val, 1);
cf8f70bf 4628 /* do not return to emulator after return from userspace */
7972995b 4629 vcpu->arch.pio.count = 0;
de7d789a
CO		 4630 return ret;
4631}
cf8f70bf 4632EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 4633
8cfdc000
ZA		 4634static void tsc_bad(void *info)
4635{
0a3aee0d 4636 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 4637}
4638
4639static void tsc_khz_changed(void *data)
c8076604 4640{
8cfdc000
ZA		 4641 struct cpufreq_freqs *freq = data;
4642 unsigned long khz = 0;
4643
4644 if (data)
4645 khz = freq->new;
4646 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4647 khz = cpufreq_quick_get(raw_smp_processor_id());
4648 if (!khz)
4649 khz = tsc_khz;
0a3aee0d 4650 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 4651}
4652
c8076604
GH		 4653static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4654 void *data)
4655{
4656 struct cpufreq_freqs *freq = data;
4657 struct kvm *kvm;
4658 struct kvm_vcpu *vcpu;
4659 int i, send_ipi = 0;
4660
8cfdc000
ZA		 4661 /*
4662 * We allow guests to temporarily run on slowing clocks,
4663 * provided we notify them after, or to run on accelerating
4664 * clocks, provided we notify them before. Thus time never
4665 * goes backwards.
4666 *
4667 * However, we have a problem. We can't atomically update
4668 * the frequency of a given CPU from this function; it is
4669 * merely a notifier, which can be called from any CPU.
4670 * Changing the TSC frequency at arbitrary points in time
4671 * requires a recomputation of local variables related to
4672 * the TSC for each VCPU. We must flag these local variables
4673 * to be updated and be sure the update takes place with the
4674 * new frequency before any guests proceed.
4675 *
4676 * Unfortunately, the combination of hotplug CPU and frequency
4677 * change creates an intractable locking scenario; the order
4678 * of when these callouts happen is undefined with respect to
4679 * CPU hotplug, and they can race with each other. As such,
4680 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
4681 * undefined; you can actually have a CPU frequency change take
4682 * place in between the computation of X and the setting of the
4683 * variable. To protect against this problem, all updates of
4684 * the per_cpu tsc_khz variable are done in an interrupt
4685 * protected IPI, and all callers wishing to update the value
4686 * must wait for a synchronous IPI to complete (which is trivial
4687 * if the caller is on the CPU already). This establishes the
4688 * necessary total order on variable updates.
4689 *
4690 * Note that because a guest time update may take place
4691 * anytime after the setting of the VCPU's request bit, the
4692 * correct TSC value must be set before the request. However,
4693 * to ensure the update actually makes it to any guest which
4694 * starts running in hardware virtualization between the set
4695 * and the acquisition of the spinlock, we must also ping the
4696 * CPU after setting the request bit.
4697 *
4698 */
4699
c8076604
GH		 4700 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
4701 return 0;
4702 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
4703 return 0;
8cfdc000
ZA		 4704
4705 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 4706
e935b837 4707 raw_spin_lock(&kvm_lock);
c8076604 4708 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 4709 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 4710 if (vcpu->cpu != freq->cpu)
4711 continue;
c285545f 4712 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 4713 if (vcpu->cpu != smp_processor_id())
8cfdc000 4714 send_ipi = 1;
c8076604
GH		 4715 }
4716 }
e935b837 4717 raw_spin_unlock(&kvm_lock);
c8076604
GH		 4718
4719 if (freq->old < freq->new && send_ipi) {
4720 /*
4721 * We upscale the frequency. Must make the guest
4722 * doesn't see old kvmclock values while running with
4723 * the new frequency, otherwise we risk the guest sees
4724 * time go backwards.
4725 *
4726 * In case we update the frequency for another cpu
4727 * (which might be in guest context) send an interrupt
4728 * to kick the cpu out of guest context. Next time
4729 * guest context is entered kvmclock will be updated,
4730 * so the guest will not see stale values.
4731 */
8cfdc000 4732 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 4733 }
4734 return 0;
4735}
4736
4737static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 4738 .notifier_call = kvmclock_cpufreq_notifier
4739};
4740
4741static int kvmclock_cpu_notifier(struct notifier_block *nfb,
4742 unsigned long action, void *hcpu)
4743{
4744 unsigned int cpu = (unsigned long)hcpu;
4745
4746 switch (action) {
4747 case CPU_ONLINE:
4748 case CPU_DOWN_FAILED:
4749 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4750 break;
4751 case CPU_DOWN_PREPARE:
4752 smp_call_function_single(cpu, tsc_bad, NULL, 1);
4753 break;
4754 }
4755 return NOTIFY_OK;
4756}
4757
4758static struct notifier_block kvmclock_cpu_notifier_block = {
4759 .notifier_call = kvmclock_cpu_notifier,
4760 .priority = -INT_MAX
c8076604
GH		 4761};
4762
b820cc0c
ZA		 4763static void kvm_timer_init(void)
4764{
4765 int cpu;
4766
c285545f 4767 max_tsc_khz = tsc_khz;
8cfdc000 4768 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 4769 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 4770#ifdef CONFIG_CPU_FREQ
4771 struct cpufreq_policy policy;
4772 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 4773 cpu = get_cpu();
4774 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 4775 if (policy.cpuinfo.max_freq)
4776 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 4777 put_cpu();
c285545f 4778#endif
b820cc0c
ZA		 4779 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4780 CPUFREQ_TRANSITION_NOTIFIER);
4781 }
c285545f 4782 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 4783 for_each_online_cpu(cpu)
4784 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 4785}
4786
ff9d07a0
ZY		 4787static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
4788
f5132b01 4789int kvm_is_in_guest(void)
ff9d07a0 4790{
086c9855 4791 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 4792}
4793
4794static int kvm_is_user_mode(void)
4795{
4796 int user_mode = 3;
dcf46b94 4797
086c9855
AS		 4798 if (__this_cpu_read(current_vcpu))
4799 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 4800
ff9d07a0
ZY		 4801 return user_mode != 0;
4802}
4803
4804static unsigned long kvm_get_guest_ip(void)
4805{
4806 unsigned long ip = 0;
dcf46b94 4807
086c9855
AS		 4808 if (__this_cpu_read(current_vcpu))
4809 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 4810
ff9d07a0
ZY		 4811 return ip;
4812}
4813
4814static struct perf_guest_info_callbacks kvm_guest_cbs = {
4815 .is_in_guest = kvm_is_in_guest,
4816 .is_user_mode = kvm_is_user_mode,
4817 .get_guest_ip = kvm_get_guest_ip,
4818};
4819
4820void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4821{
086c9855 4822 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 4823}
4824EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4825
4826void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4827{
086c9855 4828 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 4829}
4830EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4831
ce88decf
XG		 4832static void kvm_set_mmio_spte_mask(void)
4833{
4834 u64 mask;
4835 int maxphyaddr = boot_cpu_data.x86_phys_bits;
4836
4837 /*
4838 * Set the reserved bits and the present bit of an paging-structure
4839 * entry to generate page fault with PFER.RSV = 1.
4840 */
4841 mask = ((1ull << (62 - maxphyaddr + 1)) - 1) << maxphyaddr;
4842 mask |= 1ull;
4843
4844#ifdef CONFIG_X86_64
4845 /*
4846 * If reserved bit is not supported, clear the present bit to disable
4847 * mmio page fault.
4848 */
4849 if (maxphyaddr == 52)
4850 mask &= ~1ull;
4851#endif
4852
4853 kvm_mmu_set_mmio_spte_mask(mask);
4854}
4855
f8c16bba 4856int kvm_arch_init(void *opaque)
043405e1 4857{
b820cc0c 4858 int r;
f8c16bba
ZX		 4859 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4860
f8c16bba
ZX		 4861 if (kvm_x86_ops) {
4862 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 4863 r = -EEXIST;
4864 goto out;
f8c16bba
ZX		 4865 }
4866
4867 if (!ops->cpu_has_kvm_support()) {
4868 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 4869 r = -EOPNOTSUPP;
4870 goto out;
f8c16bba
ZX		 4871 }
4872 if (ops->disabled_by_bios()) {
4873 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 4874 r = -EOPNOTSUPP;
4875 goto out;
f8c16bba
ZX		 4876 }
4877
97db56ce
AK		 4878 r = kvm_mmu_module_init();
4879 if (r)
4880 goto out;
4881
ce88decf 4882 kvm_set_mmio_spte_mask();
97db56ce
AK		 4883 kvm_init_msr_list();
4884
f8c16bba 4885 kvm_x86_ops = ops;
7b52345e 4886 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 4887 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 4888
b820cc0c 4889 kvm_timer_init();
c8076604 4890
ff9d07a0
ZY		 4891 perf_register_guest_info_callbacks(&kvm_guest_cbs);
4892
2acf923e
DC		 4893 if (cpu_has_xsave)
4894 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
4895
f8c16bba 4896 return 0;
56c6d28a
ZX		 4897
4898out:
56c6d28a 4899 return r;
043405e1 4900}
8776e519 4901
f8c16bba
ZX		 4902void kvm_arch_exit(void)
4903{
ff9d07a0
ZY		 4904 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4905
888d256e
JK		 4906 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4907 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4908 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 4909 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
f8c16bba 4910 kvm_x86_ops = NULL;
56c6d28a
ZX		 4911 kvm_mmu_module_exit();
4912}
f8c16bba 4913
8776e519
HB		 4914int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4915{
4916 ++vcpu->stat.halt_exits;
4917 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 4918 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 4919 return 1;
4920 } else {
4921 vcpu->run->exit_reason = KVM_EXIT_HLT;
4922 return 0;
4923 }
4924}
4925EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4926
55cd8e5a
GN		 4927int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
4928{
4929 u64 param, ingpa, outgpa, ret;
4930 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
4931 bool fast, longmode;
4932 int cs_db, cs_l;
4933
4934 /*
4935 * hypercall generates UD from non zero cpl and real mode
4936 * per HYPER-V spec
4937 */
3eeb3288 4938 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 4939 kvm_queue_exception(vcpu, UD_VECTOR);
4940 return 0;
4941 }
4942
4943 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4944 longmode = is_long_mode(vcpu) && cs_l == 1;
4945
4946 if (!longmode) {
ccd46936
GN		 4947 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
4948 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
4949 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
4950 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
4951 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
4952 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 4953 }
4954#ifdef CONFIG_X86_64
4955 else {
4956 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
4957 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
4958 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
4959 }
4960#endif
4961
4962 code = param & 0xffff;
4963 fast = (param >> 16) & 0x1;
4964 rep_cnt = (param >> 32) & 0xfff;
4965 rep_idx = (param >> 48) & 0xfff;
4966
4967 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
4968
c25bc163
GN		 4969 switch (code) {
4970 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
4971 kvm_vcpu_on_spin(vcpu);
4972 break;
4973 default:
4974 res = HV_STATUS_INVALID_HYPERCALL_CODE;
4975 break;
4976 }
55cd8e5a
GN		 4977
4978 ret = res | (((u64)rep_done & 0xfff) << 32);
4979 if (longmode) {
4980 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
4981 } else {
4982 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
4983 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
4984 }
4985
4986 return 1;
4987}
4988
8776e519
HB		 4989int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
4990{
4991 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 4992 int r = 1;
8776e519 4993
55cd8e5a
GN		 4994 if (kvm_hv_hypercall_enabled(vcpu->kvm))
4995 return kvm_hv_hypercall(vcpu);
4996
5fdbf976
MT		 4997 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
4998 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
4999 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5000 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5001 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5002
229456fc 5003 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5004
8776e519
HB		 5005 if (!is_long_mode(vcpu)) {
5006 nr &= 0xFFFFFFFF;
5007 a0 &= 0xFFFFFFFF;
5008 a1 &= 0xFFFFFFFF;
5009 a2 &= 0xFFFFFFFF;
5010 a3 &= 0xFFFFFFFF;
5011 }
5012
07708c4a
JK		 5013 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5014 ret = -KVM_EPERM;
5015 goto out;
5016 }
5017
8776e519 5018 switch (nr) {
b93463aa
AK		 5019 case KVM_HC_VAPIC_POLL_IRQ:
5020 ret = 0;
5021 break;
8776e519
HB		 5022 default:
5023 ret = -KVM_ENOSYS;
5024 break;
5025 }
07708c4a 5026out:
5fdbf976 5027 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5028 ++vcpu->stat.hypercalls;
2f333bcb 5029 return r;
8776e519
HB		 5030}
5031EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5032
d6aa1000 5033int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5034{
d6aa1000 5035 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5036 char instruction[3];
5fdbf976 5037 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5038
8776e519
HB		 5039 /*
5040 * Blow out the MMU to ensure that no other VCPU has an active mapping
5041 * to ensure that the updated hypercall appears atomically across all
5042 * VCPUs.
5043 */
5044 kvm_mmu_zap_all(vcpu->kvm);
5045
8776e519 5046 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5047
9d74191a 5048 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5049}
5050
b6c7a5dc
HB		 5051/*
5052 * Check if userspace requested an interrupt window, and that the
5053 * interrupt window is open.
5054 *
5055 * No need to exit to userspace if we already have an interrupt queued.
5056 */
851ba692 5057static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5058{
8061823a 5059 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5060 vcpu->run->request_interrupt_window &&
5df56646 5061 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5062}
5063
851ba692 5064static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5065{
851ba692
AK		 5066 struct kvm_run *kvm_run = vcpu->run;
5067
91586a3b 5068 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5069 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5070 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5071 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5072 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5073 else
b6c7a5dc 5074 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5075 kvm_arch_interrupt_allowed(vcpu) &&
5076 !kvm_cpu_has_interrupt(vcpu) &&
5077 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5078}
5079
b93463aa
AK		 5080static void vapic_enter(struct kvm_vcpu *vcpu)
5081{
5082 struct kvm_lapic *apic = vcpu->arch.apic;
5083 struct page *page;
5084
5085 if (!apic || !apic->vapic_addr)
5086 return;
5087
5088 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 5089
5090 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 5091}
5092
5093static void vapic_exit(struct kvm_vcpu *vcpu)
5094{
5095 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 5096 int idx;
b93463aa
AK		 5097
5098 if (!apic || !apic->vapic_addr)
5099 return;
5100
f656ce01 5101 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 5102 kvm_release_page_dirty(apic->vapic_page);
5103 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 5104 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 5105}
5106
95ba8273
GN		 5107static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5108{
5109 int max_irr, tpr;
5110
5111 if (!kvm_x86_ops->update_cr8_intercept)
5112 return;
5113
88c808fd
AK		 5114 if (!vcpu->arch.apic)
5115 return;
5116
8db3baa2
GN		 5117 if (!vcpu->arch.apic->vapic_addr)
5118 max_irr = kvm_lapic_find_highest_irr(vcpu);
5119 else
5120 max_irr = -1;
95ba8273
GN		 5121
5122 if (max_irr != -1)
5123 max_irr >>= 4;
5124
5125 tpr = kvm_lapic_get_cr8(vcpu);
5126
5127 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5128}
5129
851ba692 5130static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 5131{
5132 /* try to reinject previous events if any */
b59bb7bd 5133 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5134 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5135 vcpu->arch.exception.has_error_code,
5136 vcpu->arch.exception.error_code);
b59bb7bd
GN		 5137 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5138 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5139 vcpu->arch.exception.error_code,
5140 vcpu->arch.exception.reinject);
b59bb7bd
GN		 5141 return;
5142 }
5143
95ba8273
GN		 5144 if (vcpu->arch.nmi_injected) {
5145 kvm_x86_ops->set_nmi(vcpu);
5146 return;
5147 }
5148
5149 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5150 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5151 return;
5152 }
5153
5154 /* try to inject new event if pending */
5155 if (vcpu->arch.nmi_pending) {
5156 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 5157 --vcpu->arch.nmi_pending;
95ba8273
GN		 5158 vcpu->arch.nmi_injected = true;
5159 kvm_x86_ops->set_nmi(vcpu);
5160 }
5161 } else if (kvm_cpu_has_interrupt(vcpu)) {
5162 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5163 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5164 false);
5165 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5166 }
5167 }
5168}
5169
2acf923e
DC		 5170static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
5171{
5172 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
5173 !vcpu->guest_xcr0_loaded) {
5174 /* kvm_set_xcr() also depends on this */
5175 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
5176 vcpu->guest_xcr0_loaded = 1;
5177 }
5178}
5179
5180static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
5181{
5182 if (vcpu->guest_xcr0_loaded) {
5183 if (vcpu->arch.xcr0 != host_xcr0)
5184 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
5185 vcpu->guest_xcr0_loaded = 0;
5186 }
5187}
5188
7460fb4a
AK		 5189static void process_nmi(struct kvm_vcpu *vcpu)
5190{
5191 unsigned limit = 2;
5192
5193 /*
5194 * x86 is limited to one NMI running, and one NMI pending after it.
5195 * If an NMI is already in progress, limit further NMIs to just one.
5196 * Otherwise, allow two (and we'll inject the first one immediately).
5197 */
5198 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5199 limit = 1;
5200
5201 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5202 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5203 kvm_make_request(KVM_REQ_EVENT, vcpu);
5204}
5205
851ba692 5206static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5207{
5208 int r;
6a8b1d13 5209 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5210 vcpu->run->request_interrupt_window;
d6185f20 5211 bool req_immediate_exit = 0;
b6c7a5dc 5212
3e007509 5213 if (vcpu->requests) {
a8eeb04a 5214 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5215 kvm_mmu_unload(vcpu);
a8eeb04a 5216 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5217 __kvm_migrate_timers(vcpu);
34c238a1
ZA		 5218 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5219 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 5220 if (unlikely(r))
5221 goto out;
5222 }
a8eeb04a 5223 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5224 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5225 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5226 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5227 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5228 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5229 r = 0;
5230 goto out;
5231 }
a8eeb04a 5232 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5233 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5234 r = 0;
5235 goto out;
5236 }
a8eeb04a 5237 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5238 vcpu->fpu_active = 0;
5239 kvm_x86_ops->fpu_deactivate(vcpu);
5240 }
af585b92
GN		 5241 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5242 /* Page is swapped out. Do synthetic halt */
5243 vcpu->arch.apf.halted = true;
5244 r = 1;
5245 goto out;
5246 }
c9aaa895
GC		 5247 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5248 record_steal_time(vcpu);
7460fb4a
AK		 5249 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5250 process_nmi(vcpu);
d6185f20
NHE		 5251 req_immediate_exit =
5252 kvm_check_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
f5132b01
GN		 5253 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5254 kvm_handle_pmu_event(vcpu);
5255 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5256 kvm_deliver_pmi(vcpu);
2f52d58c 5257 }
b93463aa 5258
3e007509
AK		 5259 r = kvm_mmu_reload(vcpu);
5260 if (unlikely(r))
5261 goto out;
5262
b463a6f7
AK		 5263 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5264 inject_pending_event(vcpu);
5265
5266 /* enable NMI/IRQ window open exits if needed */
7460fb4a 5267 if (vcpu->arch.nmi_pending)
b463a6f7
AK		 5268 kvm_x86_ops->enable_nmi_window(vcpu);
5269 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
5270 kvm_x86_ops->enable_irq_window(vcpu);
5271
5272 if (kvm_lapic_enabled(vcpu)) {
5273 update_cr8_intercept(vcpu);
5274 kvm_lapic_sync_to_vapic(vcpu);
5275 }
5276 }
5277
b6c7a5dc
HB		 5278 preempt_disable();
5279
5280 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 5281 if (vcpu->fpu_active)
5282 kvm_load_guest_fpu(vcpu);
2acf923e 5283 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 5284
6b7e2d09
XG		 5285 vcpu->mode = IN_GUEST_MODE;
5286
5287 /* We should set ->mode before check ->requests,
5288 * see the comment in make_all_cpus_request.
5289 */
5290 smp_mb();
b6c7a5dc 5291
d94e1dc9 5292 local_irq_disable();
32f88400 5293
6b7e2d09 5294 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 5295 || need_resched() || signal_pending(current)) {
6b7e2d09 5296 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5297 smp_wmb();
6c142801
AK		 5298 local_irq_enable();
5299 preempt_enable();
b463a6f7 5300 kvm_x86_ops->cancel_injection(vcpu);
6c142801
AK		 5301 r = 1;
5302 goto out;
5303 }
5304
f656ce01 5305 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 5306
d6185f20
NHE		 5307 if (req_immediate_exit)
5308 smp_send_reschedule(vcpu->cpu);
5309
b6c7a5dc
HB		 5310 kvm_guest_enter();
5311
42dbaa5a 5312 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 5313 set_debugreg(0, 7);
5314 set_debugreg(vcpu->arch.eff_db[0], 0);
5315 set_debugreg(vcpu->arch.eff_db[1], 1);
5316 set_debugreg(vcpu->arch.eff_db[2], 2);
5317 set_debugreg(vcpu->arch.eff_db[3], 3);
5318 }
b6c7a5dc 5319
229456fc 5320 trace_kvm_entry(vcpu->vcpu_id);
851ba692 5321 kvm_x86_ops->run(vcpu);
b6c7a5dc 5322
24f1e32c
FW		 5323 /*
5324 * If the guest has used debug registers, at least dr7
5325 * will be disabled while returning to the host.
5326 * If we don't have active breakpoints in the host, we don't
5327 * care about the messed up debug address registers. But if
5328 * we have some of them active, restore the old state.
5329 */
59d8eb53 5330 if (hw_breakpoint_active())
24f1e32c 5331 hw_breakpoint_restore();
42dbaa5a 5332
d5c1785d 5333 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu);
1d5f066e 5334
6b7e2d09 5335 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5336 smp_wmb();
b6c7a5dc
HB		 5337 local_irq_enable();
5338
5339 ++vcpu->stat.exits;
5340
5341 /*
5342 * We must have an instruction between local_irq_enable() and
5343 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5344 * the interrupt shadow. The stat.exits increment will do nicely.
5345 * But we need to prevent reordering, hence this barrier():
5346 */
5347 barrier();
5348
5349 kvm_guest_exit();
5350
5351 preempt_enable();
5352
f656ce01 5353 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 5354
b6c7a5dc
HB		 5355 /*
5356 * Profile KVM exit RIPs:
5357 */
5358 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 5359 unsigned long rip = kvm_rip_read(vcpu);
5360 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 5361 }
5362
cc578287
ZA		 5363 if (unlikely(vcpu->arch.tsc_always_catchup))
5364 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 5365
b93463aa
AK		 5366 kvm_lapic_sync_from_vapic(vcpu);
5367
851ba692 5368 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 5369out:
5370 return r;
5371}
b6c7a5dc 5372
09cec754 5373
851ba692 5374static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 5375{
5376 int r;
f656ce01 5377 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 5378
5379 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 5380 pr_debug("vcpu %d received sipi with vector # %x\n",
5381 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 5382 kvm_lapic_reset(vcpu);
5f179287 5383 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 5384 if (r)
5385 return r;
5386 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 5387 }
5388
f656ce01 5389 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 5390 vapic_enter(vcpu);
5391
5392 r = 1;
5393 while (r > 0) {
af585b92
GN		 5394 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
5395 !vcpu->arch.apf.halted)
851ba692 5396 r = vcpu_enter_guest(vcpu);
d7690175 5397 else {
f656ce01 5398 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 5399 kvm_vcpu_block(vcpu);
f656ce01 5400 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
a8eeb04a 5401 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
09cec754
GN		 5402 {
5403 switch(vcpu->arch.mp_state) {
5404 case KVM_MP_STATE_HALTED:
d7690175 5405 vcpu->arch.mp_state =
09cec754
GN		 5406 KVM_MP_STATE_RUNNABLE;
5407 case KVM_MP_STATE_RUNNABLE:
af585b92 5408 vcpu->arch.apf.halted = false;
09cec754
GN		 5409 break;
5410 case KVM_MP_STATE_SIPI_RECEIVED:
5411 default:
5412 r = -EINTR;
5413 break;
5414 }
5415 }
d7690175
MT		 5416 }
5417
09cec754
GN		 5418 if (r <= 0)
5419 break;
5420
5421 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5422 if (kvm_cpu_has_pending_timer(vcpu))
5423 kvm_inject_pending_timer_irqs(vcpu);
5424
851ba692 5425 if (dm_request_for_irq_injection(vcpu)) {
09cec754 5426 r = -EINTR;
851ba692 5427 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5428 ++vcpu->stat.request_irq_exits;
5429 }
af585b92
GN		 5430
5431 kvm_check_async_pf_completion(vcpu);
5432
09cec754
GN		 5433 if (signal_pending(current)) {
5434 r = -EINTR;
851ba692 5435 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5436 ++vcpu->stat.signal_exits;
5437 }
5438 if (need_resched()) {
f656ce01 5439 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 5440 kvm_resched(vcpu);
f656ce01 5441 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 5442 }
b6c7a5dc
HB		 5443 }
5444
f656ce01 5445 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 5446
b93463aa
AK		 5447 vapic_exit(vcpu);
5448
b6c7a5dc
HB		 5449 return r;
5450}
5451
5287f194
AK		 5452static int complete_mmio(struct kvm_vcpu *vcpu)
5453{
5454 struct kvm_run *run = vcpu->run;
5455 int r;
5456
5457 if (!(vcpu->arch.pio.count || vcpu->mmio_needed))
5458 return 1;
5459
5460 if (vcpu->mmio_needed) {
5287f194 5461 vcpu->mmio_needed = 0;
cef4dea0 5462 if (!vcpu->mmio_is_write)
0004c7c2
GN		 5463 memcpy(vcpu->mmio_data + vcpu->mmio_index,
5464 run->mmio.data, 8);
cef4dea0
AK		 5465 vcpu->mmio_index += 8;
5466 if (vcpu->mmio_index < vcpu->mmio_size) {
5467 run->exit_reason = KVM_EXIT_MMIO;
5468 run->mmio.phys_addr = vcpu->mmio_phys_addr + vcpu->mmio_index;
5469 memcpy(run->mmio.data, vcpu->mmio_data + vcpu->mmio_index, 8);
5470 run->mmio.len = min(vcpu->mmio_size - vcpu->mmio_index, 8);
5471 run->mmio.is_write = vcpu->mmio_is_write;
5472 vcpu->mmio_needed = 1;
5473 return 0;
5474 }
5475 if (vcpu->mmio_is_write)
5476 return 1;
5477 vcpu->mmio_read_completed = 1;
5287f194
AK		 5478 }
5479 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5480 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
5481 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5482 if (r != EMULATE_DONE)
5483 return 0;
5484 return 1;
5485}
5486
b6c7a5dc
HB		 5487int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
5488{
5489 int r;
5490 sigset_t sigsaved;
5491
e5c30142
AK		 5492 if (!tsk_used_math(current) && init_fpu(current))
5493 return -ENOMEM;
5494
ac9f6dc0
AK		 5495 if (vcpu->sigset_active)
5496 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
5497
a4535290 5498 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 5499 kvm_vcpu_block(vcpu);
d7690175 5500 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 5501 r = -EAGAIN;
5502 goto out;
b6c7a5dc
HB		 5503 }
5504
b6c7a5dc 5505 /* re-sync apic's tpr */
eea1cff9
AP		 5506 if (!irqchip_in_kernel(vcpu->kvm)) {
5507 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
5508 r = -EINVAL;
5509 goto out;
5510 }
5511 }
b6c7a5dc 5512
5287f194
AK		 5513 r = complete_mmio(vcpu);
5514 if (r <= 0)
5515 goto out;
5516
851ba692 5517 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 5518
5519out:
f1d86e46 5520 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 5521 if (vcpu->sigset_active)
5522 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
5523
b6c7a5dc
HB		 5524 return r;
5525}
5526
5527int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5528{
7ae441ea
GN		 5529 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
5530 /*
5531 * We are here if userspace calls get_regs() in the middle of
5532 * instruction emulation. Registers state needs to be copied
5533 * back from emulation context to vcpu. Usrapace shouldn't do
5534 * that usually, but some bad designed PV devices (vmware
5535 * backdoor interface) need this to work
5536 */
9dac77fa
AK		 5537 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
5538 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
7ae441ea
GN		 5539 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5540 }
5fdbf976
MT		 5541 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5542 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5543 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5544 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5545 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
5546 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
5547 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5548 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 5549#ifdef CONFIG_X86_64
5fdbf976
MT		 5550 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
5551 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
5552 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
5553 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
5554 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
5555 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
5556 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
5557 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 5558#endif
5559
5fdbf976 5560 regs->rip = kvm_rip_read(vcpu);
91586a3b 5561 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 5562
b6c7a5dc
HB		 5563 return 0;
5564}
5565
5566int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5567{
7ae441ea
GN		 5568 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
5569 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5570
5fdbf976
MT		 5571 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
5572 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
5573 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
5574 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
5575 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
5576 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
5577 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
5578 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 5579#ifdef CONFIG_X86_64
5fdbf976
MT		 5580 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
5581 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
5582 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
5583 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
5584 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
5585 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
5586 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
5587 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 5588#endif
5589
5fdbf976 5590 kvm_rip_write(vcpu, regs->rip);
91586a3b 5591 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 5592
b4f14abd
JK		 5593 vcpu->arch.exception.pending = false;
5594
3842d135
AK		 5595 kvm_make_request(KVM_REQ_EVENT, vcpu);
5596
b6c7a5dc
HB		 5597 return 0;
5598}
5599
b6c7a5dc
HB		 5600void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5601{
5602 struct kvm_segment cs;
5603
3e6e0aab 5604 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 5605 *db = cs.db;
5606 *l = cs.l;
5607}
5608EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
5609
5610int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
5611 struct kvm_sregs *sregs)
5612{
89a27f4d 5613 struct desc_ptr dt;
b6c7a5dc 5614
3e6e0aab
GT		 5615 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5616 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5617 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5618 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5619 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5620 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5621
3e6e0aab
GT		 5622 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5623 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 5624
5625 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 5626 sregs->idt.limit = dt.size;
5627 sregs->idt.base = dt.address;
b6c7a5dc 5628 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 5629 sregs->gdt.limit = dt.size;
5630 sregs->gdt.base = dt.address;
b6c7a5dc 5631
4d4ec087 5632 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 5633 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 5634 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 5635 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 5636 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 5637 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 5638 sregs->apic_base = kvm_get_apic_base(vcpu);
5639
923c61bb 5640 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 5641
36752c9b 5642 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 5643 set_bit(vcpu->arch.interrupt.nr,
5644 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 5645
b6c7a5dc
HB		 5646 return 0;
5647}
5648
62d9f0db
MT		 5649int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
5650 struct kvm_mp_state *mp_state)
5651{
62d9f0db 5652 mp_state->mp_state = vcpu->arch.mp_state;
62d9f0db
MT		 5653 return 0;
5654}
5655
5656int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
5657 struct kvm_mp_state *mp_state)
5658{
62d9f0db 5659 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 5660 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 5661 return 0;
5662}
5663
7f3d35fd
KW		 5664int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
5665 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 5666{
9d74191a 5667 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 5668 int ret;
e01c2426 5669
8ec4722d 5670 init_emulate_ctxt(vcpu);
c697518a 5671
7f3d35fd 5672 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 5673 has_error_code, error_code);
c697518a 5674
c697518a 5675 if (ret)
19d04437 5676 return EMULATE_FAIL;
37817f29 5677
9dac77fa 5678 memcpy(vcpu->arch.regs, ctxt->regs, sizeof ctxt->regs);
9d74191a
TY		 5679 kvm_rip_write(vcpu, ctxt->eip);
5680 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 5681 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 5682 return EMULATE_DONE;
37817f29
IE		 5683}
5684EXPORT_SYMBOL_GPL(kvm_task_switch);
5685
b6c7a5dc
HB		 5686int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5687 struct kvm_sregs *sregs)
5688{
5689 int mmu_reset_needed = 0;
63f42e02 5690 int pending_vec, max_bits, idx;
89a27f4d 5691 struct desc_ptr dt;
b6c7a5dc 5692
89a27f4d
GN		 5693 dt.size = sregs->idt.limit;
5694 dt.address = sregs->idt.base;
b6c7a5dc 5695 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 5696 dt.size = sregs->gdt.limit;
5697 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 5698 kvm_x86_ops->set_gdt(vcpu, &dt);
5699
ad312c7c 5700 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 5701 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 5702 vcpu->arch.cr3 = sregs->cr3;
aff48baa 5703 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 5704
2d3ad1f4 5705 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 5706
f6801dff 5707 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 5708 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 5709 kvm_set_apic_base(vcpu, sregs->apic_base);
5710
4d4ec087 5711 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 5712 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 5713 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 5714
fc78f519 5715 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 5716 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 5717 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 5718 kvm_update_cpuid(vcpu);
63f42e02
XG		 5719
5720 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 5721 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 5722 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 5723 mmu_reset_needed = 1;
5724 }
63f42e02 5725 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 5726
5727 if (mmu_reset_needed)
5728 kvm_mmu_reset_context(vcpu);
5729
923c61bb
GN		 5730 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5731 pending_vec = find_first_bit(
5732 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5733 if (pending_vec < max_bits) {
66fd3f7f 5734 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 5735 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 5736 }
5737
3e6e0aab
GT		 5738 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5739 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5740 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5741 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5742 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5743 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5744
3e6e0aab
GT		 5745 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5746 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 5747
5f0269f5
ME		 5748 update_cr8_intercept(vcpu);
5749
9c3e4aab 5750 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 5751 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 5752 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 5753 !is_protmode(vcpu))
9c3e4aab
MT		 5754 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5755
3842d135
AK		 5756 kvm_make_request(KVM_REQ_EVENT, vcpu);
5757
b6c7a5dc
HB		 5758 return 0;
5759}
5760
d0bfb940
JK		 5761int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5762 struct kvm_guest_debug *dbg)
b6c7a5dc 5763{
355be0b9 5764 unsigned long rflags;
ae675ef0 5765 int i, r;
b6c7a5dc 5766
4f926bf2
JK		 5767 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5768 r = -EBUSY;
5769 if (vcpu->arch.exception.pending)
2122ff5e 5770 goto out;
4f926bf2
JK		 5771 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5772 kvm_queue_exception(vcpu, DB_VECTOR);
5773 else
5774 kvm_queue_exception(vcpu, BP_VECTOR);
5775 }
5776
91586a3b
JK		 5777 /*
5778 * Read rflags as long as potentially injected trace flags are still
5779 * filtered out.
5780 */
5781 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 5782
5783 vcpu->guest_debug = dbg->control;
5784 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5785 vcpu->guest_debug = 0;
5786
5787 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 5788 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5789 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5790 vcpu->arch.switch_db_regs =
5791 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5792 } else {
5793 for (i = 0; i < KVM_NR_DB_REGS; i++)
5794 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5795 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5796 }
5797
f92653ee
JK		 5798 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5799 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5800 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 5801
91586a3b
JK		 5802 /*
5803 * Trigger an rflags update that will inject or remove the trace
5804 * flags.
5805 */
5806 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 5807
355be0b9 5808 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 5809
4f926bf2 5810 r = 0;
d0bfb940 5811
2122ff5e 5812out:
b6c7a5dc
HB		 5813
5814 return r;
5815}
5816
8b006791
ZX		 5817/*
5818 * Translate a guest virtual address to a guest physical address.
5819 */
5820int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5821 struct kvm_translation *tr)
5822{
5823 unsigned long vaddr = tr->linear_address;
5824 gpa_t gpa;
f656ce01 5825 int idx;
8b006791 5826
f656ce01 5827 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 5828 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 5829 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 5830 tr->physical_address = gpa;
5831 tr->valid = gpa != UNMAPPED_GVA;
5832 tr->writeable = 1;
5833 tr->usermode = 0;
8b006791
ZX		 5834
5835 return 0;
5836}
5837
d0752060
HB		 5838int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5839{
98918833
SY		 5840 struct i387_fxsave_struct *fxsave =
5841 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5842
d0752060
HB		 5843 memcpy(fpu->fpr, fxsave->st_space, 128);
5844 fpu->fcw = fxsave->cwd;
5845 fpu->fsw = fxsave->swd;
5846 fpu->ftwx = fxsave->twd;
5847 fpu->last_opcode = fxsave->fop;
5848 fpu->last_ip = fxsave->rip;
5849 fpu->last_dp = fxsave->rdp;
5850 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5851
d0752060
HB		 5852 return 0;
5853}
5854
5855int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5856{
98918833
SY		 5857 struct i387_fxsave_struct *fxsave =
5858 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5859
d0752060
HB		 5860 memcpy(fxsave->st_space, fpu->fpr, 128);
5861 fxsave->cwd = fpu->fcw;
5862 fxsave->swd = fpu->fsw;
5863 fxsave->twd = fpu->ftwx;
5864 fxsave->fop = fpu->last_opcode;
5865 fxsave->rip = fpu->last_ip;
5866 fxsave->rdp = fpu->last_dp;
5867 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5868
d0752060
HB		 5869 return 0;
5870}
5871
10ab25cd 5872int fx_init(struct kvm_vcpu *vcpu)
d0752060 5873{
10ab25cd
JK		 5874 int err;
5875
5876 err = fpu_alloc(&vcpu->arch.guest_fpu);
5877 if (err)
5878 return err;
5879
98918833 5880 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 5881
2acf923e
DC		 5882 /*
5883 * Ensure guest xcr0 is valid for loading
5884 */
5885 vcpu->arch.xcr0 = XSTATE_FP;
5886
ad312c7c 5887 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 5888
5889 return 0;
d0752060
HB		 5890}
5891EXPORT_SYMBOL_GPL(fx_init);
5892
98918833
SY		 5893static void fx_free(struct kvm_vcpu *vcpu)
5894{
5895 fpu_free(&vcpu->arch.guest_fpu);
5896}
5897
d0752060
HB		 5898void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5899{
2608d7a1 5900 if (vcpu->guest_fpu_loaded)
d0752060
HB		 5901 return;
5902
2acf923e
DC		 5903 /*
5904 * Restore all possible states in the guest,
5905 * and assume host would use all available bits.
5906 * Guest xcr0 would be loaded later.
5907 */
5908 kvm_put_guest_xcr0(vcpu);
d0752060 5909 vcpu->guest_fpu_loaded = 1;
7cf30855 5910 unlazy_fpu(current);
98918833 5911 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 5912 trace_kvm_fpu(1);
d0752060 5913}
d0752060
HB		 5914
5915void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5916{
2acf923e
DC		 5917 kvm_put_guest_xcr0(vcpu);
5918
d0752060
HB		 5919 if (!vcpu->guest_fpu_loaded)
5920 return;
5921
5922 vcpu->guest_fpu_loaded = 0;
98918833 5923 fpu_save_init(&vcpu->arch.guest_fpu);
f096ed85 5924 ++vcpu->stat.fpu_reload;
a8eeb04a 5925 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 5926 trace_kvm_fpu(0);
d0752060 5927}
e9b11c17
ZX		 5928
5929void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
5930{
12f9a48f 5931 kvmclock_reset(vcpu);
7f1ea208 5932
f5f48ee1 5933 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 5934 fx_free(vcpu);
e9b11c17
ZX		 5935 kvm_x86_ops->vcpu_free(vcpu);
5936}
5937
5938struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
5939 unsigned int id)
5940{
6755bae8
ZA		 5941 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
5942 printk_once(KERN_WARNING
5943 "kvm: SMP vm created on host with unstable TSC; "
5944 "guest TSC will not be reliable\n");
26e5215f
AK		 5945 return kvm_x86_ops->vcpu_create(kvm, id);
5946}
e9b11c17 5947
26e5215f
AK		 5948int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
5949{
5950 int r;
e9b11c17 5951
0bed3b56 5952 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 5953 vcpu_load(vcpu);
5954 r = kvm_arch_vcpu_reset(vcpu);
5955 if (r == 0)
5956 r = kvm_mmu_setup(vcpu);
5957 vcpu_put(vcpu);
e9b11c17 5958
26e5215f 5959 return r;
e9b11c17
ZX		 5960}
5961
d40ccc62 5962void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 5963{
344d9588
GN		 5964 vcpu->arch.apf.msr_val = 0;
5965
e9b11c17
ZX		 5966 vcpu_load(vcpu);
5967 kvm_mmu_unload(vcpu);
5968 vcpu_put(vcpu);
5969
98918833 5970 fx_free(vcpu);
e9b11c17
ZX		 5971 kvm_x86_ops->vcpu_free(vcpu);
5972}
5973
5974int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
5975{
7460fb4a
AK		 5976 atomic_set(&vcpu->arch.nmi_queued, 0);
5977 vcpu->arch.nmi_pending = 0;
448fa4a9
JK		 5978 vcpu->arch.nmi_injected = false;
5979
42dbaa5a
JK		 5980 vcpu->arch.switch_db_regs = 0;
5981 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
5982 vcpu->arch.dr6 = DR6_FIXED_1;
5983 vcpu->arch.dr7 = DR7_FIXED_1;
5984
3842d135 5985 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 5986 vcpu->arch.apf.msr_val = 0;
c9aaa895 5987 vcpu->arch.st.msr_val = 0;
3842d135 5988
12f9a48f
GC		 5989 kvmclock_reset(vcpu);
5990
af585b92
GN		 5991 kvm_clear_async_pf_completion_queue(vcpu);
5992 kvm_async_pf_hash_reset(vcpu);
5993 vcpu->arch.apf.halted = false;
3842d135 5994
f5132b01
GN		 5995 kvm_pmu_reset(vcpu);
5996
e9b11c17
ZX		 5997 return kvm_x86_ops->vcpu_reset(vcpu);
5998}
5999
10474ae8 6000int kvm_arch_hardware_enable(void *garbage)
e9b11c17 6001{
ca84d1a2
ZA		 6002 struct kvm *kvm;
6003 struct kvm_vcpu *vcpu;
6004 int i;
0dd6a6ed
ZA		 6005 int ret;
6006 u64 local_tsc;
6007 u64 max_tsc = 0;
6008 bool stable, backwards_tsc = false;
18863bdd
AK		 6009
6010 kvm_shared_msr_cpu_online();
0dd6a6ed
ZA		 6011 ret = kvm_x86_ops->hardware_enable(garbage);
6012 if (ret != 0)
6013 return ret;
6014
6015 local_tsc = native_read_tsc();
6016 stable = !check_tsc_unstable();
6017 list_for_each_entry(kvm, &vm_list, vm_list) {
6018 kvm_for_each_vcpu(i, vcpu, kvm) {
6019 if (!stable && vcpu->cpu == smp_processor_id())
6020 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6021 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6022 backwards_tsc = true;
6023 if (vcpu->arch.last_host_tsc > max_tsc)
6024 max_tsc = vcpu->arch.last_host_tsc;
6025 }
6026 }
6027 }
6028
6029 /*
6030 * Sometimes, even reliable TSCs go backwards. This happens on
6031 * platforms that reset TSC during suspend or hibernate actions, but
6032 * maintain synchronization. We must compensate. Fortunately, we can
6033 * detect that condition here, which happens early in CPU bringup,
6034 * before any KVM threads can be running. Unfortunately, we can't
6035 * bring the TSCs fully up to date with real time, as we aren't yet far
6036 * enough into CPU bringup that we know how much real time has actually
6037 * elapsed; our helper function, get_kernel_ns() will be using boot
6038 * variables that haven't been updated yet.
6039 *
6040 * So we simply find the maximum observed TSC above, then record the
6041 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
6042 * the adjustment will be applied. Note that we accumulate
6043 * adjustments, in case multiple suspend cycles happen before some VCPU
6044 * gets a chance to run again. In the event that no KVM threads get a
6045 * chance to run, we will miss the entire elapsed period, as we'll have
6046 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6047 * loose cycle time. This isn't too big a deal, since the loss will be
6048 * uniform across all VCPUs (not to mention the scenario is extremely
6049 * unlikely). It is possible that a second hibernate recovery happens
6050 * much faster than a first, causing the observed TSC here to be
6051 * smaller; this would require additional padding adjustment, which is
6052 * why we set last_host_tsc to the local tsc observed here.
6053 *
6054 * N.B. - this code below runs only on platforms with reliable TSC,
6055 * as that is the only way backwards_tsc is set above. Also note
6056 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
6057 * have the same delta_cyc adjustment applied if backwards_tsc
6058 * is detected. Note further, this adjustment is only done once,
6059 * as we reset last_host_tsc on all VCPUs to stop this from being
6060 * called multiple times (one for each physical CPU bringup).
6061 *
6062 * Platforms with unnreliable TSCs don't have to deal with this, they
6063 * will be compensated by the logic in vcpu_load, which sets the TSC to
6064 * catchup mode. This will catchup all VCPUs to real time, but cannot
6065 * guarantee that they stay in perfect synchronization.
6066 */
6067 if (backwards_tsc) {
6068 u64 delta_cyc = max_tsc - local_tsc;
6069 list_for_each_entry(kvm, &vm_list, vm_list) {
6070 kvm_for_each_vcpu(i, vcpu, kvm) {
6071 vcpu->arch.tsc_offset_adjustment += delta_cyc;
6072 vcpu->arch.last_host_tsc = local_tsc;
6073 }
6074
6075 /*
6076 * We have to disable TSC offset matching.. if you were
6077 * booting a VM while issuing an S4 host suspend....
6078 * you may have some problem. Solving this issue is
6079 * left as an exercise to the reader.
6080 */
6081 kvm->arch.last_tsc_nsec = 0;
6082 kvm->arch.last_tsc_write = 0;
6083 }
6084
6085 }
6086 return 0;
e9b11c17
ZX		 6087}
6088
6089void kvm_arch_hardware_disable(void *garbage)
6090{
6091 kvm_x86_ops->hardware_disable(garbage);
3548bab5 6092 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 6093}
6094
6095int kvm_arch_hardware_setup(void)
6096{
6097 return kvm_x86_ops->hardware_setup();
6098}
6099
6100void kvm_arch_hardware_unsetup(void)
6101{
6102 kvm_x86_ops->hardware_unsetup();
6103}
6104
6105void kvm_arch_check_processor_compat(void *rtn)
6106{
6107 kvm_x86_ops->check_processor_compatibility(rtn);
6108}
6109
6110int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6111{
6112 struct page *page;
6113 struct kvm *kvm;
6114 int r;
6115
6116 BUG_ON(vcpu->kvm == NULL);
6117 kvm = vcpu->kvm;
6118
9aabc88f 6119 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
c5af89b6 6120 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 6121 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 6122 else
a4535290 6123 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 6124
6125 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6126 if (!page) {
6127 r = -ENOMEM;
6128 goto fail;
6129 }
ad312c7c 6130 vcpu->arch.pio_data = page_address(page);
e9b11c17 6131
cc578287 6132 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 6133
e9b11c17
ZX		 6134 r = kvm_mmu_create(vcpu);
6135 if (r < 0)
6136 goto fail_free_pio_data;
6137
6138 if (irqchip_in_kernel(kvm)) {
6139 r = kvm_create_lapic(vcpu);
6140 if (r < 0)
6141 goto fail_mmu_destroy;
6142 }
6143
890ca9ae
HY		 6144 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6145 GFP_KERNEL);
6146 if (!vcpu->arch.mce_banks) {
6147 r = -ENOMEM;
443c39bc 6148 goto fail_free_lapic;
890ca9ae
HY		 6149 }
6150 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6151
f5f48ee1
SY		 6152 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
6153 goto fail_free_mce_banks;
6154
af585b92 6155 kvm_async_pf_hash_reset(vcpu);
f5132b01 6156 kvm_pmu_init(vcpu);
af585b92 6157
e9b11c17 6158 return 0;
f5f48ee1
SY		 6159fail_free_mce_banks:
6160 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 6161fail_free_lapic:
6162 kvm_free_lapic(vcpu);
e9b11c17
ZX		 6163fail_mmu_destroy:
6164 kvm_mmu_destroy(vcpu);
6165fail_free_pio_data:
ad312c7c 6166 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 6167fail:
6168 return r;
6169}
6170
6171void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6172{
f656ce01
MT		 6173 int idx;
6174
f5132b01 6175 kvm_pmu_destroy(vcpu);
36cb93fd 6176 kfree(vcpu->arch.mce_banks);
e9b11c17 6177 kvm_free_lapic(vcpu);
f656ce01 6178 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 6179 kvm_mmu_destroy(vcpu);
f656ce01 6180 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 6181 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 6182}
d19a9cd2 6183
e08b9637 6184int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 6185{
e08b9637
CO		 6186 if (type)
6187 return -EINVAL;
6188
f05e70ac 6189 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 6190 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 6191
5550af4d
SY		 6192 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
6193 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
6194
038f8c11 6195 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
53f658b3 6196
d89f5eff 6197 return 0;
d19a9cd2
ZX		 6198}
6199
6200static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
6201{
6202 vcpu_load(vcpu);
6203 kvm_mmu_unload(vcpu);
6204 vcpu_put(vcpu);
6205}
6206
6207static void kvm_free_vcpus(struct kvm *kvm)
6208{
6209 unsigned int i;
988a2cae 6210 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 6211
6212 /*
6213 * Unpin any mmu pages first.
6214 */
af585b92
GN		 6215 kvm_for_each_vcpu(i, vcpu, kvm) {
6216 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 6217 kvm_unload_vcpu_mmu(vcpu);
af585b92 6218 }
988a2cae
GN		 6219 kvm_for_each_vcpu(i, vcpu, kvm)
6220 kvm_arch_vcpu_free(vcpu);
6221
6222 mutex_lock(&kvm->lock);
6223 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
6224 kvm->vcpus[i] = NULL;
d19a9cd2 6225
988a2cae
GN		 6226 atomic_set(&kvm->online_vcpus, 0);
6227 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 6228}
6229
ad8ba2cd
SY		 6230void kvm_arch_sync_events(struct kvm *kvm)
6231{
ba4cef31 6232 kvm_free_all_assigned_devices(kvm);
aea924f6 6233 kvm_free_pit(kvm);
ad8ba2cd
SY		 6234}
6235
d19a9cd2
ZX		 6236void kvm_arch_destroy_vm(struct kvm *kvm)
6237{
6eb55818 6238 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 6239 kfree(kvm->arch.vpic);
6240 kfree(kvm->arch.vioapic);
d19a9cd2 6241 kvm_free_vcpus(kvm);
3d45830c
AK		 6242 if (kvm->arch.apic_access_page)
6243 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 6244 if (kvm->arch.ept_identity_pagetable)
6245 put_page(kvm->arch.ept_identity_pagetable);
d19a9cd2 6246}
0de10343 6247
db3fe4eb
TY		 6248void kvm_arch_free_memslot(struct kvm_memory_slot *free,
6249 struct kvm_memory_slot *dont)
6250{
6251 int i;
6252
6253 for (i = 0; i < KVM_NR_PAGE_SIZES - 1; ++i) {
6254 if (!dont || free->arch.lpage_info[i] != dont->arch.lpage_info[i]) {
6255 vfree(free->arch.lpage_info[i]);
6256 free->arch.lpage_info[i] = NULL;
6257 }
6258 }
6259}
6260
6261int kvm_arch_create_memslot(struct kvm_memory_slot *slot, unsigned long npages)
6262{
6263 int i;
6264
6265 for (i = 0; i < KVM_NR_PAGE_SIZES - 1; ++i) {
6266 unsigned long ugfn;
6267 int lpages;
6268 int level = i + 2;
6269
6270 lpages = gfn_to_index(slot->base_gfn + npages - 1,
6271 slot->base_gfn, level) + 1;
6272
6273 slot->arch.lpage_info[i] =
6274 vzalloc(lpages * sizeof(*slot->arch.lpage_info[i]));
6275 if (!slot->arch.lpage_info[i])
6276 goto out_free;
6277
6278 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
6279 slot->arch.lpage_info[i][0].write_count = 1;
6280 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
6281 slot->arch.lpage_info[i][lpages - 1].write_count = 1;
6282 ugfn = slot->userspace_addr >> PAGE_SHIFT;
6283 /*
6284 * If the gfn and userspace address are not aligned wrt each
6285 * other, or if explicitly asked to, disable large page
6286 * support for this slot
6287 */
6288 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
6289 !kvm_largepages_enabled()) {
6290 unsigned long j;
6291
6292 for (j = 0; j < lpages; ++j)
6293 slot->arch.lpage_info[i][j].write_count = 1;
6294 }
6295 }
6296
6297 return 0;
6298
6299out_free:
6300 for (i = 0; i < KVM_NR_PAGE_SIZES - 1; ++i) {
6301 vfree(slot->arch.lpage_info[i]);
6302 slot->arch.lpage_info[i] = NULL;
6303 }
6304 return -ENOMEM;
6305}
6306
f7784b8e
MT		 6307int kvm_arch_prepare_memory_region(struct kvm *kvm,
6308 struct kvm_memory_slot *memslot,
0de10343 6309 struct kvm_memory_slot old,
f7784b8e 6310 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 6311 int user_alloc)
6312{
f7784b8e 6313 int npages = memslot->npages;
7ac77099
AK		 6314 int map_flags = MAP_PRIVATE | MAP_ANONYMOUS;
6315
6316 /* Prevent internal slot pages from being moved by fork()/COW. */
6317 if (memslot->id >= KVM_MEMORY_SLOTS)
6318 map_flags = MAP_SHARED | MAP_ANONYMOUS;
0de10343
ZX		 6319
6320 /*To keep backward compatibility with older userspace,
6321 *x86 needs to hanlde !user_alloc case.
6322 */
6323 if (!user_alloc) {
6324 if (npages && !old.rmap) {
604b38ac
AA		 6325 unsigned long userspace_addr;
6326
72dc67a6 6327 down_write(&current->mm->mmap_sem);
604b38ac
AA		 6328 userspace_addr = do_mmap(NULL, 0,
6329 npages * PAGE_SIZE,
6330 PROT_READ | PROT_WRITE,
7ac77099 6331 map_flags,
604b38ac 6332 0);
72dc67a6 6333 up_write(&current->mm->mmap_sem);
0de10343 6334
604b38ac
AA		 6335 if (IS_ERR((void *)userspace_addr))
6336 return PTR_ERR((void *)userspace_addr);
6337
604b38ac 6338 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 6339 }
6340 }
6341
f7784b8e
MT		 6342
6343 return 0;
6344}
6345
6346void kvm_arch_commit_memory_region(struct kvm *kvm,
6347 struct kvm_userspace_memory_region *mem,
6348 struct kvm_memory_slot old,
6349 int user_alloc)
6350{
6351
48c0e4e9 6352 int nr_mmu_pages = 0, npages = mem->memory_size >> PAGE_SHIFT;
f7784b8e
MT		 6353
6354 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
6355 int ret;
6356
6357 down_write(&current->mm->mmap_sem);
6358 ret = do_munmap(current->mm, old.userspace_addr,
6359 old.npages * PAGE_SIZE);
6360 up_write(&current->mm->mmap_sem);
6361 if (ret < 0)
6362 printk(KERN_WARNING
6363 "kvm_vm_ioctl_set_memory_region: "
6364 "failed to munmap memory\n");
6365 }
6366
48c0e4e9
XG		 6367 if (!kvm->arch.n_requested_mmu_pages)
6368 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
6369
7c8a83b7 6370 spin_lock(&kvm->mmu_lock);
48c0e4e9 6371 if (nr_mmu_pages)
0de10343 6372 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
0de10343 6373 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 6374 spin_unlock(&kvm->mmu_lock);
0de10343 6375}
1d737c8a 6376
34d4cb8f
MT		 6377void kvm_arch_flush_shadow(struct kvm *kvm)
6378{
6379 kvm_mmu_zap_all(kvm);
8986ecc0 6380 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 6381}
6382
1d737c8a
ZX		 6383int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
6384{
af585b92
GN		 6385 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6386 !vcpu->arch.apf.halted)
6387 || !list_empty_careful(&vcpu->async_pf.done)
a1b37100 6388 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
7460fb4a 6389 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 6390 (kvm_arch_interrupt_allowed(vcpu) &&
6391 kvm_cpu_has_interrupt(vcpu));
1d737c8a 6392}
5736199a 6393
5736199a
ZX		 6394void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
6395{
32f88400
MT		 6396 int me;
6397 int cpu = vcpu->cpu;
5736199a
ZX		 6398
6399 if (waitqueue_active(&vcpu->wq)) {
6400 wake_up_interruptible(&vcpu->wq);
6401 ++vcpu->stat.halt_wakeup;
6402 }
32f88400
MT		 6403
6404 me = get_cpu();
6405 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
6b7e2d09 6406 if (kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE)
32f88400 6407 smp_send_reschedule(cpu);
e9571ed5 6408 put_cpu();
5736199a 6409}
78646121
GN		 6410
6411int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
6412{
6413 return kvm_x86_ops->interrupt_allowed(vcpu);
6414}
229456fc 6415
f92653ee
JK		 6416bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
6417{
6418 unsigned long current_rip = kvm_rip_read(vcpu) +
6419 get_segment_base(vcpu, VCPU_SREG_CS);
6420
6421 return current_rip == linear_rip;
6422}
6423EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
6424
94fe45da
JK		 6425unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
6426{
6427 unsigned long rflags;
6428
6429 rflags = kvm_x86_ops->get_rflags(vcpu);
6430 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 6431 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 6432 return rflags;
6433}
6434EXPORT_SYMBOL_GPL(kvm_get_rflags);
6435
6436void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
6437{
6438 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 6439 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 6440 rflags |= X86_EFLAGS_TF;
94fe45da 6441 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 6442 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 6443}
6444EXPORT_SYMBOL_GPL(kvm_set_rflags);
6445
56028d08
GN		 6446void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
6447{
6448 int r;
6449
fb67e14f 6450 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
c4806acd 6451 is_error_page(work->page))
56028d08
GN		 6452 return;
6453
6454 r = kvm_mmu_reload(vcpu);
6455 if (unlikely(r))
6456 return;
6457
fb67e14f
XG		 6458 if (!vcpu->arch.mmu.direct_map &&
6459 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
6460 return;
6461
56028d08
GN		 6462 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
6463}
6464
af585b92
GN		 6465static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
6466{
6467 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
6468}
6469
6470static inline u32 kvm_async_pf_next_probe(u32 key)
6471{
6472 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
6473}
6474
6475static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6476{
6477 u32 key = kvm_async_pf_hash_fn(gfn);
6478
6479 while (vcpu->arch.apf.gfns[key] != ~0)
6480 key = kvm_async_pf_next_probe(key);
6481
6482 vcpu->arch.apf.gfns[key] = gfn;
6483}
6484
6485static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
6486{
6487 int i;
6488 u32 key = kvm_async_pf_hash_fn(gfn);
6489
6490 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 6491 (vcpu->arch.apf.gfns[key] != gfn &&
6492 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 6493 key = kvm_async_pf_next_probe(key);
6494
6495 return key;
6496}
6497
6498bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6499{
6500 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
6501}
6502
6503static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6504{
6505 u32 i, j, k;
6506
6507 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
6508 while (true) {
6509 vcpu->arch.apf.gfns[i] = ~0;
6510 do {
6511 j = kvm_async_pf_next_probe(j);
6512 if (vcpu->arch.apf.gfns[j] == ~0)
6513 return;
6514 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
6515 /*
6516 * k lies cyclically in ]i,j]
6517 * | i.k.j |
6518 * |....j i.k.| or |.k..j i...|
6519 */
6520 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
6521 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
6522 i = j;
6523 }
6524}
6525
7c90705b
GN		 6526static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
6527{
6528
6529 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
6530 sizeof(val));
6531}
6532
af585b92
GN		 6533void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
6534 struct kvm_async_pf *work)
6535{
6389ee94
AK		 6536 struct x86_exception fault;
6537
7c90705b 6538 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 6539 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 6540
6541 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 6542 (vcpu->arch.apf.send_user_only &&
6543 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 6544 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
6545 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 6546 fault.vector = PF_VECTOR;
6547 fault.error_code_valid = true;
6548 fault.error_code = 0;
6549 fault.nested_page_fault = false;
6550 fault.address = work->arch.token;
6551 kvm_inject_page_fault(vcpu, &fault);
7c90705b 6552 }
af585b92
GN		 6553}
6554
6555void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
6556 struct kvm_async_pf *work)
6557{
6389ee94
AK		 6558 struct x86_exception fault;
6559
7c90705b
GN		 6560 trace_kvm_async_pf_ready(work->arch.token, work->gva);
6561 if (is_error_page(work->page))
6562 work->arch.token = ~0; /* broadcast wakeup */
6563 else
6564 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
6565
6566 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
6567 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 6568 fault.vector = PF_VECTOR;
6569 fault.error_code_valid = true;
6570 fault.error_code = 0;
6571 fault.nested_page_fault = false;
6572 fault.address = work->arch.token;
6573 kvm_inject_page_fault(vcpu, &fault);
7c90705b 6574 }
e6d53e3b 6575 vcpu->arch.apf.halted = false;
7c90705b
GN		 6576}
6577
6578bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
6579{
6580 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
6581 return true;
6582 else
6583 return !kvm_event_needs_reinjection(vcpu) &&
6584 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 6585}
6586
229456fc
MT		 6587EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
6588EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
6589EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
6590EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
6591EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 6592EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 6593EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 6594EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 6595EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 6596EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 6597EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 6598EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
kernel source for telekom puls (alcatel/mediatek)