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KVM: x86 emulator: Use em_push() instead of emulate_push()
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
313a3dc7 29
18068523 30#include <linux/clocksource.h>
4d5c5d0f 31#include <linux/interrupt.h>
313a3dc7
CO		 32#include <linux/kvm.h>
33#include <linux/fs.h>
34#include <linux/vmalloc.h>
5fb76f9b 35#include <linux/module.h>
0de10343 36#include <linux/mman.h>
2bacc55c 37#include <linux/highmem.h>
19de40a8 38#include <linux/iommu.h>
62c476c7 39#include <linux/intel-iommu.h>
c8076604 40#include <linux/cpufreq.h>
18863bdd 41#include <linux/user-return-notifier.h>
a983fb23 42#include <linux/srcu.h>
5a0e3ad6 43#include <linux/slab.h>
ff9d07a0 44#include <linux/perf_event.h>
7bee342a 45#include <linux/uaccess.h>
af585b92 46#include <linux/hash.h>
aec51dc4 47#include <trace/events/kvm.h>
2ed152af 48
229456fc
MT		 49#define CREATE_TRACE_POINTS
50#include "trace.h"
043405e1 51
24f1e32c 52#include <asm/debugreg.h>
d825ed0a 53#include <asm/msr.h>
a5f61300 54#include <asm/desc.h>
0bed3b56 55#include <asm/mtrr.h>
890ca9ae 56#include <asm/mce.h>
7cf30855 57#include <asm/i387.h>
98918833 58#include <asm/xcr.h>
1d5f066e 59#include <asm/pvclock.h>
217fc9cf 60#include <asm/div64.h>
043405e1 61
313a3dc7 62#define MAX_IO_MSRS 256
890ca9ae 63#define KVM_MAX_MCE_BANKS 32
5854dbca 64#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 65
50a37eb4
JR		 66/* EFER defaults:
67 * - enable syscall per default because its emulated by KVM
68 * - enable LME and LMA per default on 64 bit KVM
69 */
70#ifdef CONFIG_X86_64
1260edbe
LJ		 71static
72u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 73#else
1260edbe 74static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 75#endif
313a3dc7 76
ba1389b7
AK		 77#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
78#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 79
cb142eb7 80static void update_cr8_intercept(struct kvm_vcpu *vcpu);
674eea0f
AK		 81static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
82 struct kvm_cpuid_entry2 __user *entries);
83
97896d04 84struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 85EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 86
ed85c068
AP		 87int ignore_msrs = 0;
88module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
89
92a1f12d
JR		 90bool kvm_has_tsc_control;
91EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
92u32 kvm_max_guest_tsc_khz;
93EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
94
18863bdd
AK		 95#define KVM_NR_SHARED_MSRS 16
96
97struct kvm_shared_msrs_global {
98 int nr;
2bf78fa7 99 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 100};
101
102struct kvm_shared_msrs {
103 struct user_return_notifier urn;
104 bool registered;
2bf78fa7
SY		 105 struct kvm_shared_msr_values {
106 u64 host;
107 u64 curr;
108 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 109};
110
111static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
112static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
113
417bc304 114struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 115 { "pf_fixed", VCPU_STAT(pf_fixed) },
116 { "pf_guest", VCPU_STAT(pf_guest) },
117 { "tlb_flush", VCPU_STAT(tlb_flush) },
118 { "invlpg", VCPU_STAT(invlpg) },
119 { "exits", VCPU_STAT(exits) },
120 { "io_exits", VCPU_STAT(io_exits) },
121 { "mmio_exits", VCPU_STAT(mmio_exits) },
122 { "signal_exits", VCPU_STAT(signal_exits) },
123 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 124 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 125 { "halt_exits", VCPU_STAT(halt_exits) },
126 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 127 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 128 { "request_irq", VCPU_STAT(request_irq_exits) },
129 { "irq_exits", VCPU_STAT(irq_exits) },
130 { "host_state_reload", VCPU_STAT(host_state_reload) },
131 { "efer_reload", VCPU_STAT(efer_reload) },
132 { "fpu_reload", VCPU_STAT(fpu_reload) },
133 { "insn_emulation", VCPU_STAT(insn_emulation) },
134 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 135 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 136 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 137 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
138 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
139 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
140 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
141 { "mmu_flooded", VM_STAT(mmu_flooded) },
142 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 143 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 144 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 145 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 146 { "largepages", VM_STAT(lpages) },
417bc304
HB		 147 { NULL }
148};
149
2acf923e
DC		 150u64 __read_mostly host_xcr0;
151
af585b92
GN		 152static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
153{
154 int i;
155 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
156 vcpu->arch.apf.gfns[i] = ~0;
157}
158
18863bdd
AK		 159static void kvm_on_user_return(struct user_return_notifier *urn)
160{
161 unsigned slot;
18863bdd
AK		 162 struct kvm_shared_msrs *locals
163 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 164 struct kvm_shared_msr_values *values;
18863bdd
AK		 165
166 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 167 values = &locals->values[slot];
168 if (values->host != values->curr) {
169 wrmsrl(shared_msrs_global.msrs[slot], values->host);
170 values->curr = values->host;
18863bdd
AK		 171 }
172 }
173 locals->registered = false;
174 user_return_notifier_unregister(urn);
175}
176
2bf78fa7 177static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 178{
2bf78fa7 179 struct kvm_shared_msrs *smsr;
18863bdd
AK		 180 u64 value;
181
2bf78fa7
SY		 182 smsr = &__get_cpu_var(shared_msrs);
183 /* only read, and nobody should modify it at this time,
184 * so don't need lock */
185 if (slot >= shared_msrs_global.nr) {
186 printk(KERN_ERR "kvm: invalid MSR slot!");
187 return;
188 }
189 rdmsrl_safe(msr, &value);
190 smsr->values[slot].host = value;
191 smsr->values[slot].curr = value;
192}
193
194void kvm_define_shared_msr(unsigned slot, u32 msr)
195{
18863bdd
AK		 196 if (slot >= shared_msrs_global.nr)
197 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 198 shared_msrs_global.msrs[slot] = msr;
199 /* we need ensured the shared_msr_global have been updated */
200 smp_wmb();
18863bdd
AK		 201}
202EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
203
204static void kvm_shared_msr_cpu_online(void)
205{
206 unsigned i;
18863bdd
AK		 207
208 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 209 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 210}
211
d5696725 212void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 213{
214 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
215
2bf78fa7 216 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 217 return;
2bf78fa7
SY		 218 smsr->values[slot].curr = value;
219 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 220 if (!smsr->registered) {
221 smsr->urn.on_user_return = kvm_on_user_return;
222 user_return_notifier_register(&smsr->urn);
223 smsr->registered = true;
224 }
225}
226EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
227
3548bab5
AK		 228static void drop_user_return_notifiers(void *ignore)
229{
230 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
231
232 if (smsr->registered)
233 kvm_on_user_return(&smsr->urn);
234}
235
6866b83e
CO		 236u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
237{
238 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 239 return vcpu->arch.apic_base;
6866b83e 240 else
ad312c7c 241 return vcpu->arch.apic_base;
6866b83e
CO		 242}
243EXPORT_SYMBOL_GPL(kvm_get_apic_base);
244
245void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
246{
247 /* TODO: reserve bits check */
248 if (irqchip_in_kernel(vcpu->kvm))
249 kvm_lapic_set_base(vcpu, data);
250 else
ad312c7c 251 vcpu->arch.apic_base = data;
6866b83e
CO		 252}
253EXPORT_SYMBOL_GPL(kvm_set_apic_base);
254
3fd28fce
ED		 255#define EXCPT_BENIGN 0
256#define EXCPT_CONTRIBUTORY 1
257#define EXCPT_PF 2
258
259static int exception_class(int vector)
260{
261 switch (vector) {
262 case PF_VECTOR:
263 return EXCPT_PF;
264 case DE_VECTOR:
265 case TS_VECTOR:
266 case NP_VECTOR:
267 case SS_VECTOR:
268 case GP_VECTOR:
269 return EXCPT_CONTRIBUTORY;
270 default:
271 break;
272 }
273 return EXCPT_BENIGN;
274}
275
276static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 277 unsigned nr, bool has_error, u32 error_code,
278 bool reinject)
3fd28fce
ED		 279{
280 u32 prev_nr;
281 int class1, class2;
282
3842d135
AK		 283 kvm_make_request(KVM_REQ_EVENT, vcpu);
284
3fd28fce
ED		 285 if (!vcpu->arch.exception.pending) {
286 queue:
287 vcpu->arch.exception.pending = true;
288 vcpu->arch.exception.has_error_code = has_error;
289 vcpu->arch.exception.nr = nr;
290 vcpu->arch.exception.error_code = error_code;
3f0fd292 291 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 292 return;
293 }
294
295 /* to check exception */
296 prev_nr = vcpu->arch.exception.nr;
297 if (prev_nr == DF_VECTOR) {
298 /* triple fault -> shutdown */
a8eeb04a 299 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 300 return;
301 }
302 class1 = exception_class(prev_nr);
303 class2 = exception_class(nr);
304 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
305 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
306 /* generate double fault per SDM Table 5-5 */
307 vcpu->arch.exception.pending = true;
308 vcpu->arch.exception.has_error_code = true;
309 vcpu->arch.exception.nr = DF_VECTOR;
310 vcpu->arch.exception.error_code = 0;
311 } else
312 /* replace previous exception with a new one in a hope
313 that instruction re-execution will regenerate lost
314 exception */
315 goto queue;
316}
317
298101da
AK		 318void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
319{
ce7ddec4 320 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 321}
322EXPORT_SYMBOL_GPL(kvm_queue_exception);
323
ce7ddec4
JR		 324void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
325{
326 kvm_multiple_exception(vcpu, nr, false, 0, true);
327}
328EXPORT_SYMBOL_GPL(kvm_requeue_exception);
329
db8fcefa 330void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 331{
db8fcefa
AP		 332 if (err)
333 kvm_inject_gp(vcpu, 0);
334 else
335 kvm_x86_ops->skip_emulated_instruction(vcpu);
336}
337EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 338
6389ee94 339void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 340{
341 ++vcpu->stat.pf_guest;
6389ee94
AK		 342 vcpu->arch.cr2 = fault->address;
343 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee
AK		 344}
345
6389ee94 346void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 347{
6389ee94
AK		 348 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
349 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 350 else
6389ee94 351 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
d4f8cf66
JR		 352}
353
3419ffc8
SY		 354void kvm_inject_nmi(struct kvm_vcpu *vcpu)
355{
3842d135 356 kvm_make_request(KVM_REQ_EVENT, vcpu);
c761e586 357 vcpu->arch.nmi_pending = 1;
3419ffc8
SY		 358}
359EXPORT_SYMBOL_GPL(kvm_inject_nmi);
360
298101da
AK		 361void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
362{
ce7ddec4 363 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 364}
365EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
366
ce7ddec4
JR		 367void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
368{
369 kvm_multiple_exception(vcpu, nr, true, error_code, true);
370}
371EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
372
0a79b009
AK		 373/*
374 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
375 * a #GP and return false.
376 */
377bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 378{
0a79b009
AK		 379 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
380 return true;
381 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
382 return false;
298101da 383}
0a79b009 384EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 385
ec92fe44
JR		 386/*
387 * This function will be used to read from the physical memory of the currently
388 * running guest. The difference to kvm_read_guest_page is that this function
389 * can read from guest physical or from the guest's guest physical memory.
390 */
391int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
392 gfn_t ngfn, void *data, int offset, int len,
393 u32 access)
394{
395 gfn_t real_gfn;
396 gpa_t ngpa;
397
398 ngpa = gfn_to_gpa(ngfn);
399 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
400 if (real_gfn == UNMAPPED_GVA)
401 return -EFAULT;
402
403 real_gfn = gpa_to_gfn(real_gfn);
404
405 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
406}
407EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
408
3d06b8bf
JR		 409int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
410 void *data, int offset, int len, u32 access)
411{
412 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
413 data, offset, len, access);
414}
415
a03490ed
CO		 416/*
417 * Load the pae pdptrs. Return true is they are all valid.
418 */
ff03a073 419int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 420{
421 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
422 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
423 int i;
424 int ret;
ff03a073 425 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 426
ff03a073
JR		 427 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
428 offset * sizeof(u64), sizeof(pdpte),
429 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 430 if (ret < 0) {
431 ret = 0;
432 goto out;
433 }
434 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 435 if (is_present_gpte(pdpte[i]) &&
20c466b5 436 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 437 ret = 0;
438 goto out;
439 }
440 }
441 ret = 1;
442
ff03a073 443 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 444 __set_bit(VCPU_EXREG_PDPTR,
445 (unsigned long *)&vcpu->arch.regs_avail);
446 __set_bit(VCPU_EXREG_PDPTR,
447 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 448out:
a03490ed
CO		 449
450 return ret;
451}
cc4b6871 452EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 453
d835dfec
AK		 454static bool pdptrs_changed(struct kvm_vcpu *vcpu)
455{
ff03a073 456 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 457 bool changed = true;
3d06b8bf
JR		 458 int offset;
459 gfn_t gfn;
d835dfec
AK		 460 int r;
461
462 if (is_long_mode(vcpu) || !is_pae(vcpu))
463 return false;
464
6de4f3ad
AK		 465 if (!test_bit(VCPU_EXREG_PDPTR,
466 (unsigned long *)&vcpu->arch.regs_avail))
467 return true;
468
9f8fe504
AK		 469 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
470 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 471 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
472 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 473 if (r < 0)
474 goto out;
ff03a073 475 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 476out:
d835dfec
AK		 477
478 return changed;
479}
480
49a9b07e 481int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 482{
aad82703
SY		 483 unsigned long old_cr0 = kvm_read_cr0(vcpu);
484 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
485 X86_CR0_CD | X86_CR0_NW;
486
f9a48e6a
AK		 487 cr0 |= X86_CR0_ET;
488
ab344828 489#ifdef CONFIG_X86_64
0f12244f
GN		 490 if (cr0 & 0xffffffff00000000UL)
491 return 1;
ab344828
GN		 492#endif
493
494 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 495
0f12244f
GN		 496 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
497 return 1;
a03490ed 498
0f12244f
GN		 499 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
500 return 1;
a03490ed
CO		 501
502 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
503#ifdef CONFIG_X86_64
f6801dff 504 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 505 int cs_db, cs_l;
506
0f12244f
GN		 507 if (!is_pae(vcpu))
508 return 1;
a03490ed 509 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 510 if (cs_l)
511 return 1;
a03490ed
CO		 512 } else
513#endif
ff03a073 514 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 515 kvm_read_cr3(vcpu)))
0f12244f 516 return 1;
a03490ed
CO		 517 }
518
519 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 520
d170c419 521 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 522 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 523 kvm_async_pf_hash_reset(vcpu);
524 }
e5f3f027 525
aad82703
SY		 526 if ((cr0 ^ old_cr0) & update_bits)
527 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 528 return 0;
529}
2d3ad1f4 530EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 531
2d3ad1f4 532void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 533{
49a9b07e 534 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 535}
2d3ad1f4 536EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 537
2acf923e
DC		 538int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
539{
540 u64 xcr0;
541
542 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
543 if (index != XCR_XFEATURE_ENABLED_MASK)
544 return 1;
545 xcr0 = xcr;
546 if (kvm_x86_ops->get_cpl(vcpu) != 0)
547 return 1;
548 if (!(xcr0 & XSTATE_FP))
549 return 1;
550 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
551 return 1;
552 if (xcr0 & ~host_xcr0)
553 return 1;
554 vcpu->arch.xcr0 = xcr0;
555 vcpu->guest_xcr0_loaded = 0;
556 return 0;
557}
558
559int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
560{
561 if (__kvm_set_xcr(vcpu, index, xcr)) {
562 kvm_inject_gp(vcpu, 0);
563 return 1;
564 }
565 return 0;
566}
567EXPORT_SYMBOL_GPL(kvm_set_xcr);
568
569static bool guest_cpuid_has_xsave(struct kvm_vcpu *vcpu)
570{
571 struct kvm_cpuid_entry2 *best;
572
573 best = kvm_find_cpuid_entry(vcpu, 1, 0);
574 return best && (best->ecx & bit(X86_FEATURE_XSAVE));
575}
576
577static void update_cpuid(struct kvm_vcpu *vcpu)
578{
579 struct kvm_cpuid_entry2 *best;
580
581 best = kvm_find_cpuid_entry(vcpu, 1, 0);
582 if (!best)
583 return;
584
585 /* Update OSXSAVE bit */
586 if (cpu_has_xsave && best->function == 0x1) {
587 best->ecx &= ~(bit(X86_FEATURE_OSXSAVE));
588 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE))
589 best->ecx |= bit(X86_FEATURE_OSXSAVE);
590 }
591}
592
a83b29c6 593int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 594{
fc78f519 595 unsigned long old_cr4 = kvm_read_cr4(vcpu);
a2edf57f
AK		 596 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
597
0f12244f
GN		 598 if (cr4 & CR4_RESERVED_BITS)
599 return 1;
a03490ed 600
2acf923e
DC		 601 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
602 return 1;
603
a03490ed 604 if (is_long_mode(vcpu)) {
0f12244f
GN		 605 if (!(cr4 & X86_CR4_PAE))
606 return 1;
a2edf57f
AK		 607 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
608 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 609 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
610 kvm_read_cr3(vcpu)))
0f12244f
GN		 611 return 1;
612
613 if (cr4 & X86_CR4_VMXE)
614 return 1;
a03490ed 615
a03490ed 616 kvm_x86_ops->set_cr4(vcpu, cr4);
62ad0755 617
aad82703
SY		 618 if ((cr4 ^ old_cr4) & pdptr_bits)
619 kvm_mmu_reset_context(vcpu);
0f12244f 620
2acf923e
DC		 621 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
622 update_cpuid(vcpu);
623
0f12244f
GN		 624 return 0;
625}
2d3ad1f4 626EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 627
2390218b 628int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 629{
9f8fe504 630 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 631 kvm_mmu_sync_roots(vcpu);
d835dfec 632 kvm_mmu_flush_tlb(vcpu);
0f12244f 633 return 0;
d835dfec
AK		 634 }
635
a03490ed 636 if (is_long_mode(vcpu)) {
0f12244f
GN		 637 if (cr3 & CR3_L_MODE_RESERVED_BITS)
638 return 1;
a03490ed
CO		 639 } else {
640 if (is_pae(vcpu)) {
0f12244f
GN		 641 if (cr3 & CR3_PAE_RESERVED_BITS)
642 return 1;
ff03a073
JR		 643 if (is_paging(vcpu) &&
644 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
0f12244f 645 return 1;
a03490ed
CO		 646 }
647 /*
648 * We don't check reserved bits in nonpae mode, because
649 * this isn't enforced, and VMware depends on this.
650 */
651 }
652
a03490ed
CO		 653 /*
654 * Does the new cr3 value map to physical memory? (Note, we
655 * catch an invalid cr3 even in real-mode, because it would
656 * cause trouble later on when we turn on paging anyway.)
657 *
658 * A real CPU would silently accept an invalid cr3 and would
659 * attempt to use it - with largely undefined (and often hard
660 * to debug) behavior on the guest side.
661 */
662 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
0f12244f
GN		 663 return 1;
664 vcpu->arch.cr3 = cr3;
aff48baa 665 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
0f12244f
GN		 666 vcpu->arch.mmu.new_cr3(vcpu);
667 return 0;
668}
2d3ad1f4 669EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 670
eea1cff9 671int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 672{
0f12244f
GN		 673 if (cr8 & CR8_RESERVED_BITS)
674 return 1;
a03490ed
CO		 675 if (irqchip_in_kernel(vcpu->kvm))
676 kvm_lapic_set_tpr(vcpu, cr8);
677 else
ad312c7c 678 vcpu->arch.cr8 = cr8;
0f12244f
GN		 679 return 0;
680}
2d3ad1f4 681EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 682
2d3ad1f4 683unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 684{
685 if (irqchip_in_kernel(vcpu->kvm))
686 return kvm_lapic_get_cr8(vcpu);
687 else
ad312c7c 688 return vcpu->arch.cr8;
a03490ed 689}
2d3ad1f4 690EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 691
338dbc97 692static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 693{
694 switch (dr) {
695 case 0 ... 3:
696 vcpu->arch.db[dr] = val;
697 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
698 vcpu->arch.eff_db[dr] = val;
699 break;
700 case 4:
338dbc97
GN		 701 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
702 return 1; /* #UD */
020df079
GN		 703 /* fall through */
704 case 6:
338dbc97
GN		 705 if (val & 0xffffffff00000000ULL)
706 return -1; /* #GP */
020df079
GN		 707 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
708 break;
709 case 5:
338dbc97
GN		 710 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
711 return 1; /* #UD */
020df079
GN		 712 /* fall through */
713 default: /* 7 */
338dbc97
GN		 714 if (val & 0xffffffff00000000ULL)
715 return -1; /* #GP */
020df079
GN		 716 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
717 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
718 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
719 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
720 }
721 break;
722 }
723
724 return 0;
725}
338dbc97
GN		 726
727int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
728{
729 int res;
730
731 res = __kvm_set_dr(vcpu, dr, val);
732 if (res > 0)
733 kvm_queue_exception(vcpu, UD_VECTOR);
734 else if (res < 0)
735 kvm_inject_gp(vcpu, 0);
736
737 return res;
738}
020df079
GN		 739EXPORT_SYMBOL_GPL(kvm_set_dr);
740
338dbc97 741static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 742{
743 switch (dr) {
744 case 0 ... 3:
745 *val = vcpu->arch.db[dr];
746 break;
747 case 4:
338dbc97 748 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 749 return 1;
020df079
GN		 750 /* fall through */
751 case 6:
752 *val = vcpu->arch.dr6;
753 break;
754 case 5:
338dbc97 755 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 756 return 1;
020df079
GN		 757 /* fall through */
758 default: /* 7 */
759 *val = vcpu->arch.dr7;
760 break;
761 }
762
763 return 0;
764}
338dbc97
GN		 765
766int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
767{
768 if (_kvm_get_dr(vcpu, dr, val)) {
769 kvm_queue_exception(vcpu, UD_VECTOR);
770 return 1;
771 }
772 return 0;
773}
020df079
GN		 774EXPORT_SYMBOL_GPL(kvm_get_dr);
775
043405e1
CO		 776/*
777 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
778 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
779 *
780 * This list is modified at module load time to reflect the
e3267cbb
GC		 781 * capabilities of the host cpu. This capabilities test skips MSRs that are
782 * kvm-specific. Those are put in the beginning of the list.
043405e1 783 */
e3267cbb 784
344d9588 785#define KVM_SAVE_MSRS_BEGIN 8
043405e1 786static u32 msrs_to_save[] = {
e3267cbb 787 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 788 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 789 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
344d9588 790 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN,
043405e1 791 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 792 MSR_STAR,
043405e1
CO		 793#ifdef CONFIG_X86_64
794 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
795#endif
e90aa41e 796 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 797};
798
799static unsigned num_msrs_to_save;
800
801static u32 emulated_msrs[] = {
802 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 803 MSR_IA32_MCG_STATUS,
804 MSR_IA32_MCG_CTL,
043405e1
CO		 805};
806
b69e8cae 807static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 808{
aad82703
SY		 809 u64 old_efer = vcpu->arch.efer;
810
b69e8cae
RJ		 811 if (efer & efer_reserved_bits)
812 return 1;
15c4a640
CO		 813
814 if (is_paging(vcpu)
b69e8cae
RJ		 815 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
816 return 1;
15c4a640 817
1b2fd70c
AG		 818 if (efer & EFER_FFXSR) {
819 struct kvm_cpuid_entry2 *feat;
820
821 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 822 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
823 return 1;
1b2fd70c
AG		 824 }
825
d8017474
AG		 826 if (efer & EFER_SVME) {
827 struct kvm_cpuid_entry2 *feat;
828
829 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 830 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
831 return 1;
d8017474
AG		 832 }
833
15c4a640 834 efer &= ~EFER_LMA;
f6801dff 835 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 836
a3d204e2
SY		 837 kvm_x86_ops->set_efer(vcpu, efer);
838
9645bb56 839 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
b69e8cae 840
aad82703
SY		 841 /* Update reserved bits */
842 if ((efer ^ old_efer) & EFER_NX)
843 kvm_mmu_reset_context(vcpu);
844
b69e8cae 845 return 0;
15c4a640
CO		 846}
847
f2b4b7dd
JR		 848void kvm_enable_efer_bits(u64 mask)
849{
850 efer_reserved_bits &= ~mask;
851}
852EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
853
854
15c4a640
CO		 855/*
856 * Writes msr value into into the appropriate "register".
857 * Returns 0 on success, non-0 otherwise.
858 * Assumes vcpu_load() was already called.
859 */
860int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
861{
862 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
863}
864
313a3dc7
CO		 865/*
866 * Adapt set_msr() to msr_io()'s calling convention
867 */
868static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
869{
870 return kvm_set_msr(vcpu, index, *data);
871}
872
18068523
GOC		 873static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
874{
9ed3c444
AK		 875 int version;
876 int r;
50d0a0f9 877 struct pvclock_wall_clock wc;
923de3cf 878 struct timespec boot;
18068523
GOC		 879
880 if (!wall_clock)
881 return;
882
9ed3c444
AK		 883 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
884 if (r)
885 return;
886
887 if (version & 1)
888 ++version; /* first time write, random junk */
889
890 ++version;
18068523 891
18068523
GOC		 892 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
893
50d0a0f9
GH		 894 /*
895 * The guest calculates current wall clock time by adding
34c238a1 896 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 897 * wall clock specified here. guest system time equals host
898 * system time for us, thus we must fill in host boot time here.
899 */
923de3cf 900 getboottime(&boot);
50d0a0f9
GH		 901
902 wc.sec = boot.tv_sec;
903 wc.nsec = boot.tv_nsec;
904 wc.version = version;
18068523
GOC		 905
906 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
907
908 version++;
909 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 910}
911
50d0a0f9
GH		 912static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
913{
914 uint32_t quotient, remainder;
915
916 /* Don't try to replace with do_div(), this one calculates
917 * "(dividend << 32) / divisor" */
918 __asm__ ( "divl %4"
919 : "=a" (quotient), "=d" (remainder)
920 : "0" (0), "1" (dividend), "r" (divisor) );
921 return quotient;
922}
923
5f4e3f88
ZA		 924static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
925 s8 *pshift, u32 *pmultiplier)
50d0a0f9 926{
5f4e3f88 927 uint64_t scaled64;
50d0a0f9
GH		 928 int32_t shift = 0;
929 uint64_t tps64;
930 uint32_t tps32;
931
5f4e3f88
ZA		 932 tps64 = base_khz * 1000LL;
933 scaled64 = scaled_khz * 1000LL;
50933623 934 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 935 tps64 >>= 1;
936 shift--;
937 }
938
939 tps32 = (uint32_t)tps64;
50933623
JK		 940 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
941 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 942 scaled64 >>= 1;
943 else
944 tps32 <<= 1;
50d0a0f9
GH		 945 shift++;
946 }
947
5f4e3f88
ZA		 948 *pshift = shift;
949 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 950
5f4e3f88
ZA		 951 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
952 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 953}
954
759379dd
ZA		 955static inline u64 get_kernel_ns(void)
956{
957 struct timespec ts;
958
959 WARN_ON(preemptible());
960 ktime_get_ts(&ts);
961 monotonic_to_bootbased(&ts);
962 return timespec_to_ns(&ts);
50d0a0f9
GH		 963}
964
c8076604 965static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 966unsigned long max_tsc_khz;
c8076604 967
8cfdc000
ZA		 968static inline int kvm_tsc_changes_freq(void)
969{
970 int cpu = get_cpu();
971 int ret = !boot_cpu_has(X86_FEATURE_CONSTANT_TSC) &&
972 cpufreq_quick_get(cpu) != 0;
973 put_cpu();
974 return ret;
975}
976
1e993611
JR		 977static u64 vcpu_tsc_khz(struct kvm_vcpu *vcpu)
978{
979 if (vcpu->arch.virtual_tsc_khz)
980 return vcpu->arch.virtual_tsc_khz;
981 else
982 return __this_cpu_read(cpu_tsc_khz);
983}
984
857e4099 985static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
759379dd 986{
217fc9cf
AK		 987 u64 ret;
988
759379dd
ZA		 989 WARN_ON(preemptible());
990 if (kvm_tsc_changes_freq())
991 printk_once(KERN_WARNING
992 "kvm: unreliable cycle conversion on adjustable rate TSC\n");
857e4099 993 ret = nsec * vcpu_tsc_khz(vcpu);
217fc9cf
AK		 994 do_div(ret, USEC_PER_SEC);
995 return ret;
759379dd
ZA		 996}
997
1e993611 998static void kvm_init_tsc_catchup(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
c285545f
ZA		 999{
1000 /* Compute a scale to convert nanoseconds in TSC cycles */
1001 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
1e993611
JR		 1002 &vcpu->arch.tsc_catchup_shift,
1003 &vcpu->arch.tsc_catchup_mult);
c285545f
ZA		 1004}
1005
1006static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1007{
1008 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.last_tsc_nsec,
1e993611
JR		 1009 vcpu->arch.tsc_catchup_mult,
1010 vcpu->arch.tsc_catchup_shift);
c285545f
ZA		 1011 tsc += vcpu->arch.last_tsc_write;
1012 return tsc;
1013}
1014
99e3e30a
ZA		 1015void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
1016{
1017 struct kvm *kvm = vcpu->kvm;
f38e098f 1018 u64 offset, ns, elapsed;
99e3e30a 1019 unsigned long flags;
46543ba4 1020 s64 sdiff;
99e3e30a 1021
038f8c11 1022 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1023 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1024 ns = get_kernel_ns();
f38e098f 1025 elapsed = ns - kvm->arch.last_tsc_nsec;
46543ba4
ZA		 1026 sdiff = data - kvm->arch.last_tsc_write;
1027 if (sdiff < 0)
1028 sdiff = -sdiff;
f38e098f
ZA		 1029
1030 /*
46543ba4 1031 * Special case: close write to TSC within 5 seconds of
f38e098f 1032 * another CPU is interpreted as an attempt to synchronize
0d2eb44f 1033 * The 5 seconds is to accommodate host load / swapping as
46543ba4 1034 * well as any reset of TSC during the boot process.
f38e098f
ZA		 1035 *
1036 * In that case, for a reliable TSC, we can match TSC offsets,
46543ba4 1037 * or make a best guest using elapsed value.
f38e098f 1038 */
857e4099 1039 if (sdiff < nsec_to_cycles(vcpu, 5ULL * NSEC_PER_SEC) &&
46543ba4 1040 elapsed < 5ULL * NSEC_PER_SEC) {
f38e098f
ZA		 1041 if (!check_tsc_unstable()) {
1042 offset = kvm->arch.last_tsc_offset;
1043 pr_debug("kvm: matched tsc offset for %llu\n", data);
1044 } else {
857e4099 1045 u64 delta = nsec_to_cycles(vcpu, elapsed);
759379dd
ZA		 1046 offset += delta;
1047 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f
ZA		 1048 }
1049 ns = kvm->arch.last_tsc_nsec;
1050 }
1051 kvm->arch.last_tsc_nsec = ns;
1052 kvm->arch.last_tsc_write = data;
1053 kvm->arch.last_tsc_offset = offset;
99e3e30a 1054 kvm_x86_ops->write_tsc_offset(vcpu, offset);
038f8c11 1055 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
99e3e30a
ZA		 1056
1057 /* Reset of TSC must disable overshoot protection below */
1058 vcpu->arch.hv_clock.tsc_timestamp = 0;
c285545f
ZA		 1059 vcpu->arch.last_tsc_write = data;
1060 vcpu->arch.last_tsc_nsec = ns;
99e3e30a
ZA		 1061}
1062EXPORT_SYMBOL_GPL(kvm_write_tsc);
1063
34c238a1 1064static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1065{
18068523
GOC		 1066 unsigned long flags;
1067 struct kvm_vcpu_arch *vcpu = &v->arch;
1068 void *shared_kaddr;
463656c0 1069 unsigned long this_tsc_khz;
1d5f066e
ZA		 1070 s64 kernel_ns, max_kernel_ns;
1071 u64 tsc_timestamp;
18068523 1072
18068523
GOC		 1073 /* Keep irq disabled to prevent changes to the clock */
1074 local_irq_save(flags);
1d5f066e 1075 kvm_get_msr(v, MSR_IA32_TSC, &tsc_timestamp);
759379dd 1076 kernel_ns = get_kernel_ns();
1e993611 1077 this_tsc_khz = vcpu_tsc_khz(v);
8cfdc000 1078 if (unlikely(this_tsc_khz == 0)) {
c285545f 1079 local_irq_restore(flags);
34c238a1 1080 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
8cfdc000
ZA		 1081 return 1;
1082 }
18068523 1083
c285545f
ZA		 1084 /*
1085 * We may have to catch up the TSC to match elapsed wall clock
1086 * time for two reasons, even if kvmclock is used.
1087 * 1) CPU could have been running below the maximum TSC rate
1088 * 2) Broken TSC compensation resets the base at each VCPU
1089 * entry to avoid unknown leaps of TSC even when running
1090 * again on the same CPU. This may cause apparent elapsed
1091 * time to disappear, and the guest to stand still or run
1092 * very slowly.
1093 */
1094 if (vcpu->tsc_catchup) {
1095 u64 tsc = compute_guest_tsc(v, kernel_ns);
1096 if (tsc > tsc_timestamp) {
1097 kvm_x86_ops->adjust_tsc_offset(v, tsc - tsc_timestamp);
1098 tsc_timestamp = tsc;
1099 }
50d0a0f9
GH		 1100 }
1101
18068523
GOC		 1102 local_irq_restore(flags);
1103
c285545f
ZA		 1104 if (!vcpu->time_page)
1105 return 0;
18068523 1106
1d5f066e
ZA		 1107 /*
1108 * Time as measured by the TSC may go backwards when resetting the base
1109 * tsc_timestamp. The reason for this is that the TSC resolution is
1110 * higher than the resolution of the other clock scales. Thus, many
1111 * possible measurments of the TSC correspond to one measurement of any
1112 * other clock, and so a spread of values is possible. This is not a
1113 * problem for the computation of the nanosecond clock; with TSC rates
1114 * around 1GHZ, there can only be a few cycles which correspond to one
1115 * nanosecond value, and any path through this code will inevitably
1116 * take longer than that. However, with the kernel_ns value itself,
1117 * the precision may be much lower, down to HZ granularity. If the
1118 * first sampling of TSC against kernel_ns ends in the low part of the
1119 * range, and the second in the high end of the range, we can get:
1120 *
1121 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1122 *
1123 * As the sampling errors potentially range in the thousands of cycles,
1124 * it is possible such a time value has already been observed by the
1125 * guest. To protect against this, we must compute the system time as
1126 * observed by the guest and ensure the new system time is greater.
1127 */
1128 max_kernel_ns = 0;
1129 if (vcpu->hv_clock.tsc_timestamp && vcpu->last_guest_tsc) {
1130 max_kernel_ns = vcpu->last_guest_tsc -
1131 vcpu->hv_clock.tsc_timestamp;
1132 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1133 vcpu->hv_clock.tsc_to_system_mul,
1134 vcpu->hv_clock.tsc_shift);
1135 max_kernel_ns += vcpu->last_kernel_ns;
1136 }
afbcf7ab 1137
e48672fa 1138 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1139 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1140 &vcpu->hv_clock.tsc_shift,
1141 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1142 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1143 }
1144
1d5f066e
ZA		 1145 if (max_kernel_ns > kernel_ns)
1146 kernel_ns = max_kernel_ns;
1147
8cfdc000 1148 /* With all the info we got, fill in the values */
1d5f066e 1149 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1150 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1d5f066e 1151 vcpu->last_kernel_ns = kernel_ns;
28e4639a 1152 vcpu->last_guest_tsc = tsc_timestamp;
371bcf64
GC		 1153 vcpu->hv_clock.flags = 0;
1154
18068523
GOC		 1155 /*
1156 * The interface expects us to write an even number signaling that the
1157 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1158 * state, we just increase by 2 at the end.
18068523 1159 */
50d0a0f9 1160 vcpu->hv_clock.version += 2;
18068523
GOC		 1161
1162 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
1163
1164 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 1165 sizeof(vcpu->hv_clock));
18068523
GOC		 1166
1167 kunmap_atomic(shared_kaddr, KM_USER0);
1168
1169 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
8cfdc000 1170 return 0;
c8076604
GH		 1171}
1172
9ba075a6
AK		 1173static bool msr_mtrr_valid(unsigned msr)
1174{
1175 switch (msr) {
1176 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1177 case MSR_MTRRfix64K_00000:
1178 case MSR_MTRRfix16K_80000:
1179 case MSR_MTRRfix16K_A0000:
1180 case MSR_MTRRfix4K_C0000:
1181 case MSR_MTRRfix4K_C8000:
1182 case MSR_MTRRfix4K_D0000:
1183 case MSR_MTRRfix4K_D8000:
1184 case MSR_MTRRfix4K_E0000:
1185 case MSR_MTRRfix4K_E8000:
1186 case MSR_MTRRfix4K_F0000:
1187 case MSR_MTRRfix4K_F8000:
1188 case MSR_MTRRdefType:
1189 case MSR_IA32_CR_PAT:
1190 return true;
1191 case 0x2f8:
1192 return true;
1193 }
1194 return false;
1195}
1196
d6289b93
MT		 1197static bool valid_pat_type(unsigned t)
1198{
1199 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1200}
1201
1202static bool valid_mtrr_type(unsigned t)
1203{
1204 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1205}
1206
1207static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1208{
1209 int i;
1210
1211 if (!msr_mtrr_valid(msr))
1212 return false;
1213
1214 if (msr == MSR_IA32_CR_PAT) {
1215 for (i = 0; i < 8; i++)
1216 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1217 return false;
1218 return true;
1219 } else if (msr == MSR_MTRRdefType) {
1220 if (data & ~0xcff)
1221 return false;
1222 return valid_mtrr_type(data & 0xff);
1223 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1224 for (i = 0; i < 8 ; i++)
1225 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1226 return false;
1227 return true;
1228 }
1229
1230 /* variable MTRRs */
1231 return valid_mtrr_type(data & 0xff);
1232}
1233
9ba075a6
AK		 1234static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1235{
0bed3b56
SY		 1236 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1237
d6289b93 1238 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1239 return 1;
1240
0bed3b56
SY		 1241 if (msr == MSR_MTRRdefType) {
1242 vcpu->arch.mtrr_state.def_type = data;
1243 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1244 } else if (msr == MSR_MTRRfix64K_00000)
1245 p[0] = data;
1246 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1247 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1248 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1249 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1250 else if (msr == MSR_IA32_CR_PAT)
1251 vcpu->arch.pat = data;
1252 else { /* Variable MTRRs */
1253 int idx, is_mtrr_mask;
1254 u64 *pt;
1255
1256 idx = (msr - 0x200) / 2;
1257 is_mtrr_mask = msr - 0x200 - 2 * idx;
1258 if (!is_mtrr_mask)
1259 pt =
1260 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1261 else
1262 pt =
1263 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1264 *pt = data;
1265 }
1266
1267 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1268 return 0;
1269}
15c4a640 1270
890ca9ae 1271static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1272{
890ca9ae
HY		 1273 u64 mcg_cap = vcpu->arch.mcg_cap;
1274 unsigned bank_num = mcg_cap & 0xff;
1275
15c4a640 1276 switch (msr) {
15c4a640 1277 case MSR_IA32_MCG_STATUS:
890ca9ae 1278 vcpu->arch.mcg_status = data;
15c4a640 1279 break;
c7ac679c 1280 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1281 if (!(mcg_cap & MCG_CTL_P))
1282 return 1;
1283 if (data != 0 && data != ~(u64)0)
1284 return -1;
1285 vcpu->arch.mcg_ctl = data;
1286 break;
1287 default:
1288 if (msr >= MSR_IA32_MC0_CTL &&
1289 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1290 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1291 /* only 0 or all 1s can be written to IA32_MCi_CTL
1292 * some Linux kernels though clear bit 10 in bank 4 to
1293 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1294 * this to avoid an uncatched #GP in the guest
1295 */
890ca9ae 1296 if ((offset & 0x3) == 0 &&
114be429 1297 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1298 return -1;
1299 vcpu->arch.mce_banks[offset] = data;
1300 break;
1301 }
1302 return 1;
1303 }
1304 return 0;
1305}
1306
ffde22ac
ES		 1307static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1308{
1309 struct kvm *kvm = vcpu->kvm;
1310 int lm = is_long_mode(vcpu);
1311 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1312 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1313 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1314 : kvm->arch.xen_hvm_config.blob_size_32;
1315 u32 page_num = data & ~PAGE_MASK;
1316 u64 page_addr = data & PAGE_MASK;
1317 u8 *page;
1318 int r;
1319
1320 r = -E2BIG;
1321 if (page_num >= blob_size)
1322 goto out;
1323 r = -ENOMEM;
1324 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
1325 if (!page)
1326 goto out;
1327 r = -EFAULT;
1328 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
1329 goto out_free;
1330 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1331 goto out_free;
1332 r = 0;
1333out_free:
1334 kfree(page);
1335out:
1336 return r;
1337}
1338
55cd8e5a
GN		 1339static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1340{
1341 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1342}
1343
1344static bool kvm_hv_msr_partition_wide(u32 msr)
1345{
1346 bool r = false;
1347 switch (msr) {
1348 case HV_X64_MSR_GUEST_OS_ID:
1349 case HV_X64_MSR_HYPERCALL:
1350 r = true;
1351 break;
1352 }
1353
1354 return r;
1355}
1356
1357static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1358{
1359 struct kvm *kvm = vcpu->kvm;
1360
1361 switch (msr) {
1362 case HV_X64_MSR_GUEST_OS_ID:
1363 kvm->arch.hv_guest_os_id = data;
1364 /* setting guest os id to zero disables hypercall page */
1365 if (!kvm->arch.hv_guest_os_id)
1366 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1367 break;
1368 case HV_X64_MSR_HYPERCALL: {
1369 u64 gfn;
1370 unsigned long addr;
1371 u8 instructions[4];
1372
1373 /* if guest os id is not set hypercall should remain disabled */
1374 if (!kvm->arch.hv_guest_os_id)
1375 break;
1376 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1377 kvm->arch.hv_hypercall = data;
1378 break;
1379 }
1380 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1381 addr = gfn_to_hva(kvm, gfn);
1382 if (kvm_is_error_hva(addr))
1383 return 1;
1384 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1385 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1386 if (copy_to_user((void __user *)addr, instructions, 4))
1387 return 1;
1388 kvm->arch.hv_hypercall = data;
1389 break;
1390 }
1391 default:
1392 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1393 "data 0x%llx\n", msr, data);
1394 return 1;
1395 }
1396 return 0;
1397}
1398
1399static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1400{
10388a07
GN		 1401 switch (msr) {
1402 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1403 unsigned long addr;
55cd8e5a 1404
10388a07
GN		 1405 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1406 vcpu->arch.hv_vapic = data;
1407 break;
1408 }
1409 addr = gfn_to_hva(vcpu->kvm, data >>
1410 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1411 if (kvm_is_error_hva(addr))
1412 return 1;
1413 if (clear_user((void __user *)addr, PAGE_SIZE))
1414 return 1;
1415 vcpu->arch.hv_vapic = data;
1416 break;
1417 }
1418 case HV_X64_MSR_EOI:
1419 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1420 case HV_X64_MSR_ICR:
1421 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1422 case HV_X64_MSR_TPR:
1423 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1424 default:
1425 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1426 "data 0x%llx\n", msr, data);
1427 return 1;
1428 }
1429
1430 return 0;
55cd8e5a
GN		 1431}
1432
344d9588
GN		 1433static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1434{
1435 gpa_t gpa = data & ~0x3f;
1436
6adba527
GN		 1437 /* Bits 2:5 are resrved, Should be zero */
1438 if (data & 0x3c)
344d9588
GN		 1439 return 1;
1440
1441 vcpu->arch.apf.msr_val = data;
1442
1443 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1444 kvm_clear_async_pf_completion_queue(vcpu);
1445 kvm_async_pf_hash_reset(vcpu);
1446 return 0;
1447 }
1448
1449 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa))
1450 return 1;
1451
6adba527 1452 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1453 kvm_async_pf_wakeup_all(vcpu);
1454 return 0;
1455}
1456
12f9a48f
GC		 1457static void kvmclock_reset(struct kvm_vcpu *vcpu)
1458{
1459 if (vcpu->arch.time_page) {
1460 kvm_release_page_dirty(vcpu->arch.time_page);
1461 vcpu->arch.time_page = NULL;
1462 }
1463}
1464
15c4a640
CO		 1465int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1466{
1467 switch (msr) {
15c4a640 1468 case MSR_EFER:
b69e8cae 1469 return set_efer(vcpu, data);
8f1589d9
AP		 1470 case MSR_K7_HWCR:
1471 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1472 data &= ~(u64)0x100; /* ignore ignne emulation enable */
8f1589d9
AP		 1473 if (data != 0) {
1474 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1475 data);
1476 return 1;
1477 }
15c4a640 1478 break;
f7c6d140
AP		 1479 case MSR_FAM10H_MMIO_CONF_BASE:
1480 if (data != 0) {
1481 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1482 "0x%llx\n", data);
1483 return 1;
1484 }
15c4a640 1485 break;
c323c0e5 1486 case MSR_AMD64_NB_CFG:
c7ac679c 1487 break;
b5e2fec0
AG		 1488 case MSR_IA32_DEBUGCTLMSR:
1489 if (!data) {
1490 /* We support the non-activated case already */
1491 break;
1492 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1493 /* Values other than LBR and BTF are vendor-specific,
1494 thus reserved and should throw a #GP */
1495 return 1;
1496 }
1497 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1498 __func__, data);
1499 break;
15c4a640
CO		 1500 case MSR_IA32_UCODE_REV:
1501 case MSR_IA32_UCODE_WRITE:
61a6bd67 1502 case MSR_VM_HSAVE_PA:
6098ca93 1503 case MSR_AMD64_PATCH_LOADER:
15c4a640 1504 break;
9ba075a6
AK		 1505 case 0x200 ... 0x2ff:
1506 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1507 case MSR_IA32_APICBASE:
1508 kvm_set_apic_base(vcpu, data);
1509 break;
0105d1a5
GN		 1510 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1511 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 1512 case MSR_IA32_MISC_ENABLE:
ad312c7c 1513 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1514 break;
11c6bffa 1515 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1516 case MSR_KVM_WALL_CLOCK:
1517 vcpu->kvm->arch.wall_clock = data;
1518 kvm_write_wall_clock(vcpu->kvm, data);
1519 break;
11c6bffa 1520 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 1521 case MSR_KVM_SYSTEM_TIME: {
12f9a48f 1522 kvmclock_reset(vcpu);
18068523
GOC		 1523
1524 vcpu->arch.time = data;
c285545f 1525 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
18068523
GOC		 1526
1527 /* we verify if the enable bit is set... */
1528 if (!(data & 1))
1529 break;
1530
1531 /* ...but clean it before doing the actual write */
1532 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1533
18068523
GOC		 1534 vcpu->arch.time_page =
1535 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1536
1537 if (is_error_page(vcpu->arch.time_page)) {
1538 kvm_release_page_clean(vcpu->arch.time_page);
1539 vcpu->arch.time_page = NULL;
1540 }
18068523
GOC		 1541 break;
1542 }
344d9588
GN		 1543 case MSR_KVM_ASYNC_PF_EN:
1544 if (kvm_pv_enable_async_pf(vcpu, data))
1545 return 1;
1546 break;
890ca9ae
HY		 1547 case MSR_IA32_MCG_CTL:
1548 case MSR_IA32_MCG_STATUS:
1549 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1550 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1551
1552 /* Performance counters are not protected by a CPUID bit,
1553 * so we should check all of them in the generic path for the sake of
1554 * cross vendor migration.
1555 * Writing a zero into the event select MSRs disables them,
1556 * which we perfectly emulate ;-). Any other value should be at least
1557 * reported, some guests depend on them.
1558 */
1559 case MSR_P6_EVNTSEL0:
1560 case MSR_P6_EVNTSEL1:
1561 case MSR_K7_EVNTSEL0:
1562 case MSR_K7_EVNTSEL1:
1563 case MSR_K7_EVNTSEL2:
1564 case MSR_K7_EVNTSEL3:
1565 if (data != 0)
1566 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1567 "0x%x data 0x%llx\n", msr, data);
1568 break;
1569 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1570 * so we ignore writes to make it happy.
1571 */
1572 case MSR_P6_PERFCTR0:
1573 case MSR_P6_PERFCTR1:
1574 case MSR_K7_PERFCTR0:
1575 case MSR_K7_PERFCTR1:
1576 case MSR_K7_PERFCTR2:
1577 case MSR_K7_PERFCTR3:
1578 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1579 "0x%x data 0x%llx\n", msr, data);
1580 break;
84e0cefa
JS		 1581 case MSR_K7_CLK_CTL:
1582 /*
1583 * Ignore all writes to this no longer documented MSR.
1584 * Writes are only relevant for old K7 processors,
1585 * all pre-dating SVM, but a recommended workaround from
1586 * AMD for these chips. It is possible to speicify the
1587 * affected processor models on the command line, hence
1588 * the need to ignore the workaround.
1589 */
1590 break;
55cd8e5a
GN		 1591 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1592 if (kvm_hv_msr_partition_wide(msr)) {
1593 int r;
1594 mutex_lock(&vcpu->kvm->lock);
1595 r = set_msr_hyperv_pw(vcpu, msr, data);
1596 mutex_unlock(&vcpu->kvm->lock);
1597 return r;
1598 } else
1599 return set_msr_hyperv(vcpu, msr, data);
1600 break;
91c9c3ed 1601 case MSR_IA32_BBL_CR_CTL3:
1602 /* Drop writes to this legacy MSR -- see rdmsr
1603 * counterpart for further detail.
1604 */
1605 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
1606 break;
15c4a640 1607 default:
ffde22ac
ES		 1608 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1609 return xen_hvm_config(vcpu, data);
ed85c068
AP		 1610 if (!ignore_msrs) {
1611 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1612 msr, data);
1613 return 1;
1614 } else {
1615 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1616 msr, data);
1617 break;
1618 }
15c4a640
CO		 1619 }
1620 return 0;
1621}
1622EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1623
1624
1625/*
1626 * Reads an msr value (of 'msr_index') into 'pdata'.
1627 * Returns 0 on success, non-0 otherwise.
1628 * Assumes vcpu_load() was already called.
1629 */
1630int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1631{
1632 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1633}
1634
9ba075a6
AK		 1635static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1636{
0bed3b56
SY		 1637 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1638
9ba075a6
AK		 1639 if (!msr_mtrr_valid(msr))
1640 return 1;
1641
0bed3b56
SY		 1642 if (msr == MSR_MTRRdefType)
1643 *pdata = vcpu->arch.mtrr_state.def_type +
1644 (vcpu->arch.mtrr_state.enabled << 10);
1645 else if (msr == MSR_MTRRfix64K_00000)
1646 *pdata = p[0];
1647 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1648 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1649 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1650 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1651 else if (msr == MSR_IA32_CR_PAT)
1652 *pdata = vcpu->arch.pat;
1653 else { /* Variable MTRRs */
1654 int idx, is_mtrr_mask;
1655 u64 *pt;
1656
1657 idx = (msr - 0x200) / 2;
1658 is_mtrr_mask = msr - 0x200 - 2 * idx;
1659 if (!is_mtrr_mask)
1660 pt =
1661 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1662 else
1663 pt =
1664 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1665 *pdata = *pt;
1666 }
1667
9ba075a6
AK		 1668 return 0;
1669}
1670
890ca9ae 1671static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1672{
1673 u64 data;
890ca9ae
HY		 1674 u64 mcg_cap = vcpu->arch.mcg_cap;
1675 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1676
1677 switch (msr) {
15c4a640
CO		 1678 case MSR_IA32_P5_MC_ADDR:
1679 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1680 data = 0;
1681 break;
15c4a640 1682 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1683 data = vcpu->arch.mcg_cap;
1684 break;
c7ac679c 1685 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1686 if (!(mcg_cap & MCG_CTL_P))
1687 return 1;
1688 data = vcpu->arch.mcg_ctl;
1689 break;
1690 case MSR_IA32_MCG_STATUS:
1691 data = vcpu->arch.mcg_status;
1692 break;
1693 default:
1694 if (msr >= MSR_IA32_MC0_CTL &&
1695 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1696 u32 offset = msr - MSR_IA32_MC0_CTL;
1697 data = vcpu->arch.mce_banks[offset];
1698 break;
1699 }
1700 return 1;
1701 }
1702 *pdata = data;
1703 return 0;
1704}
1705
55cd8e5a
GN		 1706static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1707{
1708 u64 data = 0;
1709 struct kvm *kvm = vcpu->kvm;
1710
1711 switch (msr) {
1712 case HV_X64_MSR_GUEST_OS_ID:
1713 data = kvm->arch.hv_guest_os_id;
1714 break;
1715 case HV_X64_MSR_HYPERCALL:
1716 data = kvm->arch.hv_hypercall;
1717 break;
1718 default:
1719 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1720 return 1;
1721 }
1722
1723 *pdata = data;
1724 return 0;
1725}
1726
1727static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1728{
1729 u64 data = 0;
1730
1731 switch (msr) {
1732 case HV_X64_MSR_VP_INDEX: {
1733 int r;
1734 struct kvm_vcpu *v;
1735 kvm_for_each_vcpu(r, v, vcpu->kvm)
1736 if (v == vcpu)
1737 data = r;
1738 break;
1739 }
10388a07
GN		 1740 case HV_X64_MSR_EOI:
1741 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1742 case HV_X64_MSR_ICR:
1743 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1744 case HV_X64_MSR_TPR:
1745 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
55cd8e5a
GN		 1746 default:
1747 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1748 return 1;
1749 }
1750 *pdata = data;
1751 return 0;
1752}
1753
890ca9ae
HY		 1754int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1755{
1756 u64 data;
1757
1758 switch (msr) {
890ca9ae 1759 case MSR_IA32_PLATFORM_ID:
15c4a640 1760 case MSR_IA32_UCODE_REV:
15c4a640 1761 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1762 case MSR_IA32_DEBUGCTLMSR:
1763 case MSR_IA32_LASTBRANCHFROMIP:
1764 case MSR_IA32_LASTBRANCHTOIP:
1765 case MSR_IA32_LASTINTFROMIP:
1766 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1767 case MSR_K8_SYSCFG:
1768 case MSR_K7_HWCR:
61a6bd67 1769 case MSR_VM_HSAVE_PA:
1f3ee616
AS		 1770 case MSR_P6_PERFCTR0:
1771 case MSR_P6_PERFCTR1:
7fe29e0f
AS		 1772 case MSR_P6_EVNTSEL0:
1773 case MSR_P6_EVNTSEL1:
9e699624 1774 case MSR_K7_EVNTSEL0:
1f3ee616 1775 case MSR_K7_PERFCTR0:
1fdbd48c 1776 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1777 case MSR_AMD64_NB_CFG:
f7c6d140 1778 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1779 data = 0;
1780 break;
9ba075a6
AK		 1781 case MSR_MTRRcap:
1782 data = 0x500 | KVM_NR_VAR_MTRR;
1783 break;
1784 case 0x200 ... 0x2ff:
1785 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1786 case 0xcd: /* fsb frequency */
1787 data = 3;
1788 break;
7b914098
JS		 1789 /*
1790 * MSR_EBC_FREQUENCY_ID
1791 * Conservative value valid for even the basic CPU models.
1792 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
1793 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
1794 * and 266MHz for model 3, or 4. Set Core Clock
1795 * Frequency to System Bus Frequency Ratio to 1 (bits
1796 * 31:24) even though these are only valid for CPU
1797 * models > 2, however guests may end up dividing or
1798 * multiplying by zero otherwise.
1799 */
1800 case MSR_EBC_FREQUENCY_ID:
1801 data = 1 << 24;
1802 break;
15c4a640
CO		 1803 case MSR_IA32_APICBASE:
1804 data = kvm_get_apic_base(vcpu);
1805 break;
0105d1a5
GN		 1806 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1807 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1808 break;
15c4a640 1809 case MSR_IA32_MISC_ENABLE:
ad312c7c 1810 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1811 break;
847f0ad8
AG		 1812 case MSR_IA32_PERF_STATUS:
1813 /* TSC increment by tick */
1814 data = 1000ULL;
1815 /* CPU multiplier */
1816 data |= (((uint64_t)4ULL) << 40);
1817 break;
15c4a640 1818 case MSR_EFER:
f6801dff 1819 data = vcpu->arch.efer;
15c4a640 1820 break;
18068523 1821 case MSR_KVM_WALL_CLOCK:
11c6bffa 1822 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1823 data = vcpu->kvm->arch.wall_clock;
1824 break;
1825 case MSR_KVM_SYSTEM_TIME:
11c6bffa 1826 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1827 data = vcpu->arch.time;
1828 break;
344d9588
GN		 1829 case MSR_KVM_ASYNC_PF_EN:
1830 data = vcpu->arch.apf.msr_val;
1831 break;
890ca9ae
HY		 1832 case MSR_IA32_P5_MC_ADDR:
1833 case MSR_IA32_P5_MC_TYPE:
1834 case MSR_IA32_MCG_CAP:
1835 case MSR_IA32_MCG_CTL:
1836 case MSR_IA32_MCG_STATUS:
1837 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1838 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 1839 case MSR_K7_CLK_CTL:
1840 /*
1841 * Provide expected ramp-up count for K7. All other
1842 * are set to zero, indicating minimum divisors for
1843 * every field.
1844 *
1845 * This prevents guest kernels on AMD host with CPU
1846 * type 6, model 8 and higher from exploding due to
1847 * the rdmsr failing.
1848 */
1849 data = 0x20000000;
1850 break;
55cd8e5a
GN		 1851 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1852 if (kvm_hv_msr_partition_wide(msr)) {
1853 int r;
1854 mutex_lock(&vcpu->kvm->lock);
1855 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1856 mutex_unlock(&vcpu->kvm->lock);
1857 return r;
1858 } else
1859 return get_msr_hyperv(vcpu, msr, pdata);
1860 break;
91c9c3ed 1861 case MSR_IA32_BBL_CR_CTL3:
1862 /* This legacy MSR exists but isn't fully documented in current
1863 * silicon. It is however accessed by winxp in very narrow
1864 * scenarios where it sets bit #19, itself documented as
1865 * a "reserved" bit. Best effort attempt to source coherent
1866 * read data here should the balance of the register be
1867 * interpreted by the guest:
1868 *
1869 * L2 cache control register 3: 64GB range, 256KB size,
1870 * enabled, latency 0x1, configured
1871 */
1872 data = 0xbe702111;
1873 break;
15c4a640 1874 default:
ed85c068
AP		 1875 if (!ignore_msrs) {
1876 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1877 return 1;
1878 } else {
1879 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1880 data = 0;
1881 }
1882 break;
15c4a640
CO		 1883 }
1884 *pdata = data;
1885 return 0;
1886}
1887EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1888
313a3dc7
CO		 1889/*
1890 * Read or write a bunch of msrs. All parameters are kernel addresses.
1891 *
1892 * @return number of msrs set successfully.
1893 */
1894static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1895 struct kvm_msr_entry *entries,
1896 int (*do_msr)(struct kvm_vcpu *vcpu,
1897 unsigned index, u64 *data))
1898{
f656ce01 1899 int i, idx;
313a3dc7 1900
f656ce01 1901 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 1902 for (i = 0; i < msrs->nmsrs; ++i)
1903 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1904 break;
f656ce01 1905 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 1906
313a3dc7
CO		 1907 return i;
1908}
1909
1910/*
1911 * Read or write a bunch of msrs. Parameters are user addresses.
1912 *
1913 * @return number of msrs set successfully.
1914 */
1915static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1916 int (*do_msr)(struct kvm_vcpu *vcpu,
1917 unsigned index, u64 *data),
1918 int writeback)
1919{
1920 struct kvm_msrs msrs;
1921 struct kvm_msr_entry *entries;
1922 int r, n;
1923 unsigned size;
1924
1925 r = -EFAULT;
1926 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1927 goto out;
1928
1929 r = -E2BIG;
1930 if (msrs.nmsrs >= MAX_IO_MSRS)
1931 goto out;
1932
1933 r = -ENOMEM;
1934 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
7a73c028 1935 entries = kmalloc(size, GFP_KERNEL);
313a3dc7
CO		 1936 if (!entries)
1937 goto out;
1938
1939 r = -EFAULT;
1940 if (copy_from_user(entries, user_msrs->entries, size))
1941 goto out_free;
1942
1943 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1944 if (r < 0)
1945 goto out_free;
1946
1947 r = -EFAULT;
1948 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1949 goto out_free;
1950
1951 r = n;
1952
1953out_free:
7a73c028 1954 kfree(entries);
313a3dc7
CO		 1955out:
1956 return r;
1957}
1958
018d00d2
ZX		 1959int kvm_dev_ioctl_check_extension(long ext)
1960{
1961 int r;
1962
1963 switch (ext) {
1964 case KVM_CAP_IRQCHIP:
1965 case KVM_CAP_HLT:
1966 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1967 case KVM_CAP_SET_TSS_ADDR:
07716717 1968 case KVM_CAP_EXT_CPUID:
c8076604 1969 case KVM_CAP_CLOCKSOURCE:
7837699f 1970 case KVM_CAP_PIT:
a28e4f5a 1971 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1972 case KVM_CAP_MP_STATE:
ed848624 1973 case KVM_CAP_SYNC_MMU:
a355c85c 1974 case KVM_CAP_USER_NMI:
52d939a0 1975 case KVM_CAP_REINJECT_CONTROL:
4925663a 1976 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1977 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1978 case KVM_CAP_IRQFD:
d34e6b17 1979 case KVM_CAP_IOEVENTFD:
c5ff41ce 1980 case KVM_CAP_PIT2:
e9f42757 1981 case KVM_CAP_PIT_STATE2:
b927a3ce 1982 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 1983 case KVM_CAP_XEN_HVM:
afbcf7ab 1984 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 1985 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 1986 case KVM_CAP_HYPERV:
10388a07 1987 case KVM_CAP_HYPERV_VAPIC:
c25bc163 1988 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 1989 case KVM_CAP_PCI_SEGMENT:
a1efbe77 1990 case KVM_CAP_DEBUGREGS:
d2be1651 1991 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 1992 case KVM_CAP_XSAVE:
344d9588 1993 case KVM_CAP_ASYNC_PF:
92a1f12d 1994 case KVM_CAP_GET_TSC_KHZ:
018d00d2
ZX		 1995 r = 1;
1996 break;
542472b5
LV		 1997 case KVM_CAP_COALESCED_MMIO:
1998 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1999 break;
774ead3a
AK		 2000 case KVM_CAP_VAPIC:
2001 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2002 break;
f725230a
AK		 2003 case KVM_CAP_NR_VCPUS:
2004 r = KVM_MAX_VCPUS;
2005 break;
a988b910
AK		 2006 case KVM_CAP_NR_MEMSLOTS:
2007 r = KVM_MEMORY_SLOTS;
2008 break;
a68a6a72
MT		 2009 case KVM_CAP_PV_MMU: /* obsolete */
2010 r = 0;
2f333bcb 2011 break;
62c476c7 2012 case KVM_CAP_IOMMU:
19de40a8 2013 r = iommu_found();
62c476c7 2014 break;
890ca9ae
HY		 2015 case KVM_CAP_MCE:
2016 r = KVM_MAX_MCE_BANKS;
2017 break;
2d5b5a66
SY		 2018 case KVM_CAP_XCRS:
2019 r = cpu_has_xsave;
2020 break;
92a1f12d
JR		 2021 case KVM_CAP_TSC_CONTROL:
2022 r = kvm_has_tsc_control;
2023 break;
018d00d2
ZX		 2024 default:
2025 r = 0;
2026 break;
2027 }
2028 return r;
2029
2030}
2031
043405e1
CO		 2032long kvm_arch_dev_ioctl(struct file *filp,
2033 unsigned int ioctl, unsigned long arg)
2034{
2035 void __user *argp = (void __user *)arg;
2036 long r;
2037
2038 switch (ioctl) {
2039 case KVM_GET_MSR_INDEX_LIST: {
2040 struct kvm_msr_list __user *user_msr_list = argp;
2041 struct kvm_msr_list msr_list;
2042 unsigned n;
2043
2044 r = -EFAULT;
2045 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2046 goto out;
2047 n = msr_list.nmsrs;
2048 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2049 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2050 goto out;
2051 r = -E2BIG;
e125e7b6 2052 if (n < msr_list.nmsrs)
043405e1
CO		 2053 goto out;
2054 r = -EFAULT;
2055 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2056 num_msrs_to_save * sizeof(u32)))
2057 goto out;
e125e7b6 2058 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2059 &emulated_msrs,
2060 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2061 goto out;
2062 r = 0;
2063 break;
2064 }
674eea0f
AK		 2065 case KVM_GET_SUPPORTED_CPUID: {
2066 struct kvm_cpuid2 __user *cpuid_arg = argp;
2067 struct kvm_cpuid2 cpuid;
2068
2069 r = -EFAULT;
2070 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2071 goto out;
2072 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 2073 cpuid_arg->entries);
674eea0f
AK		 2074 if (r)
2075 goto out;
2076
2077 r = -EFAULT;
2078 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2079 goto out;
2080 r = 0;
2081 break;
2082 }
890ca9ae
HY		 2083 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2084 u64 mce_cap;
2085
2086 mce_cap = KVM_MCE_CAP_SUPPORTED;
2087 r = -EFAULT;
2088 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2089 goto out;
2090 r = 0;
2091 break;
2092 }
043405e1
CO		 2093 default:
2094 r = -EINVAL;
2095 }
2096out:
2097 return r;
2098}
2099
f5f48ee1
SY		 2100static void wbinvd_ipi(void *garbage)
2101{
2102 wbinvd();
2103}
2104
2105static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2106{
2107 return vcpu->kvm->arch.iommu_domain &&
2108 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2109}
2110
313a3dc7
CO		 2111void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2112{
f5f48ee1
SY		 2113 /* Address WBINVD may be executed by guest */
2114 if (need_emulate_wbinvd(vcpu)) {
2115 if (kvm_x86_ops->has_wbinvd_exit())
2116 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2117 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2118 smp_call_function_single(vcpu->cpu,
2119 wbinvd_ipi, NULL, 1);
2120 }
2121
313a3dc7 2122 kvm_x86_ops->vcpu_load(vcpu, cpu);
48434c20 2123 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
e48672fa 2124 /* Make sure TSC doesn't go backwards */
8f6055cb
JR		 2125 s64 tsc_delta;
2126 u64 tsc;
2127
2128 kvm_get_msr(vcpu, MSR_IA32_TSC, &tsc);
2129 tsc_delta = !vcpu->arch.last_guest_tsc ? 0 :
2130 tsc - vcpu->arch.last_guest_tsc;
2131
e48672fa
ZA		 2132 if (tsc_delta < 0)
2133 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2134 if (check_tsc_unstable()) {
e48672fa 2135 kvm_x86_ops->adjust_tsc_offset(vcpu, -tsc_delta);
c285545f 2136 vcpu->arch.tsc_catchup = 1;
c285545f 2137 }
1aa8ceef 2138 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2139 if (vcpu->cpu != cpu)
2140 kvm_migrate_timers(vcpu);
e48672fa 2141 vcpu->cpu = cpu;
6b7d7e76 2142 }
313a3dc7
CO		 2143}
2144
2145void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2146{
02daab21 2147 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2148 kvm_put_guest_fpu(vcpu);
e48672fa 2149 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2150}
2151
07716717 2152static int is_efer_nx(void)
313a3dc7 2153{
e286e86e 2154 unsigned long long efer = 0;
313a3dc7 2155
e286e86e 2156 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 2157 return efer & EFER_NX;
2158}
2159
2160static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
2161{
2162 int i;
2163 struct kvm_cpuid_entry2 *e, *entry;
2164
313a3dc7 2165 entry = NULL;
ad312c7c
ZX		 2166 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
2167 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 2168 if (e->function == 0x80000001) {
2169 entry = e;
2170 break;
2171 }
2172 }
07716717 2173 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 2174 entry->edx &= ~(1 << 20);
2175 printk(KERN_INFO "kvm: guest NX capability removed\n");
2176 }
2177}
2178
07716717 2179/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 2180static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
2181 struct kvm_cpuid *cpuid,
2182 struct kvm_cpuid_entry __user *entries)
07716717
DK		 2183{
2184 int r, i;
2185 struct kvm_cpuid_entry *cpuid_entries;
2186
2187 r = -E2BIG;
2188 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2189 goto out;
2190 r = -ENOMEM;
2191 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
2192 if (!cpuid_entries)
2193 goto out;
2194 r = -EFAULT;
2195 if (copy_from_user(cpuid_entries, entries,
2196 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
2197 goto out_free;
2198 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 2199 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
2200 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
2201 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
2202 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
2203 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
2204 vcpu->arch.cpuid_entries[i].index = 0;
2205 vcpu->arch.cpuid_entries[i].flags = 0;
2206 vcpu->arch.cpuid_entries[i].padding[0] = 0;
2207 vcpu->arch.cpuid_entries[i].padding[1] = 0;
2208 vcpu->arch.cpuid_entries[i].padding[2] = 0;
2209 }
2210 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 2211 cpuid_fix_nx_cap(vcpu);
2212 r = 0;
fc61b800 2213 kvm_apic_set_version(vcpu);
0e851880 2214 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 2215 update_cpuid(vcpu);
07716717
DK		 2216
2217out_free:
2218 vfree(cpuid_entries);
2219out:
2220 return r;
2221}
2222
2223static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 2224 struct kvm_cpuid2 *cpuid,
2225 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 2226{
2227 int r;
2228
2229 r = -E2BIG;
2230 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2231 goto out;
2232 r = -EFAULT;
ad312c7c 2233 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 2234 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 2235 goto out;
ad312c7c 2236 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 2237 kvm_apic_set_version(vcpu);
0e851880 2238 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 2239 update_cpuid(vcpu);
313a3dc7
CO		 2240 return 0;
2241
2242out:
2243 return r;
2244}
2245
07716717 2246static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 2247 struct kvm_cpuid2 *cpuid,
2248 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2249{
2250 int r;
2251
2252 r = -E2BIG;
ad312c7c 2253 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 2254 goto out;
2255 r = -EFAULT;
ad312c7c 2256 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 2257 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2258 goto out;
2259 return 0;
2260
2261out:
ad312c7c 2262 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 2263 return r;
2264}
2265
945ee35e
AK		 2266static void cpuid_mask(u32 *word, int wordnum)
2267{
2268 *word &= boot_cpu_data.x86_capability[wordnum];
2269}
2270
07716717 2271static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 2272 u32 index)
07716717
DK		 2273{
2274 entry->function = function;
2275 entry->index = index;
2276 cpuid_count(entry->function, entry->index,
19355475 2277 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 2278 entry->flags = 0;
2279}
2280
7faa4ee1
AK		 2281#define F(x) bit(X86_FEATURE_##x)
2282
07716717
DK		 2283static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
2284 u32 index, int *nent, int maxnent)
2285{
7faa4ee1 2286 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 2287#ifdef CONFIG_X86_64
17cc3935
SY		 2288 unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
2289 ? F(GBPAGES) : 0;
7faa4ee1
AK		 2290 unsigned f_lm = F(LM);
2291#else
17cc3935 2292 unsigned f_gbpages = 0;
7faa4ee1 2293 unsigned f_lm = 0;
07716717 2294#endif
4e47c7a6 2295 unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
7faa4ee1
AK		 2296
2297 /* cpuid 1.edx */
2298 const u32 kvm_supported_word0_x86_features =
2299 F(FPU) | F(VME) | F(DE) | F(PSE) |
2300 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2301 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
2302 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2303 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
2304 0 /* Reserved, DS, ACPI */ | F(MMX) |
2305 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
2306 0 /* HTT, TM, Reserved, PBE */;
2307 /* cpuid 0x80000001.edx */
2308 const u32 kvm_supported_word1_x86_features =
2309 F(FPU) | F(VME) | F(DE) | F(PSE) |
2310 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2311 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
2312 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2313 F(PAT) | F(PSE36) | 0 /* Reserved */ |
2314 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
4e47c7a6 2315 F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
7faa4ee1
AK		 2316 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
2317 /* cpuid 1.ecx */
2318 const u32 kvm_supported_word4_x86_features =
6c3f6041 2319 F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ |
d149c731
AK		 2320 0 /* DS-CPL, VMX, SMX, EST */ |
2321 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
2322 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
2323 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 2324 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
6d886fd0
AP		 2325 0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) |
2326 F(F16C);
7faa4ee1 2327 /* cpuid 0x80000001.ecx */
07716717 2328 const u32 kvm_supported_word6_x86_features =
4c62a2dc 2329 F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ |
7faa4ee1 2330 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
7ef8aa72 2331 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(XOP) |
6d886fd0 2332 0 /* SKINIT, WDT, LWP */ | F(FMA4) | F(TBM);
07716717 2333
19355475 2334 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 2335 get_cpu();
2336 do_cpuid_1_ent(entry, function, index);
2337 ++*nent;
2338
2339 switch (function) {
2340 case 0:
2acf923e 2341 entry->eax = min(entry->eax, (u32)0xd);
07716717
DK		 2342 break;
2343 case 1:
2344 entry->edx &= kvm_supported_word0_x86_features;
945ee35e 2345 cpuid_mask(&entry->edx, 0);
7faa4ee1 2346 entry->ecx &= kvm_supported_word4_x86_features;
945ee35e 2347 cpuid_mask(&entry->ecx, 4);
0d1de2d9
GN		 2348 /* we support x2apic emulation even if host does not support
2349 * it since we emulate x2apic in software */
2350 entry->ecx |= F(X2APIC);
07716717
DK		 2351 break;
2352 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
2353 * may return different values. This forces us to get_cpu() before
2354 * issuing the first command, and also to emulate this annoying behavior
2355 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
2356 case 2: {
2357 int t, times = entry->eax & 0xff;
2358
2359 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 2360 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 2361 for (t = 1; t < times && *nent < maxnent; ++t) {
2362 do_cpuid_1_ent(&entry[t], function, 0);
2363 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
2364 ++*nent;
2365 }
2366 break;
2367 }
2368 /* function 4 and 0xb have additional index. */
2369 case 4: {
14af3f3c 2370 int i, cache_type;
07716717
DK		 2371
2372 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2373 /* read more entries until cache_type is zero */
14af3f3c
HH		 2374 for (i = 1; *nent < maxnent; ++i) {
2375 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 2376 if (!cache_type)
2377 break;
14af3f3c
HH		 2378 do_cpuid_1_ent(&entry[i], function, i);
2379 entry[i].flags |=
07716717
DK		 2380 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2381 ++*nent;
2382 }
2383 break;
2384 }
2385 case 0xb: {
14af3f3c 2386 int i, level_type;
07716717
DK		 2387
2388 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2389 /* read more entries until level_type is zero */
14af3f3c 2390 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 2391 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 2392 if (!level_type)
2393 break;
14af3f3c
HH		 2394 do_cpuid_1_ent(&entry[i], function, i);
2395 entry[i].flags |=
07716717
DK		 2396 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2397 ++*nent;
2398 }
2399 break;
2400 }
2acf923e
DC		 2401 case 0xd: {
2402 int i;
2403
2404 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
20800bc9
AP		 2405 for (i = 1; *nent < maxnent && i < 64; ++i) {
2406 if (entry[i].eax == 0)
2407 continue;
2acf923e
DC		 2408 do_cpuid_1_ent(&entry[i], function, i);
2409 entry[i].flags |=
2410 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2411 ++*nent;
2412 }
2413 break;
2414 }
84478c82
GC		 2415 case KVM_CPUID_SIGNATURE: {
2416 char signature[12] = "KVMKVMKVM\0\0";
2417 u32 *sigptr = (u32 *)signature;
2418 entry->eax = 0;
2419 entry->ebx = sigptr[0];
2420 entry->ecx = sigptr[1];
2421 entry->edx = sigptr[2];
2422 break;
2423 }
2424 case KVM_CPUID_FEATURES:
2425 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) |
2426 (1 << KVM_FEATURE_NOP_IO_DELAY) |
371bcf64 2427 (1 << KVM_FEATURE_CLOCKSOURCE2) |
32918924 2428 (1 << KVM_FEATURE_ASYNC_PF) |
371bcf64 2429 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
84478c82
GC		 2430 entry->ebx = 0;
2431 entry->ecx = 0;
2432 entry->edx = 0;
2433 break;
07716717
DK		 2434 case 0x80000000:
2435 entry->eax = min(entry->eax, 0x8000001a);
2436 break;
2437 case 0x80000001:
2438 entry->edx &= kvm_supported_word1_x86_features;
945ee35e 2439 cpuid_mask(&entry->edx, 1);
07716717 2440 entry->ecx &= kvm_supported_word6_x86_features;
945ee35e 2441 cpuid_mask(&entry->ecx, 6);
07716717
DK		 2442 break;
2443 }
d4330ef2
JR		 2444
2445 kvm_x86_ops->set_supported_cpuid(function, entry);
2446
07716717
DK		 2447 put_cpu();
2448}
2449
7faa4ee1
AK		 2450#undef F
2451
674eea0f 2452static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 2453 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2454{
2455 struct kvm_cpuid_entry2 *cpuid_entries;
2456 int limit, nent = 0, r = -E2BIG;
2457 u32 func;
2458
2459 if (cpuid->nent < 1)
2460 goto out;
6a544355
AK		 2461 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2462 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
07716717
DK		 2463 r = -ENOMEM;
2464 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
2465 if (!cpuid_entries)
2466 goto out;
2467
2468 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
2469 limit = cpuid_entries[0].eax;
2470 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
2471 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2472 &nent, cpuid->nent);
07716717
DK		 2473 r = -E2BIG;
2474 if (nent >= cpuid->nent)
2475 goto out_free;
2476
2477 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
2478 limit = cpuid_entries[nent - 1].eax;
2479 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
2480 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2481 &nent, cpuid->nent);
84478c82
GC		 2482
2483
2484
2485 r = -E2BIG;
2486 if (nent >= cpuid->nent)
2487 goto out_free;
2488
2489 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_SIGNATURE, 0, &nent,
2490 cpuid->nent);
2491
2492 r = -E2BIG;
2493 if (nent >= cpuid->nent)
2494 goto out_free;
2495
2496 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_FEATURES, 0, &nent,
2497 cpuid->nent);
2498
cb007648
MM		 2499 r = -E2BIG;
2500 if (nent >= cpuid->nent)
2501 goto out_free;
2502
07716717
DK		 2503 r = -EFAULT;
2504 if (copy_to_user(entries, cpuid_entries,
19355475 2505 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2506 goto out_free;
2507 cpuid->nent = nent;
2508 r = 0;
2509
2510out_free:
2511 vfree(cpuid_entries);
2512out:
2513 return r;
2514}
2515
313a3dc7
CO		 2516static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2517 struct kvm_lapic_state *s)
2518{
ad312c7c 2519 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2520
2521 return 0;
2522}
2523
2524static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2525 struct kvm_lapic_state *s)
2526{
ad312c7c 2527 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 2528 kvm_apic_post_state_restore(vcpu);
cb142eb7 2529 update_cr8_intercept(vcpu);
313a3dc7
CO		 2530
2531 return 0;
2532}
2533
f77bc6a4
ZX		 2534static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2535 struct kvm_interrupt *irq)
2536{
2537 if (irq->irq < 0 || irq->irq >= 256)
2538 return -EINVAL;
2539 if (irqchip_in_kernel(vcpu->kvm))
2540 return -ENXIO;
f77bc6a4 2541
66fd3f7f 2542 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2543 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2544
f77bc6a4
ZX		 2545 return 0;
2546}
2547
c4abb7c9
JK		 2548static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2549{
c4abb7c9 2550 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2551
2552 return 0;
2553}
2554
b209749f
AK		 2555static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2556 struct kvm_tpr_access_ctl *tac)
2557{
2558 if (tac->flags)
2559 return -EINVAL;
2560 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2561 return 0;
2562}
2563
890ca9ae
HY		 2564static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2565 u64 mcg_cap)
2566{
2567 int r;
2568 unsigned bank_num = mcg_cap & 0xff, bank;
2569
2570 r = -EINVAL;
a9e38c3e 2571 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2572 goto out;
2573 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2574 goto out;
2575 r = 0;
2576 vcpu->arch.mcg_cap = mcg_cap;
2577 /* Init IA32_MCG_CTL to all 1s */
2578 if (mcg_cap & MCG_CTL_P)
2579 vcpu->arch.mcg_ctl = ~(u64)0;
2580 /* Init IA32_MCi_CTL to all 1s */
2581 for (bank = 0; bank < bank_num; bank++)
2582 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2583out:
2584 return r;
2585}
2586
2587static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2588 struct kvm_x86_mce *mce)
2589{
2590 u64 mcg_cap = vcpu->arch.mcg_cap;
2591 unsigned bank_num = mcg_cap & 0xff;
2592 u64 *banks = vcpu->arch.mce_banks;
2593
2594 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2595 return -EINVAL;
2596 /*
2597 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2598 * reporting is disabled
2599 */
2600 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2601 vcpu->arch.mcg_ctl != ~(u64)0)
2602 return 0;
2603 banks += 4 * mce->bank;
2604 /*
2605 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2606 * reporting is disabled for the bank
2607 */
2608 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2609 return 0;
2610 if (mce->status & MCI_STATUS_UC) {
2611 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2612 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2613 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2614 return 0;
2615 }
2616 if (banks[1] & MCI_STATUS_VAL)
2617 mce->status |= MCI_STATUS_OVER;
2618 banks[2] = mce->addr;
2619 banks[3] = mce->misc;
2620 vcpu->arch.mcg_status = mce->mcg_status;
2621 banks[1] = mce->status;
2622 kvm_queue_exception(vcpu, MC_VECTOR);
2623 } else if (!(banks[1] & MCI_STATUS_VAL)
2624 || !(banks[1] & MCI_STATUS_UC)) {
2625 if (banks[1] & MCI_STATUS_VAL)
2626 mce->status |= MCI_STATUS_OVER;
2627 banks[2] = mce->addr;
2628 banks[3] = mce->misc;
2629 banks[1] = mce->status;
2630 } else
2631 banks[1] |= MCI_STATUS_OVER;
2632 return 0;
2633}
2634
3cfc3092
JK		 2635static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2636 struct kvm_vcpu_events *events)
2637{
03b82a30
JK		 2638 events->exception.injected =
2639 vcpu->arch.exception.pending &&
2640 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2641 events->exception.nr = vcpu->arch.exception.nr;
2642 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2643 events->exception.pad = 0;
3cfc3092
JK		 2644 events->exception.error_code = vcpu->arch.exception.error_code;
2645
03b82a30
JK		 2646 events->interrupt.injected =
2647 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2648 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2649 events->interrupt.soft = 0;
48005f64
JK		 2650 events->interrupt.shadow =
2651 kvm_x86_ops->get_interrupt_shadow(vcpu,
2652 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2653
2654 events->nmi.injected = vcpu->arch.nmi_injected;
2655 events->nmi.pending = vcpu->arch.nmi_pending;
2656 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2657 events->nmi.pad = 0;
3cfc3092
JK		 2658
2659 events->sipi_vector = vcpu->arch.sipi_vector;
2660
dab4b911 2661 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2662 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2663 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 2664 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2665}
2666
2667static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2668 struct kvm_vcpu_events *events)
2669{
dab4b911 2670 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2671 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2672 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2673 return -EINVAL;
2674
3cfc3092
JK		 2675 vcpu->arch.exception.pending = events->exception.injected;
2676 vcpu->arch.exception.nr = events->exception.nr;
2677 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2678 vcpu->arch.exception.error_code = events->exception.error_code;
2679
2680 vcpu->arch.interrupt.pending = events->interrupt.injected;
2681 vcpu->arch.interrupt.nr = events->interrupt.nr;
2682 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2683 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2684 kvm_x86_ops->set_interrupt_shadow(vcpu,
2685 events->interrupt.shadow);
3cfc3092
JK		 2686
2687 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2688 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2689 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2690 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2691
dab4b911
JK		 2692 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2693 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092 2694
3842d135
AK		 2695 kvm_make_request(KVM_REQ_EVENT, vcpu);
2696
3cfc3092
JK		 2697 return 0;
2698}
2699
a1efbe77
JK		 2700static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2701 struct kvm_debugregs *dbgregs)
2702{
a1efbe77
JK		 2703 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2704 dbgregs->dr6 = vcpu->arch.dr6;
2705 dbgregs->dr7 = vcpu->arch.dr7;
2706 dbgregs->flags = 0;
97e69aa6 2707 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 2708}
2709
2710static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2711 struct kvm_debugregs *dbgregs)
2712{
2713 if (dbgregs->flags)
2714 return -EINVAL;
2715
a1efbe77
JK		 2716 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2717 vcpu->arch.dr6 = dbgregs->dr6;
2718 vcpu->arch.dr7 = dbgregs->dr7;
2719
a1efbe77
JK		 2720 return 0;
2721}
2722
2d5b5a66
SY		 2723static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2724 struct kvm_xsave *guest_xsave)
2725{
2726 if (cpu_has_xsave)
2727 memcpy(guest_xsave->region,
2728 &vcpu->arch.guest_fpu.state->xsave,
f45755b8 2729 xstate_size);
2d5b5a66
SY		 2730 else {
2731 memcpy(guest_xsave->region,
2732 &vcpu->arch.guest_fpu.state->fxsave,
2733 sizeof(struct i387_fxsave_struct));
2734 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2735 XSTATE_FPSSE;
2736 }
2737}
2738
2739static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2740 struct kvm_xsave *guest_xsave)
2741{
2742 u64 xstate_bv =
2743 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2744
2745 if (cpu_has_xsave)
2746 memcpy(&vcpu->arch.guest_fpu.state->xsave,
f45755b8 2747 guest_xsave->region, xstate_size);
2d5b5a66
SY		 2748 else {
2749 if (xstate_bv & ~XSTATE_FPSSE)
2750 return -EINVAL;
2751 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2752 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2753 }
2754 return 0;
2755}
2756
2757static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2758 struct kvm_xcrs *guest_xcrs)
2759{
2760 if (!cpu_has_xsave) {
2761 guest_xcrs->nr_xcrs = 0;
2762 return;
2763 }
2764
2765 guest_xcrs->nr_xcrs = 1;
2766 guest_xcrs->flags = 0;
2767 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2768 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2769}
2770
2771static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2772 struct kvm_xcrs *guest_xcrs)
2773{
2774 int i, r = 0;
2775
2776 if (!cpu_has_xsave)
2777 return -EINVAL;
2778
2779 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2780 return -EINVAL;
2781
2782 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2783 /* Only support XCR0 currently */
2784 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2785 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2786 guest_xcrs->xcrs[0].value);
2787 break;
2788 }
2789 if (r)
2790 r = -EINVAL;
2791 return r;
2792}
2793
313a3dc7
CO		 2794long kvm_arch_vcpu_ioctl(struct file *filp,
2795 unsigned int ioctl, unsigned long arg)
2796{
2797 struct kvm_vcpu *vcpu = filp->private_data;
2798 void __user *argp = (void __user *)arg;
2799 int r;
d1ac91d8
AK		 2800 union {
2801 struct kvm_lapic_state *lapic;
2802 struct kvm_xsave *xsave;
2803 struct kvm_xcrs *xcrs;
2804 void *buffer;
2805 } u;
2806
2807 u.buffer = NULL;
313a3dc7
CO		 2808 switch (ioctl) {
2809 case KVM_GET_LAPIC: {
2204ae3c
MT		 2810 r = -EINVAL;
2811 if (!vcpu->arch.apic)
2812 goto out;
d1ac91d8 2813 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2814
b772ff36 2815 r = -ENOMEM;
d1ac91d8 2816 if (!u.lapic)
b772ff36 2817 goto out;
d1ac91d8 2818 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 2819 if (r)
2820 goto out;
2821 r = -EFAULT;
d1ac91d8 2822 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2823 goto out;
2824 r = 0;
2825 break;
2826 }
2827 case KVM_SET_LAPIC: {
2204ae3c
MT		 2828 r = -EINVAL;
2829 if (!vcpu->arch.apic)
2830 goto out;
d1ac91d8 2831 u.lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
b772ff36 2832 r = -ENOMEM;
d1ac91d8 2833 if (!u.lapic)
b772ff36 2834 goto out;
313a3dc7 2835 r = -EFAULT;
d1ac91d8 2836 if (copy_from_user(u.lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 2837 goto out;
d1ac91d8 2838 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 2839 if (r)
2840 goto out;
2841 r = 0;
2842 break;
2843 }
f77bc6a4
ZX		 2844 case KVM_INTERRUPT: {
2845 struct kvm_interrupt irq;
2846
2847 r = -EFAULT;
2848 if (copy_from_user(&irq, argp, sizeof irq))
2849 goto out;
2850 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2851 if (r)
2852 goto out;
2853 r = 0;
2854 break;
2855 }
c4abb7c9
JK		 2856 case KVM_NMI: {
2857 r = kvm_vcpu_ioctl_nmi(vcpu);
2858 if (r)
2859 goto out;
2860 r = 0;
2861 break;
2862 }
313a3dc7
CO		 2863 case KVM_SET_CPUID: {
2864 struct kvm_cpuid __user *cpuid_arg = argp;
2865 struct kvm_cpuid cpuid;
2866
2867 r = -EFAULT;
2868 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2869 goto out;
2870 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2871 if (r)
2872 goto out;
2873 break;
2874 }
07716717
DK		 2875 case KVM_SET_CPUID2: {
2876 struct kvm_cpuid2 __user *cpuid_arg = argp;
2877 struct kvm_cpuid2 cpuid;
2878
2879 r = -EFAULT;
2880 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2881 goto out;
2882 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2883 cpuid_arg->entries);
07716717
DK		 2884 if (r)
2885 goto out;
2886 break;
2887 }
2888 case KVM_GET_CPUID2: {
2889 struct kvm_cpuid2 __user *cpuid_arg = argp;
2890 struct kvm_cpuid2 cpuid;
2891
2892 r = -EFAULT;
2893 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2894 goto out;
2895 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2896 cpuid_arg->entries);
07716717
DK		 2897 if (r)
2898 goto out;
2899 r = -EFAULT;
2900 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2901 goto out;
2902 r = 0;
2903 break;
2904 }
313a3dc7
CO		 2905 case KVM_GET_MSRS:
2906 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2907 break;
2908 case KVM_SET_MSRS:
2909 r = msr_io(vcpu, argp, do_set_msr, 0);
2910 break;
b209749f
AK		 2911 case KVM_TPR_ACCESS_REPORTING: {
2912 struct kvm_tpr_access_ctl tac;
2913
2914 r = -EFAULT;
2915 if (copy_from_user(&tac, argp, sizeof tac))
2916 goto out;
2917 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2918 if (r)
2919 goto out;
2920 r = -EFAULT;
2921 if (copy_to_user(argp, &tac, sizeof tac))
2922 goto out;
2923 r = 0;
2924 break;
2925 };
b93463aa
AK		 2926 case KVM_SET_VAPIC_ADDR: {
2927 struct kvm_vapic_addr va;
2928
2929 r = -EINVAL;
2930 if (!irqchip_in_kernel(vcpu->kvm))
2931 goto out;
2932 r = -EFAULT;
2933 if (copy_from_user(&va, argp, sizeof va))
2934 goto out;
2935 r = 0;
2936 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2937 break;
2938 }
890ca9ae
HY		 2939 case KVM_X86_SETUP_MCE: {
2940 u64 mcg_cap;
2941
2942 r = -EFAULT;
2943 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2944 goto out;
2945 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2946 break;
2947 }
2948 case KVM_X86_SET_MCE: {
2949 struct kvm_x86_mce mce;
2950
2951 r = -EFAULT;
2952 if (copy_from_user(&mce, argp, sizeof mce))
2953 goto out;
2954 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2955 break;
2956 }
3cfc3092
JK		 2957 case KVM_GET_VCPU_EVENTS: {
2958 struct kvm_vcpu_events events;
2959
2960 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2961
2962 r = -EFAULT;
2963 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2964 break;
2965 r = 0;
2966 break;
2967 }
2968 case KVM_SET_VCPU_EVENTS: {
2969 struct kvm_vcpu_events events;
2970
2971 r = -EFAULT;
2972 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2973 break;
2974
2975 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2976 break;
2977 }
a1efbe77
JK		 2978 case KVM_GET_DEBUGREGS: {
2979 struct kvm_debugregs dbgregs;
2980
2981 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2982
2983 r = -EFAULT;
2984 if (copy_to_user(argp, &dbgregs,
2985 sizeof(struct kvm_debugregs)))
2986 break;
2987 r = 0;
2988 break;
2989 }
2990 case KVM_SET_DEBUGREGS: {
2991 struct kvm_debugregs dbgregs;
2992
2993 r = -EFAULT;
2994 if (copy_from_user(&dbgregs, argp,
2995 sizeof(struct kvm_debugregs)))
2996 break;
2997
2998 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
2999 break;
3000 }
2d5b5a66 3001 case KVM_GET_XSAVE: {
d1ac91d8 3002 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3003 r = -ENOMEM;
d1ac91d8 3004 if (!u.xsave)
2d5b5a66
SY		 3005 break;
3006
d1ac91d8 3007 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3008
3009 r = -EFAULT;
d1ac91d8 3010 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3011 break;
3012 r = 0;
3013 break;
3014 }
3015 case KVM_SET_XSAVE: {
d1ac91d8 3016 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3017 r = -ENOMEM;
d1ac91d8 3018 if (!u.xsave)
2d5b5a66
SY		 3019 break;
3020
3021 r = -EFAULT;
d1ac91d8 3022 if (copy_from_user(u.xsave, argp, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3023 break;
3024
d1ac91d8 3025 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3026 break;
3027 }
3028 case KVM_GET_XCRS: {
d1ac91d8 3029 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3030 r = -ENOMEM;
d1ac91d8 3031 if (!u.xcrs)
2d5b5a66
SY		 3032 break;
3033
d1ac91d8 3034 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3035
3036 r = -EFAULT;
d1ac91d8 3037 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3038 sizeof(struct kvm_xcrs)))
3039 break;
3040 r = 0;
3041 break;
3042 }
3043 case KVM_SET_XCRS: {
d1ac91d8 3044 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3045 r = -ENOMEM;
d1ac91d8 3046 if (!u.xcrs)
2d5b5a66
SY		 3047 break;
3048
3049 r = -EFAULT;
d1ac91d8 3050 if (copy_from_user(u.xcrs, argp,
2d5b5a66
SY		 3051 sizeof(struct kvm_xcrs)))
3052 break;
3053
d1ac91d8 3054 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3055 break;
3056 }
92a1f12d
JR		 3057 case KVM_SET_TSC_KHZ: {
3058 u32 user_tsc_khz;
3059
3060 r = -EINVAL;
3061 if (!kvm_has_tsc_control)
3062 break;
3063
3064 user_tsc_khz = (u32)arg;
3065
3066 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3067 goto out;
3068
3069 kvm_x86_ops->set_tsc_khz(vcpu, user_tsc_khz);
3070
3071 r = 0;
3072 goto out;
3073 }
3074 case KVM_GET_TSC_KHZ: {
3075 r = -EIO;
3076 if (check_tsc_unstable())
3077 goto out;
3078
3079 r = vcpu_tsc_khz(vcpu);
3080
3081 goto out;
3082 }
313a3dc7
CO		 3083 default:
3084 r = -EINVAL;
3085 }
3086out:
d1ac91d8 3087 kfree(u.buffer);
313a3dc7
CO		 3088 return r;
3089}
3090
1fe779f8
CO		 3091static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3092{
3093 int ret;
3094
3095 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3096 return -1;
3097 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3098 return ret;
3099}
3100
b927a3ce
SY		 3101static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3102 u64 ident_addr)
3103{
3104 kvm->arch.ept_identity_map_addr = ident_addr;
3105 return 0;
3106}
3107
1fe779f8
CO		 3108static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3109 u32 kvm_nr_mmu_pages)
3110{
3111 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3112 return -EINVAL;
3113
79fac95e 3114 mutex_lock(&kvm->slots_lock);
7c8a83b7 3115 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 3116
3117 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3118 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3119
7c8a83b7 3120 spin_unlock(&kvm->mmu_lock);
79fac95e 3121 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3122 return 0;
3123}
3124
3125static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3126{
39de71ec 3127 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3128}
3129
1fe779f8
CO		 3130static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3131{
3132 int r;
3133
3134 r = 0;
3135 switch (chip->chip_id) {
3136 case KVM_IRQCHIP_PIC_MASTER:
3137 memcpy(&chip->chip.pic,
3138 &pic_irqchip(kvm)->pics[0],
3139 sizeof(struct kvm_pic_state));
3140 break;
3141 case KVM_IRQCHIP_PIC_SLAVE:
3142 memcpy(&chip->chip.pic,
3143 &pic_irqchip(kvm)->pics[1],
3144 sizeof(struct kvm_pic_state));
3145 break;
3146 case KVM_IRQCHIP_IOAPIC:
eba0226b 3147 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3148 break;
3149 default:
3150 r = -EINVAL;
3151 break;
3152 }
3153 return r;
3154}
3155
3156static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3157{
3158 int r;
3159
3160 r = 0;
3161 switch (chip->chip_id) {
3162 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3163 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3164 memcpy(&pic_irqchip(kvm)->pics[0],
3165 &chip->chip.pic,
3166 sizeof(struct kvm_pic_state));
f4f51050 3167 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3168 break;
3169 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3170 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3171 memcpy(&pic_irqchip(kvm)->pics[1],
3172 &chip->chip.pic,
3173 sizeof(struct kvm_pic_state));
f4f51050 3174 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3175 break;
3176 case KVM_IRQCHIP_IOAPIC:
eba0226b 3177 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3178 break;
3179 default:
3180 r = -EINVAL;
3181 break;
3182 }
3183 kvm_pic_update_irq(pic_irqchip(kvm));
3184 return r;
3185}
3186
e0f63cb9
SY		 3187static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3188{
3189 int r = 0;
3190
894a9c55 3191 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3192 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3193 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3194 return r;
3195}
3196
3197static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3198{
3199 int r = 0;
3200
894a9c55 3201 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3202 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3203 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3204 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3205 return r;
3206}
3207
3208static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3209{
3210 int r = 0;
3211
3212 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3213 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3214 sizeof(ps->channels));
3215 ps->flags = kvm->arch.vpit->pit_state.flags;
3216 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3217 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3218 return r;
3219}
3220
3221static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3222{
3223 int r = 0, start = 0;
3224 u32 prev_legacy, cur_legacy;
3225 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3226 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3227 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3228 if (!prev_legacy && cur_legacy)
3229 start = 1;
3230 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3231 sizeof(kvm->arch.vpit->pit_state.channels));
3232 kvm->arch.vpit->pit_state.flags = ps->flags;
3233 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3234 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3235 return r;
3236}
3237
52d939a0
MT		 3238static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3239 struct kvm_reinject_control *control)
3240{
3241 if (!kvm->arch.vpit)
3242 return -ENXIO;
894a9c55 3243 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 3244 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 3245 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3246 return 0;
3247}
3248
5bb064dc
ZX		 3249/*
3250 * Get (and clear) the dirty memory log for a memory slot.
3251 */
3252int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
3253 struct kvm_dirty_log *log)
3254{
87bf6e7d 3255 int r, i;
5bb064dc 3256 struct kvm_memory_slot *memslot;
87bf6e7d 3257 unsigned long n;
b050b015 3258 unsigned long is_dirty = 0;
5bb064dc 3259
79fac95e 3260 mutex_lock(&kvm->slots_lock);
5bb064dc 3261
b050b015
MT		 3262 r = -EINVAL;
3263 if (log->slot >= KVM_MEMORY_SLOTS)
3264 goto out;
3265
3266 memslot = &kvm->memslots->memslots[log->slot];
3267 r = -ENOENT;
3268 if (!memslot->dirty_bitmap)
3269 goto out;
3270
87bf6e7d 3271 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3272
b050b015
MT		 3273 for (i = 0; !is_dirty && i < n/sizeof(long); i++)
3274 is_dirty = memslot->dirty_bitmap[i];
5bb064dc
ZX		 3275
3276 /* If nothing is dirty, don't bother messing with page tables. */
3277 if (is_dirty) {
b050b015 3278 struct kvm_memslots *slots, *old_slots;
914ebccd 3279 unsigned long *dirty_bitmap;
b050b015 3280
515a0127
TY		 3281 dirty_bitmap = memslot->dirty_bitmap_head;
3282 if (memslot->dirty_bitmap == dirty_bitmap)
3283 dirty_bitmap += n / sizeof(long);
914ebccd 3284 memset(dirty_bitmap, 0, n);
b050b015 3285
914ebccd
TY		 3286 r = -ENOMEM;
3287 slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
515a0127 3288 if (!slots)
914ebccd 3289 goto out;
b050b015
MT		 3290 memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
3291 slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
49c7754c 3292 slots->generation++;
b050b015
MT		 3293
3294 old_slots = kvm->memslots;
3295 rcu_assign_pointer(kvm->memslots, slots);
3296 synchronize_srcu_expedited(&kvm->srcu);
3297 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
3298 kfree(old_slots);
914ebccd 3299
edde99ce
MT		 3300 spin_lock(&kvm->mmu_lock);
3301 kvm_mmu_slot_remove_write_access(kvm, log->slot);
3302 spin_unlock(&kvm->mmu_lock);
3303
914ebccd 3304 r = -EFAULT;
515a0127 3305 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n))
914ebccd 3306 goto out;
914ebccd
TY		 3307 } else {
3308 r = -EFAULT;
3309 if (clear_user(log->dirty_bitmap, n))
3310 goto out;
5bb064dc 3311 }
b050b015 3312
5bb064dc
ZX		 3313 r = 0;
3314out:
79fac95e 3315 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3316 return r;
3317}
3318
1fe779f8
CO		 3319long kvm_arch_vm_ioctl(struct file *filp,
3320 unsigned int ioctl, unsigned long arg)
3321{
3322 struct kvm *kvm = filp->private_data;
3323 void __user *argp = (void __user *)arg;
367e1319 3324 int r = -ENOTTY;
f0d66275
DH		 3325 /*
3326 * This union makes it completely explicit to gcc-3.x
3327 * that these two variables' stack usage should be
3328 * combined, not added together.
3329 */
3330 union {
3331 struct kvm_pit_state ps;
e9f42757 3332 struct kvm_pit_state2 ps2;
c5ff41ce 3333 struct kvm_pit_config pit_config;
f0d66275 3334 } u;
1fe779f8
CO		 3335
3336 switch (ioctl) {
3337 case KVM_SET_TSS_ADDR:
3338 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3339 if (r < 0)
3340 goto out;
3341 break;
b927a3ce
SY		 3342 case KVM_SET_IDENTITY_MAP_ADDR: {
3343 u64 ident_addr;
3344
3345 r = -EFAULT;
3346 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3347 goto out;
3348 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3349 if (r < 0)
3350 goto out;
3351 break;
3352 }
1fe779f8
CO		 3353 case KVM_SET_NR_MMU_PAGES:
3354 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3355 if (r)
3356 goto out;
3357 break;
3358 case KVM_GET_NR_MMU_PAGES:
3359 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3360 break;
3ddea128
MT		 3361 case KVM_CREATE_IRQCHIP: {
3362 struct kvm_pic *vpic;
3363
3364 mutex_lock(&kvm->lock);
3365 r = -EEXIST;
3366 if (kvm->arch.vpic)
3367 goto create_irqchip_unlock;
1fe779f8 3368 r = -ENOMEM;
3ddea128
MT		 3369 vpic = kvm_create_pic(kvm);
3370 if (vpic) {
1fe779f8
CO		 3371 r = kvm_ioapic_init(kvm);
3372 if (r) {
175504cd 3373 mutex_lock(&kvm->slots_lock);
72bb2fcd
WY		 3374 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3375 &vpic->dev);
175504cd 3376 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3377 kfree(vpic);
3378 goto create_irqchip_unlock;
1fe779f8
CO		 3379 }
3380 } else
3ddea128
MT		 3381 goto create_irqchip_unlock;
3382 smp_wmb();
3383 kvm->arch.vpic = vpic;
3384 smp_wmb();
399ec807
AK		 3385 r = kvm_setup_default_irq_routing(kvm);
3386 if (r) {
175504cd 3387 mutex_lock(&kvm->slots_lock);
3ddea128 3388 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3389 kvm_ioapic_destroy(kvm);
3390 kvm_destroy_pic(kvm);
3ddea128 3391 mutex_unlock(&kvm->irq_lock);
175504cd 3392 mutex_unlock(&kvm->slots_lock);
399ec807 3393 }
3ddea128
MT		 3394 create_irqchip_unlock:
3395 mutex_unlock(&kvm->lock);
1fe779f8 3396 break;
3ddea128 3397 }
7837699f 3398 case KVM_CREATE_PIT:
c5ff41ce
JK		 3399 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3400 goto create_pit;
3401 case KVM_CREATE_PIT2:
3402 r = -EFAULT;
3403 if (copy_from_user(&u.pit_config, argp,
3404 sizeof(struct kvm_pit_config)))
3405 goto out;
3406 create_pit:
79fac95e 3407 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3408 r = -EEXIST;
3409 if (kvm->arch.vpit)
3410 goto create_pit_unlock;
7837699f 3411 r = -ENOMEM;
c5ff41ce 3412 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3413 if (kvm->arch.vpit)
3414 r = 0;
269e05e4 3415 create_pit_unlock:
79fac95e 3416 mutex_unlock(&kvm->slots_lock);
7837699f 3417 break;
4925663a 3418 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 3419 case KVM_IRQ_LINE: {
3420 struct kvm_irq_level irq_event;
3421
3422 r = -EFAULT;
3423 if (copy_from_user(&irq_event, argp, sizeof irq_event))
3424 goto out;
160d2f6c 3425 r = -ENXIO;
1fe779f8 3426 if (irqchip_in_kernel(kvm)) {
4925663a 3427 __s32 status;
4925663a
GN		 3428 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3429 irq_event.irq, irq_event.level);
4925663a 3430 if (ioctl == KVM_IRQ_LINE_STATUS) {
160d2f6c 3431 r = -EFAULT;
4925663a
GN		 3432 irq_event.status = status;
3433 if (copy_to_user(argp, &irq_event,
3434 sizeof irq_event))
3435 goto out;
3436 }
1fe779f8
CO		 3437 r = 0;
3438 }
3439 break;
3440 }
3441 case KVM_GET_IRQCHIP: {
3442 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3443 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3444
f0d66275
DH		 3445 r = -ENOMEM;
3446 if (!chip)
1fe779f8 3447 goto out;
f0d66275
DH		 3448 r = -EFAULT;
3449 if (copy_from_user(chip, argp, sizeof *chip))
3450 goto get_irqchip_out;
1fe779f8
CO		 3451 r = -ENXIO;
3452 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3453 goto get_irqchip_out;
3454 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3455 if (r)
f0d66275 3456 goto get_irqchip_out;
1fe779f8 3457 r = -EFAULT;
f0d66275
DH		 3458 if (copy_to_user(argp, chip, sizeof *chip))
3459 goto get_irqchip_out;
1fe779f8 3460 r = 0;
f0d66275
DH		 3461 get_irqchip_out:
3462 kfree(chip);
3463 if (r)
3464 goto out;
1fe779f8
CO		 3465 break;
3466 }
3467 case KVM_SET_IRQCHIP: {
3468 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3469 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3470
f0d66275
DH		 3471 r = -ENOMEM;
3472 if (!chip)
1fe779f8 3473 goto out;
f0d66275
DH		 3474 r = -EFAULT;
3475 if (copy_from_user(chip, argp, sizeof *chip))
3476 goto set_irqchip_out;
1fe779f8
CO		 3477 r = -ENXIO;
3478 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3479 goto set_irqchip_out;
3480 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3481 if (r)
f0d66275 3482 goto set_irqchip_out;
1fe779f8 3483 r = 0;
f0d66275
DH		 3484 set_irqchip_out:
3485 kfree(chip);
3486 if (r)
3487 goto out;
1fe779f8
CO		 3488 break;
3489 }
e0f63cb9 3490 case KVM_GET_PIT: {
e0f63cb9 3491 r = -EFAULT;
f0d66275 3492 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3493 goto out;
3494 r = -ENXIO;
3495 if (!kvm->arch.vpit)
3496 goto out;
f0d66275 3497 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3498 if (r)
3499 goto out;
3500 r = -EFAULT;
f0d66275 3501 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3502 goto out;
3503 r = 0;
3504 break;
3505 }
3506 case KVM_SET_PIT: {
e0f63cb9 3507 r = -EFAULT;
f0d66275 3508 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3509 goto out;
3510 r = -ENXIO;
3511 if (!kvm->arch.vpit)
3512 goto out;
f0d66275 3513 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3514 if (r)
3515 goto out;
3516 r = 0;
3517 break;
3518 }
e9f42757
BK		 3519 case KVM_GET_PIT2: {
3520 r = -ENXIO;
3521 if (!kvm->arch.vpit)
3522 goto out;
3523 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3524 if (r)
3525 goto out;
3526 r = -EFAULT;
3527 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3528 goto out;
3529 r = 0;
3530 break;
3531 }
3532 case KVM_SET_PIT2: {
3533 r = -EFAULT;
3534 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3535 goto out;
3536 r = -ENXIO;
3537 if (!kvm->arch.vpit)
3538 goto out;
3539 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3540 if (r)
3541 goto out;
3542 r = 0;
3543 break;
3544 }
52d939a0
MT		 3545 case KVM_REINJECT_CONTROL: {
3546 struct kvm_reinject_control control;
3547 r = -EFAULT;
3548 if (copy_from_user(&control, argp, sizeof(control)))
3549 goto out;
3550 r = kvm_vm_ioctl_reinject(kvm, &control);
3551 if (r)
3552 goto out;
3553 r = 0;
3554 break;
3555 }
ffde22ac
ES		 3556 case KVM_XEN_HVM_CONFIG: {
3557 r = -EFAULT;
3558 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3559 sizeof(struct kvm_xen_hvm_config)))
3560 goto out;
3561 r = -EINVAL;
3562 if (kvm->arch.xen_hvm_config.flags)
3563 goto out;
3564 r = 0;
3565 break;
3566 }
afbcf7ab 3567 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3568 struct kvm_clock_data user_ns;
3569 u64 now_ns;
3570 s64 delta;
3571
3572 r = -EFAULT;
3573 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3574 goto out;
3575
3576 r = -EINVAL;
3577 if (user_ns.flags)
3578 goto out;
3579
3580 r = 0;
395c6b0a 3581 local_irq_disable();
759379dd 3582 now_ns = get_kernel_ns();
afbcf7ab 3583 delta = user_ns.clock - now_ns;
395c6b0a 3584 local_irq_enable();
afbcf7ab
GC		 3585 kvm->arch.kvmclock_offset = delta;
3586 break;
3587 }
3588 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3589 struct kvm_clock_data user_ns;
3590 u64 now_ns;
3591
395c6b0a 3592 local_irq_disable();
759379dd 3593 now_ns = get_kernel_ns();
afbcf7ab 3594 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3595 local_irq_enable();
afbcf7ab 3596 user_ns.flags = 0;
97e69aa6 3597 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3598
3599 r = -EFAULT;
3600 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3601 goto out;
3602 r = 0;
3603 break;
3604 }
3605
1fe779f8
CO		 3606 default:
3607 ;
3608 }
3609out:
3610 return r;
3611}
3612
a16b043c 3613static void kvm_init_msr_list(void)
043405e1
CO		 3614{
3615 u32 dummy[2];
3616 unsigned i, j;
3617
e3267cbb
GC		 3618 /* skip the first msrs in the list. KVM-specific */
3619 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3620 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3621 continue;
3622 if (j < i)
3623 msrs_to_save[j] = msrs_to_save[i];
3624 j++;
3625 }
3626 num_msrs_to_save = j;
3627}
3628
bda9020e
MT		 3629static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3630 const void *v)
bbd9b64e 3631{
70252a10
AK		 3632 int handled = 0;
3633 int n;
3634
3635 do {
3636 n = min(len, 8);
3637 if (!(vcpu->arch.apic &&
3638 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3639 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3640 break;
3641 handled += n;
3642 addr += n;
3643 len -= n;
3644 v += n;
3645 } while (len);
bbd9b64e 3646
70252a10 3647 return handled;
bbd9b64e
CO		 3648}
3649
bda9020e 3650static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3651{
70252a10
AK		 3652 int handled = 0;
3653 int n;
3654
3655 do {
3656 n = min(len, 8);
3657 if (!(vcpu->arch.apic &&
3658 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3659 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3660 break;
3661 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3662 handled += n;
3663 addr += n;
3664 len -= n;
3665 v += n;
3666 } while (len);
bbd9b64e 3667
70252a10 3668 return handled;
bbd9b64e
CO		 3669}
3670
2dafc6c2
GN		 3671static void kvm_set_segment(struct kvm_vcpu *vcpu,
3672 struct kvm_segment *var, int seg)
3673{
3674 kvm_x86_ops->set_segment(vcpu, var, seg);
3675}
3676
3677void kvm_get_segment(struct kvm_vcpu *vcpu,
3678 struct kvm_segment *var, int seg)
3679{
3680 kvm_x86_ops->get_segment(vcpu, var, seg);
3681}
3682
c30a358d
JR		 3683static gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3684{
3685 return gpa;
3686}
3687
02f59dc9
JR		 3688static gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3689{
3690 gpa_t t_gpa;
ab9ae313 3691 struct x86_exception exception;
02f59dc9
JR		 3692
3693 BUG_ON(!mmu_is_nested(vcpu));
3694
3695 /* NPT walks are always user-walks */
3696 access |= PFERR_USER_MASK;
ab9ae313 3697 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
02f59dc9
JR		 3698
3699 return t_gpa;
3700}
3701
ab9ae313
AK		 3702gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3703 struct x86_exception *exception)
1871c602
GN		 3704{
3705 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 3706 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3707}
3708
ab9ae313
AK		 3709 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3710 struct x86_exception *exception)
1871c602
GN		 3711{
3712 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3713 access |= PFERR_FETCH_MASK;
ab9ae313 3714 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3715}
3716
ab9ae313
AK		 3717gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3718 struct x86_exception *exception)
1871c602
GN		 3719{
3720 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3721 access |= PFERR_WRITE_MASK;
ab9ae313 3722 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3723}
3724
3725/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 3726gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3727 struct x86_exception *exception)
1871c602 3728{
ab9ae313 3729 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 3730}
3731
3732static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3733 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 3734 struct x86_exception *exception)
bbd9b64e
CO		 3735{
3736 void *data = val;
10589a46 3737 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3738
3739 while (bytes) {
14dfe855 3740 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 3741 exception);
bbd9b64e 3742 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3743 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3744 int ret;
3745
bcc55cba 3746 if (gpa == UNMAPPED_GVA)
ab9ae313 3747 return X86EMUL_PROPAGATE_FAULT;
77c2002e 3748 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3749 if (ret < 0) {
c3cd7ffa 3750 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3751 goto out;
3752 }
bbd9b64e 3753
77c2002e
IE		 3754 bytes -= toread;
3755 data += toread;
3756 addr += toread;
bbd9b64e 3757 }
10589a46 3758out:
10589a46 3759 return r;
bbd9b64e 3760}
77c2002e 3761
1871c602
GN		 3762/* used for instruction fetching */
3763static int kvm_fetch_guest_virt(gva_t addr, void *val, unsigned int bytes,
bcc55cba
AK		 3764 struct kvm_vcpu *vcpu,
3765 struct x86_exception *exception)
1871c602
GN		 3766{
3767 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3768 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
bcc55cba
AK		 3769 access | PFERR_FETCH_MASK,
3770 exception);
1871c602
GN		 3771}
3772
3773static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
bcc55cba
AK		 3774 struct kvm_vcpu *vcpu,
3775 struct x86_exception *exception)
1871c602
GN		 3776{
3777 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3778 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 3779 exception);
1871c602
GN		 3780}
3781
3782static int kvm_read_guest_virt_system(gva_t addr, void *val, unsigned int bytes,
bcc55cba
AK		 3783 struct kvm_vcpu *vcpu,
3784 struct x86_exception *exception)
1871c602 3785{
bcc55cba 3786 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 3787}
3788
7972995b 3789static int kvm_write_guest_virt_system(gva_t addr, void *val,
2dafc6c2 3790 unsigned int bytes,
7972995b 3791 struct kvm_vcpu *vcpu,
bcc55cba 3792 struct x86_exception *exception)
77c2002e
IE		 3793{
3794 void *data = val;
3795 int r = X86EMUL_CONTINUE;
3796
3797 while (bytes) {
14dfe855
JR		 3798 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3799 PFERR_WRITE_MASK,
ab9ae313 3800 exception);
77c2002e
IE		 3801 unsigned offset = addr & (PAGE_SIZE-1);
3802 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3803 int ret;
3804
bcc55cba 3805 if (gpa == UNMAPPED_GVA)
ab9ae313 3806 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 3807 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3808 if (ret < 0) {
c3cd7ffa 3809 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 3810 goto out;
3811 }
3812
3813 bytes -= towrite;
3814 data += towrite;
3815 addr += towrite;
3816 }
3817out:
3818 return r;
3819}
3820
bbd9b64e
CO		 3821static int emulator_read_emulated(unsigned long addr,
3822 void *val,
3823 unsigned int bytes,
bcc55cba 3824 struct x86_exception *exception,
bbd9b64e
CO		 3825 struct kvm_vcpu *vcpu)
3826{
bbd9b64e 3827 gpa_t gpa;
70252a10 3828 int handled;
bbd9b64e
CO		 3829
3830 if (vcpu->mmio_read_completed) {
3831 memcpy(val, vcpu->mmio_data, bytes);
aec51dc4
AK		 3832 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3833 vcpu->mmio_phys_addr, *(u64 *)val);
bbd9b64e
CO		 3834 vcpu->mmio_read_completed = 0;
3835 return X86EMUL_CONTINUE;
3836 }
3837
ab9ae313 3838 gpa = kvm_mmu_gva_to_gpa_read(vcpu, addr, exception);
1871c602 3839
8fe681e9 3840 if (gpa == UNMAPPED_GVA)
1871c602 3841 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3842
3843 /* For APIC access vmexit */
3844 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3845 goto mmio;
3846
bcc55cba
AK		 3847 if (kvm_read_guest_virt(addr, val, bytes, vcpu, exception)
3848 == X86EMUL_CONTINUE)
bbd9b64e 3849 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3850
3851mmio:
3852 /*
3853 * Is this MMIO handled locally?
3854 */
70252a10
AK		 3855 handled = vcpu_mmio_read(vcpu, gpa, bytes, val);
3856
3857 if (handled == bytes)
bbd9b64e 3858 return X86EMUL_CONTINUE;
70252a10
AK		 3859
3860 gpa += handled;
3861 bytes -= handled;
3862 val += handled;
aec51dc4
AK		 3863
3864 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
bbd9b64e
CO		 3865
3866 vcpu->mmio_needed = 1;
411c35b7
GN		 3867 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3868 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
cef4dea0
AK		 3869 vcpu->mmio_size = bytes;
3870 vcpu->run->mmio.len = min(vcpu->mmio_size, 8);
411c35b7 3871 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 0;
cef4dea0 3872 vcpu->mmio_index = 0;
bbd9b64e 3873
c3cd7ffa 3874 return X86EMUL_IO_NEEDED;
bbd9b64e
CO		 3875}
3876
3200f405 3877int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 3878 const void *val, int bytes)
bbd9b64e
CO		 3879{
3880 int ret;
3881
3882 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3883 if (ret < 0)
bbd9b64e 3884 return 0;
ad218f85 3885 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 3886 return 1;
3887}
3888
3889static int emulator_write_emulated_onepage(unsigned long addr,
3890 const void *val,
3891 unsigned int bytes,
bcc55cba 3892 struct x86_exception *exception,
bbd9b64e
CO		 3893 struct kvm_vcpu *vcpu)
3894{
10589a46 3895 gpa_t gpa;
70252a10 3896 int handled;
10589a46 3897
ab9ae313 3898 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, exception);
bbd9b64e 3899
8fe681e9 3900 if (gpa == UNMAPPED_GVA)
bbd9b64e 3901 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3902
3903 /* For APIC access vmexit */
3904 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3905 goto mmio;
3906
3907 if (emulator_write_phys(vcpu, gpa, val, bytes))
3908 return X86EMUL_CONTINUE;
3909
3910mmio:
aec51dc4 3911 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3912 /*
3913 * Is this MMIO handled locally?
3914 */
70252a10
AK		 3915 handled = vcpu_mmio_write(vcpu, gpa, bytes, val);
3916 if (handled == bytes)
bbd9b64e 3917 return X86EMUL_CONTINUE;
bbd9b64e 3918
70252a10
AK		 3919 gpa += handled;
3920 bytes -= handled;
3921 val += handled;
3922
bbd9b64e 3923 vcpu->mmio_needed = 1;
cef4dea0 3924 memcpy(vcpu->mmio_data, val, bytes);
411c35b7
GN		 3925 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3926 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
cef4dea0
AK		 3927 vcpu->mmio_size = bytes;
3928 vcpu->run->mmio.len = min(vcpu->mmio_size, 8);
411c35b7 3929 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 1;
cef4dea0
AK		 3930 memcpy(vcpu->run->mmio.data, vcpu->mmio_data, 8);
3931 vcpu->mmio_index = 0;
bbd9b64e
CO		 3932
3933 return X86EMUL_CONTINUE;
3934}
3935
3936int emulator_write_emulated(unsigned long addr,
8f6abd06
GN		 3937 const void *val,
3938 unsigned int bytes,
bcc55cba 3939 struct x86_exception *exception,
8f6abd06 3940 struct kvm_vcpu *vcpu)
bbd9b64e
CO		 3941{
3942 /* Crossing a page boundary? */
3943 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3944 int rc, now;
3945
3946 now = -addr & ~PAGE_MASK;
bcc55cba 3947 rc = emulator_write_emulated_onepage(addr, val, now, exception,
8fe681e9 3948 vcpu);
bbd9b64e
CO		 3949 if (rc != X86EMUL_CONTINUE)
3950 return rc;
3951 addr += now;
3952 val += now;
3953 bytes -= now;
3954 }
bcc55cba 3955 return emulator_write_emulated_onepage(addr, val, bytes, exception,
8fe681e9 3956 vcpu);
bbd9b64e 3957}
bbd9b64e 3958
daea3e73
AK		 3959#define CMPXCHG_TYPE(t, ptr, old, new) \
3960 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
3961
3962#ifdef CONFIG_X86_64
3963# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
3964#else
3965# define CMPXCHG64(ptr, old, new) \
9749a6c0 3966 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 3967#endif
3968
bbd9b64e
CO		 3969static int emulator_cmpxchg_emulated(unsigned long addr,
3970 const void *old,
3971 const void *new,
3972 unsigned int bytes,
bcc55cba 3973 struct x86_exception *exception,
bbd9b64e
CO		 3974 struct kvm_vcpu *vcpu)
3975{
daea3e73
AK		 3976 gpa_t gpa;
3977 struct page *page;
3978 char *kaddr;
3979 bool exchanged;
2bacc55c 3980
daea3e73
AK		 3981 /* guests cmpxchg8b have to be emulated atomically */
3982 if (bytes > 8 || (bytes & (bytes - 1)))
3983 goto emul_write;
10589a46 3984
daea3e73 3985 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 3986
daea3e73
AK		 3987 if (gpa == UNMAPPED_GVA ||
3988 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3989 goto emul_write;
2bacc55c 3990
daea3e73
AK		 3991 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
3992 goto emul_write;
72dc67a6 3993
daea3e73 3994 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
c19b8bd6
WY		 3995 if (is_error_page(page)) {
3996 kvm_release_page_clean(page);
3997 goto emul_write;
3998 }
72dc67a6 3999
daea3e73
AK		 4000 kaddr = kmap_atomic(page, KM_USER0);
4001 kaddr += offset_in_page(gpa);
4002 switch (bytes) {
4003 case 1:
4004 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4005 break;
4006 case 2:
4007 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4008 break;
4009 case 4:
4010 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4011 break;
4012 case 8:
4013 exchanged = CMPXCHG64(kaddr, old, new);
4014 break;
4015 default:
4016 BUG();
2bacc55c 4017 }
daea3e73
AK		 4018 kunmap_atomic(kaddr, KM_USER0);
4019 kvm_release_page_dirty(page);
4020
4021 if (!exchanged)
4022 return X86EMUL_CMPXCHG_FAILED;
4023
8f6abd06
GN		 4024 kvm_mmu_pte_write(vcpu, gpa, new, bytes, 1);
4025
4026 return X86EMUL_CONTINUE;
4a5f48f6 4027
3200f405 4028emul_write:
daea3e73 4029 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4030
bcc55cba 4031 return emulator_write_emulated(addr, new, bytes, exception, vcpu);
bbd9b64e
CO		 4032}
4033
cf8f70bf
GN		 4034static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4035{
4036 /* TODO: String I/O for in kernel device */
4037 int r;
4038
4039 if (vcpu->arch.pio.in)
4040 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4041 vcpu->arch.pio.size, pd);
4042 else
4043 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4044 vcpu->arch.pio.port, vcpu->arch.pio.size,
4045 pd);
4046 return r;
4047}
4048
4049
4050static int emulator_pio_in_emulated(int size, unsigned short port, void *val,
4051 unsigned int count, struct kvm_vcpu *vcpu)
4052{
7972995b 4053 if (vcpu->arch.pio.count)
cf8f70bf
GN		 4054 goto data_avail;
4055
61cfab2e 4056 trace_kvm_pio(0, port, size, count);
cf8f70bf
GN		 4057
4058 vcpu->arch.pio.port = port;
4059 vcpu->arch.pio.in = 1;
7972995b 4060 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4061 vcpu->arch.pio.size = size;
4062
4063 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4064 data_avail:
4065 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 4066 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4067 return 1;
4068 }
4069
4070 vcpu->run->exit_reason = KVM_EXIT_IO;
4071 vcpu->run->io.direction = KVM_EXIT_IO_IN;
4072 vcpu->run->io.size = size;
4073 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4074 vcpu->run->io.count = count;
4075 vcpu->run->io.port = port;
4076
4077 return 0;
4078}
4079
4080static int emulator_pio_out_emulated(int size, unsigned short port,
4081 const void *val, unsigned int count,
4082 struct kvm_vcpu *vcpu)
4083{
61cfab2e 4084 trace_kvm_pio(1, port, size, count);
cf8f70bf
GN		 4085
4086 vcpu->arch.pio.port = port;
4087 vcpu->arch.pio.in = 0;
7972995b 4088 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4089 vcpu->arch.pio.size = size;
4090
4091 memcpy(vcpu->arch.pio_data, val, size * count);
4092
4093 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4094 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4095 return 1;
4096 }
4097
4098 vcpu->run->exit_reason = KVM_EXIT_IO;
4099 vcpu->run->io.direction = KVM_EXIT_IO_OUT;
4100 vcpu->run->io.size = size;
4101 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4102 vcpu->run->io.count = count;
4103 vcpu->run->io.port = port;
4104
4105 return 0;
4106}
4107
bbd9b64e
CO		 4108static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4109{
4110 return kvm_x86_ops->get_segment_base(vcpu, seg);
4111}
4112
4113int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
4114{
a7052897 4115 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 4116 return X86EMUL_CONTINUE;
4117}
4118
f5f48ee1
SY		 4119int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4120{
4121 if (!need_emulate_wbinvd(vcpu))
4122 return X86EMUL_CONTINUE;
4123
4124 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4125 int cpu = get_cpu();
4126
4127 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4128 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4129 wbinvd_ipi, NULL, 1);
2eec7343 4130 put_cpu();
f5f48ee1 4131 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4132 } else
4133 wbinvd();
f5f48ee1
SY		 4134 return X86EMUL_CONTINUE;
4135}
4136EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4137
bbd9b64e
CO		 4138int emulate_clts(struct kvm_vcpu *vcpu)
4139{
4d4ec087 4140 kvm_x86_ops->set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
6b52d186 4141 kvm_x86_ops->fpu_activate(vcpu);
bbd9b64e
CO		 4142 return X86EMUL_CONTINUE;
4143}
4144
35aa5375 4145int emulator_get_dr(int dr, unsigned long *dest, struct kvm_vcpu *vcpu)
bbd9b64e 4146{
338dbc97 4147 return _kvm_get_dr(vcpu, dr, dest);
bbd9b64e
CO		 4148}
4149
35aa5375 4150int emulator_set_dr(int dr, unsigned long value, struct kvm_vcpu *vcpu)
bbd9b64e 4151{
338dbc97
GN		 4152
4153 return __kvm_set_dr(vcpu, dr, value);
bbd9b64e
CO		 4154}
4155
52a46617 4156static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4157{
52a46617 4158 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4159}
4160
52a46617 4161static unsigned long emulator_get_cr(int cr, struct kvm_vcpu *vcpu)
bbd9b64e 4162{
52a46617
GN		 4163 unsigned long value;
4164
4165 switch (cr) {
4166 case 0:
4167 value = kvm_read_cr0(vcpu);
4168 break;
4169 case 2:
4170 value = vcpu->arch.cr2;
4171 break;
4172 case 3:
9f8fe504 4173 value = kvm_read_cr3(vcpu);
52a46617
GN		 4174 break;
4175 case 4:
4176 value = kvm_read_cr4(vcpu);
4177 break;
4178 case 8:
4179 value = kvm_get_cr8(vcpu);
4180 break;
4181 default:
4182 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
4183 return 0;
4184 }
4185
4186 return value;
4187}
4188
0f12244f 4189static int emulator_set_cr(int cr, unsigned long val, struct kvm_vcpu *vcpu)
52a46617 4190{
0f12244f
GN		 4191 int res = 0;
4192
52a46617
GN		 4193 switch (cr) {
4194 case 0:
49a9b07e 4195 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4196 break;
4197 case 2:
4198 vcpu->arch.cr2 = val;
4199 break;
4200 case 3:
2390218b 4201 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4202 break;
4203 case 4:
a83b29c6 4204 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4205 break;
4206 case 8:
eea1cff9 4207 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4208 break;
4209 default:
4210 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
0f12244f 4211 res = -1;
52a46617 4212 }
0f12244f
GN		 4213
4214 return res;
52a46617
GN		 4215}
4216
9c537244
GN		 4217static int emulator_get_cpl(struct kvm_vcpu *vcpu)
4218{
4219 return kvm_x86_ops->get_cpl(vcpu);
4220}
4221
2dafc6c2
GN		 4222static void emulator_get_gdt(struct desc_ptr *dt, struct kvm_vcpu *vcpu)
4223{
4224 kvm_x86_ops->get_gdt(vcpu, dt);
4225}
4226
160ce1f1
MG		 4227static void emulator_get_idt(struct desc_ptr *dt, struct kvm_vcpu *vcpu)
4228{
4229 kvm_x86_ops->get_idt(vcpu, dt);
4230}
4231
5951c442
GN		 4232static unsigned long emulator_get_cached_segment_base(int seg,
4233 struct kvm_vcpu *vcpu)
4234{
4235 return get_segment_base(vcpu, seg);
4236}
4237
5601d05b
GN		 4238static bool emulator_get_cached_descriptor(struct desc_struct *desc, u32 *base3,
4239 int seg, struct kvm_vcpu *vcpu)
2dafc6c2
GN		 4240{
4241 struct kvm_segment var;
4242
4243 kvm_get_segment(vcpu, &var, seg);
4244
4245 if (var.unusable)
4246 return false;
4247
4248 if (var.g)
4249 var.limit >>= 12;
4250 set_desc_limit(desc, var.limit);
4251 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4252#ifdef CONFIG_X86_64
4253 if (base3)
4254 *base3 = var.base >> 32;
4255#endif
2dafc6c2
GN		 4256 desc->type = var.type;
4257 desc->s = var.s;
4258 desc->dpl = var.dpl;
4259 desc->p = var.present;
4260 desc->avl = var.avl;
4261 desc->l = var.l;
4262 desc->d = var.db;
4263 desc->g = var.g;
4264
4265 return true;
4266}
4267
5601d05b
GN		 4268static void emulator_set_cached_descriptor(struct desc_struct *desc, u32 base3,
4269 int seg, struct kvm_vcpu *vcpu)
2dafc6c2
GN		 4270{
4271 struct kvm_segment var;
4272
4273 /* needed to preserve selector */
4274 kvm_get_segment(vcpu, &var, seg);
4275
4276 var.base = get_desc_base(desc);
5601d05b
GN		 4277#ifdef CONFIG_X86_64
4278 var.base |= ((u64)base3) << 32;
4279#endif
2dafc6c2
GN		 4280 var.limit = get_desc_limit(desc);
4281 if (desc->g)
4282 var.limit = (var.limit << 12) | 0xfff;
4283 var.type = desc->type;
4284 var.present = desc->p;
4285 var.dpl = desc->dpl;
4286 var.db = desc->d;
4287 var.s = desc->s;
4288 var.l = desc->l;
4289 var.g = desc->g;
4290 var.avl = desc->avl;
4291 var.present = desc->p;
4292 var.unusable = !var.present;
4293 var.padding = 0;
4294
4295 kvm_set_segment(vcpu, &var, seg);
4296 return;
4297}
4298
4299static u16 emulator_get_segment_selector(int seg, struct kvm_vcpu *vcpu)
4300{
4301 struct kvm_segment kvm_seg;
4302
4303 kvm_get_segment(vcpu, &kvm_seg, seg);
4304 return kvm_seg.selector;
4305}
4306
4307static void emulator_set_segment_selector(u16 sel, int seg,
4308 struct kvm_vcpu *vcpu)
4309{
4310 struct kvm_segment kvm_seg;
4311
4312 kvm_get_segment(vcpu, &kvm_seg, seg);
4313 kvm_seg.selector = sel;
4314 kvm_set_segment(vcpu, &kvm_seg, seg);
4315}
4316
5037f6f3
AK		 4317static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4318{
4319 preempt_disable();
4320 kvm_load_guest_fpu(ctxt->vcpu);
4321 /*
4322 * CR0.TS may reference the host fpu state, not the guest fpu state,
4323 * so it may be clear at this point.
4324 */
4325 clts();
4326}
4327
4328static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4329{
4330 preempt_enable();
4331}
4332
8a76d7f2
JR		 4333static int emulator_intercept(struct kvm_vcpu *vcpu,
4334 struct x86_instruction_info *info,
c4f035c6
AK		 4335 enum x86_intercept_stage stage)
4336{
8a76d7f2 4337 return kvm_x86_ops->check_intercept(vcpu, info, stage);
c4f035c6
AK		 4338}
4339
14af3f3c 4340static struct x86_emulate_ops emulate_ops = {
1871c602 4341 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4342 .write_std = kvm_write_guest_virt_system,
1871c602 4343 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4344 .read_emulated = emulator_read_emulated,
4345 .write_emulated = emulator_write_emulated,
4346 .cmpxchg_emulated = emulator_cmpxchg_emulated,
cf8f70bf
GN		 4347 .pio_in_emulated = emulator_pio_in_emulated,
4348 .pio_out_emulated = emulator_pio_out_emulated,
2dafc6c2
GN		 4349 .get_cached_descriptor = emulator_get_cached_descriptor,
4350 .set_cached_descriptor = emulator_set_cached_descriptor,
4351 .get_segment_selector = emulator_get_segment_selector,
4352 .set_segment_selector = emulator_set_segment_selector,
5951c442 4353 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4354 .get_gdt = emulator_get_gdt,
160ce1f1 4355 .get_idt = emulator_get_idt,
52a46617
GN		 4356 .get_cr = emulator_get_cr,
4357 .set_cr = emulator_set_cr,
9c537244 4358 .cpl = emulator_get_cpl,
35aa5375
GN		 4359 .get_dr = emulator_get_dr,
4360 .set_dr = emulator_set_dr,
3fb1b5db
GN		 4361 .set_msr = kvm_set_msr,
4362 .get_msr = kvm_get_msr,
5037f6f3
AK		 4363 .get_fpu = emulator_get_fpu,
4364 .put_fpu = emulator_put_fpu,
c4f035c6 4365 .intercept = emulator_intercept,
bbd9b64e
CO		 4366};
4367
5fdbf976
MT		 4368static void cache_all_regs(struct kvm_vcpu *vcpu)
4369{
4370 kvm_register_read(vcpu, VCPU_REGS_RAX);
4371 kvm_register_read(vcpu, VCPU_REGS_RSP);
4372 kvm_register_read(vcpu, VCPU_REGS_RIP);
4373 vcpu->arch.regs_dirty = ~0;
4374}
4375
95cb2295
GN		 4376static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4377{
4378 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4379 /*
4380 * an sti; sti; sequence only disable interrupts for the first
4381 * instruction. So, if the last instruction, be it emulated or
4382 * not, left the system with the INT_STI flag enabled, it
4383 * means that the last instruction is an sti. We should not
4384 * leave the flag on in this case. The same goes for mov ss
4385 */
4386 if (!(int_shadow & mask))
4387 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4388}
4389
54b8486f
GN		 4390static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4391{
4392 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4393 if (ctxt->exception.vector == PF_VECTOR)
6389ee94 4394 kvm_propagate_fault(vcpu, &ctxt->exception);
da9cb575
AK		 4395 else if (ctxt->exception.error_code_valid)
4396 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4397 ctxt->exception.error_code);
54b8486f 4398 else
da9cb575 4399 kvm_queue_exception(vcpu, ctxt->exception.vector);
54b8486f
GN		 4400}
4401
8ec4722d
MG		 4402static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4403{
4404 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
4405 int cs_db, cs_l;
4406
4407 cache_all_regs(vcpu);
4408
4409 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4410
4411 vcpu->arch.emulate_ctxt.vcpu = vcpu;
f6e78475 4412 vcpu->arch.emulate_ctxt.eflags = kvm_get_rflags(vcpu);
8ec4722d
MG		 4413 vcpu->arch.emulate_ctxt.eip = kvm_rip_read(vcpu);
4414 vcpu->arch.emulate_ctxt.mode =
4415 (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4416 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
4417 ? X86EMUL_MODE_VM86 : cs_l
4418 ? X86EMUL_MODE_PROT64 : cs_db
4419 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
c4f035c6 4420 vcpu->arch.emulate_ctxt.guest_mode = is_guest_mode(vcpu);
8ec4722d
MG		 4421 memset(c, 0, sizeof(struct decode_cache));
4422 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
7ae441ea 4423 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4424}
4425
63995653
MG		 4426int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq)
4427{
4428 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
4429 int ret;
4430
4431 init_emulate_ctxt(vcpu);
4432
4433 vcpu->arch.emulate_ctxt.decode.op_bytes = 2;
4434 vcpu->arch.emulate_ctxt.decode.ad_bytes = 2;
4435 vcpu->arch.emulate_ctxt.decode.eip = vcpu->arch.emulate_ctxt.eip;
4436 ret = emulate_int_real(&vcpu->arch.emulate_ctxt, &emulate_ops, irq);
4437
4438 if (ret != X86EMUL_CONTINUE)
4439 return EMULATE_FAIL;
4440
4441 vcpu->arch.emulate_ctxt.eip = c->eip;
4442 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
4443 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
f6e78475 4444 kvm_set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
63995653
MG		 4445
4446 if (irq == NMI_VECTOR)
4447 vcpu->arch.nmi_pending = false;
4448 else
4449 vcpu->arch.interrupt.pending = false;
4450
4451 return EMULATE_DONE;
4452}
4453EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4454
6d77dbfc
GN		 4455static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4456{
fc3a9157
JR		 4457 int r = EMULATE_DONE;
4458
6d77dbfc
GN		 4459 ++vcpu->stat.insn_emulation_fail;
4460 trace_kvm_emulate_insn_failed(vcpu);
fc3a9157
JR		 4461 if (!is_guest_mode(vcpu)) {
4462 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4463 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4464 vcpu->run->internal.ndata = 0;
4465 r = EMULATE_FAIL;
4466 }
6d77dbfc 4467 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4468
4469 return r;
6d77dbfc
GN		 4470}
4471
a6f177ef
GN		 4472static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
4473{
4474 gpa_t gpa;
4475
68be0803
GN		 4476 if (tdp_enabled)
4477 return false;
4478
a6f177ef
GN		 4479 /*
4480 * if emulation was due to access to shadowed page table
4481 * and it failed try to unshadow page and re-entetr the
4482 * guest to let CPU execute the instruction.
4483 */
4484 if (kvm_mmu_unprotect_page_virt(vcpu, gva))
4485 return true;
4486
4487 gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
4488
4489 if (gpa == UNMAPPED_GVA)
4490 return true; /* let cpu generate fault */
4491
4492 if (!kvm_is_error_hva(gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT)))
4493 return true;
4494
4495 return false;
4496}
4497
51d8b661
AP		 4498int x86_emulate_instruction(struct kvm_vcpu *vcpu,
4499 unsigned long cr2,
dc25e89e
AP		 4500 int emulation_type,
4501 void *insn,
4502 int insn_len)
bbd9b64e 4503{
95cb2295 4504 int r;
4d2179e1 4505 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
7ae441ea 4506 bool writeback = true;
bbd9b64e 4507
26eef70c 4508 kvm_clear_exception_queue(vcpu);
ad312c7c 4509 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976 4510 /*
56e82318 4511 * TODO: fix emulate.c to use guest_read/write_register
5fdbf976
MT		 4512 * instead of direct ->regs accesses, can save hundred cycles
4513 * on Intel for instructions that don't read/change RSP, for
4514 * for example.
4515 */
4516 cache_all_regs(vcpu);
bbd9b64e 4517
571008da 4518 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 4519 init_emulate_ctxt(vcpu);
95cb2295 4520 vcpu->arch.emulate_ctxt.interruptibility = 0;
da9cb575 4521 vcpu->arch.emulate_ctxt.have_exception = false;
4fc40f07 4522 vcpu->arch.emulate_ctxt.perm_ok = false;
bbd9b64e 4523
4005996e
AK		 4524 vcpu->arch.emulate_ctxt.only_vendor_specific_insn
4525 = emulation_type & EMULTYPE_TRAP_UD;
4526
dc25e89e 4527 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, insn, insn_len);
bbd9b64e 4528
e46479f8 4529 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 4530 ++vcpu->stat.insn_emulation;
bbd9b64e 4531 if (r) {
4005996e
AK		 4532 if (emulation_type & EMULTYPE_TRAP_UD)
4533 return EMULATE_FAIL;
a6f177ef 4534 if (reexecute_instruction(vcpu, cr2))
bbd9b64e 4535 return EMULATE_DONE;
6d77dbfc
GN		 4536 if (emulation_type & EMULTYPE_SKIP)
4537 return EMULATE_FAIL;
4538 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4539 }
4540 }
4541
ba8afb6b
GN		 4542 if (emulation_type & EMULTYPE_SKIP) {
4543 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
4544 return EMULATE_DONE;
4545 }
4546
7ae441ea 4547 /* this is needed for vmware backdoor interface to work since it
4d2179e1 4548 changes registers values during IO operation */
7ae441ea
GN		 4549 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
4550 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
4551 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
4552 }
4d2179e1 4553
5cd21917 4554restart:
9aabc88f 4555 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt);
bbd9b64e 4556
775fde86
JR		 4557 if (r == EMULATION_INTERCEPTED)
4558 return EMULATE_DONE;
4559
d2ddd1c4 4560 if (r == EMULATION_FAILED) {
a6f177ef 4561 if (reexecute_instruction(vcpu, cr2))
c3cd7ffa
GN		 4562 return EMULATE_DONE;
4563
6d77dbfc 4564 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4565 }
4566
da9cb575 4567 if (vcpu->arch.emulate_ctxt.have_exception) {
54b8486f 4568 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 4569 r = EMULATE_DONE;
4570 } else if (vcpu->arch.pio.count) {
3457e419
GN		 4571 if (!vcpu->arch.pio.in)
4572 vcpu->arch.pio.count = 0;
7ae441ea
GN		 4573 else
4574 writeback = false;
e85d28f8 4575 r = EMULATE_DO_MMIO;
7ae441ea
GN		 4576 } else if (vcpu->mmio_needed) {
4577 if (!vcpu->mmio_is_write)
4578 writeback = false;
e85d28f8 4579 r = EMULATE_DO_MMIO;
7ae441ea 4580 } else if (r == EMULATION_RESTART)
5cd21917 4581 goto restart;
d2ddd1c4
GN		 4582 else
4583 r = EMULATE_DONE;
f850e2e6 4584
7ae441ea
GN		 4585 if (writeback) {
4586 toggle_interruptibility(vcpu,
4587 vcpu->arch.emulate_ctxt.interruptibility);
4588 kvm_set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
4589 kvm_make_request(KVM_REQ_EVENT, vcpu);
4590 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
4591 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
4592 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
4593 } else
4594 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 4595
4596 return r;
de7d789a 4597}
51d8b661 4598EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 4599
cf8f70bf 4600int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 4601{
cf8f70bf
GN		 4602 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
4603 int ret = emulator_pio_out_emulated(size, port, &val, 1, vcpu);
4604 /* do not return to emulator after return from userspace */
7972995b 4605 vcpu->arch.pio.count = 0;
de7d789a
CO		 4606 return ret;
4607}
cf8f70bf 4608EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 4609
8cfdc000
ZA		 4610static void tsc_bad(void *info)
4611{
0a3aee0d 4612 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 4613}
4614
4615static void tsc_khz_changed(void *data)
c8076604 4616{
8cfdc000
ZA		 4617 struct cpufreq_freqs *freq = data;
4618 unsigned long khz = 0;
4619
4620 if (data)
4621 khz = freq->new;
4622 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4623 khz = cpufreq_quick_get(raw_smp_processor_id());
4624 if (!khz)
4625 khz = tsc_khz;
0a3aee0d 4626 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 4627}
4628
c8076604
GH		 4629static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4630 void *data)
4631{
4632 struct cpufreq_freqs *freq = data;
4633 struct kvm *kvm;
4634 struct kvm_vcpu *vcpu;
4635 int i, send_ipi = 0;
4636
8cfdc000
ZA		 4637 /*
4638 * We allow guests to temporarily run on slowing clocks,
4639 * provided we notify them after, or to run on accelerating
4640 * clocks, provided we notify them before. Thus time never
4641 * goes backwards.
4642 *
4643 * However, we have a problem. We can't atomically update
4644 * the frequency of a given CPU from this function; it is
4645 * merely a notifier, which can be called from any CPU.
4646 * Changing the TSC frequency at arbitrary points in time
4647 * requires a recomputation of local variables related to
4648 * the TSC for each VCPU. We must flag these local variables
4649 * to be updated and be sure the update takes place with the
4650 * new frequency before any guests proceed.
4651 *
4652 * Unfortunately, the combination of hotplug CPU and frequency
4653 * change creates an intractable locking scenario; the order
4654 * of when these callouts happen is undefined with respect to
4655 * CPU hotplug, and they can race with each other. As such,
4656 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
4657 * undefined; you can actually have a CPU frequency change take
4658 * place in between the computation of X and the setting of the
4659 * variable. To protect against this problem, all updates of
4660 * the per_cpu tsc_khz variable are done in an interrupt
4661 * protected IPI, and all callers wishing to update the value
4662 * must wait for a synchronous IPI to complete (which is trivial
4663 * if the caller is on the CPU already). This establishes the
4664 * necessary total order on variable updates.
4665 *
4666 * Note that because a guest time update may take place
4667 * anytime after the setting of the VCPU's request bit, the
4668 * correct TSC value must be set before the request. However,
4669 * to ensure the update actually makes it to any guest which
4670 * starts running in hardware virtualization between the set
4671 * and the acquisition of the spinlock, we must also ping the
4672 * CPU after setting the request bit.
4673 *
4674 */
4675
c8076604
GH		 4676 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
4677 return 0;
4678 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
4679 return 0;
8cfdc000
ZA		 4680
4681 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 4682
e935b837 4683 raw_spin_lock(&kvm_lock);
c8076604 4684 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 4685 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 4686 if (vcpu->cpu != freq->cpu)
4687 continue;
c285545f 4688 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 4689 if (vcpu->cpu != smp_processor_id())
8cfdc000 4690 send_ipi = 1;
c8076604
GH		 4691 }
4692 }
e935b837 4693 raw_spin_unlock(&kvm_lock);
c8076604
GH		 4694
4695 if (freq->old < freq->new && send_ipi) {
4696 /*
4697 * We upscale the frequency. Must make the guest
4698 * doesn't see old kvmclock values while running with
4699 * the new frequency, otherwise we risk the guest sees
4700 * time go backwards.
4701 *
4702 * In case we update the frequency for another cpu
4703 * (which might be in guest context) send an interrupt
4704 * to kick the cpu out of guest context. Next time
4705 * guest context is entered kvmclock will be updated,
4706 * so the guest will not see stale values.
4707 */
8cfdc000 4708 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 4709 }
4710 return 0;
4711}
4712
4713static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 4714 .notifier_call = kvmclock_cpufreq_notifier
4715};
4716
4717static int kvmclock_cpu_notifier(struct notifier_block *nfb,
4718 unsigned long action, void *hcpu)
4719{
4720 unsigned int cpu = (unsigned long)hcpu;
4721
4722 switch (action) {
4723 case CPU_ONLINE:
4724 case CPU_DOWN_FAILED:
4725 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4726 break;
4727 case CPU_DOWN_PREPARE:
4728 smp_call_function_single(cpu, tsc_bad, NULL, 1);
4729 break;
4730 }
4731 return NOTIFY_OK;
4732}
4733
4734static struct notifier_block kvmclock_cpu_notifier_block = {
4735 .notifier_call = kvmclock_cpu_notifier,
4736 .priority = -INT_MAX
c8076604
GH		 4737};
4738
b820cc0c
ZA		 4739static void kvm_timer_init(void)
4740{
4741 int cpu;
4742
c285545f 4743 max_tsc_khz = tsc_khz;
8cfdc000 4744 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 4745 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 4746#ifdef CONFIG_CPU_FREQ
4747 struct cpufreq_policy policy;
4748 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 4749 cpu = get_cpu();
4750 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 4751 if (policy.cpuinfo.max_freq)
4752 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 4753 put_cpu();
c285545f 4754#endif
b820cc0c
ZA		 4755 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4756 CPUFREQ_TRANSITION_NOTIFIER);
4757 }
c285545f 4758 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 4759 for_each_online_cpu(cpu)
4760 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 4761}
4762
ff9d07a0
ZY		 4763static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
4764
4765static int kvm_is_in_guest(void)
4766{
4767 return percpu_read(current_vcpu) != NULL;
4768}
4769
4770static int kvm_is_user_mode(void)
4771{
4772 int user_mode = 3;
dcf46b94 4773
ff9d07a0
ZY		 4774 if (percpu_read(current_vcpu))
4775 user_mode = kvm_x86_ops->get_cpl(percpu_read(current_vcpu));
dcf46b94 4776
ff9d07a0
ZY		 4777 return user_mode != 0;
4778}
4779
4780static unsigned long kvm_get_guest_ip(void)
4781{
4782 unsigned long ip = 0;
dcf46b94 4783
ff9d07a0
ZY		 4784 if (percpu_read(current_vcpu))
4785 ip = kvm_rip_read(percpu_read(current_vcpu));
dcf46b94 4786
ff9d07a0
ZY		 4787 return ip;
4788}
4789
4790static struct perf_guest_info_callbacks kvm_guest_cbs = {
4791 .is_in_guest = kvm_is_in_guest,
4792 .is_user_mode = kvm_is_user_mode,
4793 .get_guest_ip = kvm_get_guest_ip,
4794};
4795
4796void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4797{
4798 percpu_write(current_vcpu, vcpu);
4799}
4800EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4801
4802void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4803{
4804 percpu_write(current_vcpu, NULL);
4805}
4806EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4807
f8c16bba 4808int kvm_arch_init(void *opaque)
043405e1 4809{
b820cc0c 4810 int r;
f8c16bba
ZX		 4811 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4812
f8c16bba
ZX		 4813 if (kvm_x86_ops) {
4814 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 4815 r = -EEXIST;
4816 goto out;
f8c16bba
ZX		 4817 }
4818
4819 if (!ops->cpu_has_kvm_support()) {
4820 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 4821 r = -EOPNOTSUPP;
4822 goto out;
f8c16bba
ZX		 4823 }
4824 if (ops->disabled_by_bios()) {
4825 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 4826 r = -EOPNOTSUPP;
4827 goto out;
f8c16bba
ZX		 4828 }
4829
97db56ce
AK		 4830 r = kvm_mmu_module_init();
4831 if (r)
4832 goto out;
4833
4834 kvm_init_msr_list();
4835
f8c16bba 4836 kvm_x86_ops = ops;
56c6d28a 4837 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e 4838 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 4839 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 4840
b820cc0c 4841 kvm_timer_init();
c8076604 4842
ff9d07a0
ZY		 4843 perf_register_guest_info_callbacks(&kvm_guest_cbs);
4844
2acf923e
DC		 4845 if (cpu_has_xsave)
4846 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
4847
f8c16bba 4848 return 0;
56c6d28a
ZX		 4849
4850out:
56c6d28a 4851 return r;
043405e1 4852}
8776e519 4853
f8c16bba
ZX		 4854void kvm_arch_exit(void)
4855{
ff9d07a0
ZY		 4856 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4857
888d256e
JK		 4858 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4859 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4860 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 4861 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
f8c16bba 4862 kvm_x86_ops = NULL;
56c6d28a
ZX		 4863 kvm_mmu_module_exit();
4864}
f8c16bba 4865
8776e519
HB		 4866int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4867{
4868 ++vcpu->stat.halt_exits;
4869 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 4870 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 4871 return 1;
4872 } else {
4873 vcpu->run->exit_reason = KVM_EXIT_HLT;
4874 return 0;
4875 }
4876}
4877EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4878
2f333bcb
MT		 4879static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
4880 unsigned long a1)
4881{
4882 if (is_long_mode(vcpu))
4883 return a0;
4884 else
4885 return a0 | ((gpa_t)a1 << 32);
4886}
4887
55cd8e5a
GN		 4888int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
4889{
4890 u64 param, ingpa, outgpa, ret;
4891 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
4892 bool fast, longmode;
4893 int cs_db, cs_l;
4894
4895 /*
4896 * hypercall generates UD from non zero cpl and real mode
4897 * per HYPER-V spec
4898 */
3eeb3288 4899 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 4900 kvm_queue_exception(vcpu, UD_VECTOR);
4901 return 0;
4902 }
4903
4904 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4905 longmode = is_long_mode(vcpu) && cs_l == 1;
4906
4907 if (!longmode) {
ccd46936
GN		 4908 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
4909 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
4910 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
4911 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
4912 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
4913 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 4914 }
4915#ifdef CONFIG_X86_64
4916 else {
4917 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
4918 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
4919 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
4920 }
4921#endif
4922
4923 code = param & 0xffff;
4924 fast = (param >> 16) & 0x1;
4925 rep_cnt = (param >> 32) & 0xfff;
4926 rep_idx = (param >> 48) & 0xfff;
4927
4928 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
4929
c25bc163
GN		 4930 switch (code) {
4931 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
4932 kvm_vcpu_on_spin(vcpu);
4933 break;
4934 default:
4935 res = HV_STATUS_INVALID_HYPERCALL_CODE;
4936 break;
4937 }
55cd8e5a
GN		 4938
4939 ret = res | (((u64)rep_done & 0xfff) << 32);
4940 if (longmode) {
4941 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
4942 } else {
4943 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
4944 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
4945 }
4946
4947 return 1;
4948}
4949
8776e519
HB		 4950int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
4951{
4952 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 4953 int r = 1;
8776e519 4954
55cd8e5a
GN		 4955 if (kvm_hv_hypercall_enabled(vcpu->kvm))
4956 return kvm_hv_hypercall(vcpu);
4957
5fdbf976
MT		 4958 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
4959 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
4960 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
4961 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
4962 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 4963
229456fc 4964 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 4965
8776e519
HB		 4966 if (!is_long_mode(vcpu)) {
4967 nr &= 0xFFFFFFFF;
4968 a0 &= 0xFFFFFFFF;
4969 a1 &= 0xFFFFFFFF;
4970 a2 &= 0xFFFFFFFF;
4971 a3 &= 0xFFFFFFFF;
4972 }
4973
07708c4a
JK		 4974 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
4975 ret = -KVM_EPERM;
4976 goto out;
4977 }
4978
8776e519 4979 switch (nr) {
b93463aa
AK		 4980 case KVM_HC_VAPIC_POLL_IRQ:
4981 ret = 0;
4982 break;
2f333bcb
MT		 4983 case KVM_HC_MMU_OP:
4984 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
4985 break;
8776e519
HB		 4986 default:
4987 ret = -KVM_ENOSYS;
4988 break;
4989 }
07708c4a 4990out:
5fdbf976 4991 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 4992 ++vcpu->stat.hypercalls;
2f333bcb 4993 return r;
8776e519
HB		 4994}
4995EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
4996
4997int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
4998{
4999 char instruction[3];
5fdbf976 5000 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5001
8776e519
HB		 5002 /*
5003 * Blow out the MMU to ensure that no other VCPU has an active mapping
5004 * to ensure that the updated hypercall appears atomically across all
5005 * VCPUs.
5006 */
5007 kvm_mmu_zap_all(vcpu->kvm);
5008
8776e519 5009 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5010
8fe681e9 5011 return emulator_write_emulated(rip, instruction, 3, NULL, vcpu);
8776e519
HB		 5012}
5013
8776e519
HB		 5014void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
5015{
89a27f4d 5016 struct desc_ptr dt = { limit, base };
8776e519
HB		 5017
5018 kvm_x86_ops->set_gdt(vcpu, &dt);
5019}
5020
5021void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
5022{
89a27f4d 5023 struct desc_ptr dt = { limit, base };
8776e519
HB		 5024
5025 kvm_x86_ops->set_idt(vcpu, &dt);
5026}
5027
07716717
DK		 5028static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
5029{
ad312c7c
ZX		 5030 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
5031 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 5032
5033 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
5034 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 5035 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 5036 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 5037 if (ej->function == e->function) {
5038 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
5039 return j;
5040 }
5041 }
5042 return 0; /* silence gcc, even though control never reaches here */
5043}
5044
5045/* find an entry with matching function, matching index (if needed), and that
5046 * should be read next (if it's stateful) */
5047static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
5048 u32 function, u32 index)
5049{
5050 if (e->function != function)
5051 return 0;
5052 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
5053 return 0;
5054 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 5055 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 5056 return 0;
5057 return 1;
5058}
5059
d8017474
AG		 5060struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
5061 u32 function, u32 index)
8776e519
HB		 5062{
5063 int i;
d8017474 5064 struct kvm_cpuid_entry2 *best = NULL;
8776e519 5065
ad312c7c 5066 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 5067 struct kvm_cpuid_entry2 *e;
5068
ad312c7c 5069 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 5070 if (is_matching_cpuid_entry(e, function, index)) {
5071 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
5072 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 5073 best = e;
5074 break;
5075 }
8776e519 5076 }
d8017474
AG		 5077 return best;
5078}
0e851880 5079EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
d8017474 5080
82725b20
DE		 5081int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
5082{
5083 struct kvm_cpuid_entry2 *best;
5084
f7a71197
AK		 5085 best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0);
5086 if (!best || best->eax < 0x80000008)
5087 goto not_found;
82725b20
DE		 5088 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
5089 if (best)
5090 return best->eax & 0xff;
f7a71197 5091not_found:
82725b20
DE		 5092 return 36;
5093}
5094
bd22f5cf
AP		 5095/*
5096 * If no match is found, check whether we exceed the vCPU's limit
5097 * and return the content of the highest valid _standard_ leaf instead.
5098 * This is to satisfy the CPUID specification.
5099 */
5100static struct kvm_cpuid_entry2* check_cpuid_limit(struct kvm_vcpu *vcpu,
5101 u32 function, u32 index)
5102{
5103 struct kvm_cpuid_entry2 *maxlevel;
5104
5105 maxlevel = kvm_find_cpuid_entry(vcpu, function & 0x80000000, 0);
5106 if (!maxlevel || maxlevel->eax >= function)
5107 return NULL;
5108 if (function & 0x80000000) {
5109 maxlevel = kvm_find_cpuid_entry(vcpu, 0, 0);
5110 if (!maxlevel)
5111 return NULL;
5112 }
5113 return kvm_find_cpuid_entry(vcpu, maxlevel->eax, index);
5114}
5115
d8017474
AG		 5116void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
5117{
5118 u32 function, index;
5119 struct kvm_cpuid_entry2 *best;
5120
5121 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
5122 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5123 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
5124 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
5125 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
5126 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
5127 best = kvm_find_cpuid_entry(vcpu, function, index);
bd22f5cf
AP		 5128
5129 if (!best)
5130 best = check_cpuid_limit(vcpu, function, index);
5131
8776e519 5132 if (best) {
5fdbf976
MT		 5133 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
5134 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
5135 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
5136 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 5137 }
8776e519 5138 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 5139 trace_kvm_cpuid(function,
5140 kvm_register_read(vcpu, VCPU_REGS_RAX),
5141 kvm_register_read(vcpu, VCPU_REGS_RBX),
5142 kvm_register_read(vcpu, VCPU_REGS_RCX),
5143 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 5144}
5145EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 5146
b6c7a5dc
HB		 5147/*
5148 * Check if userspace requested an interrupt window, and that the
5149 * interrupt window is open.
5150 *
5151 * No need to exit to userspace if we already have an interrupt queued.
5152 */
851ba692 5153static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5154{
8061823a 5155 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5156 vcpu->run->request_interrupt_window &&
5df56646 5157 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5158}
5159
851ba692 5160static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5161{
851ba692
AK		 5162 struct kvm_run *kvm_run = vcpu->run;
5163
91586a3b 5164 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5165 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5166 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5167 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5168 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5169 else
b6c7a5dc 5170 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5171 kvm_arch_interrupt_allowed(vcpu) &&
5172 !kvm_cpu_has_interrupt(vcpu) &&
5173 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5174}
5175
b93463aa
AK		 5176static void vapic_enter(struct kvm_vcpu *vcpu)
5177{
5178 struct kvm_lapic *apic = vcpu->arch.apic;
5179 struct page *page;
5180
5181 if (!apic || !apic->vapic_addr)
5182 return;
5183
5184 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 5185
5186 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 5187}
5188
5189static void vapic_exit(struct kvm_vcpu *vcpu)
5190{
5191 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 5192 int idx;
b93463aa
AK		 5193
5194 if (!apic || !apic->vapic_addr)
5195 return;
5196
f656ce01 5197 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 5198 kvm_release_page_dirty(apic->vapic_page);
5199 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 5200 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 5201}
5202
95ba8273
GN		 5203static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5204{
5205 int max_irr, tpr;
5206
5207 if (!kvm_x86_ops->update_cr8_intercept)
5208 return;
5209
88c808fd
AK		 5210 if (!vcpu->arch.apic)
5211 return;
5212
8db3baa2
GN		 5213 if (!vcpu->arch.apic->vapic_addr)
5214 max_irr = kvm_lapic_find_highest_irr(vcpu);
5215 else
5216 max_irr = -1;
95ba8273
GN		 5217
5218 if (max_irr != -1)
5219 max_irr >>= 4;
5220
5221 tpr = kvm_lapic_get_cr8(vcpu);
5222
5223 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5224}
5225
851ba692 5226static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 5227{
5228 /* try to reinject previous events if any */
b59bb7bd 5229 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5230 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5231 vcpu->arch.exception.has_error_code,
5232 vcpu->arch.exception.error_code);
b59bb7bd
GN		 5233 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5234 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5235 vcpu->arch.exception.error_code,
5236 vcpu->arch.exception.reinject);
b59bb7bd
GN		 5237 return;
5238 }
5239
95ba8273
GN		 5240 if (vcpu->arch.nmi_injected) {
5241 kvm_x86_ops->set_nmi(vcpu);
5242 return;
5243 }
5244
5245 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5246 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5247 return;
5248 }
5249
5250 /* try to inject new event if pending */
5251 if (vcpu->arch.nmi_pending) {
5252 if (kvm_x86_ops->nmi_allowed(vcpu)) {
5253 vcpu->arch.nmi_pending = false;
5254 vcpu->arch.nmi_injected = true;
5255 kvm_x86_ops->set_nmi(vcpu);
5256 }
5257 } else if (kvm_cpu_has_interrupt(vcpu)) {
5258 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5259 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5260 false);
5261 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5262 }
5263 }
5264}
5265
2acf923e
DC		 5266static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
5267{
5268 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
5269 !vcpu->guest_xcr0_loaded) {
5270 /* kvm_set_xcr() also depends on this */
5271 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
5272 vcpu->guest_xcr0_loaded = 1;
5273 }
5274}
5275
5276static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
5277{
5278 if (vcpu->guest_xcr0_loaded) {
5279 if (vcpu->arch.xcr0 != host_xcr0)
5280 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
5281 vcpu->guest_xcr0_loaded = 0;
5282 }
5283}
5284
851ba692 5285static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5286{
5287 int r;
1499e54a 5288 bool nmi_pending;
6a8b1d13 5289 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5290 vcpu->run->request_interrupt_window;
b6c7a5dc 5291
3e007509 5292 if (vcpu->requests) {
a8eeb04a 5293 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5294 kvm_mmu_unload(vcpu);
a8eeb04a 5295 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5296 __kvm_migrate_timers(vcpu);
34c238a1
ZA		 5297 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5298 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 5299 if (unlikely(r))
5300 goto out;
5301 }
a8eeb04a 5302 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5303 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5304 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5305 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5306 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5307 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5308 r = 0;
5309 goto out;
5310 }
a8eeb04a 5311 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5312 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5313 r = 0;
5314 goto out;
5315 }
a8eeb04a 5316 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5317 vcpu->fpu_active = 0;
5318 kvm_x86_ops->fpu_deactivate(vcpu);
5319 }
af585b92
GN		 5320 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5321 /* Page is swapped out. Do synthetic halt */
5322 vcpu->arch.apf.halted = true;
5323 r = 1;
5324 goto out;
5325 }
2f52d58c 5326 }
b93463aa 5327
3e007509
AK		 5328 r = kvm_mmu_reload(vcpu);
5329 if (unlikely(r))
5330 goto out;
5331
1499e54a
GN		 5332 /*
5333 * An NMI can be injected between local nmi_pending read and
5334 * vcpu->arch.nmi_pending read inside inject_pending_event().
5335 * But in that case, KVM_REQ_EVENT will be set, which makes
5336 * the race described above benign.
5337 */
5338 nmi_pending = ACCESS_ONCE(vcpu->arch.nmi_pending);
5339
b463a6f7
AK		 5340 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5341 inject_pending_event(vcpu);
5342
5343 /* enable NMI/IRQ window open exits if needed */
1499e54a 5344 if (nmi_pending)
b463a6f7
AK		 5345 kvm_x86_ops->enable_nmi_window(vcpu);
5346 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
5347 kvm_x86_ops->enable_irq_window(vcpu);
5348
5349 if (kvm_lapic_enabled(vcpu)) {
5350 update_cr8_intercept(vcpu);
5351 kvm_lapic_sync_to_vapic(vcpu);
5352 }
5353 }
5354
b6c7a5dc
HB		 5355 preempt_disable();
5356
5357 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 5358 if (vcpu->fpu_active)
5359 kvm_load_guest_fpu(vcpu);
2acf923e 5360 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 5361
6b7e2d09
XG		 5362 vcpu->mode = IN_GUEST_MODE;
5363
5364 /* We should set ->mode before check ->requests,
5365 * see the comment in make_all_cpus_request.
5366 */
5367 smp_mb();
b6c7a5dc 5368
d94e1dc9 5369 local_irq_disable();
32f88400 5370
6b7e2d09 5371 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 5372 || need_resched() || signal_pending(current)) {
6b7e2d09 5373 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5374 smp_wmb();
6c142801
AK		 5375 local_irq_enable();
5376 preempt_enable();
b463a6f7 5377 kvm_x86_ops->cancel_injection(vcpu);
6c142801
AK		 5378 r = 1;
5379 goto out;
5380 }
5381
f656ce01 5382 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 5383
b6c7a5dc
HB		 5384 kvm_guest_enter();
5385
42dbaa5a 5386 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 5387 set_debugreg(0, 7);
5388 set_debugreg(vcpu->arch.eff_db[0], 0);
5389 set_debugreg(vcpu->arch.eff_db[1], 1);
5390 set_debugreg(vcpu->arch.eff_db[2], 2);
5391 set_debugreg(vcpu->arch.eff_db[3], 3);
5392 }
b6c7a5dc 5393
229456fc 5394 trace_kvm_entry(vcpu->vcpu_id);
851ba692 5395 kvm_x86_ops->run(vcpu);
b6c7a5dc 5396
24f1e32c
FW		 5397 /*
5398 * If the guest has used debug registers, at least dr7
5399 * will be disabled while returning to the host.
5400 * If we don't have active breakpoints in the host, we don't
5401 * care about the messed up debug address registers. But if
5402 * we have some of them active, restore the old state.
5403 */
59d8eb53 5404 if (hw_breakpoint_active())
24f1e32c 5405 hw_breakpoint_restore();
42dbaa5a 5406
1d5f066e
ZA		 5407 kvm_get_msr(vcpu, MSR_IA32_TSC, &vcpu->arch.last_guest_tsc);
5408
6b7e2d09 5409 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5410 smp_wmb();
b6c7a5dc
HB		 5411 local_irq_enable();
5412
5413 ++vcpu->stat.exits;
5414
5415 /*
5416 * We must have an instruction between local_irq_enable() and
5417 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5418 * the interrupt shadow. The stat.exits increment will do nicely.
5419 * But we need to prevent reordering, hence this barrier():
5420 */
5421 barrier();
5422
5423 kvm_guest_exit();
5424
5425 preempt_enable();
5426
f656ce01 5427 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 5428
b6c7a5dc
HB		 5429 /*
5430 * Profile KVM exit RIPs:
5431 */
5432 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 5433 unsigned long rip = kvm_rip_read(vcpu);
5434 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 5435 }
5436
298101da 5437
b93463aa
AK		 5438 kvm_lapic_sync_from_vapic(vcpu);
5439
851ba692 5440 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 5441out:
5442 return r;
5443}
b6c7a5dc 5444
09cec754 5445
851ba692 5446static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 5447{
5448 int r;
f656ce01 5449 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 5450
5451 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 5452 pr_debug("vcpu %d received sipi with vector # %x\n",
5453 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 5454 kvm_lapic_reset(vcpu);
5f179287 5455 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 5456 if (r)
5457 return r;
5458 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 5459 }
5460
f656ce01 5461 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 5462 vapic_enter(vcpu);
5463
5464 r = 1;
5465 while (r > 0) {
af585b92
GN		 5466 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
5467 !vcpu->arch.apf.halted)
851ba692 5468 r = vcpu_enter_guest(vcpu);
d7690175 5469 else {
f656ce01 5470 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 5471 kvm_vcpu_block(vcpu);
f656ce01 5472 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
a8eeb04a 5473 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
09cec754
GN		 5474 {
5475 switch(vcpu->arch.mp_state) {
5476 case KVM_MP_STATE_HALTED:
d7690175 5477 vcpu->arch.mp_state =
09cec754
GN		 5478 KVM_MP_STATE_RUNNABLE;
5479 case KVM_MP_STATE_RUNNABLE:
af585b92 5480 vcpu->arch.apf.halted = false;
09cec754
GN		 5481 break;
5482 case KVM_MP_STATE_SIPI_RECEIVED:
5483 default:
5484 r = -EINTR;
5485 break;
5486 }
5487 }
d7690175
MT		 5488 }
5489
09cec754
GN		 5490 if (r <= 0)
5491 break;
5492
5493 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5494 if (kvm_cpu_has_pending_timer(vcpu))
5495 kvm_inject_pending_timer_irqs(vcpu);
5496
851ba692 5497 if (dm_request_for_irq_injection(vcpu)) {
09cec754 5498 r = -EINTR;
851ba692 5499 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5500 ++vcpu->stat.request_irq_exits;
5501 }
af585b92
GN		 5502
5503 kvm_check_async_pf_completion(vcpu);
5504
09cec754
GN		 5505 if (signal_pending(current)) {
5506 r = -EINTR;
851ba692 5507 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5508 ++vcpu->stat.signal_exits;
5509 }
5510 if (need_resched()) {
f656ce01 5511 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 5512 kvm_resched(vcpu);
f656ce01 5513 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 5514 }
b6c7a5dc
HB		 5515 }
5516
f656ce01 5517 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 5518
b93463aa
AK		 5519 vapic_exit(vcpu);
5520
b6c7a5dc
HB		 5521 return r;
5522}
5523
5287f194
AK		 5524static int complete_mmio(struct kvm_vcpu *vcpu)
5525{
5526 struct kvm_run *run = vcpu->run;
5527 int r;
5528
5529 if (!(vcpu->arch.pio.count || vcpu->mmio_needed))
5530 return 1;
5531
5532 if (vcpu->mmio_needed) {
5287f194 5533 vcpu->mmio_needed = 0;
cef4dea0
AK		 5534 if (!vcpu->mmio_is_write)
5535 memcpy(vcpu->mmio_data, run->mmio.data, 8);
5536 vcpu->mmio_index += 8;
5537 if (vcpu->mmio_index < vcpu->mmio_size) {
5538 run->exit_reason = KVM_EXIT_MMIO;
5539 run->mmio.phys_addr = vcpu->mmio_phys_addr + vcpu->mmio_index;
5540 memcpy(run->mmio.data, vcpu->mmio_data + vcpu->mmio_index, 8);
5541 run->mmio.len = min(vcpu->mmio_size - vcpu->mmio_index, 8);
5542 run->mmio.is_write = vcpu->mmio_is_write;
5543 vcpu->mmio_needed = 1;
5544 return 0;
5545 }
5546 if (vcpu->mmio_is_write)
5547 return 1;
5548 vcpu->mmio_read_completed = 1;
5287f194
AK		 5549 }
5550 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5551 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
5552 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5553 if (r != EMULATE_DONE)
5554 return 0;
5555 return 1;
5556}
5557
b6c7a5dc
HB		 5558int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
5559{
5560 int r;
5561 sigset_t sigsaved;
5562
e5c30142
AK		 5563 if (!tsk_used_math(current) && init_fpu(current))
5564 return -ENOMEM;
5565
ac9f6dc0
AK		 5566 if (vcpu->sigset_active)
5567 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
5568
a4535290 5569 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 5570 kvm_vcpu_block(vcpu);
d7690175 5571 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 5572 r = -EAGAIN;
5573 goto out;
b6c7a5dc
HB		 5574 }
5575
b6c7a5dc 5576 /* re-sync apic's tpr */
eea1cff9
AP		 5577 if (!irqchip_in_kernel(vcpu->kvm)) {
5578 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
5579 r = -EINVAL;
5580 goto out;
5581 }
5582 }
b6c7a5dc 5583
5287f194
AK		 5584 r = complete_mmio(vcpu);
5585 if (r <= 0)
5586 goto out;
5587
5fdbf976
MT		 5588 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
5589 kvm_register_write(vcpu, VCPU_REGS_RAX,
5590 kvm_run->hypercall.ret);
b6c7a5dc 5591
851ba692 5592 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 5593
5594out:
f1d86e46 5595 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 5596 if (vcpu->sigset_active)
5597 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
5598
b6c7a5dc
HB		 5599 return r;
5600}
5601
5602int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5603{
7ae441ea
GN		 5604 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
5605 /*
5606 * We are here if userspace calls get_regs() in the middle of
5607 * instruction emulation. Registers state needs to be copied
5608 * back from emulation context to vcpu. Usrapace shouldn't do
5609 * that usually, but some bad designed PV devices (vmware
5610 * backdoor interface) need this to work
5611 */
5612 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
5613 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
5614 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5615 }
5fdbf976
MT		 5616 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5617 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5618 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5619 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5620 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
5621 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
5622 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5623 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 5624#ifdef CONFIG_X86_64
5fdbf976
MT		 5625 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
5626 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
5627 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
5628 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
5629 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
5630 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
5631 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
5632 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 5633#endif
5634
5fdbf976 5635 regs->rip = kvm_rip_read(vcpu);
91586a3b 5636 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 5637
b6c7a5dc
HB		 5638 return 0;
5639}
5640
5641int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5642{
7ae441ea
GN		 5643 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
5644 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5645
5fdbf976
MT		 5646 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
5647 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
5648 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
5649 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
5650 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
5651 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
5652 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
5653 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 5654#ifdef CONFIG_X86_64
5fdbf976
MT		 5655 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
5656 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
5657 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
5658 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
5659 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
5660 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
5661 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
5662 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 5663#endif
5664
5fdbf976 5665 kvm_rip_write(vcpu, regs->rip);
91586a3b 5666 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 5667
b4f14abd
JK		 5668 vcpu->arch.exception.pending = false;
5669
3842d135
AK		 5670 kvm_make_request(KVM_REQ_EVENT, vcpu);
5671
b6c7a5dc
HB		 5672 return 0;
5673}
5674
b6c7a5dc
HB		 5675void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5676{
5677 struct kvm_segment cs;
5678
3e6e0aab 5679 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 5680 *db = cs.db;
5681 *l = cs.l;
5682}
5683EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
5684
5685int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
5686 struct kvm_sregs *sregs)
5687{
89a27f4d 5688 struct desc_ptr dt;
b6c7a5dc 5689
3e6e0aab
GT		 5690 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5691 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5692 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5693 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5694 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5695 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5696
3e6e0aab
GT		 5697 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5698 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 5699
5700 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 5701 sregs->idt.limit = dt.size;
5702 sregs->idt.base = dt.address;
b6c7a5dc 5703 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 5704 sregs->gdt.limit = dt.size;
5705 sregs->gdt.base = dt.address;
b6c7a5dc 5706
4d4ec087 5707 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 5708 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 5709 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 5710 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 5711 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 5712 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 5713 sregs->apic_base = kvm_get_apic_base(vcpu);
5714
923c61bb 5715 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 5716
36752c9b 5717 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 5718 set_bit(vcpu->arch.interrupt.nr,
5719 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 5720
b6c7a5dc
HB		 5721 return 0;
5722}
5723
62d9f0db
MT		 5724int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
5725 struct kvm_mp_state *mp_state)
5726{
62d9f0db 5727 mp_state->mp_state = vcpu->arch.mp_state;
62d9f0db
MT		 5728 return 0;
5729}
5730
5731int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
5732 struct kvm_mp_state *mp_state)
5733{
62d9f0db 5734 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 5735 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 5736 return 0;
5737}
5738
e269fb21
JK		 5739int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason,
5740 bool has_error_code, u32 error_code)
b6c7a5dc 5741{
4d2179e1 5742 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
8ec4722d 5743 int ret;
e01c2426 5744
8ec4722d 5745 init_emulate_ctxt(vcpu);
c697518a 5746
9aabc88f 5747 ret = emulator_task_switch(&vcpu->arch.emulate_ctxt,
e269fb21
JK		 5748 tss_selector, reason, has_error_code,
5749 error_code);
c697518a 5750
c697518a 5751 if (ret)
19d04437 5752 return EMULATE_FAIL;
37817f29 5753
4d2179e1 5754 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
95c55886 5755 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
f6e78475 5756 kvm_set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
3842d135 5757 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 5758 return EMULATE_DONE;
37817f29
IE		 5759}
5760EXPORT_SYMBOL_GPL(kvm_task_switch);
5761
b6c7a5dc
HB		 5762int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5763 struct kvm_sregs *sregs)
5764{
5765 int mmu_reset_needed = 0;
63f42e02 5766 int pending_vec, max_bits, idx;
89a27f4d 5767 struct desc_ptr dt;
b6c7a5dc 5768
89a27f4d
GN		 5769 dt.size = sregs->idt.limit;
5770 dt.address = sregs->idt.base;
b6c7a5dc 5771 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 5772 dt.size = sregs->gdt.limit;
5773 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 5774 kvm_x86_ops->set_gdt(vcpu, &dt);
5775
ad312c7c 5776 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 5777 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 5778 vcpu->arch.cr3 = sregs->cr3;
aff48baa 5779 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 5780
2d3ad1f4 5781 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 5782
f6801dff 5783 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 5784 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 5785 kvm_set_apic_base(vcpu, sregs->apic_base);
5786
4d4ec087 5787 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 5788 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 5789 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 5790
fc78f519 5791 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 5792 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c
SY		 5793 if (sregs->cr4 & X86_CR4_OSXSAVE)
5794 update_cpuid(vcpu);
63f42e02
XG		 5795
5796 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 5797 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 5798 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 5799 mmu_reset_needed = 1;
5800 }
63f42e02 5801 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 5802
5803 if (mmu_reset_needed)
5804 kvm_mmu_reset_context(vcpu);
5805
923c61bb
GN		 5806 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5807 pending_vec = find_first_bit(
5808 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5809 if (pending_vec < max_bits) {
66fd3f7f 5810 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 5811 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 5812 }
5813
3e6e0aab
GT		 5814 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5815 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5816 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5817 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5818 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5819 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5820
3e6e0aab
GT		 5821 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5822 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 5823
5f0269f5
ME		 5824 update_cr8_intercept(vcpu);
5825
9c3e4aab 5826 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 5827 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 5828 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 5829 !is_protmode(vcpu))
9c3e4aab
MT		 5830 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5831
3842d135
AK		 5832 kvm_make_request(KVM_REQ_EVENT, vcpu);
5833
b6c7a5dc
HB		 5834 return 0;
5835}
5836
d0bfb940
JK		 5837int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5838 struct kvm_guest_debug *dbg)
b6c7a5dc 5839{
355be0b9 5840 unsigned long rflags;
ae675ef0 5841 int i, r;
b6c7a5dc 5842
4f926bf2
JK		 5843 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5844 r = -EBUSY;
5845 if (vcpu->arch.exception.pending)
2122ff5e 5846 goto out;
4f926bf2
JK		 5847 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5848 kvm_queue_exception(vcpu, DB_VECTOR);
5849 else
5850 kvm_queue_exception(vcpu, BP_VECTOR);
5851 }
5852
91586a3b
JK		 5853 /*
5854 * Read rflags as long as potentially injected trace flags are still
5855 * filtered out.
5856 */
5857 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 5858
5859 vcpu->guest_debug = dbg->control;
5860 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5861 vcpu->guest_debug = 0;
5862
5863 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 5864 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5865 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5866 vcpu->arch.switch_db_regs =
5867 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5868 } else {
5869 for (i = 0; i < KVM_NR_DB_REGS; i++)
5870 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5871 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5872 }
5873
f92653ee
JK		 5874 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5875 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5876 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 5877
91586a3b
JK		 5878 /*
5879 * Trigger an rflags update that will inject or remove the trace
5880 * flags.
5881 */
5882 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 5883
355be0b9 5884 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 5885
4f926bf2 5886 r = 0;
d0bfb940 5887
2122ff5e 5888out:
b6c7a5dc
HB		 5889
5890 return r;
5891}
5892
8b006791
ZX		 5893/*
5894 * Translate a guest virtual address to a guest physical address.
5895 */
5896int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5897 struct kvm_translation *tr)
5898{
5899 unsigned long vaddr = tr->linear_address;
5900 gpa_t gpa;
f656ce01 5901 int idx;
8b006791 5902
f656ce01 5903 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 5904 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 5905 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 5906 tr->physical_address = gpa;
5907 tr->valid = gpa != UNMAPPED_GVA;
5908 tr->writeable = 1;
5909 tr->usermode = 0;
8b006791
ZX		 5910
5911 return 0;
5912}
5913
d0752060
HB		 5914int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5915{
98918833
SY		 5916 struct i387_fxsave_struct *fxsave =
5917 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5918
d0752060
HB		 5919 memcpy(fpu->fpr, fxsave->st_space, 128);
5920 fpu->fcw = fxsave->cwd;
5921 fpu->fsw = fxsave->swd;
5922 fpu->ftwx = fxsave->twd;
5923 fpu->last_opcode = fxsave->fop;
5924 fpu->last_ip = fxsave->rip;
5925 fpu->last_dp = fxsave->rdp;
5926 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5927
d0752060
HB		 5928 return 0;
5929}
5930
5931int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5932{
98918833
SY		 5933 struct i387_fxsave_struct *fxsave =
5934 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5935
d0752060
HB		 5936 memcpy(fxsave->st_space, fpu->fpr, 128);
5937 fxsave->cwd = fpu->fcw;
5938 fxsave->swd = fpu->fsw;
5939 fxsave->twd = fpu->ftwx;
5940 fxsave->fop = fpu->last_opcode;
5941 fxsave->rip = fpu->last_ip;
5942 fxsave->rdp = fpu->last_dp;
5943 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5944
d0752060
HB		 5945 return 0;
5946}
5947
10ab25cd 5948int fx_init(struct kvm_vcpu *vcpu)
d0752060 5949{
10ab25cd
JK		 5950 int err;
5951
5952 err = fpu_alloc(&vcpu->arch.guest_fpu);
5953 if (err)
5954 return err;
5955
98918833 5956 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 5957
2acf923e
DC		 5958 /*
5959 * Ensure guest xcr0 is valid for loading
5960 */
5961 vcpu->arch.xcr0 = XSTATE_FP;
5962
ad312c7c 5963 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 5964
5965 return 0;
d0752060
HB		 5966}
5967EXPORT_SYMBOL_GPL(fx_init);
5968
98918833
SY		 5969static void fx_free(struct kvm_vcpu *vcpu)
5970{
5971 fpu_free(&vcpu->arch.guest_fpu);
5972}
5973
d0752060
HB		 5974void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
5975{
2608d7a1 5976 if (vcpu->guest_fpu_loaded)
d0752060
HB		 5977 return;
5978
2acf923e
DC		 5979 /*
5980 * Restore all possible states in the guest,
5981 * and assume host would use all available bits.
5982 * Guest xcr0 would be loaded later.
5983 */
5984 kvm_put_guest_xcr0(vcpu);
d0752060 5985 vcpu->guest_fpu_loaded = 1;
7cf30855 5986 unlazy_fpu(current);
98918833 5987 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 5988 trace_kvm_fpu(1);
d0752060 5989}
d0752060
HB		 5990
5991void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
5992{
2acf923e
DC		 5993 kvm_put_guest_xcr0(vcpu);
5994
d0752060
HB		 5995 if (!vcpu->guest_fpu_loaded)
5996 return;
5997
5998 vcpu->guest_fpu_loaded = 0;
98918833 5999 fpu_save_init(&vcpu->arch.guest_fpu);
f096ed85 6000 ++vcpu->stat.fpu_reload;
a8eeb04a 6001 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 6002 trace_kvm_fpu(0);
d0752060 6003}
e9b11c17
ZX		 6004
6005void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6006{
12f9a48f 6007 kvmclock_reset(vcpu);
7f1ea208 6008
f5f48ee1 6009 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 6010 fx_free(vcpu);
e9b11c17
ZX		 6011 kvm_x86_ops->vcpu_free(vcpu);
6012}
6013
6014struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6015 unsigned int id)
6016{
6755bae8
ZA		 6017 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6018 printk_once(KERN_WARNING
6019 "kvm: SMP vm created on host with unstable TSC; "
6020 "guest TSC will not be reliable\n");
26e5215f
AK		 6021 return kvm_x86_ops->vcpu_create(kvm, id);
6022}
e9b11c17 6023
26e5215f
AK		 6024int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6025{
6026 int r;
e9b11c17 6027
0bed3b56 6028 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 6029 vcpu_load(vcpu);
6030 r = kvm_arch_vcpu_reset(vcpu);
6031 if (r == 0)
6032 r = kvm_mmu_setup(vcpu);
6033 vcpu_put(vcpu);
6034 if (r < 0)
6035 goto free_vcpu;
6036
26e5215f 6037 return 0;
e9b11c17
ZX		 6038free_vcpu:
6039 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 6040 return r;
e9b11c17
ZX		 6041}
6042
d40ccc62 6043void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 6044{
344d9588
GN		 6045 vcpu->arch.apf.msr_val = 0;
6046
e9b11c17
ZX		 6047 vcpu_load(vcpu);
6048 kvm_mmu_unload(vcpu);
6049 vcpu_put(vcpu);
6050
98918833 6051 fx_free(vcpu);
e9b11c17
ZX		 6052 kvm_x86_ops->vcpu_free(vcpu);
6053}
6054
6055int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
6056{
448fa4a9
JK		 6057 vcpu->arch.nmi_pending = false;
6058 vcpu->arch.nmi_injected = false;
6059
42dbaa5a
JK		 6060 vcpu->arch.switch_db_regs = 0;
6061 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6062 vcpu->arch.dr6 = DR6_FIXED_1;
6063 vcpu->arch.dr7 = DR7_FIXED_1;
6064
3842d135 6065 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 6066 vcpu->arch.apf.msr_val = 0;
3842d135 6067
12f9a48f
GC		 6068 kvmclock_reset(vcpu);
6069
af585b92
GN		 6070 kvm_clear_async_pf_completion_queue(vcpu);
6071 kvm_async_pf_hash_reset(vcpu);
6072 vcpu->arch.apf.halted = false;
3842d135 6073
e9b11c17
ZX		 6074 return kvm_x86_ops->vcpu_reset(vcpu);
6075}
6076
10474ae8 6077int kvm_arch_hardware_enable(void *garbage)
e9b11c17 6078{
ca84d1a2
ZA		 6079 struct kvm *kvm;
6080 struct kvm_vcpu *vcpu;
6081 int i;
18863bdd
AK		 6082
6083 kvm_shared_msr_cpu_online();
ca84d1a2
ZA		 6084 list_for_each_entry(kvm, &vm_list, vm_list)
6085 kvm_for_each_vcpu(i, vcpu, kvm)
6086 if (vcpu->cpu == smp_processor_id())
c285545f 6087 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
10474ae8 6088 return kvm_x86_ops->hardware_enable(garbage);
e9b11c17
ZX		 6089}
6090
6091void kvm_arch_hardware_disable(void *garbage)
6092{
6093 kvm_x86_ops->hardware_disable(garbage);
3548bab5 6094 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 6095}
6096
6097int kvm_arch_hardware_setup(void)
6098{
6099 return kvm_x86_ops->hardware_setup();
6100}
6101
6102void kvm_arch_hardware_unsetup(void)
6103{
6104 kvm_x86_ops->hardware_unsetup();
6105}
6106
6107void kvm_arch_check_processor_compat(void *rtn)
6108{
6109 kvm_x86_ops->check_processor_compatibility(rtn);
6110}
6111
6112int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6113{
6114 struct page *page;
6115 struct kvm *kvm;
6116 int r;
6117
6118 BUG_ON(vcpu->kvm == NULL);
6119 kvm = vcpu->kvm;
6120
9aabc88f 6121 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
14dfe855 6122 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
ad312c7c 6123 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c30a358d 6124 vcpu->arch.mmu.translate_gpa = translate_gpa;
02f59dc9 6125 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
c5af89b6 6126 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 6127 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 6128 else
a4535290 6129 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 6130
6131 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6132 if (!page) {
6133 r = -ENOMEM;
6134 goto fail;
6135 }
ad312c7c 6136 vcpu->arch.pio_data = page_address(page);
e9b11c17 6137
1e993611 6138 kvm_init_tsc_catchup(vcpu, max_tsc_khz);
c285545f 6139
e9b11c17
ZX		 6140 r = kvm_mmu_create(vcpu);
6141 if (r < 0)
6142 goto fail_free_pio_data;
6143
6144 if (irqchip_in_kernel(kvm)) {
6145 r = kvm_create_lapic(vcpu);
6146 if (r < 0)
6147 goto fail_mmu_destroy;
6148 }
6149
890ca9ae
HY		 6150 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6151 GFP_KERNEL);
6152 if (!vcpu->arch.mce_banks) {
6153 r = -ENOMEM;
443c39bc 6154 goto fail_free_lapic;
890ca9ae
HY		 6155 }
6156 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6157
f5f48ee1
SY		 6158 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
6159 goto fail_free_mce_banks;
6160
af585b92
GN		 6161 kvm_async_pf_hash_reset(vcpu);
6162
e9b11c17 6163 return 0;
f5f48ee1
SY		 6164fail_free_mce_banks:
6165 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 6166fail_free_lapic:
6167 kvm_free_lapic(vcpu);
e9b11c17
ZX		 6168fail_mmu_destroy:
6169 kvm_mmu_destroy(vcpu);
6170fail_free_pio_data:
ad312c7c 6171 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 6172fail:
6173 return r;
6174}
6175
6176void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6177{
f656ce01
MT		 6178 int idx;
6179
36cb93fd 6180 kfree(vcpu->arch.mce_banks);
e9b11c17 6181 kvm_free_lapic(vcpu);
f656ce01 6182 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 6183 kvm_mmu_destroy(vcpu);
f656ce01 6184 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 6185 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 6186}
d19a9cd2 6187
d89f5eff 6188int kvm_arch_init_vm(struct kvm *kvm)
d19a9cd2 6189{
f05e70ac 6190 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 6191 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 6192
5550af4d
SY		 6193 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
6194 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
6195
038f8c11 6196 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
53f658b3 6197
d89f5eff 6198 return 0;
d19a9cd2
ZX		 6199}
6200
6201static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
6202{
6203 vcpu_load(vcpu);
6204 kvm_mmu_unload(vcpu);
6205 vcpu_put(vcpu);
6206}
6207
6208static void kvm_free_vcpus(struct kvm *kvm)
6209{
6210 unsigned int i;
988a2cae 6211 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 6212
6213 /*
6214 * Unpin any mmu pages first.
6215 */
af585b92
GN		 6216 kvm_for_each_vcpu(i, vcpu, kvm) {
6217 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 6218 kvm_unload_vcpu_mmu(vcpu);
af585b92 6219 }
988a2cae
GN		 6220 kvm_for_each_vcpu(i, vcpu, kvm)
6221 kvm_arch_vcpu_free(vcpu);
6222
6223 mutex_lock(&kvm->lock);
6224 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
6225 kvm->vcpus[i] = NULL;
d19a9cd2 6226
988a2cae
GN		 6227 atomic_set(&kvm->online_vcpus, 0);
6228 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 6229}
6230
ad8ba2cd
SY		 6231void kvm_arch_sync_events(struct kvm *kvm)
6232{
ba4cef31 6233 kvm_free_all_assigned_devices(kvm);
aea924f6 6234 kvm_free_pit(kvm);
ad8ba2cd
SY		 6235}
6236
d19a9cd2
ZX		 6237void kvm_arch_destroy_vm(struct kvm *kvm)
6238{
6eb55818 6239 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 6240 kfree(kvm->arch.vpic);
6241 kfree(kvm->arch.vioapic);
d19a9cd2 6242 kvm_free_vcpus(kvm);
3d45830c
AK		 6243 if (kvm->arch.apic_access_page)
6244 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 6245 if (kvm->arch.ept_identity_pagetable)
6246 put_page(kvm->arch.ept_identity_pagetable);
d19a9cd2 6247}
0de10343 6248
f7784b8e
MT		 6249int kvm_arch_prepare_memory_region(struct kvm *kvm,
6250 struct kvm_memory_slot *memslot,
0de10343 6251 struct kvm_memory_slot old,
f7784b8e 6252 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 6253 int user_alloc)
6254{
f7784b8e 6255 int npages = memslot->npages;
7ac77099
AK		 6256 int map_flags = MAP_PRIVATE | MAP_ANONYMOUS;
6257
6258 /* Prevent internal slot pages from being moved by fork()/COW. */
6259 if (memslot->id >= KVM_MEMORY_SLOTS)
6260 map_flags = MAP_SHARED | MAP_ANONYMOUS;
0de10343
ZX		 6261
6262 /*To keep backward compatibility with older userspace,
6263 *x86 needs to hanlde !user_alloc case.
6264 */
6265 if (!user_alloc) {
6266 if (npages && !old.rmap) {
604b38ac
AA		 6267 unsigned long userspace_addr;
6268
72dc67a6 6269 down_write(&current->mm->mmap_sem);
604b38ac
AA		 6270 userspace_addr = do_mmap(NULL, 0,
6271 npages * PAGE_SIZE,
6272 PROT_READ | PROT_WRITE,
7ac77099 6273 map_flags,
604b38ac 6274 0);
72dc67a6 6275 up_write(&current->mm->mmap_sem);
0de10343 6276
604b38ac
AA		 6277 if (IS_ERR((void *)userspace_addr))
6278 return PTR_ERR((void *)userspace_addr);
6279
604b38ac 6280 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 6281 }
6282 }
6283
f7784b8e
MT		 6284
6285 return 0;
6286}
6287
6288void kvm_arch_commit_memory_region(struct kvm *kvm,
6289 struct kvm_userspace_memory_region *mem,
6290 struct kvm_memory_slot old,
6291 int user_alloc)
6292{
6293
48c0e4e9 6294 int nr_mmu_pages = 0, npages = mem->memory_size >> PAGE_SHIFT;
f7784b8e
MT		 6295
6296 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
6297 int ret;
6298
6299 down_write(&current->mm->mmap_sem);
6300 ret = do_munmap(current->mm, old.userspace_addr,
6301 old.npages * PAGE_SIZE);
6302 up_write(&current->mm->mmap_sem);
6303 if (ret < 0)
6304 printk(KERN_WARNING
6305 "kvm_vm_ioctl_set_memory_region: "
6306 "failed to munmap memory\n");
6307 }
6308
48c0e4e9
XG		 6309 if (!kvm->arch.n_requested_mmu_pages)
6310 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
6311
7c8a83b7 6312 spin_lock(&kvm->mmu_lock);
48c0e4e9 6313 if (nr_mmu_pages)
0de10343 6314 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
0de10343 6315 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 6316 spin_unlock(&kvm->mmu_lock);
0de10343 6317}
1d737c8a 6318
34d4cb8f
MT		 6319void kvm_arch_flush_shadow(struct kvm *kvm)
6320{
6321 kvm_mmu_zap_all(kvm);
8986ecc0 6322 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 6323}
6324
1d737c8a
ZX		 6325int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
6326{
af585b92
GN		 6327 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6328 !vcpu->arch.apf.halted)
6329 || !list_empty_careful(&vcpu->async_pf.done)
a1b37100
GN		 6330 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
6331 || vcpu->arch.nmi_pending ||
6332 (kvm_arch_interrupt_allowed(vcpu) &&
6333 kvm_cpu_has_interrupt(vcpu));
1d737c8a 6334}
5736199a 6335
5736199a
ZX		 6336void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
6337{
32f88400
MT		 6338 int me;
6339 int cpu = vcpu->cpu;
5736199a
ZX		 6340
6341 if (waitqueue_active(&vcpu->wq)) {
6342 wake_up_interruptible(&vcpu->wq);
6343 ++vcpu->stat.halt_wakeup;
6344 }
32f88400
MT		 6345
6346 me = get_cpu();
6347 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
6b7e2d09 6348 if (kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE)
32f88400 6349 smp_send_reschedule(cpu);
e9571ed5 6350 put_cpu();
5736199a 6351}
78646121
GN		 6352
6353int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
6354{
6355 return kvm_x86_ops->interrupt_allowed(vcpu);
6356}
229456fc 6357
f92653ee
JK		 6358bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
6359{
6360 unsigned long current_rip = kvm_rip_read(vcpu) +
6361 get_segment_base(vcpu, VCPU_SREG_CS);
6362
6363 return current_rip == linear_rip;
6364}
6365EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
6366
94fe45da
JK		 6367unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
6368{
6369 unsigned long rflags;
6370
6371 rflags = kvm_x86_ops->get_rflags(vcpu);
6372 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 6373 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 6374 return rflags;
6375}
6376EXPORT_SYMBOL_GPL(kvm_get_rflags);
6377
6378void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
6379{
6380 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 6381 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 6382 rflags |= X86_EFLAGS_TF;
94fe45da 6383 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 6384 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 6385}
6386EXPORT_SYMBOL_GPL(kvm_set_rflags);
6387
56028d08
GN		 6388void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
6389{
6390 int r;
6391
fb67e14f 6392 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
c4806acd 6393 is_error_page(work->page))
56028d08
GN		 6394 return;
6395
6396 r = kvm_mmu_reload(vcpu);
6397 if (unlikely(r))
6398 return;
6399
fb67e14f
XG		 6400 if (!vcpu->arch.mmu.direct_map &&
6401 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
6402 return;
6403
56028d08
GN		 6404 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
6405}
6406
af585b92
GN		 6407static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
6408{
6409 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
6410}
6411
6412static inline u32 kvm_async_pf_next_probe(u32 key)
6413{
6414 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
6415}
6416
6417static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6418{
6419 u32 key = kvm_async_pf_hash_fn(gfn);
6420
6421 while (vcpu->arch.apf.gfns[key] != ~0)
6422 key = kvm_async_pf_next_probe(key);
6423
6424 vcpu->arch.apf.gfns[key] = gfn;
6425}
6426
6427static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
6428{
6429 int i;
6430 u32 key = kvm_async_pf_hash_fn(gfn);
6431
6432 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 6433 (vcpu->arch.apf.gfns[key] != gfn &&
6434 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 6435 key = kvm_async_pf_next_probe(key);
6436
6437 return key;
6438}
6439
6440bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6441{
6442 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
6443}
6444
6445static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6446{
6447 u32 i, j, k;
6448
6449 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
6450 while (true) {
6451 vcpu->arch.apf.gfns[i] = ~0;
6452 do {
6453 j = kvm_async_pf_next_probe(j);
6454 if (vcpu->arch.apf.gfns[j] == ~0)
6455 return;
6456 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
6457 /*
6458 * k lies cyclically in ]i,j]
6459 * | i.k.j |
6460 * |....j i.k.| or |.k..j i...|
6461 */
6462 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
6463 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
6464 i = j;
6465 }
6466}
6467
7c90705b
GN		 6468static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
6469{
6470
6471 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
6472 sizeof(val));
6473}
6474
af585b92
GN		 6475void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
6476 struct kvm_async_pf *work)
6477{
6389ee94
AK		 6478 struct x86_exception fault;
6479
7c90705b 6480 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 6481 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 6482
6483 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 6484 (vcpu->arch.apf.send_user_only &&
6485 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 6486 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
6487 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 6488 fault.vector = PF_VECTOR;
6489 fault.error_code_valid = true;
6490 fault.error_code = 0;
6491 fault.nested_page_fault = false;
6492 fault.address = work->arch.token;
6493 kvm_inject_page_fault(vcpu, &fault);
7c90705b 6494 }
af585b92
GN		 6495}
6496
6497void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
6498 struct kvm_async_pf *work)
6499{
6389ee94
AK		 6500 struct x86_exception fault;
6501
7c90705b
GN		 6502 trace_kvm_async_pf_ready(work->arch.token, work->gva);
6503 if (is_error_page(work->page))
6504 work->arch.token = ~0; /* broadcast wakeup */
6505 else
6506 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
6507
6508 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
6509 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 6510 fault.vector = PF_VECTOR;
6511 fault.error_code_valid = true;
6512 fault.error_code = 0;
6513 fault.nested_page_fault = false;
6514 fault.address = work->arch.token;
6515 kvm_inject_page_fault(vcpu, &fault);
7c90705b 6516 }
e6d53e3b 6517 vcpu->arch.apf.halted = false;
7c90705b
GN		 6518}
6519
6520bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
6521{
6522 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
6523 return true;
6524 else
6525 return !kvm_event_needs_reinjection(vcpu) &&
6526 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 6527}
6528
229456fc
MT		 6529EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
6530EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
6531EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
6532EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
6533EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 6534EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 6535EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 6536EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 6537EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 6538EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 6539EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 6540EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
kernel source for telekom puls (alcatel/mediatek)