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KVM: x86 emulator: make emulate_invlpg() an emulator callback
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
313a3dc7 29
18068523 30#include <linux/clocksource.h>
4d5c5d0f 31#include <linux/interrupt.h>
313a3dc7
CO		 32#include <linux/kvm.h>
33#include <linux/fs.h>
34#include <linux/vmalloc.h>
5fb76f9b 35#include <linux/module.h>
0de10343 36#include <linux/mman.h>
2bacc55c 37#include <linux/highmem.h>
19de40a8 38#include <linux/iommu.h>
62c476c7 39#include <linux/intel-iommu.h>
c8076604 40#include <linux/cpufreq.h>
18863bdd 41#include <linux/user-return-notifier.h>
a983fb23 42#include <linux/srcu.h>
5a0e3ad6 43#include <linux/slab.h>
ff9d07a0 44#include <linux/perf_event.h>
7bee342a 45#include <linux/uaccess.h>
af585b92 46#include <linux/hash.h>
aec51dc4 47#include <trace/events/kvm.h>
2ed152af 48
229456fc
MT		 49#define CREATE_TRACE_POINTS
50#include "trace.h"
043405e1 51
24f1e32c 52#include <asm/debugreg.h>
d825ed0a 53#include <asm/msr.h>
a5f61300 54#include <asm/desc.h>
0bed3b56 55#include <asm/mtrr.h>
890ca9ae 56#include <asm/mce.h>
7cf30855 57#include <asm/i387.h>
98918833 58#include <asm/xcr.h>
1d5f066e 59#include <asm/pvclock.h>
217fc9cf 60#include <asm/div64.h>
043405e1 61
313a3dc7 62#define MAX_IO_MSRS 256
890ca9ae 63#define KVM_MAX_MCE_BANKS 32
5854dbca 64#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 65
0f65dd70
AK		 66#define emul_to_vcpu(ctxt) \
67 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
68
50a37eb4
JR		 69/* EFER defaults:
70 * - enable syscall per default because its emulated by KVM
71 * - enable LME and LMA per default on 64 bit KVM
72 */
73#ifdef CONFIG_X86_64
1260edbe
LJ		 74static
75u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 76#else
1260edbe 77static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 78#endif
313a3dc7 79
ba1389b7
AK		 80#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
81#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 82
cb142eb7 83static void update_cr8_intercept(struct kvm_vcpu *vcpu);
674eea0f
AK		 84static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
85 struct kvm_cpuid_entry2 __user *entries);
86
97896d04 87struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 88EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 89
ed85c068
AP		 90int ignore_msrs = 0;
91module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
92
92a1f12d
JR		 93bool kvm_has_tsc_control;
94EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
95u32 kvm_max_guest_tsc_khz;
96EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
97
18863bdd
AK		 98#define KVM_NR_SHARED_MSRS 16
99
100struct kvm_shared_msrs_global {
101 int nr;
2bf78fa7 102 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 103};
104
105struct kvm_shared_msrs {
106 struct user_return_notifier urn;
107 bool registered;
2bf78fa7
SY		 108 struct kvm_shared_msr_values {
109 u64 host;
110 u64 curr;
111 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 112};
113
114static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
115static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
116
417bc304 117struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 118 { "pf_fixed", VCPU_STAT(pf_fixed) },
119 { "pf_guest", VCPU_STAT(pf_guest) },
120 { "tlb_flush", VCPU_STAT(tlb_flush) },
121 { "invlpg", VCPU_STAT(invlpg) },
122 { "exits", VCPU_STAT(exits) },
123 { "io_exits", VCPU_STAT(io_exits) },
124 { "mmio_exits", VCPU_STAT(mmio_exits) },
125 { "signal_exits", VCPU_STAT(signal_exits) },
126 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 127 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 128 { "halt_exits", VCPU_STAT(halt_exits) },
129 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 130 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 131 { "request_irq", VCPU_STAT(request_irq_exits) },
132 { "irq_exits", VCPU_STAT(irq_exits) },
133 { "host_state_reload", VCPU_STAT(host_state_reload) },
134 { "efer_reload", VCPU_STAT(efer_reload) },
135 { "fpu_reload", VCPU_STAT(fpu_reload) },
136 { "insn_emulation", VCPU_STAT(insn_emulation) },
137 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 138 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 139 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 140 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
141 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
142 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
143 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
144 { "mmu_flooded", VM_STAT(mmu_flooded) },
145 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 146 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 147 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 148 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 149 { "largepages", VM_STAT(lpages) },
417bc304
HB		 150 { NULL }
151};
152
2acf923e
DC		 153u64 __read_mostly host_xcr0;
154
af585b92
GN		 155static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
156{
157 int i;
158 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
159 vcpu->arch.apf.gfns[i] = ~0;
160}
161
18863bdd
AK		 162static void kvm_on_user_return(struct user_return_notifier *urn)
163{
164 unsigned slot;
18863bdd
AK		 165 struct kvm_shared_msrs *locals
166 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 167 struct kvm_shared_msr_values *values;
18863bdd
AK		 168
169 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 170 values = &locals->values[slot];
171 if (values->host != values->curr) {
172 wrmsrl(shared_msrs_global.msrs[slot], values->host);
173 values->curr = values->host;
18863bdd
AK		 174 }
175 }
176 locals->registered = false;
177 user_return_notifier_unregister(urn);
178}
179
2bf78fa7 180static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 181{
2bf78fa7 182 struct kvm_shared_msrs *smsr;
18863bdd
AK		 183 u64 value;
184
2bf78fa7
SY		 185 smsr = &__get_cpu_var(shared_msrs);
186 /* only read, and nobody should modify it at this time,
187 * so don't need lock */
188 if (slot >= shared_msrs_global.nr) {
189 printk(KERN_ERR "kvm: invalid MSR slot!");
190 return;
191 }
192 rdmsrl_safe(msr, &value);
193 smsr->values[slot].host = value;
194 smsr->values[slot].curr = value;
195}
196
197void kvm_define_shared_msr(unsigned slot, u32 msr)
198{
18863bdd
AK		 199 if (slot >= shared_msrs_global.nr)
200 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 201 shared_msrs_global.msrs[slot] = msr;
202 /* we need ensured the shared_msr_global have been updated */
203 smp_wmb();
18863bdd
AK		 204}
205EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
206
207static void kvm_shared_msr_cpu_online(void)
208{
209 unsigned i;
18863bdd
AK		 210
211 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 212 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 213}
214
d5696725 215void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 216{
217 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
218
2bf78fa7 219 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 220 return;
2bf78fa7
SY		 221 smsr->values[slot].curr = value;
222 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 223 if (!smsr->registered) {
224 smsr->urn.on_user_return = kvm_on_user_return;
225 user_return_notifier_register(&smsr->urn);
226 smsr->registered = true;
227 }
228}
229EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
230
3548bab5
AK		 231static void drop_user_return_notifiers(void *ignore)
232{
233 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
234
235 if (smsr->registered)
236 kvm_on_user_return(&smsr->urn);
237}
238
6866b83e
CO		 239u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
240{
241 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 242 return vcpu->arch.apic_base;
6866b83e 243 else
ad312c7c 244 return vcpu->arch.apic_base;
6866b83e
CO		 245}
246EXPORT_SYMBOL_GPL(kvm_get_apic_base);
247
248void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
249{
250 /* TODO: reserve bits check */
251 if (irqchip_in_kernel(vcpu->kvm))
252 kvm_lapic_set_base(vcpu, data);
253 else
ad312c7c 254 vcpu->arch.apic_base = data;
6866b83e
CO		 255}
256EXPORT_SYMBOL_GPL(kvm_set_apic_base);
257
3fd28fce
ED		 258#define EXCPT_BENIGN 0
259#define EXCPT_CONTRIBUTORY 1
260#define EXCPT_PF 2
261
262static int exception_class(int vector)
263{
264 switch (vector) {
265 case PF_VECTOR:
266 return EXCPT_PF;
267 case DE_VECTOR:
268 case TS_VECTOR:
269 case NP_VECTOR:
270 case SS_VECTOR:
271 case GP_VECTOR:
272 return EXCPT_CONTRIBUTORY;
273 default:
274 break;
275 }
276 return EXCPT_BENIGN;
277}
278
279static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 280 unsigned nr, bool has_error, u32 error_code,
281 bool reinject)
3fd28fce
ED		 282{
283 u32 prev_nr;
284 int class1, class2;
285
3842d135
AK		 286 kvm_make_request(KVM_REQ_EVENT, vcpu);
287
3fd28fce
ED		 288 if (!vcpu->arch.exception.pending) {
289 queue:
290 vcpu->arch.exception.pending = true;
291 vcpu->arch.exception.has_error_code = has_error;
292 vcpu->arch.exception.nr = nr;
293 vcpu->arch.exception.error_code = error_code;
3f0fd292 294 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 295 return;
296 }
297
298 /* to check exception */
299 prev_nr = vcpu->arch.exception.nr;
300 if (prev_nr == DF_VECTOR) {
301 /* triple fault -> shutdown */
a8eeb04a 302 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 303 return;
304 }
305 class1 = exception_class(prev_nr);
306 class2 = exception_class(nr);
307 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
308 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
309 /* generate double fault per SDM Table 5-5 */
310 vcpu->arch.exception.pending = true;
311 vcpu->arch.exception.has_error_code = true;
312 vcpu->arch.exception.nr = DF_VECTOR;
313 vcpu->arch.exception.error_code = 0;
314 } else
315 /* replace previous exception with a new one in a hope
316 that instruction re-execution will regenerate lost
317 exception */
318 goto queue;
319}
320
298101da
AK		 321void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
322{
ce7ddec4 323 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 324}
325EXPORT_SYMBOL_GPL(kvm_queue_exception);
326
ce7ddec4
JR		 327void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
328{
329 kvm_multiple_exception(vcpu, nr, false, 0, true);
330}
331EXPORT_SYMBOL_GPL(kvm_requeue_exception);
332
db8fcefa 333void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 334{
db8fcefa
AP		 335 if (err)
336 kvm_inject_gp(vcpu, 0);
337 else
338 kvm_x86_ops->skip_emulated_instruction(vcpu);
339}
340EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 341
6389ee94 342void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 343{
344 ++vcpu->stat.pf_guest;
6389ee94
AK		 345 vcpu->arch.cr2 = fault->address;
346 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee
AK		 347}
348
6389ee94 349void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 350{
6389ee94
AK		 351 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
352 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 353 else
6389ee94 354 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
d4f8cf66
JR		 355}
356
3419ffc8
SY		 357void kvm_inject_nmi(struct kvm_vcpu *vcpu)
358{
3842d135 359 kvm_make_request(KVM_REQ_EVENT, vcpu);
c761e586 360 vcpu->arch.nmi_pending = 1;
3419ffc8
SY		 361}
362EXPORT_SYMBOL_GPL(kvm_inject_nmi);
363
298101da
AK		 364void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
365{
ce7ddec4 366 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 367}
368EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
369
ce7ddec4
JR		 370void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
371{
372 kvm_multiple_exception(vcpu, nr, true, error_code, true);
373}
374EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
375
0a79b009
AK		 376/*
377 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
378 * a #GP and return false.
379 */
380bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 381{
0a79b009
AK		 382 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
383 return true;
384 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
385 return false;
298101da 386}
0a79b009 387EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 388
ec92fe44
JR		 389/*
390 * This function will be used to read from the physical memory of the currently
391 * running guest. The difference to kvm_read_guest_page is that this function
392 * can read from guest physical or from the guest's guest physical memory.
393 */
394int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
395 gfn_t ngfn, void *data, int offset, int len,
396 u32 access)
397{
398 gfn_t real_gfn;
399 gpa_t ngpa;
400
401 ngpa = gfn_to_gpa(ngfn);
402 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
403 if (real_gfn == UNMAPPED_GVA)
404 return -EFAULT;
405
406 real_gfn = gpa_to_gfn(real_gfn);
407
408 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
409}
410EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
411
3d06b8bf
JR		 412int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
413 void *data, int offset, int len, u32 access)
414{
415 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
416 data, offset, len, access);
417}
418
a03490ed
CO		 419/*
420 * Load the pae pdptrs. Return true is they are all valid.
421 */
ff03a073 422int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 423{
424 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
425 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
426 int i;
427 int ret;
ff03a073 428 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 429
ff03a073
JR		 430 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
431 offset * sizeof(u64), sizeof(pdpte),
432 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 433 if (ret < 0) {
434 ret = 0;
435 goto out;
436 }
437 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 438 if (is_present_gpte(pdpte[i]) &&
20c466b5 439 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 440 ret = 0;
441 goto out;
442 }
443 }
444 ret = 1;
445
ff03a073 446 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 447 __set_bit(VCPU_EXREG_PDPTR,
448 (unsigned long *)&vcpu->arch.regs_avail);
449 __set_bit(VCPU_EXREG_PDPTR,
450 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 451out:
a03490ed
CO		 452
453 return ret;
454}
cc4b6871 455EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 456
d835dfec
AK		 457static bool pdptrs_changed(struct kvm_vcpu *vcpu)
458{
ff03a073 459 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 460 bool changed = true;
3d06b8bf
JR		 461 int offset;
462 gfn_t gfn;
d835dfec
AK		 463 int r;
464
465 if (is_long_mode(vcpu) || !is_pae(vcpu))
466 return false;
467
6de4f3ad
AK		 468 if (!test_bit(VCPU_EXREG_PDPTR,
469 (unsigned long *)&vcpu->arch.regs_avail))
470 return true;
471
9f8fe504
AK		 472 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
473 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 474 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
475 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 476 if (r < 0)
477 goto out;
ff03a073 478 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 479out:
d835dfec
AK		 480
481 return changed;
482}
483
49a9b07e 484int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 485{
aad82703
SY		 486 unsigned long old_cr0 = kvm_read_cr0(vcpu);
487 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
488 X86_CR0_CD | X86_CR0_NW;
489
f9a48e6a
AK		 490 cr0 |= X86_CR0_ET;
491
ab344828 492#ifdef CONFIG_X86_64
0f12244f
GN		 493 if (cr0 & 0xffffffff00000000UL)
494 return 1;
ab344828
GN		 495#endif
496
497 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 498
0f12244f
GN		 499 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
500 return 1;
a03490ed 501
0f12244f
GN		 502 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
503 return 1;
a03490ed
CO		 504
505 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
506#ifdef CONFIG_X86_64
f6801dff 507 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 508 int cs_db, cs_l;
509
0f12244f
GN		 510 if (!is_pae(vcpu))
511 return 1;
a03490ed 512 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 513 if (cs_l)
514 return 1;
a03490ed
CO		 515 } else
516#endif
ff03a073 517 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 518 kvm_read_cr3(vcpu)))
0f12244f 519 return 1;
a03490ed
CO		 520 }
521
522 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 523
d170c419 524 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 525 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 526 kvm_async_pf_hash_reset(vcpu);
527 }
e5f3f027 528
aad82703
SY		 529 if ((cr0 ^ old_cr0) & update_bits)
530 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 531 return 0;
532}
2d3ad1f4 533EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 534
2d3ad1f4 535void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 536{
49a9b07e 537 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 538}
2d3ad1f4 539EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 540
2acf923e
DC		 541int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
542{
543 u64 xcr0;
544
545 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
546 if (index != XCR_XFEATURE_ENABLED_MASK)
547 return 1;
548 xcr0 = xcr;
549 if (kvm_x86_ops->get_cpl(vcpu) != 0)
550 return 1;
551 if (!(xcr0 & XSTATE_FP))
552 return 1;
553 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
554 return 1;
555 if (xcr0 & ~host_xcr0)
556 return 1;
557 vcpu->arch.xcr0 = xcr0;
558 vcpu->guest_xcr0_loaded = 0;
559 return 0;
560}
561
562int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
563{
564 if (__kvm_set_xcr(vcpu, index, xcr)) {
565 kvm_inject_gp(vcpu, 0);
566 return 1;
567 }
568 return 0;
569}
570EXPORT_SYMBOL_GPL(kvm_set_xcr);
571
572static bool guest_cpuid_has_xsave(struct kvm_vcpu *vcpu)
573{
574 struct kvm_cpuid_entry2 *best;
575
576 best = kvm_find_cpuid_entry(vcpu, 1, 0);
577 return best && (best->ecx & bit(X86_FEATURE_XSAVE));
578}
579
580static void update_cpuid(struct kvm_vcpu *vcpu)
581{
582 struct kvm_cpuid_entry2 *best;
583
584 best = kvm_find_cpuid_entry(vcpu, 1, 0);
585 if (!best)
586 return;
587
588 /* Update OSXSAVE bit */
589 if (cpu_has_xsave && best->function == 0x1) {
590 best->ecx &= ~(bit(X86_FEATURE_OSXSAVE));
591 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE))
592 best->ecx |= bit(X86_FEATURE_OSXSAVE);
593 }
594}
595
a83b29c6 596int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 597{
fc78f519 598 unsigned long old_cr4 = kvm_read_cr4(vcpu);
a2edf57f
AK		 599 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
600
0f12244f
GN		 601 if (cr4 & CR4_RESERVED_BITS)
602 return 1;
a03490ed 603
2acf923e
DC		 604 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
605 return 1;
606
a03490ed 607 if (is_long_mode(vcpu)) {
0f12244f
GN		 608 if (!(cr4 & X86_CR4_PAE))
609 return 1;
a2edf57f
AK		 610 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
611 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 612 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
613 kvm_read_cr3(vcpu)))
0f12244f
GN		 614 return 1;
615
616 if (cr4 & X86_CR4_VMXE)
617 return 1;
a03490ed 618
a03490ed 619 kvm_x86_ops->set_cr4(vcpu, cr4);
62ad0755 620
aad82703
SY		 621 if ((cr4 ^ old_cr4) & pdptr_bits)
622 kvm_mmu_reset_context(vcpu);
0f12244f 623
2acf923e
DC		 624 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
625 update_cpuid(vcpu);
626
0f12244f
GN		 627 return 0;
628}
2d3ad1f4 629EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 630
2390218b 631int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 632{
9f8fe504 633 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 634 kvm_mmu_sync_roots(vcpu);
d835dfec 635 kvm_mmu_flush_tlb(vcpu);
0f12244f 636 return 0;
d835dfec
AK		 637 }
638
a03490ed 639 if (is_long_mode(vcpu)) {
0f12244f
GN		 640 if (cr3 & CR3_L_MODE_RESERVED_BITS)
641 return 1;
a03490ed
CO		 642 } else {
643 if (is_pae(vcpu)) {
0f12244f
GN		 644 if (cr3 & CR3_PAE_RESERVED_BITS)
645 return 1;
ff03a073
JR		 646 if (is_paging(vcpu) &&
647 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
0f12244f 648 return 1;
a03490ed
CO		 649 }
650 /*
651 * We don't check reserved bits in nonpae mode, because
652 * this isn't enforced, and VMware depends on this.
653 */
654 }
655
a03490ed
CO		 656 /*
657 * Does the new cr3 value map to physical memory? (Note, we
658 * catch an invalid cr3 even in real-mode, because it would
659 * cause trouble later on when we turn on paging anyway.)
660 *
661 * A real CPU would silently accept an invalid cr3 and would
662 * attempt to use it - with largely undefined (and often hard
663 * to debug) behavior on the guest side.
664 */
665 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
0f12244f
GN		 666 return 1;
667 vcpu->arch.cr3 = cr3;
aff48baa 668 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
0f12244f
GN		 669 vcpu->arch.mmu.new_cr3(vcpu);
670 return 0;
671}
2d3ad1f4 672EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 673
eea1cff9 674int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 675{
0f12244f
GN		 676 if (cr8 & CR8_RESERVED_BITS)
677 return 1;
a03490ed
CO		 678 if (irqchip_in_kernel(vcpu->kvm))
679 kvm_lapic_set_tpr(vcpu, cr8);
680 else
ad312c7c 681 vcpu->arch.cr8 = cr8;
0f12244f
GN		 682 return 0;
683}
2d3ad1f4 684EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 685
2d3ad1f4 686unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 687{
688 if (irqchip_in_kernel(vcpu->kvm))
689 return kvm_lapic_get_cr8(vcpu);
690 else
ad312c7c 691 return vcpu->arch.cr8;
a03490ed 692}
2d3ad1f4 693EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 694
338dbc97 695static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 696{
697 switch (dr) {
698 case 0 ... 3:
699 vcpu->arch.db[dr] = val;
700 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
701 vcpu->arch.eff_db[dr] = val;
702 break;
703 case 4:
338dbc97
GN		 704 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
705 return 1; /* #UD */
020df079
GN		 706 /* fall through */
707 case 6:
338dbc97
GN		 708 if (val & 0xffffffff00000000ULL)
709 return -1; /* #GP */
020df079
GN		 710 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
711 break;
712 case 5:
338dbc97
GN		 713 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
714 return 1; /* #UD */
020df079
GN		 715 /* fall through */
716 default: /* 7 */
338dbc97
GN		 717 if (val & 0xffffffff00000000ULL)
718 return -1; /* #GP */
020df079
GN		 719 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
720 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
721 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
722 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
723 }
724 break;
725 }
726
727 return 0;
728}
338dbc97
GN		 729
730int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
731{
732 int res;
733
734 res = __kvm_set_dr(vcpu, dr, val);
735 if (res > 0)
736 kvm_queue_exception(vcpu, UD_VECTOR);
737 else if (res < 0)
738 kvm_inject_gp(vcpu, 0);
739
740 return res;
741}
020df079
GN		 742EXPORT_SYMBOL_GPL(kvm_set_dr);
743
338dbc97 744static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 745{
746 switch (dr) {
747 case 0 ... 3:
748 *val = vcpu->arch.db[dr];
749 break;
750 case 4:
338dbc97 751 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 752 return 1;
020df079
GN		 753 /* fall through */
754 case 6:
755 *val = vcpu->arch.dr6;
756 break;
757 case 5:
338dbc97 758 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 759 return 1;
020df079
GN		 760 /* fall through */
761 default: /* 7 */
762 *val = vcpu->arch.dr7;
763 break;
764 }
765
766 return 0;
767}
338dbc97
GN		 768
769int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
770{
771 if (_kvm_get_dr(vcpu, dr, val)) {
772 kvm_queue_exception(vcpu, UD_VECTOR);
773 return 1;
774 }
775 return 0;
776}
020df079
GN		 777EXPORT_SYMBOL_GPL(kvm_get_dr);
778
043405e1
CO		 779/*
780 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
781 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
782 *
783 * This list is modified at module load time to reflect the
e3267cbb
GC		 784 * capabilities of the host cpu. This capabilities test skips MSRs that are
785 * kvm-specific. Those are put in the beginning of the list.
043405e1 786 */
e3267cbb 787
344d9588 788#define KVM_SAVE_MSRS_BEGIN 8
043405e1 789static u32 msrs_to_save[] = {
e3267cbb 790 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 791 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 792 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
344d9588 793 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN,
043405e1 794 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 795 MSR_STAR,
043405e1
CO		 796#ifdef CONFIG_X86_64
797 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
798#endif
e90aa41e 799 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 800};
801
802static unsigned num_msrs_to_save;
803
804static u32 emulated_msrs[] = {
805 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 806 MSR_IA32_MCG_STATUS,
807 MSR_IA32_MCG_CTL,
043405e1
CO		 808};
809
b69e8cae 810static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 811{
aad82703
SY		 812 u64 old_efer = vcpu->arch.efer;
813
b69e8cae
RJ		 814 if (efer & efer_reserved_bits)
815 return 1;
15c4a640
CO		 816
817 if (is_paging(vcpu)
b69e8cae
RJ		 818 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
819 return 1;
15c4a640 820
1b2fd70c
AG		 821 if (efer & EFER_FFXSR) {
822 struct kvm_cpuid_entry2 *feat;
823
824 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 825 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
826 return 1;
1b2fd70c
AG		 827 }
828
d8017474
AG		 829 if (efer & EFER_SVME) {
830 struct kvm_cpuid_entry2 *feat;
831
832 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 833 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
834 return 1;
d8017474
AG		 835 }
836
15c4a640 837 efer &= ~EFER_LMA;
f6801dff 838 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 839
a3d204e2
SY		 840 kvm_x86_ops->set_efer(vcpu, efer);
841
9645bb56 842 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
b69e8cae 843
aad82703
SY		 844 /* Update reserved bits */
845 if ((efer ^ old_efer) & EFER_NX)
846 kvm_mmu_reset_context(vcpu);
847
b69e8cae 848 return 0;
15c4a640
CO		 849}
850
f2b4b7dd
JR		 851void kvm_enable_efer_bits(u64 mask)
852{
853 efer_reserved_bits &= ~mask;
854}
855EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
856
857
15c4a640
CO		 858/*
859 * Writes msr value into into the appropriate "register".
860 * Returns 0 on success, non-0 otherwise.
861 * Assumes vcpu_load() was already called.
862 */
863int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
864{
865 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
866}
867
313a3dc7
CO		 868/*
869 * Adapt set_msr() to msr_io()'s calling convention
870 */
871static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
872{
873 return kvm_set_msr(vcpu, index, *data);
874}
875
18068523
GOC		 876static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
877{
9ed3c444
AK		 878 int version;
879 int r;
50d0a0f9 880 struct pvclock_wall_clock wc;
923de3cf 881 struct timespec boot;
18068523
GOC		 882
883 if (!wall_clock)
884 return;
885
9ed3c444
AK		 886 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
887 if (r)
888 return;
889
890 if (version & 1)
891 ++version; /* first time write, random junk */
892
893 ++version;
18068523 894
18068523
GOC		 895 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
896
50d0a0f9
GH		 897 /*
898 * The guest calculates current wall clock time by adding
34c238a1 899 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 900 * wall clock specified here. guest system time equals host
901 * system time for us, thus we must fill in host boot time here.
902 */
923de3cf 903 getboottime(&boot);
50d0a0f9
GH		 904
905 wc.sec = boot.tv_sec;
906 wc.nsec = boot.tv_nsec;
907 wc.version = version;
18068523
GOC		 908
909 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
910
911 version++;
912 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 913}
914
50d0a0f9
GH		 915static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
916{
917 uint32_t quotient, remainder;
918
919 /* Don't try to replace with do_div(), this one calculates
920 * "(dividend << 32) / divisor" */
921 __asm__ ( "divl %4"
922 : "=a" (quotient), "=d" (remainder)
923 : "0" (0), "1" (dividend), "r" (divisor) );
924 return quotient;
925}
926
5f4e3f88
ZA		 927static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
928 s8 *pshift, u32 *pmultiplier)
50d0a0f9 929{
5f4e3f88 930 uint64_t scaled64;
50d0a0f9
GH		 931 int32_t shift = 0;
932 uint64_t tps64;
933 uint32_t tps32;
934
5f4e3f88
ZA		 935 tps64 = base_khz * 1000LL;
936 scaled64 = scaled_khz * 1000LL;
50933623 937 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 938 tps64 >>= 1;
939 shift--;
940 }
941
942 tps32 = (uint32_t)tps64;
50933623
JK		 943 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
944 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 945 scaled64 >>= 1;
946 else
947 tps32 <<= 1;
50d0a0f9
GH		 948 shift++;
949 }
950
5f4e3f88
ZA		 951 *pshift = shift;
952 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 953
5f4e3f88
ZA		 954 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
955 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 956}
957
759379dd
ZA		 958static inline u64 get_kernel_ns(void)
959{
960 struct timespec ts;
961
962 WARN_ON(preemptible());
963 ktime_get_ts(&ts);
964 monotonic_to_bootbased(&ts);
965 return timespec_to_ns(&ts);
50d0a0f9
GH		 966}
967
c8076604 968static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 969unsigned long max_tsc_khz;
c8076604 970
8cfdc000
ZA		 971static inline int kvm_tsc_changes_freq(void)
972{
973 int cpu = get_cpu();
974 int ret = !boot_cpu_has(X86_FEATURE_CONSTANT_TSC) &&
975 cpufreq_quick_get(cpu) != 0;
976 put_cpu();
977 return ret;
978}
979
1e993611
JR		 980static u64 vcpu_tsc_khz(struct kvm_vcpu *vcpu)
981{
982 if (vcpu->arch.virtual_tsc_khz)
983 return vcpu->arch.virtual_tsc_khz;
984 else
985 return __this_cpu_read(cpu_tsc_khz);
986}
987
857e4099 988static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
759379dd 989{
217fc9cf
AK		 990 u64 ret;
991
759379dd
ZA		 992 WARN_ON(preemptible());
993 if (kvm_tsc_changes_freq())
994 printk_once(KERN_WARNING
995 "kvm: unreliable cycle conversion on adjustable rate TSC\n");
857e4099 996 ret = nsec * vcpu_tsc_khz(vcpu);
217fc9cf
AK		 997 do_div(ret, USEC_PER_SEC);
998 return ret;
759379dd
ZA		 999}
1000
1e993611 1001static void kvm_init_tsc_catchup(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
c285545f
ZA		 1002{
1003 /* Compute a scale to convert nanoseconds in TSC cycles */
1004 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
1e993611
JR		 1005 &vcpu->arch.tsc_catchup_shift,
1006 &vcpu->arch.tsc_catchup_mult);
c285545f
ZA		 1007}
1008
1009static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1010{
1011 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.last_tsc_nsec,
1e993611
JR		 1012 vcpu->arch.tsc_catchup_mult,
1013 vcpu->arch.tsc_catchup_shift);
c285545f
ZA		 1014 tsc += vcpu->arch.last_tsc_write;
1015 return tsc;
1016}
1017
99e3e30a
ZA		 1018void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
1019{
1020 struct kvm *kvm = vcpu->kvm;
f38e098f 1021 u64 offset, ns, elapsed;
99e3e30a 1022 unsigned long flags;
46543ba4 1023 s64 sdiff;
99e3e30a 1024
038f8c11 1025 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1026 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1027 ns = get_kernel_ns();
f38e098f 1028 elapsed = ns - kvm->arch.last_tsc_nsec;
46543ba4
ZA		 1029 sdiff = data - kvm->arch.last_tsc_write;
1030 if (sdiff < 0)
1031 sdiff = -sdiff;
f38e098f
ZA		 1032
1033 /*
46543ba4 1034 * Special case: close write to TSC within 5 seconds of
f38e098f 1035 * another CPU is interpreted as an attempt to synchronize
0d2eb44f 1036 * The 5 seconds is to accommodate host load / swapping as
46543ba4 1037 * well as any reset of TSC during the boot process.
f38e098f
ZA		 1038 *
1039 * In that case, for a reliable TSC, we can match TSC offsets,
46543ba4 1040 * or make a best guest using elapsed value.
f38e098f 1041 */
857e4099 1042 if (sdiff < nsec_to_cycles(vcpu, 5ULL * NSEC_PER_SEC) &&
46543ba4 1043 elapsed < 5ULL * NSEC_PER_SEC) {
f38e098f
ZA		 1044 if (!check_tsc_unstable()) {
1045 offset = kvm->arch.last_tsc_offset;
1046 pr_debug("kvm: matched tsc offset for %llu\n", data);
1047 } else {
857e4099 1048 u64 delta = nsec_to_cycles(vcpu, elapsed);
759379dd
ZA		 1049 offset += delta;
1050 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f
ZA		 1051 }
1052 ns = kvm->arch.last_tsc_nsec;
1053 }
1054 kvm->arch.last_tsc_nsec = ns;
1055 kvm->arch.last_tsc_write = data;
1056 kvm->arch.last_tsc_offset = offset;
99e3e30a 1057 kvm_x86_ops->write_tsc_offset(vcpu, offset);
038f8c11 1058 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
99e3e30a
ZA		 1059
1060 /* Reset of TSC must disable overshoot protection below */
1061 vcpu->arch.hv_clock.tsc_timestamp = 0;
c285545f
ZA		 1062 vcpu->arch.last_tsc_write = data;
1063 vcpu->arch.last_tsc_nsec = ns;
99e3e30a
ZA		 1064}
1065EXPORT_SYMBOL_GPL(kvm_write_tsc);
1066
34c238a1 1067static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1068{
18068523
GOC		 1069 unsigned long flags;
1070 struct kvm_vcpu_arch *vcpu = &v->arch;
1071 void *shared_kaddr;
463656c0 1072 unsigned long this_tsc_khz;
1d5f066e
ZA		 1073 s64 kernel_ns, max_kernel_ns;
1074 u64 tsc_timestamp;
18068523 1075
18068523
GOC		 1076 /* Keep irq disabled to prevent changes to the clock */
1077 local_irq_save(flags);
1d5f066e 1078 kvm_get_msr(v, MSR_IA32_TSC, &tsc_timestamp);
759379dd 1079 kernel_ns = get_kernel_ns();
1e993611 1080 this_tsc_khz = vcpu_tsc_khz(v);
8cfdc000 1081 if (unlikely(this_tsc_khz == 0)) {
c285545f 1082 local_irq_restore(flags);
34c238a1 1083 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
8cfdc000
ZA		 1084 return 1;
1085 }
18068523 1086
c285545f
ZA		 1087 /*
1088 * We may have to catch up the TSC to match elapsed wall clock
1089 * time for two reasons, even if kvmclock is used.
1090 * 1) CPU could have been running below the maximum TSC rate
1091 * 2) Broken TSC compensation resets the base at each VCPU
1092 * entry to avoid unknown leaps of TSC even when running
1093 * again on the same CPU. This may cause apparent elapsed
1094 * time to disappear, and the guest to stand still or run
1095 * very slowly.
1096 */
1097 if (vcpu->tsc_catchup) {
1098 u64 tsc = compute_guest_tsc(v, kernel_ns);
1099 if (tsc > tsc_timestamp) {
1100 kvm_x86_ops->adjust_tsc_offset(v, tsc - tsc_timestamp);
1101 tsc_timestamp = tsc;
1102 }
50d0a0f9
GH		 1103 }
1104
18068523
GOC		 1105 local_irq_restore(flags);
1106
c285545f
ZA		 1107 if (!vcpu->time_page)
1108 return 0;
18068523 1109
1d5f066e
ZA		 1110 /*
1111 * Time as measured by the TSC may go backwards when resetting the base
1112 * tsc_timestamp. The reason for this is that the TSC resolution is
1113 * higher than the resolution of the other clock scales. Thus, many
1114 * possible measurments of the TSC correspond to one measurement of any
1115 * other clock, and so a spread of values is possible. This is not a
1116 * problem for the computation of the nanosecond clock; with TSC rates
1117 * around 1GHZ, there can only be a few cycles which correspond to one
1118 * nanosecond value, and any path through this code will inevitably
1119 * take longer than that. However, with the kernel_ns value itself,
1120 * the precision may be much lower, down to HZ granularity. If the
1121 * first sampling of TSC against kernel_ns ends in the low part of the
1122 * range, and the second in the high end of the range, we can get:
1123 *
1124 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1125 *
1126 * As the sampling errors potentially range in the thousands of cycles,
1127 * it is possible such a time value has already been observed by the
1128 * guest. To protect against this, we must compute the system time as
1129 * observed by the guest and ensure the new system time is greater.
1130 */
1131 max_kernel_ns = 0;
1132 if (vcpu->hv_clock.tsc_timestamp && vcpu->last_guest_tsc) {
1133 max_kernel_ns = vcpu->last_guest_tsc -
1134 vcpu->hv_clock.tsc_timestamp;
1135 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1136 vcpu->hv_clock.tsc_to_system_mul,
1137 vcpu->hv_clock.tsc_shift);
1138 max_kernel_ns += vcpu->last_kernel_ns;
1139 }
afbcf7ab 1140
e48672fa 1141 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1142 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1143 &vcpu->hv_clock.tsc_shift,
1144 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1145 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1146 }
1147
1d5f066e
ZA		 1148 if (max_kernel_ns > kernel_ns)
1149 kernel_ns = max_kernel_ns;
1150
8cfdc000 1151 /* With all the info we got, fill in the values */
1d5f066e 1152 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1153 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1d5f066e 1154 vcpu->last_kernel_ns = kernel_ns;
28e4639a 1155 vcpu->last_guest_tsc = tsc_timestamp;
371bcf64
GC		 1156 vcpu->hv_clock.flags = 0;
1157
18068523
GOC		 1158 /*
1159 * The interface expects us to write an even number signaling that the
1160 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1161 * state, we just increase by 2 at the end.
18068523 1162 */
50d0a0f9 1163 vcpu->hv_clock.version += 2;
18068523
GOC		 1164
1165 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
1166
1167 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 1168 sizeof(vcpu->hv_clock));
18068523
GOC		 1169
1170 kunmap_atomic(shared_kaddr, KM_USER0);
1171
1172 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
8cfdc000 1173 return 0;
c8076604
GH		 1174}
1175
9ba075a6
AK		 1176static bool msr_mtrr_valid(unsigned msr)
1177{
1178 switch (msr) {
1179 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1180 case MSR_MTRRfix64K_00000:
1181 case MSR_MTRRfix16K_80000:
1182 case MSR_MTRRfix16K_A0000:
1183 case MSR_MTRRfix4K_C0000:
1184 case MSR_MTRRfix4K_C8000:
1185 case MSR_MTRRfix4K_D0000:
1186 case MSR_MTRRfix4K_D8000:
1187 case MSR_MTRRfix4K_E0000:
1188 case MSR_MTRRfix4K_E8000:
1189 case MSR_MTRRfix4K_F0000:
1190 case MSR_MTRRfix4K_F8000:
1191 case MSR_MTRRdefType:
1192 case MSR_IA32_CR_PAT:
1193 return true;
1194 case 0x2f8:
1195 return true;
1196 }
1197 return false;
1198}
1199
d6289b93
MT		 1200static bool valid_pat_type(unsigned t)
1201{
1202 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1203}
1204
1205static bool valid_mtrr_type(unsigned t)
1206{
1207 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1208}
1209
1210static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1211{
1212 int i;
1213
1214 if (!msr_mtrr_valid(msr))
1215 return false;
1216
1217 if (msr == MSR_IA32_CR_PAT) {
1218 for (i = 0; i < 8; i++)
1219 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1220 return false;
1221 return true;
1222 } else if (msr == MSR_MTRRdefType) {
1223 if (data & ~0xcff)
1224 return false;
1225 return valid_mtrr_type(data & 0xff);
1226 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1227 for (i = 0; i < 8 ; i++)
1228 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1229 return false;
1230 return true;
1231 }
1232
1233 /* variable MTRRs */
1234 return valid_mtrr_type(data & 0xff);
1235}
1236
9ba075a6
AK		 1237static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1238{
0bed3b56
SY		 1239 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1240
d6289b93 1241 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1242 return 1;
1243
0bed3b56
SY		 1244 if (msr == MSR_MTRRdefType) {
1245 vcpu->arch.mtrr_state.def_type = data;
1246 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1247 } else if (msr == MSR_MTRRfix64K_00000)
1248 p[0] = data;
1249 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1250 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1251 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1252 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1253 else if (msr == MSR_IA32_CR_PAT)
1254 vcpu->arch.pat = data;
1255 else { /* Variable MTRRs */
1256 int idx, is_mtrr_mask;
1257 u64 *pt;
1258
1259 idx = (msr - 0x200) / 2;
1260 is_mtrr_mask = msr - 0x200 - 2 * idx;
1261 if (!is_mtrr_mask)
1262 pt =
1263 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1264 else
1265 pt =
1266 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1267 *pt = data;
1268 }
1269
1270 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1271 return 0;
1272}
15c4a640 1273
890ca9ae 1274static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1275{
890ca9ae
HY		 1276 u64 mcg_cap = vcpu->arch.mcg_cap;
1277 unsigned bank_num = mcg_cap & 0xff;
1278
15c4a640 1279 switch (msr) {
15c4a640 1280 case MSR_IA32_MCG_STATUS:
890ca9ae 1281 vcpu->arch.mcg_status = data;
15c4a640 1282 break;
c7ac679c 1283 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1284 if (!(mcg_cap & MCG_CTL_P))
1285 return 1;
1286 if (data != 0 && data != ~(u64)0)
1287 return -1;
1288 vcpu->arch.mcg_ctl = data;
1289 break;
1290 default:
1291 if (msr >= MSR_IA32_MC0_CTL &&
1292 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1293 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1294 /* only 0 or all 1s can be written to IA32_MCi_CTL
1295 * some Linux kernels though clear bit 10 in bank 4 to
1296 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1297 * this to avoid an uncatched #GP in the guest
1298 */
890ca9ae 1299 if ((offset & 0x3) == 0 &&
114be429 1300 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1301 return -1;
1302 vcpu->arch.mce_banks[offset] = data;
1303 break;
1304 }
1305 return 1;
1306 }
1307 return 0;
1308}
1309
ffde22ac
ES		 1310static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1311{
1312 struct kvm *kvm = vcpu->kvm;
1313 int lm = is_long_mode(vcpu);
1314 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1315 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1316 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1317 : kvm->arch.xen_hvm_config.blob_size_32;
1318 u32 page_num = data & ~PAGE_MASK;
1319 u64 page_addr = data & PAGE_MASK;
1320 u8 *page;
1321 int r;
1322
1323 r = -E2BIG;
1324 if (page_num >= blob_size)
1325 goto out;
1326 r = -ENOMEM;
1327 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
1328 if (!page)
1329 goto out;
1330 r = -EFAULT;
1331 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
1332 goto out_free;
1333 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1334 goto out_free;
1335 r = 0;
1336out_free:
1337 kfree(page);
1338out:
1339 return r;
1340}
1341
55cd8e5a
GN		 1342static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1343{
1344 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1345}
1346
1347static bool kvm_hv_msr_partition_wide(u32 msr)
1348{
1349 bool r = false;
1350 switch (msr) {
1351 case HV_X64_MSR_GUEST_OS_ID:
1352 case HV_X64_MSR_HYPERCALL:
1353 r = true;
1354 break;
1355 }
1356
1357 return r;
1358}
1359
1360static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1361{
1362 struct kvm *kvm = vcpu->kvm;
1363
1364 switch (msr) {
1365 case HV_X64_MSR_GUEST_OS_ID:
1366 kvm->arch.hv_guest_os_id = data;
1367 /* setting guest os id to zero disables hypercall page */
1368 if (!kvm->arch.hv_guest_os_id)
1369 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1370 break;
1371 case HV_X64_MSR_HYPERCALL: {
1372 u64 gfn;
1373 unsigned long addr;
1374 u8 instructions[4];
1375
1376 /* if guest os id is not set hypercall should remain disabled */
1377 if (!kvm->arch.hv_guest_os_id)
1378 break;
1379 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1380 kvm->arch.hv_hypercall = data;
1381 break;
1382 }
1383 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1384 addr = gfn_to_hva(kvm, gfn);
1385 if (kvm_is_error_hva(addr))
1386 return 1;
1387 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1388 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1389 if (copy_to_user((void __user *)addr, instructions, 4))
1390 return 1;
1391 kvm->arch.hv_hypercall = data;
1392 break;
1393 }
1394 default:
1395 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1396 "data 0x%llx\n", msr, data);
1397 return 1;
1398 }
1399 return 0;
1400}
1401
1402static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1403{
10388a07
GN		 1404 switch (msr) {
1405 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1406 unsigned long addr;
55cd8e5a 1407
10388a07
GN		 1408 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1409 vcpu->arch.hv_vapic = data;
1410 break;
1411 }
1412 addr = gfn_to_hva(vcpu->kvm, data >>
1413 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1414 if (kvm_is_error_hva(addr))
1415 return 1;
1416 if (clear_user((void __user *)addr, PAGE_SIZE))
1417 return 1;
1418 vcpu->arch.hv_vapic = data;
1419 break;
1420 }
1421 case HV_X64_MSR_EOI:
1422 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1423 case HV_X64_MSR_ICR:
1424 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1425 case HV_X64_MSR_TPR:
1426 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1427 default:
1428 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1429 "data 0x%llx\n", msr, data);
1430 return 1;
1431 }
1432
1433 return 0;
55cd8e5a
GN		 1434}
1435
344d9588
GN		 1436static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1437{
1438 gpa_t gpa = data & ~0x3f;
1439
6adba527
GN		 1440 /* Bits 2:5 are resrved, Should be zero */
1441 if (data & 0x3c)
344d9588
GN		 1442 return 1;
1443
1444 vcpu->arch.apf.msr_val = data;
1445
1446 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1447 kvm_clear_async_pf_completion_queue(vcpu);
1448 kvm_async_pf_hash_reset(vcpu);
1449 return 0;
1450 }
1451
1452 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa))
1453 return 1;
1454
6adba527 1455 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1456 kvm_async_pf_wakeup_all(vcpu);
1457 return 0;
1458}
1459
12f9a48f
GC		 1460static void kvmclock_reset(struct kvm_vcpu *vcpu)
1461{
1462 if (vcpu->arch.time_page) {
1463 kvm_release_page_dirty(vcpu->arch.time_page);
1464 vcpu->arch.time_page = NULL;
1465 }
1466}
1467
15c4a640
CO		 1468int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1469{
1470 switch (msr) {
15c4a640 1471 case MSR_EFER:
b69e8cae 1472 return set_efer(vcpu, data);
8f1589d9
AP		 1473 case MSR_K7_HWCR:
1474 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1475 data &= ~(u64)0x100; /* ignore ignne emulation enable */
8f1589d9
AP		 1476 if (data != 0) {
1477 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1478 data);
1479 return 1;
1480 }
15c4a640 1481 break;
f7c6d140
AP		 1482 case MSR_FAM10H_MMIO_CONF_BASE:
1483 if (data != 0) {
1484 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1485 "0x%llx\n", data);
1486 return 1;
1487 }
15c4a640 1488 break;
c323c0e5 1489 case MSR_AMD64_NB_CFG:
c7ac679c 1490 break;
b5e2fec0
AG		 1491 case MSR_IA32_DEBUGCTLMSR:
1492 if (!data) {
1493 /* We support the non-activated case already */
1494 break;
1495 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1496 /* Values other than LBR and BTF are vendor-specific,
1497 thus reserved and should throw a #GP */
1498 return 1;
1499 }
1500 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1501 __func__, data);
1502 break;
15c4a640
CO		 1503 case MSR_IA32_UCODE_REV:
1504 case MSR_IA32_UCODE_WRITE:
61a6bd67 1505 case MSR_VM_HSAVE_PA:
6098ca93 1506 case MSR_AMD64_PATCH_LOADER:
15c4a640 1507 break;
9ba075a6
AK		 1508 case 0x200 ... 0x2ff:
1509 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1510 case MSR_IA32_APICBASE:
1511 kvm_set_apic_base(vcpu, data);
1512 break;
0105d1a5
GN		 1513 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1514 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 1515 case MSR_IA32_MISC_ENABLE:
ad312c7c 1516 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1517 break;
11c6bffa 1518 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1519 case MSR_KVM_WALL_CLOCK:
1520 vcpu->kvm->arch.wall_clock = data;
1521 kvm_write_wall_clock(vcpu->kvm, data);
1522 break;
11c6bffa 1523 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 1524 case MSR_KVM_SYSTEM_TIME: {
12f9a48f 1525 kvmclock_reset(vcpu);
18068523
GOC		 1526
1527 vcpu->arch.time = data;
c285545f 1528 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
18068523
GOC		 1529
1530 /* we verify if the enable bit is set... */
1531 if (!(data & 1))
1532 break;
1533
1534 /* ...but clean it before doing the actual write */
1535 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1536
18068523
GOC		 1537 vcpu->arch.time_page =
1538 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1539
1540 if (is_error_page(vcpu->arch.time_page)) {
1541 kvm_release_page_clean(vcpu->arch.time_page);
1542 vcpu->arch.time_page = NULL;
1543 }
18068523
GOC		 1544 break;
1545 }
344d9588
GN		 1546 case MSR_KVM_ASYNC_PF_EN:
1547 if (kvm_pv_enable_async_pf(vcpu, data))
1548 return 1;
1549 break;
890ca9ae
HY		 1550 case MSR_IA32_MCG_CTL:
1551 case MSR_IA32_MCG_STATUS:
1552 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1553 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1554
1555 /* Performance counters are not protected by a CPUID bit,
1556 * so we should check all of them in the generic path for the sake of
1557 * cross vendor migration.
1558 * Writing a zero into the event select MSRs disables them,
1559 * which we perfectly emulate ;-). Any other value should be at least
1560 * reported, some guests depend on them.
1561 */
1562 case MSR_P6_EVNTSEL0:
1563 case MSR_P6_EVNTSEL1:
1564 case MSR_K7_EVNTSEL0:
1565 case MSR_K7_EVNTSEL1:
1566 case MSR_K7_EVNTSEL2:
1567 case MSR_K7_EVNTSEL3:
1568 if (data != 0)
1569 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1570 "0x%x data 0x%llx\n", msr, data);
1571 break;
1572 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1573 * so we ignore writes to make it happy.
1574 */
1575 case MSR_P6_PERFCTR0:
1576 case MSR_P6_PERFCTR1:
1577 case MSR_K7_PERFCTR0:
1578 case MSR_K7_PERFCTR1:
1579 case MSR_K7_PERFCTR2:
1580 case MSR_K7_PERFCTR3:
1581 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1582 "0x%x data 0x%llx\n", msr, data);
1583 break;
84e0cefa
JS		 1584 case MSR_K7_CLK_CTL:
1585 /*
1586 * Ignore all writes to this no longer documented MSR.
1587 * Writes are only relevant for old K7 processors,
1588 * all pre-dating SVM, but a recommended workaround from
1589 * AMD for these chips. It is possible to speicify the
1590 * affected processor models on the command line, hence
1591 * the need to ignore the workaround.
1592 */
1593 break;
55cd8e5a
GN		 1594 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1595 if (kvm_hv_msr_partition_wide(msr)) {
1596 int r;
1597 mutex_lock(&vcpu->kvm->lock);
1598 r = set_msr_hyperv_pw(vcpu, msr, data);
1599 mutex_unlock(&vcpu->kvm->lock);
1600 return r;
1601 } else
1602 return set_msr_hyperv(vcpu, msr, data);
1603 break;
91c9c3ed 1604 case MSR_IA32_BBL_CR_CTL3:
1605 /* Drop writes to this legacy MSR -- see rdmsr
1606 * counterpart for further detail.
1607 */
1608 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
1609 break;
15c4a640 1610 default:
ffde22ac
ES		 1611 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1612 return xen_hvm_config(vcpu, data);
ed85c068
AP		 1613 if (!ignore_msrs) {
1614 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1615 msr, data);
1616 return 1;
1617 } else {
1618 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1619 msr, data);
1620 break;
1621 }
15c4a640
CO		 1622 }
1623 return 0;
1624}
1625EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1626
1627
1628/*
1629 * Reads an msr value (of 'msr_index') into 'pdata'.
1630 * Returns 0 on success, non-0 otherwise.
1631 * Assumes vcpu_load() was already called.
1632 */
1633int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1634{
1635 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1636}
1637
9ba075a6
AK		 1638static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1639{
0bed3b56
SY		 1640 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1641
9ba075a6
AK		 1642 if (!msr_mtrr_valid(msr))
1643 return 1;
1644
0bed3b56
SY		 1645 if (msr == MSR_MTRRdefType)
1646 *pdata = vcpu->arch.mtrr_state.def_type +
1647 (vcpu->arch.mtrr_state.enabled << 10);
1648 else if (msr == MSR_MTRRfix64K_00000)
1649 *pdata = p[0];
1650 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1651 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1652 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1653 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1654 else if (msr == MSR_IA32_CR_PAT)
1655 *pdata = vcpu->arch.pat;
1656 else { /* Variable MTRRs */
1657 int idx, is_mtrr_mask;
1658 u64 *pt;
1659
1660 idx = (msr - 0x200) / 2;
1661 is_mtrr_mask = msr - 0x200 - 2 * idx;
1662 if (!is_mtrr_mask)
1663 pt =
1664 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1665 else
1666 pt =
1667 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1668 *pdata = *pt;
1669 }
1670
9ba075a6
AK		 1671 return 0;
1672}
1673
890ca9ae 1674static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1675{
1676 u64 data;
890ca9ae
HY		 1677 u64 mcg_cap = vcpu->arch.mcg_cap;
1678 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1679
1680 switch (msr) {
15c4a640
CO		 1681 case MSR_IA32_P5_MC_ADDR:
1682 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1683 data = 0;
1684 break;
15c4a640 1685 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1686 data = vcpu->arch.mcg_cap;
1687 break;
c7ac679c 1688 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1689 if (!(mcg_cap & MCG_CTL_P))
1690 return 1;
1691 data = vcpu->arch.mcg_ctl;
1692 break;
1693 case MSR_IA32_MCG_STATUS:
1694 data = vcpu->arch.mcg_status;
1695 break;
1696 default:
1697 if (msr >= MSR_IA32_MC0_CTL &&
1698 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1699 u32 offset = msr - MSR_IA32_MC0_CTL;
1700 data = vcpu->arch.mce_banks[offset];
1701 break;
1702 }
1703 return 1;
1704 }
1705 *pdata = data;
1706 return 0;
1707}
1708
55cd8e5a
GN		 1709static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1710{
1711 u64 data = 0;
1712 struct kvm *kvm = vcpu->kvm;
1713
1714 switch (msr) {
1715 case HV_X64_MSR_GUEST_OS_ID:
1716 data = kvm->arch.hv_guest_os_id;
1717 break;
1718 case HV_X64_MSR_HYPERCALL:
1719 data = kvm->arch.hv_hypercall;
1720 break;
1721 default:
1722 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1723 return 1;
1724 }
1725
1726 *pdata = data;
1727 return 0;
1728}
1729
1730static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1731{
1732 u64 data = 0;
1733
1734 switch (msr) {
1735 case HV_X64_MSR_VP_INDEX: {
1736 int r;
1737 struct kvm_vcpu *v;
1738 kvm_for_each_vcpu(r, v, vcpu->kvm)
1739 if (v == vcpu)
1740 data = r;
1741 break;
1742 }
10388a07
GN		 1743 case HV_X64_MSR_EOI:
1744 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1745 case HV_X64_MSR_ICR:
1746 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1747 case HV_X64_MSR_TPR:
1748 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
55cd8e5a
GN		 1749 default:
1750 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1751 return 1;
1752 }
1753 *pdata = data;
1754 return 0;
1755}
1756
890ca9ae
HY		 1757int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1758{
1759 u64 data;
1760
1761 switch (msr) {
890ca9ae 1762 case MSR_IA32_PLATFORM_ID:
15c4a640 1763 case MSR_IA32_UCODE_REV:
15c4a640 1764 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1765 case MSR_IA32_DEBUGCTLMSR:
1766 case MSR_IA32_LASTBRANCHFROMIP:
1767 case MSR_IA32_LASTBRANCHTOIP:
1768 case MSR_IA32_LASTINTFROMIP:
1769 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1770 case MSR_K8_SYSCFG:
1771 case MSR_K7_HWCR:
61a6bd67 1772 case MSR_VM_HSAVE_PA:
1f3ee616
AS		 1773 case MSR_P6_PERFCTR0:
1774 case MSR_P6_PERFCTR1:
7fe29e0f
AS		 1775 case MSR_P6_EVNTSEL0:
1776 case MSR_P6_EVNTSEL1:
9e699624 1777 case MSR_K7_EVNTSEL0:
1f3ee616 1778 case MSR_K7_PERFCTR0:
1fdbd48c 1779 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1780 case MSR_AMD64_NB_CFG:
f7c6d140 1781 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1782 data = 0;
1783 break;
9ba075a6
AK		 1784 case MSR_MTRRcap:
1785 data = 0x500 | KVM_NR_VAR_MTRR;
1786 break;
1787 case 0x200 ... 0x2ff:
1788 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1789 case 0xcd: /* fsb frequency */
1790 data = 3;
1791 break;
7b914098
JS		 1792 /*
1793 * MSR_EBC_FREQUENCY_ID
1794 * Conservative value valid for even the basic CPU models.
1795 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
1796 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
1797 * and 266MHz for model 3, or 4. Set Core Clock
1798 * Frequency to System Bus Frequency Ratio to 1 (bits
1799 * 31:24) even though these are only valid for CPU
1800 * models > 2, however guests may end up dividing or
1801 * multiplying by zero otherwise.
1802 */
1803 case MSR_EBC_FREQUENCY_ID:
1804 data = 1 << 24;
1805 break;
15c4a640
CO		 1806 case MSR_IA32_APICBASE:
1807 data = kvm_get_apic_base(vcpu);
1808 break;
0105d1a5
GN		 1809 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1810 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1811 break;
15c4a640 1812 case MSR_IA32_MISC_ENABLE:
ad312c7c 1813 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1814 break;
847f0ad8
AG		 1815 case MSR_IA32_PERF_STATUS:
1816 /* TSC increment by tick */
1817 data = 1000ULL;
1818 /* CPU multiplier */
1819 data |= (((uint64_t)4ULL) << 40);
1820 break;
15c4a640 1821 case MSR_EFER:
f6801dff 1822 data = vcpu->arch.efer;
15c4a640 1823 break;
18068523 1824 case MSR_KVM_WALL_CLOCK:
11c6bffa 1825 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1826 data = vcpu->kvm->arch.wall_clock;
1827 break;
1828 case MSR_KVM_SYSTEM_TIME:
11c6bffa 1829 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1830 data = vcpu->arch.time;
1831 break;
344d9588
GN		 1832 case MSR_KVM_ASYNC_PF_EN:
1833 data = vcpu->arch.apf.msr_val;
1834 break;
890ca9ae
HY		 1835 case MSR_IA32_P5_MC_ADDR:
1836 case MSR_IA32_P5_MC_TYPE:
1837 case MSR_IA32_MCG_CAP:
1838 case MSR_IA32_MCG_CTL:
1839 case MSR_IA32_MCG_STATUS:
1840 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1841 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 1842 case MSR_K7_CLK_CTL:
1843 /*
1844 * Provide expected ramp-up count for K7. All other
1845 * are set to zero, indicating minimum divisors for
1846 * every field.
1847 *
1848 * This prevents guest kernels on AMD host with CPU
1849 * type 6, model 8 and higher from exploding due to
1850 * the rdmsr failing.
1851 */
1852 data = 0x20000000;
1853 break;
55cd8e5a
GN		 1854 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1855 if (kvm_hv_msr_partition_wide(msr)) {
1856 int r;
1857 mutex_lock(&vcpu->kvm->lock);
1858 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1859 mutex_unlock(&vcpu->kvm->lock);
1860 return r;
1861 } else
1862 return get_msr_hyperv(vcpu, msr, pdata);
1863 break;
91c9c3ed 1864 case MSR_IA32_BBL_CR_CTL3:
1865 /* This legacy MSR exists but isn't fully documented in current
1866 * silicon. It is however accessed by winxp in very narrow
1867 * scenarios where it sets bit #19, itself documented as
1868 * a "reserved" bit. Best effort attempt to source coherent
1869 * read data here should the balance of the register be
1870 * interpreted by the guest:
1871 *
1872 * L2 cache control register 3: 64GB range, 256KB size,
1873 * enabled, latency 0x1, configured
1874 */
1875 data = 0xbe702111;
1876 break;
15c4a640 1877 default:
ed85c068
AP		 1878 if (!ignore_msrs) {
1879 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1880 return 1;
1881 } else {
1882 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1883 data = 0;
1884 }
1885 break;
15c4a640
CO		 1886 }
1887 *pdata = data;
1888 return 0;
1889}
1890EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1891
313a3dc7
CO		 1892/*
1893 * Read or write a bunch of msrs. All parameters are kernel addresses.
1894 *
1895 * @return number of msrs set successfully.
1896 */
1897static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1898 struct kvm_msr_entry *entries,
1899 int (*do_msr)(struct kvm_vcpu *vcpu,
1900 unsigned index, u64 *data))
1901{
f656ce01 1902 int i, idx;
313a3dc7 1903
f656ce01 1904 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 1905 for (i = 0; i < msrs->nmsrs; ++i)
1906 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1907 break;
f656ce01 1908 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 1909
313a3dc7
CO		 1910 return i;
1911}
1912
1913/*
1914 * Read or write a bunch of msrs. Parameters are user addresses.
1915 *
1916 * @return number of msrs set successfully.
1917 */
1918static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1919 int (*do_msr)(struct kvm_vcpu *vcpu,
1920 unsigned index, u64 *data),
1921 int writeback)
1922{
1923 struct kvm_msrs msrs;
1924 struct kvm_msr_entry *entries;
1925 int r, n;
1926 unsigned size;
1927
1928 r = -EFAULT;
1929 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1930 goto out;
1931
1932 r = -E2BIG;
1933 if (msrs.nmsrs >= MAX_IO_MSRS)
1934 goto out;
1935
1936 r = -ENOMEM;
1937 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
7a73c028 1938 entries = kmalloc(size, GFP_KERNEL);
313a3dc7
CO		 1939 if (!entries)
1940 goto out;
1941
1942 r = -EFAULT;
1943 if (copy_from_user(entries, user_msrs->entries, size))
1944 goto out_free;
1945
1946 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1947 if (r < 0)
1948 goto out_free;
1949
1950 r = -EFAULT;
1951 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1952 goto out_free;
1953
1954 r = n;
1955
1956out_free:
7a73c028 1957 kfree(entries);
313a3dc7
CO		 1958out:
1959 return r;
1960}
1961
018d00d2
ZX		 1962int kvm_dev_ioctl_check_extension(long ext)
1963{
1964 int r;
1965
1966 switch (ext) {
1967 case KVM_CAP_IRQCHIP:
1968 case KVM_CAP_HLT:
1969 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1970 case KVM_CAP_SET_TSS_ADDR:
07716717 1971 case KVM_CAP_EXT_CPUID:
c8076604 1972 case KVM_CAP_CLOCKSOURCE:
7837699f 1973 case KVM_CAP_PIT:
a28e4f5a 1974 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1975 case KVM_CAP_MP_STATE:
ed848624 1976 case KVM_CAP_SYNC_MMU:
a355c85c 1977 case KVM_CAP_USER_NMI:
52d939a0 1978 case KVM_CAP_REINJECT_CONTROL:
4925663a 1979 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1980 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1981 case KVM_CAP_IRQFD:
d34e6b17 1982 case KVM_CAP_IOEVENTFD:
c5ff41ce 1983 case KVM_CAP_PIT2:
e9f42757 1984 case KVM_CAP_PIT_STATE2:
b927a3ce 1985 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 1986 case KVM_CAP_XEN_HVM:
afbcf7ab 1987 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 1988 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 1989 case KVM_CAP_HYPERV:
10388a07 1990 case KVM_CAP_HYPERV_VAPIC:
c25bc163 1991 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 1992 case KVM_CAP_PCI_SEGMENT:
a1efbe77 1993 case KVM_CAP_DEBUGREGS:
d2be1651 1994 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 1995 case KVM_CAP_XSAVE:
344d9588 1996 case KVM_CAP_ASYNC_PF:
92a1f12d 1997 case KVM_CAP_GET_TSC_KHZ:
018d00d2
ZX		 1998 r = 1;
1999 break;
542472b5
LV		 2000 case KVM_CAP_COALESCED_MMIO:
2001 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2002 break;
774ead3a
AK		 2003 case KVM_CAP_VAPIC:
2004 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2005 break;
f725230a
AK		 2006 case KVM_CAP_NR_VCPUS:
2007 r = KVM_MAX_VCPUS;
2008 break;
a988b910
AK		 2009 case KVM_CAP_NR_MEMSLOTS:
2010 r = KVM_MEMORY_SLOTS;
2011 break;
a68a6a72
MT		 2012 case KVM_CAP_PV_MMU: /* obsolete */
2013 r = 0;
2f333bcb 2014 break;
62c476c7 2015 case KVM_CAP_IOMMU:
19de40a8 2016 r = iommu_found();
62c476c7 2017 break;
890ca9ae
HY		 2018 case KVM_CAP_MCE:
2019 r = KVM_MAX_MCE_BANKS;
2020 break;
2d5b5a66
SY		 2021 case KVM_CAP_XCRS:
2022 r = cpu_has_xsave;
2023 break;
92a1f12d
JR		 2024 case KVM_CAP_TSC_CONTROL:
2025 r = kvm_has_tsc_control;
2026 break;
018d00d2
ZX		 2027 default:
2028 r = 0;
2029 break;
2030 }
2031 return r;
2032
2033}
2034
043405e1
CO		 2035long kvm_arch_dev_ioctl(struct file *filp,
2036 unsigned int ioctl, unsigned long arg)
2037{
2038 void __user *argp = (void __user *)arg;
2039 long r;
2040
2041 switch (ioctl) {
2042 case KVM_GET_MSR_INDEX_LIST: {
2043 struct kvm_msr_list __user *user_msr_list = argp;
2044 struct kvm_msr_list msr_list;
2045 unsigned n;
2046
2047 r = -EFAULT;
2048 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2049 goto out;
2050 n = msr_list.nmsrs;
2051 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2052 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2053 goto out;
2054 r = -E2BIG;
e125e7b6 2055 if (n < msr_list.nmsrs)
043405e1
CO		 2056 goto out;
2057 r = -EFAULT;
2058 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2059 num_msrs_to_save * sizeof(u32)))
2060 goto out;
e125e7b6 2061 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2062 &emulated_msrs,
2063 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2064 goto out;
2065 r = 0;
2066 break;
2067 }
674eea0f
AK		 2068 case KVM_GET_SUPPORTED_CPUID: {
2069 struct kvm_cpuid2 __user *cpuid_arg = argp;
2070 struct kvm_cpuid2 cpuid;
2071
2072 r = -EFAULT;
2073 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2074 goto out;
2075 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 2076 cpuid_arg->entries);
674eea0f
AK		 2077 if (r)
2078 goto out;
2079
2080 r = -EFAULT;
2081 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2082 goto out;
2083 r = 0;
2084 break;
2085 }
890ca9ae
HY		 2086 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2087 u64 mce_cap;
2088
2089 mce_cap = KVM_MCE_CAP_SUPPORTED;
2090 r = -EFAULT;
2091 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2092 goto out;
2093 r = 0;
2094 break;
2095 }
043405e1
CO		 2096 default:
2097 r = -EINVAL;
2098 }
2099out:
2100 return r;
2101}
2102
f5f48ee1
SY		 2103static void wbinvd_ipi(void *garbage)
2104{
2105 wbinvd();
2106}
2107
2108static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2109{
2110 return vcpu->kvm->arch.iommu_domain &&
2111 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2112}
2113
313a3dc7
CO		 2114void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2115{
f5f48ee1
SY		 2116 /* Address WBINVD may be executed by guest */
2117 if (need_emulate_wbinvd(vcpu)) {
2118 if (kvm_x86_ops->has_wbinvd_exit())
2119 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2120 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2121 smp_call_function_single(vcpu->cpu,
2122 wbinvd_ipi, NULL, 1);
2123 }
2124
313a3dc7 2125 kvm_x86_ops->vcpu_load(vcpu, cpu);
48434c20 2126 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
e48672fa 2127 /* Make sure TSC doesn't go backwards */
8f6055cb
JR		 2128 s64 tsc_delta;
2129 u64 tsc;
2130
2131 kvm_get_msr(vcpu, MSR_IA32_TSC, &tsc);
2132 tsc_delta = !vcpu->arch.last_guest_tsc ? 0 :
2133 tsc - vcpu->arch.last_guest_tsc;
2134
e48672fa
ZA		 2135 if (tsc_delta < 0)
2136 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2137 if (check_tsc_unstable()) {
e48672fa 2138 kvm_x86_ops->adjust_tsc_offset(vcpu, -tsc_delta);
c285545f 2139 vcpu->arch.tsc_catchup = 1;
c285545f 2140 }
1aa8ceef 2141 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2142 if (vcpu->cpu != cpu)
2143 kvm_migrate_timers(vcpu);
e48672fa 2144 vcpu->cpu = cpu;
6b7d7e76 2145 }
313a3dc7
CO		 2146}
2147
2148void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2149{
02daab21 2150 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2151 kvm_put_guest_fpu(vcpu);
7c4c0f4f 2152 kvm_get_msr(vcpu, MSR_IA32_TSC, &vcpu->arch.last_guest_tsc);
313a3dc7
CO		 2153}
2154
07716717 2155static int is_efer_nx(void)
313a3dc7 2156{
e286e86e 2157 unsigned long long efer = 0;
313a3dc7 2158
e286e86e 2159 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 2160 return efer & EFER_NX;
2161}
2162
2163static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
2164{
2165 int i;
2166 struct kvm_cpuid_entry2 *e, *entry;
2167
313a3dc7 2168 entry = NULL;
ad312c7c
ZX		 2169 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
2170 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 2171 if (e->function == 0x80000001) {
2172 entry = e;
2173 break;
2174 }
2175 }
07716717 2176 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 2177 entry->edx &= ~(1 << 20);
2178 printk(KERN_INFO "kvm: guest NX capability removed\n");
2179 }
2180}
2181
07716717 2182/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 2183static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
2184 struct kvm_cpuid *cpuid,
2185 struct kvm_cpuid_entry __user *entries)
07716717
DK		 2186{
2187 int r, i;
2188 struct kvm_cpuid_entry *cpuid_entries;
2189
2190 r = -E2BIG;
2191 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2192 goto out;
2193 r = -ENOMEM;
2194 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
2195 if (!cpuid_entries)
2196 goto out;
2197 r = -EFAULT;
2198 if (copy_from_user(cpuid_entries, entries,
2199 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
2200 goto out_free;
2201 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 2202 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
2203 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
2204 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
2205 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
2206 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
2207 vcpu->arch.cpuid_entries[i].index = 0;
2208 vcpu->arch.cpuid_entries[i].flags = 0;
2209 vcpu->arch.cpuid_entries[i].padding[0] = 0;
2210 vcpu->arch.cpuid_entries[i].padding[1] = 0;
2211 vcpu->arch.cpuid_entries[i].padding[2] = 0;
2212 }
2213 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 2214 cpuid_fix_nx_cap(vcpu);
2215 r = 0;
fc61b800 2216 kvm_apic_set_version(vcpu);
0e851880 2217 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 2218 update_cpuid(vcpu);
07716717
DK		 2219
2220out_free:
2221 vfree(cpuid_entries);
2222out:
2223 return r;
2224}
2225
2226static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 2227 struct kvm_cpuid2 *cpuid,
2228 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 2229{
2230 int r;
2231
2232 r = -E2BIG;
2233 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2234 goto out;
2235 r = -EFAULT;
ad312c7c 2236 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 2237 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 2238 goto out;
ad312c7c 2239 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 2240 kvm_apic_set_version(vcpu);
0e851880 2241 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 2242 update_cpuid(vcpu);
313a3dc7
CO		 2243 return 0;
2244
2245out:
2246 return r;
2247}
2248
07716717 2249static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 2250 struct kvm_cpuid2 *cpuid,
2251 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2252{
2253 int r;
2254
2255 r = -E2BIG;
ad312c7c 2256 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 2257 goto out;
2258 r = -EFAULT;
ad312c7c 2259 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 2260 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2261 goto out;
2262 return 0;
2263
2264out:
ad312c7c 2265 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 2266 return r;
2267}
2268
945ee35e
AK		 2269static void cpuid_mask(u32 *word, int wordnum)
2270{
2271 *word &= boot_cpu_data.x86_capability[wordnum];
2272}
2273
07716717 2274static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 2275 u32 index)
07716717
DK		 2276{
2277 entry->function = function;
2278 entry->index = index;
2279 cpuid_count(entry->function, entry->index,
19355475 2280 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 2281 entry->flags = 0;
2282}
2283
7faa4ee1
AK		 2284#define F(x) bit(X86_FEATURE_##x)
2285
07716717
DK		 2286static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
2287 u32 index, int *nent, int maxnent)
2288{
7faa4ee1 2289 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 2290#ifdef CONFIG_X86_64
17cc3935
SY		 2291 unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
2292 ? F(GBPAGES) : 0;
7faa4ee1
AK		 2293 unsigned f_lm = F(LM);
2294#else
17cc3935 2295 unsigned f_gbpages = 0;
7faa4ee1 2296 unsigned f_lm = 0;
07716717 2297#endif
4e47c7a6 2298 unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
7faa4ee1
AK		 2299
2300 /* cpuid 1.edx */
2301 const u32 kvm_supported_word0_x86_features =
2302 F(FPU) | F(VME) | F(DE) | F(PSE) |
2303 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2304 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
2305 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2306 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
2307 0 /* Reserved, DS, ACPI */ | F(MMX) |
2308 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
2309 0 /* HTT, TM, Reserved, PBE */;
2310 /* cpuid 0x80000001.edx */
2311 const u32 kvm_supported_word1_x86_features =
2312 F(FPU) | F(VME) | F(DE) | F(PSE) |
2313 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2314 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
2315 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2316 F(PAT) | F(PSE36) | 0 /* Reserved */ |
2317 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
4e47c7a6 2318 F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
7faa4ee1
AK		 2319 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
2320 /* cpuid 1.ecx */
2321 const u32 kvm_supported_word4_x86_features =
6c3f6041 2322 F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ |
d149c731
AK		 2323 0 /* DS-CPL, VMX, SMX, EST */ |
2324 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
2325 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
2326 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 2327 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
6d886fd0
AP		 2328 0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) |
2329 F(F16C);
7faa4ee1 2330 /* cpuid 0x80000001.ecx */
07716717 2331 const u32 kvm_supported_word6_x86_features =
4c62a2dc 2332 F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ |
7faa4ee1 2333 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
7ef8aa72 2334 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(XOP) |
6d886fd0 2335 0 /* SKINIT, WDT, LWP */ | F(FMA4) | F(TBM);
07716717 2336
19355475 2337 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 2338 get_cpu();
2339 do_cpuid_1_ent(entry, function, index);
2340 ++*nent;
2341
2342 switch (function) {
2343 case 0:
2acf923e 2344 entry->eax = min(entry->eax, (u32)0xd);
07716717
DK		 2345 break;
2346 case 1:
2347 entry->edx &= kvm_supported_word0_x86_features;
945ee35e 2348 cpuid_mask(&entry->edx, 0);
7faa4ee1 2349 entry->ecx &= kvm_supported_word4_x86_features;
945ee35e 2350 cpuid_mask(&entry->ecx, 4);
0d1de2d9
GN		 2351 /* we support x2apic emulation even if host does not support
2352 * it since we emulate x2apic in software */
2353 entry->ecx |= F(X2APIC);
07716717
DK		 2354 break;
2355 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
2356 * may return different values. This forces us to get_cpu() before
2357 * issuing the first command, and also to emulate this annoying behavior
2358 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
2359 case 2: {
2360 int t, times = entry->eax & 0xff;
2361
2362 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 2363 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 2364 for (t = 1; t < times && *nent < maxnent; ++t) {
2365 do_cpuid_1_ent(&entry[t], function, 0);
2366 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
2367 ++*nent;
2368 }
2369 break;
2370 }
2371 /* function 4 and 0xb have additional index. */
2372 case 4: {
14af3f3c 2373 int i, cache_type;
07716717
DK		 2374
2375 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2376 /* read more entries until cache_type is zero */
14af3f3c
HH		 2377 for (i = 1; *nent < maxnent; ++i) {
2378 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 2379 if (!cache_type)
2380 break;
14af3f3c
HH		 2381 do_cpuid_1_ent(&entry[i], function, i);
2382 entry[i].flags |=
07716717
DK		 2383 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2384 ++*nent;
2385 }
2386 break;
2387 }
2388 case 0xb: {
14af3f3c 2389 int i, level_type;
07716717
DK		 2390
2391 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2392 /* read more entries until level_type is zero */
14af3f3c 2393 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 2394 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 2395 if (!level_type)
2396 break;
14af3f3c
HH		 2397 do_cpuid_1_ent(&entry[i], function, i);
2398 entry[i].flags |=
07716717
DK		 2399 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2400 ++*nent;
2401 }
2402 break;
2403 }
2acf923e
DC		 2404 case 0xd: {
2405 int i;
2406
2407 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
20800bc9
AP		 2408 for (i = 1; *nent < maxnent && i < 64; ++i) {
2409 if (entry[i].eax == 0)
2410 continue;
2acf923e
DC		 2411 do_cpuid_1_ent(&entry[i], function, i);
2412 entry[i].flags |=
2413 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2414 ++*nent;
2415 }
2416 break;
2417 }
84478c82
GC		 2418 case KVM_CPUID_SIGNATURE: {
2419 char signature[12] = "KVMKVMKVM\0\0";
2420 u32 *sigptr = (u32 *)signature;
2421 entry->eax = 0;
2422 entry->ebx = sigptr[0];
2423 entry->ecx = sigptr[1];
2424 entry->edx = sigptr[2];
2425 break;
2426 }
2427 case KVM_CPUID_FEATURES:
2428 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) |
2429 (1 << KVM_FEATURE_NOP_IO_DELAY) |
371bcf64 2430 (1 << KVM_FEATURE_CLOCKSOURCE2) |
32918924 2431 (1 << KVM_FEATURE_ASYNC_PF) |
371bcf64 2432 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
84478c82
GC		 2433 entry->ebx = 0;
2434 entry->ecx = 0;
2435 entry->edx = 0;
2436 break;
07716717
DK		 2437 case 0x80000000:
2438 entry->eax = min(entry->eax, 0x8000001a);
2439 break;
2440 case 0x80000001:
2441 entry->edx &= kvm_supported_word1_x86_features;
945ee35e 2442 cpuid_mask(&entry->edx, 1);
07716717 2443 entry->ecx &= kvm_supported_word6_x86_features;
945ee35e 2444 cpuid_mask(&entry->ecx, 6);
07716717
DK		 2445 break;
2446 }
d4330ef2
JR		 2447
2448 kvm_x86_ops->set_supported_cpuid(function, entry);
2449
07716717
DK		 2450 put_cpu();
2451}
2452
7faa4ee1
AK		 2453#undef F
2454
674eea0f 2455static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 2456 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2457{
2458 struct kvm_cpuid_entry2 *cpuid_entries;
2459 int limit, nent = 0, r = -E2BIG;
2460 u32 func;
2461
2462 if (cpuid->nent < 1)
2463 goto out;
6a544355
AK		 2464 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2465 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
07716717
DK		 2466 r = -ENOMEM;
2467 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
2468 if (!cpuid_entries)
2469 goto out;
2470
2471 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
2472 limit = cpuid_entries[0].eax;
2473 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
2474 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2475 &nent, cpuid->nent);
07716717
DK		 2476 r = -E2BIG;
2477 if (nent >= cpuid->nent)
2478 goto out_free;
2479
2480 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
2481 limit = cpuid_entries[nent - 1].eax;
2482 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
2483 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2484 &nent, cpuid->nent);
84478c82
GC		 2485
2486
2487
2488 r = -E2BIG;
2489 if (nent >= cpuid->nent)
2490 goto out_free;
2491
2492 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_SIGNATURE, 0, &nent,
2493 cpuid->nent);
2494
2495 r = -E2BIG;
2496 if (nent >= cpuid->nent)
2497 goto out_free;
2498
2499 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_FEATURES, 0, &nent,
2500 cpuid->nent);
2501
cb007648
MM		 2502 r = -E2BIG;
2503 if (nent >= cpuid->nent)
2504 goto out_free;
2505
07716717
DK		 2506 r = -EFAULT;
2507 if (copy_to_user(entries, cpuid_entries,
19355475 2508 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2509 goto out_free;
2510 cpuid->nent = nent;
2511 r = 0;
2512
2513out_free:
2514 vfree(cpuid_entries);
2515out:
2516 return r;
2517}
2518
313a3dc7
CO		 2519static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2520 struct kvm_lapic_state *s)
2521{
ad312c7c 2522 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2523
2524 return 0;
2525}
2526
2527static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2528 struct kvm_lapic_state *s)
2529{
ad312c7c 2530 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 2531 kvm_apic_post_state_restore(vcpu);
cb142eb7 2532 update_cr8_intercept(vcpu);
313a3dc7
CO		 2533
2534 return 0;
2535}
2536
f77bc6a4
ZX		 2537static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2538 struct kvm_interrupt *irq)
2539{
2540 if (irq->irq < 0 || irq->irq >= 256)
2541 return -EINVAL;
2542 if (irqchip_in_kernel(vcpu->kvm))
2543 return -ENXIO;
f77bc6a4 2544
66fd3f7f 2545 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2546 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2547
f77bc6a4
ZX		 2548 return 0;
2549}
2550
c4abb7c9
JK		 2551static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2552{
c4abb7c9 2553 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2554
2555 return 0;
2556}
2557
b209749f
AK		 2558static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2559 struct kvm_tpr_access_ctl *tac)
2560{
2561 if (tac->flags)
2562 return -EINVAL;
2563 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2564 return 0;
2565}
2566
890ca9ae
HY		 2567static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2568 u64 mcg_cap)
2569{
2570 int r;
2571 unsigned bank_num = mcg_cap & 0xff, bank;
2572
2573 r = -EINVAL;
a9e38c3e 2574 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2575 goto out;
2576 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2577 goto out;
2578 r = 0;
2579 vcpu->arch.mcg_cap = mcg_cap;
2580 /* Init IA32_MCG_CTL to all 1s */
2581 if (mcg_cap & MCG_CTL_P)
2582 vcpu->arch.mcg_ctl = ~(u64)0;
2583 /* Init IA32_MCi_CTL to all 1s */
2584 for (bank = 0; bank < bank_num; bank++)
2585 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2586out:
2587 return r;
2588}
2589
2590static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2591 struct kvm_x86_mce *mce)
2592{
2593 u64 mcg_cap = vcpu->arch.mcg_cap;
2594 unsigned bank_num = mcg_cap & 0xff;
2595 u64 *banks = vcpu->arch.mce_banks;
2596
2597 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2598 return -EINVAL;
2599 /*
2600 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2601 * reporting is disabled
2602 */
2603 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2604 vcpu->arch.mcg_ctl != ~(u64)0)
2605 return 0;
2606 banks += 4 * mce->bank;
2607 /*
2608 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2609 * reporting is disabled for the bank
2610 */
2611 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2612 return 0;
2613 if (mce->status & MCI_STATUS_UC) {
2614 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2615 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2616 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2617 return 0;
2618 }
2619 if (banks[1] & MCI_STATUS_VAL)
2620 mce->status |= MCI_STATUS_OVER;
2621 banks[2] = mce->addr;
2622 banks[3] = mce->misc;
2623 vcpu->arch.mcg_status = mce->mcg_status;
2624 banks[1] = mce->status;
2625 kvm_queue_exception(vcpu, MC_VECTOR);
2626 } else if (!(banks[1] & MCI_STATUS_VAL)
2627 || !(banks[1] & MCI_STATUS_UC)) {
2628 if (banks[1] & MCI_STATUS_VAL)
2629 mce->status |= MCI_STATUS_OVER;
2630 banks[2] = mce->addr;
2631 banks[3] = mce->misc;
2632 banks[1] = mce->status;
2633 } else
2634 banks[1] |= MCI_STATUS_OVER;
2635 return 0;
2636}
2637
3cfc3092
JK		 2638static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2639 struct kvm_vcpu_events *events)
2640{
03b82a30
JK		 2641 events->exception.injected =
2642 vcpu->arch.exception.pending &&
2643 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2644 events->exception.nr = vcpu->arch.exception.nr;
2645 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2646 events->exception.pad = 0;
3cfc3092
JK		 2647 events->exception.error_code = vcpu->arch.exception.error_code;
2648
03b82a30
JK		 2649 events->interrupt.injected =
2650 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2651 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2652 events->interrupt.soft = 0;
48005f64
JK		 2653 events->interrupt.shadow =
2654 kvm_x86_ops->get_interrupt_shadow(vcpu,
2655 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2656
2657 events->nmi.injected = vcpu->arch.nmi_injected;
2658 events->nmi.pending = vcpu->arch.nmi_pending;
2659 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2660 events->nmi.pad = 0;
3cfc3092
JK		 2661
2662 events->sipi_vector = vcpu->arch.sipi_vector;
2663
dab4b911 2664 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2665 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2666 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 2667 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2668}
2669
2670static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2671 struct kvm_vcpu_events *events)
2672{
dab4b911 2673 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2674 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2675 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2676 return -EINVAL;
2677
3cfc3092
JK		 2678 vcpu->arch.exception.pending = events->exception.injected;
2679 vcpu->arch.exception.nr = events->exception.nr;
2680 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2681 vcpu->arch.exception.error_code = events->exception.error_code;
2682
2683 vcpu->arch.interrupt.pending = events->interrupt.injected;
2684 vcpu->arch.interrupt.nr = events->interrupt.nr;
2685 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2686 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2687 kvm_x86_ops->set_interrupt_shadow(vcpu,
2688 events->interrupt.shadow);
3cfc3092
JK		 2689
2690 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2691 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2692 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2693 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2694
dab4b911
JK		 2695 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2696 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092 2697
3842d135
AK		 2698 kvm_make_request(KVM_REQ_EVENT, vcpu);
2699
3cfc3092
JK		 2700 return 0;
2701}
2702
a1efbe77
JK		 2703static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2704 struct kvm_debugregs *dbgregs)
2705{
a1efbe77
JK		 2706 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2707 dbgregs->dr6 = vcpu->arch.dr6;
2708 dbgregs->dr7 = vcpu->arch.dr7;
2709 dbgregs->flags = 0;
97e69aa6 2710 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 2711}
2712
2713static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2714 struct kvm_debugregs *dbgregs)
2715{
2716 if (dbgregs->flags)
2717 return -EINVAL;
2718
a1efbe77
JK		 2719 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2720 vcpu->arch.dr6 = dbgregs->dr6;
2721 vcpu->arch.dr7 = dbgregs->dr7;
2722
a1efbe77
JK		 2723 return 0;
2724}
2725
2d5b5a66
SY		 2726static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2727 struct kvm_xsave *guest_xsave)
2728{
2729 if (cpu_has_xsave)
2730 memcpy(guest_xsave->region,
2731 &vcpu->arch.guest_fpu.state->xsave,
f45755b8 2732 xstate_size);
2d5b5a66
SY		 2733 else {
2734 memcpy(guest_xsave->region,
2735 &vcpu->arch.guest_fpu.state->fxsave,
2736 sizeof(struct i387_fxsave_struct));
2737 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2738 XSTATE_FPSSE;
2739 }
2740}
2741
2742static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2743 struct kvm_xsave *guest_xsave)
2744{
2745 u64 xstate_bv =
2746 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2747
2748 if (cpu_has_xsave)
2749 memcpy(&vcpu->arch.guest_fpu.state->xsave,
f45755b8 2750 guest_xsave->region, xstate_size);
2d5b5a66
SY		 2751 else {
2752 if (xstate_bv & ~XSTATE_FPSSE)
2753 return -EINVAL;
2754 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2755 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2756 }
2757 return 0;
2758}
2759
2760static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2761 struct kvm_xcrs *guest_xcrs)
2762{
2763 if (!cpu_has_xsave) {
2764 guest_xcrs->nr_xcrs = 0;
2765 return;
2766 }
2767
2768 guest_xcrs->nr_xcrs = 1;
2769 guest_xcrs->flags = 0;
2770 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2771 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2772}
2773
2774static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2775 struct kvm_xcrs *guest_xcrs)
2776{
2777 int i, r = 0;
2778
2779 if (!cpu_has_xsave)
2780 return -EINVAL;
2781
2782 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2783 return -EINVAL;
2784
2785 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2786 /* Only support XCR0 currently */
2787 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2788 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2789 guest_xcrs->xcrs[0].value);
2790 break;
2791 }
2792 if (r)
2793 r = -EINVAL;
2794 return r;
2795}
2796
313a3dc7
CO		 2797long kvm_arch_vcpu_ioctl(struct file *filp,
2798 unsigned int ioctl, unsigned long arg)
2799{
2800 struct kvm_vcpu *vcpu = filp->private_data;
2801 void __user *argp = (void __user *)arg;
2802 int r;
d1ac91d8
AK		 2803 union {
2804 struct kvm_lapic_state *lapic;
2805 struct kvm_xsave *xsave;
2806 struct kvm_xcrs *xcrs;
2807 void *buffer;
2808 } u;
2809
2810 u.buffer = NULL;
313a3dc7
CO		 2811 switch (ioctl) {
2812 case KVM_GET_LAPIC: {
2204ae3c
MT		 2813 r = -EINVAL;
2814 if (!vcpu->arch.apic)
2815 goto out;
d1ac91d8 2816 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2817
b772ff36 2818 r = -ENOMEM;
d1ac91d8 2819 if (!u.lapic)
b772ff36 2820 goto out;
d1ac91d8 2821 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 2822 if (r)
2823 goto out;
2824 r = -EFAULT;
d1ac91d8 2825 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2826 goto out;
2827 r = 0;
2828 break;
2829 }
2830 case KVM_SET_LAPIC: {
2204ae3c
MT		 2831 r = -EINVAL;
2832 if (!vcpu->arch.apic)
2833 goto out;
d1ac91d8 2834 u.lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
b772ff36 2835 r = -ENOMEM;
d1ac91d8 2836 if (!u.lapic)
b772ff36 2837 goto out;
313a3dc7 2838 r = -EFAULT;
d1ac91d8 2839 if (copy_from_user(u.lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 2840 goto out;
d1ac91d8 2841 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 2842 if (r)
2843 goto out;
2844 r = 0;
2845 break;
2846 }
f77bc6a4
ZX		 2847 case KVM_INTERRUPT: {
2848 struct kvm_interrupt irq;
2849
2850 r = -EFAULT;
2851 if (copy_from_user(&irq, argp, sizeof irq))
2852 goto out;
2853 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2854 if (r)
2855 goto out;
2856 r = 0;
2857 break;
2858 }
c4abb7c9
JK		 2859 case KVM_NMI: {
2860 r = kvm_vcpu_ioctl_nmi(vcpu);
2861 if (r)
2862 goto out;
2863 r = 0;
2864 break;
2865 }
313a3dc7
CO		 2866 case KVM_SET_CPUID: {
2867 struct kvm_cpuid __user *cpuid_arg = argp;
2868 struct kvm_cpuid cpuid;
2869
2870 r = -EFAULT;
2871 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2872 goto out;
2873 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2874 if (r)
2875 goto out;
2876 break;
2877 }
07716717
DK		 2878 case KVM_SET_CPUID2: {
2879 struct kvm_cpuid2 __user *cpuid_arg = argp;
2880 struct kvm_cpuid2 cpuid;
2881
2882 r = -EFAULT;
2883 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2884 goto out;
2885 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2886 cpuid_arg->entries);
07716717
DK		 2887 if (r)
2888 goto out;
2889 break;
2890 }
2891 case KVM_GET_CPUID2: {
2892 struct kvm_cpuid2 __user *cpuid_arg = argp;
2893 struct kvm_cpuid2 cpuid;
2894
2895 r = -EFAULT;
2896 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2897 goto out;
2898 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2899 cpuid_arg->entries);
07716717
DK		 2900 if (r)
2901 goto out;
2902 r = -EFAULT;
2903 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2904 goto out;
2905 r = 0;
2906 break;
2907 }
313a3dc7
CO		 2908 case KVM_GET_MSRS:
2909 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2910 break;
2911 case KVM_SET_MSRS:
2912 r = msr_io(vcpu, argp, do_set_msr, 0);
2913 break;
b209749f
AK		 2914 case KVM_TPR_ACCESS_REPORTING: {
2915 struct kvm_tpr_access_ctl tac;
2916
2917 r = -EFAULT;
2918 if (copy_from_user(&tac, argp, sizeof tac))
2919 goto out;
2920 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2921 if (r)
2922 goto out;
2923 r = -EFAULT;
2924 if (copy_to_user(argp, &tac, sizeof tac))
2925 goto out;
2926 r = 0;
2927 break;
2928 };
b93463aa
AK		 2929 case KVM_SET_VAPIC_ADDR: {
2930 struct kvm_vapic_addr va;
2931
2932 r = -EINVAL;
2933 if (!irqchip_in_kernel(vcpu->kvm))
2934 goto out;
2935 r = -EFAULT;
2936 if (copy_from_user(&va, argp, sizeof va))
2937 goto out;
2938 r = 0;
2939 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2940 break;
2941 }
890ca9ae
HY		 2942 case KVM_X86_SETUP_MCE: {
2943 u64 mcg_cap;
2944
2945 r = -EFAULT;
2946 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2947 goto out;
2948 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2949 break;
2950 }
2951 case KVM_X86_SET_MCE: {
2952 struct kvm_x86_mce mce;
2953
2954 r = -EFAULT;
2955 if (copy_from_user(&mce, argp, sizeof mce))
2956 goto out;
2957 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
2958 break;
2959 }
3cfc3092
JK		 2960 case KVM_GET_VCPU_EVENTS: {
2961 struct kvm_vcpu_events events;
2962
2963 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
2964
2965 r = -EFAULT;
2966 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
2967 break;
2968 r = 0;
2969 break;
2970 }
2971 case KVM_SET_VCPU_EVENTS: {
2972 struct kvm_vcpu_events events;
2973
2974 r = -EFAULT;
2975 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
2976 break;
2977
2978 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
2979 break;
2980 }
a1efbe77
JK		 2981 case KVM_GET_DEBUGREGS: {
2982 struct kvm_debugregs dbgregs;
2983
2984 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
2985
2986 r = -EFAULT;
2987 if (copy_to_user(argp, &dbgregs,
2988 sizeof(struct kvm_debugregs)))
2989 break;
2990 r = 0;
2991 break;
2992 }
2993 case KVM_SET_DEBUGREGS: {
2994 struct kvm_debugregs dbgregs;
2995
2996 r = -EFAULT;
2997 if (copy_from_user(&dbgregs, argp,
2998 sizeof(struct kvm_debugregs)))
2999 break;
3000
3001 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3002 break;
3003 }
2d5b5a66 3004 case KVM_GET_XSAVE: {
d1ac91d8 3005 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3006 r = -ENOMEM;
d1ac91d8 3007 if (!u.xsave)
2d5b5a66
SY		 3008 break;
3009
d1ac91d8 3010 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3011
3012 r = -EFAULT;
d1ac91d8 3013 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3014 break;
3015 r = 0;
3016 break;
3017 }
3018 case KVM_SET_XSAVE: {
d1ac91d8 3019 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3020 r = -ENOMEM;
d1ac91d8 3021 if (!u.xsave)
2d5b5a66
SY		 3022 break;
3023
3024 r = -EFAULT;
d1ac91d8 3025 if (copy_from_user(u.xsave, argp, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3026 break;
3027
d1ac91d8 3028 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3029 break;
3030 }
3031 case KVM_GET_XCRS: {
d1ac91d8 3032 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3033 r = -ENOMEM;
d1ac91d8 3034 if (!u.xcrs)
2d5b5a66
SY		 3035 break;
3036
d1ac91d8 3037 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3038
3039 r = -EFAULT;
d1ac91d8 3040 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3041 sizeof(struct kvm_xcrs)))
3042 break;
3043 r = 0;
3044 break;
3045 }
3046 case KVM_SET_XCRS: {
d1ac91d8 3047 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3048 r = -ENOMEM;
d1ac91d8 3049 if (!u.xcrs)
2d5b5a66
SY		 3050 break;
3051
3052 r = -EFAULT;
d1ac91d8 3053 if (copy_from_user(u.xcrs, argp,
2d5b5a66
SY		 3054 sizeof(struct kvm_xcrs)))
3055 break;
3056
d1ac91d8 3057 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3058 break;
3059 }
92a1f12d
JR		 3060 case KVM_SET_TSC_KHZ: {
3061 u32 user_tsc_khz;
3062
3063 r = -EINVAL;
3064 if (!kvm_has_tsc_control)
3065 break;
3066
3067 user_tsc_khz = (u32)arg;
3068
3069 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3070 goto out;
3071
3072 kvm_x86_ops->set_tsc_khz(vcpu, user_tsc_khz);
3073
3074 r = 0;
3075 goto out;
3076 }
3077 case KVM_GET_TSC_KHZ: {
3078 r = -EIO;
3079 if (check_tsc_unstable())
3080 goto out;
3081
3082 r = vcpu_tsc_khz(vcpu);
3083
3084 goto out;
3085 }
313a3dc7
CO		 3086 default:
3087 r = -EINVAL;
3088 }
3089out:
d1ac91d8 3090 kfree(u.buffer);
313a3dc7
CO		 3091 return r;
3092}
3093
1fe779f8
CO		 3094static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3095{
3096 int ret;
3097
3098 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3099 return -1;
3100 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3101 return ret;
3102}
3103
b927a3ce
SY		 3104static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3105 u64 ident_addr)
3106{
3107 kvm->arch.ept_identity_map_addr = ident_addr;
3108 return 0;
3109}
3110
1fe779f8
CO		 3111static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3112 u32 kvm_nr_mmu_pages)
3113{
3114 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3115 return -EINVAL;
3116
79fac95e 3117 mutex_lock(&kvm->slots_lock);
7c8a83b7 3118 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 3119
3120 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3121 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3122
7c8a83b7 3123 spin_unlock(&kvm->mmu_lock);
79fac95e 3124 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3125 return 0;
3126}
3127
3128static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3129{
39de71ec 3130 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3131}
3132
1fe779f8
CO		 3133static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3134{
3135 int r;
3136
3137 r = 0;
3138 switch (chip->chip_id) {
3139 case KVM_IRQCHIP_PIC_MASTER:
3140 memcpy(&chip->chip.pic,
3141 &pic_irqchip(kvm)->pics[0],
3142 sizeof(struct kvm_pic_state));
3143 break;
3144 case KVM_IRQCHIP_PIC_SLAVE:
3145 memcpy(&chip->chip.pic,
3146 &pic_irqchip(kvm)->pics[1],
3147 sizeof(struct kvm_pic_state));
3148 break;
3149 case KVM_IRQCHIP_IOAPIC:
eba0226b 3150 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3151 break;
3152 default:
3153 r = -EINVAL;
3154 break;
3155 }
3156 return r;
3157}
3158
3159static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3160{
3161 int r;
3162
3163 r = 0;
3164 switch (chip->chip_id) {
3165 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3166 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3167 memcpy(&pic_irqchip(kvm)->pics[0],
3168 &chip->chip.pic,
3169 sizeof(struct kvm_pic_state));
f4f51050 3170 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3171 break;
3172 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3173 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3174 memcpy(&pic_irqchip(kvm)->pics[1],
3175 &chip->chip.pic,
3176 sizeof(struct kvm_pic_state));
f4f51050 3177 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3178 break;
3179 case KVM_IRQCHIP_IOAPIC:
eba0226b 3180 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3181 break;
3182 default:
3183 r = -EINVAL;
3184 break;
3185 }
3186 kvm_pic_update_irq(pic_irqchip(kvm));
3187 return r;
3188}
3189
e0f63cb9
SY		 3190static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3191{
3192 int r = 0;
3193
894a9c55 3194 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3195 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3196 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3197 return r;
3198}
3199
3200static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3201{
3202 int r = 0;
3203
894a9c55 3204 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3205 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3206 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3207 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3208 return r;
3209}
3210
3211static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3212{
3213 int r = 0;
3214
3215 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3216 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3217 sizeof(ps->channels));
3218 ps->flags = kvm->arch.vpit->pit_state.flags;
3219 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3220 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3221 return r;
3222}
3223
3224static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3225{
3226 int r = 0, start = 0;
3227 u32 prev_legacy, cur_legacy;
3228 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3229 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3230 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3231 if (!prev_legacy && cur_legacy)
3232 start = 1;
3233 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3234 sizeof(kvm->arch.vpit->pit_state.channels));
3235 kvm->arch.vpit->pit_state.flags = ps->flags;
3236 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3237 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3238 return r;
3239}
3240
52d939a0
MT		 3241static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3242 struct kvm_reinject_control *control)
3243{
3244 if (!kvm->arch.vpit)
3245 return -ENXIO;
894a9c55 3246 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 3247 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 3248 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3249 return 0;
3250}
3251
5bb064dc
ZX		 3252/*
3253 * Get (and clear) the dirty memory log for a memory slot.
3254 */
3255int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
3256 struct kvm_dirty_log *log)
3257{
87bf6e7d 3258 int r, i;
5bb064dc 3259 struct kvm_memory_slot *memslot;
87bf6e7d 3260 unsigned long n;
b050b015 3261 unsigned long is_dirty = 0;
5bb064dc 3262
79fac95e 3263 mutex_lock(&kvm->slots_lock);
5bb064dc 3264
b050b015
MT		 3265 r = -EINVAL;
3266 if (log->slot >= KVM_MEMORY_SLOTS)
3267 goto out;
3268
3269 memslot = &kvm->memslots->memslots[log->slot];
3270 r = -ENOENT;
3271 if (!memslot->dirty_bitmap)
3272 goto out;
3273
87bf6e7d 3274 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3275
b050b015
MT		 3276 for (i = 0; !is_dirty && i < n/sizeof(long); i++)
3277 is_dirty = memslot->dirty_bitmap[i];
5bb064dc
ZX		 3278
3279 /* If nothing is dirty, don't bother messing with page tables. */
3280 if (is_dirty) {
b050b015 3281 struct kvm_memslots *slots, *old_slots;
914ebccd 3282 unsigned long *dirty_bitmap;
b050b015 3283
515a0127
TY		 3284 dirty_bitmap = memslot->dirty_bitmap_head;
3285 if (memslot->dirty_bitmap == dirty_bitmap)
3286 dirty_bitmap += n / sizeof(long);
914ebccd 3287 memset(dirty_bitmap, 0, n);
b050b015 3288
914ebccd
TY		 3289 r = -ENOMEM;
3290 slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
515a0127 3291 if (!slots)
914ebccd 3292 goto out;
b050b015
MT		 3293 memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
3294 slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
49c7754c 3295 slots->generation++;
b050b015
MT		 3296
3297 old_slots = kvm->memslots;
3298 rcu_assign_pointer(kvm->memslots, slots);
3299 synchronize_srcu_expedited(&kvm->srcu);
3300 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
3301 kfree(old_slots);
914ebccd 3302
edde99ce
MT		 3303 spin_lock(&kvm->mmu_lock);
3304 kvm_mmu_slot_remove_write_access(kvm, log->slot);
3305 spin_unlock(&kvm->mmu_lock);
3306
914ebccd 3307 r = -EFAULT;
515a0127 3308 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n))
914ebccd 3309 goto out;
914ebccd
TY		 3310 } else {
3311 r = -EFAULT;
3312 if (clear_user(log->dirty_bitmap, n))
3313 goto out;
5bb064dc 3314 }
b050b015 3315
5bb064dc
ZX		 3316 r = 0;
3317out:
79fac95e 3318 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3319 return r;
3320}
3321
1fe779f8
CO		 3322long kvm_arch_vm_ioctl(struct file *filp,
3323 unsigned int ioctl, unsigned long arg)
3324{
3325 struct kvm *kvm = filp->private_data;
3326 void __user *argp = (void __user *)arg;
367e1319 3327 int r = -ENOTTY;
f0d66275
DH		 3328 /*
3329 * This union makes it completely explicit to gcc-3.x
3330 * that these two variables' stack usage should be
3331 * combined, not added together.
3332 */
3333 union {
3334 struct kvm_pit_state ps;
e9f42757 3335 struct kvm_pit_state2 ps2;
c5ff41ce 3336 struct kvm_pit_config pit_config;
f0d66275 3337 } u;
1fe779f8
CO		 3338
3339 switch (ioctl) {
3340 case KVM_SET_TSS_ADDR:
3341 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3342 if (r < 0)
3343 goto out;
3344 break;
b927a3ce
SY		 3345 case KVM_SET_IDENTITY_MAP_ADDR: {
3346 u64 ident_addr;
3347
3348 r = -EFAULT;
3349 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3350 goto out;
3351 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3352 if (r < 0)
3353 goto out;
3354 break;
3355 }
1fe779f8
CO		 3356 case KVM_SET_NR_MMU_PAGES:
3357 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3358 if (r)
3359 goto out;
3360 break;
3361 case KVM_GET_NR_MMU_PAGES:
3362 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3363 break;
3ddea128
MT		 3364 case KVM_CREATE_IRQCHIP: {
3365 struct kvm_pic *vpic;
3366
3367 mutex_lock(&kvm->lock);
3368 r = -EEXIST;
3369 if (kvm->arch.vpic)
3370 goto create_irqchip_unlock;
1fe779f8 3371 r = -ENOMEM;
3ddea128
MT		 3372 vpic = kvm_create_pic(kvm);
3373 if (vpic) {
1fe779f8
CO		 3374 r = kvm_ioapic_init(kvm);
3375 if (r) {
175504cd 3376 mutex_lock(&kvm->slots_lock);
72bb2fcd
WY		 3377 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3378 &vpic->dev);
175504cd 3379 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3380 kfree(vpic);
3381 goto create_irqchip_unlock;
1fe779f8
CO		 3382 }
3383 } else
3ddea128
MT		 3384 goto create_irqchip_unlock;
3385 smp_wmb();
3386 kvm->arch.vpic = vpic;
3387 smp_wmb();
399ec807
AK		 3388 r = kvm_setup_default_irq_routing(kvm);
3389 if (r) {
175504cd 3390 mutex_lock(&kvm->slots_lock);
3ddea128 3391 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3392 kvm_ioapic_destroy(kvm);
3393 kvm_destroy_pic(kvm);
3ddea128 3394 mutex_unlock(&kvm->irq_lock);
175504cd 3395 mutex_unlock(&kvm->slots_lock);
399ec807 3396 }
3ddea128
MT		 3397 create_irqchip_unlock:
3398 mutex_unlock(&kvm->lock);
1fe779f8 3399 break;
3ddea128 3400 }
7837699f 3401 case KVM_CREATE_PIT:
c5ff41ce
JK		 3402 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3403 goto create_pit;
3404 case KVM_CREATE_PIT2:
3405 r = -EFAULT;
3406 if (copy_from_user(&u.pit_config, argp,
3407 sizeof(struct kvm_pit_config)))
3408 goto out;
3409 create_pit:
79fac95e 3410 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3411 r = -EEXIST;
3412 if (kvm->arch.vpit)
3413 goto create_pit_unlock;
7837699f 3414 r = -ENOMEM;
c5ff41ce 3415 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3416 if (kvm->arch.vpit)
3417 r = 0;
269e05e4 3418 create_pit_unlock:
79fac95e 3419 mutex_unlock(&kvm->slots_lock);
7837699f 3420 break;
4925663a 3421 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 3422 case KVM_IRQ_LINE: {
3423 struct kvm_irq_level irq_event;
3424
3425 r = -EFAULT;
3426 if (copy_from_user(&irq_event, argp, sizeof irq_event))
3427 goto out;
160d2f6c 3428 r = -ENXIO;
1fe779f8 3429 if (irqchip_in_kernel(kvm)) {
4925663a 3430 __s32 status;
4925663a
GN		 3431 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3432 irq_event.irq, irq_event.level);
4925663a 3433 if (ioctl == KVM_IRQ_LINE_STATUS) {
160d2f6c 3434 r = -EFAULT;
4925663a
GN		 3435 irq_event.status = status;
3436 if (copy_to_user(argp, &irq_event,
3437 sizeof irq_event))
3438 goto out;
3439 }
1fe779f8
CO		 3440 r = 0;
3441 }
3442 break;
3443 }
3444 case KVM_GET_IRQCHIP: {
3445 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3446 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3447
f0d66275
DH		 3448 r = -ENOMEM;
3449 if (!chip)
1fe779f8 3450 goto out;
f0d66275
DH		 3451 r = -EFAULT;
3452 if (copy_from_user(chip, argp, sizeof *chip))
3453 goto get_irqchip_out;
1fe779f8
CO		 3454 r = -ENXIO;
3455 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3456 goto get_irqchip_out;
3457 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3458 if (r)
f0d66275 3459 goto get_irqchip_out;
1fe779f8 3460 r = -EFAULT;
f0d66275
DH		 3461 if (copy_to_user(argp, chip, sizeof *chip))
3462 goto get_irqchip_out;
1fe779f8 3463 r = 0;
f0d66275
DH		 3464 get_irqchip_out:
3465 kfree(chip);
3466 if (r)
3467 goto out;
1fe779f8
CO		 3468 break;
3469 }
3470 case KVM_SET_IRQCHIP: {
3471 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3472 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3473
f0d66275
DH		 3474 r = -ENOMEM;
3475 if (!chip)
1fe779f8 3476 goto out;
f0d66275
DH		 3477 r = -EFAULT;
3478 if (copy_from_user(chip, argp, sizeof *chip))
3479 goto set_irqchip_out;
1fe779f8
CO		 3480 r = -ENXIO;
3481 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3482 goto set_irqchip_out;
3483 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3484 if (r)
f0d66275 3485 goto set_irqchip_out;
1fe779f8 3486 r = 0;
f0d66275
DH		 3487 set_irqchip_out:
3488 kfree(chip);
3489 if (r)
3490 goto out;
1fe779f8
CO		 3491 break;
3492 }
e0f63cb9 3493 case KVM_GET_PIT: {
e0f63cb9 3494 r = -EFAULT;
f0d66275 3495 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3496 goto out;
3497 r = -ENXIO;
3498 if (!kvm->arch.vpit)
3499 goto out;
f0d66275 3500 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3501 if (r)
3502 goto out;
3503 r = -EFAULT;
f0d66275 3504 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3505 goto out;
3506 r = 0;
3507 break;
3508 }
3509 case KVM_SET_PIT: {
e0f63cb9 3510 r = -EFAULT;
f0d66275 3511 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3512 goto out;
3513 r = -ENXIO;
3514 if (!kvm->arch.vpit)
3515 goto out;
f0d66275 3516 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3517 if (r)
3518 goto out;
3519 r = 0;
3520 break;
3521 }
e9f42757
BK		 3522 case KVM_GET_PIT2: {
3523 r = -ENXIO;
3524 if (!kvm->arch.vpit)
3525 goto out;
3526 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3527 if (r)
3528 goto out;
3529 r = -EFAULT;
3530 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3531 goto out;
3532 r = 0;
3533 break;
3534 }
3535 case KVM_SET_PIT2: {
3536 r = -EFAULT;
3537 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3538 goto out;
3539 r = -ENXIO;
3540 if (!kvm->arch.vpit)
3541 goto out;
3542 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3543 if (r)
3544 goto out;
3545 r = 0;
3546 break;
3547 }
52d939a0
MT		 3548 case KVM_REINJECT_CONTROL: {
3549 struct kvm_reinject_control control;
3550 r = -EFAULT;
3551 if (copy_from_user(&control, argp, sizeof(control)))
3552 goto out;
3553 r = kvm_vm_ioctl_reinject(kvm, &control);
3554 if (r)
3555 goto out;
3556 r = 0;
3557 break;
3558 }
ffde22ac
ES		 3559 case KVM_XEN_HVM_CONFIG: {
3560 r = -EFAULT;
3561 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3562 sizeof(struct kvm_xen_hvm_config)))
3563 goto out;
3564 r = -EINVAL;
3565 if (kvm->arch.xen_hvm_config.flags)
3566 goto out;
3567 r = 0;
3568 break;
3569 }
afbcf7ab 3570 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3571 struct kvm_clock_data user_ns;
3572 u64 now_ns;
3573 s64 delta;
3574
3575 r = -EFAULT;
3576 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3577 goto out;
3578
3579 r = -EINVAL;
3580 if (user_ns.flags)
3581 goto out;
3582
3583 r = 0;
395c6b0a 3584 local_irq_disable();
759379dd 3585 now_ns = get_kernel_ns();
afbcf7ab 3586 delta = user_ns.clock - now_ns;
395c6b0a 3587 local_irq_enable();
afbcf7ab
GC		 3588 kvm->arch.kvmclock_offset = delta;
3589 break;
3590 }
3591 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3592 struct kvm_clock_data user_ns;
3593 u64 now_ns;
3594
395c6b0a 3595 local_irq_disable();
759379dd 3596 now_ns = get_kernel_ns();
afbcf7ab 3597 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3598 local_irq_enable();
afbcf7ab 3599 user_ns.flags = 0;
97e69aa6 3600 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3601
3602 r = -EFAULT;
3603 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3604 goto out;
3605 r = 0;
3606 break;
3607 }
3608
1fe779f8
CO		 3609 default:
3610 ;
3611 }
3612out:
3613 return r;
3614}
3615
a16b043c 3616static void kvm_init_msr_list(void)
043405e1
CO		 3617{
3618 u32 dummy[2];
3619 unsigned i, j;
3620
e3267cbb
GC		 3621 /* skip the first msrs in the list. KVM-specific */
3622 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3623 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3624 continue;
3625 if (j < i)
3626 msrs_to_save[j] = msrs_to_save[i];
3627 j++;
3628 }
3629 num_msrs_to_save = j;
3630}
3631
bda9020e
MT		 3632static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3633 const void *v)
bbd9b64e 3634{
70252a10
AK		 3635 int handled = 0;
3636 int n;
3637
3638 do {
3639 n = min(len, 8);
3640 if (!(vcpu->arch.apic &&
3641 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3642 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3643 break;
3644 handled += n;
3645 addr += n;
3646 len -= n;
3647 v += n;
3648 } while (len);
bbd9b64e 3649
70252a10 3650 return handled;
bbd9b64e
CO		 3651}
3652
bda9020e 3653static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3654{
70252a10
AK		 3655 int handled = 0;
3656 int n;
3657
3658 do {
3659 n = min(len, 8);
3660 if (!(vcpu->arch.apic &&
3661 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3662 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3663 break;
3664 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3665 handled += n;
3666 addr += n;
3667 len -= n;
3668 v += n;
3669 } while (len);
bbd9b64e 3670
70252a10 3671 return handled;
bbd9b64e
CO		 3672}
3673
2dafc6c2
GN		 3674static void kvm_set_segment(struct kvm_vcpu *vcpu,
3675 struct kvm_segment *var, int seg)
3676{
3677 kvm_x86_ops->set_segment(vcpu, var, seg);
3678}
3679
3680void kvm_get_segment(struct kvm_vcpu *vcpu,
3681 struct kvm_segment *var, int seg)
3682{
3683 kvm_x86_ops->get_segment(vcpu, var, seg);
3684}
3685
c30a358d
JR		 3686static gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3687{
3688 return gpa;
3689}
3690
02f59dc9
JR		 3691static gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3692{
3693 gpa_t t_gpa;
ab9ae313 3694 struct x86_exception exception;
02f59dc9
JR		 3695
3696 BUG_ON(!mmu_is_nested(vcpu));
3697
3698 /* NPT walks are always user-walks */
3699 access |= PFERR_USER_MASK;
ab9ae313 3700 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
02f59dc9
JR		 3701
3702 return t_gpa;
3703}
3704
ab9ae313
AK		 3705gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3706 struct x86_exception *exception)
1871c602
GN		 3707{
3708 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 3709 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3710}
3711
ab9ae313
AK		 3712 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3713 struct x86_exception *exception)
1871c602
GN		 3714{
3715 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3716 access |= PFERR_FETCH_MASK;
ab9ae313 3717 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3718}
3719
ab9ae313
AK		 3720gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3721 struct x86_exception *exception)
1871c602
GN		 3722{
3723 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3724 access |= PFERR_WRITE_MASK;
ab9ae313 3725 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3726}
3727
3728/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 3729gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3730 struct x86_exception *exception)
1871c602 3731{
ab9ae313 3732 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 3733}
3734
3735static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3736 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 3737 struct x86_exception *exception)
bbd9b64e
CO		 3738{
3739 void *data = val;
10589a46 3740 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3741
3742 while (bytes) {
14dfe855 3743 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 3744 exception);
bbd9b64e 3745 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3746 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3747 int ret;
3748
bcc55cba 3749 if (gpa == UNMAPPED_GVA)
ab9ae313 3750 return X86EMUL_PROPAGATE_FAULT;
77c2002e 3751 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3752 if (ret < 0) {
c3cd7ffa 3753 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3754 goto out;
3755 }
bbd9b64e 3756
77c2002e
IE		 3757 bytes -= toread;
3758 data += toread;
3759 addr += toread;
bbd9b64e 3760 }
10589a46 3761out:
10589a46 3762 return r;
bbd9b64e 3763}
77c2002e 3764
1871c602 3765/* used for instruction fetching */
0f65dd70
AK		 3766static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
3767 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3768 struct x86_exception *exception)
1871c602 3769{
0f65dd70 3770 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3771 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3772
1871c602 3773 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
bcc55cba
AK		 3774 access | PFERR_FETCH_MASK,
3775 exception);
1871c602
GN		 3776}
3777
0f65dd70
AK		 3778static int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
3779 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3780 struct x86_exception *exception)
1871c602 3781{
0f65dd70 3782 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3783 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3784
1871c602 3785 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 3786 exception);
1871c602
GN		 3787}
3788
0f65dd70
AK		 3789static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3790 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3791 struct x86_exception *exception)
1871c602 3792{
0f65dd70 3793 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 3794 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 3795}
3796
0f65dd70
AK		 3797static int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3798 gva_t addr, void *val,
2dafc6c2 3799 unsigned int bytes,
bcc55cba 3800 struct x86_exception *exception)
77c2002e 3801{
0f65dd70 3802 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 3803 void *data = val;
3804 int r = X86EMUL_CONTINUE;
3805
3806 while (bytes) {
14dfe855
JR		 3807 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3808 PFERR_WRITE_MASK,
ab9ae313 3809 exception);
77c2002e
IE		 3810 unsigned offset = addr & (PAGE_SIZE-1);
3811 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3812 int ret;
3813
bcc55cba 3814 if (gpa == UNMAPPED_GVA)
ab9ae313 3815 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 3816 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3817 if (ret < 0) {
c3cd7ffa 3818 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 3819 goto out;
3820 }
3821
3822 bytes -= towrite;
3823 data += towrite;
3824 addr += towrite;
3825 }
3826out:
3827 return r;
3828}
3829
0f65dd70
AK		 3830static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
3831 unsigned long addr,
bbd9b64e
CO		 3832 void *val,
3833 unsigned int bytes,
0f65dd70 3834 struct x86_exception *exception)
bbd9b64e 3835{
0f65dd70 3836 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bbd9b64e 3837 gpa_t gpa;
70252a10 3838 int handled;
bbd9b64e
CO		 3839
3840 if (vcpu->mmio_read_completed) {
3841 memcpy(val, vcpu->mmio_data, bytes);
aec51dc4
AK		 3842 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3843 vcpu->mmio_phys_addr, *(u64 *)val);
bbd9b64e
CO		 3844 vcpu->mmio_read_completed = 0;
3845 return X86EMUL_CONTINUE;
3846 }
3847
ab9ae313 3848 gpa = kvm_mmu_gva_to_gpa_read(vcpu, addr, exception);
1871c602 3849
8fe681e9 3850 if (gpa == UNMAPPED_GVA)
1871c602 3851 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3852
3853 /* For APIC access vmexit */
3854 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3855 goto mmio;
3856
0f65dd70 3857 if (kvm_read_guest_virt(ctxt, addr, val, bytes, exception)
bcc55cba 3858 == X86EMUL_CONTINUE)
bbd9b64e 3859 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3860
3861mmio:
3862 /*
3863 * Is this MMIO handled locally?
3864 */
70252a10
AK		 3865 handled = vcpu_mmio_read(vcpu, gpa, bytes, val);
3866
3867 if (handled == bytes)
bbd9b64e 3868 return X86EMUL_CONTINUE;
70252a10
AK		 3869
3870 gpa += handled;
3871 bytes -= handled;
3872 val += handled;
aec51dc4
AK		 3873
3874 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
bbd9b64e
CO		 3875
3876 vcpu->mmio_needed = 1;
411c35b7
GN		 3877 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3878 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
cef4dea0
AK		 3879 vcpu->mmio_size = bytes;
3880 vcpu->run->mmio.len = min(vcpu->mmio_size, 8);
411c35b7 3881 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 0;
cef4dea0 3882 vcpu->mmio_index = 0;
bbd9b64e 3883
c3cd7ffa 3884 return X86EMUL_IO_NEEDED;
bbd9b64e
CO		 3885}
3886
3200f405 3887int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 3888 const void *val, int bytes)
bbd9b64e
CO		 3889{
3890 int ret;
3891
3892 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3893 if (ret < 0)
bbd9b64e 3894 return 0;
ad218f85 3895 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 3896 return 1;
3897}
3898
3899static int emulator_write_emulated_onepage(unsigned long addr,
3900 const void *val,
3901 unsigned int bytes,
bcc55cba 3902 struct x86_exception *exception,
bbd9b64e
CO		 3903 struct kvm_vcpu *vcpu)
3904{
10589a46 3905 gpa_t gpa;
70252a10 3906 int handled;
10589a46 3907
ab9ae313 3908 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, exception);
bbd9b64e 3909
8fe681e9 3910 if (gpa == UNMAPPED_GVA)
bbd9b64e 3911 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3912
3913 /* For APIC access vmexit */
3914 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3915 goto mmio;
3916
3917 if (emulator_write_phys(vcpu, gpa, val, bytes))
3918 return X86EMUL_CONTINUE;
3919
3920mmio:
aec51dc4 3921 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3922 /*
3923 * Is this MMIO handled locally?
3924 */
70252a10
AK		 3925 handled = vcpu_mmio_write(vcpu, gpa, bytes, val);
3926 if (handled == bytes)
bbd9b64e 3927 return X86EMUL_CONTINUE;
bbd9b64e 3928
70252a10
AK		 3929 gpa += handled;
3930 bytes -= handled;
3931 val += handled;
3932
bbd9b64e 3933 vcpu->mmio_needed = 1;
cef4dea0 3934 memcpy(vcpu->mmio_data, val, bytes);
411c35b7
GN		 3935 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3936 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
cef4dea0
AK		 3937 vcpu->mmio_size = bytes;
3938 vcpu->run->mmio.len = min(vcpu->mmio_size, 8);
411c35b7 3939 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 1;
cef4dea0
AK		 3940 memcpy(vcpu->run->mmio.data, vcpu->mmio_data, 8);
3941 vcpu->mmio_index = 0;
bbd9b64e
CO		 3942
3943 return X86EMUL_CONTINUE;
3944}
3945
0f65dd70
AK		 3946int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
3947 unsigned long addr,
8f6abd06
GN		 3948 const void *val,
3949 unsigned int bytes,
0f65dd70 3950 struct x86_exception *exception)
bbd9b64e 3951{
0f65dd70
AK		 3952 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3953
bbd9b64e
CO		 3954 /* Crossing a page boundary? */
3955 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3956 int rc, now;
3957
3958 now = -addr & ~PAGE_MASK;
bcc55cba 3959 rc = emulator_write_emulated_onepage(addr, val, now, exception,
8fe681e9 3960 vcpu);
bbd9b64e
CO		 3961 if (rc != X86EMUL_CONTINUE)
3962 return rc;
3963 addr += now;
3964 val += now;
3965 bytes -= now;
3966 }
bcc55cba 3967 return emulator_write_emulated_onepage(addr, val, bytes, exception,
8fe681e9 3968 vcpu);
bbd9b64e 3969}
bbd9b64e 3970
daea3e73
AK		 3971#define CMPXCHG_TYPE(t, ptr, old, new) \
3972 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
3973
3974#ifdef CONFIG_X86_64
3975# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
3976#else
3977# define CMPXCHG64(ptr, old, new) \
9749a6c0 3978 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 3979#endif
3980
0f65dd70
AK		 3981static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
3982 unsigned long addr,
bbd9b64e
CO		 3983 const void *old,
3984 const void *new,
3985 unsigned int bytes,
0f65dd70 3986 struct x86_exception *exception)
bbd9b64e 3987{
0f65dd70 3988 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 3989 gpa_t gpa;
3990 struct page *page;
3991 char *kaddr;
3992 bool exchanged;
2bacc55c 3993
daea3e73
AK		 3994 /* guests cmpxchg8b have to be emulated atomically */
3995 if (bytes > 8 || (bytes & (bytes - 1)))
3996 goto emul_write;
10589a46 3997
daea3e73 3998 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 3999
daea3e73
AK		 4000 if (gpa == UNMAPPED_GVA ||
4001 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4002 goto emul_write;
2bacc55c 4003
daea3e73
AK		 4004 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4005 goto emul_write;
72dc67a6 4006
daea3e73 4007 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
c19b8bd6
WY		 4008 if (is_error_page(page)) {
4009 kvm_release_page_clean(page);
4010 goto emul_write;
4011 }
72dc67a6 4012
daea3e73
AK		 4013 kaddr = kmap_atomic(page, KM_USER0);
4014 kaddr += offset_in_page(gpa);
4015 switch (bytes) {
4016 case 1:
4017 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4018 break;
4019 case 2:
4020 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4021 break;
4022 case 4:
4023 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4024 break;
4025 case 8:
4026 exchanged = CMPXCHG64(kaddr, old, new);
4027 break;
4028 default:
4029 BUG();
2bacc55c 4030 }
daea3e73
AK		 4031 kunmap_atomic(kaddr, KM_USER0);
4032 kvm_release_page_dirty(page);
4033
4034 if (!exchanged)
4035 return X86EMUL_CMPXCHG_FAILED;
4036
8f6abd06
GN		 4037 kvm_mmu_pte_write(vcpu, gpa, new, bytes, 1);
4038
4039 return X86EMUL_CONTINUE;
4a5f48f6 4040
3200f405 4041emul_write:
daea3e73 4042 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4043
0f65dd70 4044 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4045}
4046
cf8f70bf
GN		 4047static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4048{
4049 /* TODO: String I/O for in kernel device */
4050 int r;
4051
4052 if (vcpu->arch.pio.in)
4053 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4054 vcpu->arch.pio.size, pd);
4055 else
4056 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4057 vcpu->arch.pio.port, vcpu->arch.pio.size,
4058 pd);
4059 return r;
4060}
4061
4062
ca1d4a9e
AK		 4063static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4064 int size, unsigned short port, void *val,
4065 unsigned int count)
cf8f70bf 4066{
ca1d4a9e
AK		 4067 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4068
7972995b 4069 if (vcpu->arch.pio.count)
cf8f70bf
GN		 4070 goto data_avail;
4071
61cfab2e 4072 trace_kvm_pio(0, port, size, count);
cf8f70bf
GN		 4073
4074 vcpu->arch.pio.port = port;
4075 vcpu->arch.pio.in = 1;
7972995b 4076 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4077 vcpu->arch.pio.size = size;
4078
4079 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4080 data_avail:
4081 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 4082 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4083 return 1;
4084 }
4085
4086 vcpu->run->exit_reason = KVM_EXIT_IO;
4087 vcpu->run->io.direction = KVM_EXIT_IO_IN;
4088 vcpu->run->io.size = size;
4089 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4090 vcpu->run->io.count = count;
4091 vcpu->run->io.port = port;
4092
4093 return 0;
4094}
4095
ca1d4a9e
AK		 4096static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4097 int size, unsigned short port,
4098 const void *val, unsigned int count)
cf8f70bf 4099{
ca1d4a9e
AK		 4100 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4101
61cfab2e 4102 trace_kvm_pio(1, port, size, count);
cf8f70bf
GN		 4103
4104 vcpu->arch.pio.port = port;
4105 vcpu->arch.pio.in = 0;
7972995b 4106 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4107 vcpu->arch.pio.size = size;
4108
4109 memcpy(vcpu->arch.pio_data, val, size * count);
4110
4111 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4112 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4113 return 1;
4114 }
4115
4116 vcpu->run->exit_reason = KVM_EXIT_IO;
4117 vcpu->run->io.direction = KVM_EXIT_IO_OUT;
4118 vcpu->run->io.size = size;
4119 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4120 vcpu->run->io.count = count;
4121 vcpu->run->io.port = port;
4122
4123 return 0;
4124}
4125
bbd9b64e
CO		 4126static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4127{
4128 return kvm_x86_ops->get_segment_base(vcpu, seg);
4129}
4130
3cb16fe7 4131static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4132{
3cb16fe7 4133 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4134}
4135
f5f48ee1
SY		 4136int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4137{
4138 if (!need_emulate_wbinvd(vcpu))
4139 return X86EMUL_CONTINUE;
4140
4141 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4142 int cpu = get_cpu();
4143
4144 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4145 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4146 wbinvd_ipi, NULL, 1);
2eec7343 4147 put_cpu();
f5f48ee1 4148 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4149 } else
4150 wbinvd();
f5f48ee1
SY		 4151 return X86EMUL_CONTINUE;
4152}
4153EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4154
717746e3 4155int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
bbd9b64e 4156{
717746e3 4157 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4158}
4159
717746e3 4160int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
bbd9b64e 4161{
338dbc97 4162
717746e3 4163 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4164}
4165
52a46617 4166static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4167{
52a46617 4168 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4169}
4170
717746e3 4171static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4172{
717746e3 4173 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4174 unsigned long value;
4175
4176 switch (cr) {
4177 case 0:
4178 value = kvm_read_cr0(vcpu);
4179 break;
4180 case 2:
4181 value = vcpu->arch.cr2;
4182 break;
4183 case 3:
9f8fe504 4184 value = kvm_read_cr3(vcpu);
52a46617
GN		 4185 break;
4186 case 4:
4187 value = kvm_read_cr4(vcpu);
4188 break;
4189 case 8:
4190 value = kvm_get_cr8(vcpu);
4191 break;
4192 default:
4193 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
4194 return 0;
4195 }
4196
4197 return value;
4198}
4199
717746e3 4200static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4201{
717746e3 4202 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4203 int res = 0;
4204
52a46617
GN		 4205 switch (cr) {
4206 case 0:
49a9b07e 4207 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4208 break;
4209 case 2:
4210 vcpu->arch.cr2 = val;
4211 break;
4212 case 3:
2390218b 4213 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4214 break;
4215 case 4:
a83b29c6 4216 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4217 break;
4218 case 8:
eea1cff9 4219 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4220 break;
4221 default:
4222 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
0f12244f 4223 res = -1;
52a46617 4224 }
0f12244f
GN		 4225
4226 return res;
52a46617
GN		 4227}
4228
717746e3 4229static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4230{
717746e3 4231 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4232}
4233
4bff1e86 4234static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4235{
4bff1e86 4236 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4237}
4238
4bff1e86 4239static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4240{
4bff1e86 4241 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4242}
4243
1ac9d0cf
AK		 4244static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4245{
4246 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4247}
4248
4249static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4250{
4251 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4252}
4253
4bff1e86
AK		 4254static unsigned long emulator_get_cached_segment_base(
4255 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4256{
4bff1e86 4257 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4258}
4259
4bff1e86
AK		 4260static bool emulator_get_cached_descriptor(struct x86_emulate_ctxt *ctxt,
4261 struct desc_struct *desc, u32 *base3,
4262 int seg)
2dafc6c2
GN		 4263{
4264 struct kvm_segment var;
4265
4bff1e86 4266 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
2dafc6c2
GN		 4267
4268 if (var.unusable)
4269 return false;
4270
4271 if (var.g)
4272 var.limit >>= 12;
4273 set_desc_limit(desc, var.limit);
4274 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4275#ifdef CONFIG_X86_64
4276 if (base3)
4277 *base3 = var.base >> 32;
4278#endif
2dafc6c2
GN		 4279 desc->type = var.type;
4280 desc->s = var.s;
4281 desc->dpl = var.dpl;
4282 desc->p = var.present;
4283 desc->avl = var.avl;
4284 desc->l = var.l;
4285 desc->d = var.db;
4286 desc->g = var.g;
4287
4288 return true;
4289}
4290
4bff1e86
AK		 4291static void emulator_set_cached_descriptor(struct x86_emulate_ctxt *ctxt,
4292 struct desc_struct *desc, u32 base3,
4293 int seg)
2dafc6c2 4294{
4bff1e86 4295 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4296 struct kvm_segment var;
4297
4298 /* needed to preserve selector */
4299 kvm_get_segment(vcpu, &var, seg);
4300
4301 var.base = get_desc_base(desc);
5601d05b
GN		 4302#ifdef CONFIG_X86_64
4303 var.base |= ((u64)base3) << 32;
4304#endif
2dafc6c2
GN		 4305 var.limit = get_desc_limit(desc);
4306 if (desc->g)
4307 var.limit = (var.limit << 12) | 0xfff;
4308 var.type = desc->type;
4309 var.present = desc->p;
4310 var.dpl = desc->dpl;
4311 var.db = desc->d;
4312 var.s = desc->s;
4313 var.l = desc->l;
4314 var.g = desc->g;
4315 var.avl = desc->avl;
4316 var.present = desc->p;
4317 var.unusable = !var.present;
4318 var.padding = 0;
4319
4320 kvm_set_segment(vcpu, &var, seg);
4321 return;
4322}
4323
4bff1e86 4324static u16 emulator_get_segment_selector(struct x86_emulate_ctxt *ctxt, int seg)
2dafc6c2
GN		 4325{
4326 struct kvm_segment kvm_seg;
4327
4bff1e86 4328 kvm_get_segment(emul_to_vcpu(ctxt), &kvm_seg, seg);
2dafc6c2
GN		 4329 return kvm_seg.selector;
4330}
4331
4bff1e86
AK		 4332static void emulator_set_segment_selector(struct x86_emulate_ctxt *ctxt,
4333 u16 sel, int seg)
2dafc6c2
GN		 4334{
4335 struct kvm_segment kvm_seg;
4336
4bff1e86 4337 kvm_get_segment(emul_to_vcpu(ctxt), &kvm_seg, seg);
2dafc6c2 4338 kvm_seg.selector = sel;
4bff1e86 4339 kvm_set_segment(emul_to_vcpu(ctxt), &kvm_seg, seg);
2dafc6c2
GN		 4340}
4341
717746e3
AK		 4342static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4343 u32 msr_index, u64 *pdata)
4344{
4345 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4346}
4347
4348static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4349 u32 msr_index, u64 data)
4350{
4351 return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
4352}
4353
5037f6f3
AK		 4354static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4355{
4356 preempt_disable();
4357 kvm_load_guest_fpu(ctxt->vcpu);
4358 /*
4359 * CR0.TS may reference the host fpu state, not the guest fpu state,
4360 * so it may be clear at this point.
4361 */
4362 clts();
4363}
4364
4365static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4366{
4367 preempt_enable();
4368}
4369
2953538e 4370static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4371 struct x86_instruction_info *info,
c4f035c6
AK		 4372 enum x86_intercept_stage stage)
4373{
2953538e 4374 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4375}
4376
14af3f3c 4377static struct x86_emulate_ops emulate_ops = {
1871c602 4378 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4379 .write_std = kvm_write_guest_virt_system,
1871c602 4380 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4381 .read_emulated = emulator_read_emulated,
4382 .write_emulated = emulator_write_emulated,
4383 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4384 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4385 .pio_in_emulated = emulator_pio_in_emulated,
4386 .pio_out_emulated = emulator_pio_out_emulated,
2dafc6c2
GN		 4387 .get_cached_descriptor = emulator_get_cached_descriptor,
4388 .set_cached_descriptor = emulator_set_cached_descriptor,
4389 .get_segment_selector = emulator_get_segment_selector,
4390 .set_segment_selector = emulator_set_segment_selector,
5951c442 4391 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4392 .get_gdt = emulator_get_gdt,
160ce1f1 4393 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4394 .set_gdt = emulator_set_gdt,
4395 .set_idt = emulator_set_idt,
52a46617
GN		 4396 .get_cr = emulator_get_cr,
4397 .set_cr = emulator_set_cr,
9c537244 4398 .cpl = emulator_get_cpl,
35aa5375
GN		 4399 .get_dr = emulator_get_dr,
4400 .set_dr = emulator_set_dr,
717746e3
AK		 4401 .set_msr = emulator_set_msr,
4402 .get_msr = emulator_get_msr,
5037f6f3
AK		 4403 .get_fpu = emulator_get_fpu,
4404 .put_fpu = emulator_put_fpu,
c4f035c6 4405 .intercept = emulator_intercept,
bbd9b64e
CO		 4406};
4407
5fdbf976
MT		 4408static void cache_all_regs(struct kvm_vcpu *vcpu)
4409{
4410 kvm_register_read(vcpu, VCPU_REGS_RAX);
4411 kvm_register_read(vcpu, VCPU_REGS_RSP);
4412 kvm_register_read(vcpu, VCPU_REGS_RIP);
4413 vcpu->arch.regs_dirty = ~0;
4414}
4415
95cb2295
GN		 4416static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4417{
4418 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4419 /*
4420 * an sti; sti; sequence only disable interrupts for the first
4421 * instruction. So, if the last instruction, be it emulated or
4422 * not, left the system with the INT_STI flag enabled, it
4423 * means that the last instruction is an sti. We should not
4424 * leave the flag on in this case. The same goes for mov ss
4425 */
4426 if (!(int_shadow & mask))
4427 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4428}
4429
54b8486f
GN		 4430static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4431{
4432 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4433 if (ctxt->exception.vector == PF_VECTOR)
6389ee94 4434 kvm_propagate_fault(vcpu, &ctxt->exception);
da9cb575
AK		 4435 else if (ctxt->exception.error_code_valid)
4436 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4437 ctxt->exception.error_code);
54b8486f 4438 else
da9cb575 4439 kvm_queue_exception(vcpu, ctxt->exception.vector);
54b8486f
GN		 4440}
4441
8ec4722d
MG		 4442static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4443{
4444 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
4445 int cs_db, cs_l;
4446
4447 cache_all_regs(vcpu);
4448
4449 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4450
4451 vcpu->arch.emulate_ctxt.vcpu = vcpu;
f6e78475 4452 vcpu->arch.emulate_ctxt.eflags = kvm_get_rflags(vcpu);
8ec4722d
MG		 4453 vcpu->arch.emulate_ctxt.eip = kvm_rip_read(vcpu);
4454 vcpu->arch.emulate_ctxt.mode =
4455 (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4456 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
4457 ? X86EMUL_MODE_VM86 : cs_l
4458 ? X86EMUL_MODE_PROT64 : cs_db
4459 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
c4f035c6 4460 vcpu->arch.emulate_ctxt.guest_mode = is_guest_mode(vcpu);
8ec4722d
MG		 4461 memset(c, 0, sizeof(struct decode_cache));
4462 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
7ae441ea 4463 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4464}
4465
71f9833b 4466int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653
MG		 4467{
4468 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
4469 int ret;
4470
4471 init_emulate_ctxt(vcpu);
4472
4473 vcpu->arch.emulate_ctxt.decode.op_bytes = 2;
4474 vcpu->arch.emulate_ctxt.decode.ad_bytes = 2;
71f9833b
SH		 4475 vcpu->arch.emulate_ctxt.decode.eip = vcpu->arch.emulate_ctxt.eip +
4476 inc_eip;
63995653
MG		 4477 ret = emulate_int_real(&vcpu->arch.emulate_ctxt, &emulate_ops, irq);
4478
4479 if (ret != X86EMUL_CONTINUE)
4480 return EMULATE_FAIL;
4481
4482 vcpu->arch.emulate_ctxt.eip = c->eip;
4483 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
4484 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
f6e78475 4485 kvm_set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
63995653
MG		 4486
4487 if (irq == NMI_VECTOR)
4488 vcpu->arch.nmi_pending = false;
4489 else
4490 vcpu->arch.interrupt.pending = false;
4491
4492 return EMULATE_DONE;
4493}
4494EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4495
6d77dbfc
GN		 4496static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4497{
fc3a9157
JR		 4498 int r = EMULATE_DONE;
4499
6d77dbfc
GN		 4500 ++vcpu->stat.insn_emulation_fail;
4501 trace_kvm_emulate_insn_failed(vcpu);
fc3a9157
JR		 4502 if (!is_guest_mode(vcpu)) {
4503 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4504 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4505 vcpu->run->internal.ndata = 0;
4506 r = EMULATE_FAIL;
4507 }
6d77dbfc 4508 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4509
4510 return r;
6d77dbfc
GN		 4511}
4512
a6f177ef
GN		 4513static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
4514{
4515 gpa_t gpa;
4516
68be0803
GN		 4517 if (tdp_enabled)
4518 return false;
4519
a6f177ef
GN		 4520 /*
4521 * if emulation was due to access to shadowed page table
4522 * and it failed try to unshadow page and re-entetr the
4523 * guest to let CPU execute the instruction.
4524 */
4525 if (kvm_mmu_unprotect_page_virt(vcpu, gva))
4526 return true;
4527
4528 gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
4529
4530 if (gpa == UNMAPPED_GVA)
4531 return true; /* let cpu generate fault */
4532
4533 if (!kvm_is_error_hva(gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT)))
4534 return true;
4535
4536 return false;
4537}
4538
51d8b661
AP		 4539int x86_emulate_instruction(struct kvm_vcpu *vcpu,
4540 unsigned long cr2,
dc25e89e
AP		 4541 int emulation_type,
4542 void *insn,
4543 int insn_len)
bbd9b64e 4544{
95cb2295 4545 int r;
4d2179e1 4546 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
7ae441ea 4547 bool writeback = true;
bbd9b64e 4548
26eef70c 4549 kvm_clear_exception_queue(vcpu);
ad312c7c 4550 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976 4551 /*
56e82318 4552 * TODO: fix emulate.c to use guest_read/write_register
5fdbf976
MT		 4553 * instead of direct ->regs accesses, can save hundred cycles
4554 * on Intel for instructions that don't read/change RSP, for
4555 * for example.
4556 */
4557 cache_all_regs(vcpu);
bbd9b64e 4558
571008da 4559 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 4560 init_emulate_ctxt(vcpu);
95cb2295 4561 vcpu->arch.emulate_ctxt.interruptibility = 0;
da9cb575 4562 vcpu->arch.emulate_ctxt.have_exception = false;
4fc40f07 4563 vcpu->arch.emulate_ctxt.perm_ok = false;
bbd9b64e 4564
4005996e
AK		 4565 vcpu->arch.emulate_ctxt.only_vendor_specific_insn
4566 = emulation_type & EMULTYPE_TRAP_UD;
4567
dc25e89e 4568 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, insn, insn_len);
bbd9b64e 4569
e46479f8 4570 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 4571 ++vcpu->stat.insn_emulation;
bbd9b64e 4572 if (r) {
4005996e
AK		 4573 if (emulation_type & EMULTYPE_TRAP_UD)
4574 return EMULATE_FAIL;
a6f177ef 4575 if (reexecute_instruction(vcpu, cr2))
bbd9b64e 4576 return EMULATE_DONE;
6d77dbfc
GN		 4577 if (emulation_type & EMULTYPE_SKIP)
4578 return EMULATE_FAIL;
4579 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4580 }
4581 }
4582
ba8afb6b
GN		 4583 if (emulation_type & EMULTYPE_SKIP) {
4584 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
4585 return EMULATE_DONE;
4586 }
4587
7ae441ea 4588 /* this is needed for vmware backdoor interface to work since it
4d2179e1 4589 changes registers values during IO operation */
7ae441ea
GN		 4590 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
4591 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
4592 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
4593 }
4d2179e1 4594
5cd21917 4595restart:
9aabc88f 4596 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt);
bbd9b64e 4597
775fde86
JR		 4598 if (r == EMULATION_INTERCEPTED)
4599 return EMULATE_DONE;
4600
d2ddd1c4 4601 if (r == EMULATION_FAILED) {
a6f177ef 4602 if (reexecute_instruction(vcpu, cr2))
c3cd7ffa
GN		 4603 return EMULATE_DONE;
4604
6d77dbfc 4605 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4606 }
4607
da9cb575 4608 if (vcpu->arch.emulate_ctxt.have_exception) {
54b8486f 4609 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 4610 r = EMULATE_DONE;
4611 } else if (vcpu->arch.pio.count) {
3457e419
GN		 4612 if (!vcpu->arch.pio.in)
4613 vcpu->arch.pio.count = 0;
7ae441ea
GN		 4614 else
4615 writeback = false;
e85d28f8 4616 r = EMULATE_DO_MMIO;
7ae441ea
GN		 4617 } else if (vcpu->mmio_needed) {
4618 if (!vcpu->mmio_is_write)
4619 writeback = false;
e85d28f8 4620 r = EMULATE_DO_MMIO;
7ae441ea 4621 } else if (r == EMULATION_RESTART)
5cd21917 4622 goto restart;
d2ddd1c4
GN		 4623 else
4624 r = EMULATE_DONE;
f850e2e6 4625
7ae441ea
GN		 4626 if (writeback) {
4627 toggle_interruptibility(vcpu,
4628 vcpu->arch.emulate_ctxt.interruptibility);
4629 kvm_set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
4630 kvm_make_request(KVM_REQ_EVENT, vcpu);
4631 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
4632 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
4633 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
4634 } else
4635 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 4636
4637 return r;
de7d789a 4638}
51d8b661 4639EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 4640
cf8f70bf 4641int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 4642{
cf8f70bf 4643 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 4644 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
4645 size, port, &val, 1);
cf8f70bf 4646 /* do not return to emulator after return from userspace */
7972995b 4647 vcpu->arch.pio.count = 0;
de7d789a
CO		 4648 return ret;
4649}
cf8f70bf 4650EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 4651
8cfdc000
ZA		 4652static void tsc_bad(void *info)
4653{
0a3aee0d 4654 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 4655}
4656
4657static void tsc_khz_changed(void *data)
c8076604 4658{
8cfdc000
ZA		 4659 struct cpufreq_freqs *freq = data;
4660 unsigned long khz = 0;
4661
4662 if (data)
4663 khz = freq->new;
4664 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4665 khz = cpufreq_quick_get(raw_smp_processor_id());
4666 if (!khz)
4667 khz = tsc_khz;
0a3aee0d 4668 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 4669}
4670
c8076604
GH		 4671static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4672 void *data)
4673{
4674 struct cpufreq_freqs *freq = data;
4675 struct kvm *kvm;
4676 struct kvm_vcpu *vcpu;
4677 int i, send_ipi = 0;
4678
8cfdc000
ZA		 4679 /*
4680 * We allow guests to temporarily run on slowing clocks,
4681 * provided we notify them after, or to run on accelerating
4682 * clocks, provided we notify them before. Thus time never
4683 * goes backwards.
4684 *
4685 * However, we have a problem. We can't atomically update
4686 * the frequency of a given CPU from this function; it is
4687 * merely a notifier, which can be called from any CPU.
4688 * Changing the TSC frequency at arbitrary points in time
4689 * requires a recomputation of local variables related to
4690 * the TSC for each VCPU. We must flag these local variables
4691 * to be updated and be sure the update takes place with the
4692 * new frequency before any guests proceed.
4693 *
4694 * Unfortunately, the combination of hotplug CPU and frequency
4695 * change creates an intractable locking scenario; the order
4696 * of when these callouts happen is undefined with respect to
4697 * CPU hotplug, and they can race with each other. As such,
4698 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
4699 * undefined; you can actually have a CPU frequency change take
4700 * place in between the computation of X and the setting of the
4701 * variable. To protect against this problem, all updates of
4702 * the per_cpu tsc_khz variable are done in an interrupt
4703 * protected IPI, and all callers wishing to update the value
4704 * must wait for a synchronous IPI to complete (which is trivial
4705 * if the caller is on the CPU already). This establishes the
4706 * necessary total order on variable updates.
4707 *
4708 * Note that because a guest time update may take place
4709 * anytime after the setting of the VCPU's request bit, the
4710 * correct TSC value must be set before the request. However,
4711 * to ensure the update actually makes it to any guest which
4712 * starts running in hardware virtualization between the set
4713 * and the acquisition of the spinlock, we must also ping the
4714 * CPU after setting the request bit.
4715 *
4716 */
4717
c8076604
GH		 4718 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
4719 return 0;
4720 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
4721 return 0;
8cfdc000
ZA		 4722
4723 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 4724
e935b837 4725 raw_spin_lock(&kvm_lock);
c8076604 4726 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 4727 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 4728 if (vcpu->cpu != freq->cpu)
4729 continue;
c285545f 4730 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 4731 if (vcpu->cpu != smp_processor_id())
8cfdc000 4732 send_ipi = 1;
c8076604
GH		 4733 }
4734 }
e935b837 4735 raw_spin_unlock(&kvm_lock);
c8076604
GH		 4736
4737 if (freq->old < freq->new && send_ipi) {
4738 /*
4739 * We upscale the frequency. Must make the guest
4740 * doesn't see old kvmclock values while running with
4741 * the new frequency, otherwise we risk the guest sees
4742 * time go backwards.
4743 *
4744 * In case we update the frequency for another cpu
4745 * (which might be in guest context) send an interrupt
4746 * to kick the cpu out of guest context. Next time
4747 * guest context is entered kvmclock will be updated,
4748 * so the guest will not see stale values.
4749 */
8cfdc000 4750 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 4751 }
4752 return 0;
4753}
4754
4755static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 4756 .notifier_call = kvmclock_cpufreq_notifier
4757};
4758
4759static int kvmclock_cpu_notifier(struct notifier_block *nfb,
4760 unsigned long action, void *hcpu)
4761{
4762 unsigned int cpu = (unsigned long)hcpu;
4763
4764 switch (action) {
4765 case CPU_ONLINE:
4766 case CPU_DOWN_FAILED:
4767 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4768 break;
4769 case CPU_DOWN_PREPARE:
4770 smp_call_function_single(cpu, tsc_bad, NULL, 1);
4771 break;
4772 }
4773 return NOTIFY_OK;
4774}
4775
4776static struct notifier_block kvmclock_cpu_notifier_block = {
4777 .notifier_call = kvmclock_cpu_notifier,
4778 .priority = -INT_MAX
c8076604
GH		 4779};
4780
b820cc0c
ZA		 4781static void kvm_timer_init(void)
4782{
4783 int cpu;
4784
c285545f 4785 max_tsc_khz = tsc_khz;
8cfdc000 4786 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 4787 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 4788#ifdef CONFIG_CPU_FREQ
4789 struct cpufreq_policy policy;
4790 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 4791 cpu = get_cpu();
4792 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 4793 if (policy.cpuinfo.max_freq)
4794 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 4795 put_cpu();
c285545f 4796#endif
b820cc0c
ZA		 4797 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4798 CPUFREQ_TRANSITION_NOTIFIER);
4799 }
c285545f 4800 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 4801 for_each_online_cpu(cpu)
4802 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 4803}
4804
ff9d07a0
ZY		 4805static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
4806
4807static int kvm_is_in_guest(void)
4808{
4809 return percpu_read(current_vcpu) != NULL;
4810}
4811
4812static int kvm_is_user_mode(void)
4813{
4814 int user_mode = 3;
dcf46b94 4815
ff9d07a0
ZY		 4816 if (percpu_read(current_vcpu))
4817 user_mode = kvm_x86_ops->get_cpl(percpu_read(current_vcpu));
dcf46b94 4818
ff9d07a0
ZY		 4819 return user_mode != 0;
4820}
4821
4822static unsigned long kvm_get_guest_ip(void)
4823{
4824 unsigned long ip = 0;
dcf46b94 4825
ff9d07a0
ZY		 4826 if (percpu_read(current_vcpu))
4827 ip = kvm_rip_read(percpu_read(current_vcpu));
dcf46b94 4828
ff9d07a0
ZY		 4829 return ip;
4830}
4831
4832static struct perf_guest_info_callbacks kvm_guest_cbs = {
4833 .is_in_guest = kvm_is_in_guest,
4834 .is_user_mode = kvm_is_user_mode,
4835 .get_guest_ip = kvm_get_guest_ip,
4836};
4837
4838void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4839{
4840 percpu_write(current_vcpu, vcpu);
4841}
4842EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4843
4844void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4845{
4846 percpu_write(current_vcpu, NULL);
4847}
4848EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4849
f8c16bba 4850int kvm_arch_init(void *opaque)
043405e1 4851{
b820cc0c 4852 int r;
f8c16bba
ZX		 4853 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4854
f8c16bba
ZX		 4855 if (kvm_x86_ops) {
4856 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 4857 r = -EEXIST;
4858 goto out;
f8c16bba
ZX		 4859 }
4860
4861 if (!ops->cpu_has_kvm_support()) {
4862 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 4863 r = -EOPNOTSUPP;
4864 goto out;
f8c16bba
ZX		 4865 }
4866 if (ops->disabled_by_bios()) {
4867 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 4868 r = -EOPNOTSUPP;
4869 goto out;
f8c16bba
ZX		 4870 }
4871
97db56ce
AK		 4872 r = kvm_mmu_module_init();
4873 if (r)
4874 goto out;
4875
4876 kvm_init_msr_list();
4877
f8c16bba 4878 kvm_x86_ops = ops;
56c6d28a 4879 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e 4880 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 4881 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 4882
b820cc0c 4883 kvm_timer_init();
c8076604 4884
ff9d07a0
ZY		 4885 perf_register_guest_info_callbacks(&kvm_guest_cbs);
4886
2acf923e
DC		 4887 if (cpu_has_xsave)
4888 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
4889
f8c16bba 4890 return 0;
56c6d28a
ZX		 4891
4892out:
56c6d28a 4893 return r;
043405e1 4894}
8776e519 4895
f8c16bba
ZX		 4896void kvm_arch_exit(void)
4897{
ff9d07a0
ZY		 4898 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4899
888d256e
JK		 4900 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4901 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4902 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 4903 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
f8c16bba 4904 kvm_x86_ops = NULL;
56c6d28a
ZX		 4905 kvm_mmu_module_exit();
4906}
f8c16bba 4907
8776e519
HB		 4908int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4909{
4910 ++vcpu->stat.halt_exits;
4911 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 4912 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 4913 return 1;
4914 } else {
4915 vcpu->run->exit_reason = KVM_EXIT_HLT;
4916 return 0;
4917 }
4918}
4919EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4920
2f333bcb
MT		 4921static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
4922 unsigned long a1)
4923{
4924 if (is_long_mode(vcpu))
4925 return a0;
4926 else
4927 return a0 | ((gpa_t)a1 << 32);
4928}
4929
55cd8e5a
GN		 4930int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
4931{
4932 u64 param, ingpa, outgpa, ret;
4933 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
4934 bool fast, longmode;
4935 int cs_db, cs_l;
4936
4937 /*
4938 * hypercall generates UD from non zero cpl and real mode
4939 * per HYPER-V spec
4940 */
3eeb3288 4941 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 4942 kvm_queue_exception(vcpu, UD_VECTOR);
4943 return 0;
4944 }
4945
4946 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4947 longmode = is_long_mode(vcpu) && cs_l == 1;
4948
4949 if (!longmode) {
ccd46936
GN		 4950 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
4951 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
4952 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
4953 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
4954 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
4955 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 4956 }
4957#ifdef CONFIG_X86_64
4958 else {
4959 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
4960 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
4961 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
4962 }
4963#endif
4964
4965 code = param & 0xffff;
4966 fast = (param >> 16) & 0x1;
4967 rep_cnt = (param >> 32) & 0xfff;
4968 rep_idx = (param >> 48) & 0xfff;
4969
4970 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
4971
c25bc163
GN		 4972 switch (code) {
4973 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
4974 kvm_vcpu_on_spin(vcpu);
4975 break;
4976 default:
4977 res = HV_STATUS_INVALID_HYPERCALL_CODE;
4978 break;
4979 }
55cd8e5a
GN		 4980
4981 ret = res | (((u64)rep_done & 0xfff) << 32);
4982 if (longmode) {
4983 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
4984 } else {
4985 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
4986 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
4987 }
4988
4989 return 1;
4990}
4991
8776e519
HB		 4992int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
4993{
4994 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 4995 int r = 1;
8776e519 4996
55cd8e5a
GN		 4997 if (kvm_hv_hypercall_enabled(vcpu->kvm))
4998 return kvm_hv_hypercall(vcpu);
4999
5fdbf976
MT		 5000 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5001 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5002 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5003 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5004 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5005
229456fc 5006 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5007
8776e519
HB		 5008 if (!is_long_mode(vcpu)) {
5009 nr &= 0xFFFFFFFF;
5010 a0 &= 0xFFFFFFFF;
5011 a1 &= 0xFFFFFFFF;
5012 a2 &= 0xFFFFFFFF;
5013 a3 &= 0xFFFFFFFF;
5014 }
5015
07708c4a
JK		 5016 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5017 ret = -KVM_EPERM;
5018 goto out;
5019 }
5020
8776e519 5021 switch (nr) {
b93463aa
AK		 5022 case KVM_HC_VAPIC_POLL_IRQ:
5023 ret = 0;
5024 break;
2f333bcb
MT		 5025 case KVM_HC_MMU_OP:
5026 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
5027 break;
8776e519
HB		 5028 default:
5029 ret = -KVM_ENOSYS;
5030 break;
5031 }
07708c4a 5032out:
5fdbf976 5033 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5034 ++vcpu->stat.hypercalls;
2f333bcb 5035 return r;
8776e519
HB		 5036}
5037EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5038
5039int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
5040{
5041 char instruction[3];
5fdbf976 5042 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5043
8776e519
HB		 5044 /*
5045 * Blow out the MMU to ensure that no other VCPU has an active mapping
5046 * to ensure that the updated hypercall appears atomically across all
5047 * VCPUs.
5048 */
5049 kvm_mmu_zap_all(vcpu->kvm);
5050
8776e519 5051 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5052
0f65dd70
AK		 5053 return emulator_write_emulated(&vcpu->arch.emulate_ctxt,
5054 rip, instruction, 3, NULL);
8776e519
HB		 5055}
5056
07716717
DK		 5057static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
5058{
ad312c7c
ZX		 5059 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
5060 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 5061
5062 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
5063 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 5064 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 5065 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 5066 if (ej->function == e->function) {
5067 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
5068 return j;
5069 }
5070 }
5071 return 0; /* silence gcc, even though control never reaches here */
5072}
5073
5074/* find an entry with matching function, matching index (if needed), and that
5075 * should be read next (if it's stateful) */
5076static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
5077 u32 function, u32 index)
5078{
5079 if (e->function != function)
5080 return 0;
5081 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
5082 return 0;
5083 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 5084 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 5085 return 0;
5086 return 1;
5087}
5088
d8017474
AG		 5089struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
5090 u32 function, u32 index)
8776e519
HB		 5091{
5092 int i;
d8017474 5093 struct kvm_cpuid_entry2 *best = NULL;
8776e519 5094
ad312c7c 5095 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 5096 struct kvm_cpuid_entry2 *e;
5097
ad312c7c 5098 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 5099 if (is_matching_cpuid_entry(e, function, index)) {
5100 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
5101 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 5102 best = e;
5103 break;
5104 }
8776e519 5105 }
d8017474
AG		 5106 return best;
5107}
0e851880 5108EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
d8017474 5109
82725b20
DE		 5110int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
5111{
5112 struct kvm_cpuid_entry2 *best;
5113
f7a71197
AK		 5114 best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0);
5115 if (!best || best->eax < 0x80000008)
5116 goto not_found;
82725b20
DE		 5117 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
5118 if (best)
5119 return best->eax & 0xff;
f7a71197 5120not_found:
82725b20
DE		 5121 return 36;
5122}
5123
bd22f5cf
AP		 5124/*
5125 * If no match is found, check whether we exceed the vCPU's limit
5126 * and return the content of the highest valid _standard_ leaf instead.
5127 * This is to satisfy the CPUID specification.
5128 */
5129static struct kvm_cpuid_entry2* check_cpuid_limit(struct kvm_vcpu *vcpu,
5130 u32 function, u32 index)
5131{
5132 struct kvm_cpuid_entry2 *maxlevel;
5133
5134 maxlevel = kvm_find_cpuid_entry(vcpu, function & 0x80000000, 0);
5135 if (!maxlevel || maxlevel->eax >= function)
5136 return NULL;
5137 if (function & 0x80000000) {
5138 maxlevel = kvm_find_cpuid_entry(vcpu, 0, 0);
5139 if (!maxlevel)
5140 return NULL;
5141 }
5142 return kvm_find_cpuid_entry(vcpu, maxlevel->eax, index);
5143}
5144
d8017474
AG		 5145void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
5146{
5147 u32 function, index;
5148 struct kvm_cpuid_entry2 *best;
5149
5150 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
5151 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5152 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
5153 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
5154 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
5155 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
5156 best = kvm_find_cpuid_entry(vcpu, function, index);
bd22f5cf
AP		 5157
5158 if (!best)
5159 best = check_cpuid_limit(vcpu, function, index);
5160
8776e519 5161 if (best) {
5fdbf976
MT		 5162 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
5163 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
5164 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
5165 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 5166 }
8776e519 5167 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 5168 trace_kvm_cpuid(function,
5169 kvm_register_read(vcpu, VCPU_REGS_RAX),
5170 kvm_register_read(vcpu, VCPU_REGS_RBX),
5171 kvm_register_read(vcpu, VCPU_REGS_RCX),
5172 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 5173}
5174EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 5175
b6c7a5dc
HB		 5176/*
5177 * Check if userspace requested an interrupt window, and that the
5178 * interrupt window is open.
5179 *
5180 * No need to exit to userspace if we already have an interrupt queued.
5181 */
851ba692 5182static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5183{
8061823a 5184 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5185 vcpu->run->request_interrupt_window &&
5df56646 5186 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5187}
5188
851ba692 5189static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5190{
851ba692
AK		 5191 struct kvm_run *kvm_run = vcpu->run;
5192
91586a3b 5193 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5194 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5195 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5196 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5197 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5198 else
b6c7a5dc 5199 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5200 kvm_arch_interrupt_allowed(vcpu) &&
5201 !kvm_cpu_has_interrupt(vcpu) &&
5202 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5203}
5204
b93463aa
AK		 5205static void vapic_enter(struct kvm_vcpu *vcpu)
5206{
5207 struct kvm_lapic *apic = vcpu->arch.apic;
5208 struct page *page;
5209
5210 if (!apic || !apic->vapic_addr)
5211 return;
5212
5213 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 5214
5215 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 5216}
5217
5218static void vapic_exit(struct kvm_vcpu *vcpu)
5219{
5220 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 5221 int idx;
b93463aa
AK		 5222
5223 if (!apic || !apic->vapic_addr)
5224 return;
5225
f656ce01 5226 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 5227 kvm_release_page_dirty(apic->vapic_page);
5228 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 5229 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 5230}
5231
95ba8273
GN		 5232static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5233{
5234 int max_irr, tpr;
5235
5236 if (!kvm_x86_ops->update_cr8_intercept)
5237 return;
5238
88c808fd
AK		 5239 if (!vcpu->arch.apic)
5240 return;
5241
8db3baa2
GN		 5242 if (!vcpu->arch.apic->vapic_addr)
5243 max_irr = kvm_lapic_find_highest_irr(vcpu);
5244 else
5245 max_irr = -1;
95ba8273
GN		 5246
5247 if (max_irr != -1)
5248 max_irr >>= 4;
5249
5250 tpr = kvm_lapic_get_cr8(vcpu);
5251
5252 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5253}
5254
851ba692 5255static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 5256{
5257 /* try to reinject previous events if any */
b59bb7bd 5258 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5259 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5260 vcpu->arch.exception.has_error_code,
5261 vcpu->arch.exception.error_code);
b59bb7bd
GN		 5262 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5263 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5264 vcpu->arch.exception.error_code,
5265 vcpu->arch.exception.reinject);
b59bb7bd
GN		 5266 return;
5267 }
5268
95ba8273
GN		 5269 if (vcpu->arch.nmi_injected) {
5270 kvm_x86_ops->set_nmi(vcpu);
5271 return;
5272 }
5273
5274 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5275 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5276 return;
5277 }
5278
5279 /* try to inject new event if pending */
5280 if (vcpu->arch.nmi_pending) {
5281 if (kvm_x86_ops->nmi_allowed(vcpu)) {
5282 vcpu->arch.nmi_pending = false;
5283 vcpu->arch.nmi_injected = true;
5284 kvm_x86_ops->set_nmi(vcpu);
5285 }
5286 } else if (kvm_cpu_has_interrupt(vcpu)) {
5287 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5288 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5289 false);
5290 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5291 }
5292 }
5293}
5294
2acf923e
DC		 5295static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
5296{
5297 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
5298 !vcpu->guest_xcr0_loaded) {
5299 /* kvm_set_xcr() also depends on this */
5300 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
5301 vcpu->guest_xcr0_loaded = 1;
5302 }
5303}
5304
5305static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
5306{
5307 if (vcpu->guest_xcr0_loaded) {
5308 if (vcpu->arch.xcr0 != host_xcr0)
5309 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
5310 vcpu->guest_xcr0_loaded = 0;
5311 }
5312}
5313
851ba692 5314static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5315{
5316 int r;
1499e54a 5317 bool nmi_pending;
6a8b1d13 5318 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5319 vcpu->run->request_interrupt_window;
b6c7a5dc 5320
3e007509 5321 if (vcpu->requests) {
a8eeb04a 5322 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5323 kvm_mmu_unload(vcpu);
a8eeb04a 5324 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5325 __kvm_migrate_timers(vcpu);
34c238a1
ZA		 5326 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5327 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 5328 if (unlikely(r))
5329 goto out;
5330 }
a8eeb04a 5331 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5332 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5333 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5334 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5335 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5336 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5337 r = 0;
5338 goto out;
5339 }
a8eeb04a 5340 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5341 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5342 r = 0;
5343 goto out;
5344 }
a8eeb04a 5345 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5346 vcpu->fpu_active = 0;
5347 kvm_x86_ops->fpu_deactivate(vcpu);
5348 }
af585b92
GN		 5349 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5350 /* Page is swapped out. Do synthetic halt */
5351 vcpu->arch.apf.halted = true;
5352 r = 1;
5353 goto out;
5354 }
2f52d58c 5355 }
b93463aa 5356
3e007509
AK		 5357 r = kvm_mmu_reload(vcpu);
5358 if (unlikely(r))
5359 goto out;
5360
1499e54a
GN		 5361 /*
5362 * An NMI can be injected between local nmi_pending read and
5363 * vcpu->arch.nmi_pending read inside inject_pending_event().
5364 * But in that case, KVM_REQ_EVENT will be set, which makes
5365 * the race described above benign.
5366 */
5367 nmi_pending = ACCESS_ONCE(vcpu->arch.nmi_pending);
5368
b463a6f7
AK		 5369 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5370 inject_pending_event(vcpu);
5371
5372 /* enable NMI/IRQ window open exits if needed */
1499e54a 5373 if (nmi_pending)
b463a6f7
AK		 5374 kvm_x86_ops->enable_nmi_window(vcpu);
5375 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
5376 kvm_x86_ops->enable_irq_window(vcpu);
5377
5378 if (kvm_lapic_enabled(vcpu)) {
5379 update_cr8_intercept(vcpu);
5380 kvm_lapic_sync_to_vapic(vcpu);
5381 }
5382 }
5383
b6c7a5dc
HB		 5384 preempt_disable();
5385
5386 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 5387 if (vcpu->fpu_active)
5388 kvm_load_guest_fpu(vcpu);
2acf923e 5389 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 5390
6b7e2d09
XG		 5391 vcpu->mode = IN_GUEST_MODE;
5392
5393 /* We should set ->mode before check ->requests,
5394 * see the comment in make_all_cpus_request.
5395 */
5396 smp_mb();
b6c7a5dc 5397
d94e1dc9 5398 local_irq_disable();
32f88400 5399
6b7e2d09 5400 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 5401 || need_resched() || signal_pending(current)) {
6b7e2d09 5402 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5403 smp_wmb();
6c142801
AK		 5404 local_irq_enable();
5405 preempt_enable();
b463a6f7 5406 kvm_x86_ops->cancel_injection(vcpu);
6c142801
AK		 5407 r = 1;
5408 goto out;
5409 }
5410
f656ce01 5411 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 5412
b6c7a5dc
HB		 5413 kvm_guest_enter();
5414
42dbaa5a 5415 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 5416 set_debugreg(0, 7);
5417 set_debugreg(vcpu->arch.eff_db[0], 0);
5418 set_debugreg(vcpu->arch.eff_db[1], 1);
5419 set_debugreg(vcpu->arch.eff_db[2], 2);
5420 set_debugreg(vcpu->arch.eff_db[3], 3);
5421 }
b6c7a5dc 5422
229456fc 5423 trace_kvm_entry(vcpu->vcpu_id);
851ba692 5424 kvm_x86_ops->run(vcpu);
b6c7a5dc 5425
24f1e32c
FW		 5426 /*
5427 * If the guest has used debug registers, at least dr7
5428 * will be disabled while returning to the host.
5429 * If we don't have active breakpoints in the host, we don't
5430 * care about the messed up debug address registers. But if
5431 * we have some of them active, restore the old state.
5432 */
59d8eb53 5433 if (hw_breakpoint_active())
24f1e32c 5434 hw_breakpoint_restore();
42dbaa5a 5435
1d5f066e
ZA		 5436 kvm_get_msr(vcpu, MSR_IA32_TSC, &vcpu->arch.last_guest_tsc);
5437
6b7e2d09 5438 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5439 smp_wmb();
b6c7a5dc
HB		 5440 local_irq_enable();
5441
5442 ++vcpu->stat.exits;
5443
5444 /*
5445 * We must have an instruction between local_irq_enable() and
5446 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5447 * the interrupt shadow. The stat.exits increment will do nicely.
5448 * But we need to prevent reordering, hence this barrier():
5449 */
5450 barrier();
5451
5452 kvm_guest_exit();
5453
5454 preempt_enable();
5455
f656ce01 5456 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 5457
b6c7a5dc
HB		 5458 /*
5459 * Profile KVM exit RIPs:
5460 */
5461 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 5462 unsigned long rip = kvm_rip_read(vcpu);
5463 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 5464 }
5465
298101da 5466
b93463aa
AK		 5467 kvm_lapic_sync_from_vapic(vcpu);
5468
851ba692 5469 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 5470out:
5471 return r;
5472}
b6c7a5dc 5473
09cec754 5474
851ba692 5475static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 5476{
5477 int r;
f656ce01 5478 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 5479
5480 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 5481 pr_debug("vcpu %d received sipi with vector # %x\n",
5482 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 5483 kvm_lapic_reset(vcpu);
5f179287 5484 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 5485 if (r)
5486 return r;
5487 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 5488 }
5489
f656ce01 5490 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 5491 vapic_enter(vcpu);
5492
5493 r = 1;
5494 while (r > 0) {
af585b92
GN		 5495 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
5496 !vcpu->arch.apf.halted)
851ba692 5497 r = vcpu_enter_guest(vcpu);
d7690175 5498 else {
f656ce01 5499 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 5500 kvm_vcpu_block(vcpu);
f656ce01 5501 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
a8eeb04a 5502 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
09cec754
GN		 5503 {
5504 switch(vcpu->arch.mp_state) {
5505 case KVM_MP_STATE_HALTED:
d7690175 5506 vcpu->arch.mp_state =
09cec754
GN		 5507 KVM_MP_STATE_RUNNABLE;
5508 case KVM_MP_STATE_RUNNABLE:
af585b92 5509 vcpu->arch.apf.halted = false;
09cec754
GN		 5510 break;
5511 case KVM_MP_STATE_SIPI_RECEIVED:
5512 default:
5513 r = -EINTR;
5514 break;
5515 }
5516 }
d7690175
MT		 5517 }
5518
09cec754
GN		 5519 if (r <= 0)
5520 break;
5521
5522 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5523 if (kvm_cpu_has_pending_timer(vcpu))
5524 kvm_inject_pending_timer_irqs(vcpu);
5525
851ba692 5526 if (dm_request_for_irq_injection(vcpu)) {
09cec754 5527 r = -EINTR;
851ba692 5528 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5529 ++vcpu->stat.request_irq_exits;
5530 }
af585b92
GN		 5531
5532 kvm_check_async_pf_completion(vcpu);
5533
09cec754
GN		 5534 if (signal_pending(current)) {
5535 r = -EINTR;
851ba692 5536 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5537 ++vcpu->stat.signal_exits;
5538 }
5539 if (need_resched()) {
f656ce01 5540 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 5541 kvm_resched(vcpu);
f656ce01 5542 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 5543 }
b6c7a5dc
HB		 5544 }
5545
f656ce01 5546 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 5547
b93463aa
AK		 5548 vapic_exit(vcpu);
5549
b6c7a5dc
HB		 5550 return r;
5551}
5552
5287f194
AK		 5553static int complete_mmio(struct kvm_vcpu *vcpu)
5554{
5555 struct kvm_run *run = vcpu->run;
5556 int r;
5557
5558 if (!(vcpu->arch.pio.count || vcpu->mmio_needed))
5559 return 1;
5560
5561 if (vcpu->mmio_needed) {
5287f194 5562 vcpu->mmio_needed = 0;
cef4dea0
AK		 5563 if (!vcpu->mmio_is_write)
5564 memcpy(vcpu->mmio_data, run->mmio.data, 8);
5565 vcpu->mmio_index += 8;
5566 if (vcpu->mmio_index < vcpu->mmio_size) {
5567 run->exit_reason = KVM_EXIT_MMIO;
5568 run->mmio.phys_addr = vcpu->mmio_phys_addr + vcpu->mmio_index;
5569 memcpy(run->mmio.data, vcpu->mmio_data + vcpu->mmio_index, 8);
5570 run->mmio.len = min(vcpu->mmio_size - vcpu->mmio_index, 8);
5571 run->mmio.is_write = vcpu->mmio_is_write;
5572 vcpu->mmio_needed = 1;
5573 return 0;
5574 }
5575 if (vcpu->mmio_is_write)
5576 return 1;
5577 vcpu->mmio_read_completed = 1;
5287f194
AK		 5578 }
5579 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5580 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
5581 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5582 if (r != EMULATE_DONE)
5583 return 0;
5584 return 1;
5585}
5586
b6c7a5dc
HB		 5587int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
5588{
5589 int r;
5590 sigset_t sigsaved;
5591
e5c30142
AK		 5592 if (!tsk_used_math(current) && init_fpu(current))
5593 return -ENOMEM;
5594
ac9f6dc0
AK		 5595 if (vcpu->sigset_active)
5596 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
5597
a4535290 5598 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 5599 kvm_vcpu_block(vcpu);
d7690175 5600 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 5601 r = -EAGAIN;
5602 goto out;
b6c7a5dc
HB		 5603 }
5604
b6c7a5dc 5605 /* re-sync apic's tpr */
eea1cff9
AP		 5606 if (!irqchip_in_kernel(vcpu->kvm)) {
5607 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
5608 r = -EINVAL;
5609 goto out;
5610 }
5611 }
b6c7a5dc 5612
5287f194
AK		 5613 r = complete_mmio(vcpu);
5614 if (r <= 0)
5615 goto out;
5616
5fdbf976
MT		 5617 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
5618 kvm_register_write(vcpu, VCPU_REGS_RAX,
5619 kvm_run->hypercall.ret);
b6c7a5dc 5620
851ba692 5621 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 5622
5623out:
f1d86e46 5624 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 5625 if (vcpu->sigset_active)
5626 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
5627
b6c7a5dc
HB		 5628 return r;
5629}
5630
5631int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5632{
7ae441ea
GN		 5633 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
5634 /*
5635 * We are here if userspace calls get_regs() in the middle of
5636 * instruction emulation. Registers state needs to be copied
5637 * back from emulation context to vcpu. Usrapace shouldn't do
5638 * that usually, but some bad designed PV devices (vmware
5639 * backdoor interface) need this to work
5640 */
5641 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
5642 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
5643 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5644 }
5fdbf976
MT		 5645 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5646 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5647 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5648 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5649 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
5650 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
5651 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5652 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 5653#ifdef CONFIG_X86_64
5fdbf976
MT		 5654 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
5655 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
5656 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
5657 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
5658 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
5659 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
5660 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
5661 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 5662#endif
5663
5fdbf976 5664 regs->rip = kvm_rip_read(vcpu);
91586a3b 5665 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 5666
b6c7a5dc
HB		 5667 return 0;
5668}
5669
5670int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5671{
7ae441ea
GN		 5672 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
5673 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5674
5fdbf976
MT		 5675 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
5676 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
5677 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
5678 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
5679 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
5680 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
5681 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
5682 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 5683#ifdef CONFIG_X86_64
5fdbf976
MT		 5684 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
5685 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
5686 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
5687 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
5688 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
5689 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
5690 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
5691 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 5692#endif
5693
5fdbf976 5694 kvm_rip_write(vcpu, regs->rip);
91586a3b 5695 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 5696
b4f14abd
JK		 5697 vcpu->arch.exception.pending = false;
5698
3842d135
AK		 5699 kvm_make_request(KVM_REQ_EVENT, vcpu);
5700
b6c7a5dc
HB		 5701 return 0;
5702}
5703
b6c7a5dc
HB		 5704void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5705{
5706 struct kvm_segment cs;
5707
3e6e0aab 5708 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 5709 *db = cs.db;
5710 *l = cs.l;
5711}
5712EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
5713
5714int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
5715 struct kvm_sregs *sregs)
5716{
89a27f4d 5717 struct desc_ptr dt;
b6c7a5dc 5718
3e6e0aab
GT		 5719 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5720 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5721 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5722 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5723 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5724 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5725
3e6e0aab
GT		 5726 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5727 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 5728
5729 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 5730 sregs->idt.limit = dt.size;
5731 sregs->idt.base = dt.address;
b6c7a5dc 5732 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 5733 sregs->gdt.limit = dt.size;
5734 sregs->gdt.base = dt.address;
b6c7a5dc 5735
4d4ec087 5736 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 5737 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 5738 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 5739 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 5740 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 5741 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 5742 sregs->apic_base = kvm_get_apic_base(vcpu);
5743
923c61bb 5744 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 5745
36752c9b 5746 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 5747 set_bit(vcpu->arch.interrupt.nr,
5748 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 5749
b6c7a5dc
HB		 5750 return 0;
5751}
5752
62d9f0db
MT		 5753int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
5754 struct kvm_mp_state *mp_state)
5755{
62d9f0db 5756 mp_state->mp_state = vcpu->arch.mp_state;
62d9f0db
MT		 5757 return 0;
5758}
5759
5760int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
5761 struct kvm_mp_state *mp_state)
5762{
62d9f0db 5763 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 5764 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 5765 return 0;
5766}
5767
e269fb21
JK		 5768int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason,
5769 bool has_error_code, u32 error_code)
b6c7a5dc 5770{
4d2179e1 5771 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
8ec4722d 5772 int ret;
e01c2426 5773
8ec4722d 5774 init_emulate_ctxt(vcpu);
c697518a 5775
9aabc88f 5776 ret = emulator_task_switch(&vcpu->arch.emulate_ctxt,
e269fb21
JK		 5777 tss_selector, reason, has_error_code,
5778 error_code);
c697518a 5779
c697518a 5780 if (ret)
19d04437 5781 return EMULATE_FAIL;
37817f29 5782
4d2179e1 5783 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
95c55886 5784 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
f6e78475 5785 kvm_set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
3842d135 5786 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 5787 return EMULATE_DONE;
37817f29
IE		 5788}
5789EXPORT_SYMBOL_GPL(kvm_task_switch);
5790
b6c7a5dc
HB		 5791int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5792 struct kvm_sregs *sregs)
5793{
5794 int mmu_reset_needed = 0;
63f42e02 5795 int pending_vec, max_bits, idx;
89a27f4d 5796 struct desc_ptr dt;
b6c7a5dc 5797
89a27f4d
GN		 5798 dt.size = sregs->idt.limit;
5799 dt.address = sregs->idt.base;
b6c7a5dc 5800 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 5801 dt.size = sregs->gdt.limit;
5802 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 5803 kvm_x86_ops->set_gdt(vcpu, &dt);
5804
ad312c7c 5805 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 5806 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 5807 vcpu->arch.cr3 = sregs->cr3;
aff48baa 5808 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 5809
2d3ad1f4 5810 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 5811
f6801dff 5812 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 5813 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 5814 kvm_set_apic_base(vcpu, sregs->apic_base);
5815
4d4ec087 5816 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 5817 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 5818 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 5819
fc78f519 5820 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 5821 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c
SY		 5822 if (sregs->cr4 & X86_CR4_OSXSAVE)
5823 update_cpuid(vcpu);
63f42e02
XG		 5824
5825 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 5826 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 5827 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 5828 mmu_reset_needed = 1;
5829 }
63f42e02 5830 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 5831
5832 if (mmu_reset_needed)
5833 kvm_mmu_reset_context(vcpu);
5834
923c61bb
GN		 5835 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5836 pending_vec = find_first_bit(
5837 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5838 if (pending_vec < max_bits) {
66fd3f7f 5839 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 5840 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 5841 }
5842
3e6e0aab
GT		 5843 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5844 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5845 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5846 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5847 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5848 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5849
3e6e0aab
GT		 5850 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5851 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 5852
5f0269f5
ME		 5853 update_cr8_intercept(vcpu);
5854
9c3e4aab 5855 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 5856 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 5857 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 5858 !is_protmode(vcpu))
9c3e4aab
MT		 5859 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5860
3842d135
AK		 5861 kvm_make_request(KVM_REQ_EVENT, vcpu);
5862
b6c7a5dc
HB		 5863 return 0;
5864}
5865
d0bfb940
JK		 5866int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5867 struct kvm_guest_debug *dbg)
b6c7a5dc 5868{
355be0b9 5869 unsigned long rflags;
ae675ef0 5870 int i, r;
b6c7a5dc 5871
4f926bf2
JK		 5872 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5873 r = -EBUSY;
5874 if (vcpu->arch.exception.pending)
2122ff5e 5875 goto out;
4f926bf2
JK		 5876 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5877 kvm_queue_exception(vcpu, DB_VECTOR);
5878 else
5879 kvm_queue_exception(vcpu, BP_VECTOR);
5880 }
5881
91586a3b
JK		 5882 /*
5883 * Read rflags as long as potentially injected trace flags are still
5884 * filtered out.
5885 */
5886 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 5887
5888 vcpu->guest_debug = dbg->control;
5889 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5890 vcpu->guest_debug = 0;
5891
5892 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 5893 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5894 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5895 vcpu->arch.switch_db_regs =
5896 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5897 } else {
5898 for (i = 0; i < KVM_NR_DB_REGS; i++)
5899 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5900 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5901 }
5902
f92653ee
JK		 5903 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5904 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5905 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 5906
91586a3b
JK		 5907 /*
5908 * Trigger an rflags update that will inject or remove the trace
5909 * flags.
5910 */
5911 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 5912
355be0b9 5913 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 5914
4f926bf2 5915 r = 0;
d0bfb940 5916
2122ff5e 5917out:
b6c7a5dc
HB		 5918
5919 return r;
5920}
5921
8b006791
ZX		 5922/*
5923 * Translate a guest virtual address to a guest physical address.
5924 */
5925int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5926 struct kvm_translation *tr)
5927{
5928 unsigned long vaddr = tr->linear_address;
5929 gpa_t gpa;
f656ce01 5930 int idx;
8b006791 5931
f656ce01 5932 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 5933 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 5934 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 5935 tr->physical_address = gpa;
5936 tr->valid = gpa != UNMAPPED_GVA;
5937 tr->writeable = 1;
5938 tr->usermode = 0;
8b006791
ZX		 5939
5940 return 0;
5941}
5942
d0752060
HB		 5943int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5944{
98918833
SY		 5945 struct i387_fxsave_struct *fxsave =
5946 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5947
d0752060
HB		 5948 memcpy(fpu->fpr, fxsave->st_space, 128);
5949 fpu->fcw = fxsave->cwd;
5950 fpu->fsw = fxsave->swd;
5951 fpu->ftwx = fxsave->twd;
5952 fpu->last_opcode = fxsave->fop;
5953 fpu->last_ip = fxsave->rip;
5954 fpu->last_dp = fxsave->rdp;
5955 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5956
d0752060
HB		 5957 return 0;
5958}
5959
5960int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5961{
98918833
SY		 5962 struct i387_fxsave_struct *fxsave =
5963 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5964
d0752060
HB		 5965 memcpy(fxsave->st_space, fpu->fpr, 128);
5966 fxsave->cwd = fpu->fcw;
5967 fxsave->swd = fpu->fsw;
5968 fxsave->twd = fpu->ftwx;
5969 fxsave->fop = fpu->last_opcode;
5970 fxsave->rip = fpu->last_ip;
5971 fxsave->rdp = fpu->last_dp;
5972 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
5973
d0752060
HB		 5974 return 0;
5975}
5976
10ab25cd 5977int fx_init(struct kvm_vcpu *vcpu)
d0752060 5978{
10ab25cd
JK		 5979 int err;
5980
5981 err = fpu_alloc(&vcpu->arch.guest_fpu);
5982 if (err)
5983 return err;
5984
98918833 5985 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 5986
2acf923e
DC		 5987 /*
5988 * Ensure guest xcr0 is valid for loading
5989 */
5990 vcpu->arch.xcr0 = XSTATE_FP;
5991
ad312c7c 5992 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 5993
5994 return 0;
d0752060
HB		 5995}
5996EXPORT_SYMBOL_GPL(fx_init);
5997
98918833
SY		 5998static void fx_free(struct kvm_vcpu *vcpu)
5999{
6000 fpu_free(&vcpu->arch.guest_fpu);
6001}
6002
d0752060
HB		 6003void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6004{
2608d7a1 6005 if (vcpu->guest_fpu_loaded)
d0752060
HB		 6006 return;
6007
2acf923e
DC		 6008 /*
6009 * Restore all possible states in the guest,
6010 * and assume host would use all available bits.
6011 * Guest xcr0 would be loaded later.
6012 */
6013 kvm_put_guest_xcr0(vcpu);
d0752060 6014 vcpu->guest_fpu_loaded = 1;
7cf30855 6015 unlazy_fpu(current);
98918833 6016 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 6017 trace_kvm_fpu(1);
d0752060 6018}
d0752060
HB		 6019
6020void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6021{
2acf923e
DC		 6022 kvm_put_guest_xcr0(vcpu);
6023
d0752060
HB		 6024 if (!vcpu->guest_fpu_loaded)
6025 return;
6026
6027 vcpu->guest_fpu_loaded = 0;
98918833 6028 fpu_save_init(&vcpu->arch.guest_fpu);
f096ed85 6029 ++vcpu->stat.fpu_reload;
a8eeb04a 6030 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 6031 trace_kvm_fpu(0);
d0752060 6032}
e9b11c17
ZX		 6033
6034void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6035{
12f9a48f 6036 kvmclock_reset(vcpu);
7f1ea208 6037
f5f48ee1 6038 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 6039 fx_free(vcpu);
e9b11c17
ZX		 6040 kvm_x86_ops->vcpu_free(vcpu);
6041}
6042
6043struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6044 unsigned int id)
6045{
6755bae8
ZA		 6046 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6047 printk_once(KERN_WARNING
6048 "kvm: SMP vm created on host with unstable TSC; "
6049 "guest TSC will not be reliable\n");
26e5215f
AK		 6050 return kvm_x86_ops->vcpu_create(kvm, id);
6051}
e9b11c17 6052
26e5215f
AK		 6053int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6054{
6055 int r;
e9b11c17 6056
0bed3b56 6057 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 6058 vcpu_load(vcpu);
6059 r = kvm_arch_vcpu_reset(vcpu);
6060 if (r == 0)
6061 r = kvm_mmu_setup(vcpu);
6062 vcpu_put(vcpu);
6063 if (r < 0)
6064 goto free_vcpu;
6065
26e5215f 6066 return 0;
e9b11c17
ZX		 6067free_vcpu:
6068 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 6069 return r;
e9b11c17
ZX		 6070}
6071
d40ccc62 6072void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 6073{
344d9588
GN		 6074 vcpu->arch.apf.msr_val = 0;
6075
e9b11c17
ZX		 6076 vcpu_load(vcpu);
6077 kvm_mmu_unload(vcpu);
6078 vcpu_put(vcpu);
6079
98918833 6080 fx_free(vcpu);
e9b11c17
ZX		 6081 kvm_x86_ops->vcpu_free(vcpu);
6082}
6083
6084int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
6085{
448fa4a9
JK		 6086 vcpu->arch.nmi_pending = false;
6087 vcpu->arch.nmi_injected = false;
6088
42dbaa5a
JK		 6089 vcpu->arch.switch_db_regs = 0;
6090 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6091 vcpu->arch.dr6 = DR6_FIXED_1;
6092 vcpu->arch.dr7 = DR7_FIXED_1;
6093
3842d135 6094 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 6095 vcpu->arch.apf.msr_val = 0;
3842d135 6096
12f9a48f
GC		 6097 kvmclock_reset(vcpu);
6098
af585b92
GN		 6099 kvm_clear_async_pf_completion_queue(vcpu);
6100 kvm_async_pf_hash_reset(vcpu);
6101 vcpu->arch.apf.halted = false;
3842d135 6102
e9b11c17
ZX		 6103 return kvm_x86_ops->vcpu_reset(vcpu);
6104}
6105
10474ae8 6106int kvm_arch_hardware_enable(void *garbage)
e9b11c17 6107{
ca84d1a2
ZA		 6108 struct kvm *kvm;
6109 struct kvm_vcpu *vcpu;
6110 int i;
18863bdd
AK		 6111
6112 kvm_shared_msr_cpu_online();
ca84d1a2
ZA		 6113 list_for_each_entry(kvm, &vm_list, vm_list)
6114 kvm_for_each_vcpu(i, vcpu, kvm)
6115 if (vcpu->cpu == smp_processor_id())
c285545f 6116 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
10474ae8 6117 return kvm_x86_ops->hardware_enable(garbage);
e9b11c17
ZX		 6118}
6119
6120void kvm_arch_hardware_disable(void *garbage)
6121{
6122 kvm_x86_ops->hardware_disable(garbage);
3548bab5 6123 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 6124}
6125
6126int kvm_arch_hardware_setup(void)
6127{
6128 return kvm_x86_ops->hardware_setup();
6129}
6130
6131void kvm_arch_hardware_unsetup(void)
6132{
6133 kvm_x86_ops->hardware_unsetup();
6134}
6135
6136void kvm_arch_check_processor_compat(void *rtn)
6137{
6138 kvm_x86_ops->check_processor_compatibility(rtn);
6139}
6140
6141int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6142{
6143 struct page *page;
6144 struct kvm *kvm;
6145 int r;
6146
6147 BUG_ON(vcpu->kvm == NULL);
6148 kvm = vcpu->kvm;
6149
9aabc88f 6150 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
14dfe855 6151 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
ad312c7c 6152 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c30a358d 6153 vcpu->arch.mmu.translate_gpa = translate_gpa;
02f59dc9 6154 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
c5af89b6 6155 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 6156 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 6157 else
a4535290 6158 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 6159
6160 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6161 if (!page) {
6162 r = -ENOMEM;
6163 goto fail;
6164 }
ad312c7c 6165 vcpu->arch.pio_data = page_address(page);
e9b11c17 6166
1e993611 6167 kvm_init_tsc_catchup(vcpu, max_tsc_khz);
c285545f 6168
e9b11c17
ZX		 6169 r = kvm_mmu_create(vcpu);
6170 if (r < 0)
6171 goto fail_free_pio_data;
6172
6173 if (irqchip_in_kernel(kvm)) {
6174 r = kvm_create_lapic(vcpu);
6175 if (r < 0)
6176 goto fail_mmu_destroy;
6177 }
6178
890ca9ae
HY		 6179 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6180 GFP_KERNEL);
6181 if (!vcpu->arch.mce_banks) {
6182 r = -ENOMEM;
443c39bc 6183 goto fail_free_lapic;
890ca9ae
HY		 6184 }
6185 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6186
f5f48ee1
SY		 6187 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
6188 goto fail_free_mce_banks;
6189
af585b92
GN		 6190 kvm_async_pf_hash_reset(vcpu);
6191
e9b11c17 6192 return 0;
f5f48ee1
SY		 6193fail_free_mce_banks:
6194 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 6195fail_free_lapic:
6196 kvm_free_lapic(vcpu);
e9b11c17
ZX		 6197fail_mmu_destroy:
6198 kvm_mmu_destroy(vcpu);
6199fail_free_pio_data:
ad312c7c 6200 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 6201fail:
6202 return r;
6203}
6204
6205void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6206{
f656ce01
MT		 6207 int idx;
6208
36cb93fd 6209 kfree(vcpu->arch.mce_banks);
e9b11c17 6210 kvm_free_lapic(vcpu);
f656ce01 6211 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 6212 kvm_mmu_destroy(vcpu);
f656ce01 6213 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 6214 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 6215}
d19a9cd2 6216
d89f5eff 6217int kvm_arch_init_vm(struct kvm *kvm)
d19a9cd2 6218{
f05e70ac 6219 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 6220 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 6221
5550af4d
SY		 6222 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
6223 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
6224
038f8c11 6225 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
53f658b3 6226
d89f5eff 6227 return 0;
d19a9cd2
ZX		 6228}
6229
6230static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
6231{
6232 vcpu_load(vcpu);
6233 kvm_mmu_unload(vcpu);
6234 vcpu_put(vcpu);
6235}
6236
6237static void kvm_free_vcpus(struct kvm *kvm)
6238{
6239 unsigned int i;
988a2cae 6240 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 6241
6242 /*
6243 * Unpin any mmu pages first.
6244 */
af585b92
GN		 6245 kvm_for_each_vcpu(i, vcpu, kvm) {
6246 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 6247 kvm_unload_vcpu_mmu(vcpu);
af585b92 6248 }
988a2cae
GN		 6249 kvm_for_each_vcpu(i, vcpu, kvm)
6250 kvm_arch_vcpu_free(vcpu);
6251
6252 mutex_lock(&kvm->lock);
6253 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
6254 kvm->vcpus[i] = NULL;
d19a9cd2 6255
988a2cae
GN		 6256 atomic_set(&kvm->online_vcpus, 0);
6257 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 6258}
6259
ad8ba2cd
SY		 6260void kvm_arch_sync_events(struct kvm *kvm)
6261{
ba4cef31 6262 kvm_free_all_assigned_devices(kvm);
aea924f6 6263 kvm_free_pit(kvm);
ad8ba2cd
SY		 6264}
6265
d19a9cd2
ZX		 6266void kvm_arch_destroy_vm(struct kvm *kvm)
6267{
6eb55818 6268 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 6269 kfree(kvm->arch.vpic);
6270 kfree(kvm->arch.vioapic);
d19a9cd2 6271 kvm_free_vcpus(kvm);
3d45830c
AK		 6272 if (kvm->arch.apic_access_page)
6273 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 6274 if (kvm->arch.ept_identity_pagetable)
6275 put_page(kvm->arch.ept_identity_pagetable);
d19a9cd2 6276}
0de10343 6277
f7784b8e
MT		 6278int kvm_arch_prepare_memory_region(struct kvm *kvm,
6279 struct kvm_memory_slot *memslot,
0de10343 6280 struct kvm_memory_slot old,
f7784b8e 6281 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 6282 int user_alloc)
6283{
f7784b8e 6284 int npages = memslot->npages;
7ac77099
AK		 6285 int map_flags = MAP_PRIVATE | MAP_ANONYMOUS;
6286
6287 /* Prevent internal slot pages from being moved by fork()/COW. */
6288 if (memslot->id >= KVM_MEMORY_SLOTS)
6289 map_flags = MAP_SHARED | MAP_ANONYMOUS;
0de10343
ZX		 6290
6291 /*To keep backward compatibility with older userspace,
6292 *x86 needs to hanlde !user_alloc case.
6293 */
6294 if (!user_alloc) {
6295 if (npages && !old.rmap) {
604b38ac
AA		 6296 unsigned long userspace_addr;
6297
72dc67a6 6298 down_write(&current->mm->mmap_sem);
604b38ac
AA		 6299 userspace_addr = do_mmap(NULL, 0,
6300 npages * PAGE_SIZE,
6301 PROT_READ | PROT_WRITE,
7ac77099 6302 map_flags,
604b38ac 6303 0);
72dc67a6 6304 up_write(&current->mm->mmap_sem);
0de10343 6305
604b38ac
AA		 6306 if (IS_ERR((void *)userspace_addr))
6307 return PTR_ERR((void *)userspace_addr);
6308
604b38ac 6309 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 6310 }
6311 }
6312
f7784b8e
MT		 6313
6314 return 0;
6315}
6316
6317void kvm_arch_commit_memory_region(struct kvm *kvm,
6318 struct kvm_userspace_memory_region *mem,
6319 struct kvm_memory_slot old,
6320 int user_alloc)
6321{
6322
48c0e4e9 6323 int nr_mmu_pages = 0, npages = mem->memory_size >> PAGE_SHIFT;
f7784b8e
MT		 6324
6325 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
6326 int ret;
6327
6328 down_write(&current->mm->mmap_sem);
6329 ret = do_munmap(current->mm, old.userspace_addr,
6330 old.npages * PAGE_SIZE);
6331 up_write(&current->mm->mmap_sem);
6332 if (ret < 0)
6333 printk(KERN_WARNING
6334 "kvm_vm_ioctl_set_memory_region: "
6335 "failed to munmap memory\n");
6336 }
6337
48c0e4e9
XG		 6338 if (!kvm->arch.n_requested_mmu_pages)
6339 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
6340
7c8a83b7 6341 spin_lock(&kvm->mmu_lock);
48c0e4e9 6342 if (nr_mmu_pages)
0de10343 6343 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
0de10343 6344 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 6345 spin_unlock(&kvm->mmu_lock);
0de10343 6346}
1d737c8a 6347
34d4cb8f
MT		 6348void kvm_arch_flush_shadow(struct kvm *kvm)
6349{
6350 kvm_mmu_zap_all(kvm);
8986ecc0 6351 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 6352}
6353
1d737c8a
ZX		 6354int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
6355{
af585b92
GN		 6356 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6357 !vcpu->arch.apf.halted)
6358 || !list_empty_careful(&vcpu->async_pf.done)
a1b37100
GN		 6359 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
6360 || vcpu->arch.nmi_pending ||
6361 (kvm_arch_interrupt_allowed(vcpu) &&
6362 kvm_cpu_has_interrupt(vcpu));
1d737c8a 6363}
5736199a 6364
5736199a
ZX		 6365void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
6366{
32f88400
MT		 6367 int me;
6368 int cpu = vcpu->cpu;
5736199a
ZX		 6369
6370 if (waitqueue_active(&vcpu->wq)) {
6371 wake_up_interruptible(&vcpu->wq);
6372 ++vcpu->stat.halt_wakeup;
6373 }
32f88400
MT		 6374
6375 me = get_cpu();
6376 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
6b7e2d09 6377 if (kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE)
32f88400 6378 smp_send_reschedule(cpu);
e9571ed5 6379 put_cpu();
5736199a 6380}
78646121
GN		 6381
6382int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
6383{
6384 return kvm_x86_ops->interrupt_allowed(vcpu);
6385}
229456fc 6386
f92653ee
JK		 6387bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
6388{
6389 unsigned long current_rip = kvm_rip_read(vcpu) +
6390 get_segment_base(vcpu, VCPU_SREG_CS);
6391
6392 return current_rip == linear_rip;
6393}
6394EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
6395
94fe45da
JK		 6396unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
6397{
6398 unsigned long rflags;
6399
6400 rflags = kvm_x86_ops->get_rflags(vcpu);
6401 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 6402 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 6403 return rflags;
6404}
6405EXPORT_SYMBOL_GPL(kvm_get_rflags);
6406
6407void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
6408{
6409 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 6410 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 6411 rflags |= X86_EFLAGS_TF;
94fe45da 6412 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 6413 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 6414}
6415EXPORT_SYMBOL_GPL(kvm_set_rflags);
6416
56028d08
GN		 6417void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
6418{
6419 int r;
6420
fb67e14f 6421 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
c4806acd 6422 is_error_page(work->page))
56028d08
GN		 6423 return;
6424
6425 r = kvm_mmu_reload(vcpu);
6426 if (unlikely(r))
6427 return;
6428
fb67e14f
XG		 6429 if (!vcpu->arch.mmu.direct_map &&
6430 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
6431 return;
6432
56028d08
GN		 6433 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
6434}
6435
af585b92
GN		 6436static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
6437{
6438 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
6439}
6440
6441static inline u32 kvm_async_pf_next_probe(u32 key)
6442{
6443 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
6444}
6445
6446static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6447{
6448 u32 key = kvm_async_pf_hash_fn(gfn);
6449
6450 while (vcpu->arch.apf.gfns[key] != ~0)
6451 key = kvm_async_pf_next_probe(key);
6452
6453 vcpu->arch.apf.gfns[key] = gfn;
6454}
6455
6456static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
6457{
6458 int i;
6459 u32 key = kvm_async_pf_hash_fn(gfn);
6460
6461 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 6462 (vcpu->arch.apf.gfns[key] != gfn &&
6463 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 6464 key = kvm_async_pf_next_probe(key);
6465
6466 return key;
6467}
6468
6469bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6470{
6471 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
6472}
6473
6474static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6475{
6476 u32 i, j, k;
6477
6478 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
6479 while (true) {
6480 vcpu->arch.apf.gfns[i] = ~0;
6481 do {
6482 j = kvm_async_pf_next_probe(j);
6483 if (vcpu->arch.apf.gfns[j] == ~0)
6484 return;
6485 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
6486 /*
6487 * k lies cyclically in ]i,j]
6488 * | i.k.j |
6489 * |....j i.k.| or |.k..j i...|
6490 */
6491 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
6492 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
6493 i = j;
6494 }
6495}
6496
7c90705b
GN		 6497static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
6498{
6499
6500 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
6501 sizeof(val));
6502}
6503
af585b92
GN		 6504void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
6505 struct kvm_async_pf *work)
6506{
6389ee94
AK		 6507 struct x86_exception fault;
6508
7c90705b 6509 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 6510 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 6511
6512 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 6513 (vcpu->arch.apf.send_user_only &&
6514 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 6515 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
6516 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 6517 fault.vector = PF_VECTOR;
6518 fault.error_code_valid = true;
6519 fault.error_code = 0;
6520 fault.nested_page_fault = false;
6521 fault.address = work->arch.token;
6522 kvm_inject_page_fault(vcpu, &fault);
7c90705b 6523 }
af585b92
GN		 6524}
6525
6526void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
6527 struct kvm_async_pf *work)
6528{
6389ee94
AK		 6529 struct x86_exception fault;
6530
7c90705b
GN		 6531 trace_kvm_async_pf_ready(work->arch.token, work->gva);
6532 if (is_error_page(work->page))
6533 work->arch.token = ~0; /* broadcast wakeup */
6534 else
6535 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
6536
6537 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
6538 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 6539 fault.vector = PF_VECTOR;
6540 fault.error_code_valid = true;
6541 fault.error_code = 0;
6542 fault.nested_page_fault = false;
6543 fault.address = work->arch.token;
6544 kvm_inject_page_fault(vcpu, &fault);
7c90705b 6545 }
e6d53e3b 6546 vcpu->arch.apf.halted = false;
7c90705b
GN		 6547}
6548
6549bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
6550{
6551 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
6552 return true;
6553 else
6554 return !kvm_event_needs_reinjection(vcpu) &&
6555 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 6556}
6557
229456fc
MT		 6558EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
6559EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
6560EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
6561EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
6562EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 6563EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 6564EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 6565EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 6566EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 6567EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 6568EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 6569EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
kernel source for telekom puls (alcatel/mediatek)