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KVM: MMU: optimize pte write path if don't have protected sp
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
313a3dc7 29
18068523 30#include <linux/clocksource.h>
4d5c5d0f 31#include <linux/interrupt.h>
313a3dc7
CO		 32#include <linux/kvm.h>
33#include <linux/fs.h>
34#include <linux/vmalloc.h>
5fb76f9b 35#include <linux/module.h>
0de10343 36#include <linux/mman.h>
2bacc55c 37#include <linux/highmem.h>
19de40a8 38#include <linux/iommu.h>
62c476c7 39#include <linux/intel-iommu.h>
c8076604 40#include <linux/cpufreq.h>
18863bdd 41#include <linux/user-return-notifier.h>
a983fb23 42#include <linux/srcu.h>
5a0e3ad6 43#include <linux/slab.h>
ff9d07a0 44#include <linux/perf_event.h>
7bee342a 45#include <linux/uaccess.h>
af585b92 46#include <linux/hash.h>
aec51dc4 47#include <trace/events/kvm.h>
2ed152af 48
229456fc
MT		 49#define CREATE_TRACE_POINTS
50#include "trace.h"
043405e1 51
24f1e32c 52#include <asm/debugreg.h>
d825ed0a 53#include <asm/msr.h>
a5f61300 54#include <asm/desc.h>
0bed3b56 55#include <asm/mtrr.h>
890ca9ae 56#include <asm/mce.h>
7cf30855 57#include <asm/i387.h>
98918833 58#include <asm/xcr.h>
1d5f066e 59#include <asm/pvclock.h>
217fc9cf 60#include <asm/div64.h>
043405e1 61
313a3dc7 62#define MAX_IO_MSRS 256
890ca9ae 63#define KVM_MAX_MCE_BANKS 32
5854dbca 64#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 65
0f65dd70
AK		 66#define emul_to_vcpu(ctxt) \
67 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
68
50a37eb4
JR		 69/* EFER defaults:
70 * - enable syscall per default because its emulated by KVM
71 * - enable LME and LMA per default on 64 bit KVM
72 */
73#ifdef CONFIG_X86_64
1260edbe
LJ		 74static
75u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 76#else
1260edbe 77static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 78#endif
313a3dc7 79
ba1389b7
AK		 80#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
81#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 82
cb142eb7 83static void update_cr8_intercept(struct kvm_vcpu *vcpu);
674eea0f
AK		 84static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
85 struct kvm_cpuid_entry2 __user *entries);
86
97896d04 87struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 88EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 89
ed85c068
AP		 90int ignore_msrs = 0;
91module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
92
92a1f12d
JR		 93bool kvm_has_tsc_control;
94EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
95u32 kvm_max_guest_tsc_khz;
96EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
97
18863bdd
AK		 98#define KVM_NR_SHARED_MSRS 16
99
100struct kvm_shared_msrs_global {
101 int nr;
2bf78fa7 102 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 103};
104
105struct kvm_shared_msrs {
106 struct user_return_notifier urn;
107 bool registered;
2bf78fa7
SY		 108 struct kvm_shared_msr_values {
109 u64 host;
110 u64 curr;
111 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 112};
113
114static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
115static DEFINE_PER_CPU(struct kvm_shared_msrs, shared_msrs);
116
417bc304 117struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 118 { "pf_fixed", VCPU_STAT(pf_fixed) },
119 { "pf_guest", VCPU_STAT(pf_guest) },
120 { "tlb_flush", VCPU_STAT(tlb_flush) },
121 { "invlpg", VCPU_STAT(invlpg) },
122 { "exits", VCPU_STAT(exits) },
123 { "io_exits", VCPU_STAT(io_exits) },
124 { "mmio_exits", VCPU_STAT(mmio_exits) },
125 { "signal_exits", VCPU_STAT(signal_exits) },
126 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 127 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 128 { "halt_exits", VCPU_STAT(halt_exits) },
129 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 130 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 131 { "request_irq", VCPU_STAT(request_irq_exits) },
132 { "irq_exits", VCPU_STAT(irq_exits) },
133 { "host_state_reload", VCPU_STAT(host_state_reload) },
134 { "efer_reload", VCPU_STAT(efer_reload) },
135 { "fpu_reload", VCPU_STAT(fpu_reload) },
136 { "insn_emulation", VCPU_STAT(insn_emulation) },
137 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 138 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 139 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 140 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
141 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
142 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
143 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
144 { "mmu_flooded", VM_STAT(mmu_flooded) },
145 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 146 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 147 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 148 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 149 { "largepages", VM_STAT(lpages) },
417bc304
HB		 150 { NULL }
151};
152
2acf923e
DC		 153u64 __read_mostly host_xcr0;
154
d6aa1000
AK		 155int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
156
af585b92
GN		 157static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
158{
159 int i;
160 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
161 vcpu->arch.apf.gfns[i] = ~0;
162}
163
18863bdd
AK		 164static void kvm_on_user_return(struct user_return_notifier *urn)
165{
166 unsigned slot;
18863bdd
AK		 167 struct kvm_shared_msrs *locals
168 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 169 struct kvm_shared_msr_values *values;
18863bdd
AK		 170
171 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 172 values = &locals->values[slot];
173 if (values->host != values->curr) {
174 wrmsrl(shared_msrs_global.msrs[slot], values->host);
175 values->curr = values->host;
18863bdd
AK		 176 }
177 }
178 locals->registered = false;
179 user_return_notifier_unregister(urn);
180}
181
2bf78fa7 182static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 183{
2bf78fa7 184 struct kvm_shared_msrs *smsr;
18863bdd
AK		 185 u64 value;
186
2bf78fa7
SY		 187 smsr = &__get_cpu_var(shared_msrs);
188 /* only read, and nobody should modify it at this time,
189 * so don't need lock */
190 if (slot >= shared_msrs_global.nr) {
191 printk(KERN_ERR "kvm: invalid MSR slot!");
192 return;
193 }
194 rdmsrl_safe(msr, &value);
195 smsr->values[slot].host = value;
196 smsr->values[slot].curr = value;
197}
198
199void kvm_define_shared_msr(unsigned slot, u32 msr)
200{
18863bdd
AK		 201 if (slot >= shared_msrs_global.nr)
202 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 203 shared_msrs_global.msrs[slot] = msr;
204 /* we need ensured the shared_msr_global have been updated */
205 smp_wmb();
18863bdd
AK		 206}
207EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
208
209static void kvm_shared_msr_cpu_online(void)
210{
211 unsigned i;
18863bdd
AK		 212
213 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 214 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 215}
216
d5696725 217void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd
AK		 218{
219 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
220
2bf78fa7 221 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 222 return;
2bf78fa7
SY		 223 smsr->values[slot].curr = value;
224 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 225 if (!smsr->registered) {
226 smsr->urn.on_user_return = kvm_on_user_return;
227 user_return_notifier_register(&smsr->urn);
228 smsr->registered = true;
229 }
230}
231EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
232
3548bab5
AK		 233static void drop_user_return_notifiers(void *ignore)
234{
235 struct kvm_shared_msrs *smsr = &__get_cpu_var(shared_msrs);
236
237 if (smsr->registered)
238 kvm_on_user_return(&smsr->urn);
239}
240
6866b83e
CO		 241u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
242{
243 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 244 return vcpu->arch.apic_base;
6866b83e 245 else
ad312c7c 246 return vcpu->arch.apic_base;
6866b83e
CO		 247}
248EXPORT_SYMBOL_GPL(kvm_get_apic_base);
249
250void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
251{
252 /* TODO: reserve bits check */
253 if (irqchip_in_kernel(vcpu->kvm))
254 kvm_lapic_set_base(vcpu, data);
255 else
ad312c7c 256 vcpu->arch.apic_base = data;
6866b83e
CO		 257}
258EXPORT_SYMBOL_GPL(kvm_set_apic_base);
259
3fd28fce
ED		 260#define EXCPT_BENIGN 0
261#define EXCPT_CONTRIBUTORY 1
262#define EXCPT_PF 2
263
264static int exception_class(int vector)
265{
266 switch (vector) {
267 case PF_VECTOR:
268 return EXCPT_PF;
269 case DE_VECTOR:
270 case TS_VECTOR:
271 case NP_VECTOR:
272 case SS_VECTOR:
273 case GP_VECTOR:
274 return EXCPT_CONTRIBUTORY;
275 default:
276 break;
277 }
278 return EXCPT_BENIGN;
279}
280
281static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 282 unsigned nr, bool has_error, u32 error_code,
283 bool reinject)
3fd28fce
ED		 284{
285 u32 prev_nr;
286 int class1, class2;
287
3842d135
AK		 288 kvm_make_request(KVM_REQ_EVENT, vcpu);
289
3fd28fce
ED		 290 if (!vcpu->arch.exception.pending) {
291 queue:
292 vcpu->arch.exception.pending = true;
293 vcpu->arch.exception.has_error_code = has_error;
294 vcpu->arch.exception.nr = nr;
295 vcpu->arch.exception.error_code = error_code;
3f0fd292 296 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 297 return;
298 }
299
300 /* to check exception */
301 prev_nr = vcpu->arch.exception.nr;
302 if (prev_nr == DF_VECTOR) {
303 /* triple fault -> shutdown */
a8eeb04a 304 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 305 return;
306 }
307 class1 = exception_class(prev_nr);
308 class2 = exception_class(nr);
309 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
310 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
311 /* generate double fault per SDM Table 5-5 */
312 vcpu->arch.exception.pending = true;
313 vcpu->arch.exception.has_error_code = true;
314 vcpu->arch.exception.nr = DF_VECTOR;
315 vcpu->arch.exception.error_code = 0;
316 } else
317 /* replace previous exception with a new one in a hope
318 that instruction re-execution will regenerate lost
319 exception */
320 goto queue;
321}
322
298101da
AK		 323void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
324{
ce7ddec4 325 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 326}
327EXPORT_SYMBOL_GPL(kvm_queue_exception);
328
ce7ddec4
JR		 329void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
330{
331 kvm_multiple_exception(vcpu, nr, false, 0, true);
332}
333EXPORT_SYMBOL_GPL(kvm_requeue_exception);
334
db8fcefa 335void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 336{
db8fcefa
AP		 337 if (err)
338 kvm_inject_gp(vcpu, 0);
339 else
340 kvm_x86_ops->skip_emulated_instruction(vcpu);
341}
342EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 343
6389ee94 344void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 345{
346 ++vcpu->stat.pf_guest;
6389ee94
AK		 347 vcpu->arch.cr2 = fault->address;
348 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee
AK		 349}
350
6389ee94 351void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 352{
6389ee94
AK		 353 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
354 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 355 else
6389ee94 356 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
d4f8cf66
JR		 357}
358
3419ffc8
SY		 359void kvm_inject_nmi(struct kvm_vcpu *vcpu)
360{
3842d135 361 kvm_make_request(KVM_REQ_EVENT, vcpu);
c761e586 362 vcpu->arch.nmi_pending = 1;
3419ffc8
SY		 363}
364EXPORT_SYMBOL_GPL(kvm_inject_nmi);
365
298101da
AK		 366void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
367{
ce7ddec4 368 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 369}
370EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
371
ce7ddec4
JR		 372void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
373{
374 kvm_multiple_exception(vcpu, nr, true, error_code, true);
375}
376EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
377
0a79b009
AK		 378/*
379 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
380 * a #GP and return false.
381 */
382bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 383{
0a79b009
AK		 384 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
385 return true;
386 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
387 return false;
298101da 388}
0a79b009 389EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 390
ec92fe44
JR		 391/*
392 * This function will be used to read from the physical memory of the currently
393 * running guest. The difference to kvm_read_guest_page is that this function
394 * can read from guest physical or from the guest's guest physical memory.
395 */
396int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
397 gfn_t ngfn, void *data, int offset, int len,
398 u32 access)
399{
400 gfn_t real_gfn;
401 gpa_t ngpa;
402
403 ngpa = gfn_to_gpa(ngfn);
404 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
405 if (real_gfn == UNMAPPED_GVA)
406 return -EFAULT;
407
408 real_gfn = gpa_to_gfn(real_gfn);
409
410 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
411}
412EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
413
3d06b8bf
JR		 414int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
415 void *data, int offset, int len, u32 access)
416{
417 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
418 data, offset, len, access);
419}
420
a03490ed
CO		 421/*
422 * Load the pae pdptrs. Return true is they are all valid.
423 */
ff03a073 424int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 425{
426 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
427 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
428 int i;
429 int ret;
ff03a073 430 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 431
ff03a073
JR		 432 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
433 offset * sizeof(u64), sizeof(pdpte),
434 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 435 if (ret < 0) {
436 ret = 0;
437 goto out;
438 }
439 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 440 if (is_present_gpte(pdpte[i]) &&
20c466b5 441 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 442 ret = 0;
443 goto out;
444 }
445 }
446 ret = 1;
447
ff03a073 448 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 449 __set_bit(VCPU_EXREG_PDPTR,
450 (unsigned long *)&vcpu->arch.regs_avail);
451 __set_bit(VCPU_EXREG_PDPTR,
452 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 453out:
a03490ed
CO		 454
455 return ret;
456}
cc4b6871 457EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 458
d835dfec
AK		 459static bool pdptrs_changed(struct kvm_vcpu *vcpu)
460{
ff03a073 461 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 462 bool changed = true;
3d06b8bf
JR		 463 int offset;
464 gfn_t gfn;
d835dfec
AK		 465 int r;
466
467 if (is_long_mode(vcpu) || !is_pae(vcpu))
468 return false;
469
6de4f3ad
AK		 470 if (!test_bit(VCPU_EXREG_PDPTR,
471 (unsigned long *)&vcpu->arch.regs_avail))
472 return true;
473
9f8fe504
AK		 474 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
475 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 476 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
477 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 478 if (r < 0)
479 goto out;
ff03a073 480 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 481out:
d835dfec
AK		 482
483 return changed;
484}
485
49a9b07e 486int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 487{
aad82703
SY		 488 unsigned long old_cr0 = kvm_read_cr0(vcpu);
489 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
490 X86_CR0_CD | X86_CR0_NW;
491
f9a48e6a
AK		 492 cr0 |= X86_CR0_ET;
493
ab344828 494#ifdef CONFIG_X86_64
0f12244f
GN		 495 if (cr0 & 0xffffffff00000000UL)
496 return 1;
ab344828
GN		 497#endif
498
499 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 500
0f12244f
GN		 501 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
502 return 1;
a03490ed 503
0f12244f
GN		 504 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
505 return 1;
a03490ed
CO		 506
507 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
508#ifdef CONFIG_X86_64
f6801dff 509 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 510 int cs_db, cs_l;
511
0f12244f
GN		 512 if (!is_pae(vcpu))
513 return 1;
a03490ed 514 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 515 if (cs_l)
516 return 1;
a03490ed
CO		 517 } else
518#endif
ff03a073 519 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 520 kvm_read_cr3(vcpu)))
0f12244f 521 return 1;
a03490ed
CO		 522 }
523
524 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 525
d170c419 526 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 527 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 528 kvm_async_pf_hash_reset(vcpu);
529 }
e5f3f027 530
aad82703
SY		 531 if ((cr0 ^ old_cr0) & update_bits)
532 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 533 return 0;
534}
2d3ad1f4 535EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 536
2d3ad1f4 537void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 538{
49a9b07e 539 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 540}
2d3ad1f4 541EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 542
2acf923e
DC		 543int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
544{
545 u64 xcr0;
546
547 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
548 if (index != XCR_XFEATURE_ENABLED_MASK)
549 return 1;
550 xcr0 = xcr;
551 if (kvm_x86_ops->get_cpl(vcpu) != 0)
552 return 1;
553 if (!(xcr0 & XSTATE_FP))
554 return 1;
555 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
556 return 1;
557 if (xcr0 & ~host_xcr0)
558 return 1;
559 vcpu->arch.xcr0 = xcr0;
560 vcpu->guest_xcr0_loaded = 0;
561 return 0;
562}
563
564int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
565{
566 if (__kvm_set_xcr(vcpu, index, xcr)) {
567 kvm_inject_gp(vcpu, 0);
568 return 1;
569 }
570 return 0;
571}
572EXPORT_SYMBOL_GPL(kvm_set_xcr);
573
574static bool guest_cpuid_has_xsave(struct kvm_vcpu *vcpu)
575{
576 struct kvm_cpuid_entry2 *best;
577
578 best = kvm_find_cpuid_entry(vcpu, 1, 0);
579 return best && (best->ecx & bit(X86_FEATURE_XSAVE));
580}
581
582static void update_cpuid(struct kvm_vcpu *vcpu)
583{
584 struct kvm_cpuid_entry2 *best;
585
586 best = kvm_find_cpuid_entry(vcpu, 1, 0);
587 if (!best)
588 return;
589
590 /* Update OSXSAVE bit */
591 if (cpu_has_xsave && best->function == 0x1) {
592 best->ecx &= ~(bit(X86_FEATURE_OSXSAVE));
593 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE))
594 best->ecx |= bit(X86_FEATURE_OSXSAVE);
595 }
596}
597
a83b29c6 598int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 599{
fc78f519 600 unsigned long old_cr4 = kvm_read_cr4(vcpu);
a2edf57f
AK		 601 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
602
0f12244f
GN		 603 if (cr4 & CR4_RESERVED_BITS)
604 return 1;
a03490ed 605
2acf923e
DC		 606 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
607 return 1;
608
a03490ed 609 if (is_long_mode(vcpu)) {
0f12244f
GN		 610 if (!(cr4 & X86_CR4_PAE))
611 return 1;
a2edf57f
AK		 612 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
613 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 614 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
615 kvm_read_cr3(vcpu)))
0f12244f
GN		 616 return 1;
617
618 if (cr4 & X86_CR4_VMXE)
619 return 1;
a03490ed 620
a03490ed 621 kvm_x86_ops->set_cr4(vcpu, cr4);
62ad0755 622
aad82703
SY		 623 if ((cr4 ^ old_cr4) & pdptr_bits)
624 kvm_mmu_reset_context(vcpu);
0f12244f 625
2acf923e
DC		 626 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
627 update_cpuid(vcpu);
628
0f12244f
GN		 629 return 0;
630}
2d3ad1f4 631EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 632
2390218b 633int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 634{
9f8fe504 635 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 636 kvm_mmu_sync_roots(vcpu);
d835dfec 637 kvm_mmu_flush_tlb(vcpu);
0f12244f 638 return 0;
d835dfec
AK		 639 }
640
a03490ed 641 if (is_long_mode(vcpu)) {
0f12244f
GN		 642 if (cr3 & CR3_L_MODE_RESERVED_BITS)
643 return 1;
a03490ed
CO		 644 } else {
645 if (is_pae(vcpu)) {
0f12244f
GN		 646 if (cr3 & CR3_PAE_RESERVED_BITS)
647 return 1;
ff03a073
JR		 648 if (is_paging(vcpu) &&
649 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
0f12244f 650 return 1;
a03490ed
CO		 651 }
652 /*
653 * We don't check reserved bits in nonpae mode, because
654 * this isn't enforced, and VMware depends on this.
655 */
656 }
657
a03490ed
CO		 658 /*
659 * Does the new cr3 value map to physical memory? (Note, we
660 * catch an invalid cr3 even in real-mode, because it would
661 * cause trouble later on when we turn on paging anyway.)
662 *
663 * A real CPU would silently accept an invalid cr3 and would
664 * attempt to use it - with largely undefined (and often hard
665 * to debug) behavior on the guest side.
666 */
667 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
0f12244f
GN		 668 return 1;
669 vcpu->arch.cr3 = cr3;
aff48baa 670 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
0f12244f
GN		 671 vcpu->arch.mmu.new_cr3(vcpu);
672 return 0;
673}
2d3ad1f4 674EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 675
eea1cff9 676int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 677{
0f12244f
GN		 678 if (cr8 & CR8_RESERVED_BITS)
679 return 1;
a03490ed
CO		 680 if (irqchip_in_kernel(vcpu->kvm))
681 kvm_lapic_set_tpr(vcpu, cr8);
682 else
ad312c7c 683 vcpu->arch.cr8 = cr8;
0f12244f
GN		 684 return 0;
685}
2d3ad1f4 686EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 687
2d3ad1f4 688unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 689{
690 if (irqchip_in_kernel(vcpu->kvm))
691 return kvm_lapic_get_cr8(vcpu);
692 else
ad312c7c 693 return vcpu->arch.cr8;
a03490ed 694}
2d3ad1f4 695EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 696
338dbc97 697static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 698{
699 switch (dr) {
700 case 0 ... 3:
701 vcpu->arch.db[dr] = val;
702 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
703 vcpu->arch.eff_db[dr] = val;
704 break;
705 case 4:
338dbc97
GN		 706 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
707 return 1; /* #UD */
020df079
GN		 708 /* fall through */
709 case 6:
338dbc97
GN		 710 if (val & 0xffffffff00000000ULL)
711 return -1; /* #GP */
020df079
GN		 712 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
713 break;
714 case 5:
338dbc97
GN		 715 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
716 return 1; /* #UD */
020df079
GN		 717 /* fall through */
718 default: /* 7 */
338dbc97
GN		 719 if (val & 0xffffffff00000000ULL)
720 return -1; /* #GP */
020df079
GN		 721 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
722 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
723 kvm_x86_ops->set_dr7(vcpu, vcpu->arch.dr7);
724 vcpu->arch.switch_db_regs = (val & DR7_BP_EN_MASK);
725 }
726 break;
727 }
728
729 return 0;
730}
338dbc97
GN		 731
732int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
733{
734 int res;
735
736 res = __kvm_set_dr(vcpu, dr, val);
737 if (res > 0)
738 kvm_queue_exception(vcpu, UD_VECTOR);
739 else if (res < 0)
740 kvm_inject_gp(vcpu, 0);
741
742 return res;
743}
020df079
GN		 744EXPORT_SYMBOL_GPL(kvm_set_dr);
745
338dbc97 746static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 747{
748 switch (dr) {
749 case 0 ... 3:
750 *val = vcpu->arch.db[dr];
751 break;
752 case 4:
338dbc97 753 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 754 return 1;
020df079
GN		 755 /* fall through */
756 case 6:
757 *val = vcpu->arch.dr6;
758 break;
759 case 5:
338dbc97 760 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 761 return 1;
020df079
GN		 762 /* fall through */
763 default: /* 7 */
764 *val = vcpu->arch.dr7;
765 break;
766 }
767
768 return 0;
769}
338dbc97
GN		 770
771int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
772{
773 if (_kvm_get_dr(vcpu, dr, val)) {
774 kvm_queue_exception(vcpu, UD_VECTOR);
775 return 1;
776 }
777 return 0;
778}
020df079
GN		 779EXPORT_SYMBOL_GPL(kvm_get_dr);
780
043405e1
CO		 781/*
782 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
783 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
784 *
785 * This list is modified at module load time to reflect the
e3267cbb
GC		 786 * capabilities of the host cpu. This capabilities test skips MSRs that are
787 * kvm-specific. Those are put in the beginning of the list.
043405e1 788 */
e3267cbb 789
344d9588 790#define KVM_SAVE_MSRS_BEGIN 8
043405e1 791static u32 msrs_to_save[] = {
e3267cbb 792 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 793 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 794 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
344d9588 795 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN,
043405e1 796 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 797 MSR_STAR,
043405e1
CO		 798#ifdef CONFIG_X86_64
799 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
800#endif
e90aa41e 801 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 802};
803
804static unsigned num_msrs_to_save;
805
806static u32 emulated_msrs[] = {
807 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 808 MSR_IA32_MCG_STATUS,
809 MSR_IA32_MCG_CTL,
043405e1
CO		 810};
811
b69e8cae 812static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 813{
aad82703
SY		 814 u64 old_efer = vcpu->arch.efer;
815
b69e8cae
RJ		 816 if (efer & efer_reserved_bits)
817 return 1;
15c4a640
CO		 818
819 if (is_paging(vcpu)
b69e8cae
RJ		 820 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
821 return 1;
15c4a640 822
1b2fd70c
AG		 823 if (efer & EFER_FFXSR) {
824 struct kvm_cpuid_entry2 *feat;
825
826 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 827 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
828 return 1;
1b2fd70c
AG		 829 }
830
d8017474
AG		 831 if (efer & EFER_SVME) {
832 struct kvm_cpuid_entry2 *feat;
833
834 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 835 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
836 return 1;
d8017474
AG		 837 }
838
15c4a640 839 efer &= ~EFER_LMA;
f6801dff 840 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 841
a3d204e2
SY		 842 kvm_x86_ops->set_efer(vcpu, efer);
843
9645bb56 844 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
b69e8cae 845
aad82703
SY		 846 /* Update reserved bits */
847 if ((efer ^ old_efer) & EFER_NX)
848 kvm_mmu_reset_context(vcpu);
849
b69e8cae 850 return 0;
15c4a640
CO		 851}
852
f2b4b7dd
JR		 853void kvm_enable_efer_bits(u64 mask)
854{
855 efer_reserved_bits &= ~mask;
856}
857EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
858
859
15c4a640
CO		 860/*
861 * Writes msr value into into the appropriate "register".
862 * Returns 0 on success, non-0 otherwise.
863 * Assumes vcpu_load() was already called.
864 */
865int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
866{
867 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
868}
869
313a3dc7
CO		 870/*
871 * Adapt set_msr() to msr_io()'s calling convention
872 */
873static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
874{
875 return kvm_set_msr(vcpu, index, *data);
876}
877
18068523
GOC		 878static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
879{
9ed3c444
AK		 880 int version;
881 int r;
50d0a0f9 882 struct pvclock_wall_clock wc;
923de3cf 883 struct timespec boot;
18068523
GOC		 884
885 if (!wall_clock)
886 return;
887
9ed3c444
AK		 888 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
889 if (r)
890 return;
891
892 if (version & 1)
893 ++version; /* first time write, random junk */
894
895 ++version;
18068523 896
18068523
GOC		 897 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
898
50d0a0f9
GH		 899 /*
900 * The guest calculates current wall clock time by adding
34c238a1 901 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 902 * wall clock specified here. guest system time equals host
903 * system time for us, thus we must fill in host boot time here.
904 */
923de3cf 905 getboottime(&boot);
50d0a0f9
GH		 906
907 wc.sec = boot.tv_sec;
908 wc.nsec = boot.tv_nsec;
909 wc.version = version;
18068523
GOC		 910
911 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
912
913 version++;
914 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 915}
916
50d0a0f9
GH		 917static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
918{
919 uint32_t quotient, remainder;
920
921 /* Don't try to replace with do_div(), this one calculates
922 * "(dividend << 32) / divisor" */
923 __asm__ ( "divl %4"
924 : "=a" (quotient), "=d" (remainder)
925 : "0" (0), "1" (dividend), "r" (divisor) );
926 return quotient;
927}
928
5f4e3f88
ZA		 929static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
930 s8 *pshift, u32 *pmultiplier)
50d0a0f9 931{
5f4e3f88 932 uint64_t scaled64;
50d0a0f9
GH		 933 int32_t shift = 0;
934 uint64_t tps64;
935 uint32_t tps32;
936
5f4e3f88
ZA		 937 tps64 = base_khz * 1000LL;
938 scaled64 = scaled_khz * 1000LL;
50933623 939 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 940 tps64 >>= 1;
941 shift--;
942 }
943
944 tps32 = (uint32_t)tps64;
50933623
JK		 945 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
946 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 947 scaled64 >>= 1;
948 else
949 tps32 <<= 1;
50d0a0f9
GH		 950 shift++;
951 }
952
5f4e3f88
ZA		 953 *pshift = shift;
954 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 955
5f4e3f88
ZA		 956 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
957 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 958}
959
759379dd
ZA		 960static inline u64 get_kernel_ns(void)
961{
962 struct timespec ts;
963
964 WARN_ON(preemptible());
965 ktime_get_ts(&ts);
966 monotonic_to_bootbased(&ts);
967 return timespec_to_ns(&ts);
50d0a0f9
GH		 968}
969
c8076604 970static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 971unsigned long max_tsc_khz;
c8076604 972
8cfdc000
ZA		 973static inline int kvm_tsc_changes_freq(void)
974{
975 int cpu = get_cpu();
976 int ret = !boot_cpu_has(X86_FEATURE_CONSTANT_TSC) &&
977 cpufreq_quick_get(cpu) != 0;
978 put_cpu();
979 return ret;
980}
981
1e993611
JR		 982static u64 vcpu_tsc_khz(struct kvm_vcpu *vcpu)
983{
984 if (vcpu->arch.virtual_tsc_khz)
985 return vcpu->arch.virtual_tsc_khz;
986 else
987 return __this_cpu_read(cpu_tsc_khz);
988}
989
857e4099 990static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
759379dd 991{
217fc9cf
AK		 992 u64 ret;
993
759379dd
ZA		 994 WARN_ON(preemptible());
995 if (kvm_tsc_changes_freq())
996 printk_once(KERN_WARNING
997 "kvm: unreliable cycle conversion on adjustable rate TSC\n");
857e4099 998 ret = nsec * vcpu_tsc_khz(vcpu);
217fc9cf
AK		 999 do_div(ret, USEC_PER_SEC);
1000 return ret;
759379dd
ZA		 1001}
1002
1e993611 1003static void kvm_init_tsc_catchup(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
c285545f
ZA		 1004{
1005 /* Compute a scale to convert nanoseconds in TSC cycles */
1006 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
1e993611
JR		 1007 &vcpu->arch.tsc_catchup_shift,
1008 &vcpu->arch.tsc_catchup_mult);
c285545f
ZA		 1009}
1010
1011static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1012{
1013 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.last_tsc_nsec,
1e993611
JR		 1014 vcpu->arch.tsc_catchup_mult,
1015 vcpu->arch.tsc_catchup_shift);
c285545f
ZA		 1016 tsc += vcpu->arch.last_tsc_write;
1017 return tsc;
1018}
1019
99e3e30a
ZA		 1020void kvm_write_tsc(struct kvm_vcpu *vcpu, u64 data)
1021{
1022 struct kvm *kvm = vcpu->kvm;
f38e098f 1023 u64 offset, ns, elapsed;
99e3e30a 1024 unsigned long flags;
46543ba4 1025 s64 sdiff;
99e3e30a 1026
038f8c11 1027 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1028 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1029 ns = get_kernel_ns();
f38e098f 1030 elapsed = ns - kvm->arch.last_tsc_nsec;
46543ba4
ZA		 1031 sdiff = data - kvm->arch.last_tsc_write;
1032 if (sdiff < 0)
1033 sdiff = -sdiff;
f38e098f
ZA		 1034
1035 /*
46543ba4 1036 * Special case: close write to TSC within 5 seconds of
f38e098f 1037 * another CPU is interpreted as an attempt to synchronize
0d2eb44f 1038 * The 5 seconds is to accommodate host load / swapping as
46543ba4 1039 * well as any reset of TSC during the boot process.
f38e098f
ZA		 1040 *
1041 * In that case, for a reliable TSC, we can match TSC offsets,
46543ba4 1042 * or make a best guest using elapsed value.
f38e098f 1043 */
857e4099 1044 if (sdiff < nsec_to_cycles(vcpu, 5ULL * NSEC_PER_SEC) &&
46543ba4 1045 elapsed < 5ULL * NSEC_PER_SEC) {
f38e098f
ZA		 1046 if (!check_tsc_unstable()) {
1047 offset = kvm->arch.last_tsc_offset;
1048 pr_debug("kvm: matched tsc offset for %llu\n", data);
1049 } else {
857e4099 1050 u64 delta = nsec_to_cycles(vcpu, elapsed);
759379dd
ZA		 1051 offset += delta;
1052 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f
ZA		 1053 }
1054 ns = kvm->arch.last_tsc_nsec;
1055 }
1056 kvm->arch.last_tsc_nsec = ns;
1057 kvm->arch.last_tsc_write = data;
1058 kvm->arch.last_tsc_offset = offset;
99e3e30a 1059 kvm_x86_ops->write_tsc_offset(vcpu, offset);
038f8c11 1060 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
99e3e30a
ZA		 1061
1062 /* Reset of TSC must disable overshoot protection below */
1063 vcpu->arch.hv_clock.tsc_timestamp = 0;
c285545f
ZA		 1064 vcpu->arch.last_tsc_write = data;
1065 vcpu->arch.last_tsc_nsec = ns;
99e3e30a
ZA		 1066}
1067EXPORT_SYMBOL_GPL(kvm_write_tsc);
1068
34c238a1 1069static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1070{
18068523
GOC		 1071 unsigned long flags;
1072 struct kvm_vcpu_arch *vcpu = &v->arch;
1073 void *shared_kaddr;
463656c0 1074 unsigned long this_tsc_khz;
1d5f066e
ZA		 1075 s64 kernel_ns, max_kernel_ns;
1076 u64 tsc_timestamp;
18068523 1077
18068523
GOC		 1078 /* Keep irq disabled to prevent changes to the clock */
1079 local_irq_save(flags);
1d5f066e 1080 kvm_get_msr(v, MSR_IA32_TSC, &tsc_timestamp);
759379dd 1081 kernel_ns = get_kernel_ns();
1e993611 1082 this_tsc_khz = vcpu_tsc_khz(v);
8cfdc000 1083 if (unlikely(this_tsc_khz == 0)) {
c285545f 1084 local_irq_restore(flags);
34c238a1 1085 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
8cfdc000
ZA		 1086 return 1;
1087 }
18068523 1088
c285545f
ZA		 1089 /*
1090 * We may have to catch up the TSC to match elapsed wall clock
1091 * time for two reasons, even if kvmclock is used.
1092 * 1) CPU could have been running below the maximum TSC rate
1093 * 2) Broken TSC compensation resets the base at each VCPU
1094 * entry to avoid unknown leaps of TSC even when running
1095 * again on the same CPU. This may cause apparent elapsed
1096 * time to disappear, and the guest to stand still or run
1097 * very slowly.
1098 */
1099 if (vcpu->tsc_catchup) {
1100 u64 tsc = compute_guest_tsc(v, kernel_ns);
1101 if (tsc > tsc_timestamp) {
1102 kvm_x86_ops->adjust_tsc_offset(v, tsc - tsc_timestamp);
1103 tsc_timestamp = tsc;
1104 }
50d0a0f9
GH		 1105 }
1106
18068523
GOC		 1107 local_irq_restore(flags);
1108
c285545f
ZA		 1109 if (!vcpu->time_page)
1110 return 0;
18068523 1111
1d5f066e
ZA		 1112 /*
1113 * Time as measured by the TSC may go backwards when resetting the base
1114 * tsc_timestamp. The reason for this is that the TSC resolution is
1115 * higher than the resolution of the other clock scales. Thus, many
1116 * possible measurments of the TSC correspond to one measurement of any
1117 * other clock, and so a spread of values is possible. This is not a
1118 * problem for the computation of the nanosecond clock; with TSC rates
1119 * around 1GHZ, there can only be a few cycles which correspond to one
1120 * nanosecond value, and any path through this code will inevitably
1121 * take longer than that. However, with the kernel_ns value itself,
1122 * the precision may be much lower, down to HZ granularity. If the
1123 * first sampling of TSC against kernel_ns ends in the low part of the
1124 * range, and the second in the high end of the range, we can get:
1125 *
1126 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1127 *
1128 * As the sampling errors potentially range in the thousands of cycles,
1129 * it is possible such a time value has already been observed by the
1130 * guest. To protect against this, we must compute the system time as
1131 * observed by the guest and ensure the new system time is greater.
1132 */
1133 max_kernel_ns = 0;
1134 if (vcpu->hv_clock.tsc_timestamp && vcpu->last_guest_tsc) {
1135 max_kernel_ns = vcpu->last_guest_tsc -
1136 vcpu->hv_clock.tsc_timestamp;
1137 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1138 vcpu->hv_clock.tsc_to_system_mul,
1139 vcpu->hv_clock.tsc_shift);
1140 max_kernel_ns += vcpu->last_kernel_ns;
1141 }
afbcf7ab 1142
e48672fa 1143 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1144 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1145 &vcpu->hv_clock.tsc_shift,
1146 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1147 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1148 }
1149
1d5f066e
ZA		 1150 if (max_kernel_ns > kernel_ns)
1151 kernel_ns = max_kernel_ns;
1152
8cfdc000 1153 /* With all the info we got, fill in the values */
1d5f066e 1154 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1155 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1d5f066e 1156 vcpu->last_kernel_ns = kernel_ns;
28e4639a 1157 vcpu->last_guest_tsc = tsc_timestamp;
371bcf64
GC		 1158 vcpu->hv_clock.flags = 0;
1159
18068523
GOC		 1160 /*
1161 * The interface expects us to write an even number signaling that the
1162 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1163 * state, we just increase by 2 at the end.
18068523 1164 */
50d0a0f9 1165 vcpu->hv_clock.version += 2;
18068523
GOC		 1166
1167 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
1168
1169 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 1170 sizeof(vcpu->hv_clock));
18068523
GOC		 1171
1172 kunmap_atomic(shared_kaddr, KM_USER0);
1173
1174 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
8cfdc000 1175 return 0;
c8076604
GH		 1176}
1177
9ba075a6
AK		 1178static bool msr_mtrr_valid(unsigned msr)
1179{
1180 switch (msr) {
1181 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1182 case MSR_MTRRfix64K_00000:
1183 case MSR_MTRRfix16K_80000:
1184 case MSR_MTRRfix16K_A0000:
1185 case MSR_MTRRfix4K_C0000:
1186 case MSR_MTRRfix4K_C8000:
1187 case MSR_MTRRfix4K_D0000:
1188 case MSR_MTRRfix4K_D8000:
1189 case MSR_MTRRfix4K_E0000:
1190 case MSR_MTRRfix4K_E8000:
1191 case MSR_MTRRfix4K_F0000:
1192 case MSR_MTRRfix4K_F8000:
1193 case MSR_MTRRdefType:
1194 case MSR_IA32_CR_PAT:
1195 return true;
1196 case 0x2f8:
1197 return true;
1198 }
1199 return false;
1200}
1201
d6289b93
MT		 1202static bool valid_pat_type(unsigned t)
1203{
1204 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1205}
1206
1207static bool valid_mtrr_type(unsigned t)
1208{
1209 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1210}
1211
1212static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1213{
1214 int i;
1215
1216 if (!msr_mtrr_valid(msr))
1217 return false;
1218
1219 if (msr == MSR_IA32_CR_PAT) {
1220 for (i = 0; i < 8; i++)
1221 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1222 return false;
1223 return true;
1224 } else if (msr == MSR_MTRRdefType) {
1225 if (data & ~0xcff)
1226 return false;
1227 return valid_mtrr_type(data & 0xff);
1228 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1229 for (i = 0; i < 8 ; i++)
1230 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1231 return false;
1232 return true;
1233 }
1234
1235 /* variable MTRRs */
1236 return valid_mtrr_type(data & 0xff);
1237}
1238
9ba075a6
AK		 1239static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1240{
0bed3b56
SY		 1241 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1242
d6289b93 1243 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1244 return 1;
1245
0bed3b56
SY		 1246 if (msr == MSR_MTRRdefType) {
1247 vcpu->arch.mtrr_state.def_type = data;
1248 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1249 } else if (msr == MSR_MTRRfix64K_00000)
1250 p[0] = data;
1251 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1252 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1253 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1254 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1255 else if (msr == MSR_IA32_CR_PAT)
1256 vcpu->arch.pat = data;
1257 else { /* Variable MTRRs */
1258 int idx, is_mtrr_mask;
1259 u64 *pt;
1260
1261 idx = (msr - 0x200) / 2;
1262 is_mtrr_mask = msr - 0x200 - 2 * idx;
1263 if (!is_mtrr_mask)
1264 pt =
1265 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1266 else
1267 pt =
1268 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1269 *pt = data;
1270 }
1271
1272 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1273 return 0;
1274}
15c4a640 1275
890ca9ae 1276static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1277{
890ca9ae
HY		 1278 u64 mcg_cap = vcpu->arch.mcg_cap;
1279 unsigned bank_num = mcg_cap & 0xff;
1280
15c4a640 1281 switch (msr) {
15c4a640 1282 case MSR_IA32_MCG_STATUS:
890ca9ae 1283 vcpu->arch.mcg_status = data;
15c4a640 1284 break;
c7ac679c 1285 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1286 if (!(mcg_cap & MCG_CTL_P))
1287 return 1;
1288 if (data != 0 && data != ~(u64)0)
1289 return -1;
1290 vcpu->arch.mcg_ctl = data;
1291 break;
1292 default:
1293 if (msr >= MSR_IA32_MC0_CTL &&
1294 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1295 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1296 /* only 0 or all 1s can be written to IA32_MCi_CTL
1297 * some Linux kernels though clear bit 10 in bank 4 to
1298 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1299 * this to avoid an uncatched #GP in the guest
1300 */
890ca9ae 1301 if ((offset & 0x3) == 0 &&
114be429 1302 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1303 return -1;
1304 vcpu->arch.mce_banks[offset] = data;
1305 break;
1306 }
1307 return 1;
1308 }
1309 return 0;
1310}
1311
ffde22ac
ES		 1312static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1313{
1314 struct kvm *kvm = vcpu->kvm;
1315 int lm = is_long_mode(vcpu);
1316 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1317 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1318 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1319 : kvm->arch.xen_hvm_config.blob_size_32;
1320 u32 page_num = data & ~PAGE_MASK;
1321 u64 page_addr = data & PAGE_MASK;
1322 u8 *page;
1323 int r;
1324
1325 r = -E2BIG;
1326 if (page_num >= blob_size)
1327 goto out;
1328 r = -ENOMEM;
1329 page = kzalloc(PAGE_SIZE, GFP_KERNEL);
1330 if (!page)
1331 goto out;
1332 r = -EFAULT;
1333 if (copy_from_user(page, blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE))
1334 goto out_free;
1335 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1336 goto out_free;
1337 r = 0;
1338out_free:
1339 kfree(page);
1340out:
1341 return r;
1342}
1343
55cd8e5a
GN		 1344static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1345{
1346 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1347}
1348
1349static bool kvm_hv_msr_partition_wide(u32 msr)
1350{
1351 bool r = false;
1352 switch (msr) {
1353 case HV_X64_MSR_GUEST_OS_ID:
1354 case HV_X64_MSR_HYPERCALL:
1355 r = true;
1356 break;
1357 }
1358
1359 return r;
1360}
1361
1362static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1363{
1364 struct kvm *kvm = vcpu->kvm;
1365
1366 switch (msr) {
1367 case HV_X64_MSR_GUEST_OS_ID:
1368 kvm->arch.hv_guest_os_id = data;
1369 /* setting guest os id to zero disables hypercall page */
1370 if (!kvm->arch.hv_guest_os_id)
1371 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1372 break;
1373 case HV_X64_MSR_HYPERCALL: {
1374 u64 gfn;
1375 unsigned long addr;
1376 u8 instructions[4];
1377
1378 /* if guest os id is not set hypercall should remain disabled */
1379 if (!kvm->arch.hv_guest_os_id)
1380 break;
1381 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1382 kvm->arch.hv_hypercall = data;
1383 break;
1384 }
1385 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1386 addr = gfn_to_hva(kvm, gfn);
1387 if (kvm_is_error_hva(addr))
1388 return 1;
1389 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1390 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1391 if (copy_to_user((void __user *)addr, instructions, 4))
1392 return 1;
1393 kvm->arch.hv_hypercall = data;
1394 break;
1395 }
1396 default:
1397 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1398 "data 0x%llx\n", msr, data);
1399 return 1;
1400 }
1401 return 0;
1402}
1403
1404static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1405{
10388a07
GN		 1406 switch (msr) {
1407 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1408 unsigned long addr;
55cd8e5a 1409
10388a07
GN		 1410 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1411 vcpu->arch.hv_vapic = data;
1412 break;
1413 }
1414 addr = gfn_to_hva(vcpu->kvm, data >>
1415 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1416 if (kvm_is_error_hva(addr))
1417 return 1;
1418 if (clear_user((void __user *)addr, PAGE_SIZE))
1419 return 1;
1420 vcpu->arch.hv_vapic = data;
1421 break;
1422 }
1423 case HV_X64_MSR_EOI:
1424 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1425 case HV_X64_MSR_ICR:
1426 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1427 case HV_X64_MSR_TPR:
1428 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1429 default:
1430 pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1431 "data 0x%llx\n", msr, data);
1432 return 1;
1433 }
1434
1435 return 0;
55cd8e5a
GN		 1436}
1437
344d9588
GN		 1438static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1439{
1440 gpa_t gpa = data & ~0x3f;
1441
6adba527
GN		 1442 /* Bits 2:5 are resrved, Should be zero */
1443 if (data & 0x3c)
344d9588
GN		 1444 return 1;
1445
1446 vcpu->arch.apf.msr_val = data;
1447
1448 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1449 kvm_clear_async_pf_completion_queue(vcpu);
1450 kvm_async_pf_hash_reset(vcpu);
1451 return 0;
1452 }
1453
1454 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa))
1455 return 1;
1456
6adba527 1457 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1458 kvm_async_pf_wakeup_all(vcpu);
1459 return 0;
1460}
1461
12f9a48f
GC		 1462static void kvmclock_reset(struct kvm_vcpu *vcpu)
1463{
1464 if (vcpu->arch.time_page) {
1465 kvm_release_page_dirty(vcpu->arch.time_page);
1466 vcpu->arch.time_page = NULL;
1467 }
1468}
1469
15c4a640
CO		 1470int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1471{
1472 switch (msr) {
15c4a640 1473 case MSR_EFER:
b69e8cae 1474 return set_efer(vcpu, data);
8f1589d9
AP		 1475 case MSR_K7_HWCR:
1476 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1477 data &= ~(u64)0x100; /* ignore ignne emulation enable */
8f1589d9
AP		 1478 if (data != 0) {
1479 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1480 data);
1481 return 1;
1482 }
15c4a640 1483 break;
f7c6d140
AP		 1484 case MSR_FAM10H_MMIO_CONF_BASE:
1485 if (data != 0) {
1486 pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1487 "0x%llx\n", data);
1488 return 1;
1489 }
15c4a640 1490 break;
c323c0e5 1491 case MSR_AMD64_NB_CFG:
c7ac679c 1492 break;
b5e2fec0
AG		 1493 case MSR_IA32_DEBUGCTLMSR:
1494 if (!data) {
1495 /* We support the non-activated case already */
1496 break;
1497 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1498 /* Values other than LBR and BTF are vendor-specific,
1499 thus reserved and should throw a #GP */
1500 return 1;
1501 }
1502 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1503 __func__, data);
1504 break;
15c4a640
CO		 1505 case MSR_IA32_UCODE_REV:
1506 case MSR_IA32_UCODE_WRITE:
61a6bd67 1507 case MSR_VM_HSAVE_PA:
6098ca93 1508 case MSR_AMD64_PATCH_LOADER:
15c4a640 1509 break;
9ba075a6
AK		 1510 case 0x200 ... 0x2ff:
1511 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1512 case MSR_IA32_APICBASE:
1513 kvm_set_apic_base(vcpu, data);
1514 break;
0105d1a5
GN		 1515 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1516 return kvm_x2apic_msr_write(vcpu, msr, data);
15c4a640 1517 case MSR_IA32_MISC_ENABLE:
ad312c7c 1518 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1519 break;
11c6bffa 1520 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1521 case MSR_KVM_WALL_CLOCK:
1522 vcpu->kvm->arch.wall_clock = data;
1523 kvm_write_wall_clock(vcpu->kvm, data);
1524 break;
11c6bffa 1525 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 1526 case MSR_KVM_SYSTEM_TIME: {
12f9a48f 1527 kvmclock_reset(vcpu);
18068523
GOC		 1528
1529 vcpu->arch.time = data;
c285545f 1530 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
18068523
GOC		 1531
1532 /* we verify if the enable bit is set... */
1533 if (!(data & 1))
1534 break;
1535
1536 /* ...but clean it before doing the actual write */
1537 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1538
18068523
GOC		 1539 vcpu->arch.time_page =
1540 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 1541
1542 if (is_error_page(vcpu->arch.time_page)) {
1543 kvm_release_page_clean(vcpu->arch.time_page);
1544 vcpu->arch.time_page = NULL;
1545 }
18068523
GOC		 1546 break;
1547 }
344d9588
GN		 1548 case MSR_KVM_ASYNC_PF_EN:
1549 if (kvm_pv_enable_async_pf(vcpu, data))
1550 return 1;
1551 break;
890ca9ae
HY		 1552 case MSR_IA32_MCG_CTL:
1553 case MSR_IA32_MCG_STATUS:
1554 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1555 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 1556
1557 /* Performance counters are not protected by a CPUID bit,
1558 * so we should check all of them in the generic path for the sake of
1559 * cross vendor migration.
1560 * Writing a zero into the event select MSRs disables them,
1561 * which we perfectly emulate ;-). Any other value should be at least
1562 * reported, some guests depend on them.
1563 */
1564 case MSR_P6_EVNTSEL0:
1565 case MSR_P6_EVNTSEL1:
1566 case MSR_K7_EVNTSEL0:
1567 case MSR_K7_EVNTSEL1:
1568 case MSR_K7_EVNTSEL2:
1569 case MSR_K7_EVNTSEL3:
1570 if (data != 0)
1571 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1572 "0x%x data 0x%llx\n", msr, data);
1573 break;
1574 /* at least RHEL 4 unconditionally writes to the perfctr registers,
1575 * so we ignore writes to make it happy.
1576 */
1577 case MSR_P6_PERFCTR0:
1578 case MSR_P6_PERFCTR1:
1579 case MSR_K7_PERFCTR0:
1580 case MSR_K7_PERFCTR1:
1581 case MSR_K7_PERFCTR2:
1582 case MSR_K7_PERFCTR3:
1583 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
1584 "0x%x data 0x%llx\n", msr, data);
1585 break;
84e0cefa
JS		 1586 case MSR_K7_CLK_CTL:
1587 /*
1588 * Ignore all writes to this no longer documented MSR.
1589 * Writes are only relevant for old K7 processors,
1590 * all pre-dating SVM, but a recommended workaround from
1591 * AMD for these chips. It is possible to speicify the
1592 * affected processor models on the command line, hence
1593 * the need to ignore the workaround.
1594 */
1595 break;
55cd8e5a
GN		 1596 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1597 if (kvm_hv_msr_partition_wide(msr)) {
1598 int r;
1599 mutex_lock(&vcpu->kvm->lock);
1600 r = set_msr_hyperv_pw(vcpu, msr, data);
1601 mutex_unlock(&vcpu->kvm->lock);
1602 return r;
1603 } else
1604 return set_msr_hyperv(vcpu, msr, data);
1605 break;
91c9c3ed 1606 case MSR_IA32_BBL_CR_CTL3:
1607 /* Drop writes to this legacy MSR -- see rdmsr
1608 * counterpart for further detail.
1609 */
1610 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
1611 break;
15c4a640 1612 default:
ffde22ac
ES		 1613 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
1614 return xen_hvm_config(vcpu, data);
ed85c068
AP		 1615 if (!ignore_msrs) {
1616 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
1617 msr, data);
1618 return 1;
1619 } else {
1620 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
1621 msr, data);
1622 break;
1623 }
15c4a640
CO		 1624 }
1625 return 0;
1626}
1627EXPORT_SYMBOL_GPL(kvm_set_msr_common);
1628
1629
1630/*
1631 * Reads an msr value (of 'msr_index') into 'pdata'.
1632 * Returns 0 on success, non-0 otherwise.
1633 * Assumes vcpu_load() was already called.
1634 */
1635int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1636{
1637 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
1638}
1639
9ba075a6
AK		 1640static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1641{
0bed3b56
SY		 1642 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1643
9ba075a6
AK		 1644 if (!msr_mtrr_valid(msr))
1645 return 1;
1646
0bed3b56
SY		 1647 if (msr == MSR_MTRRdefType)
1648 *pdata = vcpu->arch.mtrr_state.def_type +
1649 (vcpu->arch.mtrr_state.enabled << 10);
1650 else if (msr == MSR_MTRRfix64K_00000)
1651 *pdata = p[0];
1652 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1653 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
1654 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1655 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
1656 else if (msr == MSR_IA32_CR_PAT)
1657 *pdata = vcpu->arch.pat;
1658 else { /* Variable MTRRs */
1659 int idx, is_mtrr_mask;
1660 u64 *pt;
1661
1662 idx = (msr - 0x200) / 2;
1663 is_mtrr_mask = msr - 0x200 - 2 * idx;
1664 if (!is_mtrr_mask)
1665 pt =
1666 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1667 else
1668 pt =
1669 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1670 *pdata = *pt;
1671 }
1672
9ba075a6
AK		 1673 return 0;
1674}
1675
890ca9ae 1676static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1677{
1678 u64 data;
890ca9ae
HY		 1679 u64 mcg_cap = vcpu->arch.mcg_cap;
1680 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1681
1682 switch (msr) {
15c4a640
CO		 1683 case MSR_IA32_P5_MC_ADDR:
1684 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1685 data = 0;
1686 break;
15c4a640 1687 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1688 data = vcpu->arch.mcg_cap;
1689 break;
c7ac679c 1690 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1691 if (!(mcg_cap & MCG_CTL_P))
1692 return 1;
1693 data = vcpu->arch.mcg_ctl;
1694 break;
1695 case MSR_IA32_MCG_STATUS:
1696 data = vcpu->arch.mcg_status;
1697 break;
1698 default:
1699 if (msr >= MSR_IA32_MC0_CTL &&
1700 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1701 u32 offset = msr - MSR_IA32_MC0_CTL;
1702 data = vcpu->arch.mce_banks[offset];
1703 break;
1704 }
1705 return 1;
1706 }
1707 *pdata = data;
1708 return 0;
1709}
1710
55cd8e5a
GN		 1711static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1712{
1713 u64 data = 0;
1714 struct kvm *kvm = vcpu->kvm;
1715
1716 switch (msr) {
1717 case HV_X64_MSR_GUEST_OS_ID:
1718 data = kvm->arch.hv_guest_os_id;
1719 break;
1720 case HV_X64_MSR_HYPERCALL:
1721 data = kvm->arch.hv_hypercall;
1722 break;
1723 default:
1724 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1725 return 1;
1726 }
1727
1728 *pdata = data;
1729 return 0;
1730}
1731
1732static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1733{
1734 u64 data = 0;
1735
1736 switch (msr) {
1737 case HV_X64_MSR_VP_INDEX: {
1738 int r;
1739 struct kvm_vcpu *v;
1740 kvm_for_each_vcpu(r, v, vcpu->kvm)
1741 if (v == vcpu)
1742 data = r;
1743 break;
1744 }
10388a07
GN		 1745 case HV_X64_MSR_EOI:
1746 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
1747 case HV_X64_MSR_ICR:
1748 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
1749 case HV_X64_MSR_TPR:
1750 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
55cd8e5a
GN		 1751 default:
1752 pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
1753 return 1;
1754 }
1755 *pdata = data;
1756 return 0;
1757}
1758
890ca9ae
HY		 1759int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1760{
1761 u64 data;
1762
1763 switch (msr) {
890ca9ae 1764 case MSR_IA32_PLATFORM_ID:
15c4a640 1765 case MSR_IA32_UCODE_REV:
15c4a640 1766 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1767 case MSR_IA32_DEBUGCTLMSR:
1768 case MSR_IA32_LASTBRANCHFROMIP:
1769 case MSR_IA32_LASTBRANCHTOIP:
1770 case MSR_IA32_LASTINTFROMIP:
1771 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1772 case MSR_K8_SYSCFG:
1773 case MSR_K7_HWCR:
61a6bd67 1774 case MSR_VM_HSAVE_PA:
1f3ee616
AS		 1775 case MSR_P6_PERFCTR0:
1776 case MSR_P6_PERFCTR1:
7fe29e0f
AS		 1777 case MSR_P6_EVNTSEL0:
1778 case MSR_P6_EVNTSEL1:
9e699624 1779 case MSR_K7_EVNTSEL0:
1f3ee616 1780 case MSR_K7_PERFCTR0:
1fdbd48c 1781 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1782 case MSR_AMD64_NB_CFG:
f7c6d140 1783 case MSR_FAM10H_MMIO_CONF_BASE:
15c4a640
CO		 1784 data = 0;
1785 break;
9ba075a6
AK		 1786 case MSR_MTRRcap:
1787 data = 0x500 | KVM_NR_VAR_MTRR;
1788 break;
1789 case 0x200 ... 0x2ff:
1790 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1791 case 0xcd: /* fsb frequency */
1792 data = 3;
1793 break;
7b914098
JS		 1794 /*
1795 * MSR_EBC_FREQUENCY_ID
1796 * Conservative value valid for even the basic CPU models.
1797 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
1798 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
1799 * and 266MHz for model 3, or 4. Set Core Clock
1800 * Frequency to System Bus Frequency Ratio to 1 (bits
1801 * 31:24) even though these are only valid for CPU
1802 * models > 2, however guests may end up dividing or
1803 * multiplying by zero otherwise.
1804 */
1805 case MSR_EBC_FREQUENCY_ID:
1806 data = 1 << 24;
1807 break;
15c4a640
CO		 1808 case MSR_IA32_APICBASE:
1809 data = kvm_get_apic_base(vcpu);
1810 break;
0105d1a5
GN		 1811 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1812 return kvm_x2apic_msr_read(vcpu, msr, pdata);
1813 break;
15c4a640 1814 case MSR_IA32_MISC_ENABLE:
ad312c7c 1815 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1816 break;
847f0ad8
AG		 1817 case MSR_IA32_PERF_STATUS:
1818 /* TSC increment by tick */
1819 data = 1000ULL;
1820 /* CPU multiplier */
1821 data |= (((uint64_t)4ULL) << 40);
1822 break;
15c4a640 1823 case MSR_EFER:
f6801dff 1824 data = vcpu->arch.efer;
15c4a640 1825 break;
18068523 1826 case MSR_KVM_WALL_CLOCK:
11c6bffa 1827 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1828 data = vcpu->kvm->arch.wall_clock;
1829 break;
1830 case MSR_KVM_SYSTEM_TIME:
11c6bffa 1831 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 1832 data = vcpu->arch.time;
1833 break;
344d9588
GN		 1834 case MSR_KVM_ASYNC_PF_EN:
1835 data = vcpu->arch.apf.msr_val;
1836 break;
890ca9ae
HY		 1837 case MSR_IA32_P5_MC_ADDR:
1838 case MSR_IA32_P5_MC_TYPE:
1839 case MSR_IA32_MCG_CAP:
1840 case MSR_IA32_MCG_CTL:
1841 case MSR_IA32_MCG_STATUS:
1842 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1843 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 1844 case MSR_K7_CLK_CTL:
1845 /*
1846 * Provide expected ramp-up count for K7. All other
1847 * are set to zero, indicating minimum divisors for
1848 * every field.
1849 *
1850 * This prevents guest kernels on AMD host with CPU
1851 * type 6, model 8 and higher from exploding due to
1852 * the rdmsr failing.
1853 */
1854 data = 0x20000000;
1855 break;
55cd8e5a
GN		 1856 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
1857 if (kvm_hv_msr_partition_wide(msr)) {
1858 int r;
1859 mutex_lock(&vcpu->kvm->lock);
1860 r = get_msr_hyperv_pw(vcpu, msr, pdata);
1861 mutex_unlock(&vcpu->kvm->lock);
1862 return r;
1863 } else
1864 return get_msr_hyperv(vcpu, msr, pdata);
1865 break;
91c9c3ed 1866 case MSR_IA32_BBL_CR_CTL3:
1867 /* This legacy MSR exists but isn't fully documented in current
1868 * silicon. It is however accessed by winxp in very narrow
1869 * scenarios where it sets bit #19, itself documented as
1870 * a "reserved" bit. Best effort attempt to source coherent
1871 * read data here should the balance of the register be
1872 * interpreted by the guest:
1873 *
1874 * L2 cache control register 3: 64GB range, 256KB size,
1875 * enabled, latency 0x1, configured
1876 */
1877 data = 0xbe702111;
1878 break;
15c4a640 1879 default:
ed85c068
AP		 1880 if (!ignore_msrs) {
1881 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1882 return 1;
1883 } else {
1884 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1885 data = 0;
1886 }
1887 break;
15c4a640
CO		 1888 }
1889 *pdata = data;
1890 return 0;
1891}
1892EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1893
313a3dc7
CO		 1894/*
1895 * Read or write a bunch of msrs. All parameters are kernel addresses.
1896 *
1897 * @return number of msrs set successfully.
1898 */
1899static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1900 struct kvm_msr_entry *entries,
1901 int (*do_msr)(struct kvm_vcpu *vcpu,
1902 unsigned index, u64 *data))
1903{
f656ce01 1904 int i, idx;
313a3dc7 1905
f656ce01 1906 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 1907 for (i = 0; i < msrs->nmsrs; ++i)
1908 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1909 break;
f656ce01 1910 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 1911
313a3dc7
CO		 1912 return i;
1913}
1914
1915/*
1916 * Read or write a bunch of msrs. Parameters are user addresses.
1917 *
1918 * @return number of msrs set successfully.
1919 */
1920static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1921 int (*do_msr)(struct kvm_vcpu *vcpu,
1922 unsigned index, u64 *data),
1923 int writeback)
1924{
1925 struct kvm_msrs msrs;
1926 struct kvm_msr_entry *entries;
1927 int r, n;
1928 unsigned size;
1929
1930 r = -EFAULT;
1931 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1932 goto out;
1933
1934 r = -E2BIG;
1935 if (msrs.nmsrs >= MAX_IO_MSRS)
1936 goto out;
1937
1938 r = -ENOMEM;
1939 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
7a73c028 1940 entries = kmalloc(size, GFP_KERNEL);
313a3dc7
CO		 1941 if (!entries)
1942 goto out;
1943
1944 r = -EFAULT;
1945 if (copy_from_user(entries, user_msrs->entries, size))
1946 goto out_free;
1947
1948 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1949 if (r < 0)
1950 goto out_free;
1951
1952 r = -EFAULT;
1953 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1954 goto out_free;
1955
1956 r = n;
1957
1958out_free:
7a73c028 1959 kfree(entries);
313a3dc7
CO		 1960out:
1961 return r;
1962}
1963
018d00d2
ZX		 1964int kvm_dev_ioctl_check_extension(long ext)
1965{
1966 int r;
1967
1968 switch (ext) {
1969 case KVM_CAP_IRQCHIP:
1970 case KVM_CAP_HLT:
1971 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1972 case KVM_CAP_SET_TSS_ADDR:
07716717 1973 case KVM_CAP_EXT_CPUID:
c8076604 1974 case KVM_CAP_CLOCKSOURCE:
7837699f 1975 case KVM_CAP_PIT:
a28e4f5a 1976 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1977 case KVM_CAP_MP_STATE:
ed848624 1978 case KVM_CAP_SYNC_MMU:
a355c85c 1979 case KVM_CAP_USER_NMI:
52d939a0 1980 case KVM_CAP_REINJECT_CONTROL:
4925663a 1981 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1982 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1983 case KVM_CAP_IRQFD:
d34e6b17 1984 case KVM_CAP_IOEVENTFD:
c5ff41ce 1985 case KVM_CAP_PIT2:
e9f42757 1986 case KVM_CAP_PIT_STATE2:
b927a3ce 1987 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 1988 case KVM_CAP_XEN_HVM:
afbcf7ab 1989 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 1990 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 1991 case KVM_CAP_HYPERV:
10388a07 1992 case KVM_CAP_HYPERV_VAPIC:
c25bc163 1993 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 1994 case KVM_CAP_PCI_SEGMENT:
a1efbe77 1995 case KVM_CAP_DEBUGREGS:
d2be1651 1996 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 1997 case KVM_CAP_XSAVE:
344d9588 1998 case KVM_CAP_ASYNC_PF:
92a1f12d 1999 case KVM_CAP_GET_TSC_KHZ:
018d00d2
ZX		 2000 r = 1;
2001 break;
542472b5
LV		 2002 case KVM_CAP_COALESCED_MMIO:
2003 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2004 break;
774ead3a
AK		 2005 case KVM_CAP_VAPIC:
2006 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2007 break;
f725230a
AK		 2008 case KVM_CAP_NR_VCPUS:
2009 r = KVM_MAX_VCPUS;
2010 break;
a988b910
AK		 2011 case KVM_CAP_NR_MEMSLOTS:
2012 r = KVM_MEMORY_SLOTS;
2013 break;
a68a6a72
MT		 2014 case KVM_CAP_PV_MMU: /* obsolete */
2015 r = 0;
2f333bcb 2016 break;
62c476c7 2017 case KVM_CAP_IOMMU:
19de40a8 2018 r = iommu_found();
62c476c7 2019 break;
890ca9ae
HY		 2020 case KVM_CAP_MCE:
2021 r = KVM_MAX_MCE_BANKS;
2022 break;
2d5b5a66
SY		 2023 case KVM_CAP_XCRS:
2024 r = cpu_has_xsave;
2025 break;
92a1f12d
JR		 2026 case KVM_CAP_TSC_CONTROL:
2027 r = kvm_has_tsc_control;
2028 break;
018d00d2
ZX		 2029 default:
2030 r = 0;
2031 break;
2032 }
2033 return r;
2034
2035}
2036
043405e1
CO		 2037long kvm_arch_dev_ioctl(struct file *filp,
2038 unsigned int ioctl, unsigned long arg)
2039{
2040 void __user *argp = (void __user *)arg;
2041 long r;
2042
2043 switch (ioctl) {
2044 case KVM_GET_MSR_INDEX_LIST: {
2045 struct kvm_msr_list __user *user_msr_list = argp;
2046 struct kvm_msr_list msr_list;
2047 unsigned n;
2048
2049 r = -EFAULT;
2050 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2051 goto out;
2052 n = msr_list.nmsrs;
2053 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2054 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2055 goto out;
2056 r = -E2BIG;
e125e7b6 2057 if (n < msr_list.nmsrs)
043405e1
CO		 2058 goto out;
2059 r = -EFAULT;
2060 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2061 num_msrs_to_save * sizeof(u32)))
2062 goto out;
e125e7b6 2063 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2064 &emulated_msrs,
2065 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2066 goto out;
2067 r = 0;
2068 break;
2069 }
674eea0f
AK		 2070 case KVM_GET_SUPPORTED_CPUID: {
2071 struct kvm_cpuid2 __user *cpuid_arg = argp;
2072 struct kvm_cpuid2 cpuid;
2073
2074 r = -EFAULT;
2075 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2076 goto out;
2077 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 2078 cpuid_arg->entries);
674eea0f
AK		 2079 if (r)
2080 goto out;
2081
2082 r = -EFAULT;
2083 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2084 goto out;
2085 r = 0;
2086 break;
2087 }
890ca9ae
HY		 2088 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2089 u64 mce_cap;
2090
2091 mce_cap = KVM_MCE_CAP_SUPPORTED;
2092 r = -EFAULT;
2093 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2094 goto out;
2095 r = 0;
2096 break;
2097 }
043405e1
CO		 2098 default:
2099 r = -EINVAL;
2100 }
2101out:
2102 return r;
2103}
2104
f5f48ee1
SY		 2105static void wbinvd_ipi(void *garbage)
2106{
2107 wbinvd();
2108}
2109
2110static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2111{
2112 return vcpu->kvm->arch.iommu_domain &&
2113 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2114}
2115
313a3dc7
CO		 2116void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2117{
f5f48ee1
SY		 2118 /* Address WBINVD may be executed by guest */
2119 if (need_emulate_wbinvd(vcpu)) {
2120 if (kvm_x86_ops->has_wbinvd_exit())
2121 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2122 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2123 smp_call_function_single(vcpu->cpu,
2124 wbinvd_ipi, NULL, 1);
2125 }
2126
313a3dc7 2127 kvm_x86_ops->vcpu_load(vcpu, cpu);
48434c20 2128 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
e48672fa 2129 /* Make sure TSC doesn't go backwards */
8f6055cb
JR		 2130 s64 tsc_delta;
2131 u64 tsc;
2132
2133 kvm_get_msr(vcpu, MSR_IA32_TSC, &tsc);
2134 tsc_delta = !vcpu->arch.last_guest_tsc ? 0 :
2135 tsc - vcpu->arch.last_guest_tsc;
2136
e48672fa
ZA		 2137 if (tsc_delta < 0)
2138 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2139 if (check_tsc_unstable()) {
e48672fa 2140 kvm_x86_ops->adjust_tsc_offset(vcpu, -tsc_delta);
c285545f 2141 vcpu->arch.tsc_catchup = 1;
c285545f 2142 }
1aa8ceef 2143 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2144 if (vcpu->cpu != cpu)
2145 kvm_migrate_timers(vcpu);
e48672fa 2146 vcpu->cpu = cpu;
6b7d7e76 2147 }
313a3dc7
CO		 2148}
2149
2150void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2151{
02daab21 2152 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2153 kvm_put_guest_fpu(vcpu);
7c4c0f4f 2154 kvm_get_msr(vcpu, MSR_IA32_TSC, &vcpu->arch.last_guest_tsc);
313a3dc7
CO		 2155}
2156
07716717 2157static int is_efer_nx(void)
313a3dc7 2158{
e286e86e 2159 unsigned long long efer = 0;
313a3dc7 2160
e286e86e 2161 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 2162 return efer & EFER_NX;
2163}
2164
2165static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
2166{
2167 int i;
2168 struct kvm_cpuid_entry2 *e, *entry;
2169
313a3dc7 2170 entry = NULL;
ad312c7c
ZX		 2171 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
2172 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 2173 if (e->function == 0x80000001) {
2174 entry = e;
2175 break;
2176 }
2177 }
07716717 2178 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 2179 entry->edx &= ~(1 << 20);
2180 printk(KERN_INFO "kvm: guest NX capability removed\n");
2181 }
2182}
2183
07716717 2184/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 2185static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
2186 struct kvm_cpuid *cpuid,
2187 struct kvm_cpuid_entry __user *entries)
07716717
DK		 2188{
2189 int r, i;
2190 struct kvm_cpuid_entry *cpuid_entries;
2191
2192 r = -E2BIG;
2193 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2194 goto out;
2195 r = -ENOMEM;
2196 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
2197 if (!cpuid_entries)
2198 goto out;
2199 r = -EFAULT;
2200 if (copy_from_user(cpuid_entries, entries,
2201 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
2202 goto out_free;
2203 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 2204 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
2205 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
2206 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
2207 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
2208 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
2209 vcpu->arch.cpuid_entries[i].index = 0;
2210 vcpu->arch.cpuid_entries[i].flags = 0;
2211 vcpu->arch.cpuid_entries[i].padding[0] = 0;
2212 vcpu->arch.cpuid_entries[i].padding[1] = 0;
2213 vcpu->arch.cpuid_entries[i].padding[2] = 0;
2214 }
2215 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 2216 cpuid_fix_nx_cap(vcpu);
2217 r = 0;
fc61b800 2218 kvm_apic_set_version(vcpu);
0e851880 2219 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 2220 update_cpuid(vcpu);
07716717
DK		 2221
2222out_free:
2223 vfree(cpuid_entries);
2224out:
2225 return r;
2226}
2227
2228static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 2229 struct kvm_cpuid2 *cpuid,
2230 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 2231{
2232 int r;
2233
2234 r = -E2BIG;
2235 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2236 goto out;
2237 r = -EFAULT;
ad312c7c 2238 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 2239 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 2240 goto out;
ad312c7c 2241 vcpu->arch.cpuid_nent = cpuid->nent;
fc61b800 2242 kvm_apic_set_version(vcpu);
0e851880 2243 kvm_x86_ops->cpuid_update(vcpu);
2acf923e 2244 update_cpuid(vcpu);
313a3dc7
CO		 2245 return 0;
2246
2247out:
2248 return r;
2249}
2250
07716717 2251static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 2252 struct kvm_cpuid2 *cpuid,
2253 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2254{
2255 int r;
2256
2257 r = -E2BIG;
ad312c7c 2258 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 2259 goto out;
2260 r = -EFAULT;
ad312c7c 2261 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 2262 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2263 goto out;
2264 return 0;
2265
2266out:
ad312c7c 2267 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 2268 return r;
2269}
2270
945ee35e
AK		 2271static void cpuid_mask(u32 *word, int wordnum)
2272{
2273 *word &= boot_cpu_data.x86_capability[wordnum];
2274}
2275
07716717 2276static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 2277 u32 index)
07716717
DK		 2278{
2279 entry->function = function;
2280 entry->index = index;
2281 cpuid_count(entry->function, entry->index,
19355475 2282 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 2283 entry->flags = 0;
2284}
2285
7faa4ee1
AK		 2286#define F(x) bit(X86_FEATURE_##x)
2287
07716717
DK		 2288static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
2289 u32 index, int *nent, int maxnent)
2290{
7faa4ee1 2291 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 2292#ifdef CONFIG_X86_64
17cc3935
SY		 2293 unsigned f_gbpages = (kvm_x86_ops->get_lpage_level() == PT_PDPE_LEVEL)
2294 ? F(GBPAGES) : 0;
7faa4ee1
AK		 2295 unsigned f_lm = F(LM);
2296#else
17cc3935 2297 unsigned f_gbpages = 0;
7faa4ee1 2298 unsigned f_lm = 0;
07716717 2299#endif
4e47c7a6 2300 unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
7faa4ee1
AK		 2301
2302 /* cpuid 1.edx */
2303 const u32 kvm_supported_word0_x86_features =
2304 F(FPU) | F(VME) | F(DE) | F(PSE) |
2305 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2306 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
2307 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2308 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
2309 0 /* Reserved, DS, ACPI */ | F(MMX) |
2310 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
2311 0 /* HTT, TM, Reserved, PBE */;
2312 /* cpuid 0x80000001.edx */
2313 const u32 kvm_supported_word1_x86_features =
2314 F(FPU) | F(VME) | F(DE) | F(PSE) |
2315 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
2316 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
2317 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
2318 F(PAT) | F(PSE36) | 0 /* Reserved */ |
2319 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
4e47c7a6 2320 F(FXSR) | F(FXSR_OPT) | f_gbpages | f_rdtscp |
7faa4ee1
AK		 2321 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
2322 /* cpuid 1.ecx */
2323 const u32 kvm_supported_word4_x86_features =
6c3f6041 2324 F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ |
d149c731
AK		 2325 0 /* DS-CPL, VMX, SMX, EST */ |
2326 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
2327 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
2328 0 /* Reserved, DCA */ | F(XMM4_1) |
0105d1a5 2329 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
6d886fd0
AP		 2330 0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) |
2331 F(F16C);
7faa4ee1 2332 /* cpuid 0x80000001.ecx */
07716717 2333 const u32 kvm_supported_word6_x86_features =
4c62a2dc 2334 F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ |
7faa4ee1 2335 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
7ef8aa72 2336 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(XOP) |
6d886fd0 2337 0 /* SKINIT, WDT, LWP */ | F(FMA4) | F(TBM);
07716717 2338
4429d5dc
B		 2339 /* cpuid 0xC0000001.edx */
2340 const u32 kvm_supported_word5_x86_features =
2341 F(XSTORE) | F(XSTORE_EN) | F(XCRYPT) | F(XCRYPT_EN) |
2342 F(ACE2) | F(ACE2_EN) | F(PHE) | F(PHE_EN) |
2343 F(PMM) | F(PMM_EN);
2344
19355475 2345 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 2346 get_cpu();
2347 do_cpuid_1_ent(entry, function, index);
2348 ++*nent;
2349
2350 switch (function) {
2351 case 0:
2acf923e 2352 entry->eax = min(entry->eax, (u32)0xd);
07716717
DK		 2353 break;
2354 case 1:
2355 entry->edx &= kvm_supported_word0_x86_features;
945ee35e 2356 cpuid_mask(&entry->edx, 0);
7faa4ee1 2357 entry->ecx &= kvm_supported_word4_x86_features;
945ee35e 2358 cpuid_mask(&entry->ecx, 4);
0d1de2d9
GN		 2359 /* we support x2apic emulation even if host does not support
2360 * it since we emulate x2apic in software */
2361 entry->ecx |= F(X2APIC);
07716717
DK		 2362 break;
2363 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
2364 * may return different values. This forces us to get_cpu() before
2365 * issuing the first command, and also to emulate this annoying behavior
2366 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
2367 case 2: {
2368 int t, times = entry->eax & 0xff;
2369
2370 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 2371 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 2372 for (t = 1; t < times && *nent < maxnent; ++t) {
2373 do_cpuid_1_ent(&entry[t], function, 0);
2374 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
2375 ++*nent;
2376 }
2377 break;
2378 }
2379 /* function 4 and 0xb have additional index. */
2380 case 4: {
14af3f3c 2381 int i, cache_type;
07716717
DK		 2382
2383 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2384 /* read more entries until cache_type is zero */
14af3f3c
HH		 2385 for (i = 1; *nent < maxnent; ++i) {
2386 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 2387 if (!cache_type)
2388 break;
14af3f3c
HH		 2389 do_cpuid_1_ent(&entry[i], function, i);
2390 entry[i].flags |=
07716717
DK		 2391 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2392 ++*nent;
2393 }
2394 break;
2395 }
2396 case 0xb: {
14af3f3c 2397 int i, level_type;
07716717
DK		 2398
2399 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2400 /* read more entries until level_type is zero */
14af3f3c 2401 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 2402 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 2403 if (!level_type)
2404 break;
14af3f3c
HH		 2405 do_cpuid_1_ent(&entry[i], function, i);
2406 entry[i].flags |=
07716717
DK		 2407 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2408 ++*nent;
2409 }
2410 break;
2411 }
2acf923e
DC		 2412 case 0xd: {
2413 int i;
2414
2415 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
20800bc9
AP		 2416 for (i = 1; *nent < maxnent && i < 64; ++i) {
2417 if (entry[i].eax == 0)
2418 continue;
2acf923e
DC		 2419 do_cpuid_1_ent(&entry[i], function, i);
2420 entry[i].flags |=
2421 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2422 ++*nent;
2423 }
2424 break;
2425 }
84478c82
GC		 2426 case KVM_CPUID_SIGNATURE: {
2427 char signature[12] = "KVMKVMKVM\0\0";
2428 u32 *sigptr = (u32 *)signature;
2429 entry->eax = 0;
2430 entry->ebx = sigptr[0];
2431 entry->ecx = sigptr[1];
2432 entry->edx = sigptr[2];
2433 break;
2434 }
2435 case KVM_CPUID_FEATURES:
2436 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) |
2437 (1 << KVM_FEATURE_NOP_IO_DELAY) |
371bcf64 2438 (1 << KVM_FEATURE_CLOCKSOURCE2) |
32918924 2439 (1 << KVM_FEATURE_ASYNC_PF) |
371bcf64 2440 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
84478c82
GC		 2441 entry->ebx = 0;
2442 entry->ecx = 0;
2443 entry->edx = 0;
2444 break;
07716717
DK		 2445 case 0x80000000:
2446 entry->eax = min(entry->eax, 0x8000001a);
2447 break;
2448 case 0x80000001:
2449 entry->edx &= kvm_supported_word1_x86_features;
945ee35e 2450 cpuid_mask(&entry->edx, 1);
07716717 2451 entry->ecx &= kvm_supported_word6_x86_features;
945ee35e 2452 cpuid_mask(&entry->ecx, 6);
07716717 2453 break;
4429d5dc
B		 2454 /*Add support for Centaur's CPUID instruction*/
2455 case 0xC0000000:
2456 /*Just support up to 0xC0000004 now*/
2457 entry->eax = min(entry->eax, 0xC0000004);
2458 break;
2459 case 0xC0000001:
2460 entry->edx &= kvm_supported_word5_x86_features;
2461 cpuid_mask(&entry->edx, 5);
2462 break;
2463 case 0xC0000002:
2464 case 0xC0000003:
2465 case 0xC0000004:
2466 /*Now nothing to do, reserved for the future*/
2467 break;
07716717 2468 }
d4330ef2
JR		 2469
2470 kvm_x86_ops->set_supported_cpuid(function, entry);
2471
07716717
DK		 2472 put_cpu();
2473}
2474
7faa4ee1
AK		 2475#undef F
2476
674eea0f 2477static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 2478 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 2479{
2480 struct kvm_cpuid_entry2 *cpuid_entries;
2481 int limit, nent = 0, r = -E2BIG;
2482 u32 func;
2483
2484 if (cpuid->nent < 1)
2485 goto out;
6a544355
AK		 2486 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
2487 cpuid->nent = KVM_MAX_CPUID_ENTRIES;
07716717
DK		 2488 r = -ENOMEM;
2489 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
2490 if (!cpuid_entries)
2491 goto out;
2492
2493 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
2494 limit = cpuid_entries[0].eax;
2495 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
2496 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2497 &nent, cpuid->nent);
07716717
DK		 2498 r = -E2BIG;
2499 if (nent >= cpuid->nent)
2500 goto out_free;
2501
2502 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
2503 limit = cpuid_entries[nent - 1].eax;
2504 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
2505 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 2506 &nent, cpuid->nent);
84478c82
GC		 2507
2508
2509
2510 r = -E2BIG;
2511 if (nent >= cpuid->nent)
2512 goto out_free;
2513
4429d5dc
B		 2514 /* Add support for Centaur's CPUID instruction. */
2515 if (boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR) {
2516 do_cpuid_ent(&cpuid_entries[nent], 0xC0000000, 0,
2517 &nent, cpuid->nent);
2518
2519 r = -E2BIG;
2520 if (nent >= cpuid->nent)
2521 goto out_free;
2522
2523 limit = cpuid_entries[nent - 1].eax;
2524 for (func = 0xC0000001;
2525 func <= limit && nent < cpuid->nent; ++func)
2526 do_cpuid_ent(&cpuid_entries[nent], func, 0,
2527 &nent, cpuid->nent);
2528
2529 r = -E2BIG;
2530 if (nent >= cpuid->nent)
2531 goto out_free;
2532 }
2533
84478c82
GC		 2534 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_SIGNATURE, 0, &nent,
2535 cpuid->nent);
2536
2537 r = -E2BIG;
2538 if (nent >= cpuid->nent)
2539 goto out_free;
2540
2541 do_cpuid_ent(&cpuid_entries[nent], KVM_CPUID_FEATURES, 0, &nent,
2542 cpuid->nent);
2543
cb007648
MM		 2544 r = -E2BIG;
2545 if (nent >= cpuid->nent)
2546 goto out_free;
2547
07716717
DK		 2548 r = -EFAULT;
2549 if (copy_to_user(entries, cpuid_entries,
19355475 2550 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 2551 goto out_free;
2552 cpuid->nent = nent;
2553 r = 0;
2554
2555out_free:
2556 vfree(cpuid_entries);
2557out:
2558 return r;
2559}
2560
313a3dc7
CO		 2561static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2562 struct kvm_lapic_state *s)
2563{
ad312c7c 2564 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2565
2566 return 0;
2567}
2568
2569static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2570 struct kvm_lapic_state *s)
2571{
ad312c7c 2572 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7 2573 kvm_apic_post_state_restore(vcpu);
cb142eb7 2574 update_cr8_intercept(vcpu);
313a3dc7
CO		 2575
2576 return 0;
2577}
2578
f77bc6a4
ZX		 2579static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2580 struct kvm_interrupt *irq)
2581{
2582 if (irq->irq < 0 || irq->irq >= 256)
2583 return -EINVAL;
2584 if (irqchip_in_kernel(vcpu->kvm))
2585 return -ENXIO;
f77bc6a4 2586
66fd3f7f 2587 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2588 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2589
f77bc6a4
ZX		 2590 return 0;
2591}
2592
c4abb7c9
JK		 2593static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2594{
c4abb7c9 2595 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2596
2597 return 0;
2598}
2599
b209749f
AK		 2600static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2601 struct kvm_tpr_access_ctl *tac)
2602{
2603 if (tac->flags)
2604 return -EINVAL;
2605 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2606 return 0;
2607}
2608
890ca9ae
HY		 2609static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2610 u64 mcg_cap)
2611{
2612 int r;
2613 unsigned bank_num = mcg_cap & 0xff, bank;
2614
2615 r = -EINVAL;
a9e38c3e 2616 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2617 goto out;
2618 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2619 goto out;
2620 r = 0;
2621 vcpu->arch.mcg_cap = mcg_cap;
2622 /* Init IA32_MCG_CTL to all 1s */
2623 if (mcg_cap & MCG_CTL_P)
2624 vcpu->arch.mcg_ctl = ~(u64)0;
2625 /* Init IA32_MCi_CTL to all 1s */
2626 for (bank = 0; bank < bank_num; bank++)
2627 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2628out:
2629 return r;
2630}
2631
2632static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2633 struct kvm_x86_mce *mce)
2634{
2635 u64 mcg_cap = vcpu->arch.mcg_cap;
2636 unsigned bank_num = mcg_cap & 0xff;
2637 u64 *banks = vcpu->arch.mce_banks;
2638
2639 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2640 return -EINVAL;
2641 /*
2642 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2643 * reporting is disabled
2644 */
2645 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2646 vcpu->arch.mcg_ctl != ~(u64)0)
2647 return 0;
2648 banks += 4 * mce->bank;
2649 /*
2650 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2651 * reporting is disabled for the bank
2652 */
2653 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2654 return 0;
2655 if (mce->status & MCI_STATUS_UC) {
2656 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2657 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2658 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2659 return 0;
2660 }
2661 if (banks[1] & MCI_STATUS_VAL)
2662 mce->status |= MCI_STATUS_OVER;
2663 banks[2] = mce->addr;
2664 banks[3] = mce->misc;
2665 vcpu->arch.mcg_status = mce->mcg_status;
2666 banks[1] = mce->status;
2667 kvm_queue_exception(vcpu, MC_VECTOR);
2668 } else if (!(banks[1] & MCI_STATUS_VAL)
2669 || !(banks[1] & MCI_STATUS_UC)) {
2670 if (banks[1] & MCI_STATUS_VAL)
2671 mce->status |= MCI_STATUS_OVER;
2672 banks[2] = mce->addr;
2673 banks[3] = mce->misc;
2674 banks[1] = mce->status;
2675 } else
2676 banks[1] |= MCI_STATUS_OVER;
2677 return 0;
2678}
2679
3cfc3092
JK		 2680static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2681 struct kvm_vcpu_events *events)
2682{
03b82a30
JK		 2683 events->exception.injected =
2684 vcpu->arch.exception.pending &&
2685 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2686 events->exception.nr = vcpu->arch.exception.nr;
2687 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2688 events->exception.pad = 0;
3cfc3092
JK		 2689 events->exception.error_code = vcpu->arch.exception.error_code;
2690
03b82a30
JK		 2691 events->interrupt.injected =
2692 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2693 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2694 events->interrupt.soft = 0;
48005f64
JK		 2695 events->interrupt.shadow =
2696 kvm_x86_ops->get_interrupt_shadow(vcpu,
2697 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2698
2699 events->nmi.injected = vcpu->arch.nmi_injected;
2700 events->nmi.pending = vcpu->arch.nmi_pending;
2701 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2702 events->nmi.pad = 0;
3cfc3092
JK		 2703
2704 events->sipi_vector = vcpu->arch.sipi_vector;
2705
dab4b911 2706 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2707 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2708 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 2709 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2710}
2711
2712static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2713 struct kvm_vcpu_events *events)
2714{
dab4b911 2715 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2716 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2717 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2718 return -EINVAL;
2719
3cfc3092
JK		 2720 vcpu->arch.exception.pending = events->exception.injected;
2721 vcpu->arch.exception.nr = events->exception.nr;
2722 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2723 vcpu->arch.exception.error_code = events->exception.error_code;
2724
2725 vcpu->arch.interrupt.pending = events->interrupt.injected;
2726 vcpu->arch.interrupt.nr = events->interrupt.nr;
2727 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2728 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2729 kvm_x86_ops->set_interrupt_shadow(vcpu,
2730 events->interrupt.shadow);
3cfc3092
JK		 2731
2732 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2733 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2734 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2735 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2736
dab4b911
JK		 2737 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2738 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092 2739
3842d135
AK		 2740 kvm_make_request(KVM_REQ_EVENT, vcpu);
2741
3cfc3092
JK		 2742 return 0;
2743}
2744
a1efbe77
JK		 2745static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2746 struct kvm_debugregs *dbgregs)
2747{
a1efbe77
JK		 2748 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2749 dbgregs->dr6 = vcpu->arch.dr6;
2750 dbgregs->dr7 = vcpu->arch.dr7;
2751 dbgregs->flags = 0;
97e69aa6 2752 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 2753}
2754
2755static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2756 struct kvm_debugregs *dbgregs)
2757{
2758 if (dbgregs->flags)
2759 return -EINVAL;
2760
a1efbe77
JK		 2761 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2762 vcpu->arch.dr6 = dbgregs->dr6;
2763 vcpu->arch.dr7 = dbgregs->dr7;
2764
a1efbe77
JK		 2765 return 0;
2766}
2767
2d5b5a66
SY		 2768static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2769 struct kvm_xsave *guest_xsave)
2770{
2771 if (cpu_has_xsave)
2772 memcpy(guest_xsave->region,
2773 &vcpu->arch.guest_fpu.state->xsave,
f45755b8 2774 xstate_size);
2d5b5a66
SY		 2775 else {
2776 memcpy(guest_xsave->region,
2777 &vcpu->arch.guest_fpu.state->fxsave,
2778 sizeof(struct i387_fxsave_struct));
2779 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2780 XSTATE_FPSSE;
2781 }
2782}
2783
2784static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2785 struct kvm_xsave *guest_xsave)
2786{
2787 u64 xstate_bv =
2788 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2789
2790 if (cpu_has_xsave)
2791 memcpy(&vcpu->arch.guest_fpu.state->xsave,
f45755b8 2792 guest_xsave->region, xstate_size);
2d5b5a66
SY		 2793 else {
2794 if (xstate_bv & ~XSTATE_FPSSE)
2795 return -EINVAL;
2796 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2797 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2798 }
2799 return 0;
2800}
2801
2802static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2803 struct kvm_xcrs *guest_xcrs)
2804{
2805 if (!cpu_has_xsave) {
2806 guest_xcrs->nr_xcrs = 0;
2807 return;
2808 }
2809
2810 guest_xcrs->nr_xcrs = 1;
2811 guest_xcrs->flags = 0;
2812 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2813 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2814}
2815
2816static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2817 struct kvm_xcrs *guest_xcrs)
2818{
2819 int i, r = 0;
2820
2821 if (!cpu_has_xsave)
2822 return -EINVAL;
2823
2824 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2825 return -EINVAL;
2826
2827 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2828 /* Only support XCR0 currently */
2829 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2830 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2831 guest_xcrs->xcrs[0].value);
2832 break;
2833 }
2834 if (r)
2835 r = -EINVAL;
2836 return r;
2837}
2838
313a3dc7
CO		 2839long kvm_arch_vcpu_ioctl(struct file *filp,
2840 unsigned int ioctl, unsigned long arg)
2841{
2842 struct kvm_vcpu *vcpu = filp->private_data;
2843 void __user *argp = (void __user *)arg;
2844 int r;
d1ac91d8
AK		 2845 union {
2846 struct kvm_lapic_state *lapic;
2847 struct kvm_xsave *xsave;
2848 struct kvm_xcrs *xcrs;
2849 void *buffer;
2850 } u;
2851
2852 u.buffer = NULL;
313a3dc7
CO		 2853 switch (ioctl) {
2854 case KVM_GET_LAPIC: {
2204ae3c
MT		 2855 r = -EINVAL;
2856 if (!vcpu->arch.apic)
2857 goto out;
d1ac91d8 2858 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 2859
b772ff36 2860 r = -ENOMEM;
d1ac91d8 2861 if (!u.lapic)
b772ff36 2862 goto out;
d1ac91d8 2863 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 2864 if (r)
2865 goto out;
2866 r = -EFAULT;
d1ac91d8 2867 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 2868 goto out;
2869 r = 0;
2870 break;
2871 }
2872 case KVM_SET_LAPIC: {
2204ae3c
MT		 2873 r = -EINVAL;
2874 if (!vcpu->arch.apic)
2875 goto out;
d1ac91d8 2876 u.lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
b772ff36 2877 r = -ENOMEM;
d1ac91d8 2878 if (!u.lapic)
b772ff36 2879 goto out;
313a3dc7 2880 r = -EFAULT;
d1ac91d8 2881 if (copy_from_user(u.lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 2882 goto out;
d1ac91d8 2883 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 2884 if (r)
2885 goto out;
2886 r = 0;
2887 break;
2888 }
f77bc6a4
ZX		 2889 case KVM_INTERRUPT: {
2890 struct kvm_interrupt irq;
2891
2892 r = -EFAULT;
2893 if (copy_from_user(&irq, argp, sizeof irq))
2894 goto out;
2895 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
2896 if (r)
2897 goto out;
2898 r = 0;
2899 break;
2900 }
c4abb7c9
JK		 2901 case KVM_NMI: {
2902 r = kvm_vcpu_ioctl_nmi(vcpu);
2903 if (r)
2904 goto out;
2905 r = 0;
2906 break;
2907 }
313a3dc7
CO		 2908 case KVM_SET_CPUID: {
2909 struct kvm_cpuid __user *cpuid_arg = argp;
2910 struct kvm_cpuid cpuid;
2911
2912 r = -EFAULT;
2913 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2914 goto out;
2915 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
2916 if (r)
2917 goto out;
2918 break;
2919 }
07716717
DK		 2920 case KVM_SET_CPUID2: {
2921 struct kvm_cpuid2 __user *cpuid_arg = argp;
2922 struct kvm_cpuid2 cpuid;
2923
2924 r = -EFAULT;
2925 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2926 goto out;
2927 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 2928 cpuid_arg->entries);
07716717
DK		 2929 if (r)
2930 goto out;
2931 break;
2932 }
2933 case KVM_GET_CPUID2: {
2934 struct kvm_cpuid2 __user *cpuid_arg = argp;
2935 struct kvm_cpuid2 cpuid;
2936
2937 r = -EFAULT;
2938 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2939 goto out;
2940 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 2941 cpuid_arg->entries);
07716717
DK		 2942 if (r)
2943 goto out;
2944 r = -EFAULT;
2945 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2946 goto out;
2947 r = 0;
2948 break;
2949 }
313a3dc7
CO		 2950 case KVM_GET_MSRS:
2951 r = msr_io(vcpu, argp, kvm_get_msr, 1);
2952 break;
2953 case KVM_SET_MSRS:
2954 r = msr_io(vcpu, argp, do_set_msr, 0);
2955 break;
b209749f
AK		 2956 case KVM_TPR_ACCESS_REPORTING: {
2957 struct kvm_tpr_access_ctl tac;
2958
2959 r = -EFAULT;
2960 if (copy_from_user(&tac, argp, sizeof tac))
2961 goto out;
2962 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
2963 if (r)
2964 goto out;
2965 r = -EFAULT;
2966 if (copy_to_user(argp, &tac, sizeof tac))
2967 goto out;
2968 r = 0;
2969 break;
2970 };
b93463aa
AK		 2971 case KVM_SET_VAPIC_ADDR: {
2972 struct kvm_vapic_addr va;
2973
2974 r = -EINVAL;
2975 if (!irqchip_in_kernel(vcpu->kvm))
2976 goto out;
2977 r = -EFAULT;
2978 if (copy_from_user(&va, argp, sizeof va))
2979 goto out;
2980 r = 0;
2981 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
2982 break;
2983 }
890ca9ae
HY		 2984 case KVM_X86_SETUP_MCE: {
2985 u64 mcg_cap;
2986
2987 r = -EFAULT;
2988 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
2989 goto out;
2990 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
2991 break;
2992 }
2993 case KVM_X86_SET_MCE: {
2994 struct kvm_x86_mce mce;
2995
2996 r = -EFAULT;
2997 if (copy_from_user(&mce, argp, sizeof mce))
2998 goto out;
2999 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3000 break;
3001 }
3cfc3092
JK		 3002 case KVM_GET_VCPU_EVENTS: {
3003 struct kvm_vcpu_events events;
3004
3005 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3006
3007 r = -EFAULT;
3008 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3009 break;
3010 r = 0;
3011 break;
3012 }
3013 case KVM_SET_VCPU_EVENTS: {
3014 struct kvm_vcpu_events events;
3015
3016 r = -EFAULT;
3017 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3018 break;
3019
3020 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3021 break;
3022 }
a1efbe77
JK		 3023 case KVM_GET_DEBUGREGS: {
3024 struct kvm_debugregs dbgregs;
3025
3026 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3027
3028 r = -EFAULT;
3029 if (copy_to_user(argp, &dbgregs,
3030 sizeof(struct kvm_debugregs)))
3031 break;
3032 r = 0;
3033 break;
3034 }
3035 case KVM_SET_DEBUGREGS: {
3036 struct kvm_debugregs dbgregs;
3037
3038 r = -EFAULT;
3039 if (copy_from_user(&dbgregs, argp,
3040 sizeof(struct kvm_debugregs)))
3041 break;
3042
3043 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3044 break;
3045 }
2d5b5a66 3046 case KVM_GET_XSAVE: {
d1ac91d8 3047 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3048 r = -ENOMEM;
d1ac91d8 3049 if (!u.xsave)
2d5b5a66
SY		 3050 break;
3051
d1ac91d8 3052 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3053
3054 r = -EFAULT;
d1ac91d8 3055 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3056 break;
3057 r = 0;
3058 break;
3059 }
3060 case KVM_SET_XSAVE: {
d1ac91d8 3061 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3062 r = -ENOMEM;
d1ac91d8 3063 if (!u.xsave)
2d5b5a66
SY		 3064 break;
3065
3066 r = -EFAULT;
d1ac91d8 3067 if (copy_from_user(u.xsave, argp, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3068 break;
3069
d1ac91d8 3070 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3071 break;
3072 }
3073 case KVM_GET_XCRS: {
d1ac91d8 3074 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3075 r = -ENOMEM;
d1ac91d8 3076 if (!u.xcrs)
2d5b5a66
SY		 3077 break;
3078
d1ac91d8 3079 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3080
3081 r = -EFAULT;
d1ac91d8 3082 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3083 sizeof(struct kvm_xcrs)))
3084 break;
3085 r = 0;
3086 break;
3087 }
3088 case KVM_SET_XCRS: {
d1ac91d8 3089 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3090 r = -ENOMEM;
d1ac91d8 3091 if (!u.xcrs)
2d5b5a66
SY		 3092 break;
3093
3094 r = -EFAULT;
d1ac91d8 3095 if (copy_from_user(u.xcrs, argp,
2d5b5a66
SY		 3096 sizeof(struct kvm_xcrs)))
3097 break;
3098
d1ac91d8 3099 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3100 break;
3101 }
92a1f12d
JR		 3102 case KVM_SET_TSC_KHZ: {
3103 u32 user_tsc_khz;
3104
3105 r = -EINVAL;
3106 if (!kvm_has_tsc_control)
3107 break;
3108
3109 user_tsc_khz = (u32)arg;
3110
3111 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3112 goto out;
3113
3114 kvm_x86_ops->set_tsc_khz(vcpu, user_tsc_khz);
3115
3116 r = 0;
3117 goto out;
3118 }
3119 case KVM_GET_TSC_KHZ: {
3120 r = -EIO;
3121 if (check_tsc_unstable())
3122 goto out;
3123
3124 r = vcpu_tsc_khz(vcpu);
3125
3126 goto out;
3127 }
313a3dc7
CO		 3128 default:
3129 r = -EINVAL;
3130 }
3131out:
d1ac91d8 3132 kfree(u.buffer);
313a3dc7
CO		 3133 return r;
3134}
3135
1fe779f8
CO		 3136static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3137{
3138 int ret;
3139
3140 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3141 return -1;
3142 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3143 return ret;
3144}
3145
b927a3ce
SY		 3146static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3147 u64 ident_addr)
3148{
3149 kvm->arch.ept_identity_map_addr = ident_addr;
3150 return 0;
3151}
3152
1fe779f8
CO		 3153static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3154 u32 kvm_nr_mmu_pages)
3155{
3156 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3157 return -EINVAL;
3158
79fac95e 3159 mutex_lock(&kvm->slots_lock);
7c8a83b7 3160 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 3161
3162 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3163 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3164
7c8a83b7 3165 spin_unlock(&kvm->mmu_lock);
79fac95e 3166 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3167 return 0;
3168}
3169
3170static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3171{
39de71ec 3172 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3173}
3174
1fe779f8
CO		 3175static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3176{
3177 int r;
3178
3179 r = 0;
3180 switch (chip->chip_id) {
3181 case KVM_IRQCHIP_PIC_MASTER:
3182 memcpy(&chip->chip.pic,
3183 &pic_irqchip(kvm)->pics[0],
3184 sizeof(struct kvm_pic_state));
3185 break;
3186 case KVM_IRQCHIP_PIC_SLAVE:
3187 memcpy(&chip->chip.pic,
3188 &pic_irqchip(kvm)->pics[1],
3189 sizeof(struct kvm_pic_state));
3190 break;
3191 case KVM_IRQCHIP_IOAPIC:
eba0226b 3192 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3193 break;
3194 default:
3195 r = -EINVAL;
3196 break;
3197 }
3198 return r;
3199}
3200
3201static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3202{
3203 int r;
3204
3205 r = 0;
3206 switch (chip->chip_id) {
3207 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3208 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3209 memcpy(&pic_irqchip(kvm)->pics[0],
3210 &chip->chip.pic,
3211 sizeof(struct kvm_pic_state));
f4f51050 3212 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3213 break;
3214 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3215 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3216 memcpy(&pic_irqchip(kvm)->pics[1],
3217 &chip->chip.pic,
3218 sizeof(struct kvm_pic_state));
f4f51050 3219 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3220 break;
3221 case KVM_IRQCHIP_IOAPIC:
eba0226b 3222 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3223 break;
3224 default:
3225 r = -EINVAL;
3226 break;
3227 }
3228 kvm_pic_update_irq(pic_irqchip(kvm));
3229 return r;
3230}
3231
e0f63cb9
SY		 3232static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3233{
3234 int r = 0;
3235
894a9c55 3236 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3237 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3238 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3239 return r;
3240}
3241
3242static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3243{
3244 int r = 0;
3245
894a9c55 3246 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3247 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3248 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3249 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3250 return r;
3251}
3252
3253static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3254{
3255 int r = 0;
3256
3257 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3258 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3259 sizeof(ps->channels));
3260 ps->flags = kvm->arch.vpit->pit_state.flags;
3261 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3262 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3263 return r;
3264}
3265
3266static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3267{
3268 int r = 0, start = 0;
3269 u32 prev_legacy, cur_legacy;
3270 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3271 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3272 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3273 if (!prev_legacy && cur_legacy)
3274 start = 1;
3275 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3276 sizeof(kvm->arch.vpit->pit_state.channels));
3277 kvm->arch.vpit->pit_state.flags = ps->flags;
3278 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3279 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3280 return r;
3281}
3282
52d939a0
MT		 3283static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3284 struct kvm_reinject_control *control)
3285{
3286 if (!kvm->arch.vpit)
3287 return -ENXIO;
894a9c55 3288 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 3289 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 3290 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3291 return 0;
3292}
3293
5bb064dc
ZX		 3294/*
3295 * Get (and clear) the dirty memory log for a memory slot.
3296 */
3297int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
3298 struct kvm_dirty_log *log)
3299{
87bf6e7d 3300 int r, i;
5bb064dc 3301 struct kvm_memory_slot *memslot;
87bf6e7d 3302 unsigned long n;
b050b015 3303 unsigned long is_dirty = 0;
5bb064dc 3304
79fac95e 3305 mutex_lock(&kvm->slots_lock);
5bb064dc 3306
b050b015
MT		 3307 r = -EINVAL;
3308 if (log->slot >= KVM_MEMORY_SLOTS)
3309 goto out;
3310
3311 memslot = &kvm->memslots->memslots[log->slot];
3312 r = -ENOENT;
3313 if (!memslot->dirty_bitmap)
3314 goto out;
3315
87bf6e7d 3316 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3317
b050b015
MT		 3318 for (i = 0; !is_dirty && i < n/sizeof(long); i++)
3319 is_dirty = memslot->dirty_bitmap[i];
5bb064dc
ZX		 3320
3321 /* If nothing is dirty, don't bother messing with page tables. */
3322 if (is_dirty) {
b050b015 3323 struct kvm_memslots *slots, *old_slots;
914ebccd 3324 unsigned long *dirty_bitmap;
b050b015 3325
515a0127
TY		 3326 dirty_bitmap = memslot->dirty_bitmap_head;
3327 if (memslot->dirty_bitmap == dirty_bitmap)
3328 dirty_bitmap += n / sizeof(long);
914ebccd 3329 memset(dirty_bitmap, 0, n);
b050b015 3330
914ebccd
TY		 3331 r = -ENOMEM;
3332 slots = kzalloc(sizeof(struct kvm_memslots), GFP_KERNEL);
515a0127 3333 if (!slots)
914ebccd 3334 goto out;
b050b015
MT		 3335 memcpy(slots, kvm->memslots, sizeof(struct kvm_memslots));
3336 slots->memslots[log->slot].dirty_bitmap = dirty_bitmap;
49c7754c 3337 slots->generation++;
b050b015
MT		 3338
3339 old_slots = kvm->memslots;
3340 rcu_assign_pointer(kvm->memslots, slots);
3341 synchronize_srcu_expedited(&kvm->srcu);
3342 dirty_bitmap = old_slots->memslots[log->slot].dirty_bitmap;
3343 kfree(old_slots);
914ebccd 3344
edde99ce
MT		 3345 spin_lock(&kvm->mmu_lock);
3346 kvm_mmu_slot_remove_write_access(kvm, log->slot);
3347 spin_unlock(&kvm->mmu_lock);
3348
914ebccd 3349 r = -EFAULT;
515a0127 3350 if (copy_to_user(log->dirty_bitmap, dirty_bitmap, n))
914ebccd 3351 goto out;
914ebccd
TY		 3352 } else {
3353 r = -EFAULT;
3354 if (clear_user(log->dirty_bitmap, n))
3355 goto out;
5bb064dc 3356 }
b050b015 3357
5bb064dc
ZX		 3358 r = 0;
3359out:
79fac95e 3360 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3361 return r;
3362}
3363
1fe779f8
CO		 3364long kvm_arch_vm_ioctl(struct file *filp,
3365 unsigned int ioctl, unsigned long arg)
3366{
3367 struct kvm *kvm = filp->private_data;
3368 void __user *argp = (void __user *)arg;
367e1319 3369 int r = -ENOTTY;
f0d66275
DH		 3370 /*
3371 * This union makes it completely explicit to gcc-3.x
3372 * that these two variables' stack usage should be
3373 * combined, not added together.
3374 */
3375 union {
3376 struct kvm_pit_state ps;
e9f42757 3377 struct kvm_pit_state2 ps2;
c5ff41ce 3378 struct kvm_pit_config pit_config;
f0d66275 3379 } u;
1fe779f8
CO		 3380
3381 switch (ioctl) {
3382 case KVM_SET_TSS_ADDR:
3383 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3384 if (r < 0)
3385 goto out;
3386 break;
b927a3ce
SY		 3387 case KVM_SET_IDENTITY_MAP_ADDR: {
3388 u64 ident_addr;
3389
3390 r = -EFAULT;
3391 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3392 goto out;
3393 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3394 if (r < 0)
3395 goto out;
3396 break;
3397 }
1fe779f8
CO		 3398 case KVM_SET_NR_MMU_PAGES:
3399 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3400 if (r)
3401 goto out;
3402 break;
3403 case KVM_GET_NR_MMU_PAGES:
3404 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3405 break;
3ddea128
MT		 3406 case KVM_CREATE_IRQCHIP: {
3407 struct kvm_pic *vpic;
3408
3409 mutex_lock(&kvm->lock);
3410 r = -EEXIST;
3411 if (kvm->arch.vpic)
3412 goto create_irqchip_unlock;
1fe779f8 3413 r = -ENOMEM;
3ddea128
MT		 3414 vpic = kvm_create_pic(kvm);
3415 if (vpic) {
1fe779f8
CO		 3416 r = kvm_ioapic_init(kvm);
3417 if (r) {
175504cd 3418 mutex_lock(&kvm->slots_lock);
72bb2fcd
WY		 3419 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3420 &vpic->dev);
175504cd 3421 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3422 kfree(vpic);
3423 goto create_irqchip_unlock;
1fe779f8
CO		 3424 }
3425 } else
3ddea128
MT		 3426 goto create_irqchip_unlock;
3427 smp_wmb();
3428 kvm->arch.vpic = vpic;
3429 smp_wmb();
399ec807
AK		 3430 r = kvm_setup_default_irq_routing(kvm);
3431 if (r) {
175504cd 3432 mutex_lock(&kvm->slots_lock);
3ddea128 3433 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3434 kvm_ioapic_destroy(kvm);
3435 kvm_destroy_pic(kvm);
3ddea128 3436 mutex_unlock(&kvm->irq_lock);
175504cd 3437 mutex_unlock(&kvm->slots_lock);
399ec807 3438 }
3ddea128
MT		 3439 create_irqchip_unlock:
3440 mutex_unlock(&kvm->lock);
1fe779f8 3441 break;
3ddea128 3442 }
7837699f 3443 case KVM_CREATE_PIT:
c5ff41ce
JK		 3444 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3445 goto create_pit;
3446 case KVM_CREATE_PIT2:
3447 r = -EFAULT;
3448 if (copy_from_user(&u.pit_config, argp,
3449 sizeof(struct kvm_pit_config)))
3450 goto out;
3451 create_pit:
79fac95e 3452 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3453 r = -EEXIST;
3454 if (kvm->arch.vpit)
3455 goto create_pit_unlock;
7837699f 3456 r = -ENOMEM;
c5ff41ce 3457 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3458 if (kvm->arch.vpit)
3459 r = 0;
269e05e4 3460 create_pit_unlock:
79fac95e 3461 mutex_unlock(&kvm->slots_lock);
7837699f 3462 break;
4925663a 3463 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 3464 case KVM_IRQ_LINE: {
3465 struct kvm_irq_level irq_event;
3466
3467 r = -EFAULT;
3468 if (copy_from_user(&irq_event, argp, sizeof irq_event))
3469 goto out;
160d2f6c 3470 r = -ENXIO;
1fe779f8 3471 if (irqchip_in_kernel(kvm)) {
4925663a 3472 __s32 status;
4925663a
GN		 3473 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3474 irq_event.irq, irq_event.level);
4925663a 3475 if (ioctl == KVM_IRQ_LINE_STATUS) {
160d2f6c 3476 r = -EFAULT;
4925663a
GN		 3477 irq_event.status = status;
3478 if (copy_to_user(argp, &irq_event,
3479 sizeof irq_event))
3480 goto out;
3481 }
1fe779f8
CO		 3482 r = 0;
3483 }
3484 break;
3485 }
3486 case KVM_GET_IRQCHIP: {
3487 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3488 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3489
f0d66275
DH		 3490 r = -ENOMEM;
3491 if (!chip)
1fe779f8 3492 goto out;
f0d66275
DH		 3493 r = -EFAULT;
3494 if (copy_from_user(chip, argp, sizeof *chip))
3495 goto get_irqchip_out;
1fe779f8
CO		 3496 r = -ENXIO;
3497 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3498 goto get_irqchip_out;
3499 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3500 if (r)
f0d66275 3501 goto get_irqchip_out;
1fe779f8 3502 r = -EFAULT;
f0d66275
DH		 3503 if (copy_to_user(argp, chip, sizeof *chip))
3504 goto get_irqchip_out;
1fe779f8 3505 r = 0;
f0d66275
DH		 3506 get_irqchip_out:
3507 kfree(chip);
3508 if (r)
3509 goto out;
1fe779f8
CO		 3510 break;
3511 }
3512 case KVM_SET_IRQCHIP: {
3513 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 3514 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 3515
f0d66275
DH		 3516 r = -ENOMEM;
3517 if (!chip)
1fe779f8 3518 goto out;
f0d66275
DH		 3519 r = -EFAULT;
3520 if (copy_from_user(chip, argp, sizeof *chip))
3521 goto set_irqchip_out;
1fe779f8
CO		 3522 r = -ENXIO;
3523 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3524 goto set_irqchip_out;
3525 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3526 if (r)
f0d66275 3527 goto set_irqchip_out;
1fe779f8 3528 r = 0;
f0d66275
DH		 3529 set_irqchip_out:
3530 kfree(chip);
3531 if (r)
3532 goto out;
1fe779f8
CO		 3533 break;
3534 }
e0f63cb9 3535 case KVM_GET_PIT: {
e0f63cb9 3536 r = -EFAULT;
f0d66275 3537 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3538 goto out;
3539 r = -ENXIO;
3540 if (!kvm->arch.vpit)
3541 goto out;
f0d66275 3542 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3543 if (r)
3544 goto out;
3545 r = -EFAULT;
f0d66275 3546 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3547 goto out;
3548 r = 0;
3549 break;
3550 }
3551 case KVM_SET_PIT: {
e0f63cb9 3552 r = -EFAULT;
f0d66275 3553 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3554 goto out;
3555 r = -ENXIO;
3556 if (!kvm->arch.vpit)
3557 goto out;
f0d66275 3558 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3559 if (r)
3560 goto out;
3561 r = 0;
3562 break;
3563 }
e9f42757
BK		 3564 case KVM_GET_PIT2: {
3565 r = -ENXIO;
3566 if (!kvm->arch.vpit)
3567 goto out;
3568 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3569 if (r)
3570 goto out;
3571 r = -EFAULT;
3572 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3573 goto out;
3574 r = 0;
3575 break;
3576 }
3577 case KVM_SET_PIT2: {
3578 r = -EFAULT;
3579 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3580 goto out;
3581 r = -ENXIO;
3582 if (!kvm->arch.vpit)
3583 goto out;
3584 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3585 if (r)
3586 goto out;
3587 r = 0;
3588 break;
3589 }
52d939a0
MT		 3590 case KVM_REINJECT_CONTROL: {
3591 struct kvm_reinject_control control;
3592 r = -EFAULT;
3593 if (copy_from_user(&control, argp, sizeof(control)))
3594 goto out;
3595 r = kvm_vm_ioctl_reinject(kvm, &control);
3596 if (r)
3597 goto out;
3598 r = 0;
3599 break;
3600 }
ffde22ac
ES		 3601 case KVM_XEN_HVM_CONFIG: {
3602 r = -EFAULT;
3603 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3604 sizeof(struct kvm_xen_hvm_config)))
3605 goto out;
3606 r = -EINVAL;
3607 if (kvm->arch.xen_hvm_config.flags)
3608 goto out;
3609 r = 0;
3610 break;
3611 }
afbcf7ab 3612 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3613 struct kvm_clock_data user_ns;
3614 u64 now_ns;
3615 s64 delta;
3616
3617 r = -EFAULT;
3618 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3619 goto out;
3620
3621 r = -EINVAL;
3622 if (user_ns.flags)
3623 goto out;
3624
3625 r = 0;
395c6b0a 3626 local_irq_disable();
759379dd 3627 now_ns = get_kernel_ns();
afbcf7ab 3628 delta = user_ns.clock - now_ns;
395c6b0a 3629 local_irq_enable();
afbcf7ab
GC		 3630 kvm->arch.kvmclock_offset = delta;
3631 break;
3632 }
3633 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3634 struct kvm_clock_data user_ns;
3635 u64 now_ns;
3636
395c6b0a 3637 local_irq_disable();
759379dd 3638 now_ns = get_kernel_ns();
afbcf7ab 3639 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3640 local_irq_enable();
afbcf7ab 3641 user_ns.flags = 0;
97e69aa6 3642 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3643
3644 r = -EFAULT;
3645 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3646 goto out;
3647 r = 0;
3648 break;
3649 }
3650
1fe779f8
CO		 3651 default:
3652 ;
3653 }
3654out:
3655 return r;
3656}
3657
a16b043c 3658static void kvm_init_msr_list(void)
043405e1
CO		 3659{
3660 u32 dummy[2];
3661 unsigned i, j;
3662
e3267cbb
GC		 3663 /* skip the first msrs in the list. KVM-specific */
3664 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3665 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3666 continue;
3667 if (j < i)
3668 msrs_to_save[j] = msrs_to_save[i];
3669 j++;
3670 }
3671 num_msrs_to_save = j;
3672}
3673
bda9020e
MT		 3674static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3675 const void *v)
bbd9b64e 3676{
70252a10
AK		 3677 int handled = 0;
3678 int n;
3679
3680 do {
3681 n = min(len, 8);
3682 if (!(vcpu->arch.apic &&
3683 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3684 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3685 break;
3686 handled += n;
3687 addr += n;
3688 len -= n;
3689 v += n;
3690 } while (len);
bbd9b64e 3691
70252a10 3692 return handled;
bbd9b64e
CO		 3693}
3694
bda9020e 3695static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3696{
70252a10
AK		 3697 int handled = 0;
3698 int n;
3699
3700 do {
3701 n = min(len, 8);
3702 if (!(vcpu->arch.apic &&
3703 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3704 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3705 break;
3706 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3707 handled += n;
3708 addr += n;
3709 len -= n;
3710 v += n;
3711 } while (len);
bbd9b64e 3712
70252a10 3713 return handled;
bbd9b64e
CO		 3714}
3715
2dafc6c2
GN		 3716static void kvm_set_segment(struct kvm_vcpu *vcpu,
3717 struct kvm_segment *var, int seg)
3718{
3719 kvm_x86_ops->set_segment(vcpu, var, seg);
3720}
3721
3722void kvm_get_segment(struct kvm_vcpu *vcpu,
3723 struct kvm_segment *var, int seg)
3724{
3725 kvm_x86_ops->get_segment(vcpu, var, seg);
3726}
3727
c30a358d
JR		 3728static gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3729{
3730 return gpa;
3731}
3732
02f59dc9
JR		 3733static gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3734{
3735 gpa_t t_gpa;
ab9ae313 3736 struct x86_exception exception;
02f59dc9
JR		 3737
3738 BUG_ON(!mmu_is_nested(vcpu));
3739
3740 /* NPT walks are always user-walks */
3741 access |= PFERR_USER_MASK;
ab9ae313 3742 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
02f59dc9
JR		 3743
3744 return t_gpa;
3745}
3746
ab9ae313
AK		 3747gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3748 struct x86_exception *exception)
1871c602
GN		 3749{
3750 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 3751 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3752}
3753
ab9ae313
AK		 3754 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3755 struct x86_exception *exception)
1871c602
GN		 3756{
3757 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3758 access |= PFERR_FETCH_MASK;
ab9ae313 3759 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3760}
3761
ab9ae313
AK		 3762gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3763 struct x86_exception *exception)
1871c602
GN		 3764{
3765 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3766 access |= PFERR_WRITE_MASK;
ab9ae313 3767 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3768}
3769
3770/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 3771gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3772 struct x86_exception *exception)
1871c602 3773{
ab9ae313 3774 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 3775}
3776
3777static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3778 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 3779 struct x86_exception *exception)
bbd9b64e
CO		 3780{
3781 void *data = val;
10589a46 3782 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3783
3784 while (bytes) {
14dfe855 3785 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 3786 exception);
bbd9b64e 3787 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3788 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3789 int ret;
3790
bcc55cba 3791 if (gpa == UNMAPPED_GVA)
ab9ae313 3792 return X86EMUL_PROPAGATE_FAULT;
77c2002e 3793 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3794 if (ret < 0) {
c3cd7ffa 3795 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3796 goto out;
3797 }
bbd9b64e 3798
77c2002e
IE		 3799 bytes -= toread;
3800 data += toread;
3801 addr += toread;
bbd9b64e 3802 }
10589a46 3803out:
10589a46 3804 return r;
bbd9b64e 3805}
77c2002e 3806
1871c602 3807/* used for instruction fetching */
0f65dd70
AK		 3808static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
3809 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3810 struct x86_exception *exception)
1871c602 3811{
0f65dd70 3812 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3813 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3814
1871c602 3815 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
bcc55cba
AK		 3816 access | PFERR_FETCH_MASK,
3817 exception);
1871c602
GN		 3818}
3819
0f65dd70
AK		 3820static int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
3821 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3822 struct x86_exception *exception)
1871c602 3823{
0f65dd70 3824 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3825 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3826
1871c602 3827 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 3828 exception);
1871c602
GN		 3829}
3830
0f65dd70
AK		 3831static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3832 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3833 struct x86_exception *exception)
1871c602 3834{
0f65dd70 3835 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 3836 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 3837}
3838
0f65dd70
AK		 3839static int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3840 gva_t addr, void *val,
2dafc6c2 3841 unsigned int bytes,
bcc55cba 3842 struct x86_exception *exception)
77c2002e 3843{
0f65dd70 3844 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 3845 void *data = val;
3846 int r = X86EMUL_CONTINUE;
3847
3848 while (bytes) {
14dfe855
JR		 3849 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3850 PFERR_WRITE_MASK,
ab9ae313 3851 exception);
77c2002e
IE		 3852 unsigned offset = addr & (PAGE_SIZE-1);
3853 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3854 int ret;
3855
bcc55cba 3856 if (gpa == UNMAPPED_GVA)
ab9ae313 3857 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 3858 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3859 if (ret < 0) {
c3cd7ffa 3860 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 3861 goto out;
3862 }
3863
3864 bytes -= towrite;
3865 data += towrite;
3866 addr += towrite;
3867 }
3868out:
3869 return r;
3870}
3871
0f65dd70
AK		 3872static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
3873 unsigned long addr,
bbd9b64e
CO		 3874 void *val,
3875 unsigned int bytes,
0f65dd70 3876 struct x86_exception *exception)
bbd9b64e 3877{
0f65dd70 3878 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bbd9b64e 3879 gpa_t gpa;
70252a10 3880 int handled;
bbd9b64e
CO		 3881
3882 if (vcpu->mmio_read_completed) {
3883 memcpy(val, vcpu->mmio_data, bytes);
aec51dc4
AK		 3884 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
3885 vcpu->mmio_phys_addr, *(u64 *)val);
bbd9b64e
CO		 3886 vcpu->mmio_read_completed = 0;
3887 return X86EMUL_CONTINUE;
3888 }
3889
ab9ae313 3890 gpa = kvm_mmu_gva_to_gpa_read(vcpu, addr, exception);
1871c602 3891
8fe681e9 3892 if (gpa == UNMAPPED_GVA)
1871c602 3893 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3894
3895 /* For APIC access vmexit */
3896 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3897 goto mmio;
3898
0f65dd70 3899 if (kvm_read_guest_virt(ctxt, addr, val, bytes, exception)
bcc55cba 3900 == X86EMUL_CONTINUE)
bbd9b64e 3901 return X86EMUL_CONTINUE;
bbd9b64e
CO		 3902
3903mmio:
3904 /*
3905 * Is this MMIO handled locally?
3906 */
70252a10
AK		 3907 handled = vcpu_mmio_read(vcpu, gpa, bytes, val);
3908
3909 if (handled == bytes)
bbd9b64e 3910 return X86EMUL_CONTINUE;
70252a10
AK		 3911
3912 gpa += handled;
3913 bytes -= handled;
3914 val += handled;
aec51dc4
AK		 3915
3916 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
bbd9b64e
CO		 3917
3918 vcpu->mmio_needed = 1;
411c35b7
GN		 3919 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3920 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
cef4dea0
AK		 3921 vcpu->mmio_size = bytes;
3922 vcpu->run->mmio.len = min(vcpu->mmio_size, 8);
411c35b7 3923 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 0;
cef4dea0 3924 vcpu->mmio_index = 0;
bbd9b64e 3925
c3cd7ffa 3926 return X86EMUL_IO_NEEDED;
bbd9b64e
CO		 3927}
3928
3200f405 3929int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 3930 const void *val, int bytes)
bbd9b64e
CO		 3931{
3932 int ret;
3933
3934 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 3935 if (ret < 0)
bbd9b64e 3936 return 0;
ad218f85 3937 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 3938 return 1;
3939}
3940
3941static int emulator_write_emulated_onepage(unsigned long addr,
3942 const void *val,
3943 unsigned int bytes,
bcc55cba 3944 struct x86_exception *exception,
bbd9b64e
CO		 3945 struct kvm_vcpu *vcpu)
3946{
10589a46 3947 gpa_t gpa;
70252a10 3948 int handled;
10589a46 3949
ab9ae313 3950 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, exception);
bbd9b64e 3951
8fe681e9 3952 if (gpa == UNMAPPED_GVA)
bbd9b64e 3953 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 3954
3955 /* For APIC access vmexit */
3956 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3957 goto mmio;
3958
3959 if (emulator_write_phys(vcpu, gpa, val, bytes))
3960 return X86EMUL_CONTINUE;
3961
3962mmio:
aec51dc4 3963 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 3964 /*
3965 * Is this MMIO handled locally?
3966 */
70252a10
AK		 3967 handled = vcpu_mmio_write(vcpu, gpa, bytes, val);
3968 if (handled == bytes)
bbd9b64e 3969 return X86EMUL_CONTINUE;
bbd9b64e 3970
70252a10
AK		 3971 gpa += handled;
3972 bytes -= handled;
3973 val += handled;
3974
bbd9b64e 3975 vcpu->mmio_needed = 1;
cef4dea0 3976 memcpy(vcpu->mmio_data, val, bytes);
411c35b7
GN		 3977 vcpu->run->exit_reason = KVM_EXIT_MMIO;
3978 vcpu->run->mmio.phys_addr = vcpu->mmio_phys_addr = gpa;
cef4dea0
AK		 3979 vcpu->mmio_size = bytes;
3980 vcpu->run->mmio.len = min(vcpu->mmio_size, 8);
411c35b7 3981 vcpu->run->mmio.is_write = vcpu->mmio_is_write = 1;
cef4dea0
AK		 3982 memcpy(vcpu->run->mmio.data, vcpu->mmio_data, 8);
3983 vcpu->mmio_index = 0;
bbd9b64e
CO		 3984
3985 return X86EMUL_CONTINUE;
3986}
3987
0f65dd70
AK		 3988int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
3989 unsigned long addr,
8f6abd06
GN		 3990 const void *val,
3991 unsigned int bytes,
0f65dd70 3992 struct x86_exception *exception)
bbd9b64e 3993{
0f65dd70
AK		 3994 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3995
bbd9b64e
CO		 3996 /* Crossing a page boundary? */
3997 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
3998 int rc, now;
3999
4000 now = -addr & ~PAGE_MASK;
bcc55cba 4001 rc = emulator_write_emulated_onepage(addr, val, now, exception,
8fe681e9 4002 vcpu);
bbd9b64e
CO		 4003 if (rc != X86EMUL_CONTINUE)
4004 return rc;
4005 addr += now;
4006 val += now;
4007 bytes -= now;
4008 }
bcc55cba 4009 return emulator_write_emulated_onepage(addr, val, bytes, exception,
8fe681e9 4010 vcpu);
bbd9b64e 4011}
bbd9b64e 4012
daea3e73
AK		 4013#define CMPXCHG_TYPE(t, ptr, old, new) \
4014 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4015
4016#ifdef CONFIG_X86_64
4017# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4018#else
4019# define CMPXCHG64(ptr, old, new) \
9749a6c0 4020 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4021#endif
4022
0f65dd70
AK		 4023static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4024 unsigned long addr,
bbd9b64e
CO		 4025 const void *old,
4026 const void *new,
4027 unsigned int bytes,
0f65dd70 4028 struct x86_exception *exception)
bbd9b64e 4029{
0f65dd70 4030 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4031 gpa_t gpa;
4032 struct page *page;
4033 char *kaddr;
4034 bool exchanged;
2bacc55c 4035
daea3e73
AK		 4036 /* guests cmpxchg8b have to be emulated atomically */
4037 if (bytes > 8 || (bytes & (bytes - 1)))
4038 goto emul_write;
10589a46 4039
daea3e73 4040 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4041
daea3e73
AK		 4042 if (gpa == UNMAPPED_GVA ||
4043 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4044 goto emul_write;
2bacc55c 4045
daea3e73
AK		 4046 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4047 goto emul_write;
72dc67a6 4048
daea3e73 4049 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
c19b8bd6
WY		 4050 if (is_error_page(page)) {
4051 kvm_release_page_clean(page);
4052 goto emul_write;
4053 }
72dc67a6 4054
daea3e73
AK		 4055 kaddr = kmap_atomic(page, KM_USER0);
4056 kaddr += offset_in_page(gpa);
4057 switch (bytes) {
4058 case 1:
4059 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4060 break;
4061 case 2:
4062 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4063 break;
4064 case 4:
4065 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4066 break;
4067 case 8:
4068 exchanged = CMPXCHG64(kaddr, old, new);
4069 break;
4070 default:
4071 BUG();
2bacc55c 4072 }
daea3e73
AK		 4073 kunmap_atomic(kaddr, KM_USER0);
4074 kvm_release_page_dirty(page);
4075
4076 if (!exchanged)
4077 return X86EMUL_CMPXCHG_FAILED;
4078
8f6abd06
GN		 4079 kvm_mmu_pte_write(vcpu, gpa, new, bytes, 1);
4080
4081 return X86EMUL_CONTINUE;
4a5f48f6 4082
3200f405 4083emul_write:
daea3e73 4084 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4085
0f65dd70 4086 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4087}
4088
cf8f70bf
GN		 4089static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4090{
4091 /* TODO: String I/O for in kernel device */
4092 int r;
4093
4094 if (vcpu->arch.pio.in)
4095 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4096 vcpu->arch.pio.size, pd);
4097 else
4098 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4099 vcpu->arch.pio.port, vcpu->arch.pio.size,
4100 pd);
4101 return r;
4102}
4103
4104
ca1d4a9e
AK		 4105static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4106 int size, unsigned short port, void *val,
4107 unsigned int count)
cf8f70bf 4108{
ca1d4a9e
AK		 4109 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4110
7972995b 4111 if (vcpu->arch.pio.count)
cf8f70bf
GN		 4112 goto data_avail;
4113
61cfab2e 4114 trace_kvm_pio(0, port, size, count);
cf8f70bf
GN		 4115
4116 vcpu->arch.pio.port = port;
4117 vcpu->arch.pio.in = 1;
7972995b 4118 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4119 vcpu->arch.pio.size = size;
4120
4121 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4122 data_avail:
4123 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 4124 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4125 return 1;
4126 }
4127
4128 vcpu->run->exit_reason = KVM_EXIT_IO;
4129 vcpu->run->io.direction = KVM_EXIT_IO_IN;
4130 vcpu->run->io.size = size;
4131 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4132 vcpu->run->io.count = count;
4133 vcpu->run->io.port = port;
4134
4135 return 0;
4136}
4137
ca1d4a9e
AK		 4138static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4139 int size, unsigned short port,
4140 const void *val, unsigned int count)
cf8f70bf 4141{
ca1d4a9e
AK		 4142 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4143
61cfab2e 4144 trace_kvm_pio(1, port, size, count);
cf8f70bf
GN		 4145
4146 vcpu->arch.pio.port = port;
4147 vcpu->arch.pio.in = 0;
7972995b 4148 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4149 vcpu->arch.pio.size = size;
4150
4151 memcpy(vcpu->arch.pio_data, val, size * count);
4152
4153 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4154 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4155 return 1;
4156 }
4157
4158 vcpu->run->exit_reason = KVM_EXIT_IO;
4159 vcpu->run->io.direction = KVM_EXIT_IO_OUT;
4160 vcpu->run->io.size = size;
4161 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4162 vcpu->run->io.count = count;
4163 vcpu->run->io.port = port;
4164
4165 return 0;
4166}
4167
bbd9b64e
CO		 4168static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4169{
4170 return kvm_x86_ops->get_segment_base(vcpu, seg);
4171}
4172
3cb16fe7 4173static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4174{
3cb16fe7 4175 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4176}
4177
f5f48ee1
SY		 4178int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4179{
4180 if (!need_emulate_wbinvd(vcpu))
4181 return X86EMUL_CONTINUE;
4182
4183 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4184 int cpu = get_cpu();
4185
4186 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4187 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4188 wbinvd_ipi, NULL, 1);
2eec7343 4189 put_cpu();
f5f48ee1 4190 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4191 } else
4192 wbinvd();
f5f48ee1
SY		 4193 return X86EMUL_CONTINUE;
4194}
4195EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4196
bcaf5cc5
AK		 4197static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4198{
4199 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4200}
4201
717746e3 4202int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
bbd9b64e 4203{
717746e3 4204 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4205}
4206
717746e3 4207int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
bbd9b64e 4208{
338dbc97 4209
717746e3 4210 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4211}
4212
52a46617 4213static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4214{
52a46617 4215 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4216}
4217
717746e3 4218static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4219{
717746e3 4220 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4221 unsigned long value;
4222
4223 switch (cr) {
4224 case 0:
4225 value = kvm_read_cr0(vcpu);
4226 break;
4227 case 2:
4228 value = vcpu->arch.cr2;
4229 break;
4230 case 3:
9f8fe504 4231 value = kvm_read_cr3(vcpu);
52a46617
GN		 4232 break;
4233 case 4:
4234 value = kvm_read_cr4(vcpu);
4235 break;
4236 case 8:
4237 value = kvm_get_cr8(vcpu);
4238 break;
4239 default:
4240 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
4241 return 0;
4242 }
4243
4244 return value;
4245}
4246
717746e3 4247static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4248{
717746e3 4249 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4250 int res = 0;
4251
52a46617
GN		 4252 switch (cr) {
4253 case 0:
49a9b07e 4254 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4255 break;
4256 case 2:
4257 vcpu->arch.cr2 = val;
4258 break;
4259 case 3:
2390218b 4260 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4261 break;
4262 case 4:
a83b29c6 4263 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4264 break;
4265 case 8:
eea1cff9 4266 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4267 break;
4268 default:
4269 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
0f12244f 4270 res = -1;
52a46617 4271 }
0f12244f
GN		 4272
4273 return res;
52a46617
GN		 4274}
4275
717746e3 4276static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4277{
717746e3 4278 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4279}
4280
4bff1e86 4281static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4282{
4bff1e86 4283 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4284}
4285
4bff1e86 4286static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4287{
4bff1e86 4288 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4289}
4290
1ac9d0cf
AK		 4291static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4292{
4293 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4294}
4295
4296static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4297{
4298 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4299}
4300
4bff1e86
AK		 4301static unsigned long emulator_get_cached_segment_base(
4302 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4303{
4bff1e86 4304 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4305}
4306
1aa36616
AK		 4307static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4308 struct desc_struct *desc, u32 *base3,
4309 int seg)
2dafc6c2
GN		 4310{
4311 struct kvm_segment var;
4312
4bff1e86 4313 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4314 *selector = var.selector;
2dafc6c2
GN		 4315
4316 if (var.unusable)
4317 return false;
4318
4319 if (var.g)
4320 var.limit >>= 12;
4321 set_desc_limit(desc, var.limit);
4322 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4323#ifdef CONFIG_X86_64
4324 if (base3)
4325 *base3 = var.base >> 32;
4326#endif
2dafc6c2
GN		 4327 desc->type = var.type;
4328 desc->s = var.s;
4329 desc->dpl = var.dpl;
4330 desc->p = var.present;
4331 desc->avl = var.avl;
4332 desc->l = var.l;
4333 desc->d = var.db;
4334 desc->g = var.g;
4335
4336 return true;
4337}
4338
1aa36616
AK		 4339static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4340 struct desc_struct *desc, u32 base3,
4341 int seg)
2dafc6c2 4342{
4bff1e86 4343 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4344 struct kvm_segment var;
4345
1aa36616 4346 var.selector = selector;
2dafc6c2 4347 var.base = get_desc_base(desc);
5601d05b
GN		 4348#ifdef CONFIG_X86_64
4349 var.base |= ((u64)base3) << 32;
4350#endif
2dafc6c2
GN		 4351 var.limit = get_desc_limit(desc);
4352 if (desc->g)
4353 var.limit = (var.limit << 12) | 0xfff;
4354 var.type = desc->type;
4355 var.present = desc->p;
4356 var.dpl = desc->dpl;
4357 var.db = desc->d;
4358 var.s = desc->s;
4359 var.l = desc->l;
4360 var.g = desc->g;
4361 var.avl = desc->avl;
4362 var.present = desc->p;
4363 var.unusable = !var.present;
4364 var.padding = 0;
4365
4366 kvm_set_segment(vcpu, &var, seg);
4367 return;
4368}
4369
717746e3
AK		 4370static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4371 u32 msr_index, u64 *pdata)
4372{
4373 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4374}
4375
4376static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4377 u32 msr_index, u64 data)
4378{
4379 return kvm_set_msr(emul_to_vcpu(ctxt), msr_index, data);
4380}
4381
6c3287f7
AK		 4382static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4383{
4384 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4385}
4386
5037f6f3
AK		 4387static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4388{
4389 preempt_disable();
5197b808 4390 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4391 /*
4392 * CR0.TS may reference the host fpu state, not the guest fpu state,
4393 * so it may be clear at this point.
4394 */
4395 clts();
4396}
4397
4398static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4399{
4400 preempt_enable();
4401}
4402
2953538e 4403static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4404 struct x86_instruction_info *info,
c4f035c6
AK		 4405 enum x86_intercept_stage stage)
4406{
2953538e 4407 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4408}
4409
14af3f3c 4410static struct x86_emulate_ops emulate_ops = {
1871c602 4411 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4412 .write_std = kvm_write_guest_virt_system,
1871c602 4413 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4414 .read_emulated = emulator_read_emulated,
4415 .write_emulated = emulator_write_emulated,
4416 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4417 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4418 .pio_in_emulated = emulator_pio_in_emulated,
4419 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4420 .get_segment = emulator_get_segment,
4421 .set_segment = emulator_set_segment,
5951c442 4422 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4423 .get_gdt = emulator_get_gdt,
160ce1f1 4424 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4425 .set_gdt = emulator_set_gdt,
4426 .set_idt = emulator_set_idt,
52a46617
GN		 4427 .get_cr = emulator_get_cr,
4428 .set_cr = emulator_set_cr,
9c537244 4429 .cpl = emulator_get_cpl,
35aa5375
GN		 4430 .get_dr = emulator_get_dr,
4431 .set_dr = emulator_set_dr,
717746e3
AK		 4432 .set_msr = emulator_set_msr,
4433 .get_msr = emulator_get_msr,
6c3287f7 4434 .halt = emulator_halt,
bcaf5cc5 4435 .wbinvd = emulator_wbinvd,
d6aa1000 4436 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4437 .get_fpu = emulator_get_fpu,
4438 .put_fpu = emulator_put_fpu,
c4f035c6 4439 .intercept = emulator_intercept,
bbd9b64e
CO		 4440};
4441
5fdbf976
MT		 4442static void cache_all_regs(struct kvm_vcpu *vcpu)
4443{
4444 kvm_register_read(vcpu, VCPU_REGS_RAX);
4445 kvm_register_read(vcpu, VCPU_REGS_RSP);
4446 kvm_register_read(vcpu, VCPU_REGS_RIP);
4447 vcpu->arch.regs_dirty = ~0;
4448}
4449
95cb2295
GN		 4450static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4451{
4452 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4453 /*
4454 * an sti; sti; sequence only disable interrupts for the first
4455 * instruction. So, if the last instruction, be it emulated or
4456 * not, left the system with the INT_STI flag enabled, it
4457 * means that the last instruction is an sti. We should not
4458 * leave the flag on in this case. The same goes for mov ss
4459 */
4460 if (!(int_shadow & mask))
4461 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4462}
4463
54b8486f
GN		 4464static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4465{
4466 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4467 if (ctxt->exception.vector == PF_VECTOR)
6389ee94 4468 kvm_propagate_fault(vcpu, &ctxt->exception);
da9cb575
AK		 4469 else if (ctxt->exception.error_code_valid)
4470 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4471 ctxt->exception.error_code);
54b8486f 4472 else
da9cb575 4473 kvm_queue_exception(vcpu, ctxt->exception.vector);
54b8486f
GN		 4474}
4475
8ec4722d
MG		 4476static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4477{
4478 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
4479 int cs_db, cs_l;
4480
2aab2c5b
GN		 4481 /*
4482 * TODO: fix emulate.c to use guest_read/write_register
4483 * instead of direct ->regs accesses, can save hundred cycles
4484 * on Intel for instructions that don't read/change RSP, for
4485 * for example.
4486 */
8ec4722d
MG		 4487 cache_all_regs(vcpu);
4488
4489 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4490
f6e78475 4491 vcpu->arch.emulate_ctxt.eflags = kvm_get_rflags(vcpu);
8ec4722d
MG		 4492 vcpu->arch.emulate_ctxt.eip = kvm_rip_read(vcpu);
4493 vcpu->arch.emulate_ctxt.mode =
4494 (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4495 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
4496 ? X86EMUL_MODE_VM86 : cs_l
4497 ? X86EMUL_MODE_PROT64 : cs_db
4498 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
c4f035c6 4499 vcpu->arch.emulate_ctxt.guest_mode = is_guest_mode(vcpu);
8ec4722d
MG		 4500 memset(c, 0, sizeof(struct decode_cache));
4501 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
7ae441ea 4502 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4503}
4504
71f9833b 4505int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653
MG		 4506{
4507 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
4508 int ret;
4509
4510 init_emulate_ctxt(vcpu);
4511
4512 vcpu->arch.emulate_ctxt.decode.op_bytes = 2;
4513 vcpu->arch.emulate_ctxt.decode.ad_bytes = 2;
71f9833b
SH		 4514 vcpu->arch.emulate_ctxt.decode.eip = vcpu->arch.emulate_ctxt.eip +
4515 inc_eip;
7b105ca2 4516 ret = emulate_int_real(&vcpu->arch.emulate_ctxt, irq);
63995653
MG		 4517
4518 if (ret != X86EMUL_CONTINUE)
4519 return EMULATE_FAIL;
4520
4521 vcpu->arch.emulate_ctxt.eip = c->eip;
4522 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
4523 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
f6e78475 4524 kvm_set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
63995653
MG		 4525
4526 if (irq == NMI_VECTOR)
4527 vcpu->arch.nmi_pending = false;
4528 else
4529 vcpu->arch.interrupt.pending = false;
4530
4531 return EMULATE_DONE;
4532}
4533EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4534
6d77dbfc
GN		 4535static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4536{
fc3a9157
JR		 4537 int r = EMULATE_DONE;
4538
6d77dbfc
GN		 4539 ++vcpu->stat.insn_emulation_fail;
4540 trace_kvm_emulate_insn_failed(vcpu);
fc3a9157
JR		 4541 if (!is_guest_mode(vcpu)) {
4542 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4543 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4544 vcpu->run->internal.ndata = 0;
4545 r = EMULATE_FAIL;
4546 }
6d77dbfc 4547 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4548
4549 return r;
6d77dbfc
GN		 4550}
4551
a6f177ef
GN		 4552static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t gva)
4553{
4554 gpa_t gpa;
4555
68be0803
GN		 4556 if (tdp_enabled)
4557 return false;
4558
a6f177ef
GN		 4559 /*
4560 * if emulation was due to access to shadowed page table
4561 * and it failed try to unshadow page and re-entetr the
4562 * guest to let CPU execute the instruction.
4563 */
4564 if (kvm_mmu_unprotect_page_virt(vcpu, gva))
4565 return true;
4566
4567 gpa = kvm_mmu_gva_to_gpa_system(vcpu, gva, NULL);
4568
4569 if (gpa == UNMAPPED_GVA)
4570 return true; /* let cpu generate fault */
4571
4572 if (!kvm_is_error_hva(gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT)))
4573 return true;
4574
4575 return false;
4576}
4577
51d8b661
AP		 4578int x86_emulate_instruction(struct kvm_vcpu *vcpu,
4579 unsigned long cr2,
dc25e89e
AP		 4580 int emulation_type,
4581 void *insn,
4582 int insn_len)
bbd9b64e 4583{
95cb2295 4584 int r;
4d2179e1 4585 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
7ae441ea 4586 bool writeback = true;
bbd9b64e 4587
26eef70c 4588 kvm_clear_exception_queue(vcpu);
8d7d8102 4589
571008da 4590 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 4591 init_emulate_ctxt(vcpu);
95cb2295 4592 vcpu->arch.emulate_ctxt.interruptibility = 0;
da9cb575 4593 vcpu->arch.emulate_ctxt.have_exception = false;
4fc40f07 4594 vcpu->arch.emulate_ctxt.perm_ok = false;
bbd9b64e 4595
4005996e
AK		 4596 vcpu->arch.emulate_ctxt.only_vendor_specific_insn
4597 = emulation_type & EMULTYPE_TRAP_UD;
4598
dc25e89e 4599 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, insn, insn_len);
bbd9b64e 4600
e46479f8 4601 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 4602 ++vcpu->stat.insn_emulation;
bbd9b64e 4603 if (r) {
4005996e
AK		 4604 if (emulation_type & EMULTYPE_TRAP_UD)
4605 return EMULATE_FAIL;
a6f177ef 4606 if (reexecute_instruction(vcpu, cr2))
bbd9b64e 4607 return EMULATE_DONE;
6d77dbfc
GN		 4608 if (emulation_type & EMULTYPE_SKIP)
4609 return EMULATE_FAIL;
4610 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4611 }
4612 }
4613
ba8afb6b
GN		 4614 if (emulation_type & EMULTYPE_SKIP) {
4615 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
4616 return EMULATE_DONE;
4617 }
4618
7ae441ea 4619 /* this is needed for vmware backdoor interface to work since it
4d2179e1 4620 changes registers values during IO operation */
7ae441ea
GN		 4621 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
4622 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
4623 memcpy(c->regs, vcpu->arch.regs, sizeof c->regs);
4624 }
4d2179e1 4625
5cd21917 4626restart:
9aabc88f 4627 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt);
bbd9b64e 4628
775fde86
JR		 4629 if (r == EMULATION_INTERCEPTED)
4630 return EMULATE_DONE;
4631
d2ddd1c4 4632 if (r == EMULATION_FAILED) {
a6f177ef 4633 if (reexecute_instruction(vcpu, cr2))
c3cd7ffa
GN		 4634 return EMULATE_DONE;
4635
6d77dbfc 4636 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4637 }
4638
da9cb575 4639 if (vcpu->arch.emulate_ctxt.have_exception) {
54b8486f 4640 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 4641 r = EMULATE_DONE;
4642 } else if (vcpu->arch.pio.count) {
3457e419
GN		 4643 if (!vcpu->arch.pio.in)
4644 vcpu->arch.pio.count = 0;
7ae441ea
GN		 4645 else
4646 writeback = false;
e85d28f8 4647 r = EMULATE_DO_MMIO;
7ae441ea
GN		 4648 } else if (vcpu->mmio_needed) {
4649 if (!vcpu->mmio_is_write)
4650 writeback = false;
e85d28f8 4651 r = EMULATE_DO_MMIO;
7ae441ea 4652 } else if (r == EMULATION_RESTART)
5cd21917 4653 goto restart;
d2ddd1c4
GN		 4654 else
4655 r = EMULATE_DONE;
f850e2e6 4656
7ae441ea
GN		 4657 if (writeback) {
4658 toggle_interruptibility(vcpu,
4659 vcpu->arch.emulate_ctxt.interruptibility);
4660 kvm_set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
4661 kvm_make_request(KVM_REQ_EVENT, vcpu);
4662 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
4663 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
4664 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
4665 } else
4666 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 4667
4668 return r;
de7d789a 4669}
51d8b661 4670EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 4671
cf8f70bf 4672int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 4673{
cf8f70bf 4674 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 4675 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
4676 size, port, &val, 1);
cf8f70bf 4677 /* do not return to emulator after return from userspace */
7972995b 4678 vcpu->arch.pio.count = 0;
de7d789a
CO		 4679 return ret;
4680}
cf8f70bf 4681EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 4682
8cfdc000
ZA		 4683static void tsc_bad(void *info)
4684{
0a3aee0d 4685 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 4686}
4687
4688static void tsc_khz_changed(void *data)
c8076604 4689{
8cfdc000
ZA		 4690 struct cpufreq_freqs *freq = data;
4691 unsigned long khz = 0;
4692
4693 if (data)
4694 khz = freq->new;
4695 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4696 khz = cpufreq_quick_get(raw_smp_processor_id());
4697 if (!khz)
4698 khz = tsc_khz;
0a3aee0d 4699 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 4700}
4701
c8076604
GH		 4702static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
4703 void *data)
4704{
4705 struct cpufreq_freqs *freq = data;
4706 struct kvm *kvm;
4707 struct kvm_vcpu *vcpu;
4708 int i, send_ipi = 0;
4709
8cfdc000
ZA		 4710 /*
4711 * We allow guests to temporarily run on slowing clocks,
4712 * provided we notify them after, or to run on accelerating
4713 * clocks, provided we notify them before. Thus time never
4714 * goes backwards.
4715 *
4716 * However, we have a problem. We can't atomically update
4717 * the frequency of a given CPU from this function; it is
4718 * merely a notifier, which can be called from any CPU.
4719 * Changing the TSC frequency at arbitrary points in time
4720 * requires a recomputation of local variables related to
4721 * the TSC for each VCPU. We must flag these local variables
4722 * to be updated and be sure the update takes place with the
4723 * new frequency before any guests proceed.
4724 *
4725 * Unfortunately, the combination of hotplug CPU and frequency
4726 * change creates an intractable locking scenario; the order
4727 * of when these callouts happen is undefined with respect to
4728 * CPU hotplug, and they can race with each other. As such,
4729 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
4730 * undefined; you can actually have a CPU frequency change take
4731 * place in between the computation of X and the setting of the
4732 * variable. To protect against this problem, all updates of
4733 * the per_cpu tsc_khz variable are done in an interrupt
4734 * protected IPI, and all callers wishing to update the value
4735 * must wait for a synchronous IPI to complete (which is trivial
4736 * if the caller is on the CPU already). This establishes the
4737 * necessary total order on variable updates.
4738 *
4739 * Note that because a guest time update may take place
4740 * anytime after the setting of the VCPU's request bit, the
4741 * correct TSC value must be set before the request. However,
4742 * to ensure the update actually makes it to any guest which
4743 * starts running in hardware virtualization between the set
4744 * and the acquisition of the spinlock, we must also ping the
4745 * CPU after setting the request bit.
4746 *
4747 */
4748
c8076604
GH		 4749 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
4750 return 0;
4751 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
4752 return 0;
8cfdc000
ZA		 4753
4754 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 4755
e935b837 4756 raw_spin_lock(&kvm_lock);
c8076604 4757 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 4758 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 4759 if (vcpu->cpu != freq->cpu)
4760 continue;
c285545f 4761 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 4762 if (vcpu->cpu != smp_processor_id())
8cfdc000 4763 send_ipi = 1;
c8076604
GH		 4764 }
4765 }
e935b837 4766 raw_spin_unlock(&kvm_lock);
c8076604
GH		 4767
4768 if (freq->old < freq->new && send_ipi) {
4769 /*
4770 * We upscale the frequency. Must make the guest
4771 * doesn't see old kvmclock values while running with
4772 * the new frequency, otherwise we risk the guest sees
4773 * time go backwards.
4774 *
4775 * In case we update the frequency for another cpu
4776 * (which might be in guest context) send an interrupt
4777 * to kick the cpu out of guest context. Next time
4778 * guest context is entered kvmclock will be updated,
4779 * so the guest will not see stale values.
4780 */
8cfdc000 4781 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 4782 }
4783 return 0;
4784}
4785
4786static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 4787 .notifier_call = kvmclock_cpufreq_notifier
4788};
4789
4790static int kvmclock_cpu_notifier(struct notifier_block *nfb,
4791 unsigned long action, void *hcpu)
4792{
4793 unsigned int cpu = (unsigned long)hcpu;
4794
4795 switch (action) {
4796 case CPU_ONLINE:
4797 case CPU_DOWN_FAILED:
4798 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
4799 break;
4800 case CPU_DOWN_PREPARE:
4801 smp_call_function_single(cpu, tsc_bad, NULL, 1);
4802 break;
4803 }
4804 return NOTIFY_OK;
4805}
4806
4807static struct notifier_block kvmclock_cpu_notifier_block = {
4808 .notifier_call = kvmclock_cpu_notifier,
4809 .priority = -INT_MAX
c8076604
GH		 4810};
4811
b820cc0c
ZA		 4812static void kvm_timer_init(void)
4813{
4814 int cpu;
4815
c285545f 4816 max_tsc_khz = tsc_khz;
8cfdc000 4817 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 4818 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 4819#ifdef CONFIG_CPU_FREQ
4820 struct cpufreq_policy policy;
4821 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 4822 cpu = get_cpu();
4823 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 4824 if (policy.cpuinfo.max_freq)
4825 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 4826 put_cpu();
c285545f 4827#endif
b820cc0c
ZA		 4828 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
4829 CPUFREQ_TRANSITION_NOTIFIER);
4830 }
c285545f 4831 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 4832 for_each_online_cpu(cpu)
4833 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 4834}
4835
ff9d07a0
ZY		 4836static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
4837
4838static int kvm_is_in_guest(void)
4839{
4840 return percpu_read(current_vcpu) != NULL;
4841}
4842
4843static int kvm_is_user_mode(void)
4844{
4845 int user_mode = 3;
dcf46b94 4846
ff9d07a0
ZY		 4847 if (percpu_read(current_vcpu))
4848 user_mode = kvm_x86_ops->get_cpl(percpu_read(current_vcpu));
dcf46b94 4849
ff9d07a0
ZY		 4850 return user_mode != 0;
4851}
4852
4853static unsigned long kvm_get_guest_ip(void)
4854{
4855 unsigned long ip = 0;
dcf46b94 4856
ff9d07a0
ZY		 4857 if (percpu_read(current_vcpu))
4858 ip = kvm_rip_read(percpu_read(current_vcpu));
dcf46b94 4859
ff9d07a0
ZY		 4860 return ip;
4861}
4862
4863static struct perf_guest_info_callbacks kvm_guest_cbs = {
4864 .is_in_guest = kvm_is_in_guest,
4865 .is_user_mode = kvm_is_user_mode,
4866 .get_guest_ip = kvm_get_guest_ip,
4867};
4868
4869void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
4870{
4871 percpu_write(current_vcpu, vcpu);
4872}
4873EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
4874
4875void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
4876{
4877 percpu_write(current_vcpu, NULL);
4878}
4879EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
4880
f8c16bba 4881int kvm_arch_init(void *opaque)
043405e1 4882{
b820cc0c 4883 int r;
f8c16bba
ZX		 4884 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
4885
f8c16bba
ZX		 4886 if (kvm_x86_ops) {
4887 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 4888 r = -EEXIST;
4889 goto out;
f8c16bba
ZX		 4890 }
4891
4892 if (!ops->cpu_has_kvm_support()) {
4893 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 4894 r = -EOPNOTSUPP;
4895 goto out;
f8c16bba
ZX		 4896 }
4897 if (ops->disabled_by_bios()) {
4898 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 4899 r = -EOPNOTSUPP;
4900 goto out;
f8c16bba
ZX		 4901 }
4902
97db56ce
AK		 4903 r = kvm_mmu_module_init();
4904 if (r)
4905 goto out;
4906
4907 kvm_init_msr_list();
4908
f8c16bba 4909 kvm_x86_ops = ops;
56c6d28a 4910 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e 4911 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 4912 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 4913
b820cc0c 4914 kvm_timer_init();
c8076604 4915
ff9d07a0
ZY		 4916 perf_register_guest_info_callbacks(&kvm_guest_cbs);
4917
2acf923e
DC		 4918 if (cpu_has_xsave)
4919 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
4920
f8c16bba 4921 return 0;
56c6d28a
ZX		 4922
4923out:
56c6d28a 4924 return r;
043405e1 4925}
8776e519 4926
f8c16bba
ZX		 4927void kvm_arch_exit(void)
4928{
ff9d07a0
ZY		 4929 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
4930
888d256e
JK		 4931 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
4932 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
4933 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 4934 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
f8c16bba 4935 kvm_x86_ops = NULL;
56c6d28a
ZX		 4936 kvm_mmu_module_exit();
4937}
f8c16bba 4938
8776e519
HB		 4939int kvm_emulate_halt(struct kvm_vcpu *vcpu)
4940{
4941 ++vcpu->stat.halt_exits;
4942 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 4943 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 4944 return 1;
4945 } else {
4946 vcpu->run->exit_reason = KVM_EXIT_HLT;
4947 return 0;
4948 }
4949}
4950EXPORT_SYMBOL_GPL(kvm_emulate_halt);
4951
2f333bcb
MT		 4952static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
4953 unsigned long a1)
4954{
4955 if (is_long_mode(vcpu))
4956 return a0;
4957 else
4958 return a0 | ((gpa_t)a1 << 32);
4959}
4960
55cd8e5a
GN		 4961int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
4962{
4963 u64 param, ingpa, outgpa, ret;
4964 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
4965 bool fast, longmode;
4966 int cs_db, cs_l;
4967
4968 /*
4969 * hypercall generates UD from non zero cpl and real mode
4970 * per HYPER-V spec
4971 */
3eeb3288 4972 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 4973 kvm_queue_exception(vcpu, UD_VECTOR);
4974 return 0;
4975 }
4976
4977 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4978 longmode = is_long_mode(vcpu) && cs_l == 1;
4979
4980 if (!longmode) {
ccd46936
GN		 4981 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
4982 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
4983 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
4984 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
4985 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
4986 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 4987 }
4988#ifdef CONFIG_X86_64
4989 else {
4990 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
4991 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
4992 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
4993 }
4994#endif
4995
4996 code = param & 0xffff;
4997 fast = (param >> 16) & 0x1;
4998 rep_cnt = (param >> 32) & 0xfff;
4999 rep_idx = (param >> 48) & 0xfff;
5000
5001 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5002
c25bc163
GN		 5003 switch (code) {
5004 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5005 kvm_vcpu_on_spin(vcpu);
5006 break;
5007 default:
5008 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5009 break;
5010 }
55cd8e5a
GN		 5011
5012 ret = res | (((u64)rep_done & 0xfff) << 32);
5013 if (longmode) {
5014 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5015 } else {
5016 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5017 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5018 }
5019
5020 return 1;
5021}
5022
8776e519
HB		 5023int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5024{
5025 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 5026 int r = 1;
8776e519 5027
55cd8e5a
GN		 5028 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5029 return kvm_hv_hypercall(vcpu);
5030
5fdbf976
MT		 5031 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5032 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5033 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5034 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5035 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5036
229456fc 5037 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5038
8776e519
HB		 5039 if (!is_long_mode(vcpu)) {
5040 nr &= 0xFFFFFFFF;
5041 a0 &= 0xFFFFFFFF;
5042 a1 &= 0xFFFFFFFF;
5043 a2 &= 0xFFFFFFFF;
5044 a3 &= 0xFFFFFFFF;
5045 }
5046
07708c4a
JK		 5047 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5048 ret = -KVM_EPERM;
5049 goto out;
5050 }
5051
8776e519 5052 switch (nr) {
b93463aa
AK		 5053 case KVM_HC_VAPIC_POLL_IRQ:
5054 ret = 0;
5055 break;
2f333bcb
MT		 5056 case KVM_HC_MMU_OP:
5057 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
5058 break;
8776e519
HB		 5059 default:
5060 ret = -KVM_ENOSYS;
5061 break;
5062 }
07708c4a 5063out:
5fdbf976 5064 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5065 ++vcpu->stat.hypercalls;
2f333bcb 5066 return r;
8776e519
HB		 5067}
5068EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5069
d6aa1000 5070int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5071{
d6aa1000 5072 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5073 char instruction[3];
5fdbf976 5074 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5075
8776e519
HB		 5076 /*
5077 * Blow out the MMU to ensure that no other VCPU has an active mapping
5078 * to ensure that the updated hypercall appears atomically across all
5079 * VCPUs.
5080 */
5081 kvm_mmu_zap_all(vcpu->kvm);
5082
8776e519 5083 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5084
0f65dd70
AK		 5085 return emulator_write_emulated(&vcpu->arch.emulate_ctxt,
5086 rip, instruction, 3, NULL);
8776e519
HB		 5087}
5088
07716717
DK		 5089static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
5090{
ad312c7c
ZX		 5091 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
5092 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 5093
5094 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
5095 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 5096 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 5097 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 5098 if (ej->function == e->function) {
5099 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
5100 return j;
5101 }
5102 }
5103 return 0; /* silence gcc, even though control never reaches here */
5104}
5105
5106/* find an entry with matching function, matching index (if needed), and that
5107 * should be read next (if it's stateful) */
5108static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
5109 u32 function, u32 index)
5110{
5111 if (e->function != function)
5112 return 0;
5113 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
5114 return 0;
5115 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 5116 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 5117 return 0;
5118 return 1;
5119}
5120
d8017474
AG		 5121struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
5122 u32 function, u32 index)
8776e519
HB		 5123{
5124 int i;
d8017474 5125 struct kvm_cpuid_entry2 *best = NULL;
8776e519 5126
ad312c7c 5127 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 5128 struct kvm_cpuid_entry2 *e;
5129
ad312c7c 5130 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 5131 if (is_matching_cpuid_entry(e, function, index)) {
5132 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
5133 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 5134 best = e;
5135 break;
5136 }
8776e519 5137 }
d8017474
AG		 5138 return best;
5139}
0e851880 5140EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry);
d8017474 5141
82725b20
DE		 5142int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
5143{
5144 struct kvm_cpuid_entry2 *best;
5145
f7a71197
AK		 5146 best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0);
5147 if (!best || best->eax < 0x80000008)
5148 goto not_found;
82725b20
DE		 5149 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
5150 if (best)
5151 return best->eax & 0xff;
f7a71197 5152not_found:
82725b20
DE		 5153 return 36;
5154}
5155
bd22f5cf
AP		 5156/*
5157 * If no match is found, check whether we exceed the vCPU's limit
5158 * and return the content of the highest valid _standard_ leaf instead.
5159 * This is to satisfy the CPUID specification.
5160 */
5161static struct kvm_cpuid_entry2* check_cpuid_limit(struct kvm_vcpu *vcpu,
5162 u32 function, u32 index)
5163{
5164 struct kvm_cpuid_entry2 *maxlevel;
5165
5166 maxlevel = kvm_find_cpuid_entry(vcpu, function & 0x80000000, 0);
5167 if (!maxlevel || maxlevel->eax >= function)
5168 return NULL;
5169 if (function & 0x80000000) {
5170 maxlevel = kvm_find_cpuid_entry(vcpu, 0, 0);
5171 if (!maxlevel)
5172 return NULL;
5173 }
5174 return kvm_find_cpuid_entry(vcpu, maxlevel->eax, index);
5175}
5176
d8017474
AG		 5177void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
5178{
5179 u32 function, index;
5180 struct kvm_cpuid_entry2 *best;
5181
5182 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
5183 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5184 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
5185 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
5186 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
5187 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
5188 best = kvm_find_cpuid_entry(vcpu, function, index);
bd22f5cf
AP		 5189
5190 if (!best)
5191 best = check_cpuid_limit(vcpu, function, index);
5192
8776e519 5193 if (best) {
5fdbf976
MT		 5194 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
5195 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
5196 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
5197 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 5198 }
8776e519 5199 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 5200 trace_kvm_cpuid(function,
5201 kvm_register_read(vcpu, VCPU_REGS_RAX),
5202 kvm_register_read(vcpu, VCPU_REGS_RBX),
5203 kvm_register_read(vcpu, VCPU_REGS_RCX),
5204 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 5205}
5206EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 5207
b6c7a5dc
HB		 5208/*
5209 * Check if userspace requested an interrupt window, and that the
5210 * interrupt window is open.
5211 *
5212 * No need to exit to userspace if we already have an interrupt queued.
5213 */
851ba692 5214static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5215{
8061823a 5216 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5217 vcpu->run->request_interrupt_window &&
5df56646 5218 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5219}
5220
851ba692 5221static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5222{
851ba692
AK		 5223 struct kvm_run *kvm_run = vcpu->run;
5224
91586a3b 5225 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5226 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5227 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5228 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5229 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5230 else
b6c7a5dc 5231 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5232 kvm_arch_interrupt_allowed(vcpu) &&
5233 !kvm_cpu_has_interrupt(vcpu) &&
5234 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5235}
5236
b93463aa
AK		 5237static void vapic_enter(struct kvm_vcpu *vcpu)
5238{
5239 struct kvm_lapic *apic = vcpu->arch.apic;
5240 struct page *page;
5241
5242 if (!apic || !apic->vapic_addr)
5243 return;
5244
5245 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 5246
5247 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 5248}
5249
5250static void vapic_exit(struct kvm_vcpu *vcpu)
5251{
5252 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 5253 int idx;
b93463aa
AK		 5254
5255 if (!apic || !apic->vapic_addr)
5256 return;
5257
f656ce01 5258 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 5259 kvm_release_page_dirty(apic->vapic_page);
5260 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 5261 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 5262}
5263
95ba8273
GN		 5264static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5265{
5266 int max_irr, tpr;
5267
5268 if (!kvm_x86_ops->update_cr8_intercept)
5269 return;
5270
88c808fd
AK		 5271 if (!vcpu->arch.apic)
5272 return;
5273
8db3baa2
GN		 5274 if (!vcpu->arch.apic->vapic_addr)
5275 max_irr = kvm_lapic_find_highest_irr(vcpu);
5276 else
5277 max_irr = -1;
95ba8273
GN		 5278
5279 if (max_irr != -1)
5280 max_irr >>= 4;
5281
5282 tpr = kvm_lapic_get_cr8(vcpu);
5283
5284 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5285}
5286
851ba692 5287static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 5288{
5289 /* try to reinject previous events if any */
b59bb7bd 5290 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5291 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5292 vcpu->arch.exception.has_error_code,
5293 vcpu->arch.exception.error_code);
b59bb7bd
GN		 5294 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5295 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5296 vcpu->arch.exception.error_code,
5297 vcpu->arch.exception.reinject);
b59bb7bd
GN		 5298 return;
5299 }
5300
95ba8273
GN		 5301 if (vcpu->arch.nmi_injected) {
5302 kvm_x86_ops->set_nmi(vcpu);
5303 return;
5304 }
5305
5306 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5307 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5308 return;
5309 }
5310
5311 /* try to inject new event if pending */
5312 if (vcpu->arch.nmi_pending) {
5313 if (kvm_x86_ops->nmi_allowed(vcpu)) {
5314 vcpu->arch.nmi_pending = false;
5315 vcpu->arch.nmi_injected = true;
5316 kvm_x86_ops->set_nmi(vcpu);
5317 }
5318 } else if (kvm_cpu_has_interrupt(vcpu)) {
5319 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5320 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5321 false);
5322 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5323 }
5324 }
5325}
5326
2acf923e
DC		 5327static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
5328{
5329 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
5330 !vcpu->guest_xcr0_loaded) {
5331 /* kvm_set_xcr() also depends on this */
5332 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
5333 vcpu->guest_xcr0_loaded = 1;
5334 }
5335}
5336
5337static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
5338{
5339 if (vcpu->guest_xcr0_loaded) {
5340 if (vcpu->arch.xcr0 != host_xcr0)
5341 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
5342 vcpu->guest_xcr0_loaded = 0;
5343 }
5344}
5345
851ba692 5346static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5347{
5348 int r;
1499e54a 5349 bool nmi_pending;
6a8b1d13 5350 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5351 vcpu->run->request_interrupt_window;
b6c7a5dc 5352
3e007509 5353 if (vcpu->requests) {
a8eeb04a 5354 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5355 kvm_mmu_unload(vcpu);
a8eeb04a 5356 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5357 __kvm_migrate_timers(vcpu);
34c238a1
ZA		 5358 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5359 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 5360 if (unlikely(r))
5361 goto out;
5362 }
a8eeb04a 5363 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5364 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5365 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5366 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5367 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5368 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5369 r = 0;
5370 goto out;
5371 }
a8eeb04a 5372 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5373 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5374 r = 0;
5375 goto out;
5376 }
a8eeb04a 5377 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5378 vcpu->fpu_active = 0;
5379 kvm_x86_ops->fpu_deactivate(vcpu);
5380 }
af585b92
GN		 5381 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5382 /* Page is swapped out. Do synthetic halt */
5383 vcpu->arch.apf.halted = true;
5384 r = 1;
5385 goto out;
5386 }
2f52d58c 5387 }
b93463aa 5388
3e007509
AK		 5389 r = kvm_mmu_reload(vcpu);
5390 if (unlikely(r))
5391 goto out;
5392
1499e54a
GN		 5393 /*
5394 * An NMI can be injected between local nmi_pending read and
5395 * vcpu->arch.nmi_pending read inside inject_pending_event().
5396 * But in that case, KVM_REQ_EVENT will be set, which makes
5397 * the race described above benign.
5398 */
5399 nmi_pending = ACCESS_ONCE(vcpu->arch.nmi_pending);
5400
b463a6f7
AK		 5401 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5402 inject_pending_event(vcpu);
5403
5404 /* enable NMI/IRQ window open exits if needed */
1499e54a 5405 if (nmi_pending)
b463a6f7
AK		 5406 kvm_x86_ops->enable_nmi_window(vcpu);
5407 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
5408 kvm_x86_ops->enable_irq_window(vcpu);
5409
5410 if (kvm_lapic_enabled(vcpu)) {
5411 update_cr8_intercept(vcpu);
5412 kvm_lapic_sync_to_vapic(vcpu);
5413 }
5414 }
5415
b6c7a5dc
HB		 5416 preempt_disable();
5417
5418 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 5419 if (vcpu->fpu_active)
5420 kvm_load_guest_fpu(vcpu);
2acf923e 5421 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 5422
6b7e2d09
XG		 5423 vcpu->mode = IN_GUEST_MODE;
5424
5425 /* We should set ->mode before check ->requests,
5426 * see the comment in make_all_cpus_request.
5427 */
5428 smp_mb();
b6c7a5dc 5429
d94e1dc9 5430 local_irq_disable();
32f88400 5431
6b7e2d09 5432 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 5433 || need_resched() || signal_pending(current)) {
6b7e2d09 5434 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5435 smp_wmb();
6c142801
AK		 5436 local_irq_enable();
5437 preempt_enable();
b463a6f7 5438 kvm_x86_ops->cancel_injection(vcpu);
6c142801
AK		 5439 r = 1;
5440 goto out;
5441 }
5442
f656ce01 5443 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 5444
b6c7a5dc
HB		 5445 kvm_guest_enter();
5446
42dbaa5a 5447 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 5448 set_debugreg(0, 7);
5449 set_debugreg(vcpu->arch.eff_db[0], 0);
5450 set_debugreg(vcpu->arch.eff_db[1], 1);
5451 set_debugreg(vcpu->arch.eff_db[2], 2);
5452 set_debugreg(vcpu->arch.eff_db[3], 3);
5453 }
b6c7a5dc 5454
229456fc 5455 trace_kvm_entry(vcpu->vcpu_id);
851ba692 5456 kvm_x86_ops->run(vcpu);
b6c7a5dc 5457
24f1e32c
FW		 5458 /*
5459 * If the guest has used debug registers, at least dr7
5460 * will be disabled while returning to the host.
5461 * If we don't have active breakpoints in the host, we don't
5462 * care about the messed up debug address registers. But if
5463 * we have some of them active, restore the old state.
5464 */
59d8eb53 5465 if (hw_breakpoint_active())
24f1e32c 5466 hw_breakpoint_restore();
42dbaa5a 5467
1d5f066e
ZA		 5468 kvm_get_msr(vcpu, MSR_IA32_TSC, &vcpu->arch.last_guest_tsc);
5469
6b7e2d09 5470 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5471 smp_wmb();
b6c7a5dc
HB		 5472 local_irq_enable();
5473
5474 ++vcpu->stat.exits;
5475
5476 /*
5477 * We must have an instruction between local_irq_enable() and
5478 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5479 * the interrupt shadow. The stat.exits increment will do nicely.
5480 * But we need to prevent reordering, hence this barrier():
5481 */
5482 barrier();
5483
5484 kvm_guest_exit();
5485
5486 preempt_enable();
5487
f656ce01 5488 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 5489
b6c7a5dc
HB		 5490 /*
5491 * Profile KVM exit RIPs:
5492 */
5493 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 5494 unsigned long rip = kvm_rip_read(vcpu);
5495 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 5496 }
5497
298101da 5498
b93463aa
AK		 5499 kvm_lapic_sync_from_vapic(vcpu);
5500
851ba692 5501 r = kvm_x86_ops->handle_exit(vcpu);
d7690175
MT		 5502out:
5503 return r;
5504}
b6c7a5dc 5505
09cec754 5506
851ba692 5507static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 5508{
5509 int r;
f656ce01 5510 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 5511
5512 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 5513 pr_debug("vcpu %d received sipi with vector # %x\n",
5514 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 5515 kvm_lapic_reset(vcpu);
5f179287 5516 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 5517 if (r)
5518 return r;
5519 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 5520 }
5521
f656ce01 5522 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 5523 vapic_enter(vcpu);
5524
5525 r = 1;
5526 while (r > 0) {
af585b92
GN		 5527 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
5528 !vcpu->arch.apf.halted)
851ba692 5529 r = vcpu_enter_guest(vcpu);
d7690175 5530 else {
f656ce01 5531 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 5532 kvm_vcpu_block(vcpu);
f656ce01 5533 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
a8eeb04a 5534 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
09cec754
GN		 5535 {
5536 switch(vcpu->arch.mp_state) {
5537 case KVM_MP_STATE_HALTED:
d7690175 5538 vcpu->arch.mp_state =
09cec754
GN		 5539 KVM_MP_STATE_RUNNABLE;
5540 case KVM_MP_STATE_RUNNABLE:
af585b92 5541 vcpu->arch.apf.halted = false;
09cec754
GN		 5542 break;
5543 case KVM_MP_STATE_SIPI_RECEIVED:
5544 default:
5545 r = -EINTR;
5546 break;
5547 }
5548 }
d7690175
MT		 5549 }
5550
09cec754
GN		 5551 if (r <= 0)
5552 break;
5553
5554 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5555 if (kvm_cpu_has_pending_timer(vcpu))
5556 kvm_inject_pending_timer_irqs(vcpu);
5557
851ba692 5558 if (dm_request_for_irq_injection(vcpu)) {
09cec754 5559 r = -EINTR;
851ba692 5560 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5561 ++vcpu->stat.request_irq_exits;
5562 }
af585b92
GN		 5563
5564 kvm_check_async_pf_completion(vcpu);
5565
09cec754
GN		 5566 if (signal_pending(current)) {
5567 r = -EINTR;
851ba692 5568 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5569 ++vcpu->stat.signal_exits;
5570 }
5571 if (need_resched()) {
f656ce01 5572 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 5573 kvm_resched(vcpu);
f656ce01 5574 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 5575 }
b6c7a5dc
HB		 5576 }
5577
f656ce01 5578 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 5579
b93463aa
AK		 5580 vapic_exit(vcpu);
5581
b6c7a5dc
HB		 5582 return r;
5583}
5584
5287f194
AK		 5585static int complete_mmio(struct kvm_vcpu *vcpu)
5586{
5587 struct kvm_run *run = vcpu->run;
5588 int r;
5589
5590 if (!(vcpu->arch.pio.count || vcpu->mmio_needed))
5591 return 1;
5592
5593 if (vcpu->mmio_needed) {
5287f194 5594 vcpu->mmio_needed = 0;
cef4dea0 5595 if (!vcpu->mmio_is_write)
0004c7c2
GN		 5596 memcpy(vcpu->mmio_data + vcpu->mmio_index,
5597 run->mmio.data, 8);
cef4dea0
AK		 5598 vcpu->mmio_index += 8;
5599 if (vcpu->mmio_index < vcpu->mmio_size) {
5600 run->exit_reason = KVM_EXIT_MMIO;
5601 run->mmio.phys_addr = vcpu->mmio_phys_addr + vcpu->mmio_index;
5602 memcpy(run->mmio.data, vcpu->mmio_data + vcpu->mmio_index, 8);
5603 run->mmio.len = min(vcpu->mmio_size - vcpu->mmio_index, 8);
5604 run->mmio.is_write = vcpu->mmio_is_write;
5605 vcpu->mmio_needed = 1;
5606 return 0;
5607 }
5608 if (vcpu->mmio_is_write)
5609 return 1;
5610 vcpu->mmio_read_completed = 1;
5287f194
AK		 5611 }
5612 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5613 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
5614 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5615 if (r != EMULATE_DONE)
5616 return 0;
5617 return 1;
5618}
5619
b6c7a5dc
HB		 5620int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
5621{
5622 int r;
5623 sigset_t sigsaved;
5624
e5c30142
AK		 5625 if (!tsk_used_math(current) && init_fpu(current))
5626 return -ENOMEM;
5627
ac9f6dc0
AK		 5628 if (vcpu->sigset_active)
5629 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
5630
a4535290 5631 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 5632 kvm_vcpu_block(vcpu);
d7690175 5633 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 5634 r = -EAGAIN;
5635 goto out;
b6c7a5dc
HB		 5636 }
5637
b6c7a5dc 5638 /* re-sync apic's tpr */
eea1cff9
AP		 5639 if (!irqchip_in_kernel(vcpu->kvm)) {
5640 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
5641 r = -EINVAL;
5642 goto out;
5643 }
5644 }
b6c7a5dc 5645
5287f194
AK		 5646 r = complete_mmio(vcpu);
5647 if (r <= 0)
5648 goto out;
5649
5fdbf976
MT		 5650 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
5651 kvm_register_write(vcpu, VCPU_REGS_RAX,
5652 kvm_run->hypercall.ret);
b6c7a5dc 5653
851ba692 5654 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 5655
5656out:
f1d86e46 5657 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 5658 if (vcpu->sigset_active)
5659 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
5660
b6c7a5dc
HB		 5661 return r;
5662}
5663
5664int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5665{
7ae441ea
GN		 5666 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
5667 /*
5668 * We are here if userspace calls get_regs() in the middle of
5669 * instruction emulation. Registers state needs to be copied
5670 * back from emulation context to vcpu. Usrapace shouldn't do
5671 * that usually, but some bad designed PV devices (vmware
5672 * backdoor interface) need this to work
5673 */
5674 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
5675 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
5676 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5677 }
5fdbf976
MT		 5678 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
5679 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
5680 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
5681 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
5682 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
5683 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
5684 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
5685 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 5686#ifdef CONFIG_X86_64
5fdbf976
MT		 5687 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
5688 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
5689 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
5690 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
5691 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
5692 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
5693 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
5694 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 5695#endif
5696
5fdbf976 5697 regs->rip = kvm_rip_read(vcpu);
91586a3b 5698 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 5699
b6c7a5dc
HB		 5700 return 0;
5701}
5702
5703int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
5704{
7ae441ea
GN		 5705 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
5706 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5707
5fdbf976
MT		 5708 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
5709 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
5710 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
5711 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
5712 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
5713 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
5714 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
5715 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 5716#ifdef CONFIG_X86_64
5fdbf976
MT		 5717 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
5718 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
5719 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
5720 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
5721 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
5722 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
5723 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
5724 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 5725#endif
5726
5fdbf976 5727 kvm_rip_write(vcpu, regs->rip);
91586a3b 5728 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 5729
b4f14abd
JK		 5730 vcpu->arch.exception.pending = false;
5731
3842d135
AK		 5732 kvm_make_request(KVM_REQ_EVENT, vcpu);
5733
b6c7a5dc
HB		 5734 return 0;
5735}
5736
b6c7a5dc
HB		 5737void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
5738{
5739 struct kvm_segment cs;
5740
3e6e0aab 5741 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 5742 *db = cs.db;
5743 *l = cs.l;
5744}
5745EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
5746
5747int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
5748 struct kvm_sregs *sregs)
5749{
89a27f4d 5750 struct desc_ptr dt;
b6c7a5dc 5751
3e6e0aab
GT		 5752 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5753 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5754 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5755 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5756 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5757 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5758
3e6e0aab
GT		 5759 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5760 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 5761
5762 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 5763 sregs->idt.limit = dt.size;
5764 sregs->idt.base = dt.address;
b6c7a5dc 5765 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 5766 sregs->gdt.limit = dt.size;
5767 sregs->gdt.base = dt.address;
b6c7a5dc 5768
4d4ec087 5769 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 5770 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 5771 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 5772 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 5773 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 5774 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 5775 sregs->apic_base = kvm_get_apic_base(vcpu);
5776
923c61bb 5777 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 5778
36752c9b 5779 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 5780 set_bit(vcpu->arch.interrupt.nr,
5781 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 5782
b6c7a5dc
HB		 5783 return 0;
5784}
5785
62d9f0db
MT		 5786int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
5787 struct kvm_mp_state *mp_state)
5788{
62d9f0db 5789 mp_state->mp_state = vcpu->arch.mp_state;
62d9f0db
MT		 5790 return 0;
5791}
5792
5793int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
5794 struct kvm_mp_state *mp_state)
5795{
62d9f0db 5796 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 5797 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 5798 return 0;
5799}
5800
e269fb21
JK		 5801int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason,
5802 bool has_error_code, u32 error_code)
b6c7a5dc 5803{
4d2179e1 5804 struct decode_cache *c = &vcpu->arch.emulate_ctxt.decode;
8ec4722d 5805 int ret;
e01c2426 5806
8ec4722d 5807 init_emulate_ctxt(vcpu);
c697518a 5808
9aabc88f 5809 ret = emulator_task_switch(&vcpu->arch.emulate_ctxt,
e269fb21
JK		 5810 tss_selector, reason, has_error_code,
5811 error_code);
c697518a 5812
c697518a 5813 if (ret)
19d04437 5814 return EMULATE_FAIL;
37817f29 5815
4d2179e1 5816 memcpy(vcpu->arch.regs, c->regs, sizeof c->regs);
95c55886 5817 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.eip);
f6e78475 5818 kvm_set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
3842d135 5819 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 5820 return EMULATE_DONE;
37817f29
IE		 5821}
5822EXPORT_SYMBOL_GPL(kvm_task_switch);
5823
b6c7a5dc
HB		 5824int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
5825 struct kvm_sregs *sregs)
5826{
5827 int mmu_reset_needed = 0;
63f42e02 5828 int pending_vec, max_bits, idx;
89a27f4d 5829 struct desc_ptr dt;
b6c7a5dc 5830
89a27f4d
GN		 5831 dt.size = sregs->idt.limit;
5832 dt.address = sregs->idt.base;
b6c7a5dc 5833 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 5834 dt.size = sregs->gdt.limit;
5835 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 5836 kvm_x86_ops->set_gdt(vcpu, &dt);
5837
ad312c7c 5838 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 5839 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 5840 vcpu->arch.cr3 = sregs->cr3;
aff48baa 5841 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 5842
2d3ad1f4 5843 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 5844
f6801dff 5845 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 5846 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 5847 kvm_set_apic_base(vcpu, sregs->apic_base);
5848
4d4ec087 5849 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 5850 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 5851 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 5852
fc78f519 5853 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 5854 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c
SY		 5855 if (sregs->cr4 & X86_CR4_OSXSAVE)
5856 update_cpuid(vcpu);
63f42e02
XG		 5857
5858 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 5859 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 5860 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 5861 mmu_reset_needed = 1;
5862 }
63f42e02 5863 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 5864
5865 if (mmu_reset_needed)
5866 kvm_mmu_reset_context(vcpu);
5867
923c61bb
GN		 5868 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
5869 pending_vec = find_first_bit(
5870 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
5871 if (pending_vec < max_bits) {
66fd3f7f 5872 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 5873 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 5874 }
5875
3e6e0aab
GT		 5876 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
5877 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
5878 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
5879 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
5880 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
5881 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 5882
3e6e0aab
GT		 5883 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
5884 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 5885
5f0269f5
ME		 5886 update_cr8_intercept(vcpu);
5887
9c3e4aab 5888 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 5889 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 5890 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 5891 !is_protmode(vcpu))
9c3e4aab
MT		 5892 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
5893
3842d135
AK		 5894 kvm_make_request(KVM_REQ_EVENT, vcpu);
5895
b6c7a5dc
HB		 5896 return 0;
5897}
5898
d0bfb940
JK		 5899int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
5900 struct kvm_guest_debug *dbg)
b6c7a5dc 5901{
355be0b9 5902 unsigned long rflags;
ae675ef0 5903 int i, r;
b6c7a5dc 5904
4f926bf2
JK		 5905 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
5906 r = -EBUSY;
5907 if (vcpu->arch.exception.pending)
2122ff5e 5908 goto out;
4f926bf2
JK		 5909 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
5910 kvm_queue_exception(vcpu, DB_VECTOR);
5911 else
5912 kvm_queue_exception(vcpu, BP_VECTOR);
5913 }
5914
91586a3b
JK		 5915 /*
5916 * Read rflags as long as potentially injected trace flags are still
5917 * filtered out.
5918 */
5919 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 5920
5921 vcpu->guest_debug = dbg->control;
5922 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
5923 vcpu->guest_debug = 0;
5924
5925 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 5926 for (i = 0; i < KVM_NR_DB_REGS; ++i)
5927 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
5928 vcpu->arch.switch_db_regs =
5929 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
5930 } else {
5931 for (i = 0; i < KVM_NR_DB_REGS; i++)
5932 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
5933 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
5934 }
5935
f92653ee
JK		 5936 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5937 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
5938 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 5939
91586a3b
JK		 5940 /*
5941 * Trigger an rflags update that will inject or remove the trace
5942 * flags.
5943 */
5944 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 5945
355be0b9 5946 kvm_x86_ops->set_guest_debug(vcpu, dbg);
b6c7a5dc 5947
4f926bf2 5948 r = 0;
d0bfb940 5949
2122ff5e 5950out:
b6c7a5dc
HB		 5951
5952 return r;
5953}
5954
8b006791
ZX		 5955/*
5956 * Translate a guest virtual address to a guest physical address.
5957 */
5958int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
5959 struct kvm_translation *tr)
5960{
5961 unsigned long vaddr = tr->linear_address;
5962 gpa_t gpa;
f656ce01 5963 int idx;
8b006791 5964
f656ce01 5965 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 5966 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 5967 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 5968 tr->physical_address = gpa;
5969 tr->valid = gpa != UNMAPPED_GVA;
5970 tr->writeable = 1;
5971 tr->usermode = 0;
8b006791
ZX		 5972
5973 return 0;
5974}
5975
d0752060
HB		 5976int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5977{
98918833
SY		 5978 struct i387_fxsave_struct *fxsave =
5979 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5980
d0752060
HB		 5981 memcpy(fpu->fpr, fxsave->st_space, 128);
5982 fpu->fcw = fxsave->cwd;
5983 fpu->fsw = fxsave->swd;
5984 fpu->ftwx = fxsave->twd;
5985 fpu->last_opcode = fxsave->fop;
5986 fpu->last_ip = fxsave->rip;
5987 fpu->last_dp = fxsave->rdp;
5988 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
5989
d0752060
HB		 5990 return 0;
5991}
5992
5993int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
5994{
98918833
SY		 5995 struct i387_fxsave_struct *fxsave =
5996 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 5997
d0752060
HB		 5998 memcpy(fxsave->st_space, fpu->fpr, 128);
5999 fxsave->cwd = fpu->fcw;
6000 fxsave->swd = fpu->fsw;
6001 fxsave->twd = fpu->ftwx;
6002 fxsave->fop = fpu->last_opcode;
6003 fxsave->rip = fpu->last_ip;
6004 fxsave->rdp = fpu->last_dp;
6005 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6006
d0752060
HB		 6007 return 0;
6008}
6009
10ab25cd 6010int fx_init(struct kvm_vcpu *vcpu)
d0752060 6011{
10ab25cd
JK		 6012 int err;
6013
6014 err = fpu_alloc(&vcpu->arch.guest_fpu);
6015 if (err)
6016 return err;
6017
98918833 6018 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 6019
2acf923e
DC		 6020 /*
6021 * Ensure guest xcr0 is valid for loading
6022 */
6023 vcpu->arch.xcr0 = XSTATE_FP;
6024
ad312c7c 6025 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 6026
6027 return 0;
d0752060
HB		 6028}
6029EXPORT_SYMBOL_GPL(fx_init);
6030
98918833
SY		 6031static void fx_free(struct kvm_vcpu *vcpu)
6032{
6033 fpu_free(&vcpu->arch.guest_fpu);
6034}
6035
d0752060
HB		 6036void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6037{
2608d7a1 6038 if (vcpu->guest_fpu_loaded)
d0752060
HB		 6039 return;
6040
2acf923e
DC		 6041 /*
6042 * Restore all possible states in the guest,
6043 * and assume host would use all available bits.
6044 * Guest xcr0 would be loaded later.
6045 */
6046 kvm_put_guest_xcr0(vcpu);
d0752060 6047 vcpu->guest_fpu_loaded = 1;
7cf30855 6048 unlazy_fpu(current);
98918833 6049 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 6050 trace_kvm_fpu(1);
d0752060 6051}
d0752060
HB		 6052
6053void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6054{
2acf923e
DC		 6055 kvm_put_guest_xcr0(vcpu);
6056
d0752060
HB		 6057 if (!vcpu->guest_fpu_loaded)
6058 return;
6059
6060 vcpu->guest_fpu_loaded = 0;
98918833 6061 fpu_save_init(&vcpu->arch.guest_fpu);
f096ed85 6062 ++vcpu->stat.fpu_reload;
a8eeb04a 6063 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 6064 trace_kvm_fpu(0);
d0752060 6065}
e9b11c17
ZX		 6066
6067void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6068{
12f9a48f 6069 kvmclock_reset(vcpu);
7f1ea208 6070
f5f48ee1 6071 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 6072 fx_free(vcpu);
e9b11c17
ZX		 6073 kvm_x86_ops->vcpu_free(vcpu);
6074}
6075
6076struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6077 unsigned int id)
6078{
6755bae8
ZA		 6079 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6080 printk_once(KERN_WARNING
6081 "kvm: SMP vm created on host with unstable TSC; "
6082 "guest TSC will not be reliable\n");
26e5215f
AK		 6083 return kvm_x86_ops->vcpu_create(kvm, id);
6084}
e9b11c17 6085
26e5215f
AK		 6086int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6087{
6088 int r;
e9b11c17 6089
0bed3b56 6090 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 6091 vcpu_load(vcpu);
6092 r = kvm_arch_vcpu_reset(vcpu);
6093 if (r == 0)
6094 r = kvm_mmu_setup(vcpu);
6095 vcpu_put(vcpu);
6096 if (r < 0)
6097 goto free_vcpu;
6098
26e5215f 6099 return 0;
e9b11c17
ZX		 6100free_vcpu:
6101 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 6102 return r;
e9b11c17
ZX		 6103}
6104
d40ccc62 6105void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 6106{
344d9588
GN		 6107 vcpu->arch.apf.msr_val = 0;
6108
e9b11c17
ZX		 6109 vcpu_load(vcpu);
6110 kvm_mmu_unload(vcpu);
6111 vcpu_put(vcpu);
6112
98918833 6113 fx_free(vcpu);
e9b11c17
ZX		 6114 kvm_x86_ops->vcpu_free(vcpu);
6115}
6116
6117int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
6118{
448fa4a9
JK		 6119 vcpu->arch.nmi_pending = false;
6120 vcpu->arch.nmi_injected = false;
6121
42dbaa5a
JK		 6122 vcpu->arch.switch_db_regs = 0;
6123 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6124 vcpu->arch.dr6 = DR6_FIXED_1;
6125 vcpu->arch.dr7 = DR7_FIXED_1;
6126
3842d135 6127 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 6128 vcpu->arch.apf.msr_val = 0;
3842d135 6129
12f9a48f
GC		 6130 kvmclock_reset(vcpu);
6131
af585b92
GN		 6132 kvm_clear_async_pf_completion_queue(vcpu);
6133 kvm_async_pf_hash_reset(vcpu);
6134 vcpu->arch.apf.halted = false;
3842d135 6135
e9b11c17
ZX		 6136 return kvm_x86_ops->vcpu_reset(vcpu);
6137}
6138
10474ae8 6139int kvm_arch_hardware_enable(void *garbage)
e9b11c17 6140{
ca84d1a2
ZA		 6141 struct kvm *kvm;
6142 struct kvm_vcpu *vcpu;
6143 int i;
18863bdd
AK		 6144
6145 kvm_shared_msr_cpu_online();
ca84d1a2
ZA		 6146 list_for_each_entry(kvm, &vm_list, vm_list)
6147 kvm_for_each_vcpu(i, vcpu, kvm)
6148 if (vcpu->cpu == smp_processor_id())
c285545f 6149 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
10474ae8 6150 return kvm_x86_ops->hardware_enable(garbage);
e9b11c17
ZX		 6151}
6152
6153void kvm_arch_hardware_disable(void *garbage)
6154{
6155 kvm_x86_ops->hardware_disable(garbage);
3548bab5 6156 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 6157}
6158
6159int kvm_arch_hardware_setup(void)
6160{
6161 return kvm_x86_ops->hardware_setup();
6162}
6163
6164void kvm_arch_hardware_unsetup(void)
6165{
6166 kvm_x86_ops->hardware_unsetup();
6167}
6168
6169void kvm_arch_check_processor_compat(void *rtn)
6170{
6171 kvm_x86_ops->check_processor_compatibility(rtn);
6172}
6173
6174int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6175{
6176 struct page *page;
6177 struct kvm *kvm;
6178 int r;
6179
6180 BUG_ON(vcpu->kvm == NULL);
6181 kvm = vcpu->kvm;
6182
9aabc88f 6183 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
14dfe855 6184 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
ad312c7c 6185 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c30a358d 6186 vcpu->arch.mmu.translate_gpa = translate_gpa;
02f59dc9 6187 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
c5af89b6 6188 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 6189 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 6190 else
a4535290 6191 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 6192
6193 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6194 if (!page) {
6195 r = -ENOMEM;
6196 goto fail;
6197 }
ad312c7c 6198 vcpu->arch.pio_data = page_address(page);
e9b11c17 6199
1e993611 6200 kvm_init_tsc_catchup(vcpu, max_tsc_khz);
c285545f 6201
e9b11c17
ZX		 6202 r = kvm_mmu_create(vcpu);
6203 if (r < 0)
6204 goto fail_free_pio_data;
6205
6206 if (irqchip_in_kernel(kvm)) {
6207 r = kvm_create_lapic(vcpu);
6208 if (r < 0)
6209 goto fail_mmu_destroy;
6210 }
6211
890ca9ae
HY		 6212 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6213 GFP_KERNEL);
6214 if (!vcpu->arch.mce_banks) {
6215 r = -ENOMEM;
443c39bc 6216 goto fail_free_lapic;
890ca9ae
HY		 6217 }
6218 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6219
f5f48ee1
SY		 6220 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
6221 goto fail_free_mce_banks;
6222
af585b92
GN		 6223 kvm_async_pf_hash_reset(vcpu);
6224
e9b11c17 6225 return 0;
f5f48ee1
SY		 6226fail_free_mce_banks:
6227 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 6228fail_free_lapic:
6229 kvm_free_lapic(vcpu);
e9b11c17
ZX		 6230fail_mmu_destroy:
6231 kvm_mmu_destroy(vcpu);
6232fail_free_pio_data:
ad312c7c 6233 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 6234fail:
6235 return r;
6236}
6237
6238void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6239{
f656ce01
MT		 6240 int idx;
6241
36cb93fd 6242 kfree(vcpu->arch.mce_banks);
e9b11c17 6243 kvm_free_lapic(vcpu);
f656ce01 6244 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 6245 kvm_mmu_destroy(vcpu);
f656ce01 6246 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 6247 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 6248}
d19a9cd2 6249
d89f5eff 6250int kvm_arch_init_vm(struct kvm *kvm)
d19a9cd2 6251{
f05e70ac 6252 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 6253 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 6254
5550af4d
SY		 6255 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
6256 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
6257
038f8c11 6258 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
53f658b3 6259
d89f5eff 6260 return 0;
d19a9cd2
ZX		 6261}
6262
6263static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
6264{
6265 vcpu_load(vcpu);
6266 kvm_mmu_unload(vcpu);
6267 vcpu_put(vcpu);
6268}
6269
6270static void kvm_free_vcpus(struct kvm *kvm)
6271{
6272 unsigned int i;
988a2cae 6273 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 6274
6275 /*
6276 * Unpin any mmu pages first.
6277 */
af585b92
GN		 6278 kvm_for_each_vcpu(i, vcpu, kvm) {
6279 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 6280 kvm_unload_vcpu_mmu(vcpu);
af585b92 6281 }
988a2cae
GN		 6282 kvm_for_each_vcpu(i, vcpu, kvm)
6283 kvm_arch_vcpu_free(vcpu);
6284
6285 mutex_lock(&kvm->lock);
6286 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
6287 kvm->vcpus[i] = NULL;
d19a9cd2 6288
988a2cae
GN		 6289 atomic_set(&kvm->online_vcpus, 0);
6290 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 6291}
6292
ad8ba2cd
SY		 6293void kvm_arch_sync_events(struct kvm *kvm)
6294{
ba4cef31 6295 kvm_free_all_assigned_devices(kvm);
aea924f6 6296 kvm_free_pit(kvm);
ad8ba2cd
SY		 6297}
6298
d19a9cd2
ZX		 6299void kvm_arch_destroy_vm(struct kvm *kvm)
6300{
6eb55818 6301 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 6302 kfree(kvm->arch.vpic);
6303 kfree(kvm->arch.vioapic);
d19a9cd2 6304 kvm_free_vcpus(kvm);
3d45830c
AK		 6305 if (kvm->arch.apic_access_page)
6306 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 6307 if (kvm->arch.ept_identity_pagetable)
6308 put_page(kvm->arch.ept_identity_pagetable);
d19a9cd2 6309}
0de10343 6310
f7784b8e
MT		 6311int kvm_arch_prepare_memory_region(struct kvm *kvm,
6312 struct kvm_memory_slot *memslot,
0de10343 6313 struct kvm_memory_slot old,
f7784b8e 6314 struct kvm_userspace_memory_region *mem,
0de10343
ZX		 6315 int user_alloc)
6316{
f7784b8e 6317 int npages = memslot->npages;
7ac77099
AK		 6318 int map_flags = MAP_PRIVATE | MAP_ANONYMOUS;
6319
6320 /* Prevent internal slot pages from being moved by fork()/COW. */
6321 if (memslot->id >= KVM_MEMORY_SLOTS)
6322 map_flags = MAP_SHARED | MAP_ANONYMOUS;
0de10343
ZX		 6323
6324 /*To keep backward compatibility with older userspace,
6325 *x86 needs to hanlde !user_alloc case.
6326 */
6327 if (!user_alloc) {
6328 if (npages && !old.rmap) {
604b38ac
AA		 6329 unsigned long userspace_addr;
6330
72dc67a6 6331 down_write(&current->mm->mmap_sem);
604b38ac
AA		 6332 userspace_addr = do_mmap(NULL, 0,
6333 npages * PAGE_SIZE,
6334 PROT_READ | PROT_WRITE,
7ac77099 6335 map_flags,
604b38ac 6336 0);
72dc67a6 6337 up_write(&current->mm->mmap_sem);
0de10343 6338
604b38ac
AA		 6339 if (IS_ERR((void *)userspace_addr))
6340 return PTR_ERR((void *)userspace_addr);
6341
604b38ac 6342 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 6343 }
6344 }
6345
f7784b8e
MT		 6346
6347 return 0;
6348}
6349
6350void kvm_arch_commit_memory_region(struct kvm *kvm,
6351 struct kvm_userspace_memory_region *mem,
6352 struct kvm_memory_slot old,
6353 int user_alloc)
6354{
6355
48c0e4e9 6356 int nr_mmu_pages = 0, npages = mem->memory_size >> PAGE_SHIFT;
f7784b8e
MT		 6357
6358 if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
6359 int ret;
6360
6361 down_write(&current->mm->mmap_sem);
6362 ret = do_munmap(current->mm, old.userspace_addr,
6363 old.npages * PAGE_SIZE);
6364 up_write(&current->mm->mmap_sem);
6365 if (ret < 0)
6366 printk(KERN_WARNING
6367 "kvm_vm_ioctl_set_memory_region: "
6368 "failed to munmap memory\n");
6369 }
6370
48c0e4e9
XG		 6371 if (!kvm->arch.n_requested_mmu_pages)
6372 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
6373
7c8a83b7 6374 spin_lock(&kvm->mmu_lock);
48c0e4e9 6375 if (nr_mmu_pages)
0de10343 6376 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
0de10343 6377 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 6378 spin_unlock(&kvm->mmu_lock);
0de10343 6379}
1d737c8a 6380
34d4cb8f
MT		 6381void kvm_arch_flush_shadow(struct kvm *kvm)
6382{
6383 kvm_mmu_zap_all(kvm);
8986ecc0 6384 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 6385}
6386
1d737c8a
ZX		 6387int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
6388{
af585b92
GN		 6389 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6390 !vcpu->arch.apf.halted)
6391 || !list_empty_careful(&vcpu->async_pf.done)
a1b37100
GN		 6392 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
6393 || vcpu->arch.nmi_pending ||
6394 (kvm_arch_interrupt_allowed(vcpu) &&
6395 kvm_cpu_has_interrupt(vcpu));
1d737c8a 6396}
5736199a 6397
5736199a
ZX		 6398void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
6399{
32f88400
MT		 6400 int me;
6401 int cpu = vcpu->cpu;
5736199a
ZX		 6402
6403 if (waitqueue_active(&vcpu->wq)) {
6404 wake_up_interruptible(&vcpu->wq);
6405 ++vcpu->stat.halt_wakeup;
6406 }
32f88400
MT		 6407
6408 me = get_cpu();
6409 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
6b7e2d09 6410 if (kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE)
32f88400 6411 smp_send_reschedule(cpu);
e9571ed5 6412 put_cpu();
5736199a 6413}
78646121
GN		 6414
6415int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
6416{
6417 return kvm_x86_ops->interrupt_allowed(vcpu);
6418}
229456fc 6419
f92653ee
JK		 6420bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
6421{
6422 unsigned long current_rip = kvm_rip_read(vcpu) +
6423 get_segment_base(vcpu, VCPU_SREG_CS);
6424
6425 return current_rip == linear_rip;
6426}
6427EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
6428
94fe45da
JK		 6429unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
6430{
6431 unsigned long rflags;
6432
6433 rflags = kvm_x86_ops->get_rflags(vcpu);
6434 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 6435 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 6436 return rflags;
6437}
6438EXPORT_SYMBOL_GPL(kvm_get_rflags);
6439
6440void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
6441{
6442 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 6443 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 6444 rflags |= X86_EFLAGS_TF;
94fe45da 6445 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 6446 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 6447}
6448EXPORT_SYMBOL_GPL(kvm_set_rflags);
6449
56028d08
GN		 6450void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
6451{
6452 int r;
6453
fb67e14f 6454 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
c4806acd 6455 is_error_page(work->page))
56028d08
GN		 6456 return;
6457
6458 r = kvm_mmu_reload(vcpu);
6459 if (unlikely(r))
6460 return;
6461
fb67e14f
XG		 6462 if (!vcpu->arch.mmu.direct_map &&
6463 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
6464 return;
6465
56028d08
GN		 6466 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
6467}
6468
af585b92
GN		 6469static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
6470{
6471 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
6472}
6473
6474static inline u32 kvm_async_pf_next_probe(u32 key)
6475{
6476 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
6477}
6478
6479static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6480{
6481 u32 key = kvm_async_pf_hash_fn(gfn);
6482
6483 while (vcpu->arch.apf.gfns[key] != ~0)
6484 key = kvm_async_pf_next_probe(key);
6485
6486 vcpu->arch.apf.gfns[key] = gfn;
6487}
6488
6489static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
6490{
6491 int i;
6492 u32 key = kvm_async_pf_hash_fn(gfn);
6493
6494 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 6495 (vcpu->arch.apf.gfns[key] != gfn &&
6496 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 6497 key = kvm_async_pf_next_probe(key);
6498
6499 return key;
6500}
6501
6502bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6503{
6504 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
6505}
6506
6507static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
6508{
6509 u32 i, j, k;
6510
6511 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
6512 while (true) {
6513 vcpu->arch.apf.gfns[i] = ~0;
6514 do {
6515 j = kvm_async_pf_next_probe(j);
6516 if (vcpu->arch.apf.gfns[j] == ~0)
6517 return;
6518 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
6519 /*
6520 * k lies cyclically in ]i,j]
6521 * | i.k.j |
6522 * |....j i.k.| or |.k..j i...|
6523 */
6524 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
6525 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
6526 i = j;
6527 }
6528}
6529
7c90705b
GN		 6530static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
6531{
6532
6533 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
6534 sizeof(val));
6535}
6536
af585b92
GN		 6537void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
6538 struct kvm_async_pf *work)
6539{
6389ee94
AK		 6540 struct x86_exception fault;
6541
7c90705b 6542 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 6543 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 6544
6545 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 6546 (vcpu->arch.apf.send_user_only &&
6547 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 6548 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
6549 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 6550 fault.vector = PF_VECTOR;
6551 fault.error_code_valid = true;
6552 fault.error_code = 0;
6553 fault.nested_page_fault = false;
6554 fault.address = work->arch.token;
6555 kvm_inject_page_fault(vcpu, &fault);
7c90705b 6556 }
af585b92
GN		 6557}
6558
6559void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
6560 struct kvm_async_pf *work)
6561{
6389ee94
AK		 6562 struct x86_exception fault;
6563
7c90705b
GN		 6564 trace_kvm_async_pf_ready(work->arch.token, work->gva);
6565 if (is_error_page(work->page))
6566 work->arch.token = ~0; /* broadcast wakeup */
6567 else
6568 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
6569
6570 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
6571 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 6572 fault.vector = PF_VECTOR;
6573 fault.error_code_valid = true;
6574 fault.error_code = 0;
6575 fault.nested_page_fault = false;
6576 fault.address = work->arch.token;
6577 kvm_inject_page_fault(vcpu, &fault);
7c90705b 6578 }
e6d53e3b 6579 vcpu->arch.apf.halted = false;
7c90705b
GN		 6580}
6581
6582bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
6583{
6584 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
6585 return true;
6586 else
6587 return !kvm_event_needs_reinjection(vcpu) &&
6588 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 6589}
6590
229456fc
MT		 6591EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
6592EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
6593EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
6594EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
6595EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 6596EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 6597EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 6598EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 6599EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 6600EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 6601EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 6602EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
kernel source for telekom puls (alcatel/mediatek)