Commit | Line | Data |
---|---|---|
b6c02715 | 1 | /* |
bf3118c1 | 2 | * Copyright (C) 2007-2009 Advanced Micro Devices, Inc. |
b6c02715 JR |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/pci.h> | |
21 | #include <linux/gfp.h> | |
22 | #include <linux/bitops.h> | |
7f26508b | 23 | #include <linux/debugfs.h> |
b6c02715 | 24 | #include <linux/scatterlist.h> |
51491367 | 25 | #include <linux/dma-mapping.h> |
b6c02715 | 26 | #include <linux/iommu-helper.h> |
c156e347 | 27 | #include <linux/iommu.h> |
b6c02715 | 28 | #include <asm/proto.h> |
46a7fa27 | 29 | #include <asm/iommu.h> |
1d9b16d1 | 30 | #include <asm/gart.h> |
6a9401a7 | 31 | #include <asm/amd_iommu_proto.h> |
b6c02715 | 32 | #include <asm/amd_iommu_types.h> |
c6da992e | 33 | #include <asm/amd_iommu.h> |
b6c02715 JR |
34 | |
35 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
36 | ||
136f78a1 JR |
37 | #define EXIT_LOOP_COUNT 10000000 |
38 | ||
b6c02715 JR |
39 | static DEFINE_RWLOCK(amd_iommu_devtable_lock); |
40 | ||
bd60b735 JR |
41 | /* A list of preallocated protection domains */ |
42 | static LIST_HEAD(iommu_pd_list); | |
43 | static DEFINE_SPINLOCK(iommu_pd_list_lock); | |
44 | ||
0feae533 JR |
45 | /* |
46 | * Domain for untranslated devices - only allocated | |
47 | * if iommu=pt passed on kernel cmd line. | |
48 | */ | |
49 | static struct protection_domain *pt_domain; | |
50 | ||
26961efe | 51 | static struct iommu_ops amd_iommu_ops; |
26961efe | 52 | |
431b2a20 JR |
53 | /* |
54 | * general struct to manage commands send to an IOMMU | |
55 | */ | |
d6449536 | 56 | struct iommu_cmd { |
b6c02715 JR |
57 | u32 data[4]; |
58 | }; | |
59 | ||
bd0e5211 JR |
60 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
61 | struct unity_map_entry *e); | |
e275a2a0 | 62 | static struct dma_ops_domain *find_protection_domain(u16 devid); |
8bc3e127 | 63 | static u64 *alloc_pte(struct protection_domain *domain, |
abdc5eb3 JR |
64 | unsigned long address, int end_lvl, |
65 | u64 **pte_page, gfp_t gfp); | |
00cd122a JR |
66 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, |
67 | unsigned long start_page, | |
68 | unsigned int pages); | |
a345b23b | 69 | static void reset_iommu_command_buffer(struct amd_iommu *iommu); |
9355a081 | 70 | static u64 *fetch_pte(struct protection_domain *domain, |
a6b256b4 | 71 | unsigned long address, int map_size); |
04bfdd84 | 72 | static void update_domain(struct protection_domain *domain); |
c1eee67b | 73 | |
15898bbc JR |
74 | /**************************************************************************** |
75 | * | |
76 | * Helper functions | |
77 | * | |
78 | ****************************************************************************/ | |
79 | ||
80 | static inline u16 get_device_id(struct device *dev) | |
81 | { | |
82 | struct pci_dev *pdev = to_pci_dev(dev); | |
83 | ||
84 | return calc_devid(pdev->bus->number, pdev->devfn); | |
85 | } | |
86 | ||
7f26508b JR |
87 | #ifdef CONFIG_AMD_IOMMU_STATS |
88 | ||
89 | /* | |
90 | * Initialization code for statistics collection | |
91 | */ | |
92 | ||
da49f6df | 93 | DECLARE_STATS_COUNTER(compl_wait); |
0f2a86f2 | 94 | DECLARE_STATS_COUNTER(cnt_map_single); |
146a6917 | 95 | DECLARE_STATS_COUNTER(cnt_unmap_single); |
d03f067a | 96 | DECLARE_STATS_COUNTER(cnt_map_sg); |
55877a6b | 97 | DECLARE_STATS_COUNTER(cnt_unmap_sg); |
c8f0fb36 | 98 | DECLARE_STATS_COUNTER(cnt_alloc_coherent); |
5d31ee7e | 99 | DECLARE_STATS_COUNTER(cnt_free_coherent); |
c1858976 | 100 | DECLARE_STATS_COUNTER(cross_page); |
f57d98ae | 101 | DECLARE_STATS_COUNTER(domain_flush_single); |
18811f55 | 102 | DECLARE_STATS_COUNTER(domain_flush_all); |
5774f7c5 | 103 | DECLARE_STATS_COUNTER(alloced_io_mem); |
8ecaf8f1 | 104 | DECLARE_STATS_COUNTER(total_map_requests); |
da49f6df | 105 | |
7f26508b JR |
106 | static struct dentry *stats_dir; |
107 | static struct dentry *de_isolate; | |
108 | static struct dentry *de_fflush; | |
109 | ||
110 | static void amd_iommu_stats_add(struct __iommu_counter *cnt) | |
111 | { | |
112 | if (stats_dir == NULL) | |
113 | return; | |
114 | ||
115 | cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir, | |
116 | &cnt->value); | |
117 | } | |
118 | ||
119 | static void amd_iommu_stats_init(void) | |
120 | { | |
121 | stats_dir = debugfs_create_dir("amd-iommu", NULL); | |
122 | if (stats_dir == NULL) | |
123 | return; | |
124 | ||
125 | de_isolate = debugfs_create_bool("isolation", 0444, stats_dir, | |
126 | (u32 *)&amd_iommu_isolate); | |
127 | ||
128 | de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir, | |
129 | (u32 *)&amd_iommu_unmap_flush); | |
da49f6df JR |
130 | |
131 | amd_iommu_stats_add(&compl_wait); | |
0f2a86f2 | 132 | amd_iommu_stats_add(&cnt_map_single); |
146a6917 | 133 | amd_iommu_stats_add(&cnt_unmap_single); |
d03f067a | 134 | amd_iommu_stats_add(&cnt_map_sg); |
55877a6b | 135 | amd_iommu_stats_add(&cnt_unmap_sg); |
c8f0fb36 | 136 | amd_iommu_stats_add(&cnt_alloc_coherent); |
5d31ee7e | 137 | amd_iommu_stats_add(&cnt_free_coherent); |
c1858976 | 138 | amd_iommu_stats_add(&cross_page); |
f57d98ae | 139 | amd_iommu_stats_add(&domain_flush_single); |
18811f55 | 140 | amd_iommu_stats_add(&domain_flush_all); |
5774f7c5 | 141 | amd_iommu_stats_add(&alloced_io_mem); |
8ecaf8f1 | 142 | amd_iommu_stats_add(&total_map_requests); |
7f26508b JR |
143 | } |
144 | ||
145 | #endif | |
146 | ||
a80dc3e0 JR |
147 | /**************************************************************************** |
148 | * | |
149 | * Interrupt handling functions | |
150 | * | |
151 | ****************************************************************************/ | |
152 | ||
e3e59876 JR |
153 | static void dump_dte_entry(u16 devid) |
154 | { | |
155 | int i; | |
156 | ||
157 | for (i = 0; i < 8; ++i) | |
158 | pr_err("AMD-Vi: DTE[%d]: %08x\n", i, | |
159 | amd_iommu_dev_table[devid].data[i]); | |
160 | } | |
161 | ||
945b4ac4 JR |
162 | static void dump_command(unsigned long phys_addr) |
163 | { | |
164 | struct iommu_cmd *cmd = phys_to_virt(phys_addr); | |
165 | int i; | |
166 | ||
167 | for (i = 0; i < 4; ++i) | |
168 | pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]); | |
169 | } | |
170 | ||
a345b23b | 171 | static void iommu_print_event(struct amd_iommu *iommu, void *__evt) |
90008ee4 JR |
172 | { |
173 | u32 *event = __evt; | |
174 | int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
175 | int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
176 | int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK; | |
177 | int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; | |
178 | u64 address = (u64)(((u64)event[3]) << 32) | event[2]; | |
179 | ||
4c6f40d4 | 180 | printk(KERN_ERR "AMD-Vi: Event logged ["); |
90008ee4 JR |
181 | |
182 | switch (type) { | |
183 | case EVENT_TYPE_ILL_DEV: | |
184 | printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x " | |
185 | "address=0x%016llx flags=0x%04x]\n", | |
186 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
187 | address, flags); | |
e3e59876 | 188 | dump_dte_entry(devid); |
90008ee4 JR |
189 | break; |
190 | case EVENT_TYPE_IO_FAULT: | |
191 | printk("IO_PAGE_FAULT device=%02x:%02x.%x " | |
192 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
193 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
194 | domid, address, flags); | |
195 | break; | |
196 | case EVENT_TYPE_DEV_TAB_ERR: | |
197 | printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
198 | "address=0x%016llx flags=0x%04x]\n", | |
199 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
200 | address, flags); | |
201 | break; | |
202 | case EVENT_TYPE_PAGE_TAB_ERR: | |
203 | printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
204 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
205 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
206 | domid, address, flags); | |
207 | break; | |
208 | case EVENT_TYPE_ILL_CMD: | |
209 | printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address); | |
a345b23b | 210 | reset_iommu_command_buffer(iommu); |
945b4ac4 | 211 | dump_command(address); |
90008ee4 JR |
212 | break; |
213 | case EVENT_TYPE_CMD_HARD_ERR: | |
214 | printk("COMMAND_HARDWARE_ERROR address=0x%016llx " | |
215 | "flags=0x%04x]\n", address, flags); | |
216 | break; | |
217 | case EVENT_TYPE_IOTLB_INV_TO: | |
218 | printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x " | |
219 | "address=0x%016llx]\n", | |
220 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
221 | address); | |
222 | break; | |
223 | case EVENT_TYPE_INV_DEV_REQ: | |
224 | printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x " | |
225 | "address=0x%016llx flags=0x%04x]\n", | |
226 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
227 | address, flags); | |
228 | break; | |
229 | default: | |
230 | printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type); | |
231 | } | |
232 | } | |
233 | ||
234 | static void iommu_poll_events(struct amd_iommu *iommu) | |
235 | { | |
236 | u32 head, tail; | |
237 | unsigned long flags; | |
238 | ||
239 | spin_lock_irqsave(&iommu->lock, flags); | |
240 | ||
241 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
242 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
243 | ||
244 | while (head != tail) { | |
a345b23b | 245 | iommu_print_event(iommu, iommu->evt_buf + head); |
90008ee4 JR |
246 | head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size; |
247 | } | |
248 | ||
249 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
250 | ||
251 | spin_unlock_irqrestore(&iommu->lock, flags); | |
252 | } | |
253 | ||
a80dc3e0 JR |
254 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
255 | { | |
90008ee4 JR |
256 | struct amd_iommu *iommu; |
257 | ||
3bd22172 | 258 | for_each_iommu(iommu) |
90008ee4 JR |
259 | iommu_poll_events(iommu); |
260 | ||
261 | return IRQ_HANDLED; | |
a80dc3e0 JR |
262 | } |
263 | ||
431b2a20 JR |
264 | /**************************************************************************** |
265 | * | |
266 | * IOMMU command queuing functions | |
267 | * | |
268 | ****************************************************************************/ | |
269 | ||
270 | /* | |
271 | * Writes the command to the IOMMUs command buffer and informs the | |
272 | * hardware about the new command. Must be called with iommu->lock held. | |
273 | */ | |
d6449536 | 274 | static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec JR |
275 | { |
276 | u32 tail, head; | |
277 | u8 *target; | |
278 | ||
279 | tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
8a7c5ef3 | 280 | target = iommu->cmd_buf + tail; |
a19ae1ec JR |
281 | memcpy_toio(target, cmd, sizeof(*cmd)); |
282 | tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; | |
283 | head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); | |
284 | if (tail == head) | |
285 | return -ENOMEM; | |
286 | writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
287 | ||
288 | return 0; | |
289 | } | |
290 | ||
431b2a20 JR |
291 | /* |
292 | * General queuing function for commands. Takes iommu->lock and calls | |
293 | * __iommu_queue_command(). | |
294 | */ | |
d6449536 | 295 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec JR |
296 | { |
297 | unsigned long flags; | |
298 | int ret; | |
299 | ||
300 | spin_lock_irqsave(&iommu->lock, flags); | |
301 | ret = __iommu_queue_command(iommu, cmd); | |
09ee17eb | 302 | if (!ret) |
0cfd7aa9 | 303 | iommu->need_sync = true; |
a19ae1ec JR |
304 | spin_unlock_irqrestore(&iommu->lock, flags); |
305 | ||
306 | return ret; | |
307 | } | |
308 | ||
8d201968 JR |
309 | /* |
310 | * This function waits until an IOMMU has completed a completion | |
311 | * wait command | |
312 | */ | |
313 | static void __iommu_wait_for_completion(struct amd_iommu *iommu) | |
314 | { | |
315 | int ready = 0; | |
316 | unsigned status = 0; | |
317 | unsigned long i = 0; | |
318 | ||
da49f6df JR |
319 | INC_STATS_COUNTER(compl_wait); |
320 | ||
8d201968 JR |
321 | while (!ready && (i < EXIT_LOOP_COUNT)) { |
322 | ++i; | |
323 | /* wait for the bit to become one */ | |
324 | status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
325 | ready = status & MMIO_STATUS_COM_WAIT_INT_MASK; | |
326 | } | |
327 | ||
328 | /* set bit back to zero */ | |
329 | status &= ~MMIO_STATUS_COM_WAIT_INT_MASK; | |
330 | writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET); | |
331 | ||
6a1eddd2 JR |
332 | if (unlikely(i == EXIT_LOOP_COUNT)) { |
333 | spin_unlock(&iommu->lock); | |
334 | reset_iommu_command_buffer(iommu); | |
335 | spin_lock(&iommu->lock); | |
336 | } | |
8d201968 JR |
337 | } |
338 | ||
339 | /* | |
340 | * This function queues a completion wait command into the command | |
341 | * buffer of an IOMMU | |
342 | */ | |
343 | static int __iommu_completion_wait(struct amd_iommu *iommu) | |
344 | { | |
345 | struct iommu_cmd cmd; | |
346 | ||
347 | memset(&cmd, 0, sizeof(cmd)); | |
348 | cmd.data[0] = CMD_COMPL_WAIT_INT_MASK; | |
349 | CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT); | |
350 | ||
351 | return __iommu_queue_command(iommu, &cmd); | |
352 | } | |
353 | ||
431b2a20 JR |
354 | /* |
355 | * This function is called whenever we need to ensure that the IOMMU has | |
356 | * completed execution of all commands we sent. It sends a | |
357 | * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs | |
358 | * us about that by writing a value to a physical address we pass with | |
359 | * the command. | |
360 | */ | |
a19ae1ec JR |
361 | static int iommu_completion_wait(struct amd_iommu *iommu) |
362 | { | |
8d201968 JR |
363 | int ret = 0; |
364 | unsigned long flags; | |
a19ae1ec | 365 | |
7e4f88da JR |
366 | spin_lock_irqsave(&iommu->lock, flags); |
367 | ||
09ee17eb JR |
368 | if (!iommu->need_sync) |
369 | goto out; | |
370 | ||
8d201968 | 371 | ret = __iommu_completion_wait(iommu); |
09ee17eb | 372 | |
0cfd7aa9 | 373 | iommu->need_sync = false; |
a19ae1ec JR |
374 | |
375 | if (ret) | |
7e4f88da | 376 | goto out; |
a19ae1ec | 377 | |
8d201968 | 378 | __iommu_wait_for_completion(iommu); |
84df8175 | 379 | |
7e4f88da JR |
380 | out: |
381 | spin_unlock_irqrestore(&iommu->lock, flags); | |
a19ae1ec JR |
382 | |
383 | return 0; | |
384 | } | |
385 | ||
0518a3a4 JR |
386 | static void iommu_flush_complete(struct protection_domain *domain) |
387 | { | |
388 | int i; | |
389 | ||
390 | for (i = 0; i < amd_iommus_present; ++i) { | |
391 | if (!domain->dev_iommu[i]) | |
392 | continue; | |
393 | ||
394 | /* | |
395 | * Devices of this domain are behind this IOMMU | |
396 | * We need to wait for completion of all commands. | |
397 | */ | |
398 | iommu_completion_wait(amd_iommus[i]); | |
399 | } | |
400 | } | |
401 | ||
431b2a20 JR |
402 | /* |
403 | * Command send function for invalidating a device table entry | |
404 | */ | |
a19ae1ec JR |
405 | static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid) |
406 | { | |
d6449536 | 407 | struct iommu_cmd cmd; |
ee2fa743 | 408 | int ret; |
a19ae1ec JR |
409 | |
410 | BUG_ON(iommu == NULL); | |
411 | ||
412 | memset(&cmd, 0, sizeof(cmd)); | |
413 | CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY); | |
414 | cmd.data[0] = devid; | |
415 | ||
ee2fa743 JR |
416 | ret = iommu_queue_command(iommu, &cmd); |
417 | ||
ee2fa743 | 418 | return ret; |
a19ae1ec JR |
419 | } |
420 | ||
237b6f33 JR |
421 | static void __iommu_build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, |
422 | u16 domid, int pde, int s) | |
423 | { | |
424 | memset(cmd, 0, sizeof(*cmd)); | |
425 | address &= PAGE_MASK; | |
426 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
427 | cmd->data[1] |= domid; | |
428 | cmd->data[2] = lower_32_bits(address); | |
429 | cmd->data[3] = upper_32_bits(address); | |
430 | if (s) /* size bit - we flush more than one 4kb page */ | |
431 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
432 | if (pde) /* PDE bit - we wan't flush everything not only the PTEs */ | |
433 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
434 | } | |
435 | ||
431b2a20 JR |
436 | /* |
437 | * Generic command send function for invalidaing TLB entries | |
438 | */ | |
a19ae1ec JR |
439 | static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu, |
440 | u64 address, u16 domid, int pde, int s) | |
441 | { | |
d6449536 | 442 | struct iommu_cmd cmd; |
ee2fa743 | 443 | int ret; |
a19ae1ec | 444 | |
237b6f33 | 445 | __iommu_build_inv_iommu_pages(&cmd, address, domid, pde, s); |
a19ae1ec | 446 | |
ee2fa743 JR |
447 | ret = iommu_queue_command(iommu, &cmd); |
448 | ||
ee2fa743 | 449 | return ret; |
a19ae1ec JR |
450 | } |
451 | ||
431b2a20 JR |
452 | /* |
453 | * TLB invalidation function which is called from the mapping functions. | |
454 | * It invalidates a single PTE if the range to flush is within a single | |
455 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
456 | */ | |
6de8ad9b JR |
457 | static void __iommu_flush_pages(struct protection_domain *domain, |
458 | u64 address, size_t size, int pde) | |
a19ae1ec | 459 | { |
6de8ad9b | 460 | int s = 0, i; |
dcd1e92e | 461 | unsigned long pages = iommu_num_pages(address, size, PAGE_SIZE); |
a19ae1ec JR |
462 | |
463 | address &= PAGE_MASK; | |
464 | ||
999ba417 JR |
465 | if (pages > 1) { |
466 | /* | |
467 | * If we have to flush more than one page, flush all | |
468 | * TLB entries for this domain | |
469 | */ | |
470 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
471 | s = 1; | |
a19ae1ec JR |
472 | } |
473 | ||
999ba417 | 474 | |
6de8ad9b JR |
475 | for (i = 0; i < amd_iommus_present; ++i) { |
476 | if (!domain->dev_iommu[i]) | |
477 | continue; | |
478 | ||
479 | /* | |
480 | * Devices of this domain are behind this IOMMU | |
481 | * We need a TLB flush | |
482 | */ | |
483 | iommu_queue_inv_iommu_pages(amd_iommus[i], address, | |
484 | domain->id, pde, s); | |
485 | } | |
486 | ||
487 | return; | |
488 | } | |
489 | ||
490 | static void iommu_flush_pages(struct protection_domain *domain, | |
491 | u64 address, size_t size) | |
492 | { | |
493 | __iommu_flush_pages(domain, address, size, 0); | |
a19ae1ec | 494 | } |
b6c02715 | 495 | |
1c655773 | 496 | /* Flush the whole IO/TLB for a given protection domain */ |
dcd1e92e | 497 | static void iommu_flush_tlb(struct protection_domain *domain) |
1c655773 | 498 | { |
dcd1e92e | 499 | __iommu_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0); |
1c655773 JR |
500 | } |
501 | ||
42a49f96 | 502 | /* Flush the whole IO/TLB for a given protection domain - including PDE */ |
dcd1e92e | 503 | static void iommu_flush_tlb_pde(struct protection_domain *domain) |
42a49f96 | 504 | { |
dcd1e92e | 505 | __iommu_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1); |
42a49f96 CW |
506 | } |
507 | ||
43f49609 | 508 | /* |
09b42804 | 509 | * This function flushes all domains that have devices on the given IOMMU |
43f49609 | 510 | */ |
09b42804 | 511 | static void flush_all_domains_on_iommu(struct amd_iommu *iommu) |
43f49609 | 512 | { |
09b42804 JR |
513 | u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; |
514 | struct protection_domain *domain; | |
e394d72a | 515 | unsigned long flags; |
18811f55 | 516 | |
09b42804 | 517 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); |
bfd1be18 | 518 | |
09b42804 JR |
519 | list_for_each_entry(domain, &amd_iommu_pd_list, list) { |
520 | if (domain->dev_iommu[iommu->index] == 0) | |
bfd1be18 | 521 | continue; |
09b42804 JR |
522 | |
523 | spin_lock(&domain->lock); | |
524 | iommu_queue_inv_iommu_pages(iommu, address, domain->id, 1, 1); | |
525 | iommu_flush_complete(domain); | |
526 | spin_unlock(&domain->lock); | |
bfd1be18 | 527 | } |
e394d72a | 528 | |
09b42804 | 529 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); |
e394d72a JR |
530 | } |
531 | ||
09b42804 JR |
532 | /* |
533 | * This function uses heavy locking and may disable irqs for some time. But | |
534 | * this is no issue because it is only called during resume. | |
535 | */ | |
bfd1be18 | 536 | void amd_iommu_flush_all_domains(void) |
e394d72a | 537 | { |
e3306664 | 538 | struct protection_domain *domain; |
09b42804 JR |
539 | unsigned long flags; |
540 | ||
541 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
e394d72a | 542 | |
e3306664 | 543 | list_for_each_entry(domain, &amd_iommu_pd_list, list) { |
09b42804 | 544 | spin_lock(&domain->lock); |
e3306664 JR |
545 | iommu_flush_tlb_pde(domain); |
546 | iommu_flush_complete(domain); | |
09b42804 | 547 | spin_unlock(&domain->lock); |
e3306664 | 548 | } |
09b42804 JR |
549 | |
550 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
bfd1be18 JR |
551 | } |
552 | ||
d586d785 | 553 | static void flush_all_devices_for_iommu(struct amd_iommu *iommu) |
bfd1be18 JR |
554 | { |
555 | int i; | |
556 | ||
d586d785 JR |
557 | for (i = 0; i <= amd_iommu_last_bdf; ++i) { |
558 | if (iommu != amd_iommu_rlookup_table[i]) | |
bfd1be18 | 559 | continue; |
d586d785 JR |
560 | |
561 | iommu_queue_inv_dev_entry(iommu, i); | |
562 | iommu_completion_wait(iommu); | |
bfd1be18 JR |
563 | } |
564 | } | |
565 | ||
6a0dbcbe | 566 | static void flush_devices_by_domain(struct protection_domain *domain) |
7d7a110c JR |
567 | { |
568 | struct amd_iommu *iommu; | |
569 | int i; | |
570 | ||
571 | for (i = 0; i <= amd_iommu_last_bdf; ++i) { | |
6a0dbcbe JR |
572 | if ((domain == NULL && amd_iommu_pd_table[i] == NULL) || |
573 | (amd_iommu_pd_table[i] != domain)) | |
7d7a110c JR |
574 | continue; |
575 | ||
576 | iommu = amd_iommu_rlookup_table[i]; | |
577 | if (!iommu) | |
578 | continue; | |
579 | ||
580 | iommu_queue_inv_dev_entry(iommu, i); | |
581 | iommu_completion_wait(iommu); | |
582 | } | |
583 | } | |
584 | ||
a345b23b JR |
585 | static void reset_iommu_command_buffer(struct amd_iommu *iommu) |
586 | { | |
587 | pr_err("AMD-Vi: Resetting IOMMU command buffer\n"); | |
588 | ||
b26e81b8 JR |
589 | if (iommu->reset_in_progress) |
590 | panic("AMD-Vi: ILLEGAL_COMMAND_ERROR while resetting command buffer\n"); | |
591 | ||
592 | iommu->reset_in_progress = true; | |
593 | ||
a345b23b JR |
594 | amd_iommu_reset_cmd_buffer(iommu); |
595 | flush_all_devices_for_iommu(iommu); | |
596 | flush_all_domains_on_iommu(iommu); | |
b26e81b8 JR |
597 | |
598 | iommu->reset_in_progress = false; | |
a345b23b JR |
599 | } |
600 | ||
6a0dbcbe JR |
601 | void amd_iommu_flush_all_devices(void) |
602 | { | |
603 | flush_devices_by_domain(NULL); | |
604 | } | |
605 | ||
431b2a20 JR |
606 | /**************************************************************************** |
607 | * | |
608 | * The functions below are used the create the page table mappings for | |
609 | * unity mapped regions. | |
610 | * | |
611 | ****************************************************************************/ | |
612 | ||
613 | /* | |
614 | * Generic mapping functions. It maps a physical address into a DMA | |
615 | * address space. It allocates the page table pages if necessary. | |
616 | * In the future it can be extended to a generic mapping function | |
617 | * supporting all features of AMD IOMMU page tables like level skipping | |
618 | * and full 64 bit address spaces. | |
619 | */ | |
38e817fe JR |
620 | static int iommu_map_page(struct protection_domain *dom, |
621 | unsigned long bus_addr, | |
622 | unsigned long phys_addr, | |
abdc5eb3 JR |
623 | int prot, |
624 | int map_size) | |
bd0e5211 | 625 | { |
8bda3092 | 626 | u64 __pte, *pte; |
bd0e5211 JR |
627 | |
628 | bus_addr = PAGE_ALIGN(bus_addr); | |
bb9d4ff8 | 629 | phys_addr = PAGE_ALIGN(phys_addr); |
bd0e5211 | 630 | |
abdc5eb3 JR |
631 | BUG_ON(!PM_ALIGNED(map_size, bus_addr)); |
632 | BUG_ON(!PM_ALIGNED(map_size, phys_addr)); | |
633 | ||
bad1cac2 | 634 | if (!(prot & IOMMU_PROT_MASK)) |
bd0e5211 JR |
635 | return -EINVAL; |
636 | ||
abdc5eb3 | 637 | pte = alloc_pte(dom, bus_addr, map_size, NULL, GFP_KERNEL); |
bd0e5211 JR |
638 | |
639 | if (IOMMU_PTE_PRESENT(*pte)) | |
640 | return -EBUSY; | |
641 | ||
642 | __pte = phys_addr | IOMMU_PTE_P; | |
643 | if (prot & IOMMU_PROT_IR) | |
644 | __pte |= IOMMU_PTE_IR; | |
645 | if (prot & IOMMU_PROT_IW) | |
646 | __pte |= IOMMU_PTE_IW; | |
647 | ||
648 | *pte = __pte; | |
649 | ||
04bfdd84 JR |
650 | update_domain(dom); |
651 | ||
bd0e5211 JR |
652 | return 0; |
653 | } | |
654 | ||
eb74ff6c | 655 | static void iommu_unmap_page(struct protection_domain *dom, |
a6b256b4 | 656 | unsigned long bus_addr, int map_size) |
eb74ff6c | 657 | { |
a6b256b4 | 658 | u64 *pte = fetch_pte(dom, bus_addr, map_size); |
eb74ff6c | 659 | |
38a76eee JR |
660 | if (pte) |
661 | *pte = 0; | |
eb74ff6c | 662 | } |
eb74ff6c | 663 | |
431b2a20 JR |
664 | /* |
665 | * This function checks if a specific unity mapping entry is needed for | |
666 | * this specific IOMMU. | |
667 | */ | |
bd0e5211 JR |
668 | static int iommu_for_unity_map(struct amd_iommu *iommu, |
669 | struct unity_map_entry *entry) | |
670 | { | |
671 | u16 bdf, i; | |
672 | ||
673 | for (i = entry->devid_start; i <= entry->devid_end; ++i) { | |
674 | bdf = amd_iommu_alias_table[i]; | |
675 | if (amd_iommu_rlookup_table[bdf] == iommu) | |
676 | return 1; | |
677 | } | |
678 | ||
679 | return 0; | |
680 | } | |
681 | ||
431b2a20 JR |
682 | /* |
683 | * Init the unity mappings for a specific IOMMU in the system | |
684 | * | |
685 | * Basically iterates over all unity mapping entries and applies them to | |
686 | * the default domain DMA of that IOMMU if necessary. | |
687 | */ | |
bd0e5211 JR |
688 | static int iommu_init_unity_mappings(struct amd_iommu *iommu) |
689 | { | |
690 | struct unity_map_entry *entry; | |
691 | int ret; | |
692 | ||
693 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
694 | if (!iommu_for_unity_map(iommu, entry)) | |
695 | continue; | |
696 | ret = dma_ops_unity_map(iommu->default_dom, entry); | |
697 | if (ret) | |
698 | return ret; | |
699 | } | |
700 | ||
701 | return 0; | |
702 | } | |
703 | ||
431b2a20 JR |
704 | /* |
705 | * This function actually applies the mapping to the page table of the | |
706 | * dma_ops domain. | |
707 | */ | |
bd0e5211 JR |
708 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
709 | struct unity_map_entry *e) | |
710 | { | |
711 | u64 addr; | |
712 | int ret; | |
713 | ||
714 | for (addr = e->address_start; addr < e->address_end; | |
715 | addr += PAGE_SIZE) { | |
abdc5eb3 JR |
716 | ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot, |
717 | PM_MAP_4k); | |
bd0e5211 JR |
718 | if (ret) |
719 | return ret; | |
720 | /* | |
721 | * if unity mapping is in aperture range mark the page | |
722 | * as allocated in the aperture | |
723 | */ | |
724 | if (addr < dma_dom->aperture_size) | |
c3239567 | 725 | __set_bit(addr >> PAGE_SHIFT, |
384de729 | 726 | dma_dom->aperture[0]->bitmap); |
bd0e5211 JR |
727 | } |
728 | ||
729 | return 0; | |
730 | } | |
731 | ||
431b2a20 JR |
732 | /* |
733 | * Inits the unity mappings required for a specific device | |
734 | */ | |
bd0e5211 JR |
735 | static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom, |
736 | u16 devid) | |
737 | { | |
738 | struct unity_map_entry *e; | |
739 | int ret; | |
740 | ||
741 | list_for_each_entry(e, &amd_iommu_unity_map, list) { | |
742 | if (!(devid >= e->devid_start && devid <= e->devid_end)) | |
743 | continue; | |
744 | ret = dma_ops_unity_map(dma_dom, e); | |
745 | if (ret) | |
746 | return ret; | |
747 | } | |
748 | ||
749 | return 0; | |
750 | } | |
751 | ||
431b2a20 JR |
752 | /**************************************************************************** |
753 | * | |
754 | * The next functions belong to the address allocator for the dma_ops | |
755 | * interface functions. They work like the allocators in the other IOMMU | |
756 | * drivers. Its basically a bitmap which marks the allocated pages in | |
757 | * the aperture. Maybe it could be enhanced in the future to a more | |
758 | * efficient allocator. | |
759 | * | |
760 | ****************************************************************************/ | |
d3086444 | 761 | |
431b2a20 | 762 | /* |
384de729 | 763 | * The address allocator core functions. |
431b2a20 JR |
764 | * |
765 | * called with domain->lock held | |
766 | */ | |
384de729 | 767 | |
00cd122a JR |
768 | /* |
769 | * This function checks if there is a PTE for a given dma address. If | |
770 | * there is one, it returns the pointer to it. | |
771 | */ | |
9355a081 | 772 | static u64 *fetch_pte(struct protection_domain *domain, |
a6b256b4 | 773 | unsigned long address, int map_size) |
00cd122a | 774 | { |
9355a081 | 775 | int level; |
00cd122a JR |
776 | u64 *pte; |
777 | ||
9355a081 JR |
778 | level = domain->mode - 1; |
779 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
00cd122a | 780 | |
a6b256b4 | 781 | while (level > map_size) { |
9355a081 JR |
782 | if (!IOMMU_PTE_PRESENT(*pte)) |
783 | return NULL; | |
00cd122a | 784 | |
9355a081 | 785 | level -= 1; |
00cd122a | 786 | |
9355a081 JR |
787 | pte = IOMMU_PTE_PAGE(*pte); |
788 | pte = &pte[PM_LEVEL_INDEX(level, address)]; | |
00cd122a | 789 | |
a6b256b4 JR |
790 | if ((PM_PTE_LEVEL(*pte) == 0) && level != map_size) { |
791 | pte = NULL; | |
792 | break; | |
793 | } | |
9355a081 | 794 | } |
00cd122a JR |
795 | |
796 | return pte; | |
797 | } | |
798 | ||
9cabe89b JR |
799 | /* |
800 | * This function is used to add a new aperture range to an existing | |
801 | * aperture in case of dma_ops domain allocation or address allocation | |
802 | * failure. | |
803 | */ | |
576175c2 | 804 | static int alloc_new_range(struct dma_ops_domain *dma_dom, |
9cabe89b JR |
805 | bool populate, gfp_t gfp) |
806 | { | |
807 | int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT; | |
576175c2 | 808 | struct amd_iommu *iommu; |
00cd122a | 809 | int i; |
9cabe89b | 810 | |
f5e9705c JR |
811 | #ifdef CONFIG_IOMMU_STRESS |
812 | populate = false; | |
813 | #endif | |
814 | ||
9cabe89b JR |
815 | if (index >= APERTURE_MAX_RANGES) |
816 | return -ENOMEM; | |
817 | ||
818 | dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp); | |
819 | if (!dma_dom->aperture[index]) | |
820 | return -ENOMEM; | |
821 | ||
822 | dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp); | |
823 | if (!dma_dom->aperture[index]->bitmap) | |
824 | goto out_free; | |
825 | ||
826 | dma_dom->aperture[index]->offset = dma_dom->aperture_size; | |
827 | ||
828 | if (populate) { | |
829 | unsigned long address = dma_dom->aperture_size; | |
830 | int i, num_ptes = APERTURE_RANGE_PAGES / 512; | |
831 | u64 *pte, *pte_page; | |
832 | ||
833 | for (i = 0; i < num_ptes; ++i) { | |
abdc5eb3 | 834 | pte = alloc_pte(&dma_dom->domain, address, PM_MAP_4k, |
9cabe89b JR |
835 | &pte_page, gfp); |
836 | if (!pte) | |
837 | goto out_free; | |
838 | ||
839 | dma_dom->aperture[index]->pte_pages[i] = pte_page; | |
840 | ||
841 | address += APERTURE_RANGE_SIZE / 64; | |
842 | } | |
843 | } | |
844 | ||
845 | dma_dom->aperture_size += APERTURE_RANGE_SIZE; | |
846 | ||
00cd122a | 847 | /* Intialize the exclusion range if necessary */ |
576175c2 JR |
848 | for_each_iommu(iommu) { |
849 | if (iommu->exclusion_start && | |
850 | iommu->exclusion_start >= dma_dom->aperture[index]->offset | |
851 | && iommu->exclusion_start < dma_dom->aperture_size) { | |
852 | unsigned long startpage; | |
853 | int pages = iommu_num_pages(iommu->exclusion_start, | |
854 | iommu->exclusion_length, | |
855 | PAGE_SIZE); | |
856 | startpage = iommu->exclusion_start >> PAGE_SHIFT; | |
857 | dma_ops_reserve_addresses(dma_dom, startpage, pages); | |
858 | } | |
00cd122a JR |
859 | } |
860 | ||
861 | /* | |
862 | * Check for areas already mapped as present in the new aperture | |
863 | * range and mark those pages as reserved in the allocator. Such | |
864 | * mappings may already exist as a result of requested unity | |
865 | * mappings for devices. | |
866 | */ | |
867 | for (i = dma_dom->aperture[index]->offset; | |
868 | i < dma_dom->aperture_size; | |
869 | i += PAGE_SIZE) { | |
a6b256b4 | 870 | u64 *pte = fetch_pte(&dma_dom->domain, i, PM_MAP_4k); |
00cd122a JR |
871 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
872 | continue; | |
873 | ||
874 | dma_ops_reserve_addresses(dma_dom, i << PAGE_SHIFT, 1); | |
875 | } | |
876 | ||
04bfdd84 JR |
877 | update_domain(&dma_dom->domain); |
878 | ||
9cabe89b JR |
879 | return 0; |
880 | ||
881 | out_free: | |
04bfdd84 JR |
882 | update_domain(&dma_dom->domain); |
883 | ||
9cabe89b JR |
884 | free_page((unsigned long)dma_dom->aperture[index]->bitmap); |
885 | ||
886 | kfree(dma_dom->aperture[index]); | |
887 | dma_dom->aperture[index] = NULL; | |
888 | ||
889 | return -ENOMEM; | |
890 | } | |
891 | ||
384de729 JR |
892 | static unsigned long dma_ops_area_alloc(struct device *dev, |
893 | struct dma_ops_domain *dom, | |
894 | unsigned int pages, | |
895 | unsigned long align_mask, | |
896 | u64 dma_mask, | |
897 | unsigned long start) | |
898 | { | |
803b8cb4 | 899 | unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE; |
384de729 JR |
900 | int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT; |
901 | int i = start >> APERTURE_RANGE_SHIFT; | |
902 | unsigned long boundary_size; | |
903 | unsigned long address = -1; | |
904 | unsigned long limit; | |
905 | ||
803b8cb4 JR |
906 | next_bit >>= PAGE_SHIFT; |
907 | ||
384de729 JR |
908 | boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, |
909 | PAGE_SIZE) >> PAGE_SHIFT; | |
910 | ||
911 | for (;i < max_index; ++i) { | |
912 | unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT; | |
913 | ||
914 | if (dom->aperture[i]->offset >= dma_mask) | |
915 | break; | |
916 | ||
917 | limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset, | |
918 | dma_mask >> PAGE_SHIFT); | |
919 | ||
920 | address = iommu_area_alloc(dom->aperture[i]->bitmap, | |
921 | limit, next_bit, pages, 0, | |
922 | boundary_size, align_mask); | |
923 | if (address != -1) { | |
924 | address = dom->aperture[i]->offset + | |
925 | (address << PAGE_SHIFT); | |
803b8cb4 | 926 | dom->next_address = address + (pages << PAGE_SHIFT); |
384de729 JR |
927 | break; |
928 | } | |
929 | ||
930 | next_bit = 0; | |
931 | } | |
932 | ||
933 | return address; | |
934 | } | |
935 | ||
d3086444 JR |
936 | static unsigned long dma_ops_alloc_addresses(struct device *dev, |
937 | struct dma_ops_domain *dom, | |
6d4f343f | 938 | unsigned int pages, |
832a90c3 JR |
939 | unsigned long align_mask, |
940 | u64 dma_mask) | |
d3086444 | 941 | { |
d3086444 | 942 | unsigned long address; |
d3086444 | 943 | |
fe16f088 JR |
944 | #ifdef CONFIG_IOMMU_STRESS |
945 | dom->next_address = 0; | |
946 | dom->need_flush = true; | |
947 | #endif | |
d3086444 | 948 | |
384de729 | 949 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
803b8cb4 | 950 | dma_mask, dom->next_address); |
d3086444 | 951 | |
1c655773 | 952 | if (address == -1) { |
803b8cb4 | 953 | dom->next_address = 0; |
384de729 JR |
954 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
955 | dma_mask, 0); | |
1c655773 JR |
956 | dom->need_flush = true; |
957 | } | |
d3086444 | 958 | |
384de729 | 959 | if (unlikely(address == -1)) |
8fd524b3 | 960 | address = DMA_ERROR_CODE; |
d3086444 JR |
961 | |
962 | WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size); | |
963 | ||
964 | return address; | |
965 | } | |
966 | ||
431b2a20 JR |
967 | /* |
968 | * The address free function. | |
969 | * | |
970 | * called with domain->lock held | |
971 | */ | |
d3086444 JR |
972 | static void dma_ops_free_addresses(struct dma_ops_domain *dom, |
973 | unsigned long address, | |
974 | unsigned int pages) | |
975 | { | |
384de729 JR |
976 | unsigned i = address >> APERTURE_RANGE_SHIFT; |
977 | struct aperture_range *range = dom->aperture[i]; | |
80be308d | 978 | |
384de729 JR |
979 | BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL); |
980 | ||
47bccd6b JR |
981 | #ifdef CONFIG_IOMMU_STRESS |
982 | if (i < 4) | |
983 | return; | |
984 | #endif | |
80be308d | 985 | |
803b8cb4 | 986 | if (address >= dom->next_address) |
80be308d | 987 | dom->need_flush = true; |
384de729 JR |
988 | |
989 | address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT; | |
803b8cb4 | 990 | |
384de729 JR |
991 | iommu_area_free(range->bitmap, address, pages); |
992 | ||
d3086444 JR |
993 | } |
994 | ||
431b2a20 JR |
995 | /**************************************************************************** |
996 | * | |
997 | * The next functions belong to the domain allocation. A domain is | |
998 | * allocated for every IOMMU as the default domain. If device isolation | |
999 | * is enabled, every device get its own domain. The most important thing | |
1000 | * about domains is the page table mapping the DMA address space they | |
1001 | * contain. | |
1002 | * | |
1003 | ****************************************************************************/ | |
1004 | ||
aeb26f55 JR |
1005 | /* |
1006 | * This function adds a protection domain to the global protection domain list | |
1007 | */ | |
1008 | static void add_domain_to_list(struct protection_domain *domain) | |
1009 | { | |
1010 | unsigned long flags; | |
1011 | ||
1012 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1013 | list_add(&domain->list, &amd_iommu_pd_list); | |
1014 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1015 | } | |
1016 | ||
1017 | /* | |
1018 | * This function removes a protection domain to the global | |
1019 | * protection domain list | |
1020 | */ | |
1021 | static void del_domain_from_list(struct protection_domain *domain) | |
1022 | { | |
1023 | unsigned long flags; | |
1024 | ||
1025 | spin_lock_irqsave(&amd_iommu_pd_lock, flags); | |
1026 | list_del(&domain->list); | |
1027 | spin_unlock_irqrestore(&amd_iommu_pd_lock, flags); | |
1028 | } | |
1029 | ||
ec487d1a JR |
1030 | static u16 domain_id_alloc(void) |
1031 | { | |
1032 | unsigned long flags; | |
1033 | int id; | |
1034 | ||
1035 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1036 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); | |
1037 | BUG_ON(id == 0); | |
1038 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1039 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
1040 | else | |
1041 | id = 0; | |
1042 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1043 | ||
1044 | return id; | |
1045 | } | |
1046 | ||
a2acfb75 JR |
1047 | static void domain_id_free(int id) |
1048 | { | |
1049 | unsigned long flags; | |
1050 | ||
1051 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1052 | if (id > 0 && id < MAX_DOMAIN_ID) | |
1053 | __clear_bit(id, amd_iommu_pd_alloc_bitmap); | |
1054 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1055 | } | |
a2acfb75 | 1056 | |
431b2a20 JR |
1057 | /* |
1058 | * Used to reserve address ranges in the aperture (e.g. for exclusion | |
1059 | * ranges. | |
1060 | */ | |
ec487d1a JR |
1061 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, |
1062 | unsigned long start_page, | |
1063 | unsigned int pages) | |
1064 | { | |
384de729 | 1065 | unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT; |
ec487d1a JR |
1066 | |
1067 | if (start_page + pages > last_page) | |
1068 | pages = last_page - start_page; | |
1069 | ||
384de729 JR |
1070 | for (i = start_page; i < start_page + pages; ++i) { |
1071 | int index = i / APERTURE_RANGE_PAGES; | |
1072 | int page = i % APERTURE_RANGE_PAGES; | |
1073 | __set_bit(page, dom->aperture[index]->bitmap); | |
1074 | } | |
ec487d1a JR |
1075 | } |
1076 | ||
86db2e5d | 1077 | static void free_pagetable(struct protection_domain *domain) |
ec487d1a JR |
1078 | { |
1079 | int i, j; | |
1080 | u64 *p1, *p2, *p3; | |
1081 | ||
86db2e5d | 1082 | p1 = domain->pt_root; |
ec487d1a JR |
1083 | |
1084 | if (!p1) | |
1085 | return; | |
1086 | ||
1087 | for (i = 0; i < 512; ++i) { | |
1088 | if (!IOMMU_PTE_PRESENT(p1[i])) | |
1089 | continue; | |
1090 | ||
1091 | p2 = IOMMU_PTE_PAGE(p1[i]); | |
3cc3d84b | 1092 | for (j = 0; j < 512; ++j) { |
ec487d1a JR |
1093 | if (!IOMMU_PTE_PRESENT(p2[j])) |
1094 | continue; | |
1095 | p3 = IOMMU_PTE_PAGE(p2[j]); | |
1096 | free_page((unsigned long)p3); | |
1097 | } | |
1098 | ||
1099 | free_page((unsigned long)p2); | |
1100 | } | |
1101 | ||
1102 | free_page((unsigned long)p1); | |
86db2e5d JR |
1103 | |
1104 | domain->pt_root = NULL; | |
ec487d1a JR |
1105 | } |
1106 | ||
431b2a20 JR |
1107 | /* |
1108 | * Free a domain, only used if something went wrong in the | |
1109 | * allocation path and we need to free an already allocated page table | |
1110 | */ | |
ec487d1a JR |
1111 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
1112 | { | |
384de729 JR |
1113 | int i; |
1114 | ||
ec487d1a JR |
1115 | if (!dom) |
1116 | return; | |
1117 | ||
aeb26f55 JR |
1118 | del_domain_from_list(&dom->domain); |
1119 | ||
86db2e5d | 1120 | free_pagetable(&dom->domain); |
ec487d1a | 1121 | |
384de729 JR |
1122 | for (i = 0; i < APERTURE_MAX_RANGES; ++i) { |
1123 | if (!dom->aperture[i]) | |
1124 | continue; | |
1125 | free_page((unsigned long)dom->aperture[i]->bitmap); | |
1126 | kfree(dom->aperture[i]); | |
1127 | } | |
ec487d1a JR |
1128 | |
1129 | kfree(dom); | |
1130 | } | |
1131 | ||
431b2a20 JR |
1132 | /* |
1133 | * Allocates a new protection domain usable for the dma_ops functions. | |
1134 | * It also intializes the page table and the address allocator data | |
1135 | * structures required for the dma_ops interface | |
1136 | */ | |
d9cfed92 | 1137 | static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu) |
ec487d1a JR |
1138 | { |
1139 | struct dma_ops_domain *dma_dom; | |
ec487d1a JR |
1140 | |
1141 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
1142 | if (!dma_dom) | |
1143 | return NULL; | |
1144 | ||
1145 | spin_lock_init(&dma_dom->domain.lock); | |
1146 | ||
1147 | dma_dom->domain.id = domain_id_alloc(); | |
1148 | if (dma_dom->domain.id == 0) | |
1149 | goto free_dma_dom; | |
8f7a017c | 1150 | dma_dom->domain.mode = PAGE_MODE_2_LEVEL; |
ec487d1a | 1151 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
9fdb19d6 | 1152 | dma_dom->domain.flags = PD_DMA_OPS_MASK; |
ec487d1a JR |
1153 | dma_dom->domain.priv = dma_dom; |
1154 | if (!dma_dom->domain.pt_root) | |
1155 | goto free_dma_dom; | |
ec487d1a | 1156 | |
1c655773 | 1157 | dma_dom->need_flush = false; |
bd60b735 | 1158 | dma_dom->target_dev = 0xffff; |
1c655773 | 1159 | |
aeb26f55 JR |
1160 | add_domain_to_list(&dma_dom->domain); |
1161 | ||
576175c2 | 1162 | if (alloc_new_range(dma_dom, true, GFP_KERNEL)) |
ec487d1a | 1163 | goto free_dma_dom; |
ec487d1a | 1164 | |
431b2a20 | 1165 | /* |
ec487d1a JR |
1166 | * mark the first page as allocated so we never return 0 as |
1167 | * a valid dma-address. So we can use 0 as error value | |
431b2a20 | 1168 | */ |
384de729 | 1169 | dma_dom->aperture[0]->bitmap[0] = 1; |
803b8cb4 | 1170 | dma_dom->next_address = 0; |
ec487d1a | 1171 | |
ec487d1a JR |
1172 | |
1173 | return dma_dom; | |
1174 | ||
1175 | free_dma_dom: | |
1176 | dma_ops_domain_free(dma_dom); | |
1177 | ||
1178 | return NULL; | |
1179 | } | |
1180 | ||
5b28df6f JR |
1181 | /* |
1182 | * little helper function to check whether a given protection domain is a | |
1183 | * dma_ops domain | |
1184 | */ | |
1185 | static bool dma_ops_domain(struct protection_domain *domain) | |
1186 | { | |
1187 | return domain->flags & PD_DMA_OPS_MASK; | |
1188 | } | |
1189 | ||
407d733e | 1190 | static void set_dte_entry(u16 devid, struct protection_domain *domain) |
b20ac0d4 | 1191 | { |
15898bbc | 1192 | struct amd_iommu *iommu = amd_iommu_rlookup_table[devid]; |
b20ac0d4 | 1193 | u64 pte_root = virt_to_phys(domain->pt_root); |
863c74eb | 1194 | |
15898bbc JR |
1195 | BUG_ON(amd_iommu_pd_table[devid] != NULL); |
1196 | ||
38ddf41b JR |
1197 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) |
1198 | << DEV_ENTRY_MODE_SHIFT; | |
1199 | pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV; | |
b20ac0d4 | 1200 | |
b20ac0d4 | 1201 | amd_iommu_dev_table[devid].data[2] = domain->id; |
aa879fff JR |
1202 | amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root); |
1203 | amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root); | |
b20ac0d4 JR |
1204 | |
1205 | amd_iommu_pd_table[devid] = domain; | |
15898bbc JR |
1206 | |
1207 | /* Do reference counting */ | |
1208 | domain->dev_iommu[iommu->index] += 1; | |
1209 | domain->dev_cnt += 1; | |
1210 | ||
1211 | /* Flush the changes DTE entry */ | |
1212 | iommu_queue_inv_dev_entry(iommu, devid); | |
1213 | } | |
1214 | ||
1215 | static void clear_dte_entry(u16 devid) | |
1216 | { | |
1217 | struct protection_domain *domain = amd_iommu_pd_table[devid]; | |
1218 | struct amd_iommu *iommu = amd_iommu_rlookup_table[devid]; | |
1219 | ||
1220 | BUG_ON(domain == NULL); | |
1221 | ||
1222 | /* remove domain from the lookup table */ | |
1223 | amd_iommu_pd_table[devid] = NULL; | |
1224 | ||
1225 | /* remove entry from the device table seen by the hardware */ | |
1226 | amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV; | |
1227 | amd_iommu_dev_table[devid].data[1] = 0; | |
1228 | amd_iommu_dev_table[devid].data[2] = 0; | |
1229 | ||
1230 | amd_iommu_apply_erratum_63(devid); | |
1231 | ||
1232 | /* decrease reference counters */ | |
1233 | domain->dev_iommu[iommu->index] -= 1; | |
1234 | domain->dev_cnt -= 1; | |
1235 | ||
1236 | iommu_queue_inv_dev_entry(iommu, devid); | |
2b681faf JR |
1237 | } |
1238 | ||
1239 | /* | |
1240 | * If a device is not yet associated with a domain, this function does | |
1241 | * assigns it visible for the hardware | |
1242 | */ | |
15898bbc JR |
1243 | static int __attach_device(struct device *dev, |
1244 | struct protection_domain *domain) | |
2b681faf | 1245 | { |
15898bbc JR |
1246 | u16 devid = get_device_id(dev); |
1247 | u16 alias = amd_iommu_alias_table[devid]; | |
1248 | ||
2b681faf JR |
1249 | /* lock domain */ |
1250 | spin_lock(&domain->lock); | |
1251 | ||
15898bbc JR |
1252 | /* Some sanity checks */ |
1253 | if (amd_iommu_pd_table[alias] != NULL && | |
1254 | amd_iommu_pd_table[alias] != domain) | |
1255 | return -EBUSY; | |
eba6ac60 | 1256 | |
15898bbc JR |
1257 | if (amd_iommu_pd_table[devid] != NULL && |
1258 | amd_iommu_pd_table[devid] != domain) | |
1259 | return -EBUSY; | |
1260 | ||
1261 | /* Do real assignment */ | |
1262 | if (alias != devid && | |
1263 | amd_iommu_pd_table[alias] == NULL) | |
1264 | set_dte_entry(alias, domain); | |
1265 | ||
1266 | if (amd_iommu_pd_table[devid] == NULL) | |
1267 | set_dte_entry(devid, domain); | |
eba6ac60 JR |
1268 | |
1269 | /* ready */ | |
1270 | spin_unlock(&domain->lock); | |
15898bbc JR |
1271 | |
1272 | return 0; | |
0feae533 | 1273 | } |
b20ac0d4 | 1274 | |
407d733e JR |
1275 | /* |
1276 | * If a device is not yet associated with a domain, this function does | |
1277 | * assigns it visible for the hardware | |
1278 | */ | |
15898bbc JR |
1279 | static int attach_device(struct device *dev, |
1280 | struct protection_domain *domain) | |
0feae533 | 1281 | { |
eba6ac60 | 1282 | unsigned long flags; |
15898bbc | 1283 | int ret; |
eba6ac60 JR |
1284 | |
1285 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
15898bbc | 1286 | ret = __attach_device(dev, domain); |
b20ac0d4 JR |
1287 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
1288 | ||
0feae533 JR |
1289 | /* |
1290 | * We might boot into a crash-kernel here. The crashed kernel | |
1291 | * left the caches in the IOMMU dirty. So we have to flush | |
1292 | * here to evict all dirty stuff. | |
1293 | */ | |
dcd1e92e | 1294 | iommu_flush_tlb_pde(domain); |
15898bbc JR |
1295 | |
1296 | return ret; | |
b20ac0d4 JR |
1297 | } |
1298 | ||
355bf553 JR |
1299 | /* |
1300 | * Removes a device from a protection domain (unlocked) | |
1301 | */ | |
15898bbc | 1302 | static void __detach_device(struct device *dev) |
355bf553 | 1303 | { |
15898bbc | 1304 | u16 devid = get_device_id(dev); |
c4596114 JR |
1305 | struct amd_iommu *iommu = amd_iommu_rlookup_table[devid]; |
1306 | ||
1307 | BUG_ON(!iommu); | |
355bf553 | 1308 | |
15898bbc | 1309 | clear_dte_entry(devid); |
21129f78 JR |
1310 | |
1311 | /* | |
1312 | * If we run in passthrough mode the device must be assigned to the | |
1313 | * passthrough domain if it is detached from any other domain | |
1314 | */ | |
15898bbc JR |
1315 | if (iommu_pass_through) |
1316 | __attach_device(dev, pt_domain); | |
355bf553 JR |
1317 | } |
1318 | ||
1319 | /* | |
1320 | * Removes a device from a protection domain (with devtable_lock held) | |
1321 | */ | |
15898bbc | 1322 | static void detach_device(struct device *dev) |
355bf553 JR |
1323 | { |
1324 | unsigned long flags; | |
1325 | ||
1326 | /* lock device table */ | |
1327 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
15898bbc | 1328 | __detach_device(dev); |
355bf553 JR |
1329 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
1330 | } | |
e275a2a0 | 1331 | |
15898bbc JR |
1332 | /* |
1333 | * Find out the protection domain structure for a given PCI device. This | |
1334 | * will give us the pointer to the page table root for example. | |
1335 | */ | |
1336 | static struct protection_domain *domain_for_device(struct device *dev) | |
1337 | { | |
1338 | struct protection_domain *dom; | |
1339 | unsigned long flags; | |
1340 | u16 devid, alias; | |
1341 | ||
1342 | devid = get_device_id(dev); | |
1343 | alias = amd_iommu_alias_table[devid]; | |
1344 | ||
1345 | read_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1346 | dom = amd_iommu_pd_table[devid]; | |
1347 | if (dom == NULL && | |
1348 | amd_iommu_pd_table[alias] != NULL) { | |
1349 | __attach_device(dev, amd_iommu_pd_table[alias]); | |
1350 | dom = amd_iommu_pd_table[devid]; | |
1351 | } | |
1352 | ||
1353 | read_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1354 | ||
1355 | return dom; | |
1356 | } | |
1357 | ||
e275a2a0 JR |
1358 | static int device_change_notifier(struct notifier_block *nb, |
1359 | unsigned long action, void *data) | |
1360 | { | |
1361 | struct device *dev = data; | |
1362 | struct pci_dev *pdev = to_pci_dev(dev); | |
1363 | u16 devid = calc_devid(pdev->bus->number, pdev->devfn); | |
1364 | struct protection_domain *domain; | |
1365 | struct dma_ops_domain *dma_domain; | |
1366 | struct amd_iommu *iommu; | |
1ac4cbbc | 1367 | unsigned long flags; |
e275a2a0 JR |
1368 | |
1369 | if (devid > amd_iommu_last_bdf) | |
1370 | goto out; | |
1371 | ||
1372 | devid = amd_iommu_alias_table[devid]; | |
1373 | ||
1374 | iommu = amd_iommu_rlookup_table[devid]; | |
1375 | if (iommu == NULL) | |
1376 | goto out; | |
1377 | ||
15898bbc | 1378 | domain = domain_for_device(dev); |
e275a2a0 JR |
1379 | |
1380 | if (domain && !dma_ops_domain(domain)) | |
1381 | WARN_ONCE(1, "AMD IOMMU WARNING: device %s already bound " | |
1382 | "to a non-dma-ops domain\n", dev_name(dev)); | |
1383 | ||
1384 | switch (action) { | |
c1eee67b | 1385 | case BUS_NOTIFY_UNBOUND_DRIVER: |
e275a2a0 JR |
1386 | if (!domain) |
1387 | goto out; | |
a1ca331c JR |
1388 | if (iommu_pass_through) |
1389 | break; | |
15898bbc | 1390 | detach_device(dev); |
1ac4cbbc JR |
1391 | break; |
1392 | case BUS_NOTIFY_ADD_DEVICE: | |
1393 | /* allocate a protection domain if a device is added */ | |
1394 | dma_domain = find_protection_domain(devid); | |
1395 | if (dma_domain) | |
1396 | goto out; | |
d9cfed92 | 1397 | dma_domain = dma_ops_domain_alloc(iommu); |
1ac4cbbc JR |
1398 | if (!dma_domain) |
1399 | goto out; | |
1400 | dma_domain->target_dev = devid; | |
1401 | ||
1402 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
1403 | list_add_tail(&dma_domain->list, &iommu_pd_list); | |
1404 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
1405 | ||
e275a2a0 JR |
1406 | break; |
1407 | default: | |
1408 | goto out; | |
1409 | } | |
1410 | ||
1411 | iommu_queue_inv_dev_entry(iommu, devid); | |
1412 | iommu_completion_wait(iommu); | |
1413 | ||
1414 | out: | |
1415 | return 0; | |
1416 | } | |
1417 | ||
b25ae679 | 1418 | static struct notifier_block device_nb = { |
e275a2a0 JR |
1419 | .notifier_call = device_change_notifier, |
1420 | }; | |
355bf553 | 1421 | |
431b2a20 JR |
1422 | /***************************************************************************** |
1423 | * | |
1424 | * The next functions belong to the dma_ops mapping/unmapping code. | |
1425 | * | |
1426 | *****************************************************************************/ | |
1427 | ||
dbcc112e JR |
1428 | /* |
1429 | * This function checks if the driver got a valid device from the caller to | |
1430 | * avoid dereferencing invalid pointers. | |
1431 | */ | |
1432 | static bool check_device(struct device *dev) | |
1433 | { | |
420aef8a JR |
1434 | u16 bdf; |
1435 | struct pci_dev *pcidev; | |
1436 | ||
dbcc112e JR |
1437 | if (!dev || !dev->dma_mask) |
1438 | return false; | |
1439 | ||
420aef8a JR |
1440 | /* No device or no PCI device */ |
1441 | if (!dev || dev->bus != &pci_bus_type) | |
1442 | return false; | |
1443 | ||
1444 | pcidev = to_pci_dev(dev); | |
1445 | ||
1446 | bdf = calc_devid(pcidev->bus->number, pcidev->devfn); | |
1447 | ||
1448 | /* Out of our scope? */ | |
1449 | if (bdf > amd_iommu_last_bdf) | |
1450 | return false; | |
1451 | ||
1452 | if (amd_iommu_rlookup_table[bdf] == NULL) | |
1453 | return false; | |
1454 | ||
dbcc112e JR |
1455 | return true; |
1456 | } | |
1457 | ||
bd60b735 JR |
1458 | /* |
1459 | * In this function the list of preallocated protection domains is traversed to | |
1460 | * find the domain for a specific device | |
1461 | */ | |
1462 | static struct dma_ops_domain *find_protection_domain(u16 devid) | |
1463 | { | |
1464 | struct dma_ops_domain *entry, *ret = NULL; | |
1465 | unsigned long flags; | |
94f6d190 | 1466 | u16 alias = amd_iommu_alias_table[devid]; |
bd60b735 JR |
1467 | |
1468 | if (list_empty(&iommu_pd_list)) | |
1469 | return NULL; | |
1470 | ||
1471 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
1472 | ||
1473 | list_for_each_entry(entry, &iommu_pd_list, list) { | |
94f6d190 JR |
1474 | if (entry->target_dev == devid || |
1475 | entry->target_dev == alias) { | |
bd60b735 | 1476 | ret = entry; |
bd60b735 JR |
1477 | break; |
1478 | } | |
1479 | } | |
1480 | ||
1481 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
1482 | ||
1483 | return ret; | |
1484 | } | |
1485 | ||
431b2a20 JR |
1486 | /* |
1487 | * In the dma_ops path we only have the struct device. This function | |
1488 | * finds the corresponding IOMMU, the protection domain and the | |
1489 | * requestor id for a given device. | |
1490 | * If the device is not yet associated with a domain this is also done | |
1491 | * in this function. | |
1492 | */ | |
94f6d190 | 1493 | static struct protection_domain *get_domain(struct device *dev) |
b20ac0d4 | 1494 | { |
94f6d190 | 1495 | struct protection_domain *domain; |
b20ac0d4 | 1496 | struct dma_ops_domain *dma_dom; |
94f6d190 | 1497 | u16 devid = get_device_id(dev); |
b20ac0d4 | 1498 | |
f99c0f1c | 1499 | if (!check_device(dev)) |
94f6d190 | 1500 | return ERR_PTR(-EINVAL); |
b20ac0d4 | 1501 | |
94f6d190 JR |
1502 | domain = domain_for_device(dev); |
1503 | if (domain != NULL && !dma_ops_domain(domain)) | |
1504 | return ERR_PTR(-EBUSY); | |
f99c0f1c | 1505 | |
94f6d190 JR |
1506 | if (domain != NULL) |
1507 | return domain; | |
b20ac0d4 | 1508 | |
15898bbc | 1509 | /* Device not bount yet - bind it */ |
94f6d190 | 1510 | dma_dom = find_protection_domain(devid); |
15898bbc | 1511 | if (!dma_dom) |
94f6d190 JR |
1512 | dma_dom = amd_iommu_rlookup_table[devid]->default_dom; |
1513 | attach_device(dev, &dma_dom->domain); | |
15898bbc | 1514 | DUMP_printk("Using protection domain %d for device %s\n", |
94f6d190 | 1515 | dma_dom->domain.id, dev_name(dev)); |
f91ba190 | 1516 | |
94f6d190 | 1517 | return &dma_dom->domain; |
b20ac0d4 JR |
1518 | } |
1519 | ||
04bfdd84 JR |
1520 | static void update_device_table(struct protection_domain *domain) |
1521 | { | |
2b681faf | 1522 | unsigned long flags; |
04bfdd84 JR |
1523 | int i; |
1524 | ||
1525 | for (i = 0; i <= amd_iommu_last_bdf; ++i) { | |
1526 | if (amd_iommu_pd_table[i] != domain) | |
1527 | continue; | |
2b681faf | 1528 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); |
04bfdd84 | 1529 | set_dte_entry(i, domain); |
2b681faf | 1530 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); |
04bfdd84 JR |
1531 | } |
1532 | } | |
1533 | ||
1534 | static void update_domain(struct protection_domain *domain) | |
1535 | { | |
1536 | if (!domain->updated) | |
1537 | return; | |
1538 | ||
1539 | update_device_table(domain); | |
1540 | flush_devices_by_domain(domain); | |
601367d7 | 1541 | iommu_flush_tlb_pde(domain); |
04bfdd84 JR |
1542 | |
1543 | domain->updated = false; | |
1544 | } | |
1545 | ||
8bda3092 | 1546 | /* |
50020fb6 JR |
1547 | * This function is used to add another level to an IO page table. Adding |
1548 | * another level increases the size of the address space by 9 bits to a size up | |
1549 | * to 64 bits. | |
8bda3092 | 1550 | */ |
50020fb6 JR |
1551 | static bool increase_address_space(struct protection_domain *domain, |
1552 | gfp_t gfp) | |
1553 | { | |
1554 | u64 *pte; | |
1555 | ||
1556 | if (domain->mode == PAGE_MODE_6_LEVEL) | |
1557 | /* address space already 64 bit large */ | |
1558 | return false; | |
1559 | ||
1560 | pte = (void *)get_zeroed_page(gfp); | |
1561 | if (!pte) | |
1562 | return false; | |
1563 | ||
1564 | *pte = PM_LEVEL_PDE(domain->mode, | |
1565 | virt_to_phys(domain->pt_root)); | |
1566 | domain->pt_root = pte; | |
1567 | domain->mode += 1; | |
1568 | domain->updated = true; | |
1569 | ||
1570 | return true; | |
1571 | } | |
1572 | ||
8bc3e127 | 1573 | static u64 *alloc_pte(struct protection_domain *domain, |
abdc5eb3 JR |
1574 | unsigned long address, |
1575 | int end_lvl, | |
1576 | u64 **pte_page, | |
1577 | gfp_t gfp) | |
8bda3092 JR |
1578 | { |
1579 | u64 *pte, *page; | |
8bc3e127 | 1580 | int level; |
8bda3092 | 1581 | |
8bc3e127 JR |
1582 | while (address > PM_LEVEL_SIZE(domain->mode)) |
1583 | increase_address_space(domain, gfp); | |
8bda3092 | 1584 | |
8bc3e127 JR |
1585 | level = domain->mode - 1; |
1586 | pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)]; | |
8bda3092 | 1587 | |
abdc5eb3 | 1588 | while (level > end_lvl) { |
8bc3e127 JR |
1589 | if (!IOMMU_PTE_PRESENT(*pte)) { |
1590 | page = (u64 *)get_zeroed_page(gfp); | |
1591 | if (!page) | |
1592 | return NULL; | |
1593 | *pte = PM_LEVEL_PDE(level, virt_to_phys(page)); | |
1594 | } | |
8bda3092 | 1595 | |
8bc3e127 | 1596 | level -= 1; |
8bda3092 | 1597 | |
8bc3e127 | 1598 | pte = IOMMU_PTE_PAGE(*pte); |
8bda3092 | 1599 | |
abdc5eb3 | 1600 | if (pte_page && level == end_lvl) |
8bc3e127 | 1601 | *pte_page = pte; |
8bda3092 | 1602 | |
8bc3e127 JR |
1603 | pte = &pte[PM_LEVEL_INDEX(level, address)]; |
1604 | } | |
8bda3092 JR |
1605 | |
1606 | return pte; | |
1607 | } | |
1608 | ||
1609 | /* | |
1610 | * This function fetches the PTE for a given address in the aperture | |
1611 | */ | |
1612 | static u64* dma_ops_get_pte(struct dma_ops_domain *dom, | |
1613 | unsigned long address) | |
1614 | { | |
384de729 | 1615 | struct aperture_range *aperture; |
8bda3092 JR |
1616 | u64 *pte, *pte_page; |
1617 | ||
384de729 JR |
1618 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
1619 | if (!aperture) | |
1620 | return NULL; | |
1621 | ||
1622 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
8bda3092 | 1623 | if (!pte) { |
abdc5eb3 JR |
1624 | pte = alloc_pte(&dom->domain, address, PM_MAP_4k, &pte_page, |
1625 | GFP_ATOMIC); | |
384de729 JR |
1626 | aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page; |
1627 | } else | |
8c8c143c | 1628 | pte += PM_LEVEL_INDEX(0, address); |
8bda3092 | 1629 | |
04bfdd84 | 1630 | update_domain(&dom->domain); |
8bda3092 JR |
1631 | |
1632 | return pte; | |
1633 | } | |
1634 | ||
431b2a20 JR |
1635 | /* |
1636 | * This is the generic map function. It maps one 4kb page at paddr to | |
1637 | * the given address in the DMA address space for the domain. | |
1638 | */ | |
680525e0 | 1639 | static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom, |
cb76c322 JR |
1640 | unsigned long address, |
1641 | phys_addr_t paddr, | |
1642 | int direction) | |
1643 | { | |
1644 | u64 *pte, __pte; | |
1645 | ||
1646 | WARN_ON(address > dom->aperture_size); | |
1647 | ||
1648 | paddr &= PAGE_MASK; | |
1649 | ||
8bda3092 | 1650 | pte = dma_ops_get_pte(dom, address); |
53812c11 | 1651 | if (!pte) |
8fd524b3 | 1652 | return DMA_ERROR_CODE; |
cb76c322 JR |
1653 | |
1654 | __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
1655 | ||
1656 | if (direction == DMA_TO_DEVICE) | |
1657 | __pte |= IOMMU_PTE_IR; | |
1658 | else if (direction == DMA_FROM_DEVICE) | |
1659 | __pte |= IOMMU_PTE_IW; | |
1660 | else if (direction == DMA_BIDIRECTIONAL) | |
1661 | __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW; | |
1662 | ||
1663 | WARN_ON(*pte); | |
1664 | ||
1665 | *pte = __pte; | |
1666 | ||
1667 | return (dma_addr_t)address; | |
1668 | } | |
1669 | ||
431b2a20 JR |
1670 | /* |
1671 | * The generic unmapping function for on page in the DMA address space. | |
1672 | */ | |
680525e0 | 1673 | static void dma_ops_domain_unmap(struct dma_ops_domain *dom, |
cb76c322 JR |
1674 | unsigned long address) |
1675 | { | |
384de729 | 1676 | struct aperture_range *aperture; |
cb76c322 JR |
1677 | u64 *pte; |
1678 | ||
1679 | if (address >= dom->aperture_size) | |
1680 | return; | |
1681 | ||
384de729 JR |
1682 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
1683 | if (!aperture) | |
1684 | return; | |
1685 | ||
1686 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
1687 | if (!pte) | |
1688 | return; | |
cb76c322 | 1689 | |
8c8c143c | 1690 | pte += PM_LEVEL_INDEX(0, address); |
cb76c322 JR |
1691 | |
1692 | WARN_ON(!*pte); | |
1693 | ||
1694 | *pte = 0ULL; | |
1695 | } | |
1696 | ||
431b2a20 JR |
1697 | /* |
1698 | * This function contains common code for mapping of a physically | |
24f81160 JR |
1699 | * contiguous memory region into DMA address space. It is used by all |
1700 | * mapping functions provided with this IOMMU driver. | |
431b2a20 JR |
1701 | * Must be called with the domain lock held. |
1702 | */ | |
cb76c322 | 1703 | static dma_addr_t __map_single(struct device *dev, |
cb76c322 JR |
1704 | struct dma_ops_domain *dma_dom, |
1705 | phys_addr_t paddr, | |
1706 | size_t size, | |
6d4f343f | 1707 | int dir, |
832a90c3 JR |
1708 | bool align, |
1709 | u64 dma_mask) | |
cb76c322 JR |
1710 | { |
1711 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
53812c11 | 1712 | dma_addr_t address, start, ret; |
cb76c322 | 1713 | unsigned int pages; |
6d4f343f | 1714 | unsigned long align_mask = 0; |
cb76c322 JR |
1715 | int i; |
1716 | ||
e3c449f5 | 1717 | pages = iommu_num_pages(paddr, size, PAGE_SIZE); |
cb76c322 JR |
1718 | paddr &= PAGE_MASK; |
1719 | ||
8ecaf8f1 JR |
1720 | INC_STATS_COUNTER(total_map_requests); |
1721 | ||
c1858976 JR |
1722 | if (pages > 1) |
1723 | INC_STATS_COUNTER(cross_page); | |
1724 | ||
6d4f343f JR |
1725 | if (align) |
1726 | align_mask = (1UL << get_order(size)) - 1; | |
1727 | ||
11b83888 | 1728 | retry: |
832a90c3 JR |
1729 | address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask, |
1730 | dma_mask); | |
8fd524b3 | 1731 | if (unlikely(address == DMA_ERROR_CODE)) { |
11b83888 JR |
1732 | /* |
1733 | * setting next_address here will let the address | |
1734 | * allocator only scan the new allocated range in the | |
1735 | * first run. This is a small optimization. | |
1736 | */ | |
1737 | dma_dom->next_address = dma_dom->aperture_size; | |
1738 | ||
576175c2 | 1739 | if (alloc_new_range(dma_dom, false, GFP_ATOMIC)) |
11b83888 JR |
1740 | goto out; |
1741 | ||
1742 | /* | |
1743 | * aperture was sucessfully enlarged by 128 MB, try | |
1744 | * allocation again | |
1745 | */ | |
1746 | goto retry; | |
1747 | } | |
cb76c322 JR |
1748 | |
1749 | start = address; | |
1750 | for (i = 0; i < pages; ++i) { | |
680525e0 | 1751 | ret = dma_ops_domain_map(dma_dom, start, paddr, dir); |
8fd524b3 | 1752 | if (ret == DMA_ERROR_CODE) |
53812c11 JR |
1753 | goto out_unmap; |
1754 | ||
cb76c322 JR |
1755 | paddr += PAGE_SIZE; |
1756 | start += PAGE_SIZE; | |
1757 | } | |
1758 | address += offset; | |
1759 | ||
5774f7c5 JR |
1760 | ADD_STATS_COUNTER(alloced_io_mem, size); |
1761 | ||
afa9fdc2 | 1762 | if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) { |
dcd1e92e | 1763 | iommu_flush_tlb(&dma_dom->domain); |
1c655773 | 1764 | dma_dom->need_flush = false; |
318afd41 | 1765 | } else if (unlikely(amd_iommu_np_cache)) |
6de8ad9b | 1766 | iommu_flush_pages(&dma_dom->domain, address, size); |
270cab24 | 1767 | |
cb76c322 JR |
1768 | out: |
1769 | return address; | |
53812c11 JR |
1770 | |
1771 | out_unmap: | |
1772 | ||
1773 | for (--i; i >= 0; --i) { | |
1774 | start -= PAGE_SIZE; | |
680525e0 | 1775 | dma_ops_domain_unmap(dma_dom, start); |
53812c11 JR |
1776 | } |
1777 | ||
1778 | dma_ops_free_addresses(dma_dom, address, pages); | |
1779 | ||
8fd524b3 | 1780 | return DMA_ERROR_CODE; |
cb76c322 JR |
1781 | } |
1782 | ||
431b2a20 JR |
1783 | /* |
1784 | * Does the reverse of the __map_single function. Must be called with | |
1785 | * the domain lock held too | |
1786 | */ | |
cd8c82e8 | 1787 | static void __unmap_single(struct dma_ops_domain *dma_dom, |
cb76c322 JR |
1788 | dma_addr_t dma_addr, |
1789 | size_t size, | |
1790 | int dir) | |
1791 | { | |
1792 | dma_addr_t i, start; | |
1793 | unsigned int pages; | |
1794 | ||
8fd524b3 | 1795 | if ((dma_addr == DMA_ERROR_CODE) || |
b8d9905d | 1796 | (dma_addr + size > dma_dom->aperture_size)) |
cb76c322 JR |
1797 | return; |
1798 | ||
e3c449f5 | 1799 | pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
cb76c322 JR |
1800 | dma_addr &= PAGE_MASK; |
1801 | start = dma_addr; | |
1802 | ||
1803 | for (i = 0; i < pages; ++i) { | |
680525e0 | 1804 | dma_ops_domain_unmap(dma_dom, start); |
cb76c322 JR |
1805 | start += PAGE_SIZE; |
1806 | } | |
1807 | ||
5774f7c5 JR |
1808 | SUB_STATS_COUNTER(alloced_io_mem, size); |
1809 | ||
cb76c322 | 1810 | dma_ops_free_addresses(dma_dom, dma_addr, pages); |
270cab24 | 1811 | |
80be308d | 1812 | if (amd_iommu_unmap_flush || dma_dom->need_flush) { |
6de8ad9b | 1813 | iommu_flush_pages(&dma_dom->domain, dma_addr, size); |
80be308d JR |
1814 | dma_dom->need_flush = false; |
1815 | } | |
cb76c322 JR |
1816 | } |
1817 | ||
431b2a20 JR |
1818 | /* |
1819 | * The exported map_single function for dma_ops. | |
1820 | */ | |
51491367 FT |
1821 | static dma_addr_t map_page(struct device *dev, struct page *page, |
1822 | unsigned long offset, size_t size, | |
1823 | enum dma_data_direction dir, | |
1824 | struct dma_attrs *attrs) | |
4da70b9e JR |
1825 | { |
1826 | unsigned long flags; | |
4da70b9e | 1827 | struct protection_domain *domain; |
4da70b9e | 1828 | dma_addr_t addr; |
832a90c3 | 1829 | u64 dma_mask; |
51491367 | 1830 | phys_addr_t paddr = page_to_phys(page) + offset; |
4da70b9e | 1831 | |
0f2a86f2 JR |
1832 | INC_STATS_COUNTER(cnt_map_single); |
1833 | ||
94f6d190 JR |
1834 | domain = get_domain(dev); |
1835 | if (PTR_ERR(domain) == -EINVAL) | |
4da70b9e | 1836 | return (dma_addr_t)paddr; |
94f6d190 JR |
1837 | else if (IS_ERR(domain)) |
1838 | return DMA_ERROR_CODE; | |
4da70b9e | 1839 | |
f99c0f1c JR |
1840 | dma_mask = *dev->dma_mask; |
1841 | ||
4da70b9e | 1842 | spin_lock_irqsave(&domain->lock, flags); |
94f6d190 | 1843 | |
cd8c82e8 | 1844 | addr = __map_single(dev, domain->priv, paddr, size, dir, false, |
832a90c3 | 1845 | dma_mask); |
8fd524b3 | 1846 | if (addr == DMA_ERROR_CODE) |
4da70b9e JR |
1847 | goto out; |
1848 | ||
0518a3a4 | 1849 | iommu_flush_complete(domain); |
4da70b9e JR |
1850 | |
1851 | out: | |
1852 | spin_unlock_irqrestore(&domain->lock, flags); | |
1853 | ||
1854 | return addr; | |
1855 | } | |
1856 | ||
431b2a20 JR |
1857 | /* |
1858 | * The exported unmap_single function for dma_ops. | |
1859 | */ | |
51491367 FT |
1860 | static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, |
1861 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
4da70b9e JR |
1862 | { |
1863 | unsigned long flags; | |
4da70b9e | 1864 | struct protection_domain *domain; |
4da70b9e | 1865 | |
146a6917 JR |
1866 | INC_STATS_COUNTER(cnt_unmap_single); |
1867 | ||
94f6d190 JR |
1868 | domain = get_domain(dev); |
1869 | if (IS_ERR(domain)) | |
5b28df6f JR |
1870 | return; |
1871 | ||
4da70b9e JR |
1872 | spin_lock_irqsave(&domain->lock, flags); |
1873 | ||
cd8c82e8 | 1874 | __unmap_single(domain->priv, dma_addr, size, dir); |
4da70b9e | 1875 | |
0518a3a4 | 1876 | iommu_flush_complete(domain); |
4da70b9e JR |
1877 | |
1878 | spin_unlock_irqrestore(&domain->lock, flags); | |
1879 | } | |
1880 | ||
431b2a20 JR |
1881 | /* |
1882 | * This is a special map_sg function which is used if we should map a | |
1883 | * device which is not handled by an AMD IOMMU in the system. | |
1884 | */ | |
65b050ad JR |
1885 | static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist, |
1886 | int nelems, int dir) | |
1887 | { | |
1888 | struct scatterlist *s; | |
1889 | int i; | |
1890 | ||
1891 | for_each_sg(sglist, s, nelems, i) { | |
1892 | s->dma_address = (dma_addr_t)sg_phys(s); | |
1893 | s->dma_length = s->length; | |
1894 | } | |
1895 | ||
1896 | return nelems; | |
1897 | } | |
1898 | ||
431b2a20 JR |
1899 | /* |
1900 | * The exported map_sg function for dma_ops (handles scatter-gather | |
1901 | * lists). | |
1902 | */ | |
65b050ad | 1903 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
1904 | int nelems, enum dma_data_direction dir, |
1905 | struct dma_attrs *attrs) | |
65b050ad JR |
1906 | { |
1907 | unsigned long flags; | |
65b050ad | 1908 | struct protection_domain *domain; |
65b050ad JR |
1909 | int i; |
1910 | struct scatterlist *s; | |
1911 | phys_addr_t paddr; | |
1912 | int mapped_elems = 0; | |
832a90c3 | 1913 | u64 dma_mask; |
65b050ad | 1914 | |
d03f067a JR |
1915 | INC_STATS_COUNTER(cnt_map_sg); |
1916 | ||
94f6d190 JR |
1917 | domain = get_domain(dev); |
1918 | if (PTR_ERR(domain) == -EINVAL) | |
f99c0f1c | 1919 | return map_sg_no_iommu(dev, sglist, nelems, dir); |
94f6d190 JR |
1920 | else if (IS_ERR(domain)) |
1921 | return 0; | |
dbcc112e | 1922 | |
832a90c3 | 1923 | dma_mask = *dev->dma_mask; |
65b050ad | 1924 | |
65b050ad JR |
1925 | spin_lock_irqsave(&domain->lock, flags); |
1926 | ||
1927 | for_each_sg(sglist, s, nelems, i) { | |
1928 | paddr = sg_phys(s); | |
1929 | ||
cd8c82e8 | 1930 | s->dma_address = __map_single(dev, domain->priv, |
832a90c3 JR |
1931 | paddr, s->length, dir, false, |
1932 | dma_mask); | |
65b050ad JR |
1933 | |
1934 | if (s->dma_address) { | |
1935 | s->dma_length = s->length; | |
1936 | mapped_elems++; | |
1937 | } else | |
1938 | goto unmap; | |
65b050ad JR |
1939 | } |
1940 | ||
0518a3a4 | 1941 | iommu_flush_complete(domain); |
65b050ad JR |
1942 | |
1943 | out: | |
1944 | spin_unlock_irqrestore(&domain->lock, flags); | |
1945 | ||
1946 | return mapped_elems; | |
1947 | unmap: | |
1948 | for_each_sg(sglist, s, mapped_elems, i) { | |
1949 | if (s->dma_address) | |
cd8c82e8 | 1950 | __unmap_single(domain->priv, s->dma_address, |
65b050ad JR |
1951 | s->dma_length, dir); |
1952 | s->dma_address = s->dma_length = 0; | |
1953 | } | |
1954 | ||
1955 | mapped_elems = 0; | |
1956 | ||
1957 | goto out; | |
1958 | } | |
1959 | ||
431b2a20 JR |
1960 | /* |
1961 | * The exported map_sg function for dma_ops (handles scatter-gather | |
1962 | * lists). | |
1963 | */ | |
65b050ad | 1964 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
1965 | int nelems, enum dma_data_direction dir, |
1966 | struct dma_attrs *attrs) | |
65b050ad JR |
1967 | { |
1968 | unsigned long flags; | |
65b050ad JR |
1969 | struct protection_domain *domain; |
1970 | struct scatterlist *s; | |
65b050ad JR |
1971 | int i; |
1972 | ||
55877a6b JR |
1973 | INC_STATS_COUNTER(cnt_unmap_sg); |
1974 | ||
94f6d190 JR |
1975 | domain = get_domain(dev); |
1976 | if (IS_ERR(domain)) | |
5b28df6f JR |
1977 | return; |
1978 | ||
65b050ad JR |
1979 | spin_lock_irqsave(&domain->lock, flags); |
1980 | ||
1981 | for_each_sg(sglist, s, nelems, i) { | |
cd8c82e8 | 1982 | __unmap_single(domain->priv, s->dma_address, |
65b050ad | 1983 | s->dma_length, dir); |
65b050ad JR |
1984 | s->dma_address = s->dma_length = 0; |
1985 | } | |
1986 | ||
0518a3a4 | 1987 | iommu_flush_complete(domain); |
65b050ad JR |
1988 | |
1989 | spin_unlock_irqrestore(&domain->lock, flags); | |
1990 | } | |
1991 | ||
431b2a20 JR |
1992 | /* |
1993 | * The exported alloc_coherent function for dma_ops. | |
1994 | */ | |
5d8b53cf JR |
1995 | static void *alloc_coherent(struct device *dev, size_t size, |
1996 | dma_addr_t *dma_addr, gfp_t flag) | |
1997 | { | |
1998 | unsigned long flags; | |
1999 | void *virt_addr; | |
5d8b53cf | 2000 | struct protection_domain *domain; |
5d8b53cf | 2001 | phys_addr_t paddr; |
832a90c3 | 2002 | u64 dma_mask = dev->coherent_dma_mask; |
5d8b53cf | 2003 | |
c8f0fb36 JR |
2004 | INC_STATS_COUNTER(cnt_alloc_coherent); |
2005 | ||
94f6d190 JR |
2006 | domain = get_domain(dev); |
2007 | if (PTR_ERR(domain) == -EINVAL) { | |
f99c0f1c JR |
2008 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); |
2009 | *dma_addr = __pa(virt_addr); | |
2010 | return virt_addr; | |
94f6d190 JR |
2011 | } else if (IS_ERR(domain)) |
2012 | return NULL; | |
5d8b53cf | 2013 | |
f99c0f1c JR |
2014 | dma_mask = dev->coherent_dma_mask; |
2015 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
2016 | flag |= __GFP_ZERO; | |
5d8b53cf JR |
2017 | |
2018 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); | |
2019 | if (!virt_addr) | |
b25ae679 | 2020 | return NULL; |
5d8b53cf | 2021 | |
5d8b53cf JR |
2022 | paddr = virt_to_phys(virt_addr); |
2023 | ||
832a90c3 JR |
2024 | if (!dma_mask) |
2025 | dma_mask = *dev->dma_mask; | |
2026 | ||
5d8b53cf JR |
2027 | spin_lock_irqsave(&domain->lock, flags); |
2028 | ||
cd8c82e8 | 2029 | *dma_addr = __map_single(dev, domain->priv, paddr, |
832a90c3 | 2030 | size, DMA_BIDIRECTIONAL, true, dma_mask); |
5d8b53cf | 2031 | |
8fd524b3 | 2032 | if (*dma_addr == DMA_ERROR_CODE) { |
367d04c4 | 2033 | spin_unlock_irqrestore(&domain->lock, flags); |
5b28df6f | 2034 | goto out_free; |
367d04c4 | 2035 | } |
5d8b53cf | 2036 | |
0518a3a4 | 2037 | iommu_flush_complete(domain); |
5d8b53cf | 2038 | |
5d8b53cf JR |
2039 | spin_unlock_irqrestore(&domain->lock, flags); |
2040 | ||
2041 | return virt_addr; | |
5b28df6f JR |
2042 | |
2043 | out_free: | |
2044 | ||
2045 | free_pages((unsigned long)virt_addr, get_order(size)); | |
2046 | ||
2047 | return NULL; | |
5d8b53cf JR |
2048 | } |
2049 | ||
431b2a20 JR |
2050 | /* |
2051 | * The exported free_coherent function for dma_ops. | |
431b2a20 | 2052 | */ |
5d8b53cf JR |
2053 | static void free_coherent(struct device *dev, size_t size, |
2054 | void *virt_addr, dma_addr_t dma_addr) | |
2055 | { | |
2056 | unsigned long flags; | |
5d8b53cf | 2057 | struct protection_domain *domain; |
5d8b53cf | 2058 | |
5d31ee7e JR |
2059 | INC_STATS_COUNTER(cnt_free_coherent); |
2060 | ||
94f6d190 JR |
2061 | domain = get_domain(dev); |
2062 | if (IS_ERR(domain)) | |
5b28df6f JR |
2063 | goto free_mem; |
2064 | ||
5d8b53cf JR |
2065 | spin_lock_irqsave(&domain->lock, flags); |
2066 | ||
cd8c82e8 | 2067 | __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL); |
5d8b53cf | 2068 | |
0518a3a4 | 2069 | iommu_flush_complete(domain); |
5d8b53cf JR |
2070 | |
2071 | spin_unlock_irqrestore(&domain->lock, flags); | |
2072 | ||
2073 | free_mem: | |
2074 | free_pages((unsigned long)virt_addr, get_order(size)); | |
2075 | } | |
2076 | ||
b39ba6ad JR |
2077 | /* |
2078 | * This function is called by the DMA layer to find out if we can handle a | |
2079 | * particular device. It is part of the dma_ops. | |
2080 | */ | |
2081 | static int amd_iommu_dma_supported(struct device *dev, u64 mask) | |
2082 | { | |
420aef8a | 2083 | return check_device(dev); |
b39ba6ad JR |
2084 | } |
2085 | ||
c432f3df | 2086 | /* |
431b2a20 JR |
2087 | * The function for pre-allocating protection domains. |
2088 | * | |
c432f3df JR |
2089 | * If the driver core informs the DMA layer if a driver grabs a device |
2090 | * we don't need to preallocate the protection domains anymore. | |
2091 | * For now we have to. | |
2092 | */ | |
0e93dd88 | 2093 | static void prealloc_protection_domains(void) |
c432f3df JR |
2094 | { |
2095 | struct pci_dev *dev = NULL; | |
2096 | struct dma_ops_domain *dma_dom; | |
2097 | struct amd_iommu *iommu; | |
be831297 | 2098 | u16 devid, __devid; |
c432f3df JR |
2099 | |
2100 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { | |
be831297 | 2101 | __devid = devid = calc_devid(dev->bus->number, dev->devfn); |
3a61ec38 | 2102 | if (devid > amd_iommu_last_bdf) |
c432f3df JR |
2103 | continue; |
2104 | devid = amd_iommu_alias_table[devid]; | |
15898bbc | 2105 | if (domain_for_device(&dev->dev)) |
c432f3df JR |
2106 | continue; |
2107 | iommu = amd_iommu_rlookup_table[devid]; | |
2108 | if (!iommu) | |
2109 | continue; | |
d9cfed92 | 2110 | dma_dom = dma_ops_domain_alloc(iommu); |
c432f3df JR |
2111 | if (!dma_dom) |
2112 | continue; | |
2113 | init_unity_mappings_for_device(dma_dom, devid); | |
bd60b735 JR |
2114 | dma_dom->target_dev = devid; |
2115 | ||
15898bbc | 2116 | attach_device(&dev->dev, &dma_dom->domain); |
be831297 | 2117 | |
bd60b735 | 2118 | list_add_tail(&dma_dom->list, &iommu_pd_list); |
c432f3df JR |
2119 | } |
2120 | } | |
2121 | ||
160c1d8e | 2122 | static struct dma_map_ops amd_iommu_dma_ops = { |
6631ee9d JR |
2123 | .alloc_coherent = alloc_coherent, |
2124 | .free_coherent = free_coherent, | |
51491367 FT |
2125 | .map_page = map_page, |
2126 | .unmap_page = unmap_page, | |
6631ee9d JR |
2127 | .map_sg = map_sg, |
2128 | .unmap_sg = unmap_sg, | |
b39ba6ad | 2129 | .dma_supported = amd_iommu_dma_supported, |
6631ee9d JR |
2130 | }; |
2131 | ||
431b2a20 JR |
2132 | /* |
2133 | * The function which clues the AMD IOMMU driver into dma_ops. | |
2134 | */ | |
6631ee9d JR |
2135 | int __init amd_iommu_init_dma_ops(void) |
2136 | { | |
2137 | struct amd_iommu *iommu; | |
6631ee9d JR |
2138 | int ret; |
2139 | ||
431b2a20 JR |
2140 | /* |
2141 | * first allocate a default protection domain for every IOMMU we | |
2142 | * found in the system. Devices not assigned to any other | |
2143 | * protection domain will be assigned to the default one. | |
2144 | */ | |
3bd22172 | 2145 | for_each_iommu(iommu) { |
d9cfed92 | 2146 | iommu->default_dom = dma_ops_domain_alloc(iommu); |
6631ee9d JR |
2147 | if (iommu->default_dom == NULL) |
2148 | return -ENOMEM; | |
e2dc14a2 | 2149 | iommu->default_dom->domain.flags |= PD_DEFAULT_MASK; |
6631ee9d JR |
2150 | ret = iommu_init_unity_mappings(iommu); |
2151 | if (ret) | |
2152 | goto free_domains; | |
2153 | } | |
2154 | ||
431b2a20 JR |
2155 | /* |
2156 | * If device isolation is enabled, pre-allocate the protection | |
2157 | * domains for each device. | |
2158 | */ | |
6631ee9d JR |
2159 | if (amd_iommu_isolate) |
2160 | prealloc_protection_domains(); | |
2161 | ||
2162 | iommu_detected = 1; | |
75f1cdf1 | 2163 | swiotlb = 0; |
92af4e29 | 2164 | #ifdef CONFIG_GART_IOMMU |
6631ee9d JR |
2165 | gart_iommu_aperture_disabled = 1; |
2166 | gart_iommu_aperture = 0; | |
92af4e29 | 2167 | #endif |
6631ee9d | 2168 | |
431b2a20 | 2169 | /* Make the driver finally visible to the drivers */ |
6631ee9d JR |
2170 | dma_ops = &amd_iommu_dma_ops; |
2171 | ||
26961efe | 2172 | register_iommu(&amd_iommu_ops); |
26961efe | 2173 | |
e275a2a0 JR |
2174 | bus_register_notifier(&pci_bus_type, &device_nb); |
2175 | ||
7f26508b JR |
2176 | amd_iommu_stats_init(); |
2177 | ||
6631ee9d JR |
2178 | return 0; |
2179 | ||
2180 | free_domains: | |
2181 | ||
3bd22172 | 2182 | for_each_iommu(iommu) { |
6631ee9d JR |
2183 | if (iommu->default_dom) |
2184 | dma_ops_domain_free(iommu->default_dom); | |
2185 | } | |
2186 | ||
2187 | return ret; | |
2188 | } | |
6d98cd80 JR |
2189 | |
2190 | /***************************************************************************** | |
2191 | * | |
2192 | * The following functions belong to the exported interface of AMD IOMMU | |
2193 | * | |
2194 | * This interface allows access to lower level functions of the IOMMU | |
2195 | * like protection domain handling and assignement of devices to domains | |
2196 | * which is not possible with the dma_ops interface. | |
2197 | * | |
2198 | *****************************************************************************/ | |
2199 | ||
6d98cd80 JR |
2200 | static void cleanup_domain(struct protection_domain *domain) |
2201 | { | |
2202 | unsigned long flags; | |
2203 | u16 devid; | |
2204 | ||
2205 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
2206 | ||
2207 | for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) | |
2208 | if (amd_iommu_pd_table[devid] == domain) | |
15898bbc | 2209 | clear_dte_entry(devid); |
6d98cd80 JR |
2210 | |
2211 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
2212 | } | |
2213 | ||
2650815f JR |
2214 | static void protection_domain_free(struct protection_domain *domain) |
2215 | { | |
2216 | if (!domain) | |
2217 | return; | |
2218 | ||
aeb26f55 JR |
2219 | del_domain_from_list(domain); |
2220 | ||
2650815f JR |
2221 | if (domain->id) |
2222 | domain_id_free(domain->id); | |
2223 | ||
2224 | kfree(domain); | |
2225 | } | |
2226 | ||
2227 | static struct protection_domain *protection_domain_alloc(void) | |
c156e347 JR |
2228 | { |
2229 | struct protection_domain *domain; | |
2230 | ||
2231 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); | |
2232 | if (!domain) | |
2650815f | 2233 | return NULL; |
c156e347 JR |
2234 | |
2235 | spin_lock_init(&domain->lock); | |
c156e347 JR |
2236 | domain->id = domain_id_alloc(); |
2237 | if (!domain->id) | |
2650815f JR |
2238 | goto out_err; |
2239 | ||
aeb26f55 JR |
2240 | add_domain_to_list(domain); |
2241 | ||
2650815f JR |
2242 | return domain; |
2243 | ||
2244 | out_err: | |
2245 | kfree(domain); | |
2246 | ||
2247 | return NULL; | |
2248 | } | |
2249 | ||
2250 | static int amd_iommu_domain_init(struct iommu_domain *dom) | |
2251 | { | |
2252 | struct protection_domain *domain; | |
2253 | ||
2254 | domain = protection_domain_alloc(); | |
2255 | if (!domain) | |
c156e347 | 2256 | goto out_free; |
2650815f JR |
2257 | |
2258 | domain->mode = PAGE_MODE_3_LEVEL; | |
c156e347 JR |
2259 | domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL); |
2260 | if (!domain->pt_root) | |
2261 | goto out_free; | |
2262 | ||
2263 | dom->priv = domain; | |
2264 | ||
2265 | return 0; | |
2266 | ||
2267 | out_free: | |
2650815f | 2268 | protection_domain_free(domain); |
c156e347 JR |
2269 | |
2270 | return -ENOMEM; | |
2271 | } | |
2272 | ||
98383fc3 JR |
2273 | static void amd_iommu_domain_destroy(struct iommu_domain *dom) |
2274 | { | |
2275 | struct protection_domain *domain = dom->priv; | |
2276 | ||
2277 | if (!domain) | |
2278 | return; | |
2279 | ||
2280 | if (domain->dev_cnt > 0) | |
2281 | cleanup_domain(domain); | |
2282 | ||
2283 | BUG_ON(domain->dev_cnt != 0); | |
2284 | ||
2285 | free_pagetable(domain); | |
2286 | ||
2287 | domain_id_free(domain->id); | |
2288 | ||
2289 | kfree(domain); | |
2290 | ||
2291 | dom->priv = NULL; | |
2292 | } | |
2293 | ||
684f2888 JR |
2294 | static void amd_iommu_detach_device(struct iommu_domain *dom, |
2295 | struct device *dev) | |
2296 | { | |
684f2888 JR |
2297 | struct amd_iommu *iommu; |
2298 | struct pci_dev *pdev; | |
2299 | u16 devid; | |
2300 | ||
2301 | if (dev->bus != &pci_bus_type) | |
2302 | return; | |
2303 | ||
2304 | pdev = to_pci_dev(dev); | |
2305 | ||
2306 | devid = calc_devid(pdev->bus->number, pdev->devfn); | |
2307 | ||
2308 | if (devid > 0) | |
15898bbc | 2309 | detach_device(dev); |
684f2888 JR |
2310 | |
2311 | iommu = amd_iommu_rlookup_table[devid]; | |
2312 | if (!iommu) | |
2313 | return; | |
2314 | ||
2315 | iommu_queue_inv_dev_entry(iommu, devid); | |
2316 | iommu_completion_wait(iommu); | |
2317 | } | |
2318 | ||
01106066 JR |
2319 | static int amd_iommu_attach_device(struct iommu_domain *dom, |
2320 | struct device *dev) | |
2321 | { | |
2322 | struct protection_domain *domain = dom->priv; | |
2323 | struct protection_domain *old_domain; | |
2324 | struct amd_iommu *iommu; | |
2325 | struct pci_dev *pdev; | |
15898bbc | 2326 | int ret; |
01106066 JR |
2327 | u16 devid; |
2328 | ||
2329 | if (dev->bus != &pci_bus_type) | |
2330 | return -EINVAL; | |
2331 | ||
2332 | pdev = to_pci_dev(dev); | |
2333 | ||
2334 | devid = calc_devid(pdev->bus->number, pdev->devfn); | |
2335 | ||
2336 | if (devid >= amd_iommu_last_bdf || | |
2337 | devid != amd_iommu_alias_table[devid]) | |
2338 | return -EINVAL; | |
2339 | ||
2340 | iommu = amd_iommu_rlookup_table[devid]; | |
2341 | if (!iommu) | |
2342 | return -EINVAL; | |
2343 | ||
15898bbc | 2344 | old_domain = amd_iommu_pd_table[devid]; |
01106066 | 2345 | if (old_domain) |
15898bbc | 2346 | detach_device(dev); |
01106066 | 2347 | |
15898bbc | 2348 | ret = attach_device(dev, domain); |
01106066 JR |
2349 | |
2350 | iommu_completion_wait(iommu); | |
2351 | ||
15898bbc | 2352 | return ret; |
01106066 JR |
2353 | } |
2354 | ||
c6229ca6 JR |
2355 | static int amd_iommu_map_range(struct iommu_domain *dom, |
2356 | unsigned long iova, phys_addr_t paddr, | |
2357 | size_t size, int iommu_prot) | |
2358 | { | |
2359 | struct protection_domain *domain = dom->priv; | |
2360 | unsigned long i, npages = iommu_num_pages(paddr, size, PAGE_SIZE); | |
2361 | int prot = 0; | |
2362 | int ret; | |
2363 | ||
2364 | if (iommu_prot & IOMMU_READ) | |
2365 | prot |= IOMMU_PROT_IR; | |
2366 | if (iommu_prot & IOMMU_WRITE) | |
2367 | prot |= IOMMU_PROT_IW; | |
2368 | ||
2369 | iova &= PAGE_MASK; | |
2370 | paddr &= PAGE_MASK; | |
2371 | ||
2372 | for (i = 0; i < npages; ++i) { | |
abdc5eb3 | 2373 | ret = iommu_map_page(domain, iova, paddr, prot, PM_MAP_4k); |
c6229ca6 JR |
2374 | if (ret) |
2375 | return ret; | |
2376 | ||
2377 | iova += PAGE_SIZE; | |
2378 | paddr += PAGE_SIZE; | |
2379 | } | |
2380 | ||
2381 | return 0; | |
2382 | } | |
2383 | ||
eb74ff6c JR |
2384 | static void amd_iommu_unmap_range(struct iommu_domain *dom, |
2385 | unsigned long iova, size_t size) | |
2386 | { | |
2387 | ||
2388 | struct protection_domain *domain = dom->priv; | |
2389 | unsigned long i, npages = iommu_num_pages(iova, size, PAGE_SIZE); | |
2390 | ||
2391 | iova &= PAGE_MASK; | |
2392 | ||
2393 | for (i = 0; i < npages; ++i) { | |
a6b256b4 | 2394 | iommu_unmap_page(domain, iova, PM_MAP_4k); |
eb74ff6c JR |
2395 | iova += PAGE_SIZE; |
2396 | } | |
2397 | ||
601367d7 | 2398 | iommu_flush_tlb_pde(domain); |
eb74ff6c JR |
2399 | } |
2400 | ||
645c4c8d JR |
2401 | static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, |
2402 | unsigned long iova) | |
2403 | { | |
2404 | struct protection_domain *domain = dom->priv; | |
2405 | unsigned long offset = iova & ~PAGE_MASK; | |
2406 | phys_addr_t paddr; | |
2407 | u64 *pte; | |
2408 | ||
a6b256b4 | 2409 | pte = fetch_pte(domain, iova, PM_MAP_4k); |
645c4c8d | 2410 | |
a6d41a40 | 2411 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) |
645c4c8d JR |
2412 | return 0; |
2413 | ||
2414 | paddr = *pte & IOMMU_PAGE_MASK; | |
2415 | paddr |= offset; | |
2416 | ||
2417 | return paddr; | |
2418 | } | |
2419 | ||
dbb9fd86 SY |
2420 | static int amd_iommu_domain_has_cap(struct iommu_domain *domain, |
2421 | unsigned long cap) | |
2422 | { | |
2423 | return 0; | |
2424 | } | |
2425 | ||
26961efe JR |
2426 | static struct iommu_ops amd_iommu_ops = { |
2427 | .domain_init = amd_iommu_domain_init, | |
2428 | .domain_destroy = amd_iommu_domain_destroy, | |
2429 | .attach_dev = amd_iommu_attach_device, | |
2430 | .detach_dev = amd_iommu_detach_device, | |
2431 | .map = amd_iommu_map_range, | |
2432 | .unmap = amd_iommu_unmap_range, | |
2433 | .iova_to_phys = amd_iommu_iova_to_phys, | |
dbb9fd86 | 2434 | .domain_has_cap = amd_iommu_domain_has_cap, |
26961efe JR |
2435 | }; |
2436 | ||
0feae533 JR |
2437 | /***************************************************************************** |
2438 | * | |
2439 | * The next functions do a basic initialization of IOMMU for pass through | |
2440 | * mode | |
2441 | * | |
2442 | * In passthrough mode the IOMMU is initialized and enabled but not used for | |
2443 | * DMA-API translation. | |
2444 | * | |
2445 | *****************************************************************************/ | |
2446 | ||
2447 | int __init amd_iommu_init_passthrough(void) | |
2448 | { | |
15898bbc | 2449 | struct amd_iommu *iommu; |
0feae533 | 2450 | struct pci_dev *dev = NULL; |
15898bbc | 2451 | u16 devid; |
0feae533 JR |
2452 | |
2453 | /* allocate passthroug domain */ | |
2454 | pt_domain = protection_domain_alloc(); | |
2455 | if (!pt_domain) | |
2456 | return -ENOMEM; | |
2457 | ||
2458 | pt_domain->mode |= PAGE_MODE_NONE; | |
2459 | ||
2460 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { | |
0feae533 JR |
2461 | |
2462 | devid = calc_devid(dev->bus->number, dev->devfn); | |
2463 | if (devid > amd_iommu_last_bdf) | |
2464 | continue; | |
2465 | ||
15898bbc | 2466 | iommu = amd_iommu_rlookup_table[devid]; |
0feae533 JR |
2467 | if (!iommu) |
2468 | continue; | |
2469 | ||
15898bbc | 2470 | attach_device(&dev->dev, pt_domain); |
0feae533 JR |
2471 | } |
2472 | ||
2473 | pr_info("AMD-Vi: Initialized for Passthrough Mode\n"); | |
2474 | ||
2475 | return 0; | |
2476 | } |