Merge branch 'v4l_for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / kernel / irq / chip.c
CommitLineData
dd87eb3a
TG
1/*
2 * linux/kernel/irq/chip.c
3 *
4 * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar
5 * Copyright (C) 2005-2006, Thomas Gleixner, Russell King
6 *
7 * This file contains the core interrupt handling code, for irq-chip
8 * based architectures.
9 *
10 * Detailed information is available in Documentation/DocBook/genericirq
11 */
12
13#include <linux/irq.h>
7fe3730d 14#include <linux/msi.h>
dd87eb3a
TG
15#include <linux/module.h>
16#include <linux/interrupt.h>
17#include <linux/kernel_stat.h>
18
f069686e
SR
19#include <trace/events/irq.h>
20
dd87eb3a
TG
21#include "internals.h"
22
23/**
a0cd9ca2 24 * irq_set_chip - set the irq chip for an irq
dd87eb3a
TG
25 * @irq: irq number
26 * @chip: pointer to irq chip description structure
27 */
a0cd9ca2 28int irq_set_chip(unsigned int irq, struct irq_chip *chip)
dd87eb3a 29{
dd87eb3a 30 unsigned long flags;
31d9d9b6 31 struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0);
dd87eb3a 32
02725e74 33 if (!desc)
dd87eb3a 34 return -EINVAL;
dd87eb3a
TG
35
36 if (!chip)
37 chip = &no_irq_chip;
38
6b8ff312 39 desc->irq_data.chip = chip;
02725e74 40 irq_put_desc_unlock(desc, flags);
d72274e5
DD
41 /*
42 * For !CONFIG_SPARSE_IRQ make the irq show up in
43 * allocated_irqs. For the CONFIG_SPARSE_IRQ case, it is
44 * already marked, and this call is harmless.
45 */
46 irq_reserve_irq(irq);
dd87eb3a
TG
47 return 0;
48}
a0cd9ca2 49EXPORT_SYMBOL(irq_set_chip);
dd87eb3a
TG
50
51/**
a0cd9ca2 52 * irq_set_type - set the irq trigger type for an irq
dd87eb3a 53 * @irq: irq number
0c5d1eb7 54 * @type: IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h
dd87eb3a 55 */
a0cd9ca2 56int irq_set_irq_type(unsigned int irq, unsigned int type)
dd87eb3a 57{
dd87eb3a 58 unsigned long flags;
31d9d9b6 59 struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, IRQ_GET_DESC_CHECK_GLOBAL);
02725e74 60 int ret = 0;
dd87eb3a 61
02725e74
TG
62 if (!desc)
63 return -EINVAL;
dd87eb3a 64
f2b662da 65 type &= IRQ_TYPE_SENSE_MASK;
a09b659c 66 ret = __irq_set_trigger(desc, irq, type);
02725e74 67 irq_put_desc_busunlock(desc, flags);
dd87eb3a
TG
68 return ret;
69}
a0cd9ca2 70EXPORT_SYMBOL(irq_set_irq_type);
dd87eb3a
TG
71
72/**
a0cd9ca2 73 * irq_set_handler_data - set irq handler data for an irq
dd87eb3a
TG
74 * @irq: Interrupt number
75 * @data: Pointer to interrupt specific data
76 *
77 * Set the hardware irq controller data for an irq
78 */
a0cd9ca2 79int irq_set_handler_data(unsigned int irq, void *data)
dd87eb3a 80{
dd87eb3a 81 unsigned long flags;
31d9d9b6 82 struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0);
dd87eb3a 83
02725e74 84 if (!desc)
dd87eb3a 85 return -EINVAL;
6b8ff312 86 desc->irq_data.handler_data = data;
02725e74 87 irq_put_desc_unlock(desc, flags);
dd87eb3a
TG
88 return 0;
89}
a0cd9ca2 90EXPORT_SYMBOL(irq_set_handler_data);
dd87eb3a 91
5b912c10 92/**
51906e77
AG
93 * irq_set_msi_desc_off - set MSI descriptor data for an irq at offset
94 * @irq_base: Interrupt number base
95 * @irq_offset: Interrupt number offset
96 * @entry: Pointer to MSI descriptor data
5b912c10 97 *
51906e77 98 * Set the MSI descriptor entry for an irq at offset
5b912c10 99 */
51906e77
AG
100int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset,
101 struct msi_desc *entry)
5b912c10 102{
5b912c10 103 unsigned long flags;
51906e77 104 struct irq_desc *desc = irq_get_desc_lock(irq_base + irq_offset, &flags, IRQ_GET_DESC_CHECK_GLOBAL);
5b912c10 105
02725e74 106 if (!desc)
5b912c10 107 return -EINVAL;
6b8ff312 108 desc->irq_data.msi_desc = entry;
51906e77
AG
109 if (entry && !irq_offset)
110 entry->irq = irq_base;
02725e74 111 irq_put_desc_unlock(desc, flags);
5b912c10
EB
112 return 0;
113}
114
51906e77
AG
115/**
116 * irq_set_msi_desc - set MSI descriptor data for an irq
117 * @irq: Interrupt number
118 * @entry: Pointer to MSI descriptor data
119 *
120 * Set the MSI descriptor entry for an irq
121 */
122int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry)
123{
124 return irq_set_msi_desc_off(irq, 0, entry);
125}
126
dd87eb3a 127/**
a0cd9ca2 128 * irq_set_chip_data - set irq chip data for an irq
dd87eb3a
TG
129 * @irq: Interrupt number
130 * @data: Pointer to chip specific data
131 *
132 * Set the hardware irq chip data for an irq
133 */
a0cd9ca2 134int irq_set_chip_data(unsigned int irq, void *data)
dd87eb3a 135{
dd87eb3a 136 unsigned long flags;
31d9d9b6 137 struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0);
dd87eb3a 138
02725e74 139 if (!desc)
dd87eb3a 140 return -EINVAL;
6b8ff312 141 desc->irq_data.chip_data = data;
02725e74 142 irq_put_desc_unlock(desc, flags);
dd87eb3a
TG
143 return 0;
144}
a0cd9ca2 145EXPORT_SYMBOL(irq_set_chip_data);
dd87eb3a 146
f303a6dd
TG
147struct irq_data *irq_get_irq_data(unsigned int irq)
148{
149 struct irq_desc *desc = irq_to_desc(irq);
150
151 return desc ? &desc->irq_data : NULL;
152}
153EXPORT_SYMBOL_GPL(irq_get_irq_data);
154
c1594b77
TG
155static void irq_state_clr_disabled(struct irq_desc *desc)
156{
801a0e9a 157 irqd_clear(&desc->irq_data, IRQD_IRQ_DISABLED);
c1594b77
TG
158}
159
160static void irq_state_set_disabled(struct irq_desc *desc)
161{
801a0e9a 162 irqd_set(&desc->irq_data, IRQD_IRQ_DISABLED);
c1594b77
TG
163}
164
6e40262e
TG
165static void irq_state_clr_masked(struct irq_desc *desc)
166{
32f4125e 167 irqd_clear(&desc->irq_data, IRQD_IRQ_MASKED);
6e40262e
TG
168}
169
170static void irq_state_set_masked(struct irq_desc *desc)
171{
32f4125e 172 irqd_set(&desc->irq_data, IRQD_IRQ_MASKED);
6e40262e
TG
173}
174
b4bc724e 175int irq_startup(struct irq_desc *desc, bool resend)
46999238 176{
b4bc724e
TG
177 int ret = 0;
178
c1594b77 179 irq_state_clr_disabled(desc);
46999238
TG
180 desc->depth = 0;
181
3aae994f 182 if (desc->irq_data.chip->irq_startup) {
b4bc724e 183 ret = desc->irq_data.chip->irq_startup(&desc->irq_data);
6e40262e 184 irq_state_clr_masked(desc);
b4bc724e
TG
185 } else {
186 irq_enable(desc);
3aae994f 187 }
b4bc724e
TG
188 if (resend)
189 check_irq_resend(desc, desc->irq_data.irq);
190 return ret;
46999238
TG
191}
192
193void irq_shutdown(struct irq_desc *desc)
194{
c1594b77 195 irq_state_set_disabled(desc);
46999238 196 desc->depth = 1;
50f7c032
TG
197 if (desc->irq_data.chip->irq_shutdown)
198 desc->irq_data.chip->irq_shutdown(&desc->irq_data);
ed585a65 199 else if (desc->irq_data.chip->irq_disable)
50f7c032
TG
200 desc->irq_data.chip->irq_disable(&desc->irq_data);
201 else
202 desc->irq_data.chip->irq_mask(&desc->irq_data);
6e40262e 203 irq_state_set_masked(desc);
46999238
TG
204}
205
87923470
TG
206void irq_enable(struct irq_desc *desc)
207{
c1594b77 208 irq_state_clr_disabled(desc);
50f7c032
TG
209 if (desc->irq_data.chip->irq_enable)
210 desc->irq_data.chip->irq_enable(&desc->irq_data);
211 else
212 desc->irq_data.chip->irq_unmask(&desc->irq_data);
6e40262e 213 irq_state_clr_masked(desc);
dd87eb3a
TG
214}
215
50f7c032 216void irq_disable(struct irq_desc *desc)
89d694b9 217{
c1594b77 218 irq_state_set_disabled(desc);
50f7c032
TG
219 if (desc->irq_data.chip->irq_disable) {
220 desc->irq_data.chip->irq_disable(&desc->irq_data);
a61d8258 221 irq_state_set_masked(desc);
50f7c032 222 }
89d694b9
TG
223}
224
31d9d9b6
MZ
225void irq_percpu_enable(struct irq_desc *desc, unsigned int cpu)
226{
227 if (desc->irq_data.chip->irq_enable)
228 desc->irq_data.chip->irq_enable(&desc->irq_data);
229 else
230 desc->irq_data.chip->irq_unmask(&desc->irq_data);
231 cpumask_set_cpu(cpu, desc->percpu_enabled);
232}
233
234void irq_percpu_disable(struct irq_desc *desc, unsigned int cpu)
235{
236 if (desc->irq_data.chip->irq_disable)
237 desc->irq_data.chip->irq_disable(&desc->irq_data);
238 else
239 desc->irq_data.chip->irq_mask(&desc->irq_data);
240 cpumask_clear_cpu(cpu, desc->percpu_enabled);
241}
242
9205e31d 243static inline void mask_ack_irq(struct irq_desc *desc)
dd87eb3a 244{
9205e31d
TG
245 if (desc->irq_data.chip->irq_mask_ack)
246 desc->irq_data.chip->irq_mask_ack(&desc->irq_data);
dd87eb3a 247 else {
e2c0f8ff 248 desc->irq_data.chip->irq_mask(&desc->irq_data);
22a49163
TG
249 if (desc->irq_data.chip->irq_ack)
250 desc->irq_data.chip->irq_ack(&desc->irq_data);
dd87eb3a 251 }
6e40262e 252 irq_state_set_masked(desc);
0b1adaa0
TG
253}
254
d4d5e089 255void mask_irq(struct irq_desc *desc)
0b1adaa0 256{
e2c0f8ff
TG
257 if (desc->irq_data.chip->irq_mask) {
258 desc->irq_data.chip->irq_mask(&desc->irq_data);
6e40262e 259 irq_state_set_masked(desc);
0b1adaa0
TG
260 }
261}
262
d4d5e089 263void unmask_irq(struct irq_desc *desc)
0b1adaa0 264{
0eda58b7
TG
265 if (desc->irq_data.chip->irq_unmask) {
266 desc->irq_data.chip->irq_unmask(&desc->irq_data);
6e40262e 267 irq_state_clr_masked(desc);
0b1adaa0 268 }
dd87eb3a
TG
269}
270
399b5da2
TG
271/*
272 * handle_nested_irq - Handle a nested irq from a irq thread
273 * @irq: the interrupt number
274 *
275 * Handle interrupts which are nested into a threaded interrupt
276 * handler. The handler function is called inside the calling
277 * threads context.
278 */
279void handle_nested_irq(unsigned int irq)
280{
281 struct irq_desc *desc = irq_to_desc(irq);
282 struct irqaction *action;
283 irqreturn_t action_ret;
284
285 might_sleep();
286
239007b8 287 raw_spin_lock_irq(&desc->lock);
399b5da2 288
293a7a0a 289 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
399b5da2
TG
290 kstat_incr_irqs_this_cpu(irq, desc);
291
292 action = desc->action;
23812b9d
NJ
293 if (unlikely(!action || irqd_irq_disabled(&desc->irq_data))) {
294 desc->istate |= IRQS_PENDING;
399b5da2 295 goto out_unlock;
23812b9d 296 }
399b5da2 297
32f4125e 298 irqd_set(&desc->irq_data, IRQD_IRQ_INPROGRESS);
239007b8 299 raw_spin_unlock_irq(&desc->lock);
399b5da2
TG
300
301 action_ret = action->thread_fn(action->irq, action->dev_id);
302 if (!noirqdebug)
303 note_interrupt(irq, desc, action_ret);
304
239007b8 305 raw_spin_lock_irq(&desc->lock);
32f4125e 306 irqd_clear(&desc->irq_data, IRQD_IRQ_INPROGRESS);
399b5da2
TG
307
308out_unlock:
239007b8 309 raw_spin_unlock_irq(&desc->lock);
399b5da2
TG
310}
311EXPORT_SYMBOL_GPL(handle_nested_irq);
312
fe200ae4
TG
313static bool irq_check_poll(struct irq_desc *desc)
314{
6954b75b 315 if (!(desc->istate & IRQS_POLL_INPROGRESS))
fe200ae4
TG
316 return false;
317 return irq_wait_for_poll(desc);
318}
319
dd87eb3a
TG
320/**
321 * handle_simple_irq - Simple and software-decoded IRQs.
322 * @irq: the interrupt number
323 * @desc: the interrupt description structure for this irq
dd87eb3a
TG
324 *
325 * Simple interrupts are either sent from a demultiplexing interrupt
326 * handler or come from hardware, where no interrupt hardware control
327 * is necessary.
328 *
329 * Note: The caller is expected to handle the ack, clear, mask and
330 * unmask issues if necessary.
331 */
7ad5b3a5 332void
7d12e780 333handle_simple_irq(unsigned int irq, struct irq_desc *desc)
dd87eb3a 334{
239007b8 335 raw_spin_lock(&desc->lock);
dd87eb3a 336
32f4125e 337 if (unlikely(irqd_irq_inprogress(&desc->irq_data)))
fe200ae4
TG
338 if (!irq_check_poll(desc))
339 goto out_unlock;
340
163ef309 341 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
d6c88a50 342 kstat_incr_irqs_this_cpu(irq, desc);
dd87eb3a 343
23812b9d
NJ
344 if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) {
345 desc->istate |= IRQS_PENDING;
dd87eb3a 346 goto out_unlock;
23812b9d 347 }
dd87eb3a 348
107781e7 349 handle_irq_event(desc);
dd87eb3a 350
dd87eb3a 351out_unlock:
239007b8 352 raw_spin_unlock(&desc->lock);
dd87eb3a 353}
edf76f83 354EXPORT_SYMBOL_GPL(handle_simple_irq);
dd87eb3a 355
ac563761
TG
356/*
357 * Called unconditionally from handle_level_irq() and only for oneshot
358 * interrupts from handle_fasteoi_irq()
359 */
360static void cond_unmask_irq(struct irq_desc *desc)
361{
362 /*
363 * We need to unmask in the following cases:
364 * - Standard level irq (IRQF_ONESHOT is not set)
365 * - Oneshot irq which did not wake the thread (caused by a
366 * spurious interrupt or a primary handler handling it
367 * completely).
368 */
369 if (!irqd_irq_disabled(&desc->irq_data) &&
370 irqd_irq_masked(&desc->irq_data) && !desc->threads_oneshot)
371 unmask_irq(desc);
372}
373
dd87eb3a
TG
374/**
375 * handle_level_irq - Level type irq handler
376 * @irq: the interrupt number
377 * @desc: the interrupt description structure for this irq
dd87eb3a
TG
378 *
379 * Level type interrupts are active as long as the hardware line has
380 * the active level. This may require to mask the interrupt and unmask
381 * it after the associated handler has acknowledged the device, so the
382 * interrupt line is back to inactive.
383 */
7ad5b3a5 384void
7d12e780 385handle_level_irq(unsigned int irq, struct irq_desc *desc)
dd87eb3a 386{
239007b8 387 raw_spin_lock(&desc->lock);
9205e31d 388 mask_ack_irq(desc);
dd87eb3a 389
32f4125e 390 if (unlikely(irqd_irq_inprogress(&desc->irq_data)))
fe200ae4
TG
391 if (!irq_check_poll(desc))
392 goto out_unlock;
393
163ef309 394 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
d6c88a50 395 kstat_incr_irqs_this_cpu(irq, desc);
dd87eb3a
TG
396
397 /*
398 * If its disabled or no action available
399 * keep it masked and get out of here
400 */
d4dc0f90
TG
401 if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) {
402 desc->istate |= IRQS_PENDING;
86998aa6 403 goto out_unlock;
d4dc0f90 404 }
dd87eb3a 405
1529866c 406 handle_irq_event(desc);
b25c340c 407
ac563761
TG
408 cond_unmask_irq(desc);
409
86998aa6 410out_unlock:
239007b8 411 raw_spin_unlock(&desc->lock);
dd87eb3a 412}
14819ea1 413EXPORT_SYMBOL_GPL(handle_level_irq);
dd87eb3a 414
78129576
TG
415#ifdef CONFIG_IRQ_PREFLOW_FASTEOI
416static inline void preflow_handler(struct irq_desc *desc)
417{
418 if (desc->preflow_handler)
419 desc->preflow_handler(&desc->irq_data);
420}
421#else
422static inline void preflow_handler(struct irq_desc *desc) { }
423#endif
424
dd87eb3a 425/**
47c2a3aa 426 * handle_fasteoi_irq - irq handler for transparent controllers
dd87eb3a
TG
427 * @irq: the interrupt number
428 * @desc: the interrupt description structure for this irq
dd87eb3a 429 *
47c2a3aa 430 * Only a single callback will be issued to the chip: an ->eoi()
dd87eb3a
TG
431 * call when the interrupt has been serviced. This enables support
432 * for modern forms of interrupt handlers, which handle the flow
433 * details in hardware, transparently.
434 */
7ad5b3a5 435void
7d12e780 436handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc)
dd87eb3a 437{
239007b8 438 raw_spin_lock(&desc->lock);
dd87eb3a 439
32f4125e 440 if (unlikely(irqd_irq_inprogress(&desc->irq_data)))
fe200ae4
TG
441 if (!irq_check_poll(desc))
442 goto out;
dd87eb3a 443
163ef309 444 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
d6c88a50 445 kstat_incr_irqs_this_cpu(irq, desc);
dd87eb3a
TG
446
447 /*
448 * If its disabled or no action available
76d21601 449 * then mask it and get out of here:
dd87eb3a 450 */
32f4125e 451 if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) {
2a0d6fb3 452 desc->istate |= IRQS_PENDING;
e2c0f8ff 453 mask_irq(desc);
dd87eb3a 454 goto out;
98bb244b 455 }
c69e3758
TG
456
457 if (desc->istate & IRQS_ONESHOT)
458 mask_irq(desc);
459
78129576 460 preflow_handler(desc);
a7ae4de5 461 handle_irq_event(desc);
77694b40 462
ac563761
TG
463 if (desc->istate & IRQS_ONESHOT)
464 cond_unmask_irq(desc);
465
77694b40 466out_eoi:
0c5c1557 467 desc->irq_data.chip->irq_eoi(&desc->irq_data);
77694b40 468out_unlock:
239007b8 469 raw_spin_unlock(&desc->lock);
77694b40
TG
470 return;
471out:
472 if (!(desc->irq_data.chip->flags & IRQCHIP_EOI_IF_HANDLED))
473 goto out_eoi;
474 goto out_unlock;
dd87eb3a
TG
475}
476
477/**
478 * handle_edge_irq - edge type IRQ handler
479 * @irq: the interrupt number
480 * @desc: the interrupt description structure for this irq
dd87eb3a
TG
481 *
482 * Interrupt occures on the falling and/or rising edge of a hardware
25985edc 483 * signal. The occurrence is latched into the irq controller hardware
dd87eb3a
TG
484 * and must be acked in order to be reenabled. After the ack another
485 * interrupt can happen on the same source even before the first one
dfff0615 486 * is handled by the associated event handler. If this happens it
dd87eb3a
TG
487 * might be necessary to disable (mask) the interrupt depending on the
488 * controller hardware. This requires to reenable the interrupt inside
489 * of the loop which handles the interrupts which have arrived while
490 * the handler was running. If all pending interrupts are handled, the
491 * loop is left.
492 */
7ad5b3a5 493void
7d12e780 494handle_edge_irq(unsigned int irq, struct irq_desc *desc)
dd87eb3a 495{
239007b8 496 raw_spin_lock(&desc->lock);
dd87eb3a 497
163ef309 498 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
dd87eb3a
TG
499 /*
500 * If we're currently running this IRQ, or its disabled,
501 * we shouldn't process the IRQ. Mark it pending, handle
502 * the necessary masking and go out
503 */
32f4125e
TG
504 if (unlikely(irqd_irq_disabled(&desc->irq_data) ||
505 irqd_irq_inprogress(&desc->irq_data) || !desc->action)) {
fe200ae4 506 if (!irq_check_poll(desc)) {
2a0d6fb3 507 desc->istate |= IRQS_PENDING;
fe200ae4
TG
508 mask_ack_irq(desc);
509 goto out_unlock;
510 }
dd87eb3a 511 }
d6c88a50 512 kstat_incr_irqs_this_cpu(irq, desc);
dd87eb3a
TG
513
514 /* Start handling the irq */
22a49163 515 desc->irq_data.chip->irq_ack(&desc->irq_data);
dd87eb3a 516
dd87eb3a 517 do {
a60a5dc2 518 if (unlikely(!desc->action)) {
e2c0f8ff 519 mask_irq(desc);
dd87eb3a
TG
520 goto out_unlock;
521 }
522
523 /*
524 * When another irq arrived while we were handling
525 * one, we could have masked the irq.
526 * Renable it, if it was not disabled in meantime.
527 */
2a0d6fb3 528 if (unlikely(desc->istate & IRQS_PENDING)) {
32f4125e
TG
529 if (!irqd_irq_disabled(&desc->irq_data) &&
530 irqd_irq_masked(&desc->irq_data))
c1594b77 531 unmask_irq(desc);
dd87eb3a
TG
532 }
533
a60a5dc2 534 handle_irq_event(desc);
dd87eb3a 535
2a0d6fb3 536 } while ((desc->istate & IRQS_PENDING) &&
32f4125e 537 !irqd_irq_disabled(&desc->irq_data));
dd87eb3a 538
dd87eb3a 539out_unlock:
239007b8 540 raw_spin_unlock(&desc->lock);
dd87eb3a 541}
3911ff30 542EXPORT_SYMBOL(handle_edge_irq);
dd87eb3a 543
0521c8fb
TG
544#ifdef CONFIG_IRQ_EDGE_EOI_HANDLER
545/**
546 * handle_edge_eoi_irq - edge eoi type IRQ handler
547 * @irq: the interrupt number
548 * @desc: the interrupt description structure for this irq
549 *
550 * Similar as the above handle_edge_irq, but using eoi and w/o the
551 * mask/unmask logic.
552 */
553void handle_edge_eoi_irq(unsigned int irq, struct irq_desc *desc)
554{
555 struct irq_chip *chip = irq_desc_get_chip(desc);
556
557 raw_spin_lock(&desc->lock);
558
559 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
560 /*
561 * If we're currently running this IRQ, or its disabled,
562 * we shouldn't process the IRQ. Mark it pending, handle
563 * the necessary masking and go out
564 */
565 if (unlikely(irqd_irq_disabled(&desc->irq_data) ||
566 irqd_irq_inprogress(&desc->irq_data) || !desc->action)) {
567 if (!irq_check_poll(desc)) {
568 desc->istate |= IRQS_PENDING;
569 goto out_eoi;
570 }
571 }
572 kstat_incr_irqs_this_cpu(irq, desc);
573
574 do {
575 if (unlikely(!desc->action))
576 goto out_eoi;
577
578 handle_irq_event(desc);
579
580 } while ((desc->istate & IRQS_PENDING) &&
581 !irqd_irq_disabled(&desc->irq_data));
582
ac0e0447 583out_eoi:
0521c8fb
TG
584 chip->irq_eoi(&desc->irq_data);
585 raw_spin_unlock(&desc->lock);
586}
587#endif
588
dd87eb3a 589/**
24b26d42 590 * handle_percpu_irq - Per CPU local irq handler
dd87eb3a
TG
591 * @irq: the interrupt number
592 * @desc: the interrupt description structure for this irq
dd87eb3a
TG
593 *
594 * Per CPU interrupts on SMP machines without locking requirements
595 */
7ad5b3a5 596void
7d12e780 597handle_percpu_irq(unsigned int irq, struct irq_desc *desc)
dd87eb3a 598{
35e857cb 599 struct irq_chip *chip = irq_desc_get_chip(desc);
dd87eb3a 600
d6c88a50 601 kstat_incr_irqs_this_cpu(irq, desc);
dd87eb3a 602
849f061c
TG
603 if (chip->irq_ack)
604 chip->irq_ack(&desc->irq_data);
dd87eb3a 605
849f061c 606 handle_irq_event_percpu(desc, desc->action);
dd87eb3a 607
849f061c
TG
608 if (chip->irq_eoi)
609 chip->irq_eoi(&desc->irq_data);
dd87eb3a
TG
610}
611
31d9d9b6
MZ
612/**
613 * handle_percpu_devid_irq - Per CPU local irq handler with per cpu dev ids
614 * @irq: the interrupt number
615 * @desc: the interrupt description structure for this irq
616 *
617 * Per CPU interrupts on SMP machines without locking requirements. Same as
618 * handle_percpu_irq() above but with the following extras:
619 *
620 * action->percpu_dev_id is a pointer to percpu variables which
621 * contain the real device id for the cpu on which this handler is
622 * called
623 */
624void handle_percpu_devid_irq(unsigned int irq, struct irq_desc *desc)
625{
626 struct irq_chip *chip = irq_desc_get_chip(desc);
627 struct irqaction *action = desc->action;
628 void *dev_id = __this_cpu_ptr(action->percpu_dev_id);
629 irqreturn_t res;
630
631 kstat_incr_irqs_this_cpu(irq, desc);
632
633 if (chip->irq_ack)
634 chip->irq_ack(&desc->irq_data);
635
636 trace_irq_handler_entry(irq, action);
637 res = action->handler(irq, dev_id);
638 trace_irq_handler_exit(irq, action, res);
639
640 if (chip->irq_eoi)
641 chip->irq_eoi(&desc->irq_data);
642}
643
dd87eb3a 644void
3836ca08 645__irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained,
a460e745 646 const char *name)
dd87eb3a 647{
dd87eb3a 648 unsigned long flags;
31d9d9b6 649 struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, 0);
dd87eb3a 650
02725e74 651 if (!desc)
dd87eb3a 652 return;
dd87eb3a 653
091738a2 654 if (!handle) {
dd87eb3a 655 handle = handle_bad_irq;
091738a2
TG
656 } else {
657 if (WARN_ON(desc->irq_data.chip == &no_irq_chip))
02725e74 658 goto out;
f8b5473f 659 }
dd87eb3a 660
dd87eb3a
TG
661 /* Uninstall? */
662 if (handle == handle_bad_irq) {
6b8ff312 663 if (desc->irq_data.chip != &no_irq_chip)
9205e31d 664 mask_ack_irq(desc);
801a0e9a 665 irq_state_set_disabled(desc);
dd87eb3a
TG
666 desc->depth = 1;
667 }
668 desc->handle_irq = handle;
a460e745 669 desc->name = name;
dd87eb3a
TG
670
671 if (handle != handle_bad_irq && is_chained) {
1ccb4e61
TG
672 irq_settings_set_noprobe(desc);
673 irq_settings_set_norequest(desc);
7f1b1244 674 irq_settings_set_nothread(desc);
b4bc724e 675 irq_startup(desc, true);
dd87eb3a 676 }
02725e74
TG
677out:
678 irq_put_desc_busunlock(desc, flags);
dd87eb3a 679}
3836ca08 680EXPORT_SYMBOL_GPL(__irq_set_handler);
dd87eb3a
TG
681
682void
3836ca08 683irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip,
a460e745 684 irq_flow_handler_t handle, const char *name)
dd87eb3a 685{
35e857cb 686 irq_set_chip(irq, chip);
3836ca08 687 __irq_set_handler(irq, handle, 0, name);
dd87eb3a 688}
b3ae66f2 689EXPORT_SYMBOL_GPL(irq_set_chip_and_handler_name);
46f4f8f6 690
44247184 691void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set)
46f4f8f6 692{
46f4f8f6 693 unsigned long flags;
31d9d9b6 694 struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0);
46f4f8f6 695
44247184 696 if (!desc)
46f4f8f6 697 return;
a005677b
TG
698 irq_settings_clr_and_set(desc, clr, set);
699
876dbd4c 700 irqd_clear(&desc->irq_data, IRQD_NO_BALANCING | IRQD_PER_CPU |
e1ef8241 701 IRQD_TRIGGER_MASK | IRQD_LEVEL | IRQD_MOVE_PCNTXT);
a005677b
TG
702 if (irq_settings_has_no_balance_set(desc))
703 irqd_set(&desc->irq_data, IRQD_NO_BALANCING);
704 if (irq_settings_is_per_cpu(desc))
705 irqd_set(&desc->irq_data, IRQD_PER_CPU);
e1ef8241
TG
706 if (irq_settings_can_move_pcntxt(desc))
707 irqd_set(&desc->irq_data, IRQD_MOVE_PCNTXT);
0ef5ca1e
TG
708 if (irq_settings_is_level(desc))
709 irqd_set(&desc->irq_data, IRQD_LEVEL);
a005677b 710
876dbd4c
TG
711 irqd_set(&desc->irq_data, irq_settings_get_trigger_mask(desc));
712
02725e74 713 irq_put_desc_unlock(desc, flags);
46f4f8f6 714}
edf76f83 715EXPORT_SYMBOL_GPL(irq_modify_status);
0fdb4b25
DD
716
717/**
718 * irq_cpu_online - Invoke all irq_cpu_online functions.
719 *
720 * Iterate through all irqs and invoke the chip.irq_cpu_online()
721 * for each.
722 */
723void irq_cpu_online(void)
724{
725 struct irq_desc *desc;
726 struct irq_chip *chip;
727 unsigned long flags;
728 unsigned int irq;
729
730 for_each_active_irq(irq) {
731 desc = irq_to_desc(irq);
732 if (!desc)
733 continue;
734
735 raw_spin_lock_irqsave(&desc->lock, flags);
736
737 chip = irq_data_get_irq_chip(&desc->irq_data);
b3d42232
TG
738 if (chip && chip->irq_cpu_online &&
739 (!(chip->flags & IRQCHIP_ONOFFLINE_ENABLED) ||
32f4125e 740 !irqd_irq_disabled(&desc->irq_data)))
0fdb4b25
DD
741 chip->irq_cpu_online(&desc->irq_data);
742
743 raw_spin_unlock_irqrestore(&desc->lock, flags);
744 }
745}
746
747/**
748 * irq_cpu_offline - Invoke all irq_cpu_offline functions.
749 *
750 * Iterate through all irqs and invoke the chip.irq_cpu_offline()
751 * for each.
752 */
753void irq_cpu_offline(void)
754{
755 struct irq_desc *desc;
756 struct irq_chip *chip;
757 unsigned long flags;
758 unsigned int irq;
759
760 for_each_active_irq(irq) {
761 desc = irq_to_desc(irq);
762 if (!desc)
763 continue;
764
765 raw_spin_lock_irqsave(&desc->lock, flags);
766
767 chip = irq_data_get_irq_chip(&desc->irq_data);
b3d42232
TG
768 if (chip && chip->irq_cpu_offline &&
769 (!(chip->flags & IRQCHIP_ONOFFLINE_ENABLED) ||
32f4125e 770 !irqd_irq_disabled(&desc->irq_data)))
0fdb4b25
DD
771 chip->irq_cpu_offline(&desc->irq_data);
772
773 raw_spin_unlock_irqrestore(&desc->lock, flags);
774 }
775}