genirq: Move IRQ_REPLAY and IRQ_WAITING to core
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / kernel / irq / chip.c
CommitLineData
dd87eb3a
TG
1/*
2 * linux/kernel/irq/chip.c
3 *
4 * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar
5 * Copyright (C) 2005-2006, Thomas Gleixner, Russell King
6 *
7 * This file contains the core interrupt handling code, for irq-chip
8 * based architectures.
9 *
10 * Detailed information is available in Documentation/DocBook/genericirq
11 */
12
13#include <linux/irq.h>
7fe3730d 14#include <linux/msi.h>
dd87eb3a
TG
15#include <linux/module.h>
16#include <linux/interrupt.h>
17#include <linux/kernel_stat.h>
18
19#include "internals.h"
20
21/**
a0cd9ca2 22 * irq_set_chip - set the irq chip for an irq
dd87eb3a
TG
23 * @irq: irq number
24 * @chip: pointer to irq chip description structure
25 */
a0cd9ca2 26int irq_set_chip(unsigned int irq, struct irq_chip *chip)
dd87eb3a 27{
d3c60047 28 struct irq_desc *desc = irq_to_desc(irq);
dd87eb3a
TG
29 unsigned long flags;
30
7d94f7ca 31 if (!desc) {
261c40c1 32 WARN(1, KERN_ERR "Trying to install chip for IRQ%d\n", irq);
dd87eb3a
TG
33 return -EINVAL;
34 }
35
36 if (!chip)
37 chip = &no_irq_chip;
38
239007b8 39 raw_spin_lock_irqsave(&desc->lock, flags);
dd87eb3a 40 irq_chip_set_defaults(chip);
6b8ff312 41 desc->irq_data.chip = chip;
239007b8 42 raw_spin_unlock_irqrestore(&desc->lock, flags);
dd87eb3a
TG
43
44 return 0;
45}
a0cd9ca2 46EXPORT_SYMBOL(irq_set_chip);
dd87eb3a
TG
47
48/**
a0cd9ca2 49 * irq_set_type - set the irq trigger type for an irq
dd87eb3a 50 * @irq: irq number
0c5d1eb7 51 * @type: IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h
dd87eb3a 52 */
a0cd9ca2 53int irq_set_irq_type(unsigned int irq, unsigned int type)
dd87eb3a 54{
d3c60047 55 struct irq_desc *desc = irq_to_desc(irq);
dd87eb3a
TG
56 unsigned long flags;
57 int ret = -ENXIO;
58
7d94f7ca 59 if (!desc) {
dd87eb3a
TG
60 printk(KERN_ERR "Trying to set irq type for IRQ%d\n", irq);
61 return -ENODEV;
62 }
63
f2b662da 64 type &= IRQ_TYPE_SENSE_MASK;
0c5d1eb7
DB
65 if (type == IRQ_TYPE_NONE)
66 return 0;
67
43abe43c 68 chip_bus_lock(desc);
239007b8 69 raw_spin_lock_irqsave(&desc->lock, flags);
0b3682ba 70 ret = __irq_set_trigger(desc, irq, type);
239007b8 71 raw_spin_unlock_irqrestore(&desc->lock, flags);
43abe43c 72 chip_bus_sync_unlock(desc);
dd87eb3a
TG
73 return ret;
74}
a0cd9ca2 75EXPORT_SYMBOL(irq_set_irq_type);
dd87eb3a
TG
76
77/**
a0cd9ca2 78 * irq_set_handler_data - set irq handler data for an irq
dd87eb3a
TG
79 * @irq: Interrupt number
80 * @data: Pointer to interrupt specific data
81 *
82 * Set the hardware irq controller data for an irq
83 */
a0cd9ca2 84int irq_set_handler_data(unsigned int irq, void *data)
dd87eb3a 85{
d3c60047 86 struct irq_desc *desc = irq_to_desc(irq);
dd87eb3a
TG
87 unsigned long flags;
88
7d94f7ca 89 if (!desc) {
dd87eb3a
TG
90 printk(KERN_ERR
91 "Trying to install controller data for IRQ%d\n", irq);
92 return -EINVAL;
93 }
94
239007b8 95 raw_spin_lock_irqsave(&desc->lock, flags);
6b8ff312 96 desc->irq_data.handler_data = data;
239007b8 97 raw_spin_unlock_irqrestore(&desc->lock, flags);
dd87eb3a
TG
98 return 0;
99}
a0cd9ca2 100EXPORT_SYMBOL(irq_set_handler_data);
dd87eb3a 101
5b912c10 102/**
a0cd9ca2 103 * irq_set_msi_desc - set MSI descriptor data for an irq
5b912c10 104 * @irq: Interrupt number
472900b8 105 * @entry: Pointer to MSI descriptor data
5b912c10 106 *
24b26d42 107 * Set the MSI descriptor entry for an irq
5b912c10 108 */
a0cd9ca2 109int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry)
5b912c10 110{
d3c60047 111 struct irq_desc *desc = irq_to_desc(irq);
5b912c10
EB
112 unsigned long flags;
113
7d94f7ca 114 if (!desc) {
5b912c10
EB
115 printk(KERN_ERR
116 "Trying to install msi data for IRQ%d\n", irq);
117 return -EINVAL;
118 }
7d94f7ca 119
239007b8 120 raw_spin_lock_irqsave(&desc->lock, flags);
6b8ff312 121 desc->irq_data.msi_desc = entry;
7fe3730d
ME
122 if (entry)
123 entry->irq = irq;
239007b8 124 raw_spin_unlock_irqrestore(&desc->lock, flags);
5b912c10
EB
125 return 0;
126}
127
dd87eb3a 128/**
a0cd9ca2 129 * irq_set_chip_data - set irq chip data for an irq
dd87eb3a
TG
130 * @irq: Interrupt number
131 * @data: Pointer to chip specific data
132 *
133 * Set the hardware irq chip data for an irq
134 */
a0cd9ca2 135int irq_set_chip_data(unsigned int irq, void *data)
dd87eb3a 136{
d3c60047 137 struct irq_desc *desc = irq_to_desc(irq);
dd87eb3a
TG
138 unsigned long flags;
139
7d94f7ca
YL
140 if (!desc) {
141 printk(KERN_ERR
142 "Trying to install chip data for IRQ%d\n", irq);
143 return -EINVAL;
144 }
145
6b8ff312 146 if (!desc->irq_data.chip) {
dd87eb3a
TG
147 printk(KERN_ERR "BUG: bad set_irq_chip_data(IRQ#%d)\n", irq);
148 return -EINVAL;
149 }
150
239007b8 151 raw_spin_lock_irqsave(&desc->lock, flags);
6b8ff312 152 desc->irq_data.chip_data = data;
239007b8 153 raw_spin_unlock_irqrestore(&desc->lock, flags);
dd87eb3a
TG
154
155 return 0;
156}
a0cd9ca2 157EXPORT_SYMBOL(irq_set_chip_data);
dd87eb3a 158
f303a6dd
TG
159struct irq_data *irq_get_irq_data(unsigned int irq)
160{
161 struct irq_desc *desc = irq_to_desc(irq);
162
163 return desc ? &desc->irq_data : NULL;
164}
165EXPORT_SYMBOL_GPL(irq_get_irq_data);
166
46999238
TG
167int irq_startup(struct irq_desc *desc)
168{
3aae994f 169 desc->status &= ~IRQ_DISABLED;
46999238
TG
170 desc->depth = 0;
171
3aae994f
TG
172 if (desc->irq_data.chip->irq_startup) {
173 int ret = desc->irq_data.chip->irq_startup(&desc->irq_data);
174 desc->status &= ~IRQ_MASKED;
175 return ret;
176 }
46999238 177
87923470 178 irq_enable(desc);
46999238
TG
179 return 0;
180}
181
182void irq_shutdown(struct irq_desc *desc)
183{
3aae994f 184 desc->status |= IRQ_DISABLED;
46999238 185 desc->depth = 1;
50f7c032
TG
186 if (desc->irq_data.chip->irq_shutdown)
187 desc->irq_data.chip->irq_shutdown(&desc->irq_data);
188 if (desc->irq_data.chip->irq_disable)
189 desc->irq_data.chip->irq_disable(&desc->irq_data);
190 else
191 desc->irq_data.chip->irq_mask(&desc->irq_data);
3aae994f 192 desc->status |= IRQ_MASKED;
46999238
TG
193}
194
87923470
TG
195void irq_enable(struct irq_desc *desc)
196{
3aae994f 197 desc->status &= ~IRQ_DISABLED;
50f7c032
TG
198 if (desc->irq_data.chip->irq_enable)
199 desc->irq_data.chip->irq_enable(&desc->irq_data);
200 else
201 desc->irq_data.chip->irq_unmask(&desc->irq_data);
dd87eb3a
TG
202 desc->status &= ~IRQ_MASKED;
203}
204
50f7c032 205void irq_disable(struct irq_desc *desc)
89d694b9 206{
3aae994f 207 desc->status |= IRQ_DISABLED;
50f7c032
TG
208 if (desc->irq_data.chip->irq_disable) {
209 desc->irq_data.chip->irq_disable(&desc->irq_data);
210 desc->status |= IRQ_MASKED;
211 }
89d694b9
TG
212}
213
bd151412 214#ifndef CONFIG_GENERIC_HARDIRQS_NO_DEPRECATED
3876ec9e 215/* Temporary migration helpers */
e2c0f8ff
TG
216static void compat_irq_mask(struct irq_data *data)
217{
218 data->chip->mask(data->irq);
219}
220
0eda58b7
TG
221static void compat_irq_unmask(struct irq_data *data)
222{
223 data->chip->unmask(data->irq);
224}
225
22a49163
TG
226static void compat_irq_ack(struct irq_data *data)
227{
228 data->chip->ack(data->irq);
229}
230
9205e31d
TG
231static void compat_irq_mask_ack(struct irq_data *data)
232{
233 data->chip->mask_ack(data->irq);
234}
235
0c5c1557
TG
236static void compat_irq_eoi(struct irq_data *data)
237{
238 data->chip->eoi(data->irq);
239}
240
c5f75634
TG
241static void compat_irq_enable(struct irq_data *data)
242{
243 data->chip->enable(data->irq);
244}
245
bc310dda
TG
246static void compat_irq_disable(struct irq_data *data)
247{
248 data->chip->disable(data->irq);
249}
250
251static void compat_irq_shutdown(struct irq_data *data)
252{
253 data->chip->shutdown(data->irq);
254}
255
37e12df7
TG
256static unsigned int compat_irq_startup(struct irq_data *data)
257{
258 return data->chip->startup(data->irq);
259}
260
c96b3b3c
TG
261static int compat_irq_set_affinity(struct irq_data *data,
262 const struct cpumask *dest, bool force)
263{
264 return data->chip->set_affinity(data->irq, dest);
265}
266
b2ba2c30
TG
267static int compat_irq_set_type(struct irq_data *data, unsigned int type)
268{
269 return data->chip->set_type(data->irq, type);
270}
271
2f7e99bb
TG
272static int compat_irq_set_wake(struct irq_data *data, unsigned int on)
273{
274 return data->chip->set_wake(data->irq, on);
275}
276
21e2b8c6
TG
277static int compat_irq_retrigger(struct irq_data *data)
278{
279 return data->chip->retrigger(data->irq);
280}
281
3876ec9e
TG
282static void compat_bus_lock(struct irq_data *data)
283{
284 data->chip->bus_lock(data->irq);
285}
286
287static void compat_bus_sync_unlock(struct irq_data *data)
288{
289 data->chip->bus_sync_unlock(data->irq);
290}
bd151412 291#endif
3876ec9e 292
dd87eb3a
TG
293/*
294 * Fixup enable/disable function pointers
295 */
296void irq_chip_set_defaults(struct irq_chip *chip)
297{
bd151412 298#ifndef CONFIG_GENERIC_HARDIRQS_NO_DEPRECATED
c5f75634
TG
299 if (chip->enable)
300 chip->irq_enable = compat_irq_enable;
bc310dda
TG
301 if (chip->disable)
302 chip->irq_disable = compat_irq_disable;
303 if (chip->shutdown)
304 chip->irq_shutdown = compat_irq_shutdown;
37e12df7
TG
305 if (chip->startup)
306 chip->irq_startup = compat_irq_startup;
b86432b4
ZY
307 if (!chip->end)
308 chip->end = dummy_irq_chip.end;
3876ec9e
TG
309 if (chip->bus_lock)
310 chip->irq_bus_lock = compat_bus_lock;
311 if (chip->bus_sync_unlock)
312 chip->irq_bus_sync_unlock = compat_bus_sync_unlock;
e2c0f8ff
TG
313 if (chip->mask)
314 chip->irq_mask = compat_irq_mask;
0eda58b7
TG
315 if (chip->unmask)
316 chip->irq_unmask = compat_irq_unmask;
22a49163
TG
317 if (chip->ack)
318 chip->irq_ack = compat_irq_ack;
9205e31d
TG
319 if (chip->mask_ack)
320 chip->irq_mask_ack = compat_irq_mask_ack;
0c5c1557
TG
321 if (chip->eoi)
322 chip->irq_eoi = compat_irq_eoi;
c96b3b3c
TG
323 if (chip->set_affinity)
324 chip->irq_set_affinity = compat_irq_set_affinity;
b2ba2c30
TG
325 if (chip->set_type)
326 chip->irq_set_type = compat_irq_set_type;
2f7e99bb
TG
327 if (chip->set_wake)
328 chip->irq_set_wake = compat_irq_set_wake;
21e2b8c6
TG
329 if (chip->retrigger)
330 chip->irq_retrigger = compat_irq_retrigger;
bd151412 331#endif
dd87eb3a
TG
332}
333
9205e31d 334static inline void mask_ack_irq(struct irq_desc *desc)
dd87eb3a 335{
9205e31d
TG
336 if (desc->irq_data.chip->irq_mask_ack)
337 desc->irq_data.chip->irq_mask_ack(&desc->irq_data);
dd87eb3a 338 else {
e2c0f8ff 339 desc->irq_data.chip->irq_mask(&desc->irq_data);
22a49163
TG
340 if (desc->irq_data.chip->irq_ack)
341 desc->irq_data.chip->irq_ack(&desc->irq_data);
dd87eb3a 342 }
0b1adaa0
TG
343 desc->status |= IRQ_MASKED;
344}
345
e2c0f8ff 346static inline void mask_irq(struct irq_desc *desc)
0b1adaa0 347{
e2c0f8ff
TG
348 if (desc->irq_data.chip->irq_mask) {
349 desc->irq_data.chip->irq_mask(&desc->irq_data);
0b1adaa0
TG
350 desc->status |= IRQ_MASKED;
351 }
352}
353
0eda58b7 354static inline void unmask_irq(struct irq_desc *desc)
0b1adaa0 355{
0eda58b7
TG
356 if (desc->irq_data.chip->irq_unmask) {
357 desc->irq_data.chip->irq_unmask(&desc->irq_data);
0b1adaa0
TG
358 desc->status &= ~IRQ_MASKED;
359 }
dd87eb3a
TG
360}
361
399b5da2
TG
362/*
363 * handle_nested_irq - Handle a nested irq from a irq thread
364 * @irq: the interrupt number
365 *
366 * Handle interrupts which are nested into a threaded interrupt
367 * handler. The handler function is called inside the calling
368 * threads context.
369 */
370void handle_nested_irq(unsigned int irq)
371{
372 struct irq_desc *desc = irq_to_desc(irq);
373 struct irqaction *action;
374 irqreturn_t action_ret;
375
376 might_sleep();
377
239007b8 378 raw_spin_lock_irq(&desc->lock);
399b5da2
TG
379
380 kstat_incr_irqs_this_cpu(irq, desc);
381
382 action = desc->action;
383 if (unlikely(!action || (desc->status & IRQ_DISABLED)))
384 goto out_unlock;
385
009b4c3b
TG
386 irq_compat_set_progress(desc);
387 desc->istate |= IRQS_INPROGRESS;
239007b8 388 raw_spin_unlock_irq(&desc->lock);
399b5da2
TG
389
390 action_ret = action->thread_fn(action->irq, action->dev_id);
391 if (!noirqdebug)
392 note_interrupt(irq, desc, action_ret);
393
239007b8 394 raw_spin_lock_irq(&desc->lock);
009b4c3b
TG
395 desc->istate &= ~IRQS_INPROGRESS;
396 irq_compat_clr_progress(desc);
399b5da2
TG
397
398out_unlock:
239007b8 399 raw_spin_unlock_irq(&desc->lock);
399b5da2
TG
400}
401EXPORT_SYMBOL_GPL(handle_nested_irq);
402
fe200ae4
TG
403static bool irq_check_poll(struct irq_desc *desc)
404{
6954b75b 405 if (!(desc->istate & IRQS_POLL_INPROGRESS))
fe200ae4
TG
406 return false;
407 return irq_wait_for_poll(desc);
408}
409
dd87eb3a
TG
410/**
411 * handle_simple_irq - Simple and software-decoded IRQs.
412 * @irq: the interrupt number
413 * @desc: the interrupt description structure for this irq
dd87eb3a
TG
414 *
415 * Simple interrupts are either sent from a demultiplexing interrupt
416 * handler or come from hardware, where no interrupt hardware control
417 * is necessary.
418 *
419 * Note: The caller is expected to handle the ack, clear, mask and
420 * unmask issues if necessary.
421 */
7ad5b3a5 422void
7d12e780 423handle_simple_irq(unsigned int irq, struct irq_desc *desc)
dd87eb3a 424{
239007b8 425 raw_spin_lock(&desc->lock);
dd87eb3a 426
009b4c3b 427 if (unlikely(desc->istate & IRQS_INPROGRESS))
fe200ae4
TG
428 if (!irq_check_poll(desc))
429 goto out_unlock;
430
163ef309 431 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
d6c88a50 432 kstat_incr_irqs_this_cpu(irq, desc);
dd87eb3a 433
107781e7 434 if (unlikely(!desc->action || (desc->status & IRQ_DISABLED)))
dd87eb3a
TG
435 goto out_unlock;
436
107781e7 437 handle_irq_event(desc);
dd87eb3a 438
dd87eb3a 439out_unlock:
239007b8 440 raw_spin_unlock(&desc->lock);
dd87eb3a
TG
441}
442
443/**
444 * handle_level_irq - Level type irq handler
445 * @irq: the interrupt number
446 * @desc: the interrupt description structure for this irq
dd87eb3a
TG
447 *
448 * Level type interrupts are active as long as the hardware line has
449 * the active level. This may require to mask the interrupt and unmask
450 * it after the associated handler has acknowledged the device, so the
451 * interrupt line is back to inactive.
452 */
7ad5b3a5 453void
7d12e780 454handle_level_irq(unsigned int irq, struct irq_desc *desc)
dd87eb3a 455{
239007b8 456 raw_spin_lock(&desc->lock);
9205e31d 457 mask_ack_irq(desc);
dd87eb3a 458
009b4c3b 459 if (unlikely(desc->istate & IRQS_INPROGRESS))
fe200ae4
TG
460 if (!irq_check_poll(desc))
461 goto out_unlock;
462
163ef309 463 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
d6c88a50 464 kstat_incr_irqs_this_cpu(irq, desc);
dd87eb3a
TG
465
466 /*
467 * If its disabled or no action available
468 * keep it masked and get out of here
469 */
1529866c 470 if (unlikely(!desc->action || (desc->status & IRQ_DISABLED)))
86998aa6 471 goto out_unlock;
dd87eb3a 472
1529866c 473 handle_irq_event(desc);
b25c340c 474
3d67baec 475 if (!(desc->status & IRQ_DISABLED) && !(desc->istate & IRQS_ONESHOT))
0eda58b7 476 unmask_irq(desc);
86998aa6 477out_unlock:
239007b8 478 raw_spin_unlock(&desc->lock);
dd87eb3a 479}
14819ea1 480EXPORT_SYMBOL_GPL(handle_level_irq);
dd87eb3a
TG
481
482/**
47c2a3aa 483 * handle_fasteoi_irq - irq handler for transparent controllers
dd87eb3a
TG
484 * @irq: the interrupt number
485 * @desc: the interrupt description structure for this irq
dd87eb3a 486 *
47c2a3aa 487 * Only a single callback will be issued to the chip: an ->eoi()
dd87eb3a
TG
488 * call when the interrupt has been serviced. This enables support
489 * for modern forms of interrupt handlers, which handle the flow
490 * details in hardware, transparently.
491 */
7ad5b3a5 492void
7d12e780 493handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc)
dd87eb3a 494{
239007b8 495 raw_spin_lock(&desc->lock);
dd87eb3a 496
009b4c3b 497 if (unlikely(desc->istate & IRQS_INPROGRESS))
fe200ae4
TG
498 if (!irq_check_poll(desc))
499 goto out;
dd87eb3a 500
163ef309 501 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
d6c88a50 502 kstat_incr_irqs_this_cpu(irq, desc);
dd87eb3a
TG
503
504 /*
505 * If its disabled or no action available
76d21601 506 * then mask it and get out of here:
dd87eb3a 507 */
a7ae4de5 508 if (unlikely(!desc->action || (desc->status & IRQ_DISABLED))) {
98bb244b 509 desc->status |= IRQ_PENDING;
e2c0f8ff 510 mask_irq(desc);
dd87eb3a 511 goto out;
98bb244b 512 }
a7ae4de5 513 handle_irq_event(desc);
dd87eb3a 514out:
0c5c1557 515 desc->irq_data.chip->irq_eoi(&desc->irq_data);
239007b8 516 raw_spin_unlock(&desc->lock);
dd87eb3a
TG
517}
518
519/**
520 * handle_edge_irq - edge type IRQ handler
521 * @irq: the interrupt number
522 * @desc: the interrupt description structure for this irq
dd87eb3a
TG
523 *
524 * Interrupt occures on the falling and/or rising edge of a hardware
525 * signal. The occurence is latched into the irq controller hardware
526 * and must be acked in order to be reenabled. After the ack another
527 * interrupt can happen on the same source even before the first one
dfff0615 528 * is handled by the associated event handler. If this happens it
dd87eb3a
TG
529 * might be necessary to disable (mask) the interrupt depending on the
530 * controller hardware. This requires to reenable the interrupt inside
531 * of the loop which handles the interrupts which have arrived while
532 * the handler was running. If all pending interrupts are handled, the
533 * loop is left.
534 */
7ad5b3a5 535void
7d12e780 536handle_edge_irq(unsigned int irq, struct irq_desc *desc)
dd87eb3a 537{
239007b8 538 raw_spin_lock(&desc->lock);
dd87eb3a 539
163ef309 540 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
dd87eb3a
TG
541 /*
542 * If we're currently running this IRQ, or its disabled,
543 * we shouldn't process the IRQ. Mark it pending, handle
544 * the necessary masking and go out
545 */
009b4c3b
TG
546 if (unlikely((desc->istate & (IRQS_INPROGRESS) ||
547 (desc->status & IRQ_DISABLED) || !desc->action))) {
fe200ae4 548 if (!irq_check_poll(desc)) {
d78f8dd3 549 desc->status |= IRQ_PENDING;
fe200ae4
TG
550 mask_ack_irq(desc);
551 goto out_unlock;
552 }
dd87eb3a 553 }
d6c88a50 554 kstat_incr_irqs_this_cpu(irq, desc);
dd87eb3a
TG
555
556 /* Start handling the irq */
22a49163 557 desc->irq_data.chip->irq_ack(&desc->irq_data);
dd87eb3a 558
dd87eb3a 559 do {
a60a5dc2 560 if (unlikely(!desc->action)) {
e2c0f8ff 561 mask_irq(desc);
dd87eb3a
TG
562 goto out_unlock;
563 }
564
565 /*
566 * When another irq arrived while we were handling
567 * one, we could have masked the irq.
568 * Renable it, if it was not disabled in meantime.
569 */
570 if (unlikely((desc->status &
571 (IRQ_PENDING | IRQ_MASKED | IRQ_DISABLED)) ==
572 (IRQ_PENDING | IRQ_MASKED))) {
0eda58b7 573 unmask_irq(desc);
dd87eb3a
TG
574 }
575
a60a5dc2 576 handle_irq_event(desc);
dd87eb3a
TG
577
578 } while ((desc->status & (IRQ_PENDING | IRQ_DISABLED)) == IRQ_PENDING);
579
dd87eb3a 580out_unlock:
239007b8 581 raw_spin_unlock(&desc->lock);
dd87eb3a
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582}
583
dd87eb3a 584/**
24b26d42 585 * handle_percpu_irq - Per CPU local irq handler
dd87eb3a
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586 * @irq: the interrupt number
587 * @desc: the interrupt description structure for this irq
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588 *
589 * Per CPU interrupts on SMP machines without locking requirements
590 */
7ad5b3a5 591void
7d12e780 592handle_percpu_irq(unsigned int irq, struct irq_desc *desc)
dd87eb3a 593{
35e857cb 594 struct irq_chip *chip = irq_desc_get_chip(desc);
dd87eb3a 595
d6c88a50 596 kstat_incr_irqs_this_cpu(irq, desc);
dd87eb3a 597
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598 if (chip->irq_ack)
599 chip->irq_ack(&desc->irq_data);
dd87eb3a 600
849f061c 601 handle_irq_event_percpu(desc, desc->action);
dd87eb3a 602
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603 if (chip->irq_eoi)
604 chip->irq_eoi(&desc->irq_data);
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605}
606
dd87eb3a 607void
a460e745
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608__set_irq_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained,
609 const char *name)
dd87eb3a 610{
d3c60047 611 struct irq_desc *desc = irq_to_desc(irq);
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612 unsigned long flags;
613
7d94f7ca 614 if (!desc) {
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615 printk(KERN_ERR
616 "Trying to install type control for IRQ%d\n", irq);
617 return;
618 }
619
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620 if (!handle)
621 handle = handle_bad_irq;
6b8ff312 622 else if (desc->irq_data.chip == &no_irq_chip) {
f8b5473f 623 printk(KERN_WARNING "Trying to install %sinterrupt handler "
b039db8e 624 "for IRQ%d\n", is_chained ? "chained " : "", irq);
f8b5473f
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625 /*
626 * Some ARM implementations install a handler for really dumb
627 * interrupt hardware without setting an irq_chip. This worked
628 * with the ARM no_irq_chip but the check in setup_irq would
629 * prevent us to setup the interrupt at all. Switch it to
630 * dummy_irq_chip for easy transition.
631 */
6b8ff312 632 desc->irq_data.chip = &dummy_irq_chip;
f8b5473f 633 }
dd87eb3a 634
3876ec9e 635 chip_bus_lock(desc);
239007b8 636 raw_spin_lock_irqsave(&desc->lock, flags);
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637
638 /* Uninstall? */
639 if (handle == handle_bad_irq) {
6b8ff312 640 if (desc->irq_data.chip != &no_irq_chip)
9205e31d 641 mask_ack_irq(desc);
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642 desc->status |= IRQ_DISABLED;
643 desc->depth = 1;
644 }
645 desc->handle_irq = handle;
a460e745 646 desc->name = name;
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647
648 if (handle != handle_bad_irq && is_chained) {
dd87eb3a 649 desc->status |= IRQ_NOREQUEST | IRQ_NOPROBE;
46999238 650 irq_startup(desc);
dd87eb3a 651 }
239007b8 652 raw_spin_unlock_irqrestore(&desc->lock, flags);
3876ec9e 653 chip_bus_sync_unlock(desc);
dd87eb3a 654}
14819ea1 655EXPORT_SYMBOL_GPL(__set_irq_handler);
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656
657void
658set_irq_chip_and_handler(unsigned int irq, struct irq_chip *chip,
57a58a94 659 irq_flow_handler_t handle)
dd87eb3a 660{
35e857cb 661 irq_set_chip(irq, chip);
a460e745 662 __set_irq_handler(irq, handle, 0, NULL);
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663}
664
a460e745
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665void
666set_irq_chip_and_handler_name(unsigned int irq, struct irq_chip *chip,
667 irq_flow_handler_t handle, const char *name)
dd87eb3a 668{
35e857cb 669 irq_set_chip(irq, chip);
a460e745 670 __set_irq_handler(irq, handle, 0, name);
dd87eb3a 671}
46f4f8f6 672
44247184 673void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set)
46f4f8f6 674{
d3c60047 675 struct irq_desc *desc = irq_to_desc(irq);
46f4f8f6
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676 unsigned long flags;
677
44247184 678 if (!desc)
46f4f8f6 679 return;
46f4f8f6 680
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681 /* Sanitize flags */
682 set &= IRQF_MODIFY_MASK;
683 clr &= IRQF_MODIFY_MASK;
46f4f8f6 684
239007b8 685 raw_spin_lock_irqsave(&desc->lock, flags);
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686 desc->status &= ~clr;
687 desc->status |= set;
239007b8 688 raw_spin_unlock_irqrestore(&desc->lock, flags);
46f4f8f6 689}