genirq: Use handle_irq_event() in handle_level_irq()
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / kernel / irq / chip.c
CommitLineData
dd87eb3a
TG
1/*
2 * linux/kernel/irq/chip.c
3 *
4 * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar
5 * Copyright (C) 2005-2006, Thomas Gleixner, Russell King
6 *
7 * This file contains the core interrupt handling code, for irq-chip
8 * based architectures.
9 *
10 * Detailed information is available in Documentation/DocBook/genericirq
11 */
12
13#include <linux/irq.h>
7fe3730d 14#include <linux/msi.h>
dd87eb3a
TG
15#include <linux/module.h>
16#include <linux/interrupt.h>
17#include <linux/kernel_stat.h>
18
19#include "internals.h"
20
21/**
a0cd9ca2 22 * irq_set_chip - set the irq chip for an irq
dd87eb3a
TG
23 * @irq: irq number
24 * @chip: pointer to irq chip description structure
25 */
a0cd9ca2 26int irq_set_chip(unsigned int irq, struct irq_chip *chip)
dd87eb3a 27{
d3c60047 28 struct irq_desc *desc = irq_to_desc(irq);
dd87eb3a
TG
29 unsigned long flags;
30
7d94f7ca 31 if (!desc) {
261c40c1 32 WARN(1, KERN_ERR "Trying to install chip for IRQ%d\n", irq);
dd87eb3a
TG
33 return -EINVAL;
34 }
35
36 if (!chip)
37 chip = &no_irq_chip;
38
239007b8 39 raw_spin_lock_irqsave(&desc->lock, flags);
dd87eb3a 40 irq_chip_set_defaults(chip);
6b8ff312 41 desc->irq_data.chip = chip;
239007b8 42 raw_spin_unlock_irqrestore(&desc->lock, flags);
dd87eb3a
TG
43
44 return 0;
45}
a0cd9ca2 46EXPORT_SYMBOL(irq_set_chip);
dd87eb3a
TG
47
48/**
a0cd9ca2 49 * irq_set_type - set the irq trigger type for an irq
dd87eb3a 50 * @irq: irq number
0c5d1eb7 51 * @type: IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h
dd87eb3a 52 */
a0cd9ca2 53int irq_set_irq_type(unsigned int irq, unsigned int type)
dd87eb3a 54{
d3c60047 55 struct irq_desc *desc = irq_to_desc(irq);
dd87eb3a
TG
56 unsigned long flags;
57 int ret = -ENXIO;
58
7d94f7ca 59 if (!desc) {
dd87eb3a
TG
60 printk(KERN_ERR "Trying to set irq type for IRQ%d\n", irq);
61 return -ENODEV;
62 }
63
f2b662da 64 type &= IRQ_TYPE_SENSE_MASK;
0c5d1eb7
DB
65 if (type == IRQ_TYPE_NONE)
66 return 0;
67
43abe43c 68 chip_bus_lock(desc);
239007b8 69 raw_spin_lock_irqsave(&desc->lock, flags);
0b3682ba 70 ret = __irq_set_trigger(desc, irq, type);
239007b8 71 raw_spin_unlock_irqrestore(&desc->lock, flags);
43abe43c 72 chip_bus_sync_unlock(desc);
dd87eb3a
TG
73 return ret;
74}
a0cd9ca2 75EXPORT_SYMBOL(irq_set_irq_type);
dd87eb3a
TG
76
77/**
a0cd9ca2 78 * irq_set_handler_data - set irq handler data for an irq
dd87eb3a
TG
79 * @irq: Interrupt number
80 * @data: Pointer to interrupt specific data
81 *
82 * Set the hardware irq controller data for an irq
83 */
a0cd9ca2 84int irq_set_handler_data(unsigned int irq, void *data)
dd87eb3a 85{
d3c60047 86 struct irq_desc *desc = irq_to_desc(irq);
dd87eb3a
TG
87 unsigned long flags;
88
7d94f7ca 89 if (!desc) {
dd87eb3a
TG
90 printk(KERN_ERR
91 "Trying to install controller data for IRQ%d\n", irq);
92 return -EINVAL;
93 }
94
239007b8 95 raw_spin_lock_irqsave(&desc->lock, flags);
6b8ff312 96 desc->irq_data.handler_data = data;
239007b8 97 raw_spin_unlock_irqrestore(&desc->lock, flags);
dd87eb3a
TG
98 return 0;
99}
a0cd9ca2 100EXPORT_SYMBOL(irq_set_handler_data);
dd87eb3a 101
5b912c10 102/**
a0cd9ca2 103 * irq_set_msi_desc - set MSI descriptor data for an irq
5b912c10 104 * @irq: Interrupt number
472900b8 105 * @entry: Pointer to MSI descriptor data
5b912c10 106 *
24b26d42 107 * Set the MSI descriptor entry for an irq
5b912c10 108 */
a0cd9ca2 109int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry)
5b912c10 110{
d3c60047 111 struct irq_desc *desc = irq_to_desc(irq);
5b912c10
EB
112 unsigned long flags;
113
7d94f7ca 114 if (!desc) {
5b912c10
EB
115 printk(KERN_ERR
116 "Trying to install msi data for IRQ%d\n", irq);
117 return -EINVAL;
118 }
7d94f7ca 119
239007b8 120 raw_spin_lock_irqsave(&desc->lock, flags);
6b8ff312 121 desc->irq_data.msi_desc = entry;
7fe3730d
ME
122 if (entry)
123 entry->irq = irq;
239007b8 124 raw_spin_unlock_irqrestore(&desc->lock, flags);
5b912c10
EB
125 return 0;
126}
127
dd87eb3a 128/**
a0cd9ca2 129 * irq_set_chip_data - set irq chip data for an irq
dd87eb3a
TG
130 * @irq: Interrupt number
131 * @data: Pointer to chip specific data
132 *
133 * Set the hardware irq chip data for an irq
134 */
a0cd9ca2 135int irq_set_chip_data(unsigned int irq, void *data)
dd87eb3a 136{
d3c60047 137 struct irq_desc *desc = irq_to_desc(irq);
dd87eb3a
TG
138 unsigned long flags;
139
7d94f7ca
YL
140 if (!desc) {
141 printk(KERN_ERR
142 "Trying to install chip data for IRQ%d\n", irq);
143 return -EINVAL;
144 }
145
6b8ff312 146 if (!desc->irq_data.chip) {
dd87eb3a
TG
147 printk(KERN_ERR "BUG: bad set_irq_chip_data(IRQ#%d)\n", irq);
148 return -EINVAL;
149 }
150
239007b8 151 raw_spin_lock_irqsave(&desc->lock, flags);
6b8ff312 152 desc->irq_data.chip_data = data;
239007b8 153 raw_spin_unlock_irqrestore(&desc->lock, flags);
dd87eb3a
TG
154
155 return 0;
156}
a0cd9ca2 157EXPORT_SYMBOL(irq_set_chip_data);
dd87eb3a 158
f303a6dd
TG
159struct irq_data *irq_get_irq_data(unsigned int irq)
160{
161 struct irq_desc *desc = irq_to_desc(irq);
162
163 return desc ? &desc->irq_data : NULL;
164}
165EXPORT_SYMBOL_GPL(irq_get_irq_data);
166
399b5da2
TG
167/**
168 * set_irq_nested_thread - Set/Reset the IRQ_NESTED_THREAD flag of an irq
169 *
170 * @irq: Interrupt number
171 * @nest: 0 to clear / 1 to set the IRQ_NESTED_THREAD flag
172 *
173 * The IRQ_NESTED_THREAD flag indicates that on
174 * request_threaded_irq() no separate interrupt thread should be
175 * created for the irq as the handler are called nested in the
176 * context of a demultiplexing interrupt handler thread.
177 */
178void set_irq_nested_thread(unsigned int irq, int nest)
179{
180 struct irq_desc *desc = irq_to_desc(irq);
181 unsigned long flags;
182
183 if (!desc)
184 return;
185
239007b8 186 raw_spin_lock_irqsave(&desc->lock, flags);
399b5da2
TG
187 if (nest)
188 desc->status |= IRQ_NESTED_THREAD;
189 else
190 desc->status &= ~IRQ_NESTED_THREAD;
239007b8 191 raw_spin_unlock_irqrestore(&desc->lock, flags);
399b5da2
TG
192}
193EXPORT_SYMBOL_GPL(set_irq_nested_thread);
194
46999238
TG
195int irq_startup(struct irq_desc *desc)
196{
3aae994f 197 desc->status &= ~IRQ_DISABLED;
46999238
TG
198 desc->depth = 0;
199
3aae994f
TG
200 if (desc->irq_data.chip->irq_startup) {
201 int ret = desc->irq_data.chip->irq_startup(&desc->irq_data);
202 desc->status &= ~IRQ_MASKED;
203 return ret;
204 }
46999238 205
87923470 206 irq_enable(desc);
46999238
TG
207 return 0;
208}
209
210void irq_shutdown(struct irq_desc *desc)
211{
3aae994f 212 desc->status |= IRQ_DISABLED;
46999238 213 desc->depth = 1;
50f7c032
TG
214 if (desc->irq_data.chip->irq_shutdown)
215 desc->irq_data.chip->irq_shutdown(&desc->irq_data);
216 if (desc->irq_data.chip->irq_disable)
217 desc->irq_data.chip->irq_disable(&desc->irq_data);
218 else
219 desc->irq_data.chip->irq_mask(&desc->irq_data);
3aae994f 220 desc->status |= IRQ_MASKED;
46999238
TG
221}
222
87923470
TG
223void irq_enable(struct irq_desc *desc)
224{
3aae994f 225 desc->status &= ~IRQ_DISABLED;
50f7c032
TG
226 if (desc->irq_data.chip->irq_enable)
227 desc->irq_data.chip->irq_enable(&desc->irq_data);
228 else
229 desc->irq_data.chip->irq_unmask(&desc->irq_data);
dd87eb3a
TG
230 desc->status &= ~IRQ_MASKED;
231}
232
50f7c032 233void irq_disable(struct irq_desc *desc)
89d694b9 234{
3aae994f 235 desc->status |= IRQ_DISABLED;
50f7c032
TG
236 if (desc->irq_data.chip->irq_disable) {
237 desc->irq_data.chip->irq_disable(&desc->irq_data);
238 desc->status |= IRQ_MASKED;
239 }
89d694b9
TG
240}
241
bd151412 242#ifndef CONFIG_GENERIC_HARDIRQS_NO_DEPRECATED
3876ec9e 243/* Temporary migration helpers */
e2c0f8ff
TG
244static void compat_irq_mask(struct irq_data *data)
245{
246 data->chip->mask(data->irq);
247}
248
0eda58b7
TG
249static void compat_irq_unmask(struct irq_data *data)
250{
251 data->chip->unmask(data->irq);
252}
253
22a49163
TG
254static void compat_irq_ack(struct irq_data *data)
255{
256 data->chip->ack(data->irq);
257}
258
9205e31d
TG
259static void compat_irq_mask_ack(struct irq_data *data)
260{
261 data->chip->mask_ack(data->irq);
262}
263
0c5c1557
TG
264static void compat_irq_eoi(struct irq_data *data)
265{
266 data->chip->eoi(data->irq);
267}
268
c5f75634
TG
269static void compat_irq_enable(struct irq_data *data)
270{
271 data->chip->enable(data->irq);
272}
273
bc310dda
TG
274static void compat_irq_disable(struct irq_data *data)
275{
276 data->chip->disable(data->irq);
277}
278
279static void compat_irq_shutdown(struct irq_data *data)
280{
281 data->chip->shutdown(data->irq);
282}
283
37e12df7
TG
284static unsigned int compat_irq_startup(struct irq_data *data)
285{
286 return data->chip->startup(data->irq);
287}
288
c96b3b3c
TG
289static int compat_irq_set_affinity(struct irq_data *data,
290 const struct cpumask *dest, bool force)
291{
292 return data->chip->set_affinity(data->irq, dest);
293}
294
b2ba2c30
TG
295static int compat_irq_set_type(struct irq_data *data, unsigned int type)
296{
297 return data->chip->set_type(data->irq, type);
298}
299
2f7e99bb
TG
300static int compat_irq_set_wake(struct irq_data *data, unsigned int on)
301{
302 return data->chip->set_wake(data->irq, on);
303}
304
21e2b8c6
TG
305static int compat_irq_retrigger(struct irq_data *data)
306{
307 return data->chip->retrigger(data->irq);
308}
309
3876ec9e
TG
310static void compat_bus_lock(struct irq_data *data)
311{
312 data->chip->bus_lock(data->irq);
313}
314
315static void compat_bus_sync_unlock(struct irq_data *data)
316{
317 data->chip->bus_sync_unlock(data->irq);
318}
bd151412 319#endif
3876ec9e 320
dd87eb3a
TG
321/*
322 * Fixup enable/disable function pointers
323 */
324void irq_chip_set_defaults(struct irq_chip *chip)
325{
bd151412 326#ifndef CONFIG_GENERIC_HARDIRQS_NO_DEPRECATED
c5f75634
TG
327 if (chip->enable)
328 chip->irq_enable = compat_irq_enable;
bc310dda
TG
329 if (chip->disable)
330 chip->irq_disable = compat_irq_disable;
331 if (chip->shutdown)
332 chip->irq_shutdown = compat_irq_shutdown;
37e12df7
TG
333 if (chip->startup)
334 chip->irq_startup = compat_irq_startup;
b86432b4
ZY
335 if (!chip->end)
336 chip->end = dummy_irq_chip.end;
3876ec9e
TG
337 if (chip->bus_lock)
338 chip->irq_bus_lock = compat_bus_lock;
339 if (chip->bus_sync_unlock)
340 chip->irq_bus_sync_unlock = compat_bus_sync_unlock;
e2c0f8ff
TG
341 if (chip->mask)
342 chip->irq_mask = compat_irq_mask;
0eda58b7
TG
343 if (chip->unmask)
344 chip->irq_unmask = compat_irq_unmask;
22a49163
TG
345 if (chip->ack)
346 chip->irq_ack = compat_irq_ack;
9205e31d
TG
347 if (chip->mask_ack)
348 chip->irq_mask_ack = compat_irq_mask_ack;
0c5c1557
TG
349 if (chip->eoi)
350 chip->irq_eoi = compat_irq_eoi;
c96b3b3c
TG
351 if (chip->set_affinity)
352 chip->irq_set_affinity = compat_irq_set_affinity;
b2ba2c30
TG
353 if (chip->set_type)
354 chip->irq_set_type = compat_irq_set_type;
2f7e99bb
TG
355 if (chip->set_wake)
356 chip->irq_set_wake = compat_irq_set_wake;
21e2b8c6
TG
357 if (chip->retrigger)
358 chip->irq_retrigger = compat_irq_retrigger;
bd151412 359#endif
dd87eb3a
TG
360}
361
9205e31d 362static inline void mask_ack_irq(struct irq_desc *desc)
dd87eb3a 363{
9205e31d
TG
364 if (desc->irq_data.chip->irq_mask_ack)
365 desc->irq_data.chip->irq_mask_ack(&desc->irq_data);
dd87eb3a 366 else {
e2c0f8ff 367 desc->irq_data.chip->irq_mask(&desc->irq_data);
22a49163
TG
368 if (desc->irq_data.chip->irq_ack)
369 desc->irq_data.chip->irq_ack(&desc->irq_data);
dd87eb3a 370 }
0b1adaa0
TG
371 desc->status |= IRQ_MASKED;
372}
373
e2c0f8ff 374static inline void mask_irq(struct irq_desc *desc)
0b1adaa0 375{
e2c0f8ff
TG
376 if (desc->irq_data.chip->irq_mask) {
377 desc->irq_data.chip->irq_mask(&desc->irq_data);
0b1adaa0
TG
378 desc->status |= IRQ_MASKED;
379 }
380}
381
0eda58b7 382static inline void unmask_irq(struct irq_desc *desc)
0b1adaa0 383{
0eda58b7
TG
384 if (desc->irq_data.chip->irq_unmask) {
385 desc->irq_data.chip->irq_unmask(&desc->irq_data);
0b1adaa0
TG
386 desc->status &= ~IRQ_MASKED;
387 }
dd87eb3a
TG
388}
389
399b5da2
TG
390/*
391 * handle_nested_irq - Handle a nested irq from a irq thread
392 * @irq: the interrupt number
393 *
394 * Handle interrupts which are nested into a threaded interrupt
395 * handler. The handler function is called inside the calling
396 * threads context.
397 */
398void handle_nested_irq(unsigned int irq)
399{
400 struct irq_desc *desc = irq_to_desc(irq);
401 struct irqaction *action;
402 irqreturn_t action_ret;
403
404 might_sleep();
405
239007b8 406 raw_spin_lock_irq(&desc->lock);
399b5da2
TG
407
408 kstat_incr_irqs_this_cpu(irq, desc);
409
410 action = desc->action;
411 if (unlikely(!action || (desc->status & IRQ_DISABLED)))
412 goto out_unlock;
413
414 desc->status |= IRQ_INPROGRESS;
239007b8 415 raw_spin_unlock_irq(&desc->lock);
399b5da2
TG
416
417 action_ret = action->thread_fn(action->irq, action->dev_id);
418 if (!noirqdebug)
419 note_interrupt(irq, desc, action_ret);
420
239007b8 421 raw_spin_lock_irq(&desc->lock);
399b5da2
TG
422 desc->status &= ~IRQ_INPROGRESS;
423
424out_unlock:
239007b8 425 raw_spin_unlock_irq(&desc->lock);
399b5da2
TG
426}
427EXPORT_SYMBOL_GPL(handle_nested_irq);
428
fe200ae4
TG
429static bool irq_check_poll(struct irq_desc *desc)
430{
431 if (!(desc->status & IRQ_POLL_INPROGRESS))
432 return false;
433 return irq_wait_for_poll(desc);
434}
435
dd87eb3a
TG
436/**
437 * handle_simple_irq - Simple and software-decoded IRQs.
438 * @irq: the interrupt number
439 * @desc: the interrupt description structure for this irq
dd87eb3a
TG
440 *
441 * Simple interrupts are either sent from a demultiplexing interrupt
442 * handler or come from hardware, where no interrupt hardware control
443 * is necessary.
444 *
445 * Note: The caller is expected to handle the ack, clear, mask and
446 * unmask issues if necessary.
447 */
7ad5b3a5 448void
7d12e780 449handle_simple_irq(unsigned int irq, struct irq_desc *desc)
dd87eb3a 450{
239007b8 451 raw_spin_lock(&desc->lock);
dd87eb3a
TG
452
453 if (unlikely(desc->status & IRQ_INPROGRESS))
fe200ae4
TG
454 if (!irq_check_poll(desc))
455 goto out_unlock;
456
971e5b35 457 desc->status &= ~(IRQ_REPLAY | IRQ_WAITING);
d6c88a50 458 kstat_incr_irqs_this_cpu(irq, desc);
dd87eb3a 459
107781e7 460 if (unlikely(!desc->action || (desc->status & IRQ_DISABLED)))
dd87eb3a
TG
461 goto out_unlock;
462
107781e7 463 handle_irq_event(desc);
dd87eb3a 464
dd87eb3a 465out_unlock:
239007b8 466 raw_spin_unlock(&desc->lock);
dd87eb3a
TG
467}
468
469/**
470 * handle_level_irq - Level type irq handler
471 * @irq: the interrupt number
472 * @desc: the interrupt description structure for this irq
dd87eb3a
TG
473 *
474 * Level type interrupts are active as long as the hardware line has
475 * the active level. This may require to mask the interrupt and unmask
476 * it after the associated handler has acknowledged the device, so the
477 * interrupt line is back to inactive.
478 */
7ad5b3a5 479void
7d12e780 480handle_level_irq(unsigned int irq, struct irq_desc *desc)
dd87eb3a 481{
239007b8 482 raw_spin_lock(&desc->lock);
9205e31d 483 mask_ack_irq(desc);
dd87eb3a
TG
484
485 if (unlikely(desc->status & IRQ_INPROGRESS))
fe200ae4
TG
486 if (!irq_check_poll(desc))
487 goto out_unlock;
488
dd87eb3a 489 desc->status &= ~(IRQ_REPLAY | IRQ_WAITING);
d6c88a50 490 kstat_incr_irqs_this_cpu(irq, desc);
dd87eb3a
TG
491
492 /*
493 * If its disabled or no action available
494 * keep it masked and get out of here
495 */
1529866c 496 if (unlikely(!desc->action || (desc->status & IRQ_DISABLED)))
86998aa6 497 goto out_unlock;
dd87eb3a 498
1529866c 499 handle_irq_event(desc);
b25c340c 500
0b1adaa0 501 if (!(desc->status & (IRQ_DISABLED | IRQ_ONESHOT)))
0eda58b7 502 unmask_irq(desc);
86998aa6 503out_unlock:
239007b8 504 raw_spin_unlock(&desc->lock);
dd87eb3a 505}
14819ea1 506EXPORT_SYMBOL_GPL(handle_level_irq);
dd87eb3a
TG
507
508/**
47c2a3aa 509 * handle_fasteoi_irq - irq handler for transparent controllers
dd87eb3a
TG
510 * @irq: the interrupt number
511 * @desc: the interrupt description structure for this irq
dd87eb3a 512 *
47c2a3aa 513 * Only a single callback will be issued to the chip: an ->eoi()
dd87eb3a
TG
514 * call when the interrupt has been serviced. This enables support
515 * for modern forms of interrupt handlers, which handle the flow
516 * details in hardware, transparently.
517 */
7ad5b3a5 518void
7d12e780 519handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc)
dd87eb3a 520{
dd87eb3a
TG
521 struct irqaction *action;
522 irqreturn_t action_ret;
523
239007b8 524 raw_spin_lock(&desc->lock);
dd87eb3a
TG
525
526 if (unlikely(desc->status & IRQ_INPROGRESS))
fe200ae4
TG
527 if (!irq_check_poll(desc))
528 goto out;
dd87eb3a
TG
529
530 desc->status &= ~(IRQ_REPLAY | IRQ_WAITING);
d6c88a50 531 kstat_incr_irqs_this_cpu(irq, desc);
dd87eb3a
TG
532
533 /*
534 * If its disabled or no action available
76d21601 535 * then mask it and get out of here:
dd87eb3a
TG
536 */
537 action = desc->action;
98bb244b
BH
538 if (unlikely(!action || (desc->status & IRQ_DISABLED))) {
539 desc->status |= IRQ_PENDING;
e2c0f8ff 540 mask_irq(desc);
dd87eb3a 541 goto out;
98bb244b 542 }
dd87eb3a
TG
543
544 desc->status |= IRQ_INPROGRESS;
98bb244b 545 desc->status &= ~IRQ_PENDING;
239007b8 546 raw_spin_unlock(&desc->lock);
dd87eb3a 547
7d12e780 548 action_ret = handle_IRQ_event(irq, action);
dd87eb3a 549 if (!noirqdebug)
7d12e780 550 note_interrupt(irq, desc, action_ret);
dd87eb3a 551
239007b8 552 raw_spin_lock(&desc->lock);
dd87eb3a
TG
553 desc->status &= ~IRQ_INPROGRESS;
554out:
0c5c1557 555 desc->irq_data.chip->irq_eoi(&desc->irq_data);
dd87eb3a 556
239007b8 557 raw_spin_unlock(&desc->lock);
dd87eb3a
TG
558}
559
560/**
561 * handle_edge_irq - edge type IRQ handler
562 * @irq: the interrupt number
563 * @desc: the interrupt description structure for this irq
dd87eb3a
TG
564 *
565 * Interrupt occures on the falling and/or rising edge of a hardware
566 * signal. The occurence is latched into the irq controller hardware
567 * and must be acked in order to be reenabled. After the ack another
568 * interrupt can happen on the same source even before the first one
dfff0615 569 * is handled by the associated event handler. If this happens it
dd87eb3a
TG
570 * might be necessary to disable (mask) the interrupt depending on the
571 * controller hardware. This requires to reenable the interrupt inside
572 * of the loop which handles the interrupts which have arrived while
573 * the handler was running. If all pending interrupts are handled, the
574 * loop is left.
575 */
7ad5b3a5 576void
7d12e780 577handle_edge_irq(unsigned int irq, struct irq_desc *desc)
dd87eb3a 578{
239007b8 579 raw_spin_lock(&desc->lock);
dd87eb3a
TG
580
581 desc->status &= ~(IRQ_REPLAY | IRQ_WAITING);
582
583 /*
584 * If we're currently running this IRQ, or its disabled,
585 * we shouldn't process the IRQ. Mark it pending, handle
586 * the necessary masking and go out
587 */
588 if (unlikely((desc->status & (IRQ_INPROGRESS | IRQ_DISABLED)) ||
589 !desc->action)) {
fe200ae4 590 if (!irq_check_poll(desc)) {
d78f8dd3 591 desc->status |= IRQ_PENDING;
fe200ae4
TG
592 mask_ack_irq(desc);
593 goto out_unlock;
594 }
dd87eb3a 595 }
d6c88a50 596 kstat_incr_irqs_this_cpu(irq, desc);
dd87eb3a
TG
597
598 /* Start handling the irq */
22a49163 599 desc->irq_data.chip->irq_ack(&desc->irq_data);
dd87eb3a
TG
600
601 /* Mark the IRQ currently in progress.*/
602 desc->status |= IRQ_INPROGRESS;
603
604 do {
605 struct irqaction *action = desc->action;
606 irqreturn_t action_ret;
607
608 if (unlikely(!action)) {
e2c0f8ff 609 mask_irq(desc);
dd87eb3a
TG
610 goto out_unlock;
611 }
612
613 /*
614 * When another irq arrived while we were handling
615 * one, we could have masked the irq.
616 * Renable it, if it was not disabled in meantime.
617 */
618 if (unlikely((desc->status &
619 (IRQ_PENDING | IRQ_MASKED | IRQ_DISABLED)) ==
620 (IRQ_PENDING | IRQ_MASKED))) {
0eda58b7 621 unmask_irq(desc);
dd87eb3a
TG
622 }
623
624 desc->status &= ~IRQ_PENDING;
239007b8 625 raw_spin_unlock(&desc->lock);
7d12e780 626 action_ret = handle_IRQ_event(irq, action);
dd87eb3a 627 if (!noirqdebug)
7d12e780 628 note_interrupt(irq, desc, action_ret);
239007b8 629 raw_spin_lock(&desc->lock);
dd87eb3a
TG
630
631 } while ((desc->status & (IRQ_PENDING | IRQ_DISABLED)) == IRQ_PENDING);
632
633 desc->status &= ~IRQ_INPROGRESS;
634out_unlock:
239007b8 635 raw_spin_unlock(&desc->lock);
dd87eb3a
TG
636}
637
dd87eb3a 638/**
24b26d42 639 * handle_percpu_irq - Per CPU local irq handler
dd87eb3a
TG
640 * @irq: the interrupt number
641 * @desc: the interrupt description structure for this irq
dd87eb3a
TG
642 *
643 * Per CPU interrupts on SMP machines without locking requirements
644 */
7ad5b3a5 645void
7d12e780 646handle_percpu_irq(unsigned int irq, struct irq_desc *desc)
dd87eb3a
TG
647{
648 irqreturn_t action_ret;
649
d6c88a50 650 kstat_incr_irqs_this_cpu(irq, desc);
dd87eb3a 651
22a49163
TG
652 if (desc->irq_data.chip->irq_ack)
653 desc->irq_data.chip->irq_ack(&desc->irq_data);
dd87eb3a 654
7d12e780 655 action_ret = handle_IRQ_event(irq, desc->action);
dd87eb3a 656 if (!noirqdebug)
7d12e780 657 note_interrupt(irq, desc, action_ret);
dd87eb3a 658
0c5c1557
TG
659 if (desc->irq_data.chip->irq_eoi)
660 desc->irq_data.chip->irq_eoi(&desc->irq_data);
dd87eb3a
TG
661}
662
dd87eb3a 663void
a460e745
IM
664__set_irq_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained,
665 const char *name)
dd87eb3a 666{
d3c60047 667 struct irq_desc *desc = irq_to_desc(irq);
dd87eb3a
TG
668 unsigned long flags;
669
7d94f7ca 670 if (!desc) {
dd87eb3a
TG
671 printk(KERN_ERR
672 "Trying to install type control for IRQ%d\n", irq);
673 return;
674 }
675
dd87eb3a
TG
676 if (!handle)
677 handle = handle_bad_irq;
6b8ff312 678 else if (desc->irq_data.chip == &no_irq_chip) {
f8b5473f 679 printk(KERN_WARNING "Trying to install %sinterrupt handler "
b039db8e 680 "for IRQ%d\n", is_chained ? "chained " : "", irq);
f8b5473f
TG
681 /*
682 * Some ARM implementations install a handler for really dumb
683 * interrupt hardware without setting an irq_chip. This worked
684 * with the ARM no_irq_chip but the check in setup_irq would
685 * prevent us to setup the interrupt at all. Switch it to
686 * dummy_irq_chip for easy transition.
687 */
6b8ff312 688 desc->irq_data.chip = &dummy_irq_chip;
f8b5473f 689 }
dd87eb3a 690
3876ec9e 691 chip_bus_lock(desc);
239007b8 692 raw_spin_lock_irqsave(&desc->lock, flags);
dd87eb3a
TG
693
694 /* Uninstall? */
695 if (handle == handle_bad_irq) {
6b8ff312 696 if (desc->irq_data.chip != &no_irq_chip)
9205e31d 697 mask_ack_irq(desc);
dd87eb3a
TG
698 desc->status |= IRQ_DISABLED;
699 desc->depth = 1;
700 }
701 desc->handle_irq = handle;
a460e745 702 desc->name = name;
dd87eb3a
TG
703
704 if (handle != handle_bad_irq && is_chained) {
dd87eb3a 705 desc->status |= IRQ_NOREQUEST | IRQ_NOPROBE;
46999238 706 irq_startup(desc);
dd87eb3a 707 }
239007b8 708 raw_spin_unlock_irqrestore(&desc->lock, flags);
3876ec9e 709 chip_bus_sync_unlock(desc);
dd87eb3a 710}
14819ea1 711EXPORT_SYMBOL_GPL(__set_irq_handler);
dd87eb3a
TG
712
713void
714set_irq_chip_and_handler(unsigned int irq, struct irq_chip *chip,
57a58a94 715 irq_flow_handler_t handle)
dd87eb3a
TG
716{
717 set_irq_chip(irq, chip);
a460e745 718 __set_irq_handler(irq, handle, 0, NULL);
dd87eb3a
TG
719}
720
a460e745
IM
721void
722set_irq_chip_and_handler_name(unsigned int irq, struct irq_chip *chip,
723 irq_flow_handler_t handle, const char *name)
dd87eb3a 724{
a460e745
IM
725 set_irq_chip(irq, chip);
726 __set_irq_handler(irq, handle, 0, name);
dd87eb3a 727}
46f4f8f6 728
44247184 729void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set)
46f4f8f6 730{
d3c60047 731 struct irq_desc *desc = irq_to_desc(irq);
46f4f8f6
RB
732 unsigned long flags;
733
44247184 734 if (!desc)
46f4f8f6 735 return;
46f4f8f6 736
44247184
TG
737 /* Sanitize flags */
738 set &= IRQF_MODIFY_MASK;
739 clr &= IRQF_MODIFY_MASK;
46f4f8f6 740
239007b8 741 raw_spin_lock_irqsave(&desc->lock, flags);
44247184
TG
742 desc->status &= ~clr;
743 desc->status |= set;
239007b8 744 raw_spin_unlock_irqrestore(&desc->lock, flags);
46f4f8f6 745}