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bnx2x: fix rx ring size report
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / bnx2x / bnx2x_ethtool.c
CommitLineData
de0c62db
DK		 1/* bnx2x_ethtool.c: Broadcom Everest network driver.
2 *
5de92408 3 * Copyright (c) 2007-2011 Broadcom Corporation
de0c62db
DK		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
15 *
16 */
17#include <linux/ethtool.h>
18#include <linux/netdevice.h>
19#include <linux/types.h>
20#include <linux/sched.h>
21#include <linux/crc32.h>
22
23
24#include "bnx2x.h"
25#include "bnx2x_cmn.h"
26#include "bnx2x_dump.h"
4a33bc03 27#include "bnx2x_init.h"
042181f5 28#include "bnx2x_sp.h"
de0c62db 29
ec6ba945
VZ		 30/* Note: in the format strings below %s is replaced by the queue-name which is
31 * either its index or 'fcoe' for the fcoe queue. Make sure the format string
32 * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2
33 */
34#define MAX_QUEUE_NAME_LEN 4
35static const struct {
36 long offset;
37 int size;
38 char string[ETH_GSTRING_LEN];
39} bnx2x_q_stats_arr[] = {
40/* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" },
ec6ba945
VZ		 41 { Q_STATS_OFFSET32(total_unicast_packets_received_hi),
42 8, "[%s]: rx_ucast_packets" },
43 { Q_STATS_OFFSET32(total_multicast_packets_received_hi),
44 8, "[%s]: rx_mcast_packets" },
45 { Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
46 8, "[%s]: rx_bcast_packets" },
47 { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" },
48 { Q_STATS_OFFSET32(rx_err_discard_pkt),
49 4, "[%s]: rx_phy_ip_err_discards"},
50 { Q_STATS_OFFSET32(rx_skb_alloc_failed),
51 4, "[%s]: rx_skb_alloc_discard" },
52 { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" },
53
619c5cb6
VZ		 54 { Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" },
55/* 10 */{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
ec6ba945
VZ		 56 8, "[%s]: tx_ucast_packets" },
57 { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi),
58 8, "[%s]: tx_mcast_packets" },
59 { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
619c5cb6
VZ		 60 8, "[%s]: tx_bcast_packets" },
61 { Q_STATS_OFFSET32(total_tpa_aggregations_hi),
62 8, "[%s]: tpa_aggregations" },
63 { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi),
64 8, "[%s]: tpa_aggregated_frames"},
65 { Q_STATS_OFFSET32(total_tpa_bytes_hi), 8, "[%s]: tpa_bytes"}
ec6ba945
VZ		 66};
67
68#define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr)
69
70static const struct {
71 long offset;
72 int size;
73 u32 flags;
74#define STATS_FLAGS_PORT 1
75#define STATS_FLAGS_FUNC 2
76#define STATS_FLAGS_BOTH (STATS_FLAGS_FUNC | STATS_FLAGS_PORT)
77 char string[ETH_GSTRING_LEN];
78} bnx2x_stats_arr[] = {
79/* 1 */ { STATS_OFFSET32(total_bytes_received_hi),
80 8, STATS_FLAGS_BOTH, "rx_bytes" },
81 { STATS_OFFSET32(error_bytes_received_hi),
82 8, STATS_FLAGS_BOTH, "rx_error_bytes" },
83 { STATS_OFFSET32(total_unicast_packets_received_hi),
84 8, STATS_FLAGS_BOTH, "rx_ucast_packets" },
85 { STATS_OFFSET32(total_multicast_packets_received_hi),
86 8, STATS_FLAGS_BOTH, "rx_mcast_packets" },
87 { STATS_OFFSET32(total_broadcast_packets_received_hi),
88 8, STATS_FLAGS_BOTH, "rx_bcast_packets" },
89 { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
90 8, STATS_FLAGS_PORT, "rx_crc_errors" },
91 { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
92 8, STATS_FLAGS_PORT, "rx_align_errors" },
93 { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
94 8, STATS_FLAGS_PORT, "rx_undersize_packets" },
95 { STATS_OFFSET32(etherstatsoverrsizepkts_hi),
96 8, STATS_FLAGS_PORT, "rx_oversize_packets" },
97/* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
98 8, STATS_FLAGS_PORT, "rx_fragments" },
99 { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
100 8, STATS_FLAGS_PORT, "rx_jabbers" },
101 { STATS_OFFSET32(no_buff_discard_hi),
102 8, STATS_FLAGS_BOTH, "rx_discards" },
103 { STATS_OFFSET32(mac_filter_discard),
104 4, STATS_FLAGS_PORT, "rx_filtered_packets" },
619c5cb6
VZ		 105 { STATS_OFFSET32(mf_tag_discard),
106 4, STATS_FLAGS_PORT, "rx_mf_tag_discard" },
ec6ba945
VZ		 107 { STATS_OFFSET32(brb_drop_hi),
108 8, STATS_FLAGS_PORT, "rx_brb_discard" },
109 { STATS_OFFSET32(brb_truncate_hi),
110 8, STATS_FLAGS_PORT, "rx_brb_truncate" },
111 { STATS_OFFSET32(pause_frames_received_hi),
112 8, STATS_FLAGS_PORT, "rx_pause_frames" },
113 { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
114 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" },
115 { STATS_OFFSET32(nig_timer_max),
116 4, STATS_FLAGS_PORT, "rx_constant_pause_events" },
117/* 20 */{ STATS_OFFSET32(rx_err_discard_pkt),
118 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"},
119 { STATS_OFFSET32(rx_skb_alloc_failed),
120 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" },
121 { STATS_OFFSET32(hw_csum_err),
122 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" },
123
124 { STATS_OFFSET32(total_bytes_transmitted_hi),
125 8, STATS_FLAGS_BOTH, "tx_bytes" },
126 { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
127 8, STATS_FLAGS_PORT, "tx_error_bytes" },
128 { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
129 8, STATS_FLAGS_BOTH, "tx_ucast_packets" },
130 { STATS_OFFSET32(total_multicast_packets_transmitted_hi),
131 8, STATS_FLAGS_BOTH, "tx_mcast_packets" },
132 { STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
133 8, STATS_FLAGS_BOTH, "tx_bcast_packets" },
134 { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
135 8, STATS_FLAGS_PORT, "tx_mac_errors" },
136 { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
137 8, STATS_FLAGS_PORT, "tx_carrier_errors" },
138/* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
139 8, STATS_FLAGS_PORT, "tx_single_collisions" },
140 { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
141 8, STATS_FLAGS_PORT, "tx_multi_collisions" },
142 { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
143 8, STATS_FLAGS_PORT, "tx_deferred" },
144 { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
145 8, STATS_FLAGS_PORT, "tx_excess_collisions" },
146 { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
147 8, STATS_FLAGS_PORT, "tx_late_collisions" },
148 { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
149 8, STATS_FLAGS_PORT, "tx_total_collisions" },
150 { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
151 8, STATS_FLAGS_PORT, "tx_64_byte_packets" },
152 { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
153 8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" },
154 { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
155 8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" },
156 { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
157 8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" },
158/* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
159 8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" },
160 { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
161 8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" },
162 { STATS_OFFSET32(etherstatspktsover1522octets_hi),
163 8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" },
164 { STATS_OFFSET32(pause_frames_sent_hi),
619c5cb6
VZ		 165 8, STATS_FLAGS_PORT, "tx_pause_frames" },
166 { STATS_OFFSET32(total_tpa_aggregations_hi),
167 8, STATS_FLAGS_FUNC, "tpa_aggregations" },
168 { STATS_OFFSET32(total_tpa_aggregated_frames_hi),
169 8, STATS_FLAGS_FUNC, "tpa_aggregated_frames"},
170 { STATS_OFFSET32(total_tpa_bytes_hi),
171 8, STATS_FLAGS_FUNC, "tpa_bytes"}
ec6ba945
VZ		 172};
173
174#define BNX2X_NUM_STATS ARRAY_SIZE(bnx2x_stats_arr)
1ac9e428
YR		 175static int bnx2x_get_port_type(struct bnx2x *bp)
176{
177 int port_type;
178 u32 phy_idx = bnx2x_get_cur_phy_idx(bp);
179 switch (bp->link_params.phy[phy_idx].media_type) {
180 case ETH_PHY_SFP_FIBER:
181 case ETH_PHY_XFP_FIBER:
182 case ETH_PHY_KR:
183 case ETH_PHY_CX4:
184 port_type = PORT_FIBRE;
185 break;
186 case ETH_PHY_DA_TWINAX:
187 port_type = PORT_DA;
188 break;
189 case ETH_PHY_BASE_T:
190 port_type = PORT_TP;
191 break;
192 case ETH_PHY_NOT_PRESENT:
193 port_type = PORT_NONE;
194 break;
195 case ETH_PHY_UNSPECIFIED:
196 default:
197 port_type = PORT_OTHER;
198 break;
199 }
200 return port_type;
201}
ec6ba945 202
de0c62db
DK		 203static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
204{
205 struct bnx2x *bp = netdev_priv(dev);
a22f0788 206 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
b3337e4c 207
a22f0788
YR		 208 /* Dual Media boards present all available port types */
209 cmd->supported = bp->port.supported[cfg_idx] |
210 (bp->port.supported[cfg_idx ^ 1] &
211 (SUPPORTED_TP | SUPPORTED_FIBRE));
212 cmd->advertising = bp->port.advertising[cfg_idx];
de0c62db
DK		 213
214 if ((bp->state == BNX2X_STATE_OPEN) &&
215 !(bp->flags & MF_FUNC_DIS) &&
216 (bp->link_vars.link_up)) {
b3337e4c 217 ethtool_cmd_speed_set(cmd, bp->link_vars.line_speed);
de0c62db 218 cmd->duplex = bp->link_vars.duplex;
de0c62db 219 } else {
b3337e4c
DD		 220 ethtool_cmd_speed_set(
221 cmd, bp->link_params.req_line_speed[cfg_idx]);
a22f0788 222 cmd->duplex = bp->link_params.req_duplex[cfg_idx];
de0c62db 223 }
f2e0899f 224
0793f83f 225 if (IS_MF(bp))
b3337e4c 226 ethtool_cmd_speed_set(cmd, bnx2x_get_mf_speed(bp));
de0c62db 227
1ac9e428 228 cmd->port = bnx2x_get_port_type(bp);
a22f0788 229
de0c62db
DK		 230 cmd->phy_address = bp->mdio.prtad;
231 cmd->transceiver = XCVR_INTERNAL;
232
a22f0788 233 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG)
de0c62db
DK		 234 cmd->autoneg = AUTONEG_ENABLE;
235 else
236 cmd->autoneg = AUTONEG_DISABLE;
237
238 cmd->maxtxpkt = 0;
239 cmd->maxrxpkt = 0;
240
241 DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n"
b3337e4c 242 DP_LEVEL " supported 0x%x advertising 0x%x speed %u\n"
de0c62db
DK		 243 DP_LEVEL " duplex %d port %d phy_address %d transceiver %d\n"
244 DP_LEVEL " autoneg %d maxtxpkt %d maxrxpkt %d\n",
b3337e4c
DD		 245 cmd->cmd, cmd->supported, cmd->advertising,
246 ethtool_cmd_speed(cmd),
de0c62db
DK		 247 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
248 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
249
250 return 0;
251}
252
253static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
254{
255 struct bnx2x *bp = netdev_priv(dev);
a22f0788 256 u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config;
0793f83f 257 u32 speed;
de0c62db 258
0793f83f 259 if (IS_MF_SD(bp))
de0c62db
DK		 260 return 0;
261
262 DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n"
b3337e4c 263 " supported 0x%x advertising 0x%x speed %u\n"
0793f83f
DK		 264 " duplex %d port %d phy_address %d transceiver %d\n"
265 " autoneg %d maxtxpkt %d maxrxpkt %d\n",
b3337e4c
DD		 266 cmd->cmd, cmd->supported, cmd->advertising,
267 ethtool_cmd_speed(cmd),
de0c62db
DK		 268 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
269 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
270
b3337e4c 271 speed = ethtool_cmd_speed(cmd);
0793f83f
DK		 272
273 if (IS_MF_SI(bp)) {
e3835b99 274 u32 part;
0793f83f
DK		 275 u32 line_speed = bp->link_vars.line_speed;
276
277 /* use 10G if no link detected */
278 if (!line_speed)
279 line_speed = 10000;
280
281 if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) {
282 BNX2X_DEV_INFO("To set speed BC %X or higher "
283 "is required, please upgrade BC\n",
284 REQ_BC_VER_4_SET_MF_BW);
285 return -EINVAL;
286 }
e3835b99 287
faa6fcbb 288 part = (speed * 100) / line_speed;
e3835b99 289
faa6fcbb
DK		 290 if (line_speed < speed || !part) {
291 BNX2X_DEV_INFO("Speed setting should be in a range "
292 "from 1%% to 100%% "
293 "of actual line speed\n");
0793f83f
DK		 294 return -EINVAL;
295 }
0793f83f 296
e3835b99
DK		 297 if (bp->state != BNX2X_STATE_OPEN)
298 /* store value for following "load" */
299 bp->pending_max = part;
300 else
301 bnx2x_update_max_mf_config(bp, part);
0793f83f 302
0793f83f
DK		 303 return 0;
304 }
305
a22f0788
YR		 306 cfg_idx = bnx2x_get_link_cfg_idx(bp);
307 old_multi_phy_config = bp->link_params.multi_phy_config;
308 switch (cmd->port) {
309 case PORT_TP:
310 if (bp->port.supported[cfg_idx] & SUPPORTED_TP)
311 break; /* no port change */
312
313 if (!(bp->port.supported[0] & SUPPORTED_TP ||
314 bp->port.supported[1] & SUPPORTED_TP)) {
315 DP(NETIF_MSG_LINK, "Unsupported port type\n");
316 return -EINVAL;
317 }
318 bp->link_params.multi_phy_config &=
319 ~PORT_HW_CFG_PHY_SELECTION_MASK;
320 if (bp->link_params.multi_phy_config &
321 PORT_HW_CFG_PHY_SWAPPED_ENABLED)
322 bp->link_params.multi_phy_config |=
323 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
324 else
325 bp->link_params.multi_phy_config |=
326 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
327 break;
328 case PORT_FIBRE:
329 if (bp->port.supported[cfg_idx] & SUPPORTED_FIBRE)
330 break; /* no port change */
331
332 if (!(bp->port.supported[0] & SUPPORTED_FIBRE ||
333 bp->port.supported[1] & SUPPORTED_FIBRE)) {
334 DP(NETIF_MSG_LINK, "Unsupported port type\n");
335 return -EINVAL;
336 }
337 bp->link_params.multi_phy_config &=
338 ~PORT_HW_CFG_PHY_SELECTION_MASK;
339 if (bp->link_params.multi_phy_config &
340 PORT_HW_CFG_PHY_SWAPPED_ENABLED)
341 bp->link_params.multi_phy_config |=
342 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
343 else
344 bp->link_params.multi_phy_config |=
345 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
346 break;
347 default:
348 DP(NETIF_MSG_LINK, "Unsupported port type\n");
349 return -EINVAL;
350 }
351 /* Save new config in case command complete successuly */
352 new_multi_phy_config = bp->link_params.multi_phy_config;
353 /* Get the new cfg_idx */
354 cfg_idx = bnx2x_get_link_cfg_idx(bp);
355 /* Restore old config in case command failed */
356 bp->link_params.multi_phy_config = old_multi_phy_config;
357 DP(NETIF_MSG_LINK, "cfg_idx = %x\n", cfg_idx);
358
de0c62db 359 if (cmd->autoneg == AUTONEG_ENABLE) {
a22f0788 360 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
de0c62db
DK		 361 DP(NETIF_MSG_LINK, "Autoneg not supported\n");
362 return -EINVAL;
363 }
364
365 /* advertise the requested speed and duplex if supported */
a22f0788 366 cmd->advertising &= bp->port.supported[cfg_idx];
de0c62db 367
a22f0788
YR		 368 bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG;
369 bp->link_params.req_duplex[cfg_idx] = DUPLEX_FULL;
370 bp->port.advertising[cfg_idx] |= (ADVERTISED_Autoneg |
de0c62db
DK		 371 cmd->advertising);
372
373 } else { /* forced speed */
374 /* advertise the requested speed and duplex if supported */
a22f0788 375 switch (speed) {
de0c62db
DK		 376 case SPEED_10:
377 if (cmd->duplex == DUPLEX_FULL) {
a22f0788 378 if (!(bp->port.supported[cfg_idx] &
de0c62db
DK		 379 SUPPORTED_10baseT_Full)) {
380 DP(NETIF_MSG_LINK,
381 "10M full not supported\n");
382 return -EINVAL;
383 }
384
385 advertising = (ADVERTISED_10baseT_Full |
386 ADVERTISED_TP);
387 } else {
a22f0788 388 if (!(bp->port.supported[cfg_idx] &
de0c62db
DK		 389 SUPPORTED_10baseT_Half)) {
390 DP(NETIF_MSG_LINK,
391 "10M half not supported\n");
392 return -EINVAL;
393 }
394
395 advertising = (ADVERTISED_10baseT_Half |
396 ADVERTISED_TP);
397 }
398 break;
399
400 case SPEED_100:
401 if (cmd->duplex == DUPLEX_FULL) {
a22f0788 402 if (!(bp->port.supported[cfg_idx] &
de0c62db
DK		 403 SUPPORTED_100baseT_Full)) {
404 DP(NETIF_MSG_LINK,
405 "100M full not supported\n");
406 return -EINVAL;
407 }
408
409 advertising = (ADVERTISED_100baseT_Full |
410 ADVERTISED_TP);
411 } else {
a22f0788 412 if (!(bp->port.supported[cfg_idx] &
de0c62db
DK		 413 SUPPORTED_100baseT_Half)) {
414 DP(NETIF_MSG_LINK,
415 "100M half not supported\n");
416 return -EINVAL;
417 }
418
419 advertising = (ADVERTISED_100baseT_Half |
420 ADVERTISED_TP);
421 }
422 break;
423
424 case SPEED_1000:
425 if (cmd->duplex != DUPLEX_FULL) {
426 DP(NETIF_MSG_LINK, "1G half not supported\n");
427 return -EINVAL;
428 }
429
a22f0788
YR		 430 if (!(bp->port.supported[cfg_idx] &
431 SUPPORTED_1000baseT_Full)) {
de0c62db
DK		 432 DP(NETIF_MSG_LINK, "1G full not supported\n");
433 return -EINVAL;
434 }
435
436 advertising = (ADVERTISED_1000baseT_Full |
437 ADVERTISED_TP);
438 break;
439
440 case SPEED_2500:
441 if (cmd->duplex != DUPLEX_FULL) {
442 DP(NETIF_MSG_LINK,
443 "2.5G half not supported\n");
444 return -EINVAL;
445 }
446
a22f0788
YR		 447 if (!(bp->port.supported[cfg_idx]
448 & SUPPORTED_2500baseX_Full)) {
de0c62db
DK		 449 DP(NETIF_MSG_LINK,
450 "2.5G full not supported\n");
451 return -EINVAL;
452 }
453
454 advertising = (ADVERTISED_2500baseX_Full |
455 ADVERTISED_TP);
456 break;
457
458 case SPEED_10000:
459 if (cmd->duplex != DUPLEX_FULL) {
460 DP(NETIF_MSG_LINK, "10G half not supported\n");
461 return -EINVAL;
462 }
463
a22f0788
YR		 464 if (!(bp->port.supported[cfg_idx]
465 & SUPPORTED_10000baseT_Full)) {
de0c62db
DK		 466 DP(NETIF_MSG_LINK, "10G full not supported\n");
467 return -EINVAL;
468 }
469
470 advertising = (ADVERTISED_10000baseT_Full |
471 ADVERTISED_FIBRE);
472 break;
473
474 default:
b3337e4c 475 DP(NETIF_MSG_LINK, "Unsupported speed %u\n", speed);
de0c62db
DK		 476 return -EINVAL;
477 }
478
a22f0788
YR		 479 bp->link_params.req_line_speed[cfg_idx] = speed;
480 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
481 bp->port.advertising[cfg_idx] = advertising;
de0c62db
DK		 482 }
483
484 DP(NETIF_MSG_LINK, "req_line_speed %d\n"
485 DP_LEVEL " req_duplex %d advertising 0x%x\n",
a22f0788
YR		 486 bp->link_params.req_line_speed[cfg_idx],
487 bp->link_params.req_duplex[cfg_idx],
488 bp->port.advertising[cfg_idx]);
de0c62db 489
a22f0788
YR		 490 /* Set new config */
491 bp->link_params.multi_phy_config = new_multi_phy_config;
de0c62db
DK		 492 if (netif_running(dev)) {
493 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
494 bnx2x_link_set(bp);
495 }
496
497 return 0;
498}
499
500#define IS_E1_ONLINE(info) (((info) & RI_E1_ONLINE) == RI_E1_ONLINE)
501#define IS_E1H_ONLINE(info) (((info) & RI_E1H_ONLINE) == RI_E1H_ONLINE)
f2e0899f 502#define IS_E2_ONLINE(info) (((info) & RI_E2_ONLINE) == RI_E2_ONLINE)
0fea29c1
VZ		 503#define IS_E3_ONLINE(info) (((info) & RI_E3_ONLINE) == RI_E3_ONLINE)
504#define IS_E3B0_ONLINE(info) (((info) & RI_E3B0_ONLINE) == RI_E3B0_ONLINE)
505
506static inline bool bnx2x_is_reg_online(struct bnx2x *bp,
507 const struct reg_addr *reg_info)
508{
509 if (CHIP_IS_E1(bp))
510 return IS_E1_ONLINE(reg_info->info);
511 else if (CHIP_IS_E1H(bp))
512 return IS_E1H_ONLINE(reg_info->info);
513 else if (CHIP_IS_E2(bp))
514 return IS_E2_ONLINE(reg_info->info);
515 else if (CHIP_IS_E3A0(bp))
516 return IS_E3_ONLINE(reg_info->info);
517 else if (CHIP_IS_E3B0(bp))
518 return IS_E3B0_ONLINE(reg_info->info);
519 else
520 return false;
521}
522
523/******* Paged registers info selectors ********/
524static inline const u32 *__bnx2x_get_page_addr_ar(struct bnx2x *bp)
525{
526 if (CHIP_IS_E2(bp))
527 return page_vals_e2;
528 else if (CHIP_IS_E3(bp))
529 return page_vals_e3;
530 else
531 return NULL;
532}
533
534static inline u32 __bnx2x_get_page_reg_num(struct bnx2x *bp)
535{
536 if (CHIP_IS_E2(bp))
537 return PAGE_MODE_VALUES_E2;
538 else if (CHIP_IS_E3(bp))
539 return PAGE_MODE_VALUES_E3;
540 else
541 return 0;
542}
543
544static inline const u32 *__bnx2x_get_page_write_ar(struct bnx2x *bp)
545{
546 if (CHIP_IS_E2(bp))
547 return page_write_regs_e2;
548 else if (CHIP_IS_E3(bp))
549 return page_write_regs_e3;
550 else
551 return NULL;
552}
553
554static inline u32 __bnx2x_get_page_write_num(struct bnx2x *bp)
555{
556 if (CHIP_IS_E2(bp))
557 return PAGE_WRITE_REGS_E2;
558 else if (CHIP_IS_E3(bp))
559 return PAGE_WRITE_REGS_E3;
560 else
561 return 0;
562}
563
564static inline const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp)
565{
566 if (CHIP_IS_E2(bp))
567 return page_read_regs_e2;
568 else if (CHIP_IS_E3(bp))
569 return page_read_regs_e3;
570 else
571 return NULL;
572}
573
574static inline u32 __bnx2x_get_page_read_num(struct bnx2x *bp)
575{
576 if (CHIP_IS_E2(bp))
577 return PAGE_READ_REGS_E2;
578 else if (CHIP_IS_E3(bp))
579 return PAGE_READ_REGS_E3;
580 else
581 return 0;
582}
583
584static inline int __bnx2x_get_regs_len(struct bnx2x *bp)
585{
586 int num_pages = __bnx2x_get_page_reg_num(bp);
587 int page_write_num = __bnx2x_get_page_write_num(bp);
588 const struct reg_addr *page_read_addr = __bnx2x_get_page_read_ar(bp);
589 int page_read_num = __bnx2x_get_page_read_num(bp);
590 int regdump_len = 0;
591 int i, j, k;
592
593 for (i = 0; i < REGS_COUNT; i++)
594 if (bnx2x_is_reg_online(bp, &reg_addrs[i]))
595 regdump_len += reg_addrs[i].size;
596
597 for (i = 0; i < num_pages; i++)
598 for (j = 0; j < page_write_num; j++)
599 for (k = 0; k < page_read_num; k++)
600 if (bnx2x_is_reg_online(bp, &page_read_addr[k]))
601 regdump_len += page_read_addr[k].size;
602
603 return regdump_len;
604}
de0c62db
DK		 605
606static int bnx2x_get_regs_len(struct net_device *dev)
607{
608 struct bnx2x *bp = netdev_priv(dev);
609 int regdump_len = 0;
de0c62db 610
0fea29c1 611 regdump_len = __bnx2x_get_regs_len(bp);
de0c62db
DK		 612 regdump_len *= 4;
613 regdump_len += sizeof(struct dump_hdr);
614
615 return regdump_len;
616}
617
0fea29c1
VZ		 618/**
619 * bnx2x_read_pages_regs - read "paged" registers
620 *
621 * @bp device handle
622 * @p output buffer
623 *
624 * Reads "paged" memories: memories that may only be read by first writing to a
625 * specific address ("write address") and then reading from a specific address
626 * ("read address"). There may be more than one write address per "page" and
627 * more than one read address per write address.
628 */
629static inline void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p)
f2e0899f
DK		 630{
631 u32 i, j, k, n;
0fea29c1
VZ		 632 /* addresses of the paged registers */
633 const u32 *page_addr = __bnx2x_get_page_addr_ar(bp);
634 /* number of paged registers */
635 int num_pages = __bnx2x_get_page_reg_num(bp);
636 /* write addresses */
637 const u32 *write_addr = __bnx2x_get_page_write_ar(bp);
638 /* number of write addresses */
639 int write_num = __bnx2x_get_page_write_num(bp);
640 /* read addresses info */
641 const struct reg_addr *read_addr = __bnx2x_get_page_read_ar(bp);
642 /* number of read addresses */
643 int read_num = __bnx2x_get_page_read_num(bp);
644
645 for (i = 0; i < num_pages; i++) {
646 for (j = 0; j < write_num; j++) {
647 REG_WR(bp, write_addr[j], page_addr[i]);
648 for (k = 0; k < read_num; k++)
649 if (bnx2x_is_reg_online(bp, &read_addr[k]))
f2e0899f 650 for (n = 0; n <
0fea29c1 651 read_addr[k].size; n++)
f2e0899f 652 *p++ = REG_RD(bp,
0fea29c1 653 read_addr[k].addr + n*4);
f2e0899f
DK		 654 }
655 }
656}
657
0fea29c1
VZ		 658static inline void __bnx2x_get_regs(struct bnx2x *bp, u32 *p)
659{
660 u32 i, j;
661
662 /* Read the regular registers */
663 for (i = 0; i < REGS_COUNT; i++)
664 if (bnx2x_is_reg_online(bp, &reg_addrs[i]))
665 for (j = 0; j < reg_addrs[i].size; j++)
666 *p++ = REG_RD(bp, reg_addrs[i].addr + j*4);
667
668 /* Read "paged" registes */
669 bnx2x_read_pages_regs(bp, p);
670}
671
de0c62db
DK		 672static void bnx2x_get_regs(struct net_device *dev,
673 struct ethtool_regs *regs, void *_p)
674{
0fea29c1 675 u32 *p = _p;
de0c62db
DK		 676 struct bnx2x *bp = netdev_priv(dev);
677 struct dump_hdr dump_hdr = {0};
678
679 regs->version = 0;
680 memset(p, 0, regs->len);
681
682 if (!netif_running(bp->dev))
683 return;
684
4a33bc03
VZ		 685 /* Disable parity attentions as long as following dump may
686 * cause false alarms by reading never written registers. We
687 * will re-enable parity attentions right after the dump.
688 */
689 bnx2x_disable_blocks_parity(bp);
690
de0c62db
DK		 691 dump_hdr.hdr_size = (sizeof(struct dump_hdr) / 4) - 1;
692 dump_hdr.dump_sign = dump_sign_all;
693 dump_hdr.xstorm_waitp = REG_RD(bp, XSTORM_WAITP_ADDR);
694 dump_hdr.tstorm_waitp = REG_RD(bp, TSTORM_WAITP_ADDR);
695 dump_hdr.ustorm_waitp = REG_RD(bp, USTORM_WAITP_ADDR);
696 dump_hdr.cstorm_waitp = REG_RD(bp, CSTORM_WAITP_ADDR);
f2e0899f
DK		 697
698 if (CHIP_IS_E1(bp))
699 dump_hdr.info = RI_E1_ONLINE;
700 else if (CHIP_IS_E1H(bp))
701 dump_hdr.info = RI_E1H_ONLINE;
619c5cb6 702 else if (!CHIP_IS_E1x(bp))
f2e0899f
DK		 703 dump_hdr.info = RI_E2_ONLINE |
704 (BP_PATH(bp) ? RI_PATH1_DUMP : RI_PATH0_DUMP);
de0c62db
DK		 705
706 memcpy(p, &dump_hdr, sizeof(struct dump_hdr));
707 p += dump_hdr.hdr_size + 1;
708
0fea29c1
VZ		 709 /* Actually read the registers */
710 __bnx2x_get_regs(bp, p);
711
4a33bc03
VZ		 712 /* Re-enable parity attentions */
713 bnx2x_clear_blocks_parity(bp);
c9ee9206 714 bnx2x_enable_blocks_parity(bp);
de0c62db
DK		 715}
716
de0c62db
DK		 717static void bnx2x_get_drvinfo(struct net_device *dev,
718 struct ethtool_drvinfo *info)
719{
720 struct bnx2x *bp = netdev_priv(dev);
721 u8 phy_fw_ver[PHY_FW_VER_LEN];
722
723 strcpy(info->driver, DRV_MODULE_NAME);
724 strcpy(info->version, DRV_MODULE_VERSION);
725
726 phy_fw_ver[0] = '\0';
727 if (bp->port.pmf) {
728 bnx2x_acquire_phy_lock(bp);
729 bnx2x_get_ext_phy_fw_version(&bp->link_params,
730 (bp->state != BNX2X_STATE_CLOSED),
731 phy_fw_ver, PHY_FW_VER_LEN);
732 bnx2x_release_phy_lock(bp);
733 }
734
735 strncpy(info->fw_version, bp->fw_ver, 32);
736 snprintf(info->fw_version + strlen(bp->fw_ver), 32 - strlen(bp->fw_ver),
737 "bc %d.%d.%d%s%s",
738 (bp->common.bc_ver & 0xff0000) >> 16,
739 (bp->common.bc_ver & 0xff00) >> 8,
740 (bp->common.bc_ver & 0xff),
741 ((phy_fw_ver[0] != '\0') ? " phy " : ""), phy_fw_ver);
742 strcpy(info->bus_info, pci_name(bp->pdev));
743 info->n_stats = BNX2X_NUM_STATS;
744 info->testinfo_len = BNX2X_NUM_TESTS;
745 info->eedump_len = bp->common.flash_size;
746 info->regdump_len = bnx2x_get_regs_len(dev);
747}
748
749static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
750{
751 struct bnx2x *bp = netdev_priv(dev);
752
753 if (bp->flags & NO_WOL_FLAG) {
754 wol->supported = 0;
755 wol->wolopts = 0;
756 } else {
757 wol->supported = WAKE_MAGIC;
758 if (bp->wol)
759 wol->wolopts = WAKE_MAGIC;
760 else
761 wol->wolopts = 0;
762 }
763 memset(&wol->sopass, 0, sizeof(wol->sopass));
764}
765
766static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
767{
768 struct bnx2x *bp = netdev_priv(dev);
769
770 if (wol->wolopts & ~WAKE_MAGIC)
771 return -EINVAL;
772
773 if (wol->wolopts & WAKE_MAGIC) {
774 if (bp->flags & NO_WOL_FLAG)
775 return -EINVAL;
776
777 bp->wol = 1;
778 } else
779 bp->wol = 0;
780
781 return 0;
782}
783
784static u32 bnx2x_get_msglevel(struct net_device *dev)
785{
786 struct bnx2x *bp = netdev_priv(dev);
787
788 return bp->msg_enable;
789}
790
791static void bnx2x_set_msglevel(struct net_device *dev, u32 level)
792{
793 struct bnx2x *bp = netdev_priv(dev);
794
7a25cc73
DK		 795 if (capable(CAP_NET_ADMIN)) {
796 /* dump MCP trace */
797 if (level & BNX2X_MSG_MCP)
798 bnx2x_fw_dump_lvl(bp, KERN_INFO);
de0c62db 799 bp->msg_enable = level;
7a25cc73 800 }
de0c62db
DK		 801}
802
803static int bnx2x_nway_reset(struct net_device *dev)
804{
805 struct bnx2x *bp = netdev_priv(dev);
806
807 if (!bp->port.pmf)
808 return 0;
809
810 if (netif_running(dev)) {
811 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
812 bnx2x_link_set(bp);
813 }
814
815 return 0;
816}
817
818static u32 bnx2x_get_link(struct net_device *dev)
819{
820 struct bnx2x *bp = netdev_priv(dev);
821
f2e0899f 822 if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN))
de0c62db
DK		 823 return 0;
824
825 return bp->link_vars.link_up;
826}
827
828static int bnx2x_get_eeprom_len(struct net_device *dev)
829{
830 struct bnx2x *bp = netdev_priv(dev);
831
832 return bp->common.flash_size;
833}
834
835static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
836{
837 int port = BP_PORT(bp);
838 int count, i;
839 u32 val = 0;
840
841 /* adjust timeout for emulation/FPGA */
754a2f52 842 count = BNX2X_NVRAM_TIMEOUT_COUNT;
de0c62db
DK		 843 if (CHIP_REV_IS_SLOW(bp))
844 count *= 100;
845
846 /* request access to nvram interface */
847 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
848 (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
849
850 for (i = 0; i < count*10; i++) {
851 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
852 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
853 break;
854
855 udelay(5);
856 }
857
858 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
859 DP(BNX2X_MSG_NVM, "cannot get access to nvram interface\n");
860 return -EBUSY;
861 }
862
863 return 0;
864}
865
866static int bnx2x_release_nvram_lock(struct bnx2x *bp)
867{
868 int port = BP_PORT(bp);
869 int count, i;
870 u32 val = 0;
871
872 /* adjust timeout for emulation/FPGA */
754a2f52 873 count = BNX2X_NVRAM_TIMEOUT_COUNT;
de0c62db
DK		 874 if (CHIP_REV_IS_SLOW(bp))
875 count *= 100;
876
877 /* relinquish nvram interface */
878 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
879 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
880
881 for (i = 0; i < count*10; i++) {
882 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
883 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
884 break;
885
886 udelay(5);
887 }
888
889 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
890 DP(BNX2X_MSG_NVM, "cannot free access to nvram interface\n");
891 return -EBUSY;
892 }
893
894 return 0;
895}
896
897static void bnx2x_enable_nvram_access(struct bnx2x *bp)
898{
899 u32 val;
900
901 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
902
903 /* enable both bits, even on read */
904 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
905 (val | MCPR_NVM_ACCESS_ENABLE_EN |
906 MCPR_NVM_ACCESS_ENABLE_WR_EN));
907}
908
909static void bnx2x_disable_nvram_access(struct bnx2x *bp)
910{
911 u32 val;
912
913 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
914
915 /* disable both bits, even after read */
916 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
917 (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
918 MCPR_NVM_ACCESS_ENABLE_WR_EN)));
919}
920
921static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val,
922 u32 cmd_flags)
923{
924 int count, i, rc;
925 u32 val;
926
927 /* build the command word */
928 cmd_flags |= MCPR_NVM_COMMAND_DOIT;
929
930 /* need to clear DONE bit separately */
931 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
932
933 /* address of the NVRAM to read from */
934 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
935 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
936
937 /* issue a read command */
938 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
939
940 /* adjust timeout for emulation/FPGA */
754a2f52 941 count = BNX2X_NVRAM_TIMEOUT_COUNT;
de0c62db
DK		 942 if (CHIP_REV_IS_SLOW(bp))
943 count *= 100;
944
945 /* wait for completion */
946 *ret_val = 0;
947 rc = -EBUSY;
948 for (i = 0; i < count; i++) {
949 udelay(5);
950 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
951
952 if (val & MCPR_NVM_COMMAND_DONE) {
953 val = REG_RD(bp, MCP_REG_MCPR_NVM_READ);
954 /* we read nvram data in cpu order
955 * but ethtool sees it as an array of bytes
956 * converting to big-endian will do the work */
957 *ret_val = cpu_to_be32(val);
958 rc = 0;
959 break;
960 }
961 }
962
963 return rc;
964}
965
966static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
967 int buf_size)
968{
969 int rc;
970 u32 cmd_flags;
971 __be32 val;
972
973 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
974 DP(BNX2X_MSG_NVM,
975 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
976 offset, buf_size);
977 return -EINVAL;
978 }
979
980 if (offset + buf_size > bp->common.flash_size) {
981 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
982 " buf_size (0x%x) > flash_size (0x%x)\n",
983 offset, buf_size, bp->common.flash_size);
984 return -EINVAL;
985 }
986
987 /* request access to nvram interface */
988 rc = bnx2x_acquire_nvram_lock(bp);
989 if (rc)
990 return rc;
991
992 /* enable access to nvram interface */
993 bnx2x_enable_nvram_access(bp);
994
995 /* read the first word(s) */
996 cmd_flags = MCPR_NVM_COMMAND_FIRST;
997 while ((buf_size > sizeof(u32)) && (rc == 0)) {
998 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
999 memcpy(ret_buf, &val, 4);
1000
1001 /* advance to the next dword */
1002 offset += sizeof(u32);
1003 ret_buf += sizeof(u32);
1004 buf_size -= sizeof(u32);
1005 cmd_flags = 0;
1006 }
1007
1008 if (rc == 0) {
1009 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1010 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1011 memcpy(ret_buf, &val, 4);
1012 }
1013
1014 /* disable access to nvram interface */
1015 bnx2x_disable_nvram_access(bp);
1016 bnx2x_release_nvram_lock(bp);
1017
1018 return rc;
1019}
1020
1021static int bnx2x_get_eeprom(struct net_device *dev,
1022 struct ethtool_eeprom *eeprom, u8 *eebuf)
1023{
1024 struct bnx2x *bp = netdev_priv(dev);
1025 int rc;
1026
1027 if (!netif_running(dev))
1028 return -EAGAIN;
1029
1030 DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1031 DP_LEVEL " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
1032 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1033 eeprom->len, eeprom->len);
1034
1035 /* parameters already validated in ethtool_get_eeprom */
1036
1037 rc = bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
1038
1039 return rc;
1040}
1041
1042static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
1043 u32 cmd_flags)
1044{
1045 int count, i, rc;
1046
1047 /* build the command word */
1048 cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
1049
1050 /* need to clear DONE bit separately */
1051 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1052
1053 /* write the data */
1054 REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val);
1055
1056 /* address of the NVRAM to write to */
1057 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1058 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1059
1060 /* issue the write command */
1061 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1062
1063 /* adjust timeout for emulation/FPGA */
754a2f52 1064 count = BNX2X_NVRAM_TIMEOUT_COUNT;
de0c62db
DK		 1065 if (CHIP_REV_IS_SLOW(bp))
1066 count *= 100;
1067
1068 /* wait for completion */
1069 rc = -EBUSY;
1070 for (i = 0; i < count; i++) {
1071 udelay(5);
1072 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1073 if (val & MCPR_NVM_COMMAND_DONE) {
1074 rc = 0;
1075 break;
1076 }
1077 }
1078
1079 return rc;
1080}
1081
1082#define BYTE_OFFSET(offset) (8 * (offset & 0x03))
1083
1084static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
1085 int buf_size)
1086{
1087 int rc;
1088 u32 cmd_flags;
1089 u32 align_offset;
1090 __be32 val;
1091
1092 if (offset + buf_size > bp->common.flash_size) {
1093 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
1094 " buf_size (0x%x) > flash_size (0x%x)\n",
1095 offset, buf_size, bp->common.flash_size);
1096 return -EINVAL;
1097 }
1098
1099 /* request access to nvram interface */
1100 rc = bnx2x_acquire_nvram_lock(bp);
1101 if (rc)
1102 return rc;
1103
1104 /* enable access to nvram interface */
1105 bnx2x_enable_nvram_access(bp);
1106
1107 cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
1108 align_offset = (offset & ~0x03);
1109 rc = bnx2x_nvram_read_dword(bp, align_offset, &val, cmd_flags);
1110
1111 if (rc == 0) {
1112 val &= ~(0xff << BYTE_OFFSET(offset));
1113 val |= (*data_buf << BYTE_OFFSET(offset));
1114
1115 /* nvram data is returned as an array of bytes
1116 * convert it back to cpu order */
1117 val = be32_to_cpu(val);
1118
1119 rc = bnx2x_nvram_write_dword(bp, align_offset, val,
1120 cmd_flags);
1121 }
1122
1123 /* disable access to nvram interface */
1124 bnx2x_disable_nvram_access(bp);
1125 bnx2x_release_nvram_lock(bp);
1126
1127 return rc;
1128}
1129
1130static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
1131 int buf_size)
1132{
1133 int rc;
1134 u32 cmd_flags;
1135 u32 val;
1136 u32 written_so_far;
1137
1138 if (buf_size == 1) /* ethtool */
1139 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
1140
1141 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1142 DP(BNX2X_MSG_NVM,
1143 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
1144 offset, buf_size);
1145 return -EINVAL;
1146 }
1147
1148 if (offset + buf_size > bp->common.flash_size) {
1149 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
1150 " buf_size (0x%x) > flash_size (0x%x)\n",
1151 offset, buf_size, bp->common.flash_size);
1152 return -EINVAL;
1153 }
1154
1155 /* request access to nvram interface */
1156 rc = bnx2x_acquire_nvram_lock(bp);
1157 if (rc)
1158 return rc;
1159
1160 /* enable access to nvram interface */
1161 bnx2x_enable_nvram_access(bp);
1162
1163 written_so_far = 0;
1164 cmd_flags = MCPR_NVM_COMMAND_FIRST;
1165 while ((written_so_far < buf_size) && (rc == 0)) {
1166 if (written_so_far == (buf_size - sizeof(u32)))
1167 cmd_flags |= MCPR_NVM_COMMAND_LAST;
754a2f52 1168 else if (((offset + 4) % BNX2X_NVRAM_PAGE_SIZE) == 0)
de0c62db 1169 cmd_flags |= MCPR_NVM_COMMAND_LAST;
754a2f52 1170 else if ((offset % BNX2X_NVRAM_PAGE_SIZE) == 0)
de0c62db
DK		 1171 cmd_flags |= MCPR_NVM_COMMAND_FIRST;
1172
1173 memcpy(&val, data_buf, 4);
1174
1175 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
1176
1177 /* advance to the next dword */
1178 offset += sizeof(u32);
1179 data_buf += sizeof(u32);
1180 written_so_far += sizeof(u32);
1181 cmd_flags = 0;
1182 }
1183
1184 /* disable access to nvram interface */
1185 bnx2x_disable_nvram_access(bp);
1186 bnx2x_release_nvram_lock(bp);
1187
1188 return rc;
1189}
1190
1191static int bnx2x_set_eeprom(struct net_device *dev,
1192 struct ethtool_eeprom *eeprom, u8 *eebuf)
1193{
1194 struct bnx2x *bp = netdev_priv(dev);
1195 int port = BP_PORT(bp);
1196 int rc = 0;
e10bc84d 1197 u32 ext_phy_config;
de0c62db
DK		 1198 if (!netif_running(dev))
1199 return -EAGAIN;
1200
1201 DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1202 DP_LEVEL " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
1203 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1204 eeprom->len, eeprom->len);
1205
1206 /* parameters already validated in ethtool_set_eeprom */
1207
1208 /* PHY eeprom can be accessed only by the PMF */
1209 if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) &&
1210 !bp->port.pmf)
1211 return -EINVAL;
1212
e10bc84d
YR		 1213 ext_phy_config =
1214 SHMEM_RD(bp,
1215 dev_info.port_hw_config[port].external_phy_config);
1216
de0c62db
DK		 1217 if (eeprom->magic == 0x50485950) {
1218 /* 'PHYP' (0x50485950): prepare phy for FW upgrade */
1219 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1220
1221 bnx2x_acquire_phy_lock(bp);
1222 rc |= bnx2x_link_reset(&bp->link_params,
1223 &bp->link_vars, 0);
e10bc84d 1224 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
de0c62db
DK		 1225 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101)
1226 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1227 MISC_REGISTERS_GPIO_HIGH, port);
1228 bnx2x_release_phy_lock(bp);
1229 bnx2x_link_report(bp);
1230
1231 } else if (eeprom->magic == 0x50485952) {
1232 /* 'PHYR' (0x50485952): re-init link after FW upgrade */
1233 if (bp->state == BNX2X_STATE_OPEN) {
1234 bnx2x_acquire_phy_lock(bp);
1235 rc |= bnx2x_link_reset(&bp->link_params,
1236 &bp->link_vars, 1);
1237
1238 rc |= bnx2x_phy_init(&bp->link_params,
1239 &bp->link_vars);
1240 bnx2x_release_phy_lock(bp);
1241 bnx2x_calc_fc_adv(bp);
1242 }
1243 } else if (eeprom->magic == 0x53985943) {
1244 /* 'PHYC' (0x53985943): PHY FW upgrade completed */
e10bc84d 1245 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
de0c62db 1246 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) {
de0c62db
DK		 1247
1248 /* DSP Remove Download Mode */
1249 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1250 MISC_REGISTERS_GPIO_LOW, port);
1251
1252 bnx2x_acquire_phy_lock(bp);
1253
e10bc84d
YR		 1254 bnx2x_sfx7101_sp_sw_reset(bp,
1255 &bp->link_params.phy[EXT_PHY1]);
de0c62db
DK		 1256
1257 /* wait 0.5 sec to allow it to run */
1258 msleep(500);
1259 bnx2x_ext_phy_hw_reset(bp, port);
1260 msleep(500);
1261 bnx2x_release_phy_lock(bp);
1262 }
1263 } else
1264 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
1265
1266 return rc;
1267}
f85582f8 1268
de0c62db
DK		 1269static int bnx2x_get_coalesce(struct net_device *dev,
1270 struct ethtool_coalesce *coal)
1271{
1272 struct bnx2x *bp = netdev_priv(dev);
1273
1274 memset(coal, 0, sizeof(struct ethtool_coalesce));
1275
1276 coal->rx_coalesce_usecs = bp->rx_ticks;
1277 coal->tx_coalesce_usecs = bp->tx_ticks;
1278
1279 return 0;
1280}
1281
1282static int bnx2x_set_coalesce(struct net_device *dev,
1283 struct ethtool_coalesce *coal)
1284{
1285 struct bnx2x *bp = netdev_priv(dev);
1286
1287 bp->rx_ticks = (u16)coal->rx_coalesce_usecs;
1288 if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT)
1289 bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT;
1290
1291 bp->tx_ticks = (u16)coal->tx_coalesce_usecs;
1292 if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT)
1293 bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT;
1294
1295 if (netif_running(dev))
1296 bnx2x_update_coalesce(bp);
1297
1298 return 0;
1299}
1300
1301static void bnx2x_get_ringparam(struct net_device *dev,
1302 struct ethtool_ringparam *ering)
1303{
1304 struct bnx2x *bp = netdev_priv(dev);
1305
1306 ering->rx_max_pending = MAX_RX_AVAIL;
1307 ering->rx_mini_max_pending = 0;
1308 ering->rx_jumbo_max_pending = 0;
1309
25141580
DK		 1310 if (bp->rx_ring_size)
1311 ering->rx_pending = bp->rx_ring_size;
1312 else
c2188952 1313 ering->rx_pending = MAX_RX_AVAIL;
25141580 1314
de0c62db
DK		 1315 ering->rx_mini_pending = 0;
1316 ering->rx_jumbo_pending = 0;
1317
1318 ering->tx_max_pending = MAX_TX_AVAIL;
1319 ering->tx_pending = bp->tx_ring_size;
1320}
1321
1322static int bnx2x_set_ringparam(struct net_device *dev,
1323 struct ethtool_ringparam *ering)
1324{
1325 struct bnx2x *bp = netdev_priv(dev);
de0c62db
DK		 1326
1327 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1328 printk(KERN_ERR "Handling parity error recovery. Try again later\n");
1329 return -EAGAIN;
1330 }
1331
1332 if ((ering->rx_pending > MAX_RX_AVAIL) ||
b3b83c3f
DK		 1333 (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA :
1334 MIN_RX_SIZE_TPA)) ||
de0c62db
DK		 1335 (ering->tx_pending > MAX_TX_AVAIL) ||
1336 (ering->tx_pending <= MAX_SKB_FRAGS + 4))
1337 return -EINVAL;
1338
1339 bp->rx_ring_size = ering->rx_pending;
1340 bp->tx_ring_size = ering->tx_pending;
1341
a9fccec7 1342 return bnx2x_reload_if_running(dev);
de0c62db
DK		 1343}
1344
1345static void bnx2x_get_pauseparam(struct net_device *dev,
1346 struct ethtool_pauseparam *epause)
1347{
1348 struct bnx2x *bp = netdev_priv(dev);
a22f0788
YR		 1349 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
1350 epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] ==
1351 BNX2X_FLOW_CTRL_AUTO);
de0c62db
DK		 1352
1353 epause->rx_pause = ((bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_RX) ==
1354 BNX2X_FLOW_CTRL_RX);
1355 epause->tx_pause = ((bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) ==
1356 BNX2X_FLOW_CTRL_TX);
1357
1358 DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n"
1359 DP_LEVEL " autoneg %d rx_pause %d tx_pause %d\n",
1360 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1361}
1362
1363static int bnx2x_set_pauseparam(struct net_device *dev,
1364 struct ethtool_pauseparam *epause)
1365{
1366 struct bnx2x *bp = netdev_priv(dev);
a22f0788 1367 u32 cfg_idx = bnx2x_get_link_cfg_idx(bp);
fb3bff17 1368 if (IS_MF(bp))
de0c62db
DK		 1369 return 0;
1370
1371 DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n"
1372 DP_LEVEL " autoneg %d rx_pause %d tx_pause %d\n",
1373 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1374
a22f0788 1375 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO;
de0c62db
DK		 1376
1377 if (epause->rx_pause)
a22f0788 1378 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX;
de0c62db
DK		 1379
1380 if (epause->tx_pause)
a22f0788 1381 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX;
de0c62db 1382
a22f0788
YR		 1383 if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO)
1384 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE;
de0c62db
DK		 1385
1386 if (epause->autoneg) {
a22f0788 1387 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
de0c62db
DK		 1388 DP(NETIF_MSG_LINK, "autoneg not supported\n");
1389 return -EINVAL;
1390 }
1391
a22f0788
YR		 1392 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) {
1393 bp->link_params.req_flow_ctrl[cfg_idx] =
1394 BNX2X_FLOW_CTRL_AUTO;
1395 }
de0c62db
DK		 1396 }
1397
1398 DP(NETIF_MSG_LINK,
a22f0788 1399 "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]);
de0c62db
DK		 1400
1401 if (netif_running(dev)) {
1402 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1403 bnx2x_link_set(bp);
1404 }
1405
1406 return 0;
1407}
1408
de0c62db
DK		 1409static const struct {
1410 char string[ETH_GSTRING_LEN];
1411} bnx2x_tests_str_arr[BNX2X_NUM_TESTS] = {
1412 { "register_test (offline)" },
1413 { "memory_test (offline)" },
1414 { "loopback_test (offline)" },
1415 { "nvram_test (online)" },
1416 { "interrupt_test (online)" },
1417 { "link_test (online)" },
1418 { "idle check (online)" }
1419};
1420
619c5cb6
VZ		 1421enum {
1422 BNX2X_CHIP_E1_OFST = 0,
1423 BNX2X_CHIP_E1H_OFST,
1424 BNX2X_CHIP_E2_OFST,
1425 BNX2X_CHIP_E3_OFST,
1426 BNX2X_CHIP_E3B0_OFST,
1427 BNX2X_CHIP_MAX_OFST
1428};
1429
1430#define BNX2X_CHIP_MASK_E1 (1 << BNX2X_CHIP_E1_OFST)
1431#define BNX2X_CHIP_MASK_E1H (1 << BNX2X_CHIP_E1H_OFST)
1432#define BNX2X_CHIP_MASK_E2 (1 << BNX2X_CHIP_E2_OFST)
1433#define BNX2X_CHIP_MASK_E3 (1 << BNX2X_CHIP_E3_OFST)
1434#define BNX2X_CHIP_MASK_E3B0 (1 << BNX2X_CHIP_E3B0_OFST)
1435
1436#define BNX2X_CHIP_MASK_ALL ((1 << BNX2X_CHIP_MAX_OFST) - 1)
1437#define BNX2X_CHIP_MASK_E1X (BNX2X_CHIP_MASK_E1 | BNX2X_CHIP_MASK_E1H)
1438
de0c62db
DK		 1439static int bnx2x_test_registers(struct bnx2x *bp)
1440{
1441 int idx, i, rc = -ENODEV;
619c5cb6 1442 u32 wr_val = 0, hw;
de0c62db
DK		 1443 int port = BP_PORT(bp);
1444 static const struct {
619c5cb6 1445 u32 hw;
de0c62db
DK		 1446 u32 offset0;
1447 u32 offset1;
1448 u32 mask;
1449 } reg_tbl[] = {
619c5cb6
VZ		 1450/* 0 */ { BNX2X_CHIP_MASK_ALL,
1451 BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff },
1452 { BNX2X_CHIP_MASK_ALL,
1453 DORQ_REG_DB_ADDR0, 4, 0xffffffff },
1454 { BNX2X_CHIP_MASK_E1X,
1455 HC_REG_AGG_INT_0, 4, 0x000003ff },
1456 { BNX2X_CHIP_MASK_ALL,
1457 PBF_REG_MAC_IF0_ENABLE, 4, 0x00000001 },
1458 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2 | BNX2X_CHIP_MASK_E3,
1459 PBF_REG_P0_INIT_CRD, 4, 0x000007ff },
1460 { BNX2X_CHIP_MASK_E3B0,
1461 PBF_REG_INIT_CRD_Q0, 4, 0x000007ff },
1462 { BNX2X_CHIP_MASK_ALL,
1463 PRS_REG_CID_PORT_0, 4, 0x00ffffff },
1464 { BNX2X_CHIP_MASK_ALL,
1465 PXP2_REG_PSWRQ_CDU0_L2P, 4, 0x000fffff },
1466 { BNX2X_CHIP_MASK_ALL,
1467 PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
1468 { BNX2X_CHIP_MASK_ALL,
1469 PXP2_REG_PSWRQ_TM0_L2P, 4, 0x000fffff },
1470/* 10 */ { BNX2X_CHIP_MASK_ALL,
1471 PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
1472 { BNX2X_CHIP_MASK_ALL,
1473 PXP2_REG_PSWRQ_TSDM0_L2P, 4, 0x000fffff },
1474 { BNX2X_CHIP_MASK_ALL,
1475 QM_REG_CONNNUM_0, 4, 0x000fffff },
1476 { BNX2X_CHIP_MASK_ALL,
1477 TM_REG_LIN0_MAX_ACTIVE_CID, 4, 0x0003ffff },
1478 { BNX2X_CHIP_MASK_ALL,
1479 SRC_REG_KEYRSS0_0, 40, 0xffffffff },
1480 { BNX2X_CHIP_MASK_ALL,
1481 SRC_REG_KEYRSS0_7, 40, 0xffffffff },
1482 { BNX2X_CHIP_MASK_ALL,
1483 XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 },
1484 { BNX2X_CHIP_MASK_ALL,
1485 XCM_REG_WU_DA_CNT_CMD00, 4, 0x00000003 },
1486 { BNX2X_CHIP_MASK_ALL,
1487 XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 4, 0x000000ff },
1488 { BNX2X_CHIP_MASK_ALL,
1489 NIG_REG_LLH0_T_BIT, 4, 0x00000001 },
1490/* 20 */ { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1491 NIG_REG_EMAC0_IN_EN, 4, 0x00000001 },
1492 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1493 NIG_REG_BMAC0_IN_EN, 4, 0x00000001 },
1494 { BNX2X_CHIP_MASK_ALL,
1495 NIG_REG_XCM0_OUT_EN, 4, 0x00000001 },
1496 { BNX2X_CHIP_MASK_ALL,
1497 NIG_REG_BRB0_OUT_EN, 4, 0x00000001 },
1498 { BNX2X_CHIP_MASK_ALL,
1499 NIG_REG_LLH0_XCM_MASK, 4, 0x00000007 },
1500 { BNX2X_CHIP_MASK_ALL,
1501 NIG_REG_LLH0_ACPI_PAT_6_LEN, 68, 0x000000ff },
1502 { BNX2X_CHIP_MASK_ALL,
1503 NIG_REG_LLH0_ACPI_PAT_0_CRC, 68, 0xffffffff },
1504 { BNX2X_CHIP_MASK_ALL,
1505 NIG_REG_LLH0_DEST_MAC_0_0, 160, 0xffffffff },
1506 { BNX2X_CHIP_MASK_ALL,
1507 NIG_REG_LLH0_DEST_IP_0_1, 160, 0xffffffff },
1508 { BNX2X_CHIP_MASK_ALL,
1509 NIG_REG_LLH0_IPV4_IPV6_0, 160, 0x00000001 },
1510/* 30 */ { BNX2X_CHIP_MASK_ALL,
1511 NIG_REG_LLH0_DEST_UDP_0, 160, 0x0000ffff },
1512 { BNX2X_CHIP_MASK_ALL,
1513 NIG_REG_LLH0_DEST_TCP_0, 160, 0x0000ffff },
1514 { BNX2X_CHIP_MASK_ALL,
1515 NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff },
1516 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1517 NIG_REG_XGXS_SERDES0_MODE_SEL, 4, 0x00000001 },
1518 { BNX2X_CHIP_MASK_ALL,
1519 NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001},
1520 { BNX2X_CHIP_MASK_ALL,
1521 NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff },
1522 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1523 NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 },
1524 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
1525 NIG_REG_SERDES0_CTRL_PHY_ADDR, 16, 0x0000001f },
1526
1527 { BNX2X_CHIP_MASK_ALL, 0xffffffff, 0, 0x00000000 }
de0c62db
DK		 1528 };
1529
1530 if (!netif_running(bp->dev))
1531 return rc;
1532
619c5cb6
VZ		 1533 if (CHIP_IS_E1(bp))
1534 hw = BNX2X_CHIP_MASK_E1;
1535 else if (CHIP_IS_E1H(bp))
1536 hw = BNX2X_CHIP_MASK_E1H;
1537 else if (CHIP_IS_E2(bp))
1538 hw = BNX2X_CHIP_MASK_E2;
1539 else if (CHIP_IS_E3B0(bp))
1540 hw = BNX2X_CHIP_MASK_E3B0;
1541 else /* e3 A0 */
1542 hw = BNX2X_CHIP_MASK_E3;
1543
de0c62db
DK		 1544 /* Repeat the test twice:
1545 First by writing 0x00000000, second by writing 0xffffffff */
1546 for (idx = 0; idx < 2; idx++) {
1547
1548 switch (idx) {
1549 case 0:
1550 wr_val = 0;
1551 break;
1552 case 1:
1553 wr_val = 0xffffffff;
1554 break;
1555 }
1556
1557 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
1558 u32 offset, mask, save_val, val;
619c5cb6 1559 if (!(hw & reg_tbl[i].hw))
f2e0899f 1560 continue;
de0c62db
DK		 1561
1562 offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1;
1563 mask = reg_tbl[i].mask;
1564
1565 save_val = REG_RD(bp, offset);
1566
ec6ba945 1567 REG_WR(bp, offset, wr_val & mask);
f85582f8 1568
de0c62db
DK		 1569 val = REG_RD(bp, offset);
1570
1571 /* Restore the original register's value */
1572 REG_WR(bp, offset, save_val);
1573
1574 /* verify value is as expected */
1575 if ((val & mask) != (wr_val & mask)) {
619c5cb6 1576 DP(NETIF_MSG_HW,
de0c62db
DK		 1577 "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n",
1578 offset, val, wr_val, mask);
1579 goto test_reg_exit;
1580 }
1581 }
1582 }
1583
1584 rc = 0;
1585
1586test_reg_exit:
1587 return rc;
1588}
1589
1590static int bnx2x_test_memory(struct bnx2x *bp)
1591{
1592 int i, j, rc = -ENODEV;
619c5cb6 1593 u32 val, index;
de0c62db
DK		 1594 static const struct {
1595 u32 offset;
1596 int size;
1597 } mem_tbl[] = {
1598 { CCM_REG_XX_DESCR_TABLE, CCM_REG_XX_DESCR_TABLE_SIZE },
1599 { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE },
1600 { CFC_REG_LINK_LIST, CFC_REG_LINK_LIST_SIZE },
1601 { DMAE_REG_CMD_MEM, DMAE_REG_CMD_MEM_SIZE },
1602 { TCM_REG_XX_DESCR_TABLE, TCM_REG_XX_DESCR_TABLE_SIZE },
1603 { UCM_REG_XX_DESCR_TABLE, UCM_REG_XX_DESCR_TABLE_SIZE },
1604 { XCM_REG_XX_DESCR_TABLE, XCM_REG_XX_DESCR_TABLE_SIZE },
1605
1606 { 0xffffffff, 0 }
1607 };
619c5cb6 1608
de0c62db
DK		 1609 static const struct {
1610 char *name;
1611 u32 offset;
619c5cb6 1612 u32 hw_mask[BNX2X_CHIP_MAX_OFST];
de0c62db 1613 } prty_tbl[] = {
619c5cb6
VZ		 1614 { "CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS,
1615 {0x3ffc0, 0, 0, 0} },
1616 { "CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS,
1617 {0x2, 0x2, 0, 0} },
1618 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS,
1619 {0, 0, 0, 0} },
1620 { "TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS,
1621 {0x3ffc0, 0, 0, 0} },
1622 { "UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS,
1623 {0x3ffc0, 0, 0, 0} },
1624 { "XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS,
1625 {0x3ffc1, 0, 0, 0} },
1626
1627 { NULL, 0xffffffff, {0, 0, 0, 0} }
de0c62db
DK		 1628 };
1629
1630 if (!netif_running(bp->dev))
1631 return rc;
1632
619c5cb6
VZ		 1633 if (CHIP_IS_E1(bp))
1634 index = BNX2X_CHIP_E1_OFST;
1635 else if (CHIP_IS_E1H(bp))
1636 index = BNX2X_CHIP_E1H_OFST;
1637 else if (CHIP_IS_E2(bp))
1638 index = BNX2X_CHIP_E2_OFST;
1639 else /* e3 */
1640 index = BNX2X_CHIP_E3_OFST;
1641
f2e0899f
DK		 1642 /* pre-Check the parity status */
1643 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
1644 val = REG_RD(bp, prty_tbl[i].offset);
619c5cb6 1645 if (val & ~(prty_tbl[i].hw_mask[index])) {
f2e0899f
DK		 1646 DP(NETIF_MSG_HW,
1647 "%s is 0x%x\n", prty_tbl[i].name, val);
1648 goto test_mem_exit;
1649 }
1650 }
1651
de0c62db
DK		 1652 /* Go through all the memories */
1653 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++)
1654 for (j = 0; j < mem_tbl[i].size; j++)
1655 REG_RD(bp, mem_tbl[i].offset + j*4);
1656
1657 /* Check the parity status */
1658 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
1659 val = REG_RD(bp, prty_tbl[i].offset);
619c5cb6 1660 if (val & ~(prty_tbl[i].hw_mask[index])) {
de0c62db
DK		 1661 DP(NETIF_MSG_HW,
1662 "%s is 0x%x\n", prty_tbl[i].name, val);
1663 goto test_mem_exit;
1664 }
1665 }
1666
1667 rc = 0;
1668
1669test_mem_exit:
1670 return rc;
1671}
1672
a22f0788 1673static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes)
de0c62db 1674{
f2e0899f 1675 int cnt = 1400;
de0c62db 1676
619c5cb6 1677 if (link_up) {
a22f0788 1678 while (bnx2x_link_test(bp, is_serdes) && cnt--)
619c5cb6
VZ		 1679 msleep(20);
1680
1681 if (cnt <= 0 && bnx2x_link_test(bp, is_serdes))
1682 DP(NETIF_MSG_LINK, "Timeout waiting for link up\n");
1683 }
de0c62db
DK		 1684}
1685
619c5cb6 1686static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode)
de0c62db
DK		 1687{
1688 unsigned int pkt_size, num_pkts, i;
1689 struct sk_buff *skb;
1690 unsigned char *packet;
1691 struct bnx2x_fastpath *fp_rx = &bp->fp[0];
1692 struct bnx2x_fastpath *fp_tx = &bp->fp[0];
6383c0b3 1693 struct bnx2x_fp_txdata *txdata = &fp_tx->txdata[0];
de0c62db
DK		 1694 u16 tx_start_idx, tx_idx;
1695 u16 rx_start_idx, rx_idx;
619c5cb6 1696 u16 pkt_prod, bd_prod, rx_comp_cons;
de0c62db
DK		 1697 struct sw_tx_bd *tx_buf;
1698 struct eth_tx_start_bd *tx_start_bd;
f2e0899f
DK		 1699 struct eth_tx_parse_bd_e1x *pbd_e1x = NULL;
1700 struct eth_tx_parse_bd_e2 *pbd_e2 = NULL;
de0c62db
DK		 1701 dma_addr_t mapping;
1702 union eth_rx_cqe *cqe;
619c5cb6 1703 u8 cqe_fp_flags, cqe_fp_type;
de0c62db
DK		 1704 struct sw_rx_bd *rx_buf;
1705 u16 len;
1706 int rc = -ENODEV;
1707
1708 /* check the loopback mode */
1709 switch (loopback_mode) {
1710 case BNX2X_PHY_LOOPBACK:
de6eae1f 1711 if (bp->link_params.loopback_mode != LOOPBACK_XGXS)
de0c62db
DK		 1712 return -EINVAL;
1713 break;
1714 case BNX2X_MAC_LOOPBACK:
619c5cb6
VZ		 1715 bp->link_params.loopback_mode = CHIP_IS_E3(bp) ?
1716 LOOPBACK_XMAC : LOOPBACK_BMAC;
de0c62db
DK		 1717 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
1718 break;
1719 default:
1720 return -EINVAL;
1721 }
1722
1723 /* prepare the loopback packet */
1724 pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ?
1725 bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN);
a8c94b91 1726 skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size);
de0c62db
DK		 1727 if (!skb) {
1728 rc = -ENOMEM;
1729 goto test_loopback_exit;
1730 }
1731 packet = skb_put(skb, pkt_size);
1732 memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
1733 memset(packet + ETH_ALEN, 0, ETH_ALEN);
1734 memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN));
1735 for (i = ETH_HLEN; i < pkt_size; i++)
1736 packet[i] = (unsigned char) (i & 0xff);
619c5cb6
VZ		 1737 mapping = dma_map_single(&bp->pdev->dev, skb->data,
1738 skb_headlen(skb), DMA_TO_DEVICE);
1739 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
1740 rc = -ENOMEM;
1741 dev_kfree_skb(skb);
1742 BNX2X_ERR("Unable to map SKB\n");
1743 goto test_loopback_exit;
1744 }
de0c62db
DK		 1745
1746 /* send the loopback packet */
1747 num_pkts = 0;
6383c0b3 1748 tx_start_idx = le16_to_cpu(*txdata->tx_cons_sb);
de0c62db
DK		 1749 rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
1750
6383c0b3
AE		 1751 pkt_prod = txdata->tx_pkt_prod++;
1752 tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)];
1753 tx_buf->first_bd = txdata->tx_bd_prod;
de0c62db
DK		 1754 tx_buf->skb = skb;
1755 tx_buf->flags = 0;
1756
6383c0b3
AE		 1757 bd_prod = TX_BD(txdata->tx_bd_prod);
1758 tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd;
de0c62db
DK		 1759 tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
1760 tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
1761 tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */
1762 tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
523224a3 1763 tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod);
de0c62db 1764 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
523224a3
DK		 1765 SET_FLAG(tx_start_bd->general_data,
1766 ETH_TX_START_BD_ETH_ADDR_TYPE,
1767 UNICAST_ADDRESS);
1768 SET_FLAG(tx_start_bd->general_data,
1769 ETH_TX_START_BD_HDR_NBDS,
1770 1);
de0c62db
DK		 1771
1772 /* turn on parsing and get a BD */
1773 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
f85582f8 1774
6383c0b3
AE		 1775 pbd_e1x = &txdata->tx_desc_ring[bd_prod].parse_bd_e1x;
1776 pbd_e2 = &txdata->tx_desc_ring[bd_prod].parse_bd_e2;
de0c62db 1777
f2e0899f 1778 memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
523224a3 1779 memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
de0c62db
DK		 1780
1781 wmb();
1782
6383c0b3 1783 txdata->tx_db.data.prod += 2;
de0c62db 1784 barrier();
6383c0b3 1785 DOORBELL(bp, txdata->cid, txdata->tx_db.raw);
de0c62db
DK		 1786
1787 mmiowb();
619c5cb6 1788 barrier();
de0c62db
DK		 1789
1790 num_pkts++;
6383c0b3 1791 txdata->tx_bd_prod += 2; /* start + pbd */
de0c62db
DK		 1792
1793 udelay(100);
1794
6383c0b3 1795 tx_idx = le16_to_cpu(*txdata->tx_cons_sb);
de0c62db
DK		 1796 if (tx_idx != tx_start_idx + num_pkts)
1797 goto test_loopback_exit;
1798
f2e0899f
DK		 1799 /* Unlike HC IGU won't generate an interrupt for status block
1800 * updates that have been performed while interrupts were
1801 * disabled.
1802 */
e1210d12
ED		 1803 if (bp->common.int_block == INT_BLOCK_IGU) {
1804 /* Disable local BHes to prevent a dead-lock situation between
1805 * sch_direct_xmit() and bnx2x_run_loopback() (calling
1806 * bnx2x_tx_int()), as both are taking netif_tx_lock().
1807 */
1808 local_bh_disable();
6383c0b3 1809 bnx2x_tx_int(bp, txdata);
e1210d12
ED		 1810 local_bh_enable();
1811 }
f2e0899f 1812
de0c62db
DK		 1813 rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
1814 if (rx_idx != rx_start_idx + num_pkts)
1815 goto test_loopback_exit;
1816
619c5cb6
VZ		 1817 rx_comp_cons = le16_to_cpu(fp_rx->rx_comp_cons);
1818 cqe = &fp_rx->rx_comp_ring[RCQ_BD(rx_comp_cons)];
de0c62db 1819 cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
619c5cb6
VZ		 1820 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
1821 if (!CQE_TYPE_FAST(cqe_fp_type) || (cqe_fp_flags & ETH_RX_ERROR_FALGS))
de0c62db
DK		 1822 goto test_loopback_rx_exit;
1823
1824 len = le16_to_cpu(cqe->fast_path_cqe.pkt_len);
1825 if (len != pkt_size)
1826 goto test_loopback_rx_exit;
1827
1828 rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)];
9924cafc 1829 dma_sync_single_for_cpu(&bp->pdev->dev,
619c5cb6
VZ		 1830 dma_unmap_addr(rx_buf, mapping),
1831 fp_rx->rx_buf_size, DMA_FROM_DEVICE);
de0c62db
DK		 1832 skb = rx_buf->skb;
1833 skb_reserve(skb, cqe->fast_path_cqe.placement_offset);
1834 for (i = ETH_HLEN; i < pkt_size; i++)
1835 if (*(skb->data + i) != (unsigned char) (i & 0xff))
1836 goto test_loopback_rx_exit;
1837
1838 rc = 0;
1839
1840test_loopback_rx_exit:
1841
1842 fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons);
1843 fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod);
1844 fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons);
1845 fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod);
1846
1847 /* Update producers */
1848 bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod,
1849 fp_rx->rx_sge_prod);
1850
1851test_loopback_exit:
1852 bp->link_params.loopback_mode = LOOPBACK_NONE;
1853
1854 return rc;
1855}
1856
619c5cb6 1857static int bnx2x_test_loopback(struct bnx2x *bp)
de0c62db
DK		 1858{
1859 int rc = 0, res;
1860
1861 if (BP_NOMCP(bp))
1862 return rc;
1863
1864 if (!netif_running(bp->dev))
1865 return BNX2X_LOOPBACK_FAILED;
1866
1867 bnx2x_netif_stop(bp, 1);
1868 bnx2x_acquire_phy_lock(bp);
1869
619c5cb6 1870 res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK);
de0c62db
DK		 1871 if (res) {
1872 DP(NETIF_MSG_PROBE, " PHY loopback failed (res %d)\n", res);
1873 rc |= BNX2X_PHY_LOOPBACK_FAILED;
1874 }
1875
619c5cb6 1876 res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK);
de0c62db
DK		 1877 if (res) {
1878 DP(NETIF_MSG_PROBE, " MAC loopback failed (res %d)\n", res);
1879 rc |= BNX2X_MAC_LOOPBACK_FAILED;
1880 }
1881
1882 bnx2x_release_phy_lock(bp);
1883 bnx2x_netif_start(bp);
1884
1885 return rc;
1886}
1887
1888#define CRC32_RESIDUAL 0xdebb20e3
1889
1890static int bnx2x_test_nvram(struct bnx2x *bp)
1891{
1892 static const struct {
1893 int offset;
1894 int size;
1895 } nvram_tbl[] = {
1896 { 0, 0x14 }, /* bootstrap */
1897 { 0x14, 0xec }, /* dir */
1898 { 0x100, 0x350 }, /* manuf_info */
1899 { 0x450, 0xf0 }, /* feature_info */
1900 { 0x640, 0x64 }, /* upgrade_key_info */
de0c62db 1901 { 0x708, 0x70 }, /* manuf_key_info */
de0c62db
DK		 1902 { 0, 0 }
1903 };
1904 __be32 buf[0x350 / 4];
1905 u8 *data = (u8 *)buf;
1906 int i, rc;
1907 u32 magic, crc;
1908
1909 if (BP_NOMCP(bp))
1910 return 0;
1911
1912 rc = bnx2x_nvram_read(bp, 0, data, 4);
1913 if (rc) {
1914 DP(NETIF_MSG_PROBE, "magic value read (rc %d)\n", rc);
1915 goto test_nvram_exit;
1916 }
1917
1918 magic = be32_to_cpu(buf[0]);
1919 if (magic != 0x669955aa) {
1920 DP(NETIF_MSG_PROBE, "magic value (0x%08x)\n", magic);
1921 rc = -ENODEV;
1922 goto test_nvram_exit;
1923 }
1924
1925 for (i = 0; nvram_tbl[i].size; i++) {
1926
1927 rc = bnx2x_nvram_read(bp, nvram_tbl[i].offset, data,
1928 nvram_tbl[i].size);
1929 if (rc) {
1930 DP(NETIF_MSG_PROBE,
1931 "nvram_tbl[%d] read data (rc %d)\n", i, rc);
1932 goto test_nvram_exit;
1933 }
1934
1935 crc = ether_crc_le(nvram_tbl[i].size, data);
1936 if (crc != CRC32_RESIDUAL) {
1937 DP(NETIF_MSG_PROBE,
1938 "nvram_tbl[%d] crc value (0x%08x)\n", i, crc);
1939 rc = -ENODEV;
1940 goto test_nvram_exit;
1941 }
1942 }
1943
1944test_nvram_exit:
1945 return rc;
1946}
1947
619c5cb6 1948/* Send an EMPTY ramrod on the first queue */
de0c62db
DK		 1949static int bnx2x_test_intr(struct bnx2x *bp)
1950{
619c5cb6 1951 struct bnx2x_queue_state_params params = {0};
de0c62db
DK		 1952
1953 if (!netif_running(bp->dev))
1954 return -ENODEV;
1955
619c5cb6
VZ		 1956 params.q_obj = &bp->fp->q_obj;
1957 params.cmd = BNX2X_Q_CMD_EMPTY;
de0c62db 1958
619c5cb6
VZ		 1959 __set_bit(RAMROD_COMP_WAIT, &params.ramrod_flags);
1960
1961 return bnx2x_queue_state_change(bp, &params);
de0c62db
DK		 1962}
1963
1964static void bnx2x_self_test(struct net_device *dev,
1965 struct ethtool_test *etest, u64 *buf)
1966{
1967 struct bnx2x *bp = netdev_priv(dev);
a22f0788 1968 u8 is_serdes;
de0c62db
DK		 1969 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1970 printk(KERN_ERR "Handling parity error recovery. Try again later\n");
1971 etest->flags |= ETH_TEST_FL_FAILED;
1972 return;
1973 }
1974
1975 memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS);
1976
1977 if (!netif_running(dev))
1978 return;
1979
1980 /* offline tests are not supported in MF mode */
fb3bff17 1981 if (IS_MF(bp))
de0c62db 1982 etest->flags &= ~ETH_TEST_FL_OFFLINE;
a22f0788 1983 is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
de0c62db
DK		 1984
1985 if (etest->flags & ETH_TEST_FL_OFFLINE) {
1986 int port = BP_PORT(bp);
1987 u32 val;
1988 u8 link_up;
1989
1990 /* save current value of input enable for TX port IF */
1991 val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4);
1992 /* disable input for TX port IF */
1993 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0);
1994
a22f0788
YR		 1995 link_up = bp->link_vars.link_up;
1996
de0c62db
DK		 1997 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
1998 bnx2x_nic_load(bp, LOAD_DIAG);
1999 /* wait until link state is restored */
619c5cb6 2000 bnx2x_wait_for_link(bp, 1, is_serdes);
de0c62db
DK		 2001
2002 if (bnx2x_test_registers(bp) != 0) {
2003 buf[0] = 1;
2004 etest->flags |= ETH_TEST_FL_FAILED;
2005 }
2006 if (bnx2x_test_memory(bp) != 0) {
2007 buf[1] = 1;
2008 etest->flags |= ETH_TEST_FL_FAILED;
2009 }
f85582f8 2010
619c5cb6 2011 buf[2] = bnx2x_test_loopback(bp);
de0c62db
DK		 2012 if (buf[2] != 0)
2013 etest->flags |= ETH_TEST_FL_FAILED;
2014
2015 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
2016
2017 /* restore input for TX port IF */
2018 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val);
2019
2020 bnx2x_nic_load(bp, LOAD_NORMAL);
2021 /* wait until link state is restored */
a22f0788 2022 bnx2x_wait_for_link(bp, link_up, is_serdes);
de0c62db
DK		 2023 }
2024 if (bnx2x_test_nvram(bp) != 0) {
2025 buf[3] = 1;
2026 etest->flags |= ETH_TEST_FL_FAILED;
2027 }
2028 if (bnx2x_test_intr(bp) != 0) {
2029 buf[4] = 1;
2030 etest->flags |= ETH_TEST_FL_FAILED;
2031 }
633ac363
DK		 2032
2033 if (bnx2x_link_test(bp, is_serdes) != 0) {
2034 buf[5] = 1;
2035 etest->flags |= ETH_TEST_FL_FAILED;
2036 }
de0c62db
DK		 2037
2038#ifdef BNX2X_EXTRA_DEBUG
2039 bnx2x_panic_dump(bp);
2040#endif
2041}
2042
de0c62db
DK		 2043#define IS_PORT_STAT(i) \
2044 ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT)
2045#define IS_FUNC_STAT(i) (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC)
fb3bff17
DK		 2046#define IS_MF_MODE_STAT(bp) \
2047 (IS_MF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS))
de0c62db 2048
619c5cb6
VZ		 2049/* ethtool statistics are displayed for all regular ethernet queues and the
2050 * fcoe L2 queue if not disabled
2051 */
2052static inline int bnx2x_num_stat_queues(struct bnx2x *bp)
2053{
2054 return BNX2X_NUM_ETH_QUEUES(bp);
2055}
2056
de0c62db
DK		 2057static int bnx2x_get_sset_count(struct net_device *dev, int stringset)
2058{
2059 struct bnx2x *bp = netdev_priv(dev);
2060 int i, num_stats;
2061
2062 switch (stringset) {
2063 case ETH_SS_STATS:
2064 if (is_multi(bp)) {
619c5cb6 2065 num_stats = bnx2x_num_stat_queues(bp) *
ec6ba945 2066 BNX2X_NUM_Q_STATS;
fb3bff17 2067 if (!IS_MF_MODE_STAT(bp))
de0c62db
DK		 2068 num_stats += BNX2X_NUM_STATS;
2069 } else {
fb3bff17 2070 if (IS_MF_MODE_STAT(bp)) {
de0c62db
DK		 2071 num_stats = 0;
2072 for (i = 0; i < BNX2X_NUM_STATS; i++)
2073 if (IS_FUNC_STAT(i))
2074 num_stats++;
2075 } else
2076 num_stats = BNX2X_NUM_STATS;
2077 }
2078 return num_stats;
2079
2080 case ETH_SS_TEST:
2081 return BNX2X_NUM_TESTS;
2082
2083 default:
2084 return -EINVAL;
2085 }
2086}
2087
2088static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
2089{
2090 struct bnx2x *bp = netdev_priv(dev);
2091 int i, j, k;
ec6ba945 2092 char queue_name[MAX_QUEUE_NAME_LEN+1];
de0c62db
DK		 2093
2094 switch (stringset) {
2095 case ETH_SS_STATS:
2096 if (is_multi(bp)) {
2097 k = 0;
619c5cb6 2098 for_each_eth_queue(bp, i) {
ec6ba945 2099 memset(queue_name, 0, sizeof(queue_name));
619c5cb6 2100 sprintf(queue_name, "%d", i);
de0c62db 2101 for (j = 0; j < BNX2X_NUM_Q_STATS; j++)
ec6ba945
VZ		 2102 snprintf(buf + (k + j)*ETH_GSTRING_LEN,
2103 ETH_GSTRING_LEN,
2104 bnx2x_q_stats_arr[j].string,
2105 queue_name);
de0c62db
DK		 2106 k += BNX2X_NUM_Q_STATS;
2107 }
fb3bff17 2108 if (IS_MF_MODE_STAT(bp))
de0c62db
DK		 2109 break;
2110 for (j = 0; j < BNX2X_NUM_STATS; j++)
2111 strcpy(buf + (k + j)*ETH_GSTRING_LEN,
2112 bnx2x_stats_arr[j].string);
2113 } else {
2114 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
fb3bff17 2115 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
de0c62db
DK		 2116 continue;
2117 strcpy(buf + j*ETH_GSTRING_LEN,
2118 bnx2x_stats_arr[i].string);
2119 j++;
2120 }
2121 }
2122 break;
2123
2124 case ETH_SS_TEST:
2125 memcpy(buf, bnx2x_tests_str_arr, sizeof(bnx2x_tests_str_arr));
2126 break;
2127 }
2128}
2129
2130static void bnx2x_get_ethtool_stats(struct net_device *dev,
2131 struct ethtool_stats *stats, u64 *buf)
2132{
2133 struct bnx2x *bp = netdev_priv(dev);
2134 u32 *hw_stats, *offset;
2135 int i, j, k;
2136
2137 if (is_multi(bp)) {
2138 k = 0;
619c5cb6 2139 for_each_eth_queue(bp, i) {
de0c62db
DK		 2140 hw_stats = (u32 *)&bp->fp[i].eth_q_stats;
2141 for (j = 0; j < BNX2X_NUM_Q_STATS; j++) {
2142 if (bnx2x_q_stats_arr[j].size == 0) {
2143 /* skip this counter */
2144 buf[k + j] = 0;
2145 continue;
2146 }
2147 offset = (hw_stats +
2148 bnx2x_q_stats_arr[j].offset);
2149 if (bnx2x_q_stats_arr[j].size == 4) {
2150 /* 4-byte counter */
2151 buf[k + j] = (u64) *offset;
2152 continue;
2153 }
2154 /* 8-byte counter */
2155 buf[k + j] = HILO_U64(*offset, *(offset + 1));
2156 }
2157 k += BNX2X_NUM_Q_STATS;
2158 }
fb3bff17 2159 if (IS_MF_MODE_STAT(bp))
de0c62db
DK		 2160 return;
2161 hw_stats = (u32 *)&bp->eth_stats;
2162 for (j = 0; j < BNX2X_NUM_STATS; j++) {
2163 if (bnx2x_stats_arr[j].size == 0) {
2164 /* skip this counter */
2165 buf[k + j] = 0;
2166 continue;
2167 }
2168 offset = (hw_stats + bnx2x_stats_arr[j].offset);
2169 if (bnx2x_stats_arr[j].size == 4) {
2170 /* 4-byte counter */
2171 buf[k + j] = (u64) *offset;
2172 continue;
2173 }
2174 /* 8-byte counter */
2175 buf[k + j] = HILO_U64(*offset, *(offset + 1));
2176 }
2177 } else {
2178 hw_stats = (u32 *)&bp->eth_stats;
2179 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
fb3bff17 2180 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
de0c62db
DK		 2181 continue;
2182 if (bnx2x_stats_arr[i].size == 0) {
2183 /* skip this counter */
2184 buf[j] = 0;
2185 j++;
2186 continue;
2187 }
2188 offset = (hw_stats + bnx2x_stats_arr[i].offset);
2189 if (bnx2x_stats_arr[i].size == 4) {
2190 /* 4-byte counter */
2191 buf[j] = (u64) *offset;
2192 j++;
2193 continue;
2194 }
2195 /* 8-byte counter */
2196 buf[j] = HILO_U64(*offset, *(offset + 1));
2197 j++;
2198 }
2199 }
2200}
2201
32d36134 2202static int bnx2x_set_phys_id(struct net_device *dev,
2203 enum ethtool_phys_id_state state)
de0c62db
DK		 2204{
2205 struct bnx2x *bp = netdev_priv(dev);
de0c62db
DK		 2206
2207 if (!netif_running(dev))
32d36134 2208 return -EAGAIN;
de0c62db
DK		 2209
2210 if (!bp->port.pmf)
32d36134 2211 return -EOPNOTSUPP;
de0c62db 2212
32d36134 2213 switch (state) {
2214 case ETHTOOL_ID_ACTIVE:
fce55922 2215 return 1; /* cycle on/off once per second */
de0c62db 2216
32d36134 2217 case ETHTOOL_ID_ON:
2218 bnx2x_set_led(&bp->link_params, &bp->link_vars,
e1943424 2219 LED_MODE_ON, SPEED_1000);
32d36134 2220 break;
de0c62db 2221
32d36134 2222 case ETHTOOL_ID_OFF:
2223 bnx2x_set_led(&bp->link_params, &bp->link_vars,
e1943424 2224 LED_MODE_FRONT_PANEL_OFF, 0);
de0c62db 2225
32d36134 2226 break;
2227
2228 case ETHTOOL_ID_INACTIVE:
e1943424
DM		 2229 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2230 LED_MODE_OPER,
2231 bp->link_vars.line_speed);
32d36134 2232 }
de0c62db
DK		 2233
2234 return 0;
2235}
2236
ab532cf3
TH		 2237static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
2238 void *rules __always_unused)
2239{
2240 struct bnx2x *bp = netdev_priv(dev);
2241
2242 switch (info->cmd) {
2243 case ETHTOOL_GRXRINGS:
2244 info->data = BNX2X_NUM_ETH_QUEUES(bp);
2245 return 0;
2246
2247 default:
2248 return -EOPNOTSUPP;
2249 }
2250}
2251
2252static int bnx2x_get_rxfh_indir(struct net_device *dev,
2253 struct ethtool_rxfh_indir *indir)
2254{
2255 struct bnx2x *bp = netdev_priv(dev);
2256 size_t copy_size =
619c5cb6
VZ		 2257 min_t(size_t, indir->size, T_ETH_INDIRECTION_TABLE_SIZE);
2258 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0};
2259 size_t i;
ab532cf3
TH		 2260
2261 if (bp->multi_mode == ETH_RSS_MODE_DISABLED)
2262 return -EOPNOTSUPP;
2263
619c5cb6
VZ		 2264 /* Get the current configuration of the RSS indirection table */
2265 bnx2x_get_rss_ind_table(&bp->rss_conf_obj, ind_table);
2266
2267 /*
2268 * We can't use a memcpy() as an internal storage of an
2269 * indirection table is a u8 array while indir->ring_index
2270 * points to an array of u32.
2271 *
2272 * Indirection table contains the FW Client IDs, so we need to
2273 * align the returned table to the Client ID of the leading RSS
2274 * queue.
2275 */
2276 for (i = 0; i < copy_size; i++)
2277 indir->ring_index[i] = ind_table[i] - bp->fp->cl_id;
2278
2279 indir->size = T_ETH_INDIRECTION_TABLE_SIZE;
2280
ab532cf3
TH		 2281 return 0;
2282}
2283
2284static int bnx2x_set_rxfh_indir(struct net_device *dev,
2285 const struct ethtool_rxfh_indir *indir)
2286{
2287 struct bnx2x *bp = netdev_priv(dev);
2288 size_t i;
619c5cb6
VZ		 2289 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0};
2290 u32 num_eth_queues = BNX2X_NUM_ETH_QUEUES(bp);
ab532cf3
TH		 2291
2292 if (bp->multi_mode == ETH_RSS_MODE_DISABLED)
2293 return -EOPNOTSUPP;
2294
619c5cb6
VZ		 2295 /* validate the size */
2296 if (indir->size != T_ETH_INDIRECTION_TABLE_SIZE)
ab532cf3 2297 return -EINVAL;
619c5cb6
VZ		 2298
2299 for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) {
2300 /* validate the indices */
2301 if (indir->ring_index[i] >= num_eth_queues)
ab532cf3 2302 return -EINVAL;
619c5cb6
VZ		 2303 /*
2304 * The same as in bnx2x_get_rxfh_indir: we can't use a memcpy()
2305 * as an internal storage of an indirection table is a u8 array
2306 * while indir->ring_index points to an array of u32.
2307 *
2308 * Indirection table contains the FW Client IDs, so we need to
2309 * align the received table to the Client ID of the leading RSS
2310 * queue
2311 */
2312 ind_table[i] = indir->ring_index[i] + bp->fp->cl_id;
2313 }
ab532cf3 2314
619c5cb6 2315 return bnx2x_config_rss_pf(bp, ind_table, false);
ab532cf3
TH		 2316}
2317
de0c62db
DK		 2318static const struct ethtool_ops bnx2x_ethtool_ops = {
2319 .get_settings = bnx2x_get_settings,
2320 .set_settings = bnx2x_set_settings,
2321 .get_drvinfo = bnx2x_get_drvinfo,
2322 .get_regs_len = bnx2x_get_regs_len,
2323 .get_regs = bnx2x_get_regs,
2324 .get_wol = bnx2x_get_wol,
2325 .set_wol = bnx2x_set_wol,
2326 .get_msglevel = bnx2x_get_msglevel,
2327 .set_msglevel = bnx2x_set_msglevel,
2328 .nway_reset = bnx2x_nway_reset,
2329 .get_link = bnx2x_get_link,
2330 .get_eeprom_len = bnx2x_get_eeprom_len,
2331 .get_eeprom = bnx2x_get_eeprom,
2332 .set_eeprom = bnx2x_set_eeprom,
2333 .get_coalesce = bnx2x_get_coalesce,
2334 .set_coalesce = bnx2x_set_coalesce,
2335 .get_ringparam = bnx2x_get_ringparam,
2336 .set_ringparam = bnx2x_set_ringparam,
2337 .get_pauseparam = bnx2x_get_pauseparam,
2338 .set_pauseparam = bnx2x_set_pauseparam,
de0c62db
DK		 2339 .self_test = bnx2x_self_test,
2340 .get_sset_count = bnx2x_get_sset_count,
2341 .get_strings = bnx2x_get_strings,
32d36134 2342 .set_phys_id = bnx2x_set_phys_id,
de0c62db 2343 .get_ethtool_stats = bnx2x_get_ethtool_stats,
ab532cf3
TH		 2344 .get_rxnfc = bnx2x_get_rxnfc,
2345 .get_rxfh_indir = bnx2x_get_rxfh_indir,
2346 .set_rxfh_indir = bnx2x_set_rxfh_indir,
de0c62db
DK		 2347};
2348
2349void bnx2x_set_ethtool_ops(struct net_device *netdev)
2350{
2351 SET_ETHTOOL_OPS(netdev, &bnx2x_ethtool_ops);
2352}
kernel source for telekom puls (alcatel/mediatek)