Commit | Line | Data |
---|---|---|
a2fbb9ea ET |
1 | /* bnx2x.h: Broadcom Everest network driver. |
2 | * | |
3359fced | 3 | * Copyright (c) 2007-2010 Broadcom Corporation |
a2fbb9ea ET |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
24e3fcef EG |
9 | * Maintained by: Eilon Greenstein <eilong@broadcom.com> |
10 | * Written by: Eliezer Tamir | |
a2fbb9ea ET |
11 | * Based on code from Michael Chan's bnx2 driver |
12 | */ | |
13 | ||
14 | #ifndef BNX2X_H | |
15 | #define BNX2X_H | |
ec6ba945 VZ |
16 | #include <linux/netdevice.h> |
17 | #include <linux/types.h> | |
a2fbb9ea | 18 | |
34f80b04 EG |
19 | /* compilation time flags */ |
20 | ||
21 | /* define this to make the driver freeze on error to allow getting debug info | |
22 | * (you will need to reboot afterwards) */ | |
23 | /* #define BNX2X_STOP_ON_ERROR */ | |
24 | ||
f404c2fe VZ |
25 | #define DRV_MODULE_VERSION "1.60.00-7" |
26 | #define DRV_MODULE_RELDATE "2010/12/08" | |
de0c62db DK |
27 | #define BNX2X_BC_VER 0x040200 |
28 | ||
1ac218c8 VZ |
29 | #define BNX2X_MULTI_QUEUE |
30 | ||
31 | #define BNX2X_NEW_NAPI | |
32 | ||
33 | ||
993ac7b5 MC |
34 | #if defined(CONFIG_CNIC) || defined(CONFIG_CNIC_MODULE) |
35 | #define BCM_CNIC 1 | |
5d1e859c | 36 | #include "../cnic_if.h" |
993ac7b5 | 37 | #endif |
0c6671b0 | 38 | |
1ac218c8 VZ |
39 | #ifdef BCM_CNIC |
40 | #define BNX2X_MIN_MSIX_VEC_CNT 3 | |
41 | #define BNX2X_MSIX_VEC_FP_START 2 | |
42 | #else | |
43 | #define BNX2X_MIN_MSIX_VEC_CNT 2 | |
44 | #define BNX2X_MSIX_VEC_FP_START 1 | |
45 | #endif | |
01cd4528 EG |
46 | |
47 | #include <linux/mdio.h> | |
9f6c9258 | 48 | #include <linux/pci.h> |
359d8b15 EG |
49 | #include "bnx2x_reg.h" |
50 | #include "bnx2x_fw_defs.h" | |
51 | #include "bnx2x_hsi.h" | |
52 | #include "bnx2x_link.h" | |
6c719d00 | 53 | #include "bnx2x_stats.h" |
359d8b15 | 54 | |
a2fbb9ea ET |
55 | /* error/debug prints */ |
56 | ||
34f80b04 | 57 | #define DRV_MODULE_NAME "bnx2x" |
a2fbb9ea ET |
58 | |
59 | /* for messages that are currently off */ | |
34f80b04 EG |
60 | #define BNX2X_MSG_OFF 0 |
61 | #define BNX2X_MSG_MCP 0x010000 /* was: NETIF_MSG_HW */ | |
62 | #define BNX2X_MSG_STATS 0x020000 /* was: NETIF_MSG_TIMER */ | |
63 | #define BNX2X_MSG_NVM 0x040000 /* was: NETIF_MSG_HW */ | |
64 | #define BNX2X_MSG_DMAE 0x080000 /* was: NETIF_MSG_HW */ | |
f1410647 ET |
65 | #define BNX2X_MSG_SP 0x100000 /* was: NETIF_MSG_INTR */ |
66 | #define BNX2X_MSG_FP 0x200000 /* was: NETIF_MSG_INTR */ | |
a2fbb9ea | 67 | |
34f80b04 | 68 | #define DP_LEVEL KERN_NOTICE /* was: KERN_DEBUG */ |
a2fbb9ea ET |
69 | |
70 | /* regular debug print */ | |
7995c64e JP |
71 | #define DP(__mask, __fmt, __args...) \ |
72 | do { \ | |
73 | if (bp->msg_enable & (__mask)) \ | |
74 | printk(DP_LEVEL "[%s:%d(%s)]" __fmt, \ | |
75 | __func__, __LINE__, \ | |
76 | bp->dev ? (bp->dev->name) : "?", \ | |
77 | ##__args); \ | |
78 | } while (0) | |
a2fbb9ea | 79 | |
34f80b04 | 80 | /* errors debug print */ |
7995c64e JP |
81 | #define BNX2X_DBG_ERR(__fmt, __args...) \ |
82 | do { \ | |
83 | if (netif_msg_probe(bp)) \ | |
84 | pr_err("[%s:%d(%s)]" __fmt, \ | |
85 | __func__, __LINE__, \ | |
86 | bp->dev ? (bp->dev->name) : "?", \ | |
87 | ##__args); \ | |
88 | } while (0) | |
a2fbb9ea | 89 | |
34f80b04 | 90 | /* for errors (never masked) */ |
7995c64e JP |
91 | #define BNX2X_ERR(__fmt, __args...) \ |
92 | do { \ | |
93 | pr_err("[%s:%d(%s)]" __fmt, \ | |
94 | __func__, __LINE__, \ | |
95 | bp->dev ? (bp->dev->name) : "?", \ | |
96 | ##__args); \ | |
cdaa7cb8 VZ |
97 | } while (0) |
98 | ||
99 | #define BNX2X_ERROR(__fmt, __args...) do { \ | |
100 | pr_err("[%s:%d]" __fmt, __func__, __LINE__, ##__args); \ | |
101 | } while (0) | |
102 | ||
f1410647 | 103 | |
a2fbb9ea | 104 | /* before we have a dev->name use dev_info() */ |
7995c64e JP |
105 | #define BNX2X_DEV_INFO(__fmt, __args...) \ |
106 | do { \ | |
107 | if (netif_msg_probe(bp)) \ | |
108 | dev_info(&bp->pdev->dev, __fmt, ##__args); \ | |
109 | } while (0) | |
a2fbb9ea | 110 | |
6c719d00 | 111 | void bnx2x_panic_dump(struct bnx2x *bp); |
a2fbb9ea ET |
112 | |
113 | #ifdef BNX2X_STOP_ON_ERROR | |
114 | #define bnx2x_panic() do { \ | |
115 | bp->panic = 1; \ | |
116 | BNX2X_ERR("driver assert\n"); \ | |
34f80b04 | 117 | bnx2x_int_disable(bp); \ |
a2fbb9ea ET |
118 | bnx2x_panic_dump(bp); \ |
119 | } while (0) | |
120 | #else | |
121 | #define bnx2x_panic() do { \ | |
e3553b29 | 122 | bp->panic = 1; \ |
a2fbb9ea ET |
123 | BNX2X_ERR("driver assert\n"); \ |
124 | bnx2x_panic_dump(bp); \ | |
125 | } while (0) | |
126 | #endif | |
127 | ||
523224a3 | 128 | #define bnx2x_mc_addr(ha) ((ha)->addr) |
a2fbb9ea | 129 | |
34f80b04 EG |
130 | #define U64_LO(x) (u32)(((u64)(x)) & 0xffffffff) |
131 | #define U64_HI(x) (u32)(((u64)(x)) >> 32) | |
132 | #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo)) | |
a2fbb9ea | 133 | |
a2fbb9ea | 134 | |
523224a3 | 135 | #define REG_ADDR(bp, offset) ((bp->regview) + (offset)) |
a2fbb9ea | 136 | |
34f80b04 EG |
137 | #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset)) |
138 | #define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset)) | |
523224a3 | 139 | #define REG_RD16(bp, offset) readw(REG_ADDR(bp, offset)) |
34f80b04 EG |
140 | |
141 | #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset)) | |
a2fbb9ea | 142 | #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset)) |
34f80b04 | 143 | #define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset)) |
a2fbb9ea | 144 | |
34f80b04 EG |
145 | #define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset) |
146 | #define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val) | |
a2fbb9ea | 147 | |
c18487ee YR |
148 | #define REG_RD_DMAE(bp, offset, valp, len32) \ |
149 | do { \ | |
150 | bnx2x_read_dmae(bp, offset, len32);\ | |
573f2035 | 151 | memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \ |
c18487ee YR |
152 | } while (0) |
153 | ||
34f80b04 | 154 | #define REG_WR_DMAE(bp, offset, valp, len32) \ |
a2fbb9ea | 155 | do { \ |
573f2035 | 156 | memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \ |
a2fbb9ea ET |
157 | bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \ |
158 | offset, len32); \ | |
159 | } while (0) | |
160 | ||
523224a3 DK |
161 | #define REG_WR_DMAE_LEN(bp, offset, valp, len32) \ |
162 | REG_WR_DMAE(bp, offset, valp, len32) | |
163 | ||
3359fced | 164 | #define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) \ |
573f2035 EG |
165 | do { \ |
166 | memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \ | |
167 | bnx2x_write_big_buf_wb(bp, addr, len32); \ | |
168 | } while (0) | |
169 | ||
34f80b04 EG |
170 | #define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \ |
171 | offsetof(struct shmem_region, field)) | |
172 | #define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field)) | |
173 | #define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val) | |
a2fbb9ea | 174 | |
2691d51d EG |
175 | #define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \ |
176 | offsetof(struct shmem2_region, field)) | |
177 | #define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field)) | |
178 | #define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val) | |
523224a3 DK |
179 | #define MF_CFG_ADDR(bp, field) (bp->common.mf_cfg_base + \ |
180 | offsetof(struct mf_cfg, field)) | |
f85582f8 | 181 | #define MF2_CFG_ADDR(bp, field) (bp->common.mf2_cfg_base + \ |
f2e0899f | 182 | offsetof(struct mf2_cfg, field)) |
2691d51d | 183 | |
523224a3 DK |
184 | #define MF_CFG_RD(bp, field) REG_RD(bp, MF_CFG_ADDR(bp, field)) |
185 | #define MF_CFG_WR(bp, field, val) REG_WR(bp,\ | |
186 | MF_CFG_ADDR(bp, field), (val)) | |
f2e0899f | 187 | #define MF2_CFG_RD(bp, field) REG_RD(bp, MF2_CFG_ADDR(bp, field)) |
f85582f8 | 188 | |
f2e0899f DK |
189 | #define SHMEM2_HAS(bp, field) ((bp)->common.shmem2_base && \ |
190 | (SHMEM2_RD((bp), size) > \ | |
191 | offsetof(struct shmem2_region, field))) | |
72fd0718 | 192 | |
345b5d52 | 193 | #define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg) |
3196a88a | 194 | #define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val) |
a2fbb9ea | 195 | |
523224a3 DK |
196 | /* SP SB indices */ |
197 | ||
198 | /* General SP events - stats query, cfc delete, etc */ | |
199 | #define HC_SP_INDEX_ETH_DEF_CONS 3 | |
200 | ||
201 | /* EQ completions */ | |
202 | #define HC_SP_INDEX_EQ_CONS 7 | |
203 | ||
ec6ba945 VZ |
204 | /* FCoE L2 connection completions */ |
205 | #define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6 | |
206 | #define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4 | |
523224a3 DK |
207 | /* iSCSI L2 */ |
208 | #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5 | |
209 | #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1 | |
210 | ||
ec6ba945 VZ |
211 | /* Special clients parameters */ |
212 | ||
213 | /* SB indices */ | |
214 | /* FCoE L2 */ | |
215 | #define BNX2X_FCOE_L2_RX_INDEX \ | |
216 | (&bp->def_status_blk->sp_sb.\ | |
217 | index_values[HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS]) | |
218 | ||
219 | #define BNX2X_FCOE_L2_TX_INDEX \ | |
220 | (&bp->def_status_blk->sp_sb.\ | |
221 | index_values[HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS]) | |
222 | ||
523224a3 DK |
223 | /** |
224 | * CIDs and CLIDs: | |
225 | * CLIDs below is a CLID for func 0, then the CLID for other | |
226 | * functions will be calculated by the formula: | |
227 | * | |
228 | * FUNC_N_CLID_X = N * NUM_SPECIAL_CLIENTS + FUNC_0_CLID_X | |
229 | * | |
230 | */ | |
231 | /* iSCSI L2 */ | |
232 | #define BNX2X_ISCSI_ETH_CL_ID 17 | |
233 | #define BNX2X_ISCSI_ETH_CID 17 | |
234 | ||
ec6ba945 VZ |
235 | /* FCoE L2 */ |
236 | #define BNX2X_FCOE_ETH_CL_ID 18 | |
237 | #define BNX2X_FCOE_ETH_CID 18 | |
238 | ||
523224a3 DK |
239 | /** Additional rings budgeting */ |
240 | #ifdef BCM_CNIC | |
241 | #define CNIC_CONTEXT_USE 1 | |
ec6ba945 | 242 | #define FCOE_CONTEXT_USE 1 |
523224a3 DK |
243 | #else |
244 | #define CNIC_CONTEXT_USE 0 | |
ec6ba945 | 245 | #define FCOE_CONTEXT_USE 0 |
523224a3 | 246 | #endif /* BCM_CNIC */ |
ec6ba945 | 247 | #define NONE_ETH_CONTEXT_USE (FCOE_CONTEXT_USE) |
523224a3 | 248 | |
72fd0718 VZ |
249 | #define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \ |
250 | AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR | |
251 | ||
523224a3 DK |
252 | #define SM_RX_ID 0 |
253 | #define SM_TX_ID 1 | |
a2fbb9ea | 254 | |
7a9b2557 | 255 | /* fast path */ |
a2fbb9ea | 256 | |
a2fbb9ea | 257 | struct sw_rx_bd { |
34f80b04 | 258 | struct sk_buff *skb; |
1a983142 | 259 | DEFINE_DMA_UNMAP_ADDR(mapping); |
a2fbb9ea ET |
260 | }; |
261 | ||
262 | struct sw_tx_bd { | |
34f80b04 EG |
263 | struct sk_buff *skb; |
264 | u16 first_bd; | |
ca00392c EG |
265 | u8 flags; |
266 | /* Set on the first BD descriptor when there is a split BD */ | |
267 | #define BNX2X_TSO_SPLIT_BD (1<<0) | |
a2fbb9ea ET |
268 | }; |
269 | ||
7a9b2557 VZ |
270 | struct sw_rx_page { |
271 | struct page *page; | |
1a983142 | 272 | DEFINE_DMA_UNMAP_ADDR(mapping); |
7a9b2557 VZ |
273 | }; |
274 | ||
ca00392c EG |
275 | union db_prod { |
276 | struct doorbell_set_prod data; | |
277 | u32 raw; | |
278 | }; | |
279 | ||
7a9b2557 VZ |
280 | |
281 | /* MC hsi */ | |
282 | #define BCM_PAGE_SHIFT 12 | |
283 | #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT) | |
284 | #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1)) | |
285 | #define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK) | |
286 | ||
287 | #define PAGES_PER_SGE_SHIFT 0 | |
288 | #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT) | |
4f40f2cb EG |
289 | #define SGE_PAGE_SIZE PAGE_SIZE |
290 | #define SGE_PAGE_SHIFT PAGE_SHIFT | |
5b6402d1 | 291 | #define SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))(addr)) |
7a9b2557 VZ |
292 | |
293 | /* SGE ring related macros */ | |
294 | #define NUM_RX_SGE_PAGES 2 | |
295 | #define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge)) | |
296 | #define MAX_RX_SGE_CNT (RX_SGE_CNT - 2) | |
33471629 | 297 | /* RX_SGE_CNT is promised to be a power of 2 */ |
7a9b2557 VZ |
298 | #define RX_SGE_MASK (RX_SGE_CNT - 1) |
299 | #define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES) | |
300 | #define MAX_RX_SGE (NUM_RX_SGE - 1) | |
301 | #define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \ | |
302 | (MAX_RX_SGE_CNT - 1)) ? (x) + 3 : (x) + 1) | |
303 | #define RX_SGE(x) ((x) & MAX_RX_SGE) | |
304 | ||
305 | /* SGE producer mask related macros */ | |
306 | /* Number of bits in one sge_mask array element */ | |
307 | #define RX_SGE_MASK_ELEM_SZ 64 | |
308 | #define RX_SGE_MASK_ELEM_SHIFT 6 | |
309 | #define RX_SGE_MASK_ELEM_MASK ((u64)RX_SGE_MASK_ELEM_SZ - 1) | |
310 | ||
311 | /* Creates a bitmask of all ones in less significant bits. | |
312 | idx - index of the most significant bit in the created mask */ | |
313 | #define RX_SGE_ONES_MASK(idx) \ | |
314 | (((u64)0x1 << (((idx) & RX_SGE_MASK_ELEM_MASK) + 1)) - 1) | |
315 | #define RX_SGE_MASK_ELEM_ONE_MASK ((u64)(~0)) | |
316 | ||
317 | /* Number of u64 elements in SGE mask array */ | |
318 | #define RX_SGE_MASK_LEN ((NUM_RX_SGE_PAGES * RX_SGE_CNT) / \ | |
319 | RX_SGE_MASK_ELEM_SZ) | |
320 | #define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1) | |
321 | #define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK) | |
322 | ||
523224a3 DK |
323 | union host_hc_status_block { |
324 | /* pointer to fp status block e1x */ | |
325 | struct host_hc_status_block_e1x *e1x_sb; | |
f2e0899f DK |
326 | /* pointer to fp status block e2 */ |
327 | struct host_hc_status_block_e2 *e2_sb; | |
523224a3 | 328 | }; |
7a9b2557 | 329 | |
a2fbb9ea ET |
330 | struct bnx2x_fastpath { |
331 | ||
d6214d7a | 332 | #define BNX2X_NAPI_WEIGHT 128 |
34f80b04 | 333 | struct napi_struct napi; |
f85582f8 | 334 | union host_hc_status_block status_blk; |
523224a3 DK |
335 | /* chip independed shortcuts into sb structure */ |
336 | __le16 *sb_index_values; | |
337 | __le16 *sb_running_index; | |
338 | /* chip independed shortcut into rx_prods_offset memory */ | |
339 | u32 ustorm_rx_prods_offset; | |
340 | ||
34f80b04 | 341 | dma_addr_t status_blk_mapping; |
a2fbb9ea | 342 | |
34f80b04 | 343 | struct sw_tx_bd *tx_buf_ring; |
a2fbb9ea | 344 | |
ca00392c | 345 | union eth_tx_bd_types *tx_desc_ring; |
34f80b04 | 346 | dma_addr_t tx_desc_mapping; |
a2fbb9ea | 347 | |
7a9b2557 VZ |
348 | struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */ |
349 | struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */ | |
a2fbb9ea ET |
350 | |
351 | struct eth_rx_bd *rx_desc_ring; | |
34f80b04 | 352 | dma_addr_t rx_desc_mapping; |
a2fbb9ea ET |
353 | |
354 | union eth_rx_cqe *rx_comp_ring; | |
34f80b04 EG |
355 | dma_addr_t rx_comp_mapping; |
356 | ||
7a9b2557 VZ |
357 | /* SGE ring */ |
358 | struct eth_rx_sge *rx_sge_ring; | |
359 | dma_addr_t rx_sge_mapping; | |
360 | ||
361 | u64 sge_mask[RX_SGE_MASK_LEN]; | |
362 | ||
34f80b04 EG |
363 | int state; |
364 | #define BNX2X_FP_STATE_CLOSED 0 | |
365 | #define BNX2X_FP_STATE_IRQ 0x80000 | |
366 | #define BNX2X_FP_STATE_OPENING 0x90000 | |
367 | #define BNX2X_FP_STATE_OPEN 0xa0000 | |
368 | #define BNX2X_FP_STATE_HALTING 0xb0000 | |
369 | #define BNX2X_FP_STATE_HALTED 0xc0000 | |
523224a3 DK |
370 | #define BNX2X_FP_STATE_TERMINATING 0xd0000 |
371 | #define BNX2X_FP_STATE_TERMINATED 0xe0000 | |
34f80b04 | 372 | |
f85582f8 DK |
373 | u8 index; /* number in fp array */ |
374 | u8 cl_id; /* eth client id */ | |
523224a3 DK |
375 | u8 cl_qzone_id; |
376 | u8 fw_sb_id; /* status block number in FW */ | |
377 | u8 igu_sb_id; /* status block number in HW */ | |
378 | u32 cid; | |
34f80b04 | 379 | |
ca00392c EG |
380 | union db_prod tx_db; |
381 | ||
34f80b04 EG |
382 | u16 tx_pkt_prod; |
383 | u16 tx_pkt_cons; | |
384 | u16 tx_bd_prod; | |
385 | u16 tx_bd_cons; | |
4781bfad | 386 | __le16 *tx_cons_sb; |
34f80b04 | 387 | |
523224a3 | 388 | __le16 fp_hc_idx; |
34f80b04 EG |
389 | |
390 | u16 rx_bd_prod; | |
391 | u16 rx_bd_cons; | |
392 | u16 rx_comp_prod; | |
393 | u16 rx_comp_cons; | |
7a9b2557 VZ |
394 | u16 rx_sge_prod; |
395 | /* The last maximal completed SGE */ | |
396 | u16 last_max_sge; | |
4781bfad | 397 | __le16 *rx_cons_sb; |
523224a3 | 398 | |
34f80b04 | 399 | unsigned long tx_pkt, |
a2fbb9ea | 400 | rx_pkt, |
66e855f3 | 401 | rx_calls; |
ab6ad5a4 | 402 | |
7a9b2557 VZ |
403 | /* TPA related */ |
404 | struct sw_rx_bd tpa_pool[ETH_MAX_AGGREGATION_QUEUES_E1H]; | |
405 | u8 tpa_state[ETH_MAX_AGGREGATION_QUEUES_E1H]; | |
406 | #define BNX2X_TPA_START 1 | |
407 | #define BNX2X_TPA_STOP 2 | |
408 | u8 disable_tpa; | |
409 | #ifdef BNX2X_STOP_ON_ERROR | |
410 | u64 tpa_queue_used; | |
411 | #endif | |
a2fbb9ea | 412 | |
de832a55 EG |
413 | struct tstorm_per_client_stats old_tclient; |
414 | struct ustorm_per_client_stats old_uclient; | |
415 | struct xstorm_per_client_stats old_xclient; | |
416 | struct bnx2x_eth_q_stats eth_q_stats; | |
417 | ||
ca00392c EG |
418 | /* The size is calculated using the following: |
419 | sizeof name field from netdev structure + | |
420 | 4 ('-Xx-' string) + | |
421 | 4 (for the digits and to make it DWORD aligned) */ | |
422 | #define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8) | |
423 | char name[FP_NAME_SIZE]; | |
34f80b04 | 424 | struct bnx2x *bp; /* parent */ |
a2fbb9ea ET |
425 | }; |
426 | ||
34f80b04 | 427 | #define bnx2x_fp(bp, nr, var) (bp->fp[nr].var) |
ec6ba945 VZ |
428 | #ifdef BCM_CNIC |
429 | /* FCoE L2 `fastpath' is right after the eth entries */ | |
430 | #define FCOE_IDX BNX2X_NUM_ETH_QUEUES(bp) | |
431 | #define bnx2x_fcoe_fp(bp) (&bp->fp[FCOE_IDX]) | |
432 | #define bnx2x_fcoe(bp, var) (bnx2x_fcoe_fp(bp)->var) | |
433 | #define IS_FCOE_FP(fp) (fp->index == FCOE_IDX) | |
434 | #define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX) | |
435 | #else | |
436 | #define IS_FCOE_FP(fp) false | |
437 | #define IS_FCOE_IDX(idx) false | |
438 | #endif | |
7a9b2557 VZ |
439 | |
440 | ||
441 | /* MC hsi */ | |
442 | #define MAX_FETCH_BD 13 /* HW max BDs per packet */ | |
443 | #define RX_COPY_THRESH 92 | |
444 | ||
445 | #define NUM_TX_RINGS 16 | |
ca00392c | 446 | #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types)) |
7a9b2557 VZ |
447 | #define MAX_TX_DESC_CNT (TX_DESC_CNT - 1) |
448 | #define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS) | |
449 | #define MAX_TX_BD (NUM_TX_BD - 1) | |
450 | #define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2) | |
523224a3 DK |
451 | #define INIT_JUMBO_TX_RING_SIZE MAX_TX_AVAIL |
452 | #define INIT_TX_RING_SIZE MAX_TX_AVAIL | |
7a9b2557 VZ |
453 | #define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \ |
454 | (MAX_TX_DESC_CNT - 1)) ? (x) + 2 : (x) + 1) | |
455 | #define TX_BD(x) ((x) & MAX_TX_BD) | |
456 | #define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT) | |
457 | ||
458 | /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */ | |
459 | #define NUM_RX_RINGS 8 | |
460 | #define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd)) | |
461 | #define MAX_RX_DESC_CNT (RX_DESC_CNT - 2) | |
462 | #define RX_DESC_MASK (RX_DESC_CNT - 1) | |
463 | #define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS) | |
464 | #define MAX_RX_BD (NUM_RX_BD - 1) | |
465 | #define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2) | |
25141580 | 466 | #define MIN_RX_AVAIL 128 |
523224a3 DK |
467 | #define INIT_JUMBO_RX_RING_SIZE MAX_RX_AVAIL |
468 | #define INIT_RX_RING_SIZE MAX_RX_AVAIL | |
7a9b2557 VZ |
469 | #define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \ |
470 | (MAX_RX_DESC_CNT - 1)) ? (x) + 3 : (x) + 1) | |
471 | #define RX_BD(x) ((x) & MAX_RX_BD) | |
472 | ||
473 | /* As long as CQE is 4 times bigger than BD entry we have to allocate | |
474 | 4 times more pages for CQ ring in order to keep it balanced with | |
475 | BD ring */ | |
476 | #define NUM_RCQ_RINGS (NUM_RX_RINGS * 4) | |
477 | #define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe)) | |
478 | #define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - 1) | |
479 | #define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS) | |
480 | #define MAX_RCQ_BD (NUM_RCQ_BD - 1) | |
481 | #define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2) | |
482 | #define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \ | |
483 | (MAX_RCQ_DESC_CNT - 1)) ? (x) + 2 : (x) + 1) | |
484 | #define RCQ_BD(x) ((x) & MAX_RCQ_BD) | |
485 | ||
486 | ||
33471629 | 487 | /* This is needed for determining of last_max */ |
34f80b04 | 488 | #define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b)) |
a2fbb9ea | 489 | |
7a9b2557 VZ |
490 | #define __SGE_MASK_SET_BIT(el, bit) \ |
491 | do { \ | |
492 | el = ((el) | ((u64)0x1 << (bit))); \ | |
493 | } while (0) | |
494 | ||
495 | #define __SGE_MASK_CLEAR_BIT(el, bit) \ | |
496 | do { \ | |
497 | el = ((el) & (~((u64)0x1 << (bit)))); \ | |
498 | } while (0) | |
499 | ||
500 | #define SGE_MASK_SET_BIT(fp, idx) \ | |
501 | __SGE_MASK_SET_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \ | |
502 | ((idx) & RX_SGE_MASK_ELEM_MASK)) | |
503 | ||
504 | #define SGE_MASK_CLEAR_BIT(fp, idx) \ | |
505 | __SGE_MASK_CLEAR_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \ | |
506 | ((idx) & RX_SGE_MASK_ELEM_MASK)) | |
507 | ||
508 | ||
509 | /* used on a CID received from the HW */ | |
510 | #define SW_CID(x) (le32_to_cpu(x) & \ | |
511 | (COMMON_RAMROD_ETH_RX_CQE_CID >> 7)) | |
512 | #define CQE_CMD(x) (le32_to_cpu(x) >> \ | |
513 | COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT) | |
514 | ||
bb2a0f7a YG |
515 | #define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \ |
516 | le32_to_cpu((bd)->addr_lo)) | |
517 | #define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes)) | |
518 | ||
523224a3 DK |
519 | #define BNX2X_DB_MIN_SHIFT 3 /* 8 bytes */ |
520 | #define BNX2X_DB_SHIFT 7 /* 128 bytes*/ | |
7a9b2557 VZ |
521 | #define DPM_TRIGER_TYPE 0x40 |
522 | #define DOORBELL(bp, cid, val) \ | |
523 | do { \ | |
523224a3 | 524 | writel((u32)(val), bp->doorbells + (bp->db_size * (cid)) + \ |
7a9b2557 VZ |
525 | DPM_TRIGER_TYPE); \ |
526 | } while (0) | |
527 | ||
528 | ||
529 | /* TX CSUM helpers */ | |
530 | #define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \ | |
531 | skb->csum_offset) | |
532 | #define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \ | |
533 | skb->csum_offset)) | |
534 | ||
535 | #define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff) | |
536 | ||
537 | #define XMIT_PLAIN 0 | |
538 | #define XMIT_CSUM_V4 0x1 | |
539 | #define XMIT_CSUM_V6 0x2 | |
540 | #define XMIT_CSUM_TCP 0x4 | |
541 | #define XMIT_GSO_V4 0x8 | |
542 | #define XMIT_GSO_V6 0x10 | |
543 | ||
544 | #define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6) | |
545 | #define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6) | |
546 | ||
547 | ||
34f80b04 | 548 | /* stuff added to make the code fit 80Col */ |
a2fbb9ea | 549 | |
34f80b04 | 550 | #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE) |
a2fbb9ea | 551 | |
7a9b2557 VZ |
552 | #define TPA_TYPE_START ETH_FAST_PATH_RX_CQE_START_FLG |
553 | #define TPA_TYPE_END ETH_FAST_PATH_RX_CQE_END_FLG | |
554 | #define TPA_TYPE(cqe_fp_flags) ((cqe_fp_flags) & \ | |
555 | (TPA_TYPE_START | TPA_TYPE_END)) | |
556 | ||
1adcd8be EG |
557 | #define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG |
558 | ||
559 | #define BNX2X_IP_CSUM_ERR(cqe) \ | |
560 | (!((cqe)->fast_path_cqe.status_flags & \ | |
561 | ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG) && \ | |
562 | ((cqe)->fast_path_cqe.type_error_flags & \ | |
563 | ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG)) | |
564 | ||
565 | #define BNX2X_L4_CSUM_ERR(cqe) \ | |
566 | (!((cqe)->fast_path_cqe.status_flags & \ | |
567 | ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG) && \ | |
568 | ((cqe)->fast_path_cqe.type_error_flags & \ | |
569 | ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG)) | |
570 | ||
571 | #define BNX2X_RX_CSUM_OK(cqe) \ | |
572 | (!(BNX2X_L4_CSUM_ERR(cqe) || BNX2X_IP_CSUM_ERR(cqe))) | |
7a9b2557 | 573 | |
052a38e0 EG |
574 | #define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \ |
575 | (((le16_to_cpu(flags) & \ | |
576 | PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \ | |
577 | PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \ | |
578 | == PRS_FLAG_OVERETH_IPV4) | |
7a9b2557 | 579 | #define BNX2X_RX_SUM_FIX(cqe) \ |
052a38e0 | 580 | BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags) |
7a9b2557 | 581 | |
523224a3 DK |
582 | #define U_SB_ETH_RX_CQ_INDEX 1 |
583 | #define U_SB_ETH_RX_BD_INDEX 2 | |
584 | #define C_SB_ETH_TX_CQ_INDEX 5 | |
a2fbb9ea | 585 | |
34f80b04 | 586 | #define BNX2X_RX_SB_INDEX \ |
523224a3 | 587 | (&fp->sb_index_values[U_SB_ETH_RX_CQ_INDEX]) |
a2fbb9ea | 588 | |
34f80b04 | 589 | #define BNX2X_TX_SB_INDEX \ |
523224a3 | 590 | (&fp->sb_index_values[C_SB_ETH_TX_CQ_INDEX]) |
7a9b2557 VZ |
591 | |
592 | /* end of fast path */ | |
593 | ||
34f80b04 | 594 | /* common */ |
a2fbb9ea | 595 | |
34f80b04 | 596 | struct bnx2x_common { |
a2fbb9ea | 597 | |
ad8d3948 | 598 | u32 chip_id; |
a2fbb9ea | 599 | /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ |
34f80b04 | 600 | #define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0) |
ad8d3948 | 601 | |
34f80b04 | 602 | #define CHIP_NUM(bp) (bp->common.chip_id >> 16) |
ad8d3948 EG |
603 | #define CHIP_NUM_57710 0x164e |
604 | #define CHIP_NUM_57711 0x164f | |
605 | #define CHIP_NUM_57711E 0x1650 | |
f2e0899f DK |
606 | #define CHIP_NUM_57712 0x1662 |
607 | #define CHIP_NUM_57712E 0x1663 | |
ad8d3948 EG |
608 | #define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710) |
609 | #define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711) | |
610 | #define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E) | |
f2e0899f DK |
611 | #define CHIP_IS_57712(bp) (CHIP_NUM(bp) == CHIP_NUM_57712) |
612 | #define CHIP_IS_57712E(bp) (CHIP_NUM(bp) == CHIP_NUM_57712E) | |
ad8d3948 EG |
613 | #define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \ |
614 | CHIP_IS_57711E(bp)) | |
f2e0899f DK |
615 | #define CHIP_IS_E2(bp) (CHIP_IS_57712(bp) || \ |
616 | CHIP_IS_57712E(bp)) | |
617 | #define CHIP_IS_E1x(bp) (CHIP_IS_E1((bp)) || CHIP_IS_E1H((bp))) | |
618 | #define IS_E1H_OFFSET (CHIP_IS_E1H(bp) || CHIP_IS_E2(bp)) | |
ad8d3948 | 619 | |
34f80b04 | 620 | #define CHIP_REV(bp) (bp->common.chip_id & 0x0000f000) |
ad8d3948 EG |
621 | #define CHIP_REV_Ax 0x00000000 |
622 | /* assume maximum 5 revisions */ | |
623 | #define CHIP_REV_IS_SLOW(bp) (CHIP_REV(bp) > 0x00005000) | |
624 | /* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */ | |
625 | #define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \ | |
626 | !(CHIP_REV(bp) & 0x00001000)) | |
627 | /* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */ | |
628 | #define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \ | |
629 | (CHIP_REV(bp) & 0x00001000)) | |
630 | ||
631 | #define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \ | |
632 | ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1)) | |
633 | ||
34f80b04 EG |
634 | #define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0) |
635 | #define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f) | |
a2fbb9ea | 636 | |
34f80b04 EG |
637 | int flash_size; |
638 | #define NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */ | |
639 | #define NVRAM_TIMEOUT_COUNT 30000 | |
640 | #define NVRAM_PAGE_SIZE 256 | |
a2fbb9ea | 641 | |
34f80b04 | 642 | u32 shmem_base; |
2691d51d | 643 | u32 shmem2_base; |
523224a3 | 644 | u32 mf_cfg_base; |
f2e0899f | 645 | u32 mf2_cfg_base; |
34f80b04 EG |
646 | |
647 | u32 hw_config; | |
c18487ee | 648 | |
34f80b04 | 649 | u32 bc_ver; |
523224a3 DK |
650 | |
651 | u8 int_block; | |
652 | #define INT_BLOCK_HC 0 | |
f2e0899f DK |
653 | #define INT_BLOCK_IGU 1 |
654 | #define INT_BLOCK_MODE_NORMAL 0 | |
655 | #define INT_BLOCK_MODE_BW_COMP 2 | |
656 | #define CHIP_INT_MODE_IS_NBC(bp) \ | |
657 | (CHIP_IS_E2(bp) && \ | |
658 | !((bp)->common.int_block & INT_BLOCK_MODE_BW_COMP)) | |
659 | #define CHIP_INT_MODE_IS_BC(bp) (!CHIP_INT_MODE_IS_NBC(bp)) | |
660 | ||
523224a3 | 661 | u8 chip_port_mode; |
f2e0899f DK |
662 | #define CHIP_4_PORT_MODE 0x0 |
663 | #define CHIP_2_PORT_MODE 0x1 | |
523224a3 | 664 | #define CHIP_PORT_MODE_NONE 0x2 |
f2e0899f DK |
665 | #define CHIP_MODE(bp) (bp->common.chip_port_mode) |
666 | #define CHIP_MODE_IS_4_PORT(bp) (CHIP_MODE(bp) == CHIP_4_PORT_MODE) | |
34f80b04 | 667 | }; |
c18487ee | 668 | |
f2e0899f DK |
669 | /* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */ |
670 | #define BNX2X_IGU_STAS_MSG_VF_CNT 64 | |
671 | #define BNX2X_IGU_STAS_MSG_PF_CNT 4 | |
34f80b04 EG |
672 | |
673 | /* end of common */ | |
674 | ||
675 | /* port */ | |
676 | ||
677 | struct bnx2x_port { | |
678 | u32 pmf; | |
c18487ee | 679 | |
a22f0788 | 680 | u32 link_config[LINK_CONFIG_SIZE]; |
a2fbb9ea | 681 | |
a22f0788 | 682 | u32 supported[LINK_CONFIG_SIZE]; |
34f80b04 EG |
683 | /* link settings - missing defines */ |
684 | #define SUPPORTED_2500baseX_Full (1 << 15) | |
685 | ||
a22f0788 | 686 | u32 advertising[LINK_CONFIG_SIZE]; |
a2fbb9ea | 687 | /* link settings - missing defines */ |
34f80b04 | 688 | #define ADVERTISED_2500baseX_Full (1 << 15) |
a2fbb9ea | 689 | |
34f80b04 | 690 | u32 phy_addr; |
c18487ee YR |
691 | |
692 | /* used to synchronize phy accesses */ | |
693 | struct mutex phy_mutex; | |
46c6a674 | 694 | int need_hw_lock; |
c18487ee | 695 | |
34f80b04 | 696 | u32 port_stx; |
a2fbb9ea | 697 | |
34f80b04 EG |
698 | struct nig_stats old_nig_stats; |
699 | }; | |
a2fbb9ea | 700 | |
34f80b04 EG |
701 | /* end of port */ |
702 | ||
523224a3 DK |
703 | /* e1h Classification CAM line allocations */ |
704 | enum { | |
705 | CAM_ETH_LINE = 0, | |
706 | CAM_ISCSI_ETH_LINE, | |
ec6ba945 VZ |
707 | CAM_FIP_ETH_LINE, |
708 | CAM_FIP_MCAST_LINE, | |
709 | CAM_MAX_PF_LINE = CAM_FIP_MCAST_LINE | |
523224a3 | 710 | }; |
0793f83f DK |
711 | /* number of MACs per function in NIG memory - used for SI mode */ |
712 | #define NIG_LLH_FUNC_MEM_SIZE 16 | |
713 | /* number of entries in NIG_REG_LLHX_FUNC_MEM */ | |
714 | #define NIG_LLH_FUNC_MEM_MAX_OFFSET 8 | |
bb2a0f7a | 715 | |
523224a3 | 716 | #define BNX2X_VF_ID_INVALID 0xFF |
34f80b04 | 717 | |
523224a3 DK |
718 | /* |
719 | * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is | |
720 | * control by the number of fast-path status blocks supported by the | |
721 | * device (HW/FW). Each fast-path status block (FP-SB) aka non-default | |
722 | * status block represents an independent interrupts context that can | |
723 | * serve a regular L2 networking queue. However special L2 queues such | |
724 | * as the FCoE queue do not require a FP-SB and other components like | |
725 | * the CNIC may consume FP-SB reducing the number of possible L2 queues | |
726 | * | |
727 | * If the maximum number of FP-SB available is X then: | |
728 | * a. If CNIC is supported it consumes 1 FP-SB thus the max number of | |
729 | * regular L2 queues is Y=X-1 | |
730 | * b. in MF mode the actual number of L2 queues is Y= (X-1/MF_factor) | |
731 | * c. If the FCoE L2 queue is supported the actual number of L2 queues | |
732 | * is Y+1 | |
733 | * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for | |
734 | * slow-path interrupts) or Y+2 if CNIC is supported (one additional | |
735 | * FP interrupt context for the CNIC). | |
736 | * e. The number of HW context (CID count) is always X or X+1 if FCoE | |
737 | * L2 queue is supported. the cid for the FCoE L2 queue is always X. | |
738 | */ | |
739 | ||
740 | #define FP_SB_MAX_E1x 16 /* fast-path interrupt contexts E1x */ | |
f2e0899f | 741 | #define FP_SB_MAX_E2 16 /* fast-path interrupt contexts E2 */ |
523224a3 DK |
742 | |
743 | /* | |
744 | * cid_cnt paramter below refers to the value returned by | |
745 | * 'bnx2x_get_l2_cid_count()' routine | |
746 | */ | |
747 | ||
748 | /* | |
749 | * The number of FP context allocated by the driver == max number of regular | |
750 | * L2 queues + 1 for the FCoE L2 queue | |
751 | */ | |
752 | #define L2_FP_COUNT(cid_cnt) ((cid_cnt) - CNIC_CONTEXT_USE) | |
34f80b04 | 753 | |
ec6ba945 VZ |
754 | /* |
755 | * The number of FP-SB allocated by the driver == max number of regular L2 | |
756 | * queues + 1 for the CNIC which also consumes an FP-SB | |
757 | */ | |
758 | #define FP_SB_COUNT(cid_cnt) ((cid_cnt) - FCOE_CONTEXT_USE) | |
759 | #define NUM_IGU_SB_REQUIRED(cid_cnt) \ | |
760 | (FP_SB_COUNT(cid_cnt) - NONE_ETH_CONTEXT_USE) | |
761 | ||
34f80b04 EG |
762 | union cdu_context { |
763 | struct eth_context eth; | |
764 | char pad[1024]; | |
765 | }; | |
766 | ||
523224a3 DK |
767 | /* CDU host DB constants */ |
768 | #define CDU_ILT_PAGE_SZ_HW 3 | |
769 | #define CDU_ILT_PAGE_SZ (4096 << CDU_ILT_PAGE_SZ_HW) /* 32K */ | |
770 | #define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context)) | |
771 | ||
772 | #ifdef BCM_CNIC | |
773 | #define CNIC_ISCSI_CID_MAX 256 | |
ec6ba945 VZ |
774 | #define CNIC_FCOE_CID_MAX 2048 |
775 | #define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX) | |
523224a3 DK |
776 | #define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS) |
777 | #endif | |
778 | ||
779 | #define QM_ILT_PAGE_SZ_HW 3 | |
780 | #define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 32K */ | |
781 | #define QM_CID_ROUND 1024 | |
782 | ||
783 | #ifdef BCM_CNIC | |
784 | /* TM (timers) host DB constants */ | |
785 | #define TM_ILT_PAGE_SZ_HW 2 | |
786 | #define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 16K */ | |
787 | /* #define TM_CONN_NUM (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */ | |
788 | #define TM_CONN_NUM 1024 | |
789 | #define TM_ILT_SZ (8 * TM_CONN_NUM) | |
790 | #define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ) | |
791 | ||
792 | /* SRC (Searcher) host DB constants */ | |
793 | #define SRC_ILT_PAGE_SZ_HW 3 | |
794 | #define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 32K */ | |
795 | #define SRC_HASH_BITS 10 | |
796 | #define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */ | |
797 | #define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM) | |
798 | #define SRC_T2_SZ SRC_ILT_SZ | |
799 | #define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ) | |
800 | #endif | |
801 | ||
bb2a0f7a | 802 | #define MAX_DMAE_C 8 |
34f80b04 EG |
803 | |
804 | /* DMA memory not used in fastpath */ | |
805 | struct bnx2x_slowpath { | |
34f80b04 EG |
806 | struct eth_stats_query fw_stats; |
807 | struct mac_configuration_cmd mac_config; | |
808 | struct mac_configuration_cmd mcast_config; | |
523224a3 | 809 | struct client_init_ramrod_data client_init_data; |
34f80b04 EG |
810 | |
811 | /* used by dmae command executer */ | |
812 | struct dmae_command dmae[MAX_DMAE_C]; | |
813 | ||
bb2a0f7a YG |
814 | u32 stats_comp; |
815 | union mac_stats mac_stats; | |
816 | struct nig_stats nig_stats; | |
817 | struct host_port_stats port_stats; | |
818 | struct host_func_stats func_stats; | |
6fe49bb9 | 819 | struct host_func_stats func_stats_base; |
34f80b04 EG |
820 | |
821 | u32 wb_comp; | |
34f80b04 EG |
822 | u32 wb_data[4]; |
823 | }; | |
824 | ||
825 | #define bnx2x_sp(bp, var) (&bp->slowpath->var) | |
826 | #define bnx2x_sp_mapping(bp, var) \ | |
827 | (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var)) | |
828 | ||
829 | ||
830 | /* attn group wiring */ | |
831 | #define MAX_DYNAMIC_ATTN_GRPS 8 | |
832 | ||
833 | struct attn_route { | |
f2e0899f | 834 | u32 sig[5]; |
34f80b04 EG |
835 | }; |
836 | ||
523224a3 DK |
837 | struct iro { |
838 | u32 base; | |
839 | u16 m1; | |
840 | u16 m2; | |
841 | u16 m3; | |
842 | u16 size; | |
843 | }; | |
844 | ||
845 | struct hw_context { | |
846 | union cdu_context *vcxt; | |
847 | dma_addr_t cxt_mapping; | |
848 | size_t size; | |
849 | }; | |
850 | ||
851 | /* forward */ | |
852 | struct bnx2x_ilt; | |
853 | ||
72fd0718 VZ |
854 | typedef enum { |
855 | BNX2X_RECOVERY_DONE, | |
856 | BNX2X_RECOVERY_INIT, | |
857 | BNX2X_RECOVERY_WAIT, | |
858 | } bnx2x_recovery_state_t; | |
859 | ||
523224a3 DK |
860 | /** |
861 | * Event queue (EQ or event ring) MC hsi | |
862 | * NUM_EQ_PAGES and EQ_DESC_CNT_PAGE must be power of 2 | |
863 | */ | |
864 | #define NUM_EQ_PAGES 1 | |
865 | #define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem)) | |
866 | #define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1) | |
867 | #define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES) | |
868 | #define EQ_DESC_MASK (NUM_EQ_DESC - 1) | |
869 | #define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2) | |
870 | ||
871 | /* depends on EQ_DESC_CNT_PAGE being a power of 2 */ | |
872 | #define NEXT_EQ_IDX(x) ((((x) & EQ_DESC_MAX_PAGE) == \ | |
873 | (EQ_DESC_MAX_PAGE - 1)) ? (x) + 2 : (x) + 1) | |
874 | ||
875 | /* depends on the above and on NUM_EQ_PAGES being a power of 2 */ | |
876 | #define EQ_DESC(x) ((x) & EQ_DESC_MASK) | |
877 | ||
878 | #define BNX2X_EQ_INDEX \ | |
879 | (&bp->def_status_blk->sp_sb.\ | |
880 | index_values[HC_SP_INDEX_EQ_CONS]) | |
881 | ||
34f80b04 EG |
882 | struct bnx2x { |
883 | /* Fields used in the tx and intr/napi performance paths | |
884 | * are grouped together in the beginning of the structure | |
885 | */ | |
523224a3 | 886 | struct bnx2x_fastpath *fp; |
34f80b04 EG |
887 | void __iomem *regview; |
888 | void __iomem *doorbells; | |
523224a3 | 889 | u16 db_size; |
34f80b04 EG |
890 | |
891 | struct net_device *dev; | |
892 | struct pci_dev *pdev; | |
893 | ||
523224a3 DK |
894 | struct iro *iro_arr; |
895 | #define IRO (bp->iro_arr) | |
896 | ||
34f80b04 | 897 | atomic_t intr_sem; |
72fd0718 VZ |
898 | |
899 | bnx2x_recovery_state_t recovery_state; | |
900 | int is_leader; | |
523224a3 | 901 | struct msix_entry *msix_table; |
8badd27a EG |
902 | #define INT_MODE_INTx 1 |
903 | #define INT_MODE_MSI 2 | |
34f80b04 EG |
904 | |
905 | int tx_ring_size; | |
906 | ||
34f80b04 | 907 | u32 rx_csum; |
437cf2f1 | 908 | u32 rx_buf_size; |
523224a3 DK |
909 | /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */ |
910 | #define ETH_OVREHEAD (ETH_HLEN + 8 + 8) | |
34f80b04 EG |
911 | #define ETH_MIN_PACKET_SIZE 60 |
912 | #define ETH_MAX_PACKET_SIZE 1500 | |
913 | #define ETH_MAX_JUMBO_PACKET_SIZE 9600 | |
a2fbb9ea | 914 | |
0f00846d EG |
915 | /* Max supported alignment is 256 (8 shift) */ |
916 | #define BNX2X_RX_ALIGN_SHIFT ((L1_CACHE_SHIFT < 8) ? \ | |
917 | L1_CACHE_SHIFT : 8) | |
918 | #define BNX2X_RX_ALIGN (1 << BNX2X_RX_ALIGN_SHIFT) | |
523224a3 | 919 | #define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5) |
0f00846d | 920 | |
523224a3 DK |
921 | struct host_sp_status_block *def_status_blk; |
922 | #define DEF_SB_IGU_ID 16 | |
923 | #define DEF_SB_ID HC_SP_SB_ID | |
924 | __le16 def_idx; | |
4781bfad | 925 | __le16 def_att_idx; |
34f80b04 EG |
926 | u32 attn_state; |
927 | struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS]; | |
34f80b04 EG |
928 | |
929 | /* slow path ring */ | |
930 | struct eth_spe *spq; | |
931 | dma_addr_t spq_mapping; | |
932 | u16 spq_prod_idx; | |
933 | struct eth_spe *spq_prod_bd; | |
934 | struct eth_spe *spq_last_bd; | |
4781bfad | 935 | __le16 *dsb_sp_prod; |
8fe23fbd | 936 | atomic_t spq_left; /* serialize spq */ |
34f80b04 EG |
937 | /* used to synchronize spq accesses */ |
938 | spinlock_t spq_lock; | |
939 | ||
523224a3 DK |
940 | /* event queue */ |
941 | union event_ring_elem *eq_ring; | |
942 | dma_addr_t eq_mapping; | |
943 | u16 eq_prod; | |
944 | u16 eq_cons; | |
945 | __le16 *eq_cons_sb; | |
946 | ||
bb2a0f7a YG |
947 | /* Flags for marking that there is a STAT_QUERY or |
948 | SET_MAC ramrod pending */ | |
e665bfda MC |
949 | int stats_pending; |
950 | int set_mac_pending; | |
34f80b04 | 951 | |
33471629 | 952 | /* End of fields used in the performance code paths */ |
34f80b04 EG |
953 | |
954 | int panic; | |
7995c64e | 955 | int msg_enable; |
34f80b04 EG |
956 | |
957 | u32 flags; | |
958 | #define PCIX_FLAG 1 | |
959 | #define PCI_32BIT_FLAG 2 | |
1c06328c | 960 | #define ONE_PORT_FLAG 4 |
34f80b04 EG |
961 | #define NO_WOL_FLAG 8 |
962 | #define USING_DAC_FLAG 0x10 | |
963 | #define USING_MSIX_FLAG 0x20 | |
8badd27a | 964 | #define USING_MSI_FLAG 0x40 |
d6214d7a | 965 | |
7a9b2557 | 966 | #define TPA_ENABLE_FLAG 0x80 |
34f80b04 | 967 | #define NO_MCP_FLAG 0x100 |
d6214d7a | 968 | #define DISABLE_MSI_FLAG 0x200 |
34f80b04 | 969 | #define BP_NOMCP(bp) (bp->flags & NO_MCP_FLAG) |
f34d28ea | 970 | #define MF_FUNC_DIS 0x1000 |
ec6ba945 VZ |
971 | #define FCOE_MACS_SET 0x2000 |
972 | #define NO_FCOE_FLAG 0x4000 | |
973 | ||
974 | #define NO_FCOE(bp) ((bp)->flags & NO_FCOE_FLAG) | |
34f80b04 | 975 | |
f2e0899f DK |
976 | int pf_num; /* absolute PF number */ |
977 | int pfid; /* per-path PF number */ | |
523224a3 | 978 | int base_fw_ndsb; |
f2e0899f DK |
979 | #define BP_PATH(bp) (!CHIP_IS_E2(bp) ? \ |
980 | 0 : (bp->pf_num & 1)) | |
981 | #define BP_PORT(bp) (bp->pfid & 1) | |
982 | #define BP_FUNC(bp) (bp->pfid) | |
983 | #define BP_ABS_FUNC(bp) (bp->pf_num) | |
984 | #define BP_E1HVN(bp) (bp->pfid >> 1) | |
985 | #define BP_VN(bp) (CHIP_MODE_IS_4_PORT(bp) ? \ | |
986 | 0 : BP_E1HVN(bp)) | |
34f80b04 | 987 | #define BP_L_ID(bp) (BP_E1HVN(bp) << 2) |
f2e0899f DK |
988 | #define BP_FW_MB_IDX(bp) (BP_PORT(bp) +\ |
989 | BP_VN(bp) * (CHIP_IS_E1x(bp) ? 2 : 1)) | |
34f80b04 | 990 | |
37b091ba MC |
991 | #ifdef BCM_CNIC |
992 | #define BCM_CNIC_CID_START 16 | |
993 | #define BCM_ISCSI_ETH_CL_ID 17 | |
994 | #endif | |
995 | ||
34f80b04 EG |
996 | int pm_cap; |
997 | int pcie_cap; | |
8d5726c4 | 998 | int mrrs; |
34f80b04 | 999 | |
1cf167f2 | 1000 | struct delayed_work sp_task; |
72fd0718 | 1001 | struct delayed_work reset_task; |
34f80b04 | 1002 | struct timer_list timer; |
34f80b04 EG |
1003 | int current_interval; |
1004 | ||
1005 | u16 fw_seq; | |
1006 | u16 fw_drv_pulse_wr_seq; | |
1007 | u32 func_stx; | |
1008 | ||
1009 | struct link_params link_params; | |
1010 | struct link_vars link_vars; | |
01cd4528 | 1011 | struct mdio_if_info mdio; |
a2fbb9ea | 1012 | |
34f80b04 EG |
1013 | struct bnx2x_common common; |
1014 | struct bnx2x_port port; | |
1015 | ||
8a1c38d1 EG |
1016 | struct cmng_struct_per_port cmng; |
1017 | u32 vn_weight_sum; | |
1018 | ||
f2e0899f DK |
1019 | u32 mf_config[E1HVN_MAX]; |
1020 | u32 mf2_config[E2_FUNC_MAX]; | |
fb3bff17 DK |
1021 | u16 mf_ov; |
1022 | u8 mf_mode; | |
f85582f8 | 1023 | #define IS_MF(bp) (bp->mf_mode != 0) |
0793f83f DK |
1024 | #define IS_MF_SI(bp) (bp->mf_mode == MULTI_FUNCTION_SI) |
1025 | #define IS_MF_SD(bp) (bp->mf_mode == MULTI_FUNCTION_SD) | |
a2fbb9ea | 1026 | |
f1410647 ET |
1027 | u8 wol; |
1028 | ||
34f80b04 | 1029 | int rx_ring_size; |
a2fbb9ea | 1030 | |
34f80b04 EG |
1031 | u16 tx_quick_cons_trip_int; |
1032 | u16 tx_quick_cons_trip; | |
1033 | u16 tx_ticks_int; | |
1034 | u16 tx_ticks; | |
a2fbb9ea | 1035 | |
34f80b04 EG |
1036 | u16 rx_quick_cons_trip_int; |
1037 | u16 rx_quick_cons_trip; | |
1038 | u16 rx_ticks_int; | |
1039 | u16 rx_ticks; | |
cdaa7cb8 VZ |
1040 | /* Maximal coalescing timeout in us */ |
1041 | #define BNX2X_MAX_COALESCE_TOUT (0xf0*12) | |
a2fbb9ea | 1042 | |
34f80b04 | 1043 | u32 lin_cnt; |
a2fbb9ea | 1044 | |
34f80b04 | 1045 | int state; |
356e2385 | 1046 | #define BNX2X_STATE_CLOSED 0 |
34f80b04 EG |
1047 | #define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000 |
1048 | #define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000 | |
a2fbb9ea | 1049 | #define BNX2X_STATE_OPEN 0x3000 |
34f80b04 | 1050 | #define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000 |
a2fbb9ea ET |
1051 | #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000 |
1052 | #define BNX2X_STATE_CLOSING_WAIT4_UNLOAD 0x6000 | |
523224a3 | 1053 | #define BNX2X_STATE_FUNC_STARTED 0x7000 |
34f80b04 EG |
1054 | #define BNX2X_STATE_DIAG 0xe000 |
1055 | #define BNX2X_STATE_ERROR 0xf000 | |
a2fbb9ea | 1056 | |
555f6c78 | 1057 | int multi_mode; |
54b9ddaa | 1058 | int num_queues; |
5d7cd496 DK |
1059 | int disable_tpa; |
1060 | int int_mode; | |
a2fbb9ea | 1061 | |
523224a3 DK |
1062 | struct tstorm_eth_mac_filter_config mac_filters; |
1063 | #define BNX2X_ACCEPT_NONE 0x0000 | |
1064 | #define BNX2X_ACCEPT_UNICAST 0x0001 | |
1065 | #define BNX2X_ACCEPT_MULTICAST 0x0002 | |
1066 | #define BNX2X_ACCEPT_ALL_UNICAST 0x0004 | |
1067 | #define BNX2X_ACCEPT_ALL_MULTICAST 0x0008 | |
1068 | #define BNX2X_ACCEPT_BROADCAST 0x0010 | |
0793f83f | 1069 | #define BNX2X_ACCEPT_UNMATCHED_UCAST 0x0020 |
523224a3 DK |
1070 | #define BNX2X_PROMISCUOUS_MODE 0x10000 |
1071 | ||
34f80b04 EG |
1072 | u32 rx_mode; |
1073 | #define BNX2X_RX_MODE_NONE 0 | |
1074 | #define BNX2X_RX_MODE_NORMAL 1 | |
1075 | #define BNX2X_RX_MODE_ALLMULTI 2 | |
1076 | #define BNX2X_RX_MODE_PROMISC 3 | |
1077 | #define BNX2X_MAX_MULTICAST 64 | |
1078 | #define BNX2X_MAX_EMUL_MULTI 16 | |
a2fbb9ea | 1079 | |
523224a3 DK |
1080 | u8 igu_dsb_id; |
1081 | u8 igu_base_sb; | |
1082 | u8 igu_sb_cnt; | |
34f80b04 | 1083 | dma_addr_t def_status_blk_mapping; |
a2fbb9ea | 1084 | |
34f80b04 EG |
1085 | struct bnx2x_slowpath *slowpath; |
1086 | dma_addr_t slowpath_mapping; | |
523224a3 DK |
1087 | struct hw_context context; |
1088 | ||
1089 | struct bnx2x_ilt *ilt; | |
1090 | #define BP_ILT(bp) ((bp)->ilt) | |
1091 | #define ILT_MAX_LINES 128 | |
1092 | ||
1093 | int l2_cid_count; | |
1094 | #define L2_ILT_LINES(bp) (DIV_ROUND_UP((bp)->l2_cid_count, \ | |
1095 | ILT_PAGE_CIDS)) | |
1096 | #define BNX2X_DB_SIZE(bp) ((bp)->l2_cid_count * (1 << BNX2X_DB_SHIFT)) | |
1097 | ||
1098 | int qm_cid_count; | |
a2fbb9ea | 1099 | |
a18f5128 EG |
1100 | int dropless_fc; |
1101 | ||
37b091ba MC |
1102 | #ifdef BCM_CNIC |
1103 | u32 cnic_flags; | |
1104 | #define BNX2X_CNIC_FLAG_MAC_SET 1 | |
37b091ba MC |
1105 | void *t2; |
1106 | dma_addr_t t2_mapping; | |
37b091ba MC |
1107 | struct cnic_ops *cnic_ops; |
1108 | void *cnic_data; | |
1109 | u32 cnic_tag; | |
1110 | struct cnic_eth_dev cnic_eth_dev; | |
523224a3 | 1111 | union host_hc_status_block cnic_sb; |
37b091ba | 1112 | dma_addr_t cnic_sb_mapping; |
523224a3 DK |
1113 | #define CNIC_SB_ID(bp) ((bp)->base_fw_ndsb + BP_L_ID(bp)) |
1114 | #define CNIC_IGU_SB_ID(bp) ((bp)->igu_base_sb) | |
37b091ba MC |
1115 | struct eth_spe *cnic_kwq; |
1116 | struct eth_spe *cnic_kwq_prod; | |
1117 | struct eth_spe *cnic_kwq_cons; | |
1118 | struct eth_spe *cnic_kwq_last; | |
1119 | u16 cnic_kwq_pending; | |
1120 | u16 cnic_spq_pending; | |
1121 | struct mutex cnic_mutex; | |
ec6ba945 VZ |
1122 | u8 iscsi_mac[ETH_ALEN]; |
1123 | u8 fip_mac[ETH_ALEN]; | |
37b091ba MC |
1124 | #endif |
1125 | ||
ad8d3948 EG |
1126 | int dmae_ready; |
1127 | /* used to synchronize dmae accesses */ | |
1128 | struct mutex dmae_mutex; | |
ad8d3948 | 1129 | |
c4ff7cbf EG |
1130 | /* used to protect the FW mail box */ |
1131 | struct mutex fw_mb_mutex; | |
1132 | ||
bb2a0f7a YG |
1133 | /* used to synchronize stats collecting */ |
1134 | int stats_state; | |
a13773a5 VZ |
1135 | |
1136 | /* used for synchronization of concurrent threads statistics handling */ | |
1137 | spinlock_t stats_lock; | |
1138 | ||
bb2a0f7a YG |
1139 | /* used by dmae command loader */ |
1140 | struct dmae_command stats_dmae; | |
1141 | int executer_idx; | |
ad8d3948 | 1142 | |
bb2a0f7a | 1143 | u16 stats_counter; |
bb2a0f7a YG |
1144 | struct bnx2x_eth_stats eth_stats; |
1145 | ||
1146 | struct z_stream_s *strm; | |
1147 | void *gunzip_buf; | |
1148 | dma_addr_t gunzip_mapping; | |
1149 | int gunzip_outlen; | |
ad8d3948 | 1150 | #define FW_BUF_SIZE 0x8000 |
573f2035 EG |
1151 | #define GUNZIP_BUF(bp) (bp->gunzip_buf) |
1152 | #define GUNZIP_PHYS(bp) (bp->gunzip_mapping) | |
1153 | #define GUNZIP_OUTLEN(bp) (bp->gunzip_outlen) | |
a2fbb9ea | 1154 | |
ab6ad5a4 | 1155 | struct raw_op *init_ops; |
94a78b79 | 1156 | /* Init blocks offsets inside init_ops */ |
ab6ad5a4 | 1157 | u16 *init_ops_offsets; |
94a78b79 | 1158 | /* Data blob - has 32 bit granularity */ |
ab6ad5a4 | 1159 | u32 *init_data; |
94a78b79 | 1160 | /* Zipped PRAM blobs - raw data */ |
ab6ad5a4 EG |
1161 | const u8 *tsem_int_table_data; |
1162 | const u8 *tsem_pram_data; | |
1163 | const u8 *usem_int_table_data; | |
1164 | const u8 *usem_pram_data; | |
1165 | const u8 *xsem_int_table_data; | |
1166 | const u8 *xsem_pram_data; | |
1167 | const u8 *csem_int_table_data; | |
1168 | const u8 *csem_pram_data; | |
573f2035 EG |
1169 | #define INIT_OPS(bp) (bp->init_ops) |
1170 | #define INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets) | |
1171 | #define INIT_DATA(bp) (bp->init_data) | |
1172 | #define INIT_TSEM_INT_TABLE_DATA(bp) (bp->tsem_int_table_data) | |
1173 | #define INIT_TSEM_PRAM_DATA(bp) (bp->tsem_pram_data) | |
1174 | #define INIT_USEM_INT_TABLE_DATA(bp) (bp->usem_int_table_data) | |
1175 | #define INIT_USEM_PRAM_DATA(bp) (bp->usem_pram_data) | |
1176 | #define INIT_XSEM_INT_TABLE_DATA(bp) (bp->xsem_int_table_data) | |
1177 | #define INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data) | |
1178 | #define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data) | |
1179 | #define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data) | |
1180 | ||
34f24c7f | 1181 | char fw_ver[32]; |
ab6ad5a4 | 1182 | const struct firmware *firmware; |
a2fbb9ea ET |
1183 | }; |
1184 | ||
523224a3 DK |
1185 | /** |
1186 | * Init queue/func interface | |
1187 | */ | |
1188 | /* queue init flags */ | |
1189 | #define QUEUE_FLG_TPA 0x0001 | |
1190 | #define QUEUE_FLG_CACHE_ALIGN 0x0002 | |
1191 | #define QUEUE_FLG_STATS 0x0004 | |
1192 | #define QUEUE_FLG_OV 0x0008 | |
1193 | #define QUEUE_FLG_VLAN 0x0010 | |
1194 | #define QUEUE_FLG_COS 0x0020 | |
1195 | #define QUEUE_FLG_HC 0x0040 | |
1196 | #define QUEUE_FLG_DHC 0x0080 | |
1197 | #define QUEUE_FLG_OOO 0x0100 | |
1198 | ||
1199 | #define QUEUE_DROP_IP_CS_ERR TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR | |
1200 | #define QUEUE_DROP_TCP_CS_ERR TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR | |
1201 | #define QUEUE_DROP_TTL0 TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0 | |
1202 | #define QUEUE_DROP_UDP_CS_ERR TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR | |
1203 | ||
1204 | ||
1205 | ||
1206 | /* rss capabilities */ | |
1207 | #define RSS_IPV4_CAP 0x0001 | |
1208 | #define RSS_IPV4_TCP_CAP 0x0002 | |
1209 | #define RSS_IPV6_CAP 0x0004 | |
1210 | #define RSS_IPV6_TCP_CAP 0x0008 | |
a2fbb9ea | 1211 | |
54b9ddaa | 1212 | #define BNX2X_NUM_QUEUES(bp) (bp->num_queues) |
ec6ba945 VZ |
1213 | #define BNX2X_NUM_ETH_QUEUES(bp) (BNX2X_NUM_QUEUES(bp) - NONE_ETH_CONTEXT_USE) |
1214 | ||
1215 | /* ethtool statistics are displayed for all regular ethernet queues and the | |
1216 | * fcoe L2 queue if not disabled | |
1217 | */ | |
1218 | #define BNX2X_NUM_STAT_QUEUES(bp) (NO_FCOE(bp) ? BNX2X_NUM_ETH_QUEUES(bp) : \ | |
1219 | (BNX2X_NUM_ETH_QUEUES(bp) + FCOE_CONTEXT_USE)) | |
1220 | ||
54b9ddaa | 1221 | #define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1) |
3196a88a | 1222 | |
f2e0899f | 1223 | #define BNX2X_MAX_QUEUES(bp) (bp->igu_sb_cnt - CNIC_CONTEXT_USE) |
523224a3 DK |
1224 | |
1225 | #define RSS_IPV4_CAP_MASK \ | |
1226 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY | |
1227 | ||
1228 | #define RSS_IPV4_TCP_CAP_MASK \ | |
1229 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | |
1230 | ||
1231 | #define RSS_IPV6_CAP_MASK \ | |
1232 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY | |
1233 | ||
1234 | #define RSS_IPV6_TCP_CAP_MASK \ | |
1235 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | |
1236 | ||
1237 | /* func init flags */ | |
030f3356 DK |
1238 | #define FUNC_FLG_STATS 0x0001 |
1239 | #define FUNC_FLG_TPA 0x0002 | |
1240 | #define FUNC_FLG_SPQ 0x0004 | |
1241 | #define FUNC_FLG_LEADING 0x0008 /* PF only */ | |
523224a3 DK |
1242 | |
1243 | struct rxq_pause_params { | |
1244 | u16 bd_th_lo; | |
1245 | u16 bd_th_hi; | |
1246 | u16 rcq_th_lo; | |
1247 | u16 rcq_th_hi; | |
1248 | u16 sge_th_lo; /* valid iff QUEUE_FLG_TPA */ | |
1249 | u16 sge_th_hi; /* valid iff QUEUE_FLG_TPA */ | |
1250 | u16 pri_map; | |
1251 | }; | |
1252 | ||
1253 | struct bnx2x_rxq_init_params { | |
1254 | /* cxt*/ | |
1255 | struct eth_context *cxt; | |
1256 | ||
1257 | /* dma */ | |
1258 | dma_addr_t dscr_map; | |
1259 | dma_addr_t sge_map; | |
1260 | dma_addr_t rcq_map; | |
1261 | dma_addr_t rcq_np_map; | |
1262 | ||
1263 | u16 flags; | |
1264 | u16 drop_flags; | |
1265 | u16 mtu; | |
1266 | u16 buf_sz; | |
1267 | u16 fw_sb_id; | |
1268 | u16 cl_id; | |
1269 | u16 spcl_id; | |
1270 | u16 cl_qzone_id; | |
1271 | ||
1272 | /* valid iff QUEUE_FLG_STATS */ | |
1273 | u16 stat_id; | |
1274 | ||
1275 | /* valid iff QUEUE_FLG_TPA */ | |
1276 | u16 tpa_agg_sz; | |
1277 | u16 sge_buf_sz; | |
1278 | u16 max_sges_pkt; | |
1279 | ||
1280 | /* valid iff QUEUE_FLG_CACHE_ALIGN */ | |
1281 | u8 cache_line_log; | |
1282 | ||
1283 | u8 sb_cq_index; | |
1284 | u32 cid; | |
1285 | ||
1286 | /* desired interrupts per sec. valid iff QUEUE_FLG_HC */ | |
1287 | u32 hc_rate; | |
1288 | }; | |
1289 | ||
1290 | struct bnx2x_txq_init_params { | |
1291 | /* cxt*/ | |
1292 | struct eth_context *cxt; | |
1293 | ||
1294 | /* dma */ | |
1295 | dma_addr_t dscr_map; | |
1296 | ||
1297 | u16 flags; | |
1298 | u16 fw_sb_id; | |
1299 | u8 sb_cq_index; | |
1300 | u8 cos; /* valid iff QUEUE_FLG_COS */ | |
1301 | u16 stat_id; /* valid iff QUEUE_FLG_STATS */ | |
1302 | u16 traffic_type; | |
1303 | u32 cid; | |
1304 | u16 hc_rate; /* desired interrupts per sec.*/ | |
1305 | /* valid iff QUEUE_FLG_HC */ | |
1306 | ||
1307 | }; | |
1308 | ||
1309 | struct bnx2x_client_ramrod_params { | |
1310 | int *pstate; | |
1311 | int state; | |
1312 | u16 index; | |
1313 | u16 cl_id; | |
1314 | u32 cid; | |
1315 | u8 poll; | |
ec6ba945 | 1316 | #define CLIENT_IS_FCOE 0x01 |
523224a3 DK |
1317 | #define CLIENT_IS_LEADING_RSS 0x02 |
1318 | u8 flags; | |
1319 | }; | |
1320 | ||
1321 | struct bnx2x_client_init_params { | |
1322 | struct rxq_pause_params pause; | |
1323 | struct bnx2x_rxq_init_params rxq_params; | |
1324 | struct bnx2x_txq_init_params txq_params; | |
1325 | struct bnx2x_client_ramrod_params ramrod_params; | |
1326 | }; | |
1327 | ||
1328 | struct bnx2x_rss_params { | |
1329 | int mode; | |
1330 | u16 cap; | |
1331 | u16 result_mask; | |
1332 | }; | |
1333 | ||
1334 | struct bnx2x_func_init_params { | |
1335 | ||
1336 | /* rss */ | |
1337 | struct bnx2x_rss_params *rss; /* valid iff FUNC_FLG_RSS */ | |
1338 | ||
1339 | /* dma */ | |
1340 | dma_addr_t fw_stat_map; /* valid iff FUNC_FLG_STATS */ | |
1341 | dma_addr_t spq_map; /* valid iff FUNC_FLG_SPQ */ | |
1342 | ||
1343 | u16 func_flgs; | |
1344 | u16 func_id; /* abs fid */ | |
1345 | u16 pf_id; | |
1346 | u16 spq_prod; /* valid iff FUNC_FLG_SPQ */ | |
1347 | }; | |
1348 | ||
ec6ba945 VZ |
1349 | #define for_each_eth_queue(bp, var) \ |
1350 | for (var = 0; var < BNX2X_NUM_ETH_QUEUES(bp); var++) | |
1351 | ||
1352 | #define for_each_nondefault_eth_queue(bp, var) \ | |
1353 | for (var = 1; var < BNX2X_NUM_ETH_QUEUES(bp); var++) | |
1354 | ||
1355 | #define for_each_napi_queue(bp, var) \ | |
1356 | for (var = 0; \ | |
1357 | var < BNX2X_NUM_ETH_QUEUES(bp) + FCOE_CONTEXT_USE; var++) \ | |
1358 | if (skip_queue(bp, var)) \ | |
1359 | continue; \ | |
1360 | else | |
1361 | ||
555f6c78 | 1362 | #define for_each_queue(bp, var) \ |
ec6ba945 VZ |
1363 | for (var = 0; var < BNX2X_NUM_QUEUES(bp); var++) \ |
1364 | if (skip_queue(bp, var)) \ | |
1365 | continue; \ | |
1366 | else | |
1367 | ||
1368 | #define for_each_rx_queue(bp, var) \ | |
1369 | for (var = 0; var < BNX2X_NUM_QUEUES(bp); var++) \ | |
1370 | if (skip_rx_queue(bp, var)) \ | |
1371 | continue; \ | |
1372 | else | |
1373 | ||
1374 | #define for_each_tx_queue(bp, var) \ | |
1375 | for (var = 0; var < BNX2X_NUM_QUEUES(bp); var++) \ | |
1376 | if (skip_tx_queue(bp, var)) \ | |
1377 | continue; \ | |
1378 | else | |
1379 | ||
3196a88a | 1380 | #define for_each_nondefault_queue(bp, var) \ |
ec6ba945 VZ |
1381 | for (var = 1; var < BNX2X_NUM_QUEUES(bp); var++) \ |
1382 | if (skip_queue(bp, var)) \ | |
1383 | continue; \ | |
1384 | else | |
3196a88a | 1385 | |
ec6ba945 VZ |
1386 | /* skip rx queue |
1387 | * if FCOE l2 support is diabled and this is the fcoe L2 queue | |
1388 | */ | |
1389 | #define skip_rx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) | |
1390 | ||
1391 | /* skip tx queue | |
1392 | * if FCOE l2 support is diabled and this is the fcoe L2 queue | |
1393 | */ | |
1394 | #define skip_tx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) | |
1395 | ||
1396 | #define skip_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) | |
3196a88a | 1397 | |
f85582f8 DK |
1398 | #define WAIT_RAMROD_POLL 0x01 |
1399 | #define WAIT_RAMROD_COMMON 0x02 | |
f85582f8 DK |
1400 | |
1401 | /* dmae */ | |
c18487ee YR |
1402 | void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32); |
1403 | void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, | |
1404 | u32 len32); | |
f85582f8 DK |
1405 | void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx); |
1406 | u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type); | |
1407 | u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode); | |
1408 | u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type, | |
1409 | bool with_comp, u8 comp_type); | |
1410 | ||
4acac6a5 | 1411 | int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port); |
17de50b7 | 1412 | int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port); |
4acac6a5 | 1413 | int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port); |
a22f0788 | 1414 | u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param); |
f85582f8 | 1415 | |
de0c62db DK |
1416 | void bnx2x_calc_fc_adv(struct bnx2x *bp); |
1417 | int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, | |
1418 | u32 data_hi, u32 data_lo, int common); | |
1419 | void bnx2x_update_coalesce(struct bnx2x *bp); | |
a22f0788 | 1420 | int bnx2x_get_link_cfg_idx(struct bnx2x *bp); |
f85582f8 | 1421 | |
34f80b04 EG |
1422 | static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms, |
1423 | int wait) | |
1424 | { | |
1425 | u32 val; | |
1426 | ||
1427 | do { | |
1428 | val = REG_RD(bp, reg); | |
1429 | if (val == expected) | |
1430 | break; | |
1431 | ms -= wait; | |
1432 | msleep(wait); | |
1433 | ||
1434 | } while (ms > 0); | |
1435 | ||
1436 | return val; | |
1437 | } | |
f85582f8 | 1438 | |
523224a3 DK |
1439 | #define BNX2X_ILT_ZALLOC(x, y, size) \ |
1440 | do { \ | |
d245a111 | 1441 | x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \ |
523224a3 DK |
1442 | if (x) \ |
1443 | memset(x, 0, size); \ | |
1444 | } while (0) | |
1445 | ||
1446 | #define BNX2X_ILT_FREE(x, y, size) \ | |
1447 | do { \ | |
1448 | if (x) { \ | |
d245a111 | 1449 | dma_free_coherent(&bp->pdev->dev, size, x, y); \ |
523224a3 DK |
1450 | x = NULL; \ |
1451 | y = 0; \ | |
1452 | } \ | |
1453 | } while (0) | |
1454 | ||
1455 | #define ILOG2(x) (ilog2((x))) | |
1456 | ||
1457 | #define ILT_NUM_PAGE_ENTRIES (3072) | |
1458 | /* In 57710/11 we use whole table since we have 8 func | |
f85582f8 DK |
1459 | * In 57712 we have only 4 func, but use same size per func, then only half of |
1460 | * the table in use | |
523224a3 DK |
1461 | */ |
1462 | #define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES/8) | |
1463 | ||
1464 | #define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC) | |
1465 | /* | |
1466 | * the phys address is shifted right 12 bits and has an added | |
1467 | * 1=valid bit added to the 53rd bit | |
1468 | * then since this is a wide register(TM) | |
1469 | * we split it into two 32 bit writes | |
1470 | */ | |
1471 | #define ONCHIP_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF)) | |
1472 | #define ONCHIP_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44))) | |
34f80b04 | 1473 | |
34f80b04 EG |
1474 | /* load/unload mode */ |
1475 | #define LOAD_NORMAL 0 | |
1476 | #define LOAD_OPEN 1 | |
1477 | #define LOAD_DIAG 2 | |
1478 | #define UNLOAD_NORMAL 0 | |
1479 | #define UNLOAD_CLOSE 1 | |
f85582f8 | 1480 | #define UNLOAD_RECOVERY 2 |
34f80b04 | 1481 | |
bb2a0f7a | 1482 | |
ad8d3948 | 1483 | /* DMAE command defines */ |
f2e0899f DK |
1484 | #define DMAE_TIMEOUT -1 |
1485 | #define DMAE_PCI_ERROR -2 /* E2 and onward */ | |
1486 | #define DMAE_NOT_RDY -3 | |
1487 | #define DMAE_PCI_ERR_FLAG 0x80000000 | |
1488 | ||
1489 | #define DMAE_SRC_PCI 0 | |
1490 | #define DMAE_SRC_GRC 1 | |
1491 | ||
1492 | #define DMAE_DST_NONE 0 | |
1493 | #define DMAE_DST_PCI 1 | |
1494 | #define DMAE_DST_GRC 2 | |
1495 | ||
1496 | #define DMAE_COMP_PCI 0 | |
1497 | #define DMAE_COMP_GRC 1 | |
1498 | ||
1499 | /* E2 and onward - PCI error handling in the completion */ | |
1500 | ||
1501 | #define DMAE_COMP_REGULAR 0 | |
1502 | #define DMAE_COM_SET_ERR 1 | |
ad8d3948 | 1503 | |
f2e0899f DK |
1504 | #define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << \ |
1505 | DMAE_COMMAND_SRC_SHIFT) | |
1506 | #define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << \ | |
1507 | DMAE_COMMAND_SRC_SHIFT) | |
ad8d3948 | 1508 | |
f2e0899f DK |
1509 | #define DMAE_CMD_DST_PCI (DMAE_DST_PCI << \ |
1510 | DMAE_COMMAND_DST_SHIFT) | |
1511 | #define DMAE_CMD_DST_GRC (DMAE_DST_GRC << \ | |
1512 | DMAE_COMMAND_DST_SHIFT) | |
1513 | ||
1514 | #define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << \ | |
1515 | DMAE_COMMAND_C_DST_SHIFT) | |
1516 | #define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << \ | |
1517 | DMAE_COMMAND_C_DST_SHIFT) | |
ad8d3948 EG |
1518 | |
1519 | #define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE | |
1520 | ||
1521 | #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT) | |
1522 | #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT) | |
1523 | #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT) | |
1524 | #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT) | |
1525 | ||
1526 | #define DMAE_CMD_PORT_0 0 | |
1527 | #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT | |
1528 | ||
1529 | #define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET | |
1530 | #define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET | |
1531 | #define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT | |
1532 | ||
f2e0899f DK |
1533 | #define DMAE_SRC_PF 0 |
1534 | #define DMAE_SRC_VF 1 | |
1535 | ||
1536 | #define DMAE_DST_PF 0 | |
1537 | #define DMAE_DST_VF 1 | |
1538 | ||
1539 | #define DMAE_C_SRC 0 | |
1540 | #define DMAE_C_DST 1 | |
1541 | ||
ad8d3948 | 1542 | #define DMAE_LEN32_RD_MAX 0x80 |
02e3c6cb | 1543 | #define DMAE_LEN32_WR_MAX(bp) (CHIP_IS_E1(bp) ? 0x400 : 0x2000) |
ad8d3948 | 1544 | |
f2e0899f DK |
1545 | #define DMAE_COMP_VAL 0x60d0d0ae /* E2 and on - upper bit |
1546 | indicates eror */ | |
ad8d3948 EG |
1547 | |
1548 | #define MAX_DMAE_C_PER_PORT 8 | |
ab6ad5a4 | 1549 | #define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ |
ad8d3948 | 1550 | BP_E1HVN(bp)) |
ab6ad5a4 | 1551 | #define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ |
ad8d3948 EG |
1552 | E1HVN_MAX) |
1553 | ||
25047950 ET |
1554 | /* PCIE link and speed */ |
1555 | #define PCICFG_LINK_WIDTH 0x1f00000 | |
1556 | #define PCICFG_LINK_WIDTH_SHIFT 20 | |
1557 | #define PCICFG_LINK_SPEED 0xf0000 | |
1558 | #define PCICFG_LINK_SPEED_SHIFT 16 | |
a2fbb9ea | 1559 | |
bb2a0f7a | 1560 | |
d3d4f495 | 1561 | #define BNX2X_NUM_TESTS 7 |
bb2a0f7a | 1562 | |
b5bf9068 EG |
1563 | #define BNX2X_PHY_LOOPBACK 0 |
1564 | #define BNX2X_MAC_LOOPBACK 1 | |
1565 | #define BNX2X_PHY_LOOPBACK_FAILED 1 | |
1566 | #define BNX2X_MAC_LOOPBACK_FAILED 2 | |
bb2a0f7a YG |
1567 | #define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \ |
1568 | BNX2X_PHY_LOOPBACK_FAILED) | |
96fc1784 | 1569 | |
7a9b2557 VZ |
1570 | |
1571 | #define STROM_ASSERT_ARRAY_SIZE 50 | |
1572 | ||
96fc1784 | 1573 | |
34f80b04 | 1574 | /* must be used on a CID before placing it on a HW ring */ |
ab6ad5a4 EG |
1575 | #define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \ |
1576 | (BP_E1HVN(bp) << 17) | (x)) | |
7a9b2557 VZ |
1577 | |
1578 | #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe)) | |
1579 | #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1) | |
1580 | ||
1581 | ||
523224a3 | 1582 | #define BNX2X_BTR 4 |
7a9b2557 | 1583 | #define MAX_SPQ_PENDING 8 |
a2fbb9ea | 1584 | |
a2fbb9ea | 1585 | |
34f80b04 EG |
1586 | /* CMNG constants |
1587 | derived from lab experiments, and not from system spec calculations !!! */ | |
1588 | #define DEF_MIN_RATE 100 | |
1589 | /* resolution of the rate shaping timer - 100 usec */ | |
1590 | #define RS_PERIODIC_TIMEOUT_USEC 100 | |
1591 | /* resolution of fairness algorithm in usecs - | |
33471629 | 1592 | coefficient for calculating the actual t fair */ |
34f80b04 EG |
1593 | #define T_FAIR_COEF 10000000 |
1594 | /* number of bytes in single QM arbitration cycle - | |
33471629 | 1595 | coefficient for calculating the fairness timer */ |
34f80b04 EG |
1596 | #define QM_ARB_BYTES 40000 |
1597 | #define FAIR_MEM 2 | |
1598 | ||
1599 | ||
1600 | #define ATTN_NIG_FOR_FUNC (1L << 8) | |
1601 | #define ATTN_SW_TIMER_4_FUNC (1L << 9) | |
1602 | #define GPIO_2_FUNC (1L << 10) | |
1603 | #define GPIO_3_FUNC (1L << 11) | |
1604 | #define GPIO_4_FUNC (1L << 12) | |
1605 | #define ATTN_GENERAL_ATTN_1 (1L << 13) | |
1606 | #define ATTN_GENERAL_ATTN_2 (1L << 14) | |
1607 | #define ATTN_GENERAL_ATTN_3 (1L << 15) | |
1608 | #define ATTN_GENERAL_ATTN_4 (1L << 13) | |
1609 | #define ATTN_GENERAL_ATTN_5 (1L << 14) | |
1610 | #define ATTN_GENERAL_ATTN_6 (1L << 15) | |
1611 | ||
1612 | #define ATTN_HARD_WIRED_MASK 0xff00 | |
1613 | #define ATTENTION_ID 4 | |
a2fbb9ea ET |
1614 | |
1615 | ||
34f80b04 EG |
1616 | /* stuff added to make the code fit 80Col */ |
1617 | ||
1618 | #define BNX2X_PMF_LINK_ASSERT \ | |
1619 | GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp)) | |
1620 | ||
a2fbb9ea ET |
1621 | #define BNX2X_MC_ASSERT_BITS \ |
1622 | (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ | |
1623 | GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \ | |
1624 | GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ | |
1625 | GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT)) | |
1626 | ||
1627 | #define BNX2X_MCP_ASSERT \ | |
1628 | GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT) | |
1629 | ||
34f80b04 EG |
1630 | #define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC) |
1631 | #define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \ | |
1632 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \ | |
1633 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \ | |
1634 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \ | |
1635 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \ | |
1636 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC)) | |
1637 | ||
a2fbb9ea ET |
1638 | #define HW_INTERRUT_ASSERT_SET_0 \ |
1639 | (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \ | |
1640 | AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \ | |
1641 | AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \ | |
1642 | AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT) | |
34f80b04 | 1643 | #define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \ |
a2fbb9ea ET |
1644 | AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \ |
1645 | AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \ | |
1646 | AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\ | |
1647 | AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR) | |
1648 | #define HW_INTERRUT_ASSERT_SET_1 \ | |
1649 | (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \ | |
1650 | AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \ | |
1651 | AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \ | |
1652 | AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \ | |
1653 | AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \ | |
1654 | AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \ | |
1655 | AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \ | |
1656 | AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \ | |
1657 | AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \ | |
1658 | AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \ | |
1659 | AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT) | |
34f80b04 | 1660 | #define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR |\ |
a2fbb9ea ET |
1661 | AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \ |
1662 | AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \ | |
1663 | AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \ | |
ab6ad5a4 EG |
1664 | AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\ |
1665 | AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\ | |
a2fbb9ea ET |
1666 | AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \ |
1667 | AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \ | |
1668 | AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \ | |
1669 | AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \ | |
1670 | AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR) | |
1671 | #define HW_INTERRUT_ASSERT_SET_2 \ | |
1672 | (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \ | |
1673 | AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \ | |
1674 | AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \ | |
1675 | AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\ | |
1676 | AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT) | |
34f80b04 | 1677 | #define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \ |
a2fbb9ea ET |
1678 | AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \ |
1679 | AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\ | |
1680 | AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \ | |
1681 | AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \ | |
1682 | AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \ | |
1683 | AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR) | |
1684 | ||
72fd0718 VZ |
1685 | #define HW_PRTY_ASSERT_SET_3 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \ |
1686 | AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \ | |
1687 | AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \ | |
1688 | AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY) | |
a2fbb9ea | 1689 | |
c68ed255 | 1690 | #define RSS_FLAGS(bp) \ |
34f80b04 EG |
1691 | (TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY | \ |
1692 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | \ | |
1693 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY | \ | |
1694 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | \ | |
555f6c78 EG |
1695 | (bp->multi_mode << \ |
1696 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT)) | |
34f80b04 | 1697 | #define MULTI_MASK 0x7f |
a2fbb9ea | 1698 | |
a2fbb9ea | 1699 | #define BNX2X_SP_DSB_INDEX \ |
523224a3 DK |
1700 | (&bp->def_status_blk->sp_sb.\ |
1701 | index_values[HC_SP_INDEX_ETH_DEF_CONS]) | |
f85582f8 | 1702 | |
523224a3 DK |
1703 | #define SET_FLAG(value, mask, flag) \ |
1704 | do {\ | |
1705 | (value) &= ~(mask);\ | |
1706 | (value) |= ((flag) << (mask##_SHIFT));\ | |
1707 | } while (0) | |
a2fbb9ea | 1708 | |
523224a3 DK |
1709 | #define GET_FLAG(value, mask) \ |
1710 | (((value) &= (mask)) >> (mask##_SHIFT)) | |
a2fbb9ea | 1711 | |
f2e0899f DK |
1712 | #define GET_FIELD(value, fname) \ |
1713 | (((value) & (fname##_MASK)) >> (fname##_SHIFT)) | |
1714 | ||
a2fbb9ea | 1715 | #define CAM_IS_INVALID(x) \ |
523224a3 DK |
1716 | (GET_FLAG(x.flags, \ |
1717 | MAC_CONFIGURATION_ENTRY_ACTION_TYPE) == \ | |
1718 | (T_ETH_MAC_COMMAND_INVALIDATE)) | |
a2fbb9ea | 1719 | |
34f80b04 EG |
1720 | /* Number of u32 elements in MC hash array */ |
1721 | #define MC_HASH_SIZE 8 | |
1722 | #define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \ | |
1723 | TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4) | |
a2fbb9ea ET |
1724 | |
1725 | ||
34f80b04 EG |
1726 | #ifndef PXP2_REG_PXP2_INT_STS |
1727 | #define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0 | |
1728 | #endif | |
1729 | ||
f2e0899f DK |
1730 | #ifndef ETH_MAX_RX_CLIENTS_E2 |
1731 | #define ETH_MAX_RX_CLIENTS_E2 ETH_MAX_RX_CLIENTS_E1H | |
1732 | #endif | |
f85582f8 | 1733 | |
34f24c7f VZ |
1734 | #define BNX2X_VPD_LEN 128 |
1735 | #define VENDOR_ID_LEN 4 | |
1736 | ||
523224a3 DK |
1737 | /* Congestion management fairness mode */ |
1738 | #define CMNG_FNS_NONE 0 | |
1739 | #define CMNG_FNS_MINMAX 1 | |
1740 | ||
1741 | #define HC_SEG_ACCESS_DEF 0 /*Driver decision 0-3*/ | |
1742 | #define HC_SEG_ACCESS_ATTN 4 | |
1743 | #define HC_SEG_ACCESS_NORM 0 /*Driver decision 0-1*/ | |
1744 | ||
b0efbb99 DK |
1745 | #ifdef BNX2X_MAIN |
1746 | #define BNX2X_EXTERN | |
1747 | #else | |
1748 | #define BNX2X_EXTERN extern | |
1749 | #endif | |
1750 | ||
f2e0899f | 1751 | BNX2X_EXTERN int load_count[2][3]; /* per path: 0-common, 1-port0, 2-port1 */ |
b0efbb99 | 1752 | |
de0c62db DK |
1753 | extern void bnx2x_set_ethtool_ops(struct net_device *netdev); |
1754 | ||
a2fbb9ea | 1755 | #endif /* bnx2x.h */ |