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a2fbb9ea ET |
1 | /* bnx2x.h: Broadcom Everest network driver. |
2 | * | |
d05c26ce | 3 | * Copyright (c) 2007-2009 Broadcom Corporation |
a2fbb9ea ET |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
24e3fcef EG |
9 | * Maintained by: Eilon Greenstein <eilong@broadcom.com> |
10 | * Written by: Eliezer Tamir | |
a2fbb9ea ET |
11 | * Based on code from Michael Chan's bnx2 driver |
12 | */ | |
13 | ||
14 | #ifndef BNX2X_H | |
15 | #define BNX2X_H | |
16 | ||
34f80b04 EG |
17 | /* compilation time flags */ |
18 | ||
19 | /* define this to make the driver freeze on error to allow getting debug info | |
20 | * (you will need to reboot afterwards) */ | |
21 | /* #define BNX2X_STOP_ON_ERROR */ | |
22 | ||
0c6671b0 EG |
23 | #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) |
24 | #define BCM_VLAN 1 | |
25 | #endif | |
26 | ||
27 | ||
555f6c78 EG |
28 | #define BNX2X_MULTI_QUEUE |
29 | ||
30 | #define BNX2X_NEW_NAPI | |
31 | ||
a2fbb9ea ET |
32 | /* error/debug prints */ |
33 | ||
34f80b04 EG |
34 | #define DRV_MODULE_NAME "bnx2x" |
35 | #define PFX DRV_MODULE_NAME ": " | |
a2fbb9ea ET |
36 | |
37 | /* for messages that are currently off */ | |
34f80b04 EG |
38 | #define BNX2X_MSG_OFF 0 |
39 | #define BNX2X_MSG_MCP 0x010000 /* was: NETIF_MSG_HW */ | |
40 | #define BNX2X_MSG_STATS 0x020000 /* was: NETIF_MSG_TIMER */ | |
41 | #define BNX2X_MSG_NVM 0x040000 /* was: NETIF_MSG_HW */ | |
42 | #define BNX2X_MSG_DMAE 0x080000 /* was: NETIF_MSG_HW */ | |
f1410647 ET |
43 | #define BNX2X_MSG_SP 0x100000 /* was: NETIF_MSG_INTR */ |
44 | #define BNX2X_MSG_FP 0x200000 /* was: NETIF_MSG_INTR */ | |
a2fbb9ea | 45 | |
34f80b04 | 46 | #define DP_LEVEL KERN_NOTICE /* was: KERN_DEBUG */ |
a2fbb9ea ET |
47 | |
48 | /* regular debug print */ | |
49 | #define DP(__mask, __fmt, __args...) do { \ | |
50 | if (bp->msglevel & (__mask)) \ | |
34f80b04 | 51 | printk(DP_LEVEL "[%s:%d(%s)]" __fmt, __func__, __LINE__, \ |
6378c025 | 52 | bp->dev ? (bp->dev->name) : "?", ##__args); \ |
a2fbb9ea ET |
53 | } while (0) |
54 | ||
34f80b04 EG |
55 | /* errors debug print */ |
56 | #define BNX2X_DBG_ERR(__fmt, __args...) do { \ | |
57 | if (bp->msglevel & NETIF_MSG_PROBE) \ | |
58 | printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \ | |
6378c025 | 59 | bp->dev ? (bp->dev->name) : "?", ##__args); \ |
a2fbb9ea ET |
60 | } while (0) |
61 | ||
34f80b04 EG |
62 | /* for errors (never masked) */ |
63 | #define BNX2X_ERR(__fmt, __args...) do { \ | |
64 | printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \ | |
6378c025 | 65 | bp->dev ? (bp->dev->name) : "?", ##__args); \ |
f1410647 ET |
66 | } while (0) |
67 | ||
a2fbb9ea ET |
68 | /* before we have a dev->name use dev_info() */ |
69 | #define BNX2X_DEV_INFO(__fmt, __args...) do { \ | |
70 | if (bp->msglevel & NETIF_MSG_PROBE) \ | |
71 | dev_info(&bp->pdev->dev, __fmt, ##__args); \ | |
72 | } while (0) | |
73 | ||
74 | ||
75 | #ifdef BNX2X_STOP_ON_ERROR | |
76 | #define bnx2x_panic() do { \ | |
77 | bp->panic = 1; \ | |
78 | BNX2X_ERR("driver assert\n"); \ | |
34f80b04 | 79 | bnx2x_int_disable(bp); \ |
a2fbb9ea ET |
80 | bnx2x_panic_dump(bp); \ |
81 | } while (0) | |
82 | #else | |
83 | #define bnx2x_panic() do { \ | |
84 | BNX2X_ERR("driver assert\n"); \ | |
85 | bnx2x_panic_dump(bp); \ | |
86 | } while (0) | |
87 | #endif | |
88 | ||
89 | ||
34f80b04 EG |
90 | #define U64_LO(x) (u32)(((u64)(x)) & 0xffffffff) |
91 | #define U64_HI(x) (u32)(((u64)(x)) >> 32) | |
92 | #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo)) | |
a2fbb9ea | 93 | |
a2fbb9ea | 94 | |
34f80b04 | 95 | #define REG_ADDR(bp, offset) (bp->regview + offset) |
a2fbb9ea | 96 | |
34f80b04 EG |
97 | #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset)) |
98 | #define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset)) | |
99 | #define REG_RD64(bp, offset) readq(REG_ADDR(bp, offset)) | |
100 | ||
101 | #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset)) | |
a2fbb9ea | 102 | #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset)) |
34f80b04 EG |
103 | #define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset)) |
104 | #define REG_WR32(bp, offset, val) REG_WR(bp, offset, val) | |
a2fbb9ea | 105 | |
34f80b04 EG |
106 | #define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset) |
107 | #define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val) | |
a2fbb9ea | 108 | |
c18487ee YR |
109 | #define REG_RD_DMAE(bp, offset, valp, len32) \ |
110 | do { \ | |
111 | bnx2x_read_dmae(bp, offset, len32);\ | |
112 | memcpy(valp, bnx2x_sp(bp, wb_data[0]), len32 * 4); \ | |
113 | } while (0) | |
114 | ||
34f80b04 | 115 | #define REG_WR_DMAE(bp, offset, valp, len32) \ |
a2fbb9ea | 116 | do { \ |
34f80b04 | 117 | memcpy(bnx2x_sp(bp, wb_data[0]), valp, len32 * 4); \ |
a2fbb9ea ET |
118 | bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \ |
119 | offset, len32); \ | |
120 | } while (0) | |
121 | ||
34f80b04 EG |
122 | #define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \ |
123 | offsetof(struct shmem_region, field)) | |
124 | #define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field)) | |
125 | #define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val) | |
a2fbb9ea | 126 | |
345b5d52 | 127 | #define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg) |
3196a88a | 128 | #define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val) |
a2fbb9ea ET |
129 | |
130 | ||
7a9b2557 | 131 | /* fast path */ |
a2fbb9ea | 132 | |
a2fbb9ea | 133 | struct sw_rx_bd { |
34f80b04 | 134 | struct sk_buff *skb; |
a2fbb9ea ET |
135 | DECLARE_PCI_UNMAP_ADDR(mapping) |
136 | }; | |
137 | ||
138 | struct sw_tx_bd { | |
34f80b04 EG |
139 | struct sk_buff *skb; |
140 | u16 first_bd; | |
a2fbb9ea ET |
141 | }; |
142 | ||
7a9b2557 VZ |
143 | struct sw_rx_page { |
144 | struct page *page; | |
145 | DECLARE_PCI_UNMAP_ADDR(mapping) | |
146 | }; | |
147 | ||
148 | ||
149 | /* MC hsi */ | |
150 | #define BCM_PAGE_SHIFT 12 | |
151 | #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT) | |
152 | #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1)) | |
153 | #define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK) | |
154 | ||
155 | #define PAGES_PER_SGE_SHIFT 0 | |
156 | #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT) | |
4f40f2cb EG |
157 | #define SGE_PAGE_SIZE PAGE_SIZE |
158 | #define SGE_PAGE_SHIFT PAGE_SHIFT | |
159 | #define SGE_PAGE_ALIGN(addr) PAGE_ALIGN(addr) | |
7a9b2557 VZ |
160 | |
161 | /* SGE ring related macros */ | |
162 | #define NUM_RX_SGE_PAGES 2 | |
163 | #define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge)) | |
164 | #define MAX_RX_SGE_CNT (RX_SGE_CNT - 2) | |
33471629 | 165 | /* RX_SGE_CNT is promised to be a power of 2 */ |
7a9b2557 VZ |
166 | #define RX_SGE_MASK (RX_SGE_CNT - 1) |
167 | #define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES) | |
168 | #define MAX_RX_SGE (NUM_RX_SGE - 1) | |
169 | #define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \ | |
170 | (MAX_RX_SGE_CNT - 1)) ? (x) + 3 : (x) + 1) | |
171 | #define RX_SGE(x) ((x) & MAX_RX_SGE) | |
172 | ||
173 | /* SGE producer mask related macros */ | |
174 | /* Number of bits in one sge_mask array element */ | |
175 | #define RX_SGE_MASK_ELEM_SZ 64 | |
176 | #define RX_SGE_MASK_ELEM_SHIFT 6 | |
177 | #define RX_SGE_MASK_ELEM_MASK ((u64)RX_SGE_MASK_ELEM_SZ - 1) | |
178 | ||
179 | /* Creates a bitmask of all ones in less significant bits. | |
180 | idx - index of the most significant bit in the created mask */ | |
181 | #define RX_SGE_ONES_MASK(idx) \ | |
182 | (((u64)0x1 << (((idx) & RX_SGE_MASK_ELEM_MASK) + 1)) - 1) | |
183 | #define RX_SGE_MASK_ELEM_ONE_MASK ((u64)(~0)) | |
184 | ||
185 | /* Number of u64 elements in SGE mask array */ | |
186 | #define RX_SGE_MASK_LEN ((NUM_RX_SGE_PAGES * RX_SGE_CNT) / \ | |
187 | RX_SGE_MASK_ELEM_SZ) | |
188 | #define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1) | |
189 | #define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK) | |
190 | ||
191 | ||
a2fbb9ea ET |
192 | struct bnx2x_fastpath { |
193 | ||
34f80b04 | 194 | struct napi_struct napi; |
a2fbb9ea ET |
195 | |
196 | struct host_status_block *status_blk; | |
34f80b04 | 197 | dma_addr_t status_blk_mapping; |
a2fbb9ea | 198 | |
34f80b04 EG |
199 | struct eth_tx_db_data *hw_tx_prods; |
200 | dma_addr_t tx_prods_mapping; | |
a2fbb9ea | 201 | |
34f80b04 | 202 | struct sw_tx_bd *tx_buf_ring; |
a2fbb9ea ET |
203 | |
204 | struct eth_tx_bd *tx_desc_ring; | |
34f80b04 | 205 | dma_addr_t tx_desc_mapping; |
a2fbb9ea | 206 | |
7a9b2557 VZ |
207 | struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */ |
208 | struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */ | |
a2fbb9ea ET |
209 | |
210 | struct eth_rx_bd *rx_desc_ring; | |
34f80b04 | 211 | dma_addr_t rx_desc_mapping; |
a2fbb9ea ET |
212 | |
213 | union eth_rx_cqe *rx_comp_ring; | |
34f80b04 EG |
214 | dma_addr_t rx_comp_mapping; |
215 | ||
7a9b2557 VZ |
216 | /* SGE ring */ |
217 | struct eth_rx_sge *rx_sge_ring; | |
218 | dma_addr_t rx_sge_mapping; | |
219 | ||
220 | u64 sge_mask[RX_SGE_MASK_LEN]; | |
221 | ||
34f80b04 EG |
222 | int state; |
223 | #define BNX2X_FP_STATE_CLOSED 0 | |
224 | #define BNX2X_FP_STATE_IRQ 0x80000 | |
225 | #define BNX2X_FP_STATE_OPENING 0x90000 | |
226 | #define BNX2X_FP_STATE_OPEN 0xa0000 | |
227 | #define BNX2X_FP_STATE_HALTING 0xb0000 | |
228 | #define BNX2X_FP_STATE_HALTED 0xc0000 | |
229 | ||
230 | u8 index; /* number in fp array */ | |
231 | u8 cl_id; /* eth client id */ | |
232 | u8 sb_id; /* status block number in HW */ | |
233 | #define FP_IDX(fp) (fp->index) | |
234 | #define FP_CL_ID(fp) (fp->cl_id) | |
235 | #define BP_CL_ID(bp) (bp->fp[0].cl_id) | |
236 | #define FP_SB_ID(fp) (fp->sb_id) | |
237 | #define CNIC_SB_ID 0 | |
238 | ||
239 | u16 tx_pkt_prod; | |
240 | u16 tx_pkt_cons; | |
241 | u16 tx_bd_prod; | |
242 | u16 tx_bd_cons; | |
243 | u16 *tx_cons_sb; | |
244 | ||
245 | u16 fp_c_idx; | |
246 | u16 fp_u_idx; | |
247 | ||
248 | u16 rx_bd_prod; | |
249 | u16 rx_bd_cons; | |
250 | u16 rx_comp_prod; | |
251 | u16 rx_comp_cons; | |
7a9b2557 VZ |
252 | u16 rx_sge_prod; |
253 | /* The last maximal completed SGE */ | |
254 | u16 last_max_sge; | |
34f80b04 | 255 | u16 *rx_cons_sb; |
7a9b2557 | 256 | u16 *rx_bd_cons_sb; |
34f80b04 EG |
257 | |
258 | unsigned long tx_pkt, | |
a2fbb9ea | 259 | rx_pkt, |
66e855f3 | 260 | rx_calls; |
7a9b2557 VZ |
261 | /* TPA related */ |
262 | struct sw_rx_bd tpa_pool[ETH_MAX_AGGREGATION_QUEUES_E1H]; | |
263 | u8 tpa_state[ETH_MAX_AGGREGATION_QUEUES_E1H]; | |
264 | #define BNX2X_TPA_START 1 | |
265 | #define BNX2X_TPA_STOP 2 | |
266 | u8 disable_tpa; | |
267 | #ifdef BNX2X_STOP_ON_ERROR | |
268 | u64 tpa_queue_used; | |
269 | #endif | |
a2fbb9ea | 270 | |
555f6c78 | 271 | char name[IFNAMSIZ]; |
34f80b04 | 272 | struct bnx2x *bp; /* parent */ |
a2fbb9ea ET |
273 | }; |
274 | ||
34f80b04 | 275 | #define bnx2x_fp(bp, nr, var) (bp->fp[nr].var) |
7a9b2557 | 276 | |
237907c1 | 277 | #define BNX2X_HAS_WORK(fp) (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp)) |
da5a662a | 278 | |
7a9b2557 VZ |
279 | |
280 | /* MC hsi */ | |
281 | #define MAX_FETCH_BD 13 /* HW max BDs per packet */ | |
282 | #define RX_COPY_THRESH 92 | |
283 | ||
284 | #define NUM_TX_RINGS 16 | |
285 | #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_tx_bd)) | |
286 | #define MAX_TX_DESC_CNT (TX_DESC_CNT - 1) | |
287 | #define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS) | |
288 | #define MAX_TX_BD (NUM_TX_BD - 1) | |
289 | #define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2) | |
290 | #define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \ | |
291 | (MAX_TX_DESC_CNT - 1)) ? (x) + 2 : (x) + 1) | |
292 | #define TX_BD(x) ((x) & MAX_TX_BD) | |
293 | #define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT) | |
294 | ||
295 | /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */ | |
296 | #define NUM_RX_RINGS 8 | |
297 | #define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd)) | |
298 | #define MAX_RX_DESC_CNT (RX_DESC_CNT - 2) | |
299 | #define RX_DESC_MASK (RX_DESC_CNT - 1) | |
300 | #define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS) | |
301 | #define MAX_RX_BD (NUM_RX_BD - 1) | |
302 | #define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2) | |
303 | #define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \ | |
304 | (MAX_RX_DESC_CNT - 1)) ? (x) + 3 : (x) + 1) | |
305 | #define RX_BD(x) ((x) & MAX_RX_BD) | |
306 | ||
307 | /* As long as CQE is 4 times bigger than BD entry we have to allocate | |
308 | 4 times more pages for CQ ring in order to keep it balanced with | |
309 | BD ring */ | |
310 | #define NUM_RCQ_RINGS (NUM_RX_RINGS * 4) | |
311 | #define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe)) | |
312 | #define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - 1) | |
313 | #define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS) | |
314 | #define MAX_RCQ_BD (NUM_RCQ_BD - 1) | |
315 | #define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2) | |
316 | #define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \ | |
317 | (MAX_RCQ_DESC_CNT - 1)) ? (x) + 2 : (x) + 1) | |
318 | #define RCQ_BD(x) ((x) & MAX_RCQ_BD) | |
319 | ||
320 | ||
33471629 | 321 | /* This is needed for determining of last_max */ |
34f80b04 | 322 | #define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b)) |
a2fbb9ea | 323 | |
7a9b2557 VZ |
324 | #define __SGE_MASK_SET_BIT(el, bit) \ |
325 | do { \ | |
326 | el = ((el) | ((u64)0x1 << (bit))); \ | |
327 | } while (0) | |
328 | ||
329 | #define __SGE_MASK_CLEAR_BIT(el, bit) \ | |
330 | do { \ | |
331 | el = ((el) & (~((u64)0x1 << (bit)))); \ | |
332 | } while (0) | |
333 | ||
334 | #define SGE_MASK_SET_BIT(fp, idx) \ | |
335 | __SGE_MASK_SET_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \ | |
336 | ((idx) & RX_SGE_MASK_ELEM_MASK)) | |
337 | ||
338 | #define SGE_MASK_CLEAR_BIT(fp, idx) \ | |
339 | __SGE_MASK_CLEAR_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \ | |
340 | ((idx) & RX_SGE_MASK_ELEM_MASK)) | |
341 | ||
342 | ||
343 | /* used on a CID received from the HW */ | |
344 | #define SW_CID(x) (le32_to_cpu(x) & \ | |
345 | (COMMON_RAMROD_ETH_RX_CQE_CID >> 7)) | |
346 | #define CQE_CMD(x) (le32_to_cpu(x) >> \ | |
347 | COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT) | |
348 | ||
bb2a0f7a YG |
349 | #define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \ |
350 | le32_to_cpu((bd)->addr_lo)) | |
351 | #define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes)) | |
352 | ||
7a9b2557 VZ |
353 | |
354 | #define DPM_TRIGER_TYPE 0x40 | |
355 | #define DOORBELL(bp, cid, val) \ | |
356 | do { \ | |
357 | writel((u32)val, (bp)->doorbells + (BCM_PAGE_SIZE * cid) + \ | |
358 | DPM_TRIGER_TYPE); \ | |
359 | } while (0) | |
360 | ||
361 | ||
362 | /* TX CSUM helpers */ | |
363 | #define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \ | |
364 | skb->csum_offset) | |
365 | #define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \ | |
366 | skb->csum_offset)) | |
367 | ||
368 | #define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff) | |
369 | ||
370 | #define XMIT_PLAIN 0 | |
371 | #define XMIT_CSUM_V4 0x1 | |
372 | #define XMIT_CSUM_V6 0x2 | |
373 | #define XMIT_CSUM_TCP 0x4 | |
374 | #define XMIT_GSO_V4 0x8 | |
375 | #define XMIT_GSO_V6 0x10 | |
376 | ||
377 | #define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6) | |
378 | #define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6) | |
379 | ||
380 | ||
34f80b04 | 381 | /* stuff added to make the code fit 80Col */ |
a2fbb9ea | 382 | |
34f80b04 | 383 | #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE) |
a2fbb9ea | 384 | |
7a9b2557 VZ |
385 | #define TPA_TYPE_START ETH_FAST_PATH_RX_CQE_START_FLG |
386 | #define TPA_TYPE_END ETH_FAST_PATH_RX_CQE_END_FLG | |
387 | #define TPA_TYPE(cqe_fp_flags) ((cqe_fp_flags) & \ | |
388 | (TPA_TYPE_START | TPA_TYPE_END)) | |
389 | ||
1adcd8be EG |
390 | #define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG |
391 | ||
392 | #define BNX2X_IP_CSUM_ERR(cqe) \ | |
393 | (!((cqe)->fast_path_cqe.status_flags & \ | |
394 | ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG) && \ | |
395 | ((cqe)->fast_path_cqe.type_error_flags & \ | |
396 | ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG)) | |
397 | ||
398 | #define BNX2X_L4_CSUM_ERR(cqe) \ | |
399 | (!((cqe)->fast_path_cqe.status_flags & \ | |
400 | ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG) && \ | |
401 | ((cqe)->fast_path_cqe.type_error_flags & \ | |
402 | ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG)) | |
403 | ||
404 | #define BNX2X_RX_CSUM_OK(cqe) \ | |
405 | (!(BNX2X_L4_CSUM_ERR(cqe) || BNX2X_IP_CSUM_ERR(cqe))) | |
7a9b2557 VZ |
406 | |
407 | #define BNX2X_RX_SUM_FIX(cqe) \ | |
408 | ((le16_to_cpu(cqe->fast_path_cqe.pars_flags.flags) & \ | |
409 | PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) == \ | |
410 | (1 << PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT)) | |
411 | ||
a2fbb9ea | 412 | |
bb2a0f7a YG |
413 | #define FP_USB_FUNC_OFF (2 + 2*HC_USTORM_SB_NUM_INDICES) |
414 | #define FP_CSB_FUNC_OFF (2 + 2*HC_CSTORM_SB_NUM_INDICES) | |
415 | ||
34f80b04 EG |
416 | #define U_SB_ETH_RX_CQ_INDEX HC_INDEX_U_ETH_RX_CQ_CONS |
417 | #define U_SB_ETH_RX_BD_INDEX HC_INDEX_U_ETH_RX_BD_CONS | |
418 | #define C_SB_ETH_TX_CQ_INDEX HC_INDEX_C_ETH_TX_CQ_CONS | |
a2fbb9ea | 419 | |
34f80b04 EG |
420 | #define BNX2X_RX_SB_INDEX \ |
421 | (&fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_CQ_INDEX]) | |
a2fbb9ea | 422 | |
34f80b04 EG |
423 | #define BNX2X_RX_SB_BD_INDEX \ |
424 | (&fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_BD_INDEX]) | |
a2fbb9ea | 425 | |
34f80b04 EG |
426 | #define BNX2X_RX_SB_INDEX_NUM \ |
427 | (((U_SB_ETH_RX_CQ_INDEX << \ | |
428 | USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER_SHIFT) & \ | |
429 | USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER) | \ | |
430 | ((U_SB_ETH_RX_BD_INDEX << \ | |
431 | USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER_SHIFT) & \ | |
432 | USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER)) | |
a2fbb9ea | 433 | |
34f80b04 EG |
434 | #define BNX2X_TX_SB_INDEX \ |
435 | (&fp->status_blk->c_status_block.index_values[C_SB_ETH_TX_CQ_INDEX]) | |
a2fbb9ea | 436 | |
7a9b2557 VZ |
437 | |
438 | /* end of fast path */ | |
439 | ||
34f80b04 | 440 | /* common */ |
a2fbb9ea | 441 | |
34f80b04 | 442 | struct bnx2x_common { |
a2fbb9ea | 443 | |
ad8d3948 | 444 | u32 chip_id; |
a2fbb9ea | 445 | /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ |
34f80b04 | 446 | #define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0) |
ad8d3948 | 447 | |
34f80b04 | 448 | #define CHIP_NUM(bp) (bp->common.chip_id >> 16) |
ad8d3948 EG |
449 | #define CHIP_NUM_57710 0x164e |
450 | #define CHIP_NUM_57711 0x164f | |
451 | #define CHIP_NUM_57711E 0x1650 | |
452 | #define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710) | |
453 | #define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711) | |
454 | #define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E) | |
455 | #define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \ | |
456 | CHIP_IS_57711E(bp)) | |
457 | #define IS_E1H_OFFSET CHIP_IS_E1H(bp) | |
458 | ||
34f80b04 | 459 | #define CHIP_REV(bp) (bp->common.chip_id & 0x0000f000) |
ad8d3948 EG |
460 | #define CHIP_REV_Ax 0x00000000 |
461 | /* assume maximum 5 revisions */ | |
462 | #define CHIP_REV_IS_SLOW(bp) (CHIP_REV(bp) > 0x00005000) | |
463 | /* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */ | |
464 | #define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \ | |
465 | !(CHIP_REV(bp) & 0x00001000)) | |
466 | /* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */ | |
467 | #define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \ | |
468 | (CHIP_REV(bp) & 0x00001000)) | |
469 | ||
470 | #define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \ | |
471 | ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1)) | |
472 | ||
34f80b04 EG |
473 | #define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0) |
474 | #define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f) | |
a2fbb9ea | 475 | |
34f80b04 EG |
476 | int flash_size; |
477 | #define NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */ | |
478 | #define NVRAM_TIMEOUT_COUNT 30000 | |
479 | #define NVRAM_PAGE_SIZE 256 | |
a2fbb9ea | 480 | |
34f80b04 EG |
481 | u32 shmem_base; |
482 | ||
483 | u32 hw_config; | |
f1410647 | 484 | u32 board; |
c18487ee | 485 | |
34f80b04 EG |
486 | u32 bc_ver; |
487 | ||
488 | char *name; | |
489 | }; | |
c18487ee | 490 | |
34f80b04 EG |
491 | |
492 | /* end of common */ | |
493 | ||
494 | /* port */ | |
495 | ||
bb2a0f7a YG |
496 | struct nig_stats { |
497 | u32 brb_discard; | |
498 | u32 brb_packet; | |
499 | u32 brb_truncate; | |
500 | u32 flow_ctrl_discard; | |
501 | u32 flow_ctrl_octets; | |
502 | u32 flow_ctrl_packet; | |
503 | u32 mng_discard; | |
504 | u32 mng_octet_inp; | |
505 | u32 mng_octet_out; | |
506 | u32 mng_packet_inp; | |
507 | u32 mng_packet_out; | |
508 | u32 pbf_octets; | |
509 | u32 pbf_packet; | |
510 | u32 safc_inp; | |
511 | u32 egress_mac_pkt0_lo; | |
512 | u32 egress_mac_pkt0_hi; | |
513 | u32 egress_mac_pkt1_lo; | |
514 | u32 egress_mac_pkt1_hi; | |
515 | }; | |
516 | ||
34f80b04 EG |
517 | struct bnx2x_port { |
518 | u32 pmf; | |
c18487ee YR |
519 | |
520 | u32 link_config; | |
a2fbb9ea | 521 | |
34f80b04 EG |
522 | u32 supported; |
523 | /* link settings - missing defines */ | |
524 | #define SUPPORTED_2500baseX_Full (1 << 15) | |
525 | ||
526 | u32 advertising; | |
a2fbb9ea | 527 | /* link settings - missing defines */ |
34f80b04 | 528 | #define ADVERTISED_2500baseX_Full (1 << 15) |
a2fbb9ea | 529 | |
34f80b04 | 530 | u32 phy_addr; |
c18487ee YR |
531 | |
532 | /* used to synchronize phy accesses */ | |
533 | struct mutex phy_mutex; | |
534 | ||
34f80b04 | 535 | u32 port_stx; |
a2fbb9ea | 536 | |
34f80b04 EG |
537 | struct nig_stats old_nig_stats; |
538 | }; | |
a2fbb9ea | 539 | |
34f80b04 EG |
540 | /* end of port */ |
541 | ||
bb2a0f7a YG |
542 | |
543 | enum bnx2x_stats_event { | |
544 | STATS_EVENT_PMF = 0, | |
545 | STATS_EVENT_LINK_UP, | |
546 | STATS_EVENT_UPDATE, | |
547 | STATS_EVENT_STOP, | |
548 | STATS_EVENT_MAX | |
549 | }; | |
550 | ||
551 | enum bnx2x_stats_state { | |
552 | STATS_STATE_DISABLED = 0, | |
553 | STATS_STATE_ENABLED, | |
554 | STATS_STATE_MAX | |
555 | }; | |
556 | ||
557 | struct bnx2x_eth_stats { | |
558 | u32 total_bytes_received_hi; | |
559 | u32 total_bytes_received_lo; | |
560 | u32 total_bytes_transmitted_hi; | |
561 | u32 total_bytes_transmitted_lo; | |
562 | u32 total_unicast_packets_received_hi; | |
563 | u32 total_unicast_packets_received_lo; | |
564 | u32 total_multicast_packets_received_hi; | |
565 | u32 total_multicast_packets_received_lo; | |
566 | u32 total_broadcast_packets_received_hi; | |
567 | u32 total_broadcast_packets_received_lo; | |
568 | u32 total_unicast_packets_transmitted_hi; | |
569 | u32 total_unicast_packets_transmitted_lo; | |
570 | u32 total_multicast_packets_transmitted_hi; | |
571 | u32 total_multicast_packets_transmitted_lo; | |
572 | u32 total_broadcast_packets_transmitted_hi; | |
573 | u32 total_broadcast_packets_transmitted_lo; | |
574 | u32 valid_bytes_received_hi; | |
575 | u32 valid_bytes_received_lo; | |
576 | ||
577 | u32 error_bytes_received_hi; | |
578 | u32 error_bytes_received_lo; | |
579 | ||
580 | u32 rx_stat_ifhcinbadoctets_hi; | |
581 | u32 rx_stat_ifhcinbadoctets_lo; | |
582 | u32 tx_stat_ifhcoutbadoctets_hi; | |
583 | u32 tx_stat_ifhcoutbadoctets_lo; | |
584 | u32 rx_stat_dot3statsfcserrors_hi; | |
585 | u32 rx_stat_dot3statsfcserrors_lo; | |
586 | u32 rx_stat_dot3statsalignmenterrors_hi; | |
587 | u32 rx_stat_dot3statsalignmenterrors_lo; | |
588 | u32 rx_stat_dot3statscarriersenseerrors_hi; | |
589 | u32 rx_stat_dot3statscarriersenseerrors_lo; | |
590 | u32 rx_stat_falsecarriererrors_hi; | |
591 | u32 rx_stat_falsecarriererrors_lo; | |
592 | u32 rx_stat_etherstatsundersizepkts_hi; | |
593 | u32 rx_stat_etherstatsundersizepkts_lo; | |
594 | u32 rx_stat_dot3statsframestoolong_hi; | |
595 | u32 rx_stat_dot3statsframestoolong_lo; | |
596 | u32 rx_stat_etherstatsfragments_hi; | |
597 | u32 rx_stat_etherstatsfragments_lo; | |
598 | u32 rx_stat_etherstatsjabbers_hi; | |
599 | u32 rx_stat_etherstatsjabbers_lo; | |
600 | u32 rx_stat_maccontrolframesreceived_hi; | |
601 | u32 rx_stat_maccontrolframesreceived_lo; | |
602 | u32 rx_stat_bmac_xpf_hi; | |
603 | u32 rx_stat_bmac_xpf_lo; | |
604 | u32 rx_stat_bmac_xcf_hi; | |
605 | u32 rx_stat_bmac_xcf_lo; | |
606 | u32 rx_stat_xoffstateentered_hi; | |
607 | u32 rx_stat_xoffstateentered_lo; | |
608 | u32 rx_stat_xonpauseframesreceived_hi; | |
609 | u32 rx_stat_xonpauseframesreceived_lo; | |
610 | u32 rx_stat_xoffpauseframesreceived_hi; | |
611 | u32 rx_stat_xoffpauseframesreceived_lo; | |
612 | u32 tx_stat_outxonsent_hi; | |
613 | u32 tx_stat_outxonsent_lo; | |
614 | u32 tx_stat_outxoffsent_hi; | |
615 | u32 tx_stat_outxoffsent_lo; | |
616 | u32 tx_stat_flowcontroldone_hi; | |
617 | u32 tx_stat_flowcontroldone_lo; | |
618 | u32 tx_stat_etherstatscollisions_hi; | |
619 | u32 tx_stat_etherstatscollisions_lo; | |
620 | u32 tx_stat_dot3statssinglecollisionframes_hi; | |
621 | u32 tx_stat_dot3statssinglecollisionframes_lo; | |
622 | u32 tx_stat_dot3statsmultiplecollisionframes_hi; | |
623 | u32 tx_stat_dot3statsmultiplecollisionframes_lo; | |
624 | u32 tx_stat_dot3statsdeferredtransmissions_hi; | |
625 | u32 tx_stat_dot3statsdeferredtransmissions_lo; | |
626 | u32 tx_stat_dot3statsexcessivecollisions_hi; | |
627 | u32 tx_stat_dot3statsexcessivecollisions_lo; | |
628 | u32 tx_stat_dot3statslatecollisions_hi; | |
629 | u32 tx_stat_dot3statslatecollisions_lo; | |
630 | u32 tx_stat_etherstatspkts64octets_hi; | |
631 | u32 tx_stat_etherstatspkts64octets_lo; | |
632 | u32 tx_stat_etherstatspkts65octetsto127octets_hi; | |
633 | u32 tx_stat_etherstatspkts65octetsto127octets_lo; | |
634 | u32 tx_stat_etherstatspkts128octetsto255octets_hi; | |
635 | u32 tx_stat_etherstatspkts128octetsto255octets_lo; | |
636 | u32 tx_stat_etherstatspkts256octetsto511octets_hi; | |
637 | u32 tx_stat_etherstatspkts256octetsto511octets_lo; | |
638 | u32 tx_stat_etherstatspkts512octetsto1023octets_hi; | |
639 | u32 tx_stat_etherstatspkts512octetsto1023octets_lo; | |
640 | u32 tx_stat_etherstatspkts1024octetsto1522octets_hi; | |
641 | u32 tx_stat_etherstatspkts1024octetsto1522octets_lo; | |
642 | u32 tx_stat_etherstatspktsover1522octets_hi; | |
643 | u32 tx_stat_etherstatspktsover1522octets_lo; | |
644 | u32 tx_stat_bmac_2047_hi; | |
645 | u32 tx_stat_bmac_2047_lo; | |
646 | u32 tx_stat_bmac_4095_hi; | |
647 | u32 tx_stat_bmac_4095_lo; | |
648 | u32 tx_stat_bmac_9216_hi; | |
649 | u32 tx_stat_bmac_9216_lo; | |
650 | u32 tx_stat_bmac_16383_hi; | |
651 | u32 tx_stat_bmac_16383_lo; | |
652 | u32 tx_stat_dot3statsinternalmactransmiterrors_hi; | |
653 | u32 tx_stat_dot3statsinternalmactransmiterrors_lo; | |
654 | u32 tx_stat_bmac_ufl_hi; | |
655 | u32 tx_stat_bmac_ufl_lo; | |
656 | ||
657 | u32 brb_drop_hi; | |
658 | u32 brb_drop_lo; | |
66e855f3 YG |
659 | u32 brb_truncate_hi; |
660 | u32 brb_truncate_lo; | |
bb2a0f7a YG |
661 | |
662 | u32 jabber_packets_received; | |
663 | ||
664 | u32 etherstatspkts1024octetsto1522octets_hi; | |
665 | u32 etherstatspkts1024octetsto1522octets_lo; | |
666 | u32 etherstatspktsover1522octets_hi; | |
667 | u32 etherstatspktsover1522octets_lo; | |
668 | ||
669 | u32 no_buff_discard; | |
670 | ||
671 | u32 mac_filter_discard; | |
672 | u32 xxoverflow_discard; | |
673 | u32 brb_truncate_discard; | |
674 | u32 mac_discard; | |
675 | ||
676 | u32 driver_xoff; | |
66e855f3 YG |
677 | u32 rx_err_discard_pkt; |
678 | u32 rx_skb_alloc_failed; | |
679 | u32 hw_csum_err; | |
bb2a0f7a YG |
680 | }; |
681 | ||
682 | #define STATS_OFFSET32(stat_name) \ | |
683 | (offsetof(struct bnx2x_eth_stats, stat_name) / 4) | |
684 | ||
34f80b04 | 685 | |
34f80b04 | 686 | #define MAX_CONTEXT 16 |
34f80b04 EG |
687 | |
688 | union cdu_context { | |
689 | struct eth_context eth; | |
690 | char pad[1024]; | |
691 | }; | |
692 | ||
bb2a0f7a | 693 | #define MAX_DMAE_C 8 |
34f80b04 EG |
694 | |
695 | /* DMA memory not used in fastpath */ | |
696 | struct bnx2x_slowpath { | |
697 | union cdu_context context[MAX_CONTEXT]; | |
698 | struct eth_stats_query fw_stats; | |
699 | struct mac_configuration_cmd mac_config; | |
700 | struct mac_configuration_cmd mcast_config; | |
701 | ||
702 | /* used by dmae command executer */ | |
703 | struct dmae_command dmae[MAX_DMAE_C]; | |
704 | ||
bb2a0f7a YG |
705 | u32 stats_comp; |
706 | union mac_stats mac_stats; | |
707 | struct nig_stats nig_stats; | |
708 | struct host_port_stats port_stats; | |
709 | struct host_func_stats func_stats; | |
34f80b04 EG |
710 | |
711 | u32 wb_comp; | |
34f80b04 EG |
712 | u32 wb_data[4]; |
713 | }; | |
714 | ||
715 | #define bnx2x_sp(bp, var) (&bp->slowpath->var) | |
716 | #define bnx2x_sp_mapping(bp, var) \ | |
717 | (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var)) | |
718 | ||
719 | ||
720 | /* attn group wiring */ | |
721 | #define MAX_DYNAMIC_ATTN_GRPS 8 | |
722 | ||
723 | struct attn_route { | |
724 | u32 sig[4]; | |
725 | }; | |
726 | ||
727 | struct bnx2x { | |
728 | /* Fields used in the tx and intr/napi performance paths | |
729 | * are grouped together in the beginning of the structure | |
730 | */ | |
731 | struct bnx2x_fastpath fp[MAX_CONTEXT]; | |
732 | void __iomem *regview; | |
733 | void __iomem *doorbells; | |
a5f67a04 | 734 | #define BNX2X_DB_SIZE (16*BCM_PAGE_SIZE) |
34f80b04 EG |
735 | |
736 | struct net_device *dev; | |
737 | struct pci_dev *pdev; | |
738 | ||
739 | atomic_t intr_sem; | |
7a9b2557 | 740 | struct msix_entry msix_table[MAX_CONTEXT+1]; |
8badd27a EG |
741 | #define INT_MODE_INTx 1 |
742 | #define INT_MODE_MSI 2 | |
743 | #define INT_MODE_MSIX 3 | |
34f80b04 EG |
744 | |
745 | int tx_ring_size; | |
746 | ||
747 | #ifdef BCM_VLAN | |
748 | struct vlan_group *vlgrp; | |
749 | #endif | |
a2fbb9ea | 750 | |
34f80b04 EG |
751 | u32 rx_csum; |
752 | u32 rx_offset; | |
437cf2f1 | 753 | u32 rx_buf_size; |
34f80b04 EG |
754 | #define ETH_OVREHEAD (ETH_HLEN + 8) /* 8 for CRC + VLAN */ |
755 | #define ETH_MIN_PACKET_SIZE 60 | |
756 | #define ETH_MAX_PACKET_SIZE 1500 | |
757 | #define ETH_MAX_JUMBO_PACKET_SIZE 9600 | |
a2fbb9ea | 758 | |
0f00846d EG |
759 | /* Max supported alignment is 256 (8 shift) */ |
760 | #define BNX2X_RX_ALIGN_SHIFT ((L1_CACHE_SHIFT < 8) ? \ | |
761 | L1_CACHE_SHIFT : 8) | |
762 | #define BNX2X_RX_ALIGN (1 << BNX2X_RX_ALIGN_SHIFT) | |
763 | ||
34f80b04 EG |
764 | struct host_def_status_block *def_status_blk; |
765 | #define DEF_SB_ID 16 | |
766 | u16 def_c_idx; | |
767 | u16 def_u_idx; | |
768 | u16 def_x_idx; | |
769 | u16 def_t_idx; | |
770 | u16 def_att_idx; | |
771 | u32 attn_state; | |
772 | struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS]; | |
34f80b04 EG |
773 | u32 nig_mask; |
774 | ||
775 | /* slow path ring */ | |
776 | struct eth_spe *spq; | |
777 | dma_addr_t spq_mapping; | |
778 | u16 spq_prod_idx; | |
779 | struct eth_spe *spq_prod_bd; | |
780 | struct eth_spe *spq_last_bd; | |
781 | u16 *dsb_sp_prod; | |
782 | u16 spq_left; /* serialize spq */ | |
783 | /* used to synchronize spq accesses */ | |
784 | spinlock_t spq_lock; | |
785 | ||
bb2a0f7a YG |
786 | /* Flags for marking that there is a STAT_QUERY or |
787 | SET_MAC ramrod pending */ | |
788 | u8 stats_pending; | |
789 | u8 set_mac_pending; | |
34f80b04 | 790 | |
33471629 | 791 | /* End of fields used in the performance code paths */ |
34f80b04 EG |
792 | |
793 | int panic; | |
794 | int msglevel; | |
795 | ||
796 | u32 flags; | |
797 | #define PCIX_FLAG 1 | |
798 | #define PCI_32BIT_FLAG 2 | |
799 | #define ONE_TDMA_FLAG 4 /* no longer used */ | |
800 | #define NO_WOL_FLAG 8 | |
801 | #define USING_DAC_FLAG 0x10 | |
802 | #define USING_MSIX_FLAG 0x20 | |
8badd27a | 803 | #define USING_MSI_FLAG 0x40 |
7a9b2557 | 804 | #define TPA_ENABLE_FLAG 0x80 |
34f80b04 EG |
805 | #define NO_MCP_FLAG 0x100 |
806 | #define BP_NOMCP(bp) (bp->flags & NO_MCP_FLAG) | |
0c6671b0 EG |
807 | #define HW_VLAN_TX_FLAG 0x400 |
808 | #define HW_VLAN_RX_FLAG 0x800 | |
34f80b04 EG |
809 | |
810 | int func; | |
811 | #define BP_PORT(bp) (bp->func % PORT_MAX) | |
812 | #define BP_FUNC(bp) (bp->func) | |
813 | #define BP_E1HVN(bp) (bp->func >> 1) | |
814 | #define BP_L_ID(bp) (BP_E1HVN(bp) << 2) | |
34f80b04 EG |
815 | |
816 | int pm_cap; | |
817 | int pcie_cap; | |
818 | ||
1cf167f2 | 819 | struct delayed_work sp_task; |
34f80b04 EG |
820 | struct work_struct reset_task; |
821 | ||
822 | struct timer_list timer; | |
823 | int timer_interval; | |
824 | int current_interval; | |
825 | ||
826 | u16 fw_seq; | |
827 | u16 fw_drv_pulse_wr_seq; | |
828 | u32 func_stx; | |
829 | ||
830 | struct link_params link_params; | |
831 | struct link_vars link_vars; | |
a2fbb9ea | 832 | |
34f80b04 EG |
833 | struct bnx2x_common common; |
834 | struct bnx2x_port port; | |
835 | ||
836 | u32 mf_config; | |
837 | u16 e1hov; | |
838 | u8 e1hmf; | |
3196a88a | 839 | #define IS_E1HMF(bp) (bp->e1hmf != 0) |
a2fbb9ea | 840 | |
f1410647 ET |
841 | u8 wol; |
842 | ||
34f80b04 | 843 | int rx_ring_size; |
a2fbb9ea | 844 | |
34f80b04 EG |
845 | u16 tx_quick_cons_trip_int; |
846 | u16 tx_quick_cons_trip; | |
847 | u16 tx_ticks_int; | |
848 | u16 tx_ticks; | |
a2fbb9ea | 849 | |
34f80b04 EG |
850 | u16 rx_quick_cons_trip_int; |
851 | u16 rx_quick_cons_trip; | |
852 | u16 rx_ticks_int; | |
853 | u16 rx_ticks; | |
a2fbb9ea | 854 | |
34f80b04 | 855 | u32 lin_cnt; |
a2fbb9ea | 856 | |
34f80b04 EG |
857 | int state; |
858 | #define BNX2X_STATE_CLOSED 0x0 | |
859 | #define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000 | |
860 | #define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000 | |
a2fbb9ea | 861 | #define BNX2X_STATE_OPEN 0x3000 |
34f80b04 | 862 | #define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000 |
a2fbb9ea ET |
863 | #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000 |
864 | #define BNX2X_STATE_CLOSING_WAIT4_UNLOAD 0x6000 | |
34f80b04 EG |
865 | #define BNX2X_STATE_DISABLED 0xd000 |
866 | #define BNX2X_STATE_DIAG 0xe000 | |
867 | #define BNX2X_STATE_ERROR 0xf000 | |
a2fbb9ea | 868 | |
555f6c78 EG |
869 | int multi_mode; |
870 | int num_rx_queues; | |
871 | int num_tx_queues; | |
a2fbb9ea | 872 | |
34f80b04 EG |
873 | u32 rx_mode; |
874 | #define BNX2X_RX_MODE_NONE 0 | |
875 | #define BNX2X_RX_MODE_NORMAL 1 | |
876 | #define BNX2X_RX_MODE_ALLMULTI 2 | |
877 | #define BNX2X_RX_MODE_PROMISC 3 | |
878 | #define BNX2X_MAX_MULTICAST 64 | |
879 | #define BNX2X_MAX_EMUL_MULTI 16 | |
a2fbb9ea | 880 | |
34f80b04 | 881 | dma_addr_t def_status_blk_mapping; |
a2fbb9ea | 882 | |
34f80b04 EG |
883 | struct bnx2x_slowpath *slowpath; |
884 | dma_addr_t slowpath_mapping; | |
a2fbb9ea ET |
885 | |
886 | #ifdef BCM_ISCSI | |
887 | void *t1; | |
888 | dma_addr_t t1_mapping; | |
889 | void *t2; | |
890 | dma_addr_t t2_mapping; | |
891 | void *timers; | |
892 | dma_addr_t timers_mapping; | |
893 | void *qm; | |
894 | dma_addr_t qm_mapping; | |
895 | #endif | |
896 | ||
ad8d3948 EG |
897 | int dmae_ready; |
898 | /* used to synchronize dmae accesses */ | |
899 | struct mutex dmae_mutex; | |
900 | struct dmae_command init_dmae; | |
901 | ||
bb2a0f7a YG |
902 | /* used to synchronize stats collecting */ |
903 | int stats_state; | |
904 | /* used by dmae command loader */ | |
905 | struct dmae_command stats_dmae; | |
906 | int executer_idx; | |
ad8d3948 | 907 | |
bb2a0f7a | 908 | u16 stats_counter; |
a2fbb9ea | 909 | struct tstorm_per_client_stats old_tclient; |
bb2a0f7a YG |
910 | struct xstorm_per_client_stats old_xclient; |
911 | struct bnx2x_eth_stats eth_stats; | |
912 | ||
913 | struct z_stream_s *strm; | |
914 | void *gunzip_buf; | |
915 | dma_addr_t gunzip_mapping; | |
916 | int gunzip_outlen; | |
ad8d3948 | 917 | #define FW_BUF_SIZE 0x8000 |
a2fbb9ea ET |
918 | |
919 | }; | |
920 | ||
921 | ||
555f6c78 EG |
922 | #define BNX2X_MAX_QUEUES(bp) (IS_E1HMF(bp) ? (MAX_CONTEXT / E1HVN_MAX) : \ |
923 | MAX_CONTEXT) | |
924 | #define BNX2X_NUM_QUEUES(bp) max(bp->num_rx_queues, bp->num_tx_queues) | |
925 | #define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1) | |
3196a88a | 926 | |
555f6c78 EG |
927 | #define for_each_rx_queue(bp, var) \ |
928 | for (var = 0; var < bp->num_rx_queues; var++) | |
929 | #define for_each_tx_queue(bp, var) \ | |
930 | for (var = 0; var < bp->num_tx_queues; var++) | |
931 | #define for_each_queue(bp, var) \ | |
932 | for (var = 0; var < BNX2X_NUM_QUEUES(bp); var++) | |
3196a88a | 933 | #define for_each_nondefault_queue(bp, var) \ |
555f6c78 | 934 | for (var = 1; var < BNX2X_NUM_QUEUES(bp); var++) |
3196a88a EG |
935 | |
936 | ||
c18487ee YR |
937 | void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32); |
938 | void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, | |
939 | u32 len32); | |
17de50b7 | 940 | int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port); |
c18487ee | 941 | |
34f80b04 EG |
942 | static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms, |
943 | int wait) | |
944 | { | |
945 | u32 val; | |
946 | ||
947 | do { | |
948 | val = REG_RD(bp, reg); | |
949 | if (val == expected) | |
950 | break; | |
951 | ms -= wait; | |
952 | msleep(wait); | |
953 | ||
954 | } while (ms > 0); | |
955 | ||
956 | return val; | |
957 | } | |
958 | ||
959 | ||
960 | /* load/unload mode */ | |
961 | #define LOAD_NORMAL 0 | |
962 | #define LOAD_OPEN 1 | |
963 | #define LOAD_DIAG 2 | |
964 | #define UNLOAD_NORMAL 0 | |
965 | #define UNLOAD_CLOSE 1 | |
966 | ||
bb2a0f7a | 967 | |
ad8d3948 EG |
968 | /* DMAE command defines */ |
969 | #define DMAE_CMD_SRC_PCI 0 | |
970 | #define DMAE_CMD_SRC_GRC DMAE_COMMAND_SRC | |
971 | ||
972 | #define DMAE_CMD_DST_PCI (1 << DMAE_COMMAND_DST_SHIFT) | |
973 | #define DMAE_CMD_DST_GRC (2 << DMAE_COMMAND_DST_SHIFT) | |
974 | ||
975 | #define DMAE_CMD_C_DST_PCI 0 | |
976 | #define DMAE_CMD_C_DST_GRC (1 << DMAE_COMMAND_C_DST_SHIFT) | |
977 | ||
978 | #define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE | |
979 | ||
980 | #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT) | |
981 | #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT) | |
982 | #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT) | |
983 | #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT) | |
984 | ||
985 | #define DMAE_CMD_PORT_0 0 | |
986 | #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT | |
987 | ||
988 | #define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET | |
989 | #define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET | |
990 | #define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT | |
991 | ||
992 | #define DMAE_LEN32_RD_MAX 0x80 | |
993 | #define DMAE_LEN32_WR_MAX 0x400 | |
994 | ||
995 | #define DMAE_COMP_VAL 0xe0d0d0ae | |
996 | ||
997 | #define MAX_DMAE_C_PER_PORT 8 | |
998 | #define INIT_DMAE_C(bp) (BP_PORT(bp)*MAX_DMAE_C_PER_PORT + \ | |
999 | BP_E1HVN(bp)) | |
1000 | #define PMF_DMAE_C(bp) (BP_PORT(bp)*MAX_DMAE_C_PER_PORT + \ | |
1001 | E1HVN_MAX) | |
1002 | ||
1003 | ||
25047950 ET |
1004 | /* PCIE link and speed */ |
1005 | #define PCICFG_LINK_WIDTH 0x1f00000 | |
1006 | #define PCICFG_LINK_WIDTH_SHIFT 20 | |
1007 | #define PCICFG_LINK_SPEED 0xf0000 | |
1008 | #define PCICFG_LINK_SPEED_SHIFT 16 | |
a2fbb9ea | 1009 | |
bb2a0f7a | 1010 | |
66e855f3 | 1011 | #define BNX2X_NUM_STATS 42 |
d3d4f495 | 1012 | #define BNX2X_NUM_TESTS 7 |
bb2a0f7a YG |
1013 | |
1014 | #define BNX2X_MAC_LOOPBACK 0 | |
1015 | #define BNX2X_PHY_LOOPBACK 1 | |
1016 | #define BNX2X_MAC_LOOPBACK_FAILED 1 | |
1017 | #define BNX2X_PHY_LOOPBACK_FAILED 2 | |
1018 | #define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \ | |
1019 | BNX2X_PHY_LOOPBACK_FAILED) | |
96fc1784 | 1020 | |
7a9b2557 VZ |
1021 | |
1022 | #define STROM_ASSERT_ARRAY_SIZE 50 | |
1023 | ||
96fc1784 | 1024 | |
34f80b04 | 1025 | /* must be used on a CID before placing it on a HW ring */ |
7a9b2557 VZ |
1026 | #define HW_CID(bp, x) ((BP_PORT(bp) << 23) | (BP_E1HVN(bp) << 17) | x) |
1027 | ||
1028 | #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe)) | |
1029 | #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1) | |
1030 | ||
1031 | ||
1032 | #define BNX2X_BTR 3 | |
1033 | #define MAX_SPQ_PENDING 8 | |
a2fbb9ea | 1034 | |
a2fbb9ea | 1035 | |
34f80b04 EG |
1036 | /* CMNG constants |
1037 | derived from lab experiments, and not from system spec calculations !!! */ | |
1038 | #define DEF_MIN_RATE 100 | |
1039 | /* resolution of the rate shaping timer - 100 usec */ | |
1040 | #define RS_PERIODIC_TIMEOUT_USEC 100 | |
1041 | /* resolution of fairness algorithm in usecs - | |
33471629 | 1042 | coefficient for calculating the actual t fair */ |
34f80b04 EG |
1043 | #define T_FAIR_COEF 10000000 |
1044 | /* number of bytes in single QM arbitration cycle - | |
33471629 | 1045 | coefficient for calculating the fairness timer */ |
34f80b04 EG |
1046 | #define QM_ARB_BYTES 40000 |
1047 | #define FAIR_MEM 2 | |
1048 | ||
1049 | ||
1050 | #define ATTN_NIG_FOR_FUNC (1L << 8) | |
1051 | #define ATTN_SW_TIMER_4_FUNC (1L << 9) | |
1052 | #define GPIO_2_FUNC (1L << 10) | |
1053 | #define GPIO_3_FUNC (1L << 11) | |
1054 | #define GPIO_4_FUNC (1L << 12) | |
1055 | #define ATTN_GENERAL_ATTN_1 (1L << 13) | |
1056 | #define ATTN_GENERAL_ATTN_2 (1L << 14) | |
1057 | #define ATTN_GENERAL_ATTN_3 (1L << 15) | |
1058 | #define ATTN_GENERAL_ATTN_4 (1L << 13) | |
1059 | #define ATTN_GENERAL_ATTN_5 (1L << 14) | |
1060 | #define ATTN_GENERAL_ATTN_6 (1L << 15) | |
1061 | ||
1062 | #define ATTN_HARD_WIRED_MASK 0xff00 | |
1063 | #define ATTENTION_ID 4 | |
a2fbb9ea ET |
1064 | |
1065 | ||
34f80b04 EG |
1066 | /* stuff added to make the code fit 80Col */ |
1067 | ||
1068 | #define BNX2X_PMF_LINK_ASSERT \ | |
1069 | GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp)) | |
1070 | ||
a2fbb9ea ET |
1071 | #define BNX2X_MC_ASSERT_BITS \ |
1072 | (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ | |
1073 | GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \ | |
1074 | GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ | |
1075 | GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT)) | |
1076 | ||
1077 | #define BNX2X_MCP_ASSERT \ | |
1078 | GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT) | |
1079 | ||
1080 | #define BNX2X_DOORQ_ASSERT \ | |
1081 | AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT | |
1082 | ||
34f80b04 EG |
1083 | #define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC) |
1084 | #define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \ | |
1085 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \ | |
1086 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \ | |
1087 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \ | |
1088 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \ | |
1089 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC)) | |
1090 | ||
a2fbb9ea ET |
1091 | #define HW_INTERRUT_ASSERT_SET_0 \ |
1092 | (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \ | |
1093 | AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \ | |
1094 | AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \ | |
1095 | AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT) | |
34f80b04 | 1096 | #define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \ |
a2fbb9ea ET |
1097 | AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \ |
1098 | AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \ | |
1099 | AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\ | |
1100 | AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR) | |
1101 | #define HW_INTERRUT_ASSERT_SET_1 \ | |
1102 | (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \ | |
1103 | AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \ | |
1104 | AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \ | |
1105 | AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \ | |
1106 | AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \ | |
1107 | AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \ | |
1108 | AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \ | |
1109 | AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \ | |
1110 | AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \ | |
1111 | AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \ | |
1112 | AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT) | |
34f80b04 | 1113 | #define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR |\ |
a2fbb9ea ET |
1114 | AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \ |
1115 | AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \ | |
1116 | AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \ | |
1117 | AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\ | |
1118 | AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\ | |
1119 | AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \ | |
1120 | AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \ | |
1121 | AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \ | |
1122 | AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \ | |
1123 | AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR) | |
1124 | #define HW_INTERRUT_ASSERT_SET_2 \ | |
1125 | (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \ | |
1126 | AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \ | |
1127 | AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \ | |
1128 | AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\ | |
1129 | AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT) | |
34f80b04 | 1130 | #define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \ |
a2fbb9ea ET |
1131 | AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \ |
1132 | AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\ | |
1133 | AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \ | |
1134 | AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \ | |
1135 | AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \ | |
1136 | AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR) | |
1137 | ||
1138 | ||
555f6c78 | 1139 | #define MULTI_FLAGS(bp) \ |
34f80b04 EG |
1140 | (TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY | \ |
1141 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | \ | |
1142 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY | \ | |
1143 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | \ | |
555f6c78 EG |
1144 | (bp->multi_mode << \ |
1145 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT)) | |
a2fbb9ea | 1146 | |
34f80b04 | 1147 | #define MULTI_MASK 0x7f |
a2fbb9ea ET |
1148 | |
1149 | ||
34f80b04 EG |
1150 | #define DEF_USB_FUNC_OFF (2 + 2*HC_USTORM_DEF_SB_NUM_INDICES) |
1151 | #define DEF_CSB_FUNC_OFF (2 + 2*HC_CSTORM_DEF_SB_NUM_INDICES) | |
1152 | #define DEF_XSB_FUNC_OFF (2 + 2*HC_XSTORM_DEF_SB_NUM_INDICES) | |
1153 | #define DEF_TSB_FUNC_OFF (2 + 2*HC_TSTORM_DEF_SB_NUM_INDICES) | |
a2fbb9ea | 1154 | |
34f80b04 | 1155 | #define C_DEF_SB_SP_INDEX HC_INDEX_DEF_C_ETH_SLOW_PATH |
a2fbb9ea ET |
1156 | |
1157 | #define BNX2X_SP_DSB_INDEX \ | |
34f80b04 | 1158 | (&bp->def_status_blk->c_def_status_block.index_values[C_DEF_SB_SP_INDEX]) |
a2fbb9ea ET |
1159 | |
1160 | ||
1161 | #define CAM_IS_INVALID(x) \ | |
1162 | (x.target_table_entry.flags == TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE) | |
1163 | ||
1164 | #define CAM_INVALIDATE(x) \ | |
34f80b04 EG |
1165 | (x.target_table_entry.flags = TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE) |
1166 | ||
1167 | ||
1168 | /* Number of u32 elements in MC hash array */ | |
1169 | #define MC_HASH_SIZE 8 | |
1170 | #define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \ | |
1171 | TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4) | |
a2fbb9ea ET |
1172 | |
1173 | ||
34f80b04 EG |
1174 | #ifndef PXP2_REG_PXP2_INT_STS |
1175 | #define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0 | |
1176 | #endif | |
1177 | ||
a2fbb9ea ET |
1178 | /* MISC_REG_RESET_REG - this is here for the hsi to work don't touch */ |
1179 | ||
1180 | #endif /* bnx2x.h */ |