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bnx2x: Use VPD-R V0 entry to display firmware revision
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / bnx2x.h
CommitLineData
a2fbb9ea
ET		 1/* bnx2x.h: Broadcom Everest network driver.
2 *
3359fced 3 * Copyright (c) 2007-2010 Broadcom Corporation
a2fbb9ea
ET		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
24e3fcef
EG		 9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
a2fbb9ea
ET		 11 * Based on code from Michael Chan's bnx2 driver
12 */
13
14#ifndef BNX2X_H
15#define BNX2X_H
16
34f80b04
EG		 17/* compilation time flags */
18
19/* define this to make the driver freeze on error to allow getting debug info
20 * (you will need to reboot afterwards) */
21/* #define BNX2X_STOP_ON_ERROR */
22
0c6671b0
EG		 23#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
24#define BCM_VLAN 1
25#endif
26
993ac7b5
MC		 27#if defined(CONFIG_CNIC) || defined(CONFIG_CNIC_MODULE)
28#define BCM_CNIC 1
29#include "cnic_if.h"
30#endif
0c6671b0 31
555f6c78
EG		 32#define BNX2X_MULTI_QUEUE
33
34#define BNX2X_NEW_NAPI
35
359d8b15 36
01cd4528
EG		 37
38#include <linux/mdio.h>
359d8b15
EG		 39#include "bnx2x_reg.h"
40#include "bnx2x_fw_defs.h"
41#include "bnx2x_hsi.h"
42#include "bnx2x_link.h"
43
a2fbb9ea
ET		 44/* error/debug prints */
45
34f80b04 46#define DRV_MODULE_NAME "bnx2x"
a2fbb9ea
ET		 47
48/* for messages that are currently off */
34f80b04
EG		 49#define BNX2X_MSG_OFF 0
50#define BNX2X_MSG_MCP 0x010000 /* was: NETIF_MSG_HW */
51#define BNX2X_MSG_STATS 0x020000 /* was: NETIF_MSG_TIMER */
52#define BNX2X_MSG_NVM 0x040000 /* was: NETIF_MSG_HW */
53#define BNX2X_MSG_DMAE 0x080000 /* was: NETIF_MSG_HW */
f1410647
ET		 54#define BNX2X_MSG_SP 0x100000 /* was: NETIF_MSG_INTR */
55#define BNX2X_MSG_FP 0x200000 /* was: NETIF_MSG_INTR */
a2fbb9ea 56
34f80b04 57#define DP_LEVEL KERN_NOTICE /* was: KERN_DEBUG */
a2fbb9ea
ET		 58
59/* regular debug print */
7995c64e
JP		 60#define DP(__mask, __fmt, __args...) \
61do { \
62 if (bp->msg_enable & (__mask)) \
63 printk(DP_LEVEL "[%s:%d(%s)]" __fmt, \
64 __func__, __LINE__, \
65 bp->dev ? (bp->dev->name) : "?", \
66 ##__args); \
67} while (0)
a2fbb9ea 68
34f80b04 69/* errors debug print */
7995c64e
JP		 70#define BNX2X_DBG_ERR(__fmt, __args...) \
71do { \
72 if (netif_msg_probe(bp)) \
73 pr_err("[%s:%d(%s)]" __fmt, \
74 __func__, __LINE__, \
75 bp->dev ? (bp->dev->name) : "?", \
76 ##__args); \
77} while (0)
a2fbb9ea 78
34f80b04 79/* for errors (never masked) */
7995c64e
JP		 80#define BNX2X_ERR(__fmt, __args...) \
81do { \
82 pr_err("[%s:%d(%s)]" __fmt, \
83 __func__, __LINE__, \
84 bp->dev ? (bp->dev->name) : "?", \
85 ##__args); \
86} while (0)
f1410647 87
a2fbb9ea 88/* before we have a dev->name use dev_info() */
7995c64e
JP		 89#define BNX2X_DEV_INFO(__fmt, __args...) \
90do { \
91 if (netif_msg_probe(bp)) \
92 dev_info(&bp->pdev->dev, __fmt, ##__args); \
93} while (0)
a2fbb9ea
ET		 94
95
96#ifdef BNX2X_STOP_ON_ERROR
97#define bnx2x_panic() do { \
98 bp->panic = 1; \
99 BNX2X_ERR("driver assert\n"); \
34f80b04 100 bnx2x_int_disable(bp); \
a2fbb9ea
ET		 101 bnx2x_panic_dump(bp); \
102 } while (0)
103#else
104#define bnx2x_panic() do { \
e3553b29 105 bp->panic = 1; \
a2fbb9ea
ET		 106 BNX2X_ERR("driver assert\n"); \
107 bnx2x_panic_dump(bp); \
108 } while (0)
109#endif
110
111
34f80b04
EG		 112#define U64_LO(x) (u32)(((u64)(x)) & 0xffffffff)
113#define U64_HI(x) (u32)(((u64)(x)) >> 32)
114#define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))
a2fbb9ea 115
a2fbb9ea 116
34f80b04 117#define REG_ADDR(bp, offset) (bp->regview + offset)
a2fbb9ea 118
34f80b04
EG		 119#define REG_RD(bp, offset) readl(REG_ADDR(bp, offset))
120#define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset))
34f80b04
EG		 121
122#define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset))
a2fbb9ea 123#define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset))
34f80b04 124#define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset))
a2fbb9ea 125
34f80b04
EG		 126#define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset)
127#define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val)
a2fbb9ea 128
c18487ee
YR		 129#define REG_RD_DMAE(bp, offset, valp, len32) \
130 do { \
131 bnx2x_read_dmae(bp, offset, len32);\
573f2035 132 memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \
c18487ee
YR		 133 } while (0)
134
34f80b04 135#define REG_WR_DMAE(bp, offset, valp, len32) \
a2fbb9ea 136 do { \
573f2035 137 memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \
a2fbb9ea
ET		 138 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \
139 offset, len32); \
140 } while (0)
141
3359fced 142#define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) \
573f2035
EG		 143 do { \
144 memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \
145 bnx2x_write_big_buf_wb(bp, addr, len32); \
146 } while (0)
147
34f80b04
EG		 148#define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \
149 offsetof(struct shmem_region, field))
150#define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field))
151#define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val)
a2fbb9ea 152
2691d51d
EG		 153#define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \
154 offsetof(struct shmem2_region, field))
155#define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field))
156#define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val)
157
72fd0718
VZ		 158#define MF_CFG_RD(bp, field) SHMEM_RD(bp, mf_cfg.field)
159#define MF_CFG_WR(bp, field, val) SHMEM_WR(bp, mf_cfg.field, val)
160
345b5d52 161#define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg)
3196a88a 162#define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val)
a2fbb9ea 163
72fd0718
VZ		 164#define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \
165 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR
166
a2fbb9ea 167
7a9b2557 168/* fast path */
a2fbb9ea 169
a2fbb9ea 170struct sw_rx_bd {
34f80b04 171 struct sk_buff *skb;
1a983142 172 DEFINE_DMA_UNMAP_ADDR(mapping);
a2fbb9ea
ET		 173};
174
175struct sw_tx_bd {
34f80b04
EG		 176 struct sk_buff *skb;
177 u16 first_bd;
ca00392c
EG		 178 u8 flags;
179/* Set on the first BD descriptor when there is a split BD */
180#define BNX2X_TSO_SPLIT_BD (1<<0)
a2fbb9ea
ET		 181};
182
7a9b2557
VZ		 183struct sw_rx_page {
184 struct page *page;
1a983142 185 DEFINE_DMA_UNMAP_ADDR(mapping);
7a9b2557
VZ		 186};
187
ca00392c
EG		 188union db_prod {
189 struct doorbell_set_prod data;
190 u32 raw;
191};
192
7a9b2557
VZ		 193
194/* MC hsi */
195#define BCM_PAGE_SHIFT 12
196#define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT)
197#define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1))
198#define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK)
199
200#define PAGES_PER_SGE_SHIFT 0
201#define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT)
4f40f2cb
EG		 202#define SGE_PAGE_SIZE PAGE_SIZE
203#define SGE_PAGE_SHIFT PAGE_SHIFT
5b6402d1 204#define SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))(addr))
7a9b2557
VZ		 205
206/* SGE ring related macros */
207#define NUM_RX_SGE_PAGES 2
208#define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
209#define MAX_RX_SGE_CNT (RX_SGE_CNT - 2)
33471629 210/* RX_SGE_CNT is promised to be a power of 2 */
7a9b2557
VZ		 211#define RX_SGE_MASK (RX_SGE_CNT - 1)
212#define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES)
213#define MAX_RX_SGE (NUM_RX_SGE - 1)
214#define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \
215 (MAX_RX_SGE_CNT - 1)) ? (x) + 3 : (x) + 1)
216#define RX_SGE(x) ((x) & MAX_RX_SGE)
217
218/* SGE producer mask related macros */
219/* Number of bits in one sge_mask array element */
220#define RX_SGE_MASK_ELEM_SZ 64
221#define RX_SGE_MASK_ELEM_SHIFT 6
222#define RX_SGE_MASK_ELEM_MASK ((u64)RX_SGE_MASK_ELEM_SZ - 1)
223
224/* Creates a bitmask of all ones in less significant bits.
225 idx - index of the most significant bit in the created mask */
226#define RX_SGE_ONES_MASK(idx) \
227 (((u64)0x1 << (((idx) & RX_SGE_MASK_ELEM_MASK) + 1)) - 1)
228#define RX_SGE_MASK_ELEM_ONE_MASK ((u64)(~0))
229
230/* Number of u64 elements in SGE mask array */
231#define RX_SGE_MASK_LEN ((NUM_RX_SGE_PAGES * RX_SGE_CNT) / \
232 RX_SGE_MASK_ELEM_SZ)
233#define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1)
234#define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK)
235
236
de832a55
EG		 237struct bnx2x_eth_q_stats {
238 u32 total_bytes_received_hi;
239 u32 total_bytes_received_lo;
240 u32 total_bytes_transmitted_hi;
241 u32 total_bytes_transmitted_lo;
242 u32 total_unicast_packets_received_hi;
243 u32 total_unicast_packets_received_lo;
244 u32 total_multicast_packets_received_hi;
245 u32 total_multicast_packets_received_lo;
246 u32 total_broadcast_packets_received_hi;
247 u32 total_broadcast_packets_received_lo;
248 u32 total_unicast_packets_transmitted_hi;
249 u32 total_unicast_packets_transmitted_lo;
250 u32 total_multicast_packets_transmitted_hi;
251 u32 total_multicast_packets_transmitted_lo;
252 u32 total_broadcast_packets_transmitted_hi;
253 u32 total_broadcast_packets_transmitted_lo;
254 u32 valid_bytes_received_hi;
255 u32 valid_bytes_received_lo;
256
257 u32 error_bytes_received_hi;
258 u32 error_bytes_received_lo;
259 u32 etherstatsoverrsizepkts_hi;
260 u32 etherstatsoverrsizepkts_lo;
261 u32 no_buff_discard_hi;
262 u32 no_buff_discard_lo;
263
264 u32 driver_xoff;
265 u32 rx_err_discard_pkt;
266 u32 rx_skb_alloc_failed;
267 u32 hw_csum_err;
268};
269
270#define BNX2X_NUM_Q_STATS 11
271#define Q_STATS_OFFSET32(stat_name) \
272 (offsetof(struct bnx2x_eth_q_stats, stat_name) / 4)
273
a2fbb9ea
ET		 274struct bnx2x_fastpath {
275
34f80b04 276 struct napi_struct napi;
a2fbb9ea 277 struct host_status_block *status_blk;
34f80b04 278 dma_addr_t status_blk_mapping;
a2fbb9ea 279
34f80b04 280 struct sw_tx_bd *tx_buf_ring;
a2fbb9ea 281
ca00392c 282 union eth_tx_bd_types *tx_desc_ring;
34f80b04 283 dma_addr_t tx_desc_mapping;
a2fbb9ea 284
7a9b2557
VZ		 285 struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */
286 struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */
a2fbb9ea
ET		 287
288 struct eth_rx_bd *rx_desc_ring;
34f80b04 289 dma_addr_t rx_desc_mapping;
a2fbb9ea
ET		 290
291 union eth_rx_cqe *rx_comp_ring;
34f80b04
EG		 292 dma_addr_t rx_comp_mapping;
293
7a9b2557
VZ		 294 /* SGE ring */
295 struct eth_rx_sge *rx_sge_ring;
296 dma_addr_t rx_sge_mapping;
297
298 u64 sge_mask[RX_SGE_MASK_LEN];
299
34f80b04
EG		 300 int state;
301#define BNX2X_FP_STATE_CLOSED 0
302#define BNX2X_FP_STATE_IRQ 0x80000
303#define BNX2X_FP_STATE_OPENING 0x90000
304#define BNX2X_FP_STATE_OPEN 0xa0000
305#define BNX2X_FP_STATE_HALTING 0xb0000
306#define BNX2X_FP_STATE_HALTED 0xc0000
307
308 u8 index; /* number in fp array */
309 u8 cl_id; /* eth client id */
310 u8 sb_id; /* status block number in HW */
34f80b04 311
ca00392c
EG		 312 union db_prod tx_db;
313
34f80b04
EG		 314 u16 tx_pkt_prod;
315 u16 tx_pkt_cons;
316 u16 tx_bd_prod;
317 u16 tx_bd_cons;
4781bfad 318 __le16 *tx_cons_sb;
34f80b04 319
4781bfad
EG		 320 __le16 fp_c_idx;
321 __le16 fp_u_idx;
34f80b04
EG		 322
323 u16 rx_bd_prod;
324 u16 rx_bd_cons;
325 u16 rx_comp_prod;
326 u16 rx_comp_cons;
7a9b2557
VZ		 327 u16 rx_sge_prod;
328 /* The last maximal completed SGE */
329 u16 last_max_sge;
4781bfad
EG		 330 __le16 *rx_cons_sb;
331 __le16 *rx_bd_cons_sb;
34f80b04 332
ab6ad5a4 333
34f80b04 334 unsigned long tx_pkt,
a2fbb9ea 335 rx_pkt,
66e855f3 336 rx_calls;
ab6ad5a4 337
7a9b2557
VZ		 338 /* TPA related */
339 struct sw_rx_bd tpa_pool[ETH_MAX_AGGREGATION_QUEUES_E1H];
340 u8 tpa_state[ETH_MAX_AGGREGATION_QUEUES_E1H];
341#define BNX2X_TPA_START 1
342#define BNX2X_TPA_STOP 2
343 u8 disable_tpa;
344#ifdef BNX2X_STOP_ON_ERROR
345 u64 tpa_queue_used;
346#endif
a2fbb9ea 347
de832a55
EG		 348 struct tstorm_per_client_stats old_tclient;
349 struct ustorm_per_client_stats old_uclient;
350 struct xstorm_per_client_stats old_xclient;
351 struct bnx2x_eth_q_stats eth_q_stats;
352
ca00392c
EG		 353 /* The size is calculated using the following:
354 sizeof name field from netdev structure +
355 4 ('-Xx-' string) +
356 4 (for the digits and to make it DWORD aligned) */
357#define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8)
358 char name[FP_NAME_SIZE];
34f80b04 359 struct bnx2x *bp; /* parent */
a2fbb9ea
ET		 360};
361
34f80b04 362#define bnx2x_fp(bp, nr, var) (bp->fp[nr].var)
7a9b2557
VZ		 363
364
365/* MC hsi */
366#define MAX_FETCH_BD 13 /* HW max BDs per packet */
367#define RX_COPY_THRESH 92
368
369#define NUM_TX_RINGS 16
ca00392c 370#define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types))
7a9b2557
VZ		 371#define MAX_TX_DESC_CNT (TX_DESC_CNT - 1)
372#define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS)
373#define MAX_TX_BD (NUM_TX_BD - 1)
374#define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2)
375#define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \
376 (MAX_TX_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
377#define TX_BD(x) ((x) & MAX_TX_BD)
378#define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT)
379
380/* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */
381#define NUM_RX_RINGS 8
382#define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
383#define MAX_RX_DESC_CNT (RX_DESC_CNT - 2)
384#define RX_DESC_MASK (RX_DESC_CNT - 1)
385#define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS)
386#define MAX_RX_BD (NUM_RX_BD - 1)
387#define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2)
388#define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \
389 (MAX_RX_DESC_CNT - 1)) ? (x) + 3 : (x) + 1)
390#define RX_BD(x) ((x) & MAX_RX_BD)
391
392/* As long as CQE is 4 times bigger than BD entry we have to allocate
393 4 times more pages for CQ ring in order to keep it balanced with
394 BD ring */
395#define NUM_RCQ_RINGS (NUM_RX_RINGS * 4)
396#define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
397#define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - 1)
398#define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS)
399#define MAX_RCQ_BD (NUM_RCQ_BD - 1)
400#define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2)
401#define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \
402 (MAX_RCQ_DESC_CNT - 1)) ? (x) + 2 : (x) + 1)
403#define RCQ_BD(x) ((x) & MAX_RCQ_BD)
404
405
33471629 406/* This is needed for determining of last_max */
34f80b04 407#define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b))
a2fbb9ea 408
7a9b2557
VZ		 409#define __SGE_MASK_SET_BIT(el, bit) \
410 do { \
411 el = ((el) | ((u64)0x1 << (bit))); \
412 } while (0)
413
414#define __SGE_MASK_CLEAR_BIT(el, bit) \
415 do { \
416 el = ((el) & (~((u64)0x1 << (bit)))); \
417 } while (0)
418
419#define SGE_MASK_SET_BIT(fp, idx) \
420 __SGE_MASK_SET_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
421 ((idx) & RX_SGE_MASK_ELEM_MASK))
422
423#define SGE_MASK_CLEAR_BIT(fp, idx) \
424 __SGE_MASK_CLEAR_BIT(fp->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
425 ((idx) & RX_SGE_MASK_ELEM_MASK))
426
427
428/* used on a CID received from the HW */
429#define SW_CID(x) (le32_to_cpu(x) & \
430 (COMMON_RAMROD_ETH_RX_CQE_CID >> 7))
431#define CQE_CMD(x) (le32_to_cpu(x) >> \
432 COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
433
bb2a0f7a
YG		 434#define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \
435 le32_to_cpu((bd)->addr_lo))
436#define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes))
437
7a9b2557
VZ		 438
439#define DPM_TRIGER_TYPE 0x40
440#define DOORBELL(bp, cid, val) \
441 do { \
ca00392c 442 writel((u32)(val), bp->doorbells + (BCM_PAGE_SIZE * (cid)) + \
7a9b2557
VZ		 443 DPM_TRIGER_TYPE); \
444 } while (0)
445
446
447/* TX CSUM helpers */
448#define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \
449 skb->csum_offset)
450#define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \
451 skb->csum_offset))
452
453#define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff)
454
455#define XMIT_PLAIN 0
456#define XMIT_CSUM_V4 0x1
457#define XMIT_CSUM_V6 0x2
458#define XMIT_CSUM_TCP 0x4
459#define XMIT_GSO_V4 0x8
460#define XMIT_GSO_V6 0x10
461
462#define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6)
463#define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6)
464
465
34f80b04 466/* stuff added to make the code fit 80Col */
a2fbb9ea 467
34f80b04 468#define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
a2fbb9ea 469
7a9b2557
VZ		 470#define TPA_TYPE_START ETH_FAST_PATH_RX_CQE_START_FLG
471#define TPA_TYPE_END ETH_FAST_PATH_RX_CQE_END_FLG
472#define TPA_TYPE(cqe_fp_flags) ((cqe_fp_flags) & \
473 (TPA_TYPE_START | TPA_TYPE_END))
474
1adcd8be
EG		 475#define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG
476
477#define BNX2X_IP_CSUM_ERR(cqe) \
478 (!((cqe)->fast_path_cqe.status_flags & \
479 ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG) && \
480 ((cqe)->fast_path_cqe.type_error_flags & \
481 ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG))
482
483#define BNX2X_L4_CSUM_ERR(cqe) \
484 (!((cqe)->fast_path_cqe.status_flags & \
485 ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG) && \
486 ((cqe)->fast_path_cqe.type_error_flags & \
487 ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG))
488
489#define BNX2X_RX_CSUM_OK(cqe) \
490 (!(BNX2X_L4_CSUM_ERR(cqe) || BNX2X_IP_CSUM_ERR(cqe)))
7a9b2557 491
052a38e0
EG		 492#define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \
493 (((le16_to_cpu(flags) & \
494 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \
495 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \
496 == PRS_FLAG_OVERETH_IPV4)
7a9b2557 497#define BNX2X_RX_SUM_FIX(cqe) \
052a38e0 498 BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags)
7a9b2557 499
a2fbb9ea 500
bb2a0f7a
YG		 501#define FP_USB_FUNC_OFF (2 + 2*HC_USTORM_SB_NUM_INDICES)
502#define FP_CSB_FUNC_OFF (2 + 2*HC_CSTORM_SB_NUM_INDICES)
503
34f80b04
EG		 504#define U_SB_ETH_RX_CQ_INDEX HC_INDEX_U_ETH_RX_CQ_CONS
505#define U_SB_ETH_RX_BD_INDEX HC_INDEX_U_ETH_RX_BD_CONS
506#define C_SB_ETH_TX_CQ_INDEX HC_INDEX_C_ETH_TX_CQ_CONS
a2fbb9ea 507
34f80b04
EG		 508#define BNX2X_RX_SB_INDEX \
509 (&fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_CQ_INDEX])
a2fbb9ea 510
34f80b04
EG		 511#define BNX2X_RX_SB_BD_INDEX \
512 (&fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_BD_INDEX])
a2fbb9ea 513
34f80b04
EG		 514#define BNX2X_RX_SB_INDEX_NUM \
515 (((U_SB_ETH_RX_CQ_INDEX << \
516 USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER_SHIFT) & \
517 USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER) | \
518 ((U_SB_ETH_RX_BD_INDEX << \
519 USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER_SHIFT) & \
520 USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER))
a2fbb9ea 521
34f80b04
EG		 522#define BNX2X_TX_SB_INDEX \
523 (&fp->status_blk->c_status_block.index_values[C_SB_ETH_TX_CQ_INDEX])
a2fbb9ea 524
7a9b2557
VZ		 525
526/* end of fast path */
527
34f80b04 528/* common */
a2fbb9ea 529
34f80b04 530struct bnx2x_common {
a2fbb9ea 531
ad8d3948 532 u32 chip_id;
a2fbb9ea 533/* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
34f80b04 534#define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0)
ad8d3948 535
34f80b04 536#define CHIP_NUM(bp) (bp->common.chip_id >> 16)
ad8d3948
EG		 537#define CHIP_NUM_57710 0x164e
538#define CHIP_NUM_57711 0x164f
539#define CHIP_NUM_57711E 0x1650
540#define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710)
541#define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711)
542#define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E)
543#define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \
544 CHIP_IS_57711E(bp))
545#define IS_E1H_OFFSET CHIP_IS_E1H(bp)
546
34f80b04 547#define CHIP_REV(bp) (bp->common.chip_id & 0x0000f000)
ad8d3948
EG		 548#define CHIP_REV_Ax 0x00000000
549/* assume maximum 5 revisions */
550#define CHIP_REV_IS_SLOW(bp) (CHIP_REV(bp) > 0x00005000)
551/* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */
552#define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \
553 !(CHIP_REV(bp) & 0x00001000))
554/* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */
555#define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \
556 (CHIP_REV(bp) & 0x00001000))
557
558#define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \
559 ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1))
560
34f80b04
EG		 561#define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0)
562#define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f)
a2fbb9ea 563
34f80b04
EG		 564 int flash_size;
565#define NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */
566#define NVRAM_TIMEOUT_COUNT 30000
567#define NVRAM_PAGE_SIZE 256
a2fbb9ea 568
34f80b04 569 u32 shmem_base;
2691d51d 570 u32 shmem2_base;
34f80b04
EG		 571
572 u32 hw_config;
c18487ee 573
34f80b04 574 u32 bc_ver;
34f80b04 575};
c18487ee 576
34f80b04
EG		 577
578/* end of common */
579
580/* port */
581
bb2a0f7a
YG		 582struct nig_stats {
583 u32 brb_discard;
584 u32 brb_packet;
585 u32 brb_truncate;
586 u32 flow_ctrl_discard;
587 u32 flow_ctrl_octets;
588 u32 flow_ctrl_packet;
589 u32 mng_discard;
590 u32 mng_octet_inp;
591 u32 mng_octet_out;
592 u32 mng_packet_inp;
593 u32 mng_packet_out;
594 u32 pbf_octets;
595 u32 pbf_packet;
596 u32 safc_inp;
597 u32 egress_mac_pkt0_lo;
598 u32 egress_mac_pkt0_hi;
599 u32 egress_mac_pkt1_lo;
600 u32 egress_mac_pkt1_hi;
601};
602
34f80b04
EG		 603struct bnx2x_port {
604 u32 pmf;
c18487ee
YR		 605
606 u32 link_config;
a2fbb9ea 607
34f80b04
EG		 608 u32 supported;
609/* link settings - missing defines */
610#define SUPPORTED_2500baseX_Full (1 << 15)
611
612 u32 advertising;
a2fbb9ea 613/* link settings - missing defines */
34f80b04 614#define ADVERTISED_2500baseX_Full (1 << 15)
a2fbb9ea 615
34f80b04 616 u32 phy_addr;
c18487ee
YR		 617
618 /* used to synchronize phy accesses */
619 struct mutex phy_mutex;
46c6a674 620 int need_hw_lock;
c18487ee 621
34f80b04 622 u32 port_stx;
a2fbb9ea 623
34f80b04
EG		 624 struct nig_stats old_nig_stats;
625};
a2fbb9ea 626
34f80b04
EG		 627/* end of port */
628
bb2a0f7a
YG		 629
630enum bnx2x_stats_event {
631 STATS_EVENT_PMF = 0,
632 STATS_EVENT_LINK_UP,
633 STATS_EVENT_UPDATE,
634 STATS_EVENT_STOP,
635 STATS_EVENT_MAX
636};
637
638enum bnx2x_stats_state {
639 STATS_STATE_DISABLED = 0,
640 STATS_STATE_ENABLED,
641 STATS_STATE_MAX
642};
643
644struct bnx2x_eth_stats {
645 u32 total_bytes_received_hi;
646 u32 total_bytes_received_lo;
647 u32 total_bytes_transmitted_hi;
648 u32 total_bytes_transmitted_lo;
649 u32 total_unicast_packets_received_hi;
650 u32 total_unicast_packets_received_lo;
651 u32 total_multicast_packets_received_hi;
652 u32 total_multicast_packets_received_lo;
653 u32 total_broadcast_packets_received_hi;
654 u32 total_broadcast_packets_received_lo;
655 u32 total_unicast_packets_transmitted_hi;
656 u32 total_unicast_packets_transmitted_lo;
657 u32 total_multicast_packets_transmitted_hi;
658 u32 total_multicast_packets_transmitted_lo;
659 u32 total_broadcast_packets_transmitted_hi;
660 u32 total_broadcast_packets_transmitted_lo;
661 u32 valid_bytes_received_hi;
662 u32 valid_bytes_received_lo;
663
664 u32 error_bytes_received_hi;
665 u32 error_bytes_received_lo;
de832a55
EG		 666 u32 etherstatsoverrsizepkts_hi;
667 u32 etherstatsoverrsizepkts_lo;
668 u32 no_buff_discard_hi;
669 u32 no_buff_discard_lo;
bb2a0f7a
YG		 670
671 u32 rx_stat_ifhcinbadoctets_hi;
672 u32 rx_stat_ifhcinbadoctets_lo;
673 u32 tx_stat_ifhcoutbadoctets_hi;
674 u32 tx_stat_ifhcoutbadoctets_lo;
675 u32 rx_stat_dot3statsfcserrors_hi;
676 u32 rx_stat_dot3statsfcserrors_lo;
677 u32 rx_stat_dot3statsalignmenterrors_hi;
678 u32 rx_stat_dot3statsalignmenterrors_lo;
679 u32 rx_stat_dot3statscarriersenseerrors_hi;
680 u32 rx_stat_dot3statscarriersenseerrors_lo;
681 u32 rx_stat_falsecarriererrors_hi;
682 u32 rx_stat_falsecarriererrors_lo;
683 u32 rx_stat_etherstatsundersizepkts_hi;
684 u32 rx_stat_etherstatsundersizepkts_lo;
685 u32 rx_stat_dot3statsframestoolong_hi;
686 u32 rx_stat_dot3statsframestoolong_lo;
687 u32 rx_stat_etherstatsfragments_hi;
688 u32 rx_stat_etherstatsfragments_lo;
689 u32 rx_stat_etherstatsjabbers_hi;
690 u32 rx_stat_etherstatsjabbers_lo;
691 u32 rx_stat_maccontrolframesreceived_hi;
692 u32 rx_stat_maccontrolframesreceived_lo;
693 u32 rx_stat_bmac_xpf_hi;
694 u32 rx_stat_bmac_xpf_lo;
695 u32 rx_stat_bmac_xcf_hi;
696 u32 rx_stat_bmac_xcf_lo;
697 u32 rx_stat_xoffstateentered_hi;
698 u32 rx_stat_xoffstateentered_lo;
699 u32 rx_stat_xonpauseframesreceived_hi;
700 u32 rx_stat_xonpauseframesreceived_lo;
701 u32 rx_stat_xoffpauseframesreceived_hi;
702 u32 rx_stat_xoffpauseframesreceived_lo;
703 u32 tx_stat_outxonsent_hi;
704 u32 tx_stat_outxonsent_lo;
705 u32 tx_stat_outxoffsent_hi;
706 u32 tx_stat_outxoffsent_lo;
707 u32 tx_stat_flowcontroldone_hi;
708 u32 tx_stat_flowcontroldone_lo;
709 u32 tx_stat_etherstatscollisions_hi;
710 u32 tx_stat_etherstatscollisions_lo;
711 u32 tx_stat_dot3statssinglecollisionframes_hi;
712 u32 tx_stat_dot3statssinglecollisionframes_lo;
713 u32 tx_stat_dot3statsmultiplecollisionframes_hi;
714 u32 tx_stat_dot3statsmultiplecollisionframes_lo;
715 u32 tx_stat_dot3statsdeferredtransmissions_hi;
716 u32 tx_stat_dot3statsdeferredtransmissions_lo;
717 u32 tx_stat_dot3statsexcessivecollisions_hi;
718 u32 tx_stat_dot3statsexcessivecollisions_lo;
719 u32 tx_stat_dot3statslatecollisions_hi;
720 u32 tx_stat_dot3statslatecollisions_lo;
721 u32 tx_stat_etherstatspkts64octets_hi;
722 u32 tx_stat_etherstatspkts64octets_lo;
723 u32 tx_stat_etherstatspkts65octetsto127octets_hi;
724 u32 tx_stat_etherstatspkts65octetsto127octets_lo;
725 u32 tx_stat_etherstatspkts128octetsto255octets_hi;
726 u32 tx_stat_etherstatspkts128octetsto255octets_lo;
727 u32 tx_stat_etherstatspkts256octetsto511octets_hi;
728 u32 tx_stat_etherstatspkts256octetsto511octets_lo;
729 u32 tx_stat_etherstatspkts512octetsto1023octets_hi;
730 u32 tx_stat_etherstatspkts512octetsto1023octets_lo;
731 u32 tx_stat_etherstatspkts1024octetsto1522octets_hi;
732 u32 tx_stat_etherstatspkts1024octetsto1522octets_lo;
733 u32 tx_stat_etherstatspktsover1522octets_hi;
734 u32 tx_stat_etherstatspktsover1522octets_lo;
735 u32 tx_stat_bmac_2047_hi;
736 u32 tx_stat_bmac_2047_lo;
737 u32 tx_stat_bmac_4095_hi;
738 u32 tx_stat_bmac_4095_lo;
739 u32 tx_stat_bmac_9216_hi;
740 u32 tx_stat_bmac_9216_lo;
741 u32 tx_stat_bmac_16383_hi;
742 u32 tx_stat_bmac_16383_lo;
743 u32 tx_stat_dot3statsinternalmactransmiterrors_hi;
744 u32 tx_stat_dot3statsinternalmactransmiterrors_lo;
745 u32 tx_stat_bmac_ufl_hi;
746 u32 tx_stat_bmac_ufl_lo;
747
de832a55
EG		 748 u32 pause_frames_received_hi;
749 u32 pause_frames_received_lo;
750 u32 pause_frames_sent_hi;
751 u32 pause_frames_sent_lo;
bb2a0f7a
YG		 752
753 u32 etherstatspkts1024octetsto1522octets_hi;
754 u32 etherstatspkts1024octetsto1522octets_lo;
755 u32 etherstatspktsover1522octets_hi;
756 u32 etherstatspktsover1522octets_lo;
757
de832a55
EG		 758 u32 brb_drop_hi;
759 u32 brb_drop_lo;
760 u32 brb_truncate_hi;
761 u32 brb_truncate_lo;
bb2a0f7a
YG		 762
763 u32 mac_filter_discard;
764 u32 xxoverflow_discard;
765 u32 brb_truncate_discard;
766 u32 mac_discard;
767
768 u32 driver_xoff;
66e855f3
YG		 769 u32 rx_err_discard_pkt;
770 u32 rx_skb_alloc_failed;
771 u32 hw_csum_err;
de832a55
EG		 772
773 u32 nig_timer_max;
bb2a0f7a
YG		 774};
775
de832a55 776#define BNX2X_NUM_STATS 41
bb2a0f7a
YG		 777#define STATS_OFFSET32(stat_name) \
778 (offsetof(struct bnx2x_eth_stats, stat_name) / 4)
779
34f80b04 780
37b091ba
MC		 781#ifdef BCM_CNIC
782#define MAX_CONTEXT 15
783#else
34f80b04 784#define MAX_CONTEXT 16
37b091ba 785#endif
34f80b04
EG		 786
787union cdu_context {
788 struct eth_context eth;
789 char pad[1024];
790};
791
bb2a0f7a 792#define MAX_DMAE_C 8
34f80b04
EG		 793
794/* DMA memory not used in fastpath */
795struct bnx2x_slowpath {
796 union cdu_context context[MAX_CONTEXT];
797 struct eth_stats_query fw_stats;
798 struct mac_configuration_cmd mac_config;
799 struct mac_configuration_cmd mcast_config;
800
801 /* used by dmae command executer */
802 struct dmae_command dmae[MAX_DMAE_C];
803
bb2a0f7a
YG		 804 u32 stats_comp;
805 union mac_stats mac_stats;
806 struct nig_stats nig_stats;
807 struct host_port_stats port_stats;
808 struct host_func_stats func_stats;
6fe49bb9 809 struct host_func_stats func_stats_base;
34f80b04
EG		 810
811 u32 wb_comp;
34f80b04
EG		 812 u32 wb_data[4];
813};
814
815#define bnx2x_sp(bp, var) (&bp->slowpath->var)
816#define bnx2x_sp_mapping(bp, var) \
817 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var))
818
819
820/* attn group wiring */
821#define MAX_DYNAMIC_ATTN_GRPS 8
822
823struct attn_route {
824 u32 sig[4];
825};
826
72fd0718
VZ		 827typedef enum {
828 BNX2X_RECOVERY_DONE,
829 BNX2X_RECOVERY_INIT,
830 BNX2X_RECOVERY_WAIT,
831} bnx2x_recovery_state_t;
832
34f80b04
EG		 833struct bnx2x {
834 /* Fields used in the tx and intr/napi performance paths
835 * are grouped together in the beginning of the structure
836 */
837 struct bnx2x_fastpath fp[MAX_CONTEXT];
838 void __iomem *regview;
839 void __iomem *doorbells;
37b091ba
MC		 840#ifdef BCM_CNIC
841#define BNX2X_DB_SIZE (18*BCM_PAGE_SIZE)
842#else
a5f67a04 843#define BNX2X_DB_SIZE (16*BCM_PAGE_SIZE)
37b091ba 844#endif
34f80b04
EG		 845
846 struct net_device *dev;
847 struct pci_dev *pdev;
848
849 atomic_t intr_sem;
72fd0718
VZ		 850
851 bnx2x_recovery_state_t recovery_state;
852 int is_leader;
37b091ba
MC		 853#ifdef BCM_CNIC
854 struct msix_entry msix_table[MAX_CONTEXT+2];
855#else
7a9b2557 856 struct msix_entry msix_table[MAX_CONTEXT+1];
37b091ba 857#endif
8badd27a
EG		 858#define INT_MODE_INTx 1
859#define INT_MODE_MSI 2
860#define INT_MODE_MSIX 3
34f80b04
EG		 861
862 int tx_ring_size;
863
864#ifdef BCM_VLAN
865 struct vlan_group *vlgrp;
866#endif
a2fbb9ea 867
34f80b04 868 u32 rx_csum;
437cf2f1 869 u32 rx_buf_size;
34f80b04
EG		 870#define ETH_OVREHEAD (ETH_HLEN + 8) /* 8 for CRC + VLAN */
871#define ETH_MIN_PACKET_SIZE 60
872#define ETH_MAX_PACKET_SIZE 1500
873#define ETH_MAX_JUMBO_PACKET_SIZE 9600
a2fbb9ea 874
0f00846d
EG		 875 /* Max supported alignment is 256 (8 shift) */
876#define BNX2X_RX_ALIGN_SHIFT ((L1_CACHE_SHIFT < 8) ? \
877 L1_CACHE_SHIFT : 8)
878#define BNX2X_RX_ALIGN (1 << BNX2X_RX_ALIGN_SHIFT)
879
34f80b04
EG		 880 struct host_def_status_block *def_status_blk;
881#define DEF_SB_ID 16
4781bfad
EG		 882 __le16 def_c_idx;
883 __le16 def_u_idx;
884 __le16 def_x_idx;
885 __le16 def_t_idx;
886 __le16 def_att_idx;
34f80b04
EG		 887 u32 attn_state;
888 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS];
34f80b04
EG		 889
890 /* slow path ring */
891 struct eth_spe *spq;
892 dma_addr_t spq_mapping;
893 u16 spq_prod_idx;
894 struct eth_spe *spq_prod_bd;
895 struct eth_spe *spq_last_bd;
4781bfad 896 __le16 *dsb_sp_prod;
34f80b04
EG		 897 u16 spq_left; /* serialize spq */
898 /* used to synchronize spq accesses */
899 spinlock_t spq_lock;
900
bb2a0f7a
YG		 901 /* Flags for marking that there is a STAT_QUERY or
902 SET_MAC ramrod pending */
e665bfda
MC		 903 int stats_pending;
904 int set_mac_pending;
34f80b04 905
33471629 906 /* End of fields used in the performance code paths */
34f80b04
EG		 907
908 int panic;
7995c64e 909 int msg_enable;
34f80b04
EG		 910
911 u32 flags;
912#define PCIX_FLAG 1
913#define PCI_32BIT_FLAG 2
1c06328c 914#define ONE_PORT_FLAG 4
34f80b04
EG		 915#define NO_WOL_FLAG 8
916#define USING_DAC_FLAG 0x10
917#define USING_MSIX_FLAG 0x20
8badd27a 918#define USING_MSI_FLAG 0x40
7a9b2557 919#define TPA_ENABLE_FLAG 0x80
34f80b04
EG		 920#define NO_MCP_FLAG 0x100
921#define BP_NOMCP(bp) (bp->flags & NO_MCP_FLAG)
0c6671b0
EG		 922#define HW_VLAN_TX_FLAG 0x400
923#define HW_VLAN_RX_FLAG 0x800
f34d28ea 924#define MF_FUNC_DIS 0x1000
34f80b04
EG		 925
926 int func;
927#define BP_PORT(bp) (bp->func % PORT_MAX)
928#define BP_FUNC(bp) (bp->func)
929#define BP_E1HVN(bp) (bp->func >> 1)
930#define BP_L_ID(bp) (BP_E1HVN(bp) << 2)
34f80b04 931
37b091ba
MC		 932#ifdef BCM_CNIC
933#define BCM_CNIC_CID_START 16
934#define BCM_ISCSI_ETH_CL_ID 17
935#endif
936
34f80b04
EG		 937 int pm_cap;
938 int pcie_cap;
8d5726c4 939 int mrrs;
34f80b04 940
1cf167f2 941 struct delayed_work sp_task;
72fd0718 942 struct delayed_work reset_task;
34f80b04 943 struct timer_list timer;
34f80b04
EG		 944 int current_interval;
945
946 u16 fw_seq;
947 u16 fw_drv_pulse_wr_seq;
948 u32 func_stx;
949
950 struct link_params link_params;
951 struct link_vars link_vars;
01cd4528 952 struct mdio_if_info mdio;
a2fbb9ea 953
34f80b04
EG		 954 struct bnx2x_common common;
955 struct bnx2x_port port;
956
8a1c38d1
EG		 957 struct cmng_struct_per_port cmng;
958 u32 vn_weight_sum;
959
34f80b04
EG		 960 u32 mf_config;
961 u16 e1hov;
962 u8 e1hmf;
3196a88a 963#define IS_E1HMF(bp) (bp->e1hmf != 0)
a2fbb9ea 964
f1410647
ET		 965 u8 wol;
966
34f80b04 967 int rx_ring_size;
a2fbb9ea 968
34f80b04
EG		 969 u16 tx_quick_cons_trip_int;
970 u16 tx_quick_cons_trip;
971 u16 tx_ticks_int;
972 u16 tx_ticks;
a2fbb9ea 973
34f80b04
EG		 974 u16 rx_quick_cons_trip_int;
975 u16 rx_quick_cons_trip;
976 u16 rx_ticks_int;
977 u16 rx_ticks;
a2fbb9ea 978
34f80b04 979 u32 lin_cnt;
a2fbb9ea 980
34f80b04 981 int state;
356e2385 982#define BNX2X_STATE_CLOSED 0
34f80b04
EG		 983#define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000
984#define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000
a2fbb9ea 985#define BNX2X_STATE_OPEN 0x3000
34f80b04 986#define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000
a2fbb9ea
ET		 987#define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000
988#define BNX2X_STATE_CLOSING_WAIT4_UNLOAD 0x6000
34f80b04
EG		 989#define BNX2X_STATE_DIAG 0xe000
990#define BNX2X_STATE_ERROR 0xf000
a2fbb9ea 991
555f6c78 992 int multi_mode;
54b9ddaa 993 int num_queues;
a2fbb9ea 994
34f80b04
EG		 995 u32 rx_mode;
996#define BNX2X_RX_MODE_NONE 0
997#define BNX2X_RX_MODE_NORMAL 1
998#define BNX2X_RX_MODE_ALLMULTI 2
999#define BNX2X_RX_MODE_PROMISC 3
1000#define BNX2X_MAX_MULTICAST 64
1001#define BNX2X_MAX_EMUL_MULTI 16
a2fbb9ea 1002
37b091ba
MC		 1003 u32 rx_mode_cl_mask;
1004
34f80b04 1005 dma_addr_t def_status_blk_mapping;
a2fbb9ea 1006
34f80b04
EG		 1007 struct bnx2x_slowpath *slowpath;
1008 dma_addr_t slowpath_mapping;
a2fbb9ea 1009
a18f5128
EG		 1010 int dropless_fc;
1011
37b091ba
MC		 1012#ifdef BCM_CNIC
1013 u32 cnic_flags;
1014#define BNX2X_CNIC_FLAG_MAC_SET 1
1015
1016 void *t1;
1017 dma_addr_t t1_mapping;
1018 void *t2;
1019 dma_addr_t t2_mapping;
1020 void *timers;
1021 dma_addr_t timers_mapping;
1022 void *qm;
1023 dma_addr_t qm_mapping;
1024 struct cnic_ops *cnic_ops;
1025 void *cnic_data;
1026 u32 cnic_tag;
1027 struct cnic_eth_dev cnic_eth_dev;
1028 struct host_status_block *cnic_sb;
1029 dma_addr_t cnic_sb_mapping;
1030#define CNIC_SB_ID(bp) BP_L_ID(bp)
1031 struct eth_spe *cnic_kwq;
1032 struct eth_spe *cnic_kwq_prod;
1033 struct eth_spe *cnic_kwq_cons;
1034 struct eth_spe *cnic_kwq_last;
1035 u16 cnic_kwq_pending;
1036 u16 cnic_spq_pending;
1037 struct mutex cnic_mutex;
1038 u8 iscsi_mac[6];
1039#endif
1040
ad8d3948
EG		 1041 int dmae_ready;
1042 /* used to synchronize dmae accesses */
1043 struct mutex dmae_mutex;
ad8d3948 1044
c4ff7cbf
EG		 1045 /* used to protect the FW mail box */
1046 struct mutex fw_mb_mutex;
1047
bb2a0f7a
YG		 1048 /* used to synchronize stats collecting */
1049 int stats_state;
1050 /* used by dmae command loader */
1051 struct dmae_command stats_dmae;
1052 int executer_idx;
ad8d3948 1053
bb2a0f7a 1054 u16 stats_counter;
bb2a0f7a
YG		 1055 struct bnx2x_eth_stats eth_stats;
1056
1057 struct z_stream_s *strm;
1058 void *gunzip_buf;
1059 dma_addr_t gunzip_mapping;
1060 int gunzip_outlen;
ad8d3948 1061#define FW_BUF_SIZE 0x8000
573f2035
EG		 1062#define GUNZIP_BUF(bp) (bp->gunzip_buf)
1063#define GUNZIP_PHYS(bp) (bp->gunzip_mapping)
1064#define GUNZIP_OUTLEN(bp) (bp->gunzip_outlen)
a2fbb9ea 1065
ab6ad5a4 1066 struct raw_op *init_ops;
94a78b79 1067 /* Init blocks offsets inside init_ops */
ab6ad5a4 1068 u16 *init_ops_offsets;
94a78b79 1069 /* Data blob - has 32 bit granularity */
ab6ad5a4 1070 u32 *init_data;
94a78b79 1071 /* Zipped PRAM blobs - raw data */
ab6ad5a4
EG		 1072 const u8 *tsem_int_table_data;
1073 const u8 *tsem_pram_data;
1074 const u8 *usem_int_table_data;
1075 const u8 *usem_pram_data;
1076 const u8 *xsem_int_table_data;
1077 const u8 *xsem_pram_data;
1078 const u8 *csem_int_table_data;
1079 const u8 *csem_pram_data;
573f2035
EG		 1080#define INIT_OPS(bp) (bp->init_ops)
1081#define INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets)
1082#define INIT_DATA(bp) (bp->init_data)
1083#define INIT_TSEM_INT_TABLE_DATA(bp) (bp->tsem_int_table_data)
1084#define INIT_TSEM_PRAM_DATA(bp) (bp->tsem_pram_data)
1085#define INIT_USEM_INT_TABLE_DATA(bp) (bp->usem_int_table_data)
1086#define INIT_USEM_PRAM_DATA(bp) (bp->usem_pram_data)
1087#define INIT_XSEM_INT_TABLE_DATA(bp) (bp->xsem_int_table_data)
1088#define INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data)
1089#define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data)
1090#define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data)
1091
34f24c7f 1092 char fw_ver[32];
ab6ad5a4 1093 const struct firmware *firmware;
a2fbb9ea
ET		 1094};
1095
1096
54b9ddaa
VZ		 1097#define BNX2X_MAX_QUEUES(bp) (IS_E1HMF(bp) ? (MAX_CONTEXT/E1HVN_MAX) \
1098 : MAX_CONTEXT)
1099#define BNX2X_NUM_QUEUES(bp) (bp->num_queues)
1100#define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1)
3196a88a 1101
555f6c78
EG		 1102#define for_each_queue(bp, var) \
1103 for (var = 0; var < BNX2X_NUM_QUEUES(bp); var++)
3196a88a 1104#define for_each_nondefault_queue(bp, var) \
54b9ddaa 1105 for (var = 1; var < BNX2X_NUM_QUEUES(bp); var++)
3196a88a
EG		 1106
1107
c18487ee
YR		 1108void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
1109void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
1110 u32 len32);
4acac6a5 1111int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port);
17de50b7 1112int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
4acac6a5 1113int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
4d295db0 1114u32 bnx2x_fw_command(struct bnx2x *bp, u32 command);
573f2035
EG		 1115void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val);
1116void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
1117 u32 addr, u32 len);
c18487ee 1118
34f80b04
EG		 1119static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
1120 int wait)
1121{
1122 u32 val;
1123
1124 do {
1125 val = REG_RD(bp, reg);
1126 if (val == expected)
1127 break;
1128 ms -= wait;
1129 msleep(wait);
1130
1131 } while (ms > 0);
1132
1133 return val;
1134}
1135
1136
1137/* load/unload mode */
1138#define LOAD_NORMAL 0
1139#define LOAD_OPEN 1
1140#define LOAD_DIAG 2
1141#define UNLOAD_NORMAL 0
1142#define UNLOAD_CLOSE 1
72fd0718 1143#define UNLOAD_RECOVERY 2
34f80b04 1144
bb2a0f7a 1145
ad8d3948
EG		 1146/* DMAE command defines */
1147#define DMAE_CMD_SRC_PCI 0
1148#define DMAE_CMD_SRC_GRC DMAE_COMMAND_SRC
1149
1150#define DMAE_CMD_DST_PCI (1 << DMAE_COMMAND_DST_SHIFT)
1151#define DMAE_CMD_DST_GRC (2 << DMAE_COMMAND_DST_SHIFT)
1152
1153#define DMAE_CMD_C_DST_PCI 0
1154#define DMAE_CMD_C_DST_GRC (1 << DMAE_COMMAND_C_DST_SHIFT)
1155
1156#define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE
1157
1158#define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
1159#define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
1160#define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
1161#define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
1162
1163#define DMAE_CMD_PORT_0 0
1164#define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT
1165
1166#define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET
1167#define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET
1168#define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT
1169
1170#define DMAE_LEN32_RD_MAX 0x80
1171#define DMAE_LEN32_WR_MAX 0x400
1172
1173#define DMAE_COMP_VAL 0xe0d0d0ae
1174
1175#define MAX_DMAE_C_PER_PORT 8
ab6ad5a4 1176#define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
ad8d3948 1177 BP_E1HVN(bp))
ab6ad5a4 1178#define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
ad8d3948
EG		 1179 E1HVN_MAX)
1180
1181
25047950
ET		 1182/* PCIE link and speed */
1183#define PCICFG_LINK_WIDTH 0x1f00000
1184#define PCICFG_LINK_WIDTH_SHIFT 20
1185#define PCICFG_LINK_SPEED 0xf0000
1186#define PCICFG_LINK_SPEED_SHIFT 16
a2fbb9ea 1187
bb2a0f7a 1188
d3d4f495 1189#define BNX2X_NUM_TESTS 7
bb2a0f7a 1190
b5bf9068
EG		 1191#define BNX2X_PHY_LOOPBACK 0
1192#define BNX2X_MAC_LOOPBACK 1
1193#define BNX2X_PHY_LOOPBACK_FAILED 1
1194#define BNX2X_MAC_LOOPBACK_FAILED 2
bb2a0f7a
YG		 1195#define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \
1196 BNX2X_PHY_LOOPBACK_FAILED)
96fc1784 1197
7a9b2557
VZ		 1198
1199#define STROM_ASSERT_ARRAY_SIZE 50
1200
96fc1784 1201
34f80b04 1202/* must be used on a CID before placing it on a HW ring */
ab6ad5a4
EG		 1203#define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \
1204 (BP_E1HVN(bp) << 17) | (x))
7a9b2557
VZ		 1205
1206#define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe))
1207#define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
1208
1209
7d323bfd 1210#define BNX2X_BTR 1
7a9b2557 1211#define MAX_SPQ_PENDING 8
a2fbb9ea 1212
a2fbb9ea 1213
34f80b04
EG		 1214/* CMNG constants
1215 derived from lab experiments, and not from system spec calculations !!! */
1216#define DEF_MIN_RATE 100
1217/* resolution of the rate shaping timer - 100 usec */
1218#define RS_PERIODIC_TIMEOUT_USEC 100
1219/* resolution of fairness algorithm in usecs -
33471629 1220 coefficient for calculating the actual t fair */
34f80b04
EG		 1221#define T_FAIR_COEF 10000000
1222/* number of bytes in single QM arbitration cycle -
33471629 1223 coefficient for calculating the fairness timer */
34f80b04
EG		 1224#define QM_ARB_BYTES 40000
1225#define FAIR_MEM 2
1226
1227
1228#define ATTN_NIG_FOR_FUNC (1L << 8)
1229#define ATTN_SW_TIMER_4_FUNC (1L << 9)
1230#define GPIO_2_FUNC (1L << 10)
1231#define GPIO_3_FUNC (1L << 11)
1232#define GPIO_4_FUNC (1L << 12)
1233#define ATTN_GENERAL_ATTN_1 (1L << 13)
1234#define ATTN_GENERAL_ATTN_2 (1L << 14)
1235#define ATTN_GENERAL_ATTN_3 (1L << 15)
1236#define ATTN_GENERAL_ATTN_4 (1L << 13)
1237#define ATTN_GENERAL_ATTN_5 (1L << 14)
1238#define ATTN_GENERAL_ATTN_6 (1L << 15)
1239
1240#define ATTN_HARD_WIRED_MASK 0xff00
1241#define ATTENTION_ID 4
a2fbb9ea
ET		 1242
1243
34f80b04
EG		 1244/* stuff added to make the code fit 80Col */
1245
1246#define BNX2X_PMF_LINK_ASSERT \
1247 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp))
1248
a2fbb9ea
ET		 1249#define BNX2X_MC_ASSERT_BITS \
1250 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1251 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1252 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1253 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
1254
1255#define BNX2X_MCP_ASSERT \
1256 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
1257
34f80b04
EG		 1258#define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
1259#define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
1260 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
1261 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \
1262 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
1263 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
1264 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
1265
a2fbb9ea
ET		 1266#define HW_INTERRUT_ASSERT_SET_0 \
1267 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
1268 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
1269 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \
1270 AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT)
34f80b04 1271#define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
a2fbb9ea
ET		 1272 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
1273 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
1274 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
1275 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR)
1276#define HW_INTERRUT_ASSERT_SET_1 \
1277 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \
1278 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \
1279 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \
1280 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \
1281 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \
1282 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \
1283 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \
1284 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \
1285 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
1286 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
1287 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
34f80b04 1288#define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR |\
a2fbb9ea
ET		 1289 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
1290 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
1291 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
ab6ad5a4
EG		 1292 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
1293 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
a2fbb9ea
ET		 1294 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \
1295 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \
1296 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \
1297 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \
1298 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR)
1299#define HW_INTERRUT_ASSERT_SET_2 \
1300 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \
1301 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \
1302 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \
1303 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
1304 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
34f80b04 1305#define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \
a2fbb9ea
ET		 1306 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \
1307 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
1308 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
1309 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \
1310 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \
1311 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
1312
72fd0718
VZ		 1313#define HW_PRTY_ASSERT_SET_3 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
1314 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
1315 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \
1316 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
a2fbb9ea 1317
555f6c78 1318#define MULTI_FLAGS(bp) \
34f80b04
EG		 1319 (TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY | \
1320 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | \
1321 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY | \
1322 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | \
555f6c78
EG		 1323 (bp->multi_mode << \
1324 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT))
34f80b04 1325#define MULTI_MASK 0x7f
a2fbb9ea
ET		 1326
1327
34f80b04
EG		 1328#define DEF_USB_FUNC_OFF (2 + 2*HC_USTORM_DEF_SB_NUM_INDICES)
1329#define DEF_CSB_FUNC_OFF (2 + 2*HC_CSTORM_DEF_SB_NUM_INDICES)
1330#define DEF_XSB_FUNC_OFF (2 + 2*HC_XSTORM_DEF_SB_NUM_INDICES)
1331#define DEF_TSB_FUNC_OFF (2 + 2*HC_TSTORM_DEF_SB_NUM_INDICES)
a2fbb9ea 1332
34f80b04 1333#define C_DEF_SB_SP_INDEX HC_INDEX_DEF_C_ETH_SLOW_PATH
a2fbb9ea
ET		 1334
1335#define BNX2X_SP_DSB_INDEX \
34f80b04 1336(&bp->def_status_blk->c_def_status_block.index_values[C_DEF_SB_SP_INDEX])
a2fbb9ea
ET		 1337
1338
1339#define CAM_IS_INVALID(x) \
1340(x.target_table_entry.flags == TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE)
1341
1342#define CAM_INVALIDATE(x) \
34f80b04
EG		 1343 (x.target_table_entry.flags = TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE)
1344
1345
1346/* Number of u32 elements in MC hash array */
1347#define MC_HASH_SIZE 8
1348#define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \
1349 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4)
a2fbb9ea
ET		 1350
1351
34f80b04
EG		 1352#ifndef PXP2_REG_PXP2_INT_STS
1353#define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0
1354#endif
1355
34f24c7f
VZ		 1356#define BNX2X_VPD_LEN 128
1357#define VENDOR_ID_LEN 4
1358
a2fbb9ea
ET		 1359/* MISC_REG_RESET_REG - this is here for the hsi to work don't touch */
1360
1361#endif /* bnx2x.h */
kernel source for telekom puls (alcatel/mediatek)