Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * processor_idle - idle state submodule to the ACPI processor driver | |
3 | * | |
4 | * Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com> | |
5 | * Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com> | |
c5ab81ca | 6 | * Copyright (C) 2004, 2005 Dominik Brodowski <linux@brodo.de> |
1da177e4 LT |
7 | * Copyright (C) 2004 Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> |
8 | * - Added processor hotplug support | |
02df8b93 VP |
9 | * Copyright (C) 2005 Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> |
10 | * - Added support for C3 on SMP | |
1da177e4 LT |
11 | * |
12 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or modify | |
15 | * it under the terms of the GNU General Public License as published by | |
16 | * the Free Software Foundation; either version 2 of the License, or (at | |
17 | * your option) any later version. | |
18 | * | |
19 | * This program is distributed in the hope that it will be useful, but | |
20 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
22 | * General Public License for more details. | |
23 | * | |
24 | * You should have received a copy of the GNU General Public License along | |
25 | * with this program; if not, write to the Free Software Foundation, Inc., | |
26 | * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. | |
27 | * | |
28 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
29 | */ | |
30 | ||
31 | #include <linux/kernel.h> | |
32 | #include <linux/module.h> | |
33 | #include <linux/init.h> | |
34 | #include <linux/cpufreq.h> | |
35 | #include <linux/proc_fs.h> | |
36 | #include <linux/seq_file.h> | |
37 | #include <linux/acpi.h> | |
38 | #include <linux/dmi.h> | |
39 | #include <linux/moduleparam.h> | |
4e57b681 | 40 | #include <linux/sched.h> /* need_resched() */ |
f011e2e2 | 41 | #include <linux/pm_qos_params.h> |
e9e2cdb4 | 42 | #include <linux/clockchips.h> |
4f86d3a8 | 43 | #include <linux/cpuidle.h> |
ba84be23 | 44 | #include <linux/irqflags.h> |
1da177e4 | 45 | |
3434933b TG |
46 | /* |
47 | * Include the apic definitions for x86 to have the APIC timer related defines | |
48 | * available also for UP (on SMP it gets magically included via linux/smp.h). | |
49 | * asm/acpi.h is not an option, as it would require more include magic. Also | |
50 | * creating an empty asm-ia64/apic.h would just trade pest vs. cholera. | |
51 | */ | |
52 | #ifdef CONFIG_X86 | |
53 | #include <asm/apic.h> | |
54 | #endif | |
55 | ||
1da177e4 LT |
56 | #include <asm/io.h> |
57 | #include <asm/uaccess.h> | |
58 | ||
59 | #include <acpi/acpi_bus.h> | |
60 | #include <acpi/processor.h> | |
c1e3b377 | 61 | #include <asm/processor.h> |
1da177e4 | 62 | |
a192a958 LB |
63 | #define PREFIX "ACPI: " |
64 | ||
1da177e4 | 65 | #define ACPI_PROCESSOR_CLASS "processor" |
1da177e4 | 66 | #define _COMPONENT ACPI_PROCESSOR_COMPONENT |
f52fd66d | 67 | ACPI_MODULE_NAME("processor_idle"); |
1da177e4 | 68 | #define ACPI_PROCESSOR_FILE_POWER "power" |
2aa44d05 | 69 | #define PM_TIMER_TICK_NS (1000000000ULL/PM_TIMER_FREQUENCY) |
4f86d3a8 LB |
70 | #define C2_OVERHEAD 1 /* 1us */ |
71 | #define C3_OVERHEAD 1 /* 1us */ | |
4f86d3a8 | 72 | #define PM_TIMER_TICKS_TO_US(p) (((p) * 1000)/(PM_TIMER_FREQUENCY/1000)) |
1da177e4 | 73 | |
4f86d3a8 LB |
74 | static unsigned int max_cstate __read_mostly = ACPI_PROCESSOR_MAX_POWER; |
75 | module_param(max_cstate, uint, 0000); | |
b6835052 | 76 | static unsigned int nocst __read_mostly; |
1da177e4 LT |
77 | module_param(nocst, uint, 0000); |
78 | ||
25de5718 | 79 | static unsigned int latency_factor __read_mostly = 2; |
4963f620 | 80 | module_param(latency_factor, uint, 0644); |
1da177e4 | 81 | |
ff69f2bb | 82 | static s64 us_to_pm_timer_ticks(s64 t) |
83 | { | |
84 | return div64_u64(t * PM_TIMER_FREQUENCY, 1000000); | |
85 | } | |
1da177e4 LT |
86 | /* |
87 | * IBM ThinkPad R40e crashes mysteriously when going into C2 or C3. | |
88 | * For now disable this. Probably a bug somewhere else. | |
89 | * | |
90 | * To skip this limit, boot/load with a large max_cstate limit. | |
91 | */ | |
1855256c | 92 | static int set_max_cstate(const struct dmi_system_id *id) |
1da177e4 LT |
93 | { |
94 | if (max_cstate > ACPI_PROCESSOR_MAX_POWER) | |
95 | return 0; | |
96 | ||
3d35600a | 97 | printk(KERN_NOTICE PREFIX "%s detected - limiting to C%ld max_cstate." |
4be44fcd LB |
98 | " Override with \"processor.max_cstate=%d\"\n", id->ident, |
99 | (long)id->driver_data, ACPI_PROCESSOR_MAX_POWER + 1); | |
1da177e4 | 100 | |
3d35600a | 101 | max_cstate = (long)id->driver_data; |
1da177e4 LT |
102 | |
103 | return 0; | |
104 | } | |
105 | ||
7ded5689 AR |
106 | /* Actually this shouldn't be __cpuinitdata, would be better to fix the |
107 | callers to only run once -AK */ | |
108 | static struct dmi_system_id __cpuinitdata processor_power_dmi_table[] = { | |
876c184b TR |
109 | { set_max_cstate, "Clevo 5600D", { |
110 | DMI_MATCH(DMI_BIOS_VENDOR,"Phoenix Technologies LTD"), | |
111 | DMI_MATCH(DMI_BIOS_VERSION,"SHE845M0.86C.0013.D.0302131307")}, | |
4be44fcd | 112 | (void *)2}, |
1da177e4 LT |
113 | {}, |
114 | }; | |
115 | ||
4f86d3a8 | 116 | |
2e906655 | 117 | /* |
118 | * Callers should disable interrupts before the call and enable | |
119 | * interrupts after return. | |
120 | */ | |
ddc081a1 VP |
121 | static void acpi_safe_halt(void) |
122 | { | |
123 | current_thread_info()->status &= ~TS_POLLING; | |
124 | /* | |
125 | * TS_POLLING-cleared state must be visible before we | |
126 | * test NEED_RESCHED: | |
127 | */ | |
128 | smp_mb(); | |
71e93d15 | 129 | if (!need_resched()) { |
ddc081a1 | 130 | safe_halt(); |
71e93d15 VP |
131 | local_irq_disable(); |
132 | } | |
ddc081a1 VP |
133 | current_thread_info()->status |= TS_POLLING; |
134 | } | |
135 | ||
169a0abb TG |
136 | #ifdef ARCH_APICTIMER_STOPS_ON_C3 |
137 | ||
138 | /* | |
139 | * Some BIOS implementations switch to C3 in the published C2 state. | |
296d93cd LT |
140 | * This seems to be a common problem on AMD boxen, but other vendors |
141 | * are affected too. We pick the most conservative approach: we assume | |
142 | * that the local APIC stops in both C2 and C3. | |
169a0abb | 143 | */ |
7e275cc4 | 144 | static void lapic_timer_check_state(int state, struct acpi_processor *pr, |
169a0abb TG |
145 | struct acpi_processor_cx *cx) |
146 | { | |
147 | struct acpi_processor_power *pwr = &pr->power; | |
e585bef8 | 148 | u8 type = local_apic_timer_c2_ok ? ACPI_STATE_C3 : ACPI_STATE_C2; |
169a0abb | 149 | |
db954b58 VP |
150 | if (cpu_has(&cpu_data(pr->id), X86_FEATURE_ARAT)) |
151 | return; | |
152 | ||
87ad57ba SL |
153 | if (boot_cpu_has(X86_FEATURE_AMDC1E)) |
154 | type = ACPI_STATE_C1; | |
155 | ||
169a0abb TG |
156 | /* |
157 | * Check, if one of the previous states already marked the lapic | |
158 | * unstable | |
159 | */ | |
160 | if (pwr->timer_broadcast_on_state < state) | |
161 | return; | |
162 | ||
e585bef8 | 163 | if (cx->type >= type) |
296d93cd | 164 | pr->power.timer_broadcast_on_state = state; |
169a0abb TG |
165 | } |
166 | ||
918aae42 | 167 | static void __lapic_timer_propagate_broadcast(void *arg) |
169a0abb | 168 | { |
f833bab8 | 169 | struct acpi_processor *pr = (struct acpi_processor *) arg; |
e9e2cdb4 TG |
170 | unsigned long reason; |
171 | ||
172 | reason = pr->power.timer_broadcast_on_state < INT_MAX ? | |
173 | CLOCK_EVT_NOTIFY_BROADCAST_ON : CLOCK_EVT_NOTIFY_BROADCAST_OFF; | |
174 | ||
175 | clockevents_notify(reason, &pr->id); | |
e9e2cdb4 TG |
176 | } |
177 | ||
918aae42 HS |
178 | static void lapic_timer_propagate_broadcast(struct acpi_processor *pr) |
179 | { | |
180 | smp_call_function_single(pr->id, __lapic_timer_propagate_broadcast, | |
181 | (void *)pr, 1); | |
182 | } | |
183 | ||
e9e2cdb4 | 184 | /* Power(C) State timer broadcast control */ |
7e275cc4 | 185 | static void lapic_timer_state_broadcast(struct acpi_processor *pr, |
e9e2cdb4 TG |
186 | struct acpi_processor_cx *cx, |
187 | int broadcast) | |
188 | { | |
e9e2cdb4 TG |
189 | int state = cx - pr->power.states; |
190 | ||
191 | if (state >= pr->power.timer_broadcast_on_state) { | |
192 | unsigned long reason; | |
193 | ||
194 | reason = broadcast ? CLOCK_EVT_NOTIFY_BROADCAST_ENTER : | |
195 | CLOCK_EVT_NOTIFY_BROADCAST_EXIT; | |
196 | clockevents_notify(reason, &pr->id); | |
197 | } | |
169a0abb TG |
198 | } |
199 | ||
200 | #else | |
201 | ||
7e275cc4 | 202 | static void lapic_timer_check_state(int state, struct acpi_processor *pr, |
169a0abb | 203 | struct acpi_processor_cx *cstate) { } |
7e275cc4 LB |
204 | static void lapic_timer_propagate_broadcast(struct acpi_processor *pr) { } |
205 | static void lapic_timer_state_broadcast(struct acpi_processor *pr, | |
e9e2cdb4 TG |
206 | struct acpi_processor_cx *cx, |
207 | int broadcast) | |
208 | { | |
209 | } | |
169a0abb TG |
210 | |
211 | #endif | |
212 | ||
b04e7bdb TG |
213 | /* |
214 | * Suspend / resume control | |
215 | */ | |
216 | static int acpi_idle_suspend; | |
815ab0fd LB |
217 | static u32 saved_bm_rld; |
218 | ||
219 | static void acpi_idle_bm_rld_save(void) | |
220 | { | |
221 | acpi_read_bit_register(ACPI_BITREG_BUS_MASTER_RLD, &saved_bm_rld); | |
222 | } | |
223 | static void acpi_idle_bm_rld_restore(void) | |
224 | { | |
225 | u32 resumed_bm_rld; | |
226 | ||
227 | acpi_read_bit_register(ACPI_BITREG_BUS_MASTER_RLD, &resumed_bm_rld); | |
228 | ||
229 | if (resumed_bm_rld != saved_bm_rld) | |
230 | acpi_write_bit_register(ACPI_BITREG_BUS_MASTER_RLD, saved_bm_rld); | |
231 | } | |
b04e7bdb TG |
232 | |
233 | int acpi_processor_suspend(struct acpi_device * device, pm_message_t state) | |
234 | { | |
815ab0fd LB |
235 | if (acpi_idle_suspend == 1) |
236 | return 0; | |
237 | ||
238 | acpi_idle_bm_rld_save(); | |
b04e7bdb TG |
239 | acpi_idle_suspend = 1; |
240 | return 0; | |
241 | } | |
242 | ||
243 | int acpi_processor_resume(struct acpi_device * device) | |
244 | { | |
815ab0fd LB |
245 | if (acpi_idle_suspend == 0) |
246 | return 0; | |
247 | ||
248 | acpi_idle_bm_rld_restore(); | |
b04e7bdb TG |
249 | acpi_idle_suspend = 0; |
250 | return 0; | |
251 | } | |
252 | ||
61331168 | 253 | #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86) |
520daf72 | 254 | static void tsc_check_state(int state) |
ddb25f9a AK |
255 | { |
256 | switch (boot_cpu_data.x86_vendor) { | |
257 | case X86_VENDOR_AMD: | |
40fb1715 | 258 | case X86_VENDOR_INTEL: |
ddb25f9a AK |
259 | /* |
260 | * AMD Fam10h TSC will tick in all | |
261 | * C/P/S0/S1 states when this bit is set. | |
262 | */ | |
40fb1715 | 263 | if (boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) |
520daf72 | 264 | return; |
40fb1715 | 265 | |
ddb25f9a | 266 | /*FALL THROUGH*/ |
ddb25f9a | 267 | default: |
520daf72 LB |
268 | /* TSC could halt in idle, so notify users */ |
269 | if (state > ACPI_STATE_C1) | |
270 | mark_tsc_unstable("TSC halts in idle"); | |
ddb25f9a AK |
271 | } |
272 | } | |
520daf72 LB |
273 | #else |
274 | static void tsc_check_state(int state) { return; } | |
ddb25f9a AK |
275 | #endif |
276 | ||
4be44fcd | 277 | static int acpi_processor_get_power_info_fadt(struct acpi_processor *pr) |
1da177e4 | 278 | { |
1da177e4 LT |
279 | |
280 | if (!pr) | |
d550d98d | 281 | return -EINVAL; |
1da177e4 LT |
282 | |
283 | if (!pr->pblk) | |
d550d98d | 284 | return -ENODEV; |
1da177e4 | 285 | |
1da177e4 | 286 | /* if info is obtained from pblk/fadt, type equals state */ |
1da177e4 LT |
287 | pr->power.states[ACPI_STATE_C2].type = ACPI_STATE_C2; |
288 | pr->power.states[ACPI_STATE_C3].type = ACPI_STATE_C3; | |
289 | ||
4c033552 VP |
290 | #ifndef CONFIG_HOTPLUG_CPU |
291 | /* | |
292 | * Check for P_LVL2_UP flag before entering C2 and above on | |
4f86d3a8 | 293 | * an SMP system. |
4c033552 | 294 | */ |
ad71860a | 295 | if ((num_online_cpus() > 1) && |
cee324b1 | 296 | !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED)) |
d550d98d | 297 | return -ENODEV; |
4c033552 VP |
298 | #endif |
299 | ||
1da177e4 LT |
300 | /* determine C2 and C3 address from pblk */ |
301 | pr->power.states[ACPI_STATE_C2].address = pr->pblk + 4; | |
302 | pr->power.states[ACPI_STATE_C3].address = pr->pblk + 5; | |
303 | ||
304 | /* determine latencies from FADT */ | |
cee324b1 AS |
305 | pr->power.states[ACPI_STATE_C2].latency = acpi_gbl_FADT.C2latency; |
306 | pr->power.states[ACPI_STATE_C3].latency = acpi_gbl_FADT.C3latency; | |
1da177e4 | 307 | |
5d76b6f6 LB |
308 | /* |
309 | * FADT specified C2 latency must be less than or equal to | |
310 | * 100 microseconds. | |
311 | */ | |
312 | if (acpi_gbl_FADT.C2latency > ACPI_PROCESSOR_MAX_C2_LATENCY) { | |
313 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
314 | "C2 latency too large [%d]\n", acpi_gbl_FADT.C2latency)); | |
315 | /* invalidate C2 */ | |
316 | pr->power.states[ACPI_STATE_C2].address = 0; | |
317 | } | |
318 | ||
a6d72c18 LB |
319 | /* |
320 | * FADT supplied C3 latency must be less than or equal to | |
321 | * 1000 microseconds. | |
322 | */ | |
323 | if (acpi_gbl_FADT.C3latency > ACPI_PROCESSOR_MAX_C3_LATENCY) { | |
324 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
325 | "C3 latency too large [%d]\n", acpi_gbl_FADT.C3latency)); | |
326 | /* invalidate C3 */ | |
327 | pr->power.states[ACPI_STATE_C3].address = 0; | |
328 | } | |
329 | ||
1da177e4 LT |
330 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, |
331 | "lvl2[0x%08x] lvl3[0x%08x]\n", | |
332 | pr->power.states[ACPI_STATE_C2].address, | |
333 | pr->power.states[ACPI_STATE_C3].address)); | |
334 | ||
d550d98d | 335 | return 0; |
1da177e4 LT |
336 | } |
337 | ||
991528d7 | 338 | static int acpi_processor_get_power_info_default(struct acpi_processor *pr) |
acf05f4b | 339 | { |
991528d7 VP |
340 | if (!pr->power.states[ACPI_STATE_C1].valid) { |
341 | /* set the first C-State to C1 */ | |
342 | /* all processors need to support C1 */ | |
343 | pr->power.states[ACPI_STATE_C1].type = ACPI_STATE_C1; | |
344 | pr->power.states[ACPI_STATE_C1].valid = 1; | |
0fda6b40 | 345 | pr->power.states[ACPI_STATE_C1].entry_method = ACPI_CSTATE_HALT; |
991528d7 VP |
346 | } |
347 | /* the C0 state only exists as a filler in our array */ | |
acf05f4b | 348 | pr->power.states[ACPI_STATE_C0].valid = 1; |
d550d98d | 349 | return 0; |
acf05f4b VP |
350 | } |
351 | ||
4be44fcd | 352 | static int acpi_processor_get_power_info_cst(struct acpi_processor *pr) |
1da177e4 | 353 | { |
4be44fcd LB |
354 | acpi_status status = 0; |
355 | acpi_integer count; | |
cf824788 | 356 | int current_count; |
4be44fcd LB |
357 | int i; |
358 | struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; | |
359 | union acpi_object *cst; | |
1da177e4 | 360 | |
1da177e4 | 361 | |
1da177e4 | 362 | if (nocst) |
d550d98d | 363 | return -ENODEV; |
1da177e4 | 364 | |
991528d7 | 365 | current_count = 0; |
1da177e4 LT |
366 | |
367 | status = acpi_evaluate_object(pr->handle, "_CST", NULL, &buffer); | |
368 | if (ACPI_FAILURE(status)) { | |
369 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, "No _CST, giving up\n")); | |
d550d98d | 370 | return -ENODEV; |
4be44fcd | 371 | } |
1da177e4 | 372 | |
50dd0969 | 373 | cst = buffer.pointer; |
1da177e4 LT |
374 | |
375 | /* There must be at least 2 elements */ | |
376 | if (!cst || (cst->type != ACPI_TYPE_PACKAGE) || cst->package.count < 2) { | |
6468463a | 377 | printk(KERN_ERR PREFIX "not enough elements in _CST\n"); |
1da177e4 LT |
378 | status = -EFAULT; |
379 | goto end; | |
380 | } | |
381 | ||
382 | count = cst->package.elements[0].integer.value; | |
383 | ||
384 | /* Validate number of power states. */ | |
385 | if (count < 1 || count != cst->package.count - 1) { | |
6468463a | 386 | printk(KERN_ERR PREFIX "count given by _CST is not valid\n"); |
1da177e4 LT |
387 | status = -EFAULT; |
388 | goto end; | |
389 | } | |
390 | ||
1da177e4 LT |
391 | /* Tell driver that at least _CST is supported. */ |
392 | pr->flags.has_cst = 1; | |
393 | ||
394 | for (i = 1; i <= count; i++) { | |
395 | union acpi_object *element; | |
396 | union acpi_object *obj; | |
397 | struct acpi_power_register *reg; | |
398 | struct acpi_processor_cx cx; | |
399 | ||
400 | memset(&cx, 0, sizeof(cx)); | |
401 | ||
50dd0969 | 402 | element = &(cst->package.elements[i]); |
1da177e4 LT |
403 | if (element->type != ACPI_TYPE_PACKAGE) |
404 | continue; | |
405 | ||
406 | if (element->package.count != 4) | |
407 | continue; | |
408 | ||
50dd0969 | 409 | obj = &(element->package.elements[0]); |
1da177e4 LT |
410 | |
411 | if (obj->type != ACPI_TYPE_BUFFER) | |
412 | continue; | |
413 | ||
4be44fcd | 414 | reg = (struct acpi_power_register *)obj->buffer.pointer; |
1da177e4 LT |
415 | |
416 | if (reg->space_id != ACPI_ADR_SPACE_SYSTEM_IO && | |
4be44fcd | 417 | (reg->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE)) |
1da177e4 LT |
418 | continue; |
419 | ||
1da177e4 | 420 | /* There should be an easy way to extract an integer... */ |
50dd0969 | 421 | obj = &(element->package.elements[1]); |
1da177e4 LT |
422 | if (obj->type != ACPI_TYPE_INTEGER) |
423 | continue; | |
424 | ||
425 | cx.type = obj->integer.value; | |
991528d7 VP |
426 | /* |
427 | * Some buggy BIOSes won't list C1 in _CST - | |
428 | * Let acpi_processor_get_power_info_default() handle them later | |
429 | */ | |
430 | if (i == 1 && cx.type != ACPI_STATE_C1) | |
431 | current_count++; | |
432 | ||
433 | cx.address = reg->address; | |
434 | cx.index = current_count + 1; | |
435 | ||
bc71bec9 | 436 | cx.entry_method = ACPI_CSTATE_SYSTEMIO; |
991528d7 VP |
437 | if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE) { |
438 | if (acpi_processor_ffh_cstate_probe | |
439 | (pr->id, &cx, reg) == 0) { | |
bc71bec9 | 440 | cx.entry_method = ACPI_CSTATE_FFH; |
441 | } else if (cx.type == ACPI_STATE_C1) { | |
991528d7 VP |
442 | /* |
443 | * C1 is a special case where FIXED_HARDWARE | |
444 | * can be handled in non-MWAIT way as well. | |
445 | * In that case, save this _CST entry info. | |
991528d7 VP |
446 | * Otherwise, ignore this info and continue. |
447 | */ | |
bc71bec9 | 448 | cx.entry_method = ACPI_CSTATE_HALT; |
4fcb2fcd | 449 | snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI HLT"); |
bc71bec9 | 450 | } else { |
991528d7 VP |
451 | continue; |
452 | } | |
da5e09a1 ZY |
453 | if (cx.type == ACPI_STATE_C1 && |
454 | (idle_halt || idle_nomwait)) { | |
c1e3b377 ZY |
455 | /* |
456 | * In most cases the C1 space_id obtained from | |
457 | * _CST object is FIXED_HARDWARE access mode. | |
458 | * But when the option of idle=halt is added, | |
459 | * the entry_method type should be changed from | |
460 | * CSTATE_FFH to CSTATE_HALT. | |
da5e09a1 ZY |
461 | * When the option of idle=nomwait is added, |
462 | * the C1 entry_method type should be | |
463 | * CSTATE_HALT. | |
c1e3b377 ZY |
464 | */ |
465 | cx.entry_method = ACPI_CSTATE_HALT; | |
466 | snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI HLT"); | |
467 | } | |
4fcb2fcd VP |
468 | } else { |
469 | snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI IOPORT 0x%x", | |
470 | cx.address); | |
991528d7 | 471 | } |
1da177e4 | 472 | |
0fda6b40 VP |
473 | if (cx.type == ACPI_STATE_C1) { |
474 | cx.valid = 1; | |
475 | } | |
4fcb2fcd | 476 | |
50dd0969 | 477 | obj = &(element->package.elements[2]); |
1da177e4 LT |
478 | if (obj->type != ACPI_TYPE_INTEGER) |
479 | continue; | |
480 | ||
481 | cx.latency = obj->integer.value; | |
482 | ||
50dd0969 | 483 | obj = &(element->package.elements[3]); |
1da177e4 LT |
484 | if (obj->type != ACPI_TYPE_INTEGER) |
485 | continue; | |
486 | ||
487 | cx.power = obj->integer.value; | |
488 | ||
cf824788 JM |
489 | current_count++; |
490 | memcpy(&(pr->power.states[current_count]), &cx, sizeof(cx)); | |
491 | ||
492 | /* | |
493 | * We support total ACPI_PROCESSOR_MAX_POWER - 1 | |
494 | * (From 1 through ACPI_PROCESSOR_MAX_POWER - 1) | |
495 | */ | |
496 | if (current_count >= (ACPI_PROCESSOR_MAX_POWER - 1)) { | |
497 | printk(KERN_WARNING | |
498 | "Limiting number of power states to max (%d)\n", | |
499 | ACPI_PROCESSOR_MAX_POWER); | |
500 | printk(KERN_WARNING | |
501 | "Please increase ACPI_PROCESSOR_MAX_POWER if needed.\n"); | |
502 | break; | |
503 | } | |
1da177e4 LT |
504 | } |
505 | ||
4be44fcd | 506 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Found %d power states\n", |
cf824788 | 507 | current_count)); |
1da177e4 LT |
508 | |
509 | /* Validate number of power states discovered */ | |
cf824788 | 510 | if (current_count < 2) |
6d93c648 | 511 | status = -EFAULT; |
1da177e4 | 512 | |
4be44fcd | 513 | end: |
02438d87 | 514 | kfree(buffer.pointer); |
1da177e4 | 515 | |
d550d98d | 516 | return status; |
1da177e4 LT |
517 | } |
518 | ||
1da177e4 LT |
519 | static void acpi_processor_power_verify_c2(struct acpi_processor_cx *cx) |
520 | { | |
1da177e4 LT |
521 | |
522 | if (!cx->address) | |
d550d98d | 523 | return; |
1da177e4 | 524 | |
1da177e4 LT |
525 | /* |
526 | * Otherwise we've met all of our C2 requirements. | |
527 | * Normalize the C2 latency to expidite policy | |
528 | */ | |
529 | cx->valid = 1; | |
4f86d3a8 | 530 | |
4f86d3a8 | 531 | cx->latency_ticks = cx->latency; |
1da177e4 | 532 | |
d550d98d | 533 | return; |
1da177e4 LT |
534 | } |
535 | ||
4be44fcd LB |
536 | static void acpi_processor_power_verify_c3(struct acpi_processor *pr, |
537 | struct acpi_processor_cx *cx) | |
1da177e4 | 538 | { |
ee1ca48f PV |
539 | static int bm_check_flag = -1; |
540 | static int bm_control_flag = -1; | |
02df8b93 | 541 | |
1da177e4 LT |
542 | |
543 | if (!cx->address) | |
d550d98d | 544 | return; |
1da177e4 | 545 | |
1da177e4 LT |
546 | /* |
547 | * PIIX4 Erratum #18: We don't support C3 when Type-F (fast) | |
548 | * DMA transfers are used by any ISA device to avoid livelock. | |
549 | * Note that we could disable Type-F DMA (as recommended by | |
550 | * the erratum), but this is known to disrupt certain ISA | |
551 | * devices thus we take the conservative approach. | |
552 | */ | |
553 | else if (errata.piix4.fdma) { | |
554 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
4be44fcd | 555 | "C3 not supported on PIIX4 with Type-F DMA\n")); |
d550d98d | 556 | return; |
1da177e4 LT |
557 | } |
558 | ||
02df8b93 | 559 | /* All the logic here assumes flags.bm_check is same across all CPUs */ |
ee1ca48f | 560 | if (bm_check_flag == -1) { |
02df8b93 VP |
561 | /* Determine whether bm_check is needed based on CPU */ |
562 | acpi_processor_power_init_bm_check(&(pr->flags), pr->id); | |
563 | bm_check_flag = pr->flags.bm_check; | |
ee1ca48f | 564 | bm_control_flag = pr->flags.bm_control; |
02df8b93 VP |
565 | } else { |
566 | pr->flags.bm_check = bm_check_flag; | |
ee1ca48f | 567 | pr->flags.bm_control = bm_control_flag; |
02df8b93 VP |
568 | } |
569 | ||
570 | if (pr->flags.bm_check) { | |
02df8b93 | 571 | if (!pr->flags.bm_control) { |
ed3110ef VP |
572 | if (pr->flags.has_cst != 1) { |
573 | /* bus mastering control is necessary */ | |
574 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
575 | "C3 support requires BM control\n")); | |
576 | return; | |
577 | } else { | |
578 | /* Here we enter C3 without bus mastering */ | |
579 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
580 | "C3 support without BM control\n")); | |
581 | } | |
02df8b93 VP |
582 | } |
583 | } else { | |
02df8b93 VP |
584 | /* |
585 | * WBINVD should be set in fadt, for C3 state to be | |
586 | * supported on when bm_check is not required. | |
587 | */ | |
cee324b1 | 588 | if (!(acpi_gbl_FADT.flags & ACPI_FADT_WBINVD)) { |
02df8b93 | 589 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, |
4be44fcd LB |
590 | "Cache invalidation should work properly" |
591 | " for C3 to be enabled on SMP systems\n")); | |
d550d98d | 592 | return; |
02df8b93 | 593 | } |
02df8b93 VP |
594 | } |
595 | ||
1da177e4 LT |
596 | /* |
597 | * Otherwise we've met all of our C3 requirements. | |
598 | * Normalize the C3 latency to expidite policy. Enable | |
599 | * checking of bus mastering status (bm_check) so we can | |
600 | * use this in our C3 policy | |
601 | */ | |
602 | cx->valid = 1; | |
4f86d3a8 | 603 | |
4f86d3a8 | 604 | cx->latency_ticks = cx->latency; |
31878dd8 LB |
605 | /* |
606 | * On older chipsets, BM_RLD needs to be set | |
607 | * in order for Bus Master activity to wake the | |
608 | * system from C3. Newer chipsets handle DMA | |
609 | * during C3 automatically and BM_RLD is a NOP. | |
610 | * In either case, the proper way to | |
611 | * handle BM_RLD is to set it and leave it set. | |
612 | */ | |
50ffba1b | 613 | acpi_write_bit_register(ACPI_BITREG_BUS_MASTER_RLD, 1); |
1da177e4 | 614 | |
d550d98d | 615 | return; |
1da177e4 LT |
616 | } |
617 | ||
1da177e4 LT |
618 | static int acpi_processor_power_verify(struct acpi_processor *pr) |
619 | { | |
620 | unsigned int i; | |
621 | unsigned int working = 0; | |
6eb0a0fd | 622 | |
169a0abb | 623 | pr->power.timer_broadcast_on_state = INT_MAX; |
6eb0a0fd | 624 | |
a0bf284b | 625 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER && i <= max_cstate; i++) { |
1da177e4 LT |
626 | struct acpi_processor_cx *cx = &pr->power.states[i]; |
627 | ||
628 | switch (cx->type) { | |
629 | case ACPI_STATE_C1: | |
630 | cx->valid = 1; | |
631 | break; | |
632 | ||
633 | case ACPI_STATE_C2: | |
634 | acpi_processor_power_verify_c2(cx); | |
635 | break; | |
636 | ||
637 | case ACPI_STATE_C3: | |
638 | acpi_processor_power_verify_c3(pr, cx); | |
639 | break; | |
640 | } | |
7e275cc4 LB |
641 | if (!cx->valid) |
642 | continue; | |
1da177e4 | 643 | |
7e275cc4 LB |
644 | lapic_timer_check_state(i, pr, cx); |
645 | tsc_check_state(cx->type); | |
646 | working++; | |
1da177e4 | 647 | } |
bd663347 | 648 | |
918aae42 | 649 | lapic_timer_propagate_broadcast(pr); |
1da177e4 LT |
650 | |
651 | return (working); | |
652 | } | |
653 | ||
4be44fcd | 654 | static int acpi_processor_get_power_info(struct acpi_processor *pr) |
1da177e4 LT |
655 | { |
656 | unsigned int i; | |
657 | int result; | |
658 | ||
1da177e4 LT |
659 | |
660 | /* NOTE: the idle thread may not be running while calling | |
661 | * this function */ | |
662 | ||
991528d7 VP |
663 | /* Zero initialize all the C-states info. */ |
664 | memset(pr->power.states, 0, sizeof(pr->power.states)); | |
665 | ||
1da177e4 | 666 | result = acpi_processor_get_power_info_cst(pr); |
6d93c648 | 667 | if (result == -ENODEV) |
c5a114f1 | 668 | result = acpi_processor_get_power_info_fadt(pr); |
6d93c648 | 669 | |
991528d7 VP |
670 | if (result) |
671 | return result; | |
672 | ||
673 | acpi_processor_get_power_info_default(pr); | |
674 | ||
cf824788 | 675 | pr->power.count = acpi_processor_power_verify(pr); |
1da177e4 | 676 | |
1da177e4 LT |
677 | /* |
678 | * if one state of type C2 or C3 is available, mark this | |
679 | * CPU as being "idle manageable" | |
680 | */ | |
681 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) { | |
acf05f4b | 682 | if (pr->power.states[i].valid) { |
1da177e4 | 683 | pr->power.count = i; |
2203d6ed LT |
684 | if (pr->power.states[i].type >= ACPI_STATE_C2) |
685 | pr->flags.power = 1; | |
acf05f4b | 686 | } |
1da177e4 LT |
687 | } |
688 | ||
d550d98d | 689 | return 0; |
1da177e4 LT |
690 | } |
691 | ||
74cad4ee | 692 | #ifdef CONFIG_ACPI_PROCFS |
1da177e4 LT |
693 | static int acpi_processor_power_seq_show(struct seq_file *seq, void *offset) |
694 | { | |
50dd0969 | 695 | struct acpi_processor *pr = seq->private; |
4be44fcd | 696 | unsigned int i; |
1da177e4 | 697 | |
1da177e4 LT |
698 | |
699 | if (!pr) | |
700 | goto end; | |
701 | ||
702 | seq_printf(seq, "active state: C%zd\n" | |
4be44fcd | 703 | "max_cstate: C%d\n" |
5c87579e | 704 | "maximum allowed latency: %d usec\n", |
4be44fcd | 705 | pr->power.state ? pr->power.state - pr->power.states : 0, |
92614610 | 706 | max_cstate, pm_qos_requirement(PM_QOS_CPU_DMA_LATENCY)); |
1da177e4 LT |
707 | |
708 | seq_puts(seq, "states:\n"); | |
709 | ||
710 | for (i = 1; i <= pr->power.count; i++) { | |
711 | seq_printf(seq, " %cC%d: ", | |
4be44fcd LB |
712 | (&pr->power.states[i] == |
713 | pr->power.state ? '*' : ' '), i); | |
1da177e4 LT |
714 | |
715 | if (!pr->power.states[i].valid) { | |
716 | seq_puts(seq, "<not supported>\n"); | |
717 | continue; | |
718 | } | |
719 | ||
720 | switch (pr->power.states[i].type) { | |
721 | case ACPI_STATE_C1: | |
722 | seq_printf(seq, "type[C1] "); | |
723 | break; | |
724 | case ACPI_STATE_C2: | |
725 | seq_printf(seq, "type[C2] "); | |
726 | break; | |
727 | case ACPI_STATE_C3: | |
728 | seq_printf(seq, "type[C3] "); | |
729 | break; | |
730 | default: | |
731 | seq_printf(seq, "type[--] "); | |
732 | break; | |
733 | } | |
734 | ||
735 | if (pr->power.states[i].promotion.state) | |
736 | seq_printf(seq, "promotion[C%zd] ", | |
4be44fcd LB |
737 | (pr->power.states[i].promotion.state - |
738 | pr->power.states)); | |
1da177e4 LT |
739 | else |
740 | seq_puts(seq, "promotion[--] "); | |
741 | ||
742 | if (pr->power.states[i].demotion.state) | |
743 | seq_printf(seq, "demotion[C%zd] ", | |
4be44fcd LB |
744 | (pr->power.states[i].demotion.state - |
745 | pr->power.states)); | |
1da177e4 LT |
746 | else |
747 | seq_puts(seq, "demotion[--] "); | |
748 | ||
a3c6598f | 749 | seq_printf(seq, "latency[%03d] usage[%08d] duration[%020llu]\n", |
4be44fcd | 750 | pr->power.states[i].latency, |
a3c6598f | 751 | pr->power.states[i].usage, |
b0b7eaaf | 752 | (unsigned long long)pr->power.states[i].time); |
1da177e4 LT |
753 | } |
754 | ||
4be44fcd | 755 | end: |
d550d98d | 756 | return 0; |
1da177e4 LT |
757 | } |
758 | ||
759 | static int acpi_processor_power_open_fs(struct inode *inode, struct file *file) | |
760 | { | |
761 | return single_open(file, acpi_processor_power_seq_show, | |
4be44fcd | 762 | PDE(inode)->data); |
1da177e4 LT |
763 | } |
764 | ||
d7508032 | 765 | static const struct file_operations acpi_processor_power_fops = { |
cf7acfab | 766 | .owner = THIS_MODULE, |
4be44fcd LB |
767 | .open = acpi_processor_power_open_fs, |
768 | .read = seq_read, | |
769 | .llseek = seq_lseek, | |
770 | .release = single_release, | |
1da177e4 | 771 | }; |
74cad4ee | 772 | #endif |
4f86d3a8 LB |
773 | |
774 | /** | |
775 | * acpi_idle_bm_check - checks if bus master activity was detected | |
776 | */ | |
777 | static int acpi_idle_bm_check(void) | |
778 | { | |
779 | u32 bm_status = 0; | |
780 | ||
50ffba1b | 781 | acpi_read_bit_register(ACPI_BITREG_BUS_MASTER_STATUS, &bm_status); |
4f86d3a8 | 782 | if (bm_status) |
50ffba1b | 783 | acpi_write_bit_register(ACPI_BITREG_BUS_MASTER_STATUS, 1); |
4f86d3a8 LB |
784 | /* |
785 | * PIIX4 Erratum #18: Note that BM_STS doesn't always reflect | |
786 | * the true state of bus mastering activity; forcing us to | |
787 | * manually check the BMIDEA bit of each IDE channel. | |
788 | */ | |
789 | else if (errata.piix4.bmisx) { | |
790 | if ((inb_p(errata.piix4.bmisx + 0x02) & 0x01) | |
791 | || (inb_p(errata.piix4.bmisx + 0x0A) & 0x01)) | |
792 | bm_status = 1; | |
793 | } | |
794 | return bm_status; | |
795 | } | |
796 | ||
4f86d3a8 LB |
797 | /** |
798 | * acpi_idle_do_entry - a helper function that does C2 and C3 type entry | |
799 | * @cx: cstate data | |
bc71bec9 | 800 | * |
801 | * Caller disables interrupt before call and enables interrupt after return. | |
4f86d3a8 LB |
802 | */ |
803 | static inline void acpi_idle_do_entry(struct acpi_processor_cx *cx) | |
804 | { | |
dcf30997 SR |
805 | /* Don't trace irqs off for idle */ |
806 | stop_critical_timings(); | |
bc71bec9 | 807 | if (cx->entry_method == ACPI_CSTATE_FFH) { |
4f86d3a8 LB |
808 | /* Call into architectural FFH based C-state */ |
809 | acpi_processor_ffh_cstate_enter(cx); | |
bc71bec9 | 810 | } else if (cx->entry_method == ACPI_CSTATE_HALT) { |
811 | acpi_safe_halt(); | |
4f86d3a8 LB |
812 | } else { |
813 | int unused; | |
814 | /* IO port based C-state */ | |
815 | inb(cx->address); | |
816 | /* Dummy wait op - must do something useless after P_LVL2 read | |
817 | because chipsets cannot guarantee that STPCLK# signal | |
818 | gets asserted in time to freeze execution properly. */ | |
819 | unused = inl(acpi_gbl_FADT.xpm_timer_block.address); | |
820 | } | |
dcf30997 | 821 | start_critical_timings(); |
4f86d3a8 LB |
822 | } |
823 | ||
824 | /** | |
825 | * acpi_idle_enter_c1 - enters an ACPI C1 state-type | |
826 | * @dev: the target CPU | |
827 | * @state: the state data | |
828 | * | |
829 | * This is equivalent to the HALT instruction. | |
830 | */ | |
831 | static int acpi_idle_enter_c1(struct cpuidle_device *dev, | |
832 | struct cpuidle_state *state) | |
833 | { | |
ff69f2bb | 834 | ktime_t kt1, kt2; |
835 | s64 idle_time; | |
4f86d3a8 LB |
836 | struct acpi_processor *pr; |
837 | struct acpi_processor_cx *cx = cpuidle_get_statedata(state); | |
9b12e18c | 838 | |
706546d0 | 839 | pr = __get_cpu_var(processors); |
4f86d3a8 LB |
840 | |
841 | if (unlikely(!pr)) | |
842 | return 0; | |
843 | ||
2e906655 | 844 | local_irq_disable(); |
b077fbad VP |
845 | |
846 | /* Do not access any ACPI IO ports in suspend path */ | |
847 | if (acpi_idle_suspend) { | |
b077fbad | 848 | local_irq_enable(); |
7d60e8ab | 849 | cpu_relax(); |
b077fbad VP |
850 | return 0; |
851 | } | |
852 | ||
7e275cc4 | 853 | lapic_timer_state_broadcast(pr, cx, 1); |
ff69f2bb | 854 | kt1 = ktime_get_real(); |
bc71bec9 | 855 | acpi_idle_do_entry(cx); |
ff69f2bb | 856 | kt2 = ktime_get_real(); |
857 | idle_time = ktime_to_us(ktime_sub(kt2, kt1)); | |
4f86d3a8 | 858 | |
2e906655 | 859 | local_irq_enable(); |
4f86d3a8 | 860 | cx->usage++; |
7e275cc4 | 861 | lapic_timer_state_broadcast(pr, cx, 0); |
4f86d3a8 | 862 | |
ff69f2bb | 863 | return idle_time; |
4f86d3a8 LB |
864 | } |
865 | ||
866 | /** | |
867 | * acpi_idle_enter_simple - enters an ACPI state without BM handling | |
868 | * @dev: the target CPU | |
869 | * @state: the state data | |
870 | */ | |
871 | static int acpi_idle_enter_simple(struct cpuidle_device *dev, | |
872 | struct cpuidle_state *state) | |
873 | { | |
874 | struct acpi_processor *pr; | |
875 | struct acpi_processor_cx *cx = cpuidle_get_statedata(state); | |
ff69f2bb | 876 | ktime_t kt1, kt2; |
877 | s64 idle_time; | |
878 | s64 sleep_ticks = 0; | |
50629118 | 879 | |
706546d0 | 880 | pr = __get_cpu_var(processors); |
4f86d3a8 LB |
881 | |
882 | if (unlikely(!pr)) | |
883 | return 0; | |
884 | ||
e196441b LB |
885 | if (acpi_idle_suspend) |
886 | return(acpi_idle_enter_c1(dev, state)); | |
887 | ||
4f86d3a8 LB |
888 | local_irq_disable(); |
889 | current_thread_info()->status &= ~TS_POLLING; | |
890 | /* | |
891 | * TS_POLLING-cleared state must be visible before we test | |
892 | * NEED_RESCHED: | |
893 | */ | |
894 | smp_mb(); | |
895 | ||
896 | if (unlikely(need_resched())) { | |
897 | current_thread_info()->status |= TS_POLLING; | |
898 | local_irq_enable(); | |
899 | return 0; | |
900 | } | |
901 | ||
e17bcb43 TG |
902 | /* |
903 | * Must be done before busmaster disable as we might need to | |
904 | * access HPET ! | |
905 | */ | |
7e275cc4 | 906 | lapic_timer_state_broadcast(pr, cx, 1); |
e17bcb43 | 907 | |
4f86d3a8 LB |
908 | if (cx->type == ACPI_STATE_C3) |
909 | ACPI_FLUSH_CPU_CACHE(); | |
910 | ||
ff69f2bb | 911 | kt1 = ktime_get_real(); |
50629118 VP |
912 | /* Tell the scheduler that we are going deep-idle: */ |
913 | sched_clock_idle_sleep_event(); | |
4f86d3a8 | 914 | acpi_idle_do_entry(cx); |
ff69f2bb | 915 | kt2 = ktime_get_real(); |
916 | idle_time = ktime_to_us(ktime_sub(kt2, kt1)); | |
4f86d3a8 | 917 | |
ff69f2bb | 918 | sleep_ticks = us_to_pm_timer_ticks(idle_time); |
50629118 VP |
919 | |
920 | /* Tell the scheduler how much we idled: */ | |
921 | sched_clock_idle_wakeup_event(sleep_ticks*PM_TIMER_TICK_NS); | |
4f86d3a8 LB |
922 | |
923 | local_irq_enable(); | |
924 | current_thread_info()->status |= TS_POLLING; | |
925 | ||
926 | cx->usage++; | |
927 | ||
7e275cc4 | 928 | lapic_timer_state_broadcast(pr, cx, 0); |
50629118 | 929 | cx->time += sleep_ticks; |
ff69f2bb | 930 | return idle_time; |
4f86d3a8 LB |
931 | } |
932 | ||
933 | static int c3_cpu_count; | |
934 | static DEFINE_SPINLOCK(c3_lock); | |
935 | ||
936 | /** | |
937 | * acpi_idle_enter_bm - enters C3 with proper BM handling | |
938 | * @dev: the target CPU | |
939 | * @state: the state data | |
940 | * | |
941 | * If BM is detected, the deepest non-C3 idle state is entered instead. | |
942 | */ | |
943 | static int acpi_idle_enter_bm(struct cpuidle_device *dev, | |
944 | struct cpuidle_state *state) | |
945 | { | |
946 | struct acpi_processor *pr; | |
947 | struct acpi_processor_cx *cx = cpuidle_get_statedata(state); | |
ff69f2bb | 948 | ktime_t kt1, kt2; |
949 | s64 idle_time; | |
950 | s64 sleep_ticks = 0; | |
951 | ||
50629118 | 952 | |
706546d0 | 953 | pr = __get_cpu_var(processors); |
4f86d3a8 LB |
954 | |
955 | if (unlikely(!pr)) | |
956 | return 0; | |
957 | ||
e196441b LB |
958 | if (acpi_idle_suspend) |
959 | return(acpi_idle_enter_c1(dev, state)); | |
960 | ||
ddc081a1 VP |
961 | if (acpi_idle_bm_check()) { |
962 | if (dev->safe_state) { | |
addbad46 | 963 | dev->last_state = dev->safe_state; |
ddc081a1 VP |
964 | return dev->safe_state->enter(dev, dev->safe_state); |
965 | } else { | |
2e906655 | 966 | local_irq_disable(); |
ddc081a1 | 967 | acpi_safe_halt(); |
2e906655 | 968 | local_irq_enable(); |
ddc081a1 VP |
969 | return 0; |
970 | } | |
971 | } | |
972 | ||
4f86d3a8 LB |
973 | local_irq_disable(); |
974 | current_thread_info()->status &= ~TS_POLLING; | |
975 | /* | |
976 | * TS_POLLING-cleared state must be visible before we test | |
977 | * NEED_RESCHED: | |
978 | */ | |
979 | smp_mb(); | |
980 | ||
981 | if (unlikely(need_resched())) { | |
982 | current_thread_info()->status |= TS_POLLING; | |
983 | local_irq_enable(); | |
984 | return 0; | |
985 | } | |
986 | ||
996520c1 VP |
987 | acpi_unlazy_tlb(smp_processor_id()); |
988 | ||
50629118 VP |
989 | /* Tell the scheduler that we are going deep-idle: */ |
990 | sched_clock_idle_sleep_event(); | |
4f86d3a8 LB |
991 | /* |
992 | * Must be done before busmaster disable as we might need to | |
993 | * access HPET ! | |
994 | */ | |
7e275cc4 | 995 | lapic_timer_state_broadcast(pr, cx, 1); |
4f86d3a8 | 996 | |
f461ddea | 997 | kt1 = ktime_get_real(); |
ddc081a1 VP |
998 | /* |
999 | * disable bus master | |
1000 | * bm_check implies we need ARB_DIS | |
1001 | * !bm_check implies we need cache flush | |
1002 | * bm_control implies whether we can do ARB_DIS | |
1003 | * | |
1004 | * That leaves a case where bm_check is set and bm_control is | |
1005 | * not set. In that case we cannot do much, we enter C3 | |
1006 | * without doing anything. | |
1007 | */ | |
1008 | if (pr->flags.bm_check && pr->flags.bm_control) { | |
4f86d3a8 LB |
1009 | spin_lock(&c3_lock); |
1010 | c3_cpu_count++; | |
1011 | /* Disable bus master arbitration when all CPUs are in C3 */ | |
1012 | if (c3_cpu_count == num_online_cpus()) | |
50ffba1b | 1013 | acpi_write_bit_register(ACPI_BITREG_ARB_DISABLE, 1); |
4f86d3a8 | 1014 | spin_unlock(&c3_lock); |
ddc081a1 VP |
1015 | } else if (!pr->flags.bm_check) { |
1016 | ACPI_FLUSH_CPU_CACHE(); | |
1017 | } | |
4f86d3a8 | 1018 | |
ddc081a1 | 1019 | acpi_idle_do_entry(cx); |
4f86d3a8 | 1020 | |
ddc081a1 VP |
1021 | /* Re-enable bus master arbitration */ |
1022 | if (pr->flags.bm_check && pr->flags.bm_control) { | |
4f86d3a8 | 1023 | spin_lock(&c3_lock); |
50ffba1b | 1024 | acpi_write_bit_register(ACPI_BITREG_ARB_DISABLE, 0); |
4f86d3a8 LB |
1025 | c3_cpu_count--; |
1026 | spin_unlock(&c3_lock); | |
1027 | } | |
f461ddea LB |
1028 | kt2 = ktime_get_real(); |
1029 | idle_time = ktime_to_us(ktime_sub(kt2, kt1)); | |
4f86d3a8 | 1030 | |
ff69f2bb | 1031 | sleep_ticks = us_to_pm_timer_ticks(idle_time); |
50629118 VP |
1032 | /* Tell the scheduler how much we idled: */ |
1033 | sched_clock_idle_wakeup_event(sleep_ticks*PM_TIMER_TICK_NS); | |
4f86d3a8 LB |
1034 | |
1035 | local_irq_enable(); | |
1036 | current_thread_info()->status |= TS_POLLING; | |
1037 | ||
1038 | cx->usage++; | |
1039 | ||
7e275cc4 | 1040 | lapic_timer_state_broadcast(pr, cx, 0); |
50629118 | 1041 | cx->time += sleep_ticks; |
ff69f2bb | 1042 | return idle_time; |
4f86d3a8 LB |
1043 | } |
1044 | ||
1045 | struct cpuidle_driver acpi_idle_driver = { | |
1046 | .name = "acpi_idle", | |
1047 | .owner = THIS_MODULE, | |
1048 | }; | |
1049 | ||
1050 | /** | |
1051 | * acpi_processor_setup_cpuidle - prepares and configures CPUIDLE | |
1052 | * @pr: the ACPI processor | |
1053 | */ | |
1054 | static int acpi_processor_setup_cpuidle(struct acpi_processor *pr) | |
1055 | { | |
9a0b8415 | 1056 | int i, count = CPUIDLE_DRIVER_STATE_START; |
4f86d3a8 LB |
1057 | struct acpi_processor_cx *cx; |
1058 | struct cpuidle_state *state; | |
1059 | struct cpuidle_device *dev = &pr->power.dev; | |
1060 | ||
1061 | if (!pr->flags.power_setup_done) | |
1062 | return -EINVAL; | |
1063 | ||
1064 | if (pr->flags.power == 0) { | |
1065 | return -EINVAL; | |
1066 | } | |
1067 | ||
dcb84f33 | 1068 | dev->cpu = pr->id; |
4fcb2fcd VP |
1069 | for (i = 0; i < CPUIDLE_STATE_MAX; i++) { |
1070 | dev->states[i].name[0] = '\0'; | |
1071 | dev->states[i].desc[0] = '\0'; | |
1072 | } | |
1073 | ||
615dfd93 LB |
1074 | if (max_cstate == 0) |
1075 | max_cstate = 1; | |
1076 | ||
4f86d3a8 LB |
1077 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER && i <= max_cstate; i++) { |
1078 | cx = &pr->power.states[i]; | |
1079 | state = &dev->states[count]; | |
1080 | ||
1081 | if (!cx->valid) | |
1082 | continue; | |
1083 | ||
1084 | #ifdef CONFIG_HOTPLUG_CPU | |
1085 | if ((cx->type != ACPI_STATE_C1) && (num_online_cpus() > 1) && | |
1086 | !pr->flags.has_cst && | |
1087 | !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED)) | |
1088 | continue; | |
1fec74a9 | 1089 | #endif |
4f86d3a8 LB |
1090 | cpuidle_set_statedata(state, cx); |
1091 | ||
1092 | snprintf(state->name, CPUIDLE_NAME_LEN, "C%d", i); | |
4fcb2fcd | 1093 | strncpy(state->desc, cx->desc, CPUIDLE_DESC_LEN); |
4f86d3a8 | 1094 | state->exit_latency = cx->latency; |
4963f620 | 1095 | state->target_residency = cx->latency * latency_factor; |
4f86d3a8 LB |
1096 | state->power_usage = cx->power; |
1097 | ||
1098 | state->flags = 0; | |
1099 | switch (cx->type) { | |
1100 | case ACPI_STATE_C1: | |
1101 | state->flags |= CPUIDLE_FLAG_SHALLOW; | |
8e92b660 VP |
1102 | if (cx->entry_method == ACPI_CSTATE_FFH) |
1103 | state->flags |= CPUIDLE_FLAG_TIME_VALID; | |
1104 | ||
4f86d3a8 | 1105 | state->enter = acpi_idle_enter_c1; |
ddc081a1 | 1106 | dev->safe_state = state; |
4f86d3a8 LB |
1107 | break; |
1108 | ||
1109 | case ACPI_STATE_C2: | |
1110 | state->flags |= CPUIDLE_FLAG_BALANCED; | |
1111 | state->flags |= CPUIDLE_FLAG_TIME_VALID; | |
1112 | state->enter = acpi_idle_enter_simple; | |
ddc081a1 | 1113 | dev->safe_state = state; |
4f86d3a8 LB |
1114 | break; |
1115 | ||
1116 | case ACPI_STATE_C3: | |
1117 | state->flags |= CPUIDLE_FLAG_DEEP; | |
1118 | state->flags |= CPUIDLE_FLAG_TIME_VALID; | |
1119 | state->flags |= CPUIDLE_FLAG_CHECK_BM; | |
1120 | state->enter = pr->flags.bm_check ? | |
1121 | acpi_idle_enter_bm : | |
1122 | acpi_idle_enter_simple; | |
1123 | break; | |
1124 | } | |
1125 | ||
1126 | count++; | |
9a0b8415 | 1127 | if (count == CPUIDLE_STATE_MAX) |
1128 | break; | |
4f86d3a8 LB |
1129 | } |
1130 | ||
1131 | dev->state_count = count; | |
1132 | ||
1133 | if (!count) | |
1134 | return -EINVAL; | |
1135 | ||
4f86d3a8 LB |
1136 | return 0; |
1137 | } | |
1138 | ||
1139 | int acpi_processor_cst_has_changed(struct acpi_processor *pr) | |
1140 | { | |
dcb84f33 | 1141 | int ret = 0; |
4f86d3a8 | 1142 | |
36a91358 VP |
1143 | if (boot_option_idle_override) |
1144 | return 0; | |
1145 | ||
4f86d3a8 LB |
1146 | if (!pr) |
1147 | return -EINVAL; | |
1148 | ||
1149 | if (nocst) { | |
1150 | return -ENODEV; | |
1151 | } | |
1152 | ||
1153 | if (!pr->flags.power_setup_done) | |
1154 | return -ENODEV; | |
1155 | ||
1156 | cpuidle_pause_and_lock(); | |
1157 | cpuidle_disable_device(&pr->power.dev); | |
1158 | acpi_processor_get_power_info(pr); | |
dcb84f33 VP |
1159 | if (pr->flags.power) { |
1160 | acpi_processor_setup_cpuidle(pr); | |
1161 | ret = cpuidle_enable_device(&pr->power.dev); | |
1162 | } | |
4f86d3a8 LB |
1163 | cpuidle_resume_and_unlock(); |
1164 | ||
1165 | return ret; | |
1166 | } | |
1167 | ||
7af8b660 | 1168 | int __cpuinit acpi_processor_power_init(struct acpi_processor *pr, |
4be44fcd | 1169 | struct acpi_device *device) |
1da177e4 | 1170 | { |
4be44fcd | 1171 | acpi_status status = 0; |
b6835052 | 1172 | static int first_run; |
b188e4ce | 1173 | #ifdef CONFIG_ACPI_PROCFS |
4be44fcd | 1174 | struct proc_dir_entry *entry = NULL; |
b188e4ce | 1175 | #endif |
1da177e4 | 1176 | |
36a91358 VP |
1177 | if (boot_option_idle_override) |
1178 | return 0; | |
1da177e4 LT |
1179 | |
1180 | if (!first_run) { | |
c1e3b377 ZY |
1181 | if (idle_halt) { |
1182 | /* | |
1183 | * When the boot option of "idle=halt" is added, halt | |
1184 | * is used for CPU IDLE. | |
1185 | * In such case C2/C3 is meaningless. So the max_cstate | |
1186 | * is set to one. | |
1187 | */ | |
1188 | max_cstate = 1; | |
1189 | } | |
1da177e4 | 1190 | dmi_check_system(processor_power_dmi_table); |
c1c30634 | 1191 | max_cstate = acpi_processor_cstate_check(max_cstate); |
1da177e4 | 1192 | if (max_cstate < ACPI_C_STATES_MAX) |
4be44fcd LB |
1193 | printk(KERN_NOTICE |
1194 | "ACPI: processor limited to max C-state %d\n", | |
1195 | max_cstate); | |
1da177e4 LT |
1196 | first_run++; |
1197 | } | |
1198 | ||
02df8b93 | 1199 | if (!pr) |
d550d98d | 1200 | return -EINVAL; |
02df8b93 | 1201 | |
cee324b1 | 1202 | if (acpi_gbl_FADT.cst_control && !nocst) { |
4be44fcd | 1203 | status = |
cee324b1 | 1204 | acpi_os_write_port(acpi_gbl_FADT.smi_command, acpi_gbl_FADT.cst_control, 8); |
1da177e4 | 1205 | if (ACPI_FAILURE(status)) { |
a6fc6720 TR |
1206 | ACPI_EXCEPTION((AE_INFO, status, |
1207 | "Notifying BIOS of _CST ability failed")); | |
1da177e4 LT |
1208 | } |
1209 | } | |
1210 | ||
1211 | acpi_processor_get_power_info(pr); | |
4f86d3a8 | 1212 | pr->flags.power_setup_done = 1; |
1da177e4 LT |
1213 | |
1214 | /* | |
1215 | * Install the idle handler if processor power management is supported. | |
1216 | * Note that we use previously set idle handler will be used on | |
1217 | * platforms that only support C1. | |
1218 | */ | |
36a91358 | 1219 | if (pr->flags.power) { |
4f86d3a8 | 1220 | acpi_processor_setup_cpuidle(pr); |
4f86d3a8 LB |
1221 | if (cpuidle_register_device(&pr->power.dev)) |
1222 | return -EIO; | |
1da177e4 | 1223 | } |
74cad4ee | 1224 | #ifdef CONFIG_ACPI_PROCFS |
1da177e4 | 1225 | /* 'power' [R] */ |
cf7acfab DL |
1226 | entry = proc_create_data(ACPI_PROCESSOR_FILE_POWER, |
1227 | S_IRUGO, acpi_device_dir(device), | |
1228 | &acpi_processor_power_fops, | |
1229 | acpi_driver_data(device)); | |
1da177e4 | 1230 | if (!entry) |
a6fc6720 | 1231 | return -EIO; |
74cad4ee | 1232 | #endif |
d550d98d | 1233 | return 0; |
1da177e4 LT |
1234 | } |
1235 | ||
4be44fcd LB |
1236 | int acpi_processor_power_exit(struct acpi_processor *pr, |
1237 | struct acpi_device *device) | |
1da177e4 | 1238 | { |
36a91358 VP |
1239 | if (boot_option_idle_override) |
1240 | return 0; | |
1241 | ||
dcb84f33 | 1242 | cpuidle_unregister_device(&pr->power.dev); |
1da177e4 LT |
1243 | pr->flags.power_setup_done = 0; |
1244 | ||
74cad4ee | 1245 | #ifdef CONFIG_ACPI_PROCFS |
1da177e4 | 1246 | if (acpi_device_dir(device)) |
4be44fcd LB |
1247 | remove_proc_entry(ACPI_PROCESSOR_FILE_POWER, |
1248 | acpi_device_dir(device)); | |
74cad4ee | 1249 | #endif |
1da177e4 | 1250 | |
d550d98d | 1251 | return 0; |
1da177e4 | 1252 | } |