Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * processor_idle - idle state submodule to the ACPI processor driver | |
3 | * | |
4 | * Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com> | |
5 | * Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com> | |
c5ab81ca | 6 | * Copyright (C) 2004, 2005 Dominik Brodowski <linux@brodo.de> |
1da177e4 LT |
7 | * Copyright (C) 2004 Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> |
8 | * - Added processor hotplug support | |
02df8b93 VP |
9 | * Copyright (C) 2005 Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> |
10 | * - Added support for C3 on SMP | |
1da177e4 LT |
11 | * |
12 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or modify | |
15 | * it under the terms of the GNU General Public License as published by | |
16 | * the Free Software Foundation; either version 2 of the License, or (at | |
17 | * your option) any later version. | |
18 | * | |
19 | * This program is distributed in the hope that it will be useful, but | |
20 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
22 | * General Public License for more details. | |
23 | * | |
24 | * You should have received a copy of the GNU General Public License along | |
25 | * with this program; if not, write to the Free Software Foundation, Inc., | |
26 | * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. | |
27 | * | |
28 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
29 | */ | |
30 | ||
31 | #include <linux/kernel.h> | |
32 | #include <linux/module.h> | |
33 | #include <linux/init.h> | |
34 | #include <linux/cpufreq.h> | |
35 | #include <linux/proc_fs.h> | |
36 | #include <linux/seq_file.h> | |
37 | #include <linux/acpi.h> | |
38 | #include <linux/dmi.h> | |
39 | #include <linux/moduleparam.h> | |
4e57b681 | 40 | #include <linux/sched.h> /* need_resched() */ |
f011e2e2 | 41 | #include <linux/pm_qos_params.h> |
e9e2cdb4 | 42 | #include <linux/clockchips.h> |
4f86d3a8 | 43 | #include <linux/cpuidle.h> |
c1e3b377 | 44 | #include <linux/cpuidle.h> |
1da177e4 | 45 | |
3434933b TG |
46 | /* |
47 | * Include the apic definitions for x86 to have the APIC timer related defines | |
48 | * available also for UP (on SMP it gets magically included via linux/smp.h). | |
49 | * asm/acpi.h is not an option, as it would require more include magic. Also | |
50 | * creating an empty asm-ia64/apic.h would just trade pest vs. cholera. | |
51 | */ | |
52 | #ifdef CONFIG_X86 | |
53 | #include <asm/apic.h> | |
54 | #endif | |
55 | ||
1da177e4 LT |
56 | #include <asm/io.h> |
57 | #include <asm/uaccess.h> | |
58 | ||
59 | #include <acpi/acpi_bus.h> | |
60 | #include <acpi/processor.h> | |
c1e3b377 | 61 | #include <asm/processor.h> |
1da177e4 LT |
62 | |
63 | #define ACPI_PROCESSOR_COMPONENT 0x01000000 | |
64 | #define ACPI_PROCESSOR_CLASS "processor" | |
1da177e4 | 65 | #define _COMPONENT ACPI_PROCESSOR_COMPONENT |
f52fd66d | 66 | ACPI_MODULE_NAME("processor_idle"); |
1da177e4 | 67 | #define ACPI_PROCESSOR_FILE_POWER "power" |
1da177e4 | 68 | #define US_TO_PM_TIMER_TICKS(t) ((t * (PM_TIMER_FREQUENCY/1000)) / 1000) |
2aa44d05 | 69 | #define PM_TIMER_TICK_NS (1000000000ULL/PM_TIMER_FREQUENCY) |
4f86d3a8 | 70 | #ifndef CONFIG_CPU_IDLE |
1da177e4 LT |
71 | #define C2_OVERHEAD 4 /* 1us (3.579 ticks per us) */ |
72 | #define C3_OVERHEAD 4 /* 1us (3.579 ticks per us) */ | |
b6835052 | 73 | static void (*pm_idle_save) (void) __read_mostly; |
4f86d3a8 LB |
74 | #else |
75 | #define C2_OVERHEAD 1 /* 1us */ | |
76 | #define C3_OVERHEAD 1 /* 1us */ | |
77 | #endif | |
78 | #define PM_TIMER_TICKS_TO_US(p) (((p) * 1000)/(PM_TIMER_FREQUENCY/1000)) | |
1da177e4 | 79 | |
4f86d3a8 | 80 | static unsigned int max_cstate __read_mostly = ACPI_PROCESSOR_MAX_POWER; |
5b3f0e6c | 81 | #ifdef CONFIG_CPU_IDLE |
4f86d3a8 | 82 | module_param(max_cstate, uint, 0000); |
5b3f0e6c VP |
83 | #else |
84 | module_param(max_cstate, uint, 0644); | |
85 | #endif | |
b6835052 | 86 | static unsigned int nocst __read_mostly; |
1da177e4 LT |
87 | module_param(nocst, uint, 0000); |
88 | ||
4f86d3a8 | 89 | #ifndef CONFIG_CPU_IDLE |
1da177e4 LT |
90 | /* |
91 | * bm_history -- bit-mask with a bit per jiffy of bus-master activity | |
92 | * 1000 HZ: 0xFFFFFFFF: 32 jiffies = 32ms | |
93 | * 800 HZ: 0xFFFFFFFF: 32 jiffies = 40ms | |
94 | * 100 HZ: 0x0000000F: 4 jiffies = 40ms | |
95 | * reduce history for more aggressive entry into C3 | |
96 | */ | |
b6835052 | 97 | static unsigned int bm_history __read_mostly = |
4be44fcd | 98 | (HZ >= 800 ? 0xFFFFFFFF : ((1U << (HZ / 25)) - 1)); |
1da177e4 | 99 | module_param(bm_history, uint, 0644); |
4f86d3a8 LB |
100 | |
101 | static int acpi_processor_set_power_policy(struct acpi_processor *pr); | |
102 | ||
4963f620 | 103 | #else /* CONFIG_CPU_IDLE */ |
25de5718 | 104 | static unsigned int latency_factor __read_mostly = 2; |
4963f620 | 105 | module_param(latency_factor, uint, 0644); |
4f86d3a8 | 106 | #endif |
1da177e4 LT |
107 | |
108 | /* | |
109 | * IBM ThinkPad R40e crashes mysteriously when going into C2 or C3. | |
110 | * For now disable this. Probably a bug somewhere else. | |
111 | * | |
112 | * To skip this limit, boot/load with a large max_cstate limit. | |
113 | */ | |
1855256c | 114 | static int set_max_cstate(const struct dmi_system_id *id) |
1da177e4 LT |
115 | { |
116 | if (max_cstate > ACPI_PROCESSOR_MAX_POWER) | |
117 | return 0; | |
118 | ||
3d35600a | 119 | printk(KERN_NOTICE PREFIX "%s detected - limiting to C%ld max_cstate." |
4be44fcd LB |
120 | " Override with \"processor.max_cstate=%d\"\n", id->ident, |
121 | (long)id->driver_data, ACPI_PROCESSOR_MAX_POWER + 1); | |
1da177e4 | 122 | |
3d35600a | 123 | max_cstate = (long)id->driver_data; |
1da177e4 LT |
124 | |
125 | return 0; | |
126 | } | |
127 | ||
7ded5689 AR |
128 | /* Actually this shouldn't be __cpuinitdata, would be better to fix the |
129 | callers to only run once -AK */ | |
130 | static struct dmi_system_id __cpuinitdata processor_power_dmi_table[] = { | |
f831335d BS |
131 | { set_max_cstate, "IBM ThinkPad R40e", { |
132 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
133 | DMI_MATCH(DMI_BIOS_VERSION,"1SET70WW")}, (void *)1}, | |
876c184b TR |
134 | { set_max_cstate, "IBM ThinkPad R40e", { |
135 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
136 | DMI_MATCH(DMI_BIOS_VERSION,"1SET60WW")}, (void *)1}, | |
137 | { set_max_cstate, "IBM ThinkPad R40e", { | |
138 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
139 | DMI_MATCH(DMI_BIOS_VERSION,"1SET43WW") }, (void*)1}, | |
140 | { set_max_cstate, "IBM ThinkPad R40e", { | |
141 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
142 | DMI_MATCH(DMI_BIOS_VERSION,"1SET45WW") }, (void*)1}, | |
143 | { set_max_cstate, "IBM ThinkPad R40e", { | |
144 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
145 | DMI_MATCH(DMI_BIOS_VERSION,"1SET47WW") }, (void*)1}, | |
146 | { set_max_cstate, "IBM ThinkPad R40e", { | |
147 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
148 | DMI_MATCH(DMI_BIOS_VERSION,"1SET50WW") }, (void*)1}, | |
149 | { set_max_cstate, "IBM ThinkPad R40e", { | |
150 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
151 | DMI_MATCH(DMI_BIOS_VERSION,"1SET52WW") }, (void*)1}, | |
152 | { set_max_cstate, "IBM ThinkPad R40e", { | |
153 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
154 | DMI_MATCH(DMI_BIOS_VERSION,"1SET55WW") }, (void*)1}, | |
155 | { set_max_cstate, "IBM ThinkPad R40e", { | |
156 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
157 | DMI_MATCH(DMI_BIOS_VERSION,"1SET56WW") }, (void*)1}, | |
158 | { set_max_cstate, "IBM ThinkPad R40e", { | |
159 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
160 | DMI_MATCH(DMI_BIOS_VERSION,"1SET59WW") }, (void*)1}, | |
161 | { set_max_cstate, "IBM ThinkPad R40e", { | |
162 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
163 | DMI_MATCH(DMI_BIOS_VERSION,"1SET60WW") }, (void*)1}, | |
164 | { set_max_cstate, "IBM ThinkPad R40e", { | |
165 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
166 | DMI_MATCH(DMI_BIOS_VERSION,"1SET61WW") }, (void*)1}, | |
167 | { set_max_cstate, "IBM ThinkPad R40e", { | |
168 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
169 | DMI_MATCH(DMI_BIOS_VERSION,"1SET62WW") }, (void*)1}, | |
170 | { set_max_cstate, "IBM ThinkPad R40e", { | |
171 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
172 | DMI_MATCH(DMI_BIOS_VERSION,"1SET64WW") }, (void*)1}, | |
173 | { set_max_cstate, "IBM ThinkPad R40e", { | |
174 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
175 | DMI_MATCH(DMI_BIOS_VERSION,"1SET65WW") }, (void*)1}, | |
176 | { set_max_cstate, "IBM ThinkPad R40e", { | |
177 | DMI_MATCH(DMI_BIOS_VENDOR,"IBM"), | |
178 | DMI_MATCH(DMI_BIOS_VERSION,"1SET68WW") }, (void*)1}, | |
179 | { set_max_cstate, "Medion 41700", { | |
180 | DMI_MATCH(DMI_BIOS_VENDOR,"Phoenix Technologies LTD"), | |
181 | DMI_MATCH(DMI_BIOS_VERSION,"R01-A1J")}, (void *)1}, | |
182 | { set_max_cstate, "Clevo 5600D", { | |
183 | DMI_MATCH(DMI_BIOS_VENDOR,"Phoenix Technologies LTD"), | |
184 | DMI_MATCH(DMI_BIOS_VERSION,"SHE845M0.86C.0013.D.0302131307")}, | |
4be44fcd | 185 | (void *)2}, |
1da177e4 LT |
186 | {}, |
187 | }; | |
188 | ||
4be44fcd | 189 | static inline u32 ticks_elapsed(u32 t1, u32 t2) |
1da177e4 LT |
190 | { |
191 | if (t2 >= t1) | |
192 | return (t2 - t1); | |
cee324b1 | 193 | else if (!(acpi_gbl_FADT.flags & ACPI_FADT_32BIT_TIMER)) |
1da177e4 LT |
194 | return (((0x00FFFFFF - t1) + t2) & 0x00FFFFFF); |
195 | else | |
196 | return ((0xFFFFFFFF - t1) + t2); | |
197 | } | |
198 | ||
4f86d3a8 LB |
199 | static inline u32 ticks_elapsed_in_us(u32 t1, u32 t2) |
200 | { | |
201 | if (t2 >= t1) | |
202 | return PM_TIMER_TICKS_TO_US(t2 - t1); | |
203 | else if (!(acpi_gbl_FADT.flags & ACPI_FADT_32BIT_TIMER)) | |
204 | return PM_TIMER_TICKS_TO_US(((0x00FFFFFF - t1) + t2) & 0x00FFFFFF); | |
205 | else | |
206 | return PM_TIMER_TICKS_TO_US((0xFFFFFFFF - t1) + t2); | |
207 | } | |
208 | ||
2e906655 | 209 | /* |
210 | * Callers should disable interrupts before the call and enable | |
211 | * interrupts after return. | |
212 | */ | |
ddc081a1 VP |
213 | static void acpi_safe_halt(void) |
214 | { | |
215 | current_thread_info()->status &= ~TS_POLLING; | |
216 | /* | |
217 | * TS_POLLING-cleared state must be visible before we | |
218 | * test NEED_RESCHED: | |
219 | */ | |
220 | smp_mb(); | |
71e93d15 | 221 | if (!need_resched()) { |
ddc081a1 | 222 | safe_halt(); |
71e93d15 VP |
223 | local_irq_disable(); |
224 | } | |
ddc081a1 VP |
225 | current_thread_info()->status |= TS_POLLING; |
226 | } | |
227 | ||
4f86d3a8 LB |
228 | #ifndef CONFIG_CPU_IDLE |
229 | ||
1da177e4 | 230 | static void |
4be44fcd LB |
231 | acpi_processor_power_activate(struct acpi_processor *pr, |
232 | struct acpi_processor_cx *new) | |
1da177e4 | 233 | { |
4be44fcd | 234 | struct acpi_processor_cx *old; |
1da177e4 LT |
235 | |
236 | if (!pr || !new) | |
237 | return; | |
238 | ||
239 | old = pr->power.state; | |
240 | ||
241 | if (old) | |
242 | old->promotion.count = 0; | |
4be44fcd | 243 | new->demotion.count = 0; |
1da177e4 LT |
244 | |
245 | /* Cleanup from old state. */ | |
246 | if (old) { | |
247 | switch (old->type) { | |
248 | case ACPI_STATE_C3: | |
249 | /* Disable bus master reload */ | |
02df8b93 | 250 | if (new->type != ACPI_STATE_C3 && pr->flags.bm_check) |
d8c71b6d | 251 | acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 0); |
1da177e4 LT |
252 | break; |
253 | } | |
254 | } | |
255 | ||
256 | /* Prepare to use new state. */ | |
257 | switch (new->type) { | |
258 | case ACPI_STATE_C3: | |
259 | /* Enable bus master reload */ | |
02df8b93 | 260 | if (old->type != ACPI_STATE_C3 && pr->flags.bm_check) |
d8c71b6d | 261 | acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 1); |
1da177e4 LT |
262 | break; |
263 | } | |
264 | ||
265 | pr->power.state = new; | |
266 | ||
267 | return; | |
268 | } | |
269 | ||
4be44fcd | 270 | static atomic_t c3_cpu_count; |
1da177e4 | 271 | |
991528d7 VP |
272 | /* Common C-state entry for C2, C3, .. */ |
273 | static void acpi_cstate_enter(struct acpi_processor_cx *cstate) | |
274 | { | |
bc71bec9 | 275 | if (cstate->entry_method == ACPI_CSTATE_FFH) { |
991528d7 VP |
276 | /* Call into architectural FFH based C-state */ |
277 | acpi_processor_ffh_cstate_enter(cstate); | |
278 | } else { | |
279 | int unused; | |
280 | /* IO port based C-state */ | |
281 | inb(cstate->address); | |
282 | /* Dummy wait op - must do something useless after P_LVL2 read | |
283 | because chipsets cannot guarantee that STPCLK# signal | |
284 | gets asserted in time to freeze execution properly. */ | |
cee324b1 | 285 | unused = inl(acpi_gbl_FADT.xpm_timer_block.address); |
991528d7 VP |
286 | } |
287 | } | |
4f86d3a8 | 288 | #endif /* !CONFIG_CPU_IDLE */ |
991528d7 | 289 | |
169a0abb TG |
290 | #ifdef ARCH_APICTIMER_STOPS_ON_C3 |
291 | ||
292 | /* | |
293 | * Some BIOS implementations switch to C3 in the published C2 state. | |
296d93cd LT |
294 | * This seems to be a common problem on AMD boxen, but other vendors |
295 | * are affected too. We pick the most conservative approach: we assume | |
296 | * that the local APIC stops in both C2 and C3. | |
169a0abb TG |
297 | */ |
298 | static void acpi_timer_check_state(int state, struct acpi_processor *pr, | |
299 | struct acpi_processor_cx *cx) | |
300 | { | |
301 | struct acpi_processor_power *pwr = &pr->power; | |
e585bef8 | 302 | u8 type = local_apic_timer_c2_ok ? ACPI_STATE_C3 : ACPI_STATE_C2; |
169a0abb TG |
303 | |
304 | /* | |
305 | * Check, if one of the previous states already marked the lapic | |
306 | * unstable | |
307 | */ | |
308 | if (pwr->timer_broadcast_on_state < state) | |
309 | return; | |
310 | ||
e585bef8 | 311 | if (cx->type >= type) |
296d93cd | 312 | pr->power.timer_broadcast_on_state = state; |
169a0abb TG |
313 | } |
314 | ||
315 | static void acpi_propagate_timer_broadcast(struct acpi_processor *pr) | |
316 | { | |
e9e2cdb4 TG |
317 | unsigned long reason; |
318 | ||
319 | reason = pr->power.timer_broadcast_on_state < INT_MAX ? | |
320 | CLOCK_EVT_NOTIFY_BROADCAST_ON : CLOCK_EVT_NOTIFY_BROADCAST_OFF; | |
321 | ||
322 | clockevents_notify(reason, &pr->id); | |
e9e2cdb4 TG |
323 | } |
324 | ||
325 | /* Power(C) State timer broadcast control */ | |
326 | static void acpi_state_timer_broadcast(struct acpi_processor *pr, | |
327 | struct acpi_processor_cx *cx, | |
328 | int broadcast) | |
329 | { | |
e9e2cdb4 TG |
330 | int state = cx - pr->power.states; |
331 | ||
332 | if (state >= pr->power.timer_broadcast_on_state) { | |
333 | unsigned long reason; | |
334 | ||
335 | reason = broadcast ? CLOCK_EVT_NOTIFY_BROADCAST_ENTER : | |
336 | CLOCK_EVT_NOTIFY_BROADCAST_EXIT; | |
337 | clockevents_notify(reason, &pr->id); | |
338 | } | |
169a0abb TG |
339 | } |
340 | ||
341 | #else | |
342 | ||
343 | static void acpi_timer_check_state(int state, struct acpi_processor *pr, | |
344 | struct acpi_processor_cx *cstate) { } | |
345 | static void acpi_propagate_timer_broadcast(struct acpi_processor *pr) { } | |
e9e2cdb4 TG |
346 | static void acpi_state_timer_broadcast(struct acpi_processor *pr, |
347 | struct acpi_processor_cx *cx, | |
348 | int broadcast) | |
349 | { | |
350 | } | |
169a0abb TG |
351 | |
352 | #endif | |
353 | ||
b04e7bdb TG |
354 | /* |
355 | * Suspend / resume control | |
356 | */ | |
357 | static int acpi_idle_suspend; | |
358 | ||
359 | int acpi_processor_suspend(struct acpi_device * device, pm_message_t state) | |
360 | { | |
361 | acpi_idle_suspend = 1; | |
362 | return 0; | |
363 | } | |
364 | ||
365 | int acpi_processor_resume(struct acpi_device * device) | |
366 | { | |
367 | acpi_idle_suspend = 0; | |
368 | return 0; | |
369 | } | |
370 | ||
61331168 | 371 | #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86) |
ddb25f9a AK |
372 | static int tsc_halts_in_c(int state) |
373 | { | |
374 | switch (boot_cpu_data.x86_vendor) { | |
375 | case X86_VENDOR_AMD: | |
376 | /* | |
377 | * AMD Fam10h TSC will tick in all | |
378 | * C/P/S0/S1 states when this bit is set. | |
379 | */ | |
380 | if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) | |
381 | return 0; | |
382 | /*FALL THROUGH*/ | |
383 | case X86_VENDOR_INTEL: | |
384 | /* Several cases known where TSC halts in C2 too */ | |
385 | default: | |
386 | return state > ACPI_STATE_C1; | |
387 | } | |
388 | } | |
389 | #endif | |
390 | ||
4f86d3a8 | 391 | #ifndef CONFIG_CPU_IDLE |
4be44fcd | 392 | static void acpi_processor_idle(void) |
1da177e4 | 393 | { |
4be44fcd | 394 | struct acpi_processor *pr = NULL; |
1da177e4 LT |
395 | struct acpi_processor_cx *cx = NULL; |
396 | struct acpi_processor_cx *next_state = NULL; | |
4be44fcd LB |
397 | int sleep_ticks = 0; |
398 | u32 t1, t2 = 0; | |
1da177e4 | 399 | |
1da177e4 LT |
400 | /* |
401 | * Interrupts must be disabled during bus mastering calculations and | |
402 | * for C2/C3 transitions. | |
403 | */ | |
404 | local_irq_disable(); | |
405 | ||
706546d0 | 406 | pr = __get_cpu_var(processors); |
d5a3d32a VP |
407 | if (!pr) { |
408 | local_irq_enable(); | |
409 | return; | |
410 | } | |
411 | ||
1da177e4 LT |
412 | /* |
413 | * Check whether we truly need to go idle, or should | |
414 | * reschedule: | |
415 | */ | |
416 | if (unlikely(need_resched())) { | |
417 | local_irq_enable(); | |
418 | return; | |
419 | } | |
420 | ||
421 | cx = pr->power.state; | |
b04e7bdb | 422 | if (!cx || acpi_idle_suspend) { |
7f424a8b PZ |
423 | if (pm_idle_save) { |
424 | pm_idle_save(); /* enables IRQs */ | |
425 | } else { | |
64c7c8f8 | 426 | acpi_safe_halt(); |
71e93d15 | 427 | local_irq_enable(); |
7f424a8b | 428 | } |
71e93d15 | 429 | |
64c7c8f8 NP |
430 | return; |
431 | } | |
1da177e4 LT |
432 | |
433 | /* | |
434 | * Check BM Activity | |
435 | * ----------------- | |
436 | * Check for bus mastering activity (if required), record, and check | |
437 | * for demotion. | |
438 | */ | |
439 | if (pr->flags.bm_check) { | |
4be44fcd LB |
440 | u32 bm_status = 0; |
441 | unsigned long diff = jiffies - pr->power.bm_check_timestamp; | |
1da177e4 | 442 | |
c5ab81ca DB |
443 | if (diff > 31) |
444 | diff = 31; | |
1da177e4 | 445 | |
c5ab81ca | 446 | pr->power.bm_activity <<= diff; |
1da177e4 | 447 | |
d8c71b6d | 448 | acpi_get_register(ACPI_BITREG_BUS_MASTER_STATUS, &bm_status); |
1da177e4 | 449 | if (bm_status) { |
c5ab81ca | 450 | pr->power.bm_activity |= 0x1; |
d8c71b6d | 451 | acpi_set_register(ACPI_BITREG_BUS_MASTER_STATUS, 1); |
1da177e4 LT |
452 | } |
453 | /* | |
454 | * PIIX4 Erratum #18: Note that BM_STS doesn't always reflect | |
455 | * the true state of bus mastering activity; forcing us to | |
456 | * manually check the BMIDEA bit of each IDE channel. | |
457 | */ | |
458 | else if (errata.piix4.bmisx) { | |
459 | if ((inb_p(errata.piix4.bmisx + 0x02) & 0x01) | |
4be44fcd | 460 | || (inb_p(errata.piix4.bmisx + 0x0A) & 0x01)) |
c5ab81ca | 461 | pr->power.bm_activity |= 0x1; |
1da177e4 LT |
462 | } |
463 | ||
464 | pr->power.bm_check_timestamp = jiffies; | |
465 | ||
466 | /* | |
c4a001b1 | 467 | * If bus mastering is or was active this jiffy, demote |
1da177e4 LT |
468 | * to avoid a faulty transition. Note that the processor |
469 | * won't enter a low-power state during this call (to this | |
c4a001b1 | 470 | * function) but should upon the next. |
1da177e4 LT |
471 | * |
472 | * TBD: A better policy might be to fallback to the demotion | |
473 | * state (use it for this quantum only) istead of | |
474 | * demoting -- and rely on duration as our sole demotion | |
475 | * qualification. This may, however, introduce DMA | |
476 | * issues (e.g. floppy DMA transfer overrun/underrun). | |
477 | */ | |
c4a001b1 DB |
478 | if ((pr->power.bm_activity & 0x1) && |
479 | cx->demotion.threshold.bm) { | |
1da177e4 LT |
480 | local_irq_enable(); |
481 | next_state = cx->demotion.state; | |
482 | goto end; | |
483 | } | |
484 | } | |
485 | ||
4c033552 VP |
486 | #ifdef CONFIG_HOTPLUG_CPU |
487 | /* | |
488 | * Check for P_LVL2_UP flag before entering C2 and above on | |
489 | * an SMP system. We do it here instead of doing it at _CST/P_LVL | |
490 | * detection phase, to work cleanly with logical CPU hotplug. | |
491 | */ | |
4f86d3a8 | 492 | if ((cx->type != ACPI_STATE_C1) && (num_online_cpus() > 1) && |
cee324b1 | 493 | !pr->flags.has_cst && !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED)) |
1e483969 | 494 | cx = &pr->power.states[ACPI_STATE_C1]; |
4c033552 | 495 | #endif |
1e483969 | 496 | |
1da177e4 LT |
497 | /* |
498 | * Sleep: | |
499 | * ------ | |
500 | * Invoke the current Cx state to put the processor to sleep. | |
501 | */ | |
2a298a35 | 502 | if (cx->type == ACPI_STATE_C2 || cx->type == ACPI_STATE_C3) { |
495ab9c0 | 503 | current_thread_info()->status &= ~TS_POLLING; |
0888f06a IM |
504 | /* |
505 | * TS_POLLING-cleared state must be visible before we | |
506 | * test NEED_RESCHED: | |
507 | */ | |
508 | smp_mb(); | |
2a298a35 | 509 | if (need_resched()) { |
495ab9c0 | 510 | current_thread_info()->status |= TS_POLLING; |
af2eb17b | 511 | local_irq_enable(); |
2a298a35 NP |
512 | return; |
513 | } | |
514 | } | |
515 | ||
1da177e4 LT |
516 | switch (cx->type) { |
517 | ||
518 | case ACPI_STATE_C1: | |
519 | /* | |
520 | * Invoke C1. | |
521 | * Use the appropriate idle routine, the one that would | |
522 | * be used without acpi C-states. | |
523 | */ | |
7f424a8b PZ |
524 | if (pm_idle_save) { |
525 | pm_idle_save(); /* enables IRQs */ | |
526 | } else { | |
64c7c8f8 | 527 | acpi_safe_halt(); |
7f424a8b PZ |
528 | local_irq_enable(); |
529 | } | |
64c7c8f8 | 530 | |
1da177e4 | 531 | /* |
4be44fcd | 532 | * TBD: Can't get time duration while in C1, as resumes |
1da177e4 LT |
533 | * go to an ISR rather than here. Need to instrument |
534 | * base interrupt handler. | |
2aa44d05 IM |
535 | * |
536 | * Note: the TSC better not stop in C1, sched_clock() will | |
537 | * skew otherwise. | |
1da177e4 LT |
538 | */ |
539 | sleep_ticks = 0xFFFFFFFF; | |
71e93d15 | 540 | |
1da177e4 LT |
541 | break; |
542 | ||
543 | case ACPI_STATE_C2: | |
544 | /* Get start time (ticks) */ | |
cee324b1 | 545 | t1 = inl(acpi_gbl_FADT.xpm_timer_block.address); |
2aa44d05 IM |
546 | /* Tell the scheduler that we are going deep-idle: */ |
547 | sched_clock_idle_sleep_event(); | |
1da177e4 | 548 | /* Invoke C2 */ |
e9e2cdb4 | 549 | acpi_state_timer_broadcast(pr, cx, 1); |
991528d7 | 550 | acpi_cstate_enter(cx); |
1da177e4 | 551 | /* Get end time (ticks) */ |
cee324b1 | 552 | t2 = inl(acpi_gbl_FADT.xpm_timer_block.address); |
539eb11e | 553 | |
61331168 | 554 | #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86) |
539eb11e | 555 | /* TSC halts in C2, so notify users */ |
ddb25f9a AK |
556 | if (tsc_halts_in_c(ACPI_STATE_C2)) |
557 | mark_tsc_unstable("possible TSC halt in C2"); | |
539eb11e | 558 | #endif |
2aa44d05 IM |
559 | /* Compute time (ticks) that we were actually asleep */ |
560 | sleep_ticks = ticks_elapsed(t1, t2); | |
561 | ||
562 | /* Tell the scheduler how much we idled: */ | |
563 | sched_clock_idle_wakeup_event(sleep_ticks*PM_TIMER_TICK_NS); | |
564 | ||
1da177e4 LT |
565 | /* Re-enable interrupts */ |
566 | local_irq_enable(); | |
2aa44d05 IM |
567 | /* Do not account our idle-switching overhead: */ |
568 | sleep_ticks -= cx->latency_ticks + C2_OVERHEAD; | |
569 | ||
495ab9c0 | 570 | current_thread_info()->status |= TS_POLLING; |
e9e2cdb4 | 571 | acpi_state_timer_broadcast(pr, cx, 0); |
1da177e4 LT |
572 | break; |
573 | ||
574 | case ACPI_STATE_C3: | |
bde6f5f5 | 575 | acpi_unlazy_tlb(smp_processor_id()); |
e17bcb43 TG |
576 | /* |
577 | * Must be done before busmaster disable as we might | |
578 | * need to access HPET ! | |
579 | */ | |
580 | acpi_state_timer_broadcast(pr, cx, 1); | |
18eab855 VP |
581 | /* |
582 | * disable bus master | |
583 | * bm_check implies we need ARB_DIS | |
584 | * !bm_check implies we need cache flush | |
585 | * bm_control implies whether we can do ARB_DIS | |
586 | * | |
587 | * That leaves a case where bm_check is set and bm_control is | |
588 | * not set. In that case we cannot do much, we enter C3 | |
589 | * without doing anything. | |
590 | */ | |
591 | if (pr->flags.bm_check && pr->flags.bm_control) { | |
02df8b93 | 592 | if (atomic_inc_return(&c3_cpu_count) == |
4be44fcd | 593 | num_online_cpus()) { |
02df8b93 VP |
594 | /* |
595 | * All CPUs are trying to go to C3 | |
596 | * Disable bus master arbitration | |
597 | */ | |
d8c71b6d | 598 | acpi_set_register(ACPI_BITREG_ARB_DISABLE, 1); |
02df8b93 | 599 | } |
18eab855 | 600 | } else if (!pr->flags.bm_check) { |
02df8b93 VP |
601 | /* SMP with no shared cache... Invalidate cache */ |
602 | ACPI_FLUSH_CPU_CACHE(); | |
603 | } | |
4be44fcd | 604 | |
1da177e4 | 605 | /* Get start time (ticks) */ |
cee324b1 | 606 | t1 = inl(acpi_gbl_FADT.xpm_timer_block.address); |
1da177e4 | 607 | /* Invoke C3 */ |
2aa44d05 IM |
608 | /* Tell the scheduler that we are going deep-idle: */ |
609 | sched_clock_idle_sleep_event(); | |
991528d7 | 610 | acpi_cstate_enter(cx); |
1da177e4 | 611 | /* Get end time (ticks) */ |
cee324b1 | 612 | t2 = inl(acpi_gbl_FADT.xpm_timer_block.address); |
18eab855 | 613 | if (pr->flags.bm_check && pr->flags.bm_control) { |
02df8b93 VP |
614 | /* Enable bus master arbitration */ |
615 | atomic_dec(&c3_cpu_count); | |
d8c71b6d | 616 | acpi_set_register(ACPI_BITREG_ARB_DISABLE, 0); |
02df8b93 VP |
617 | } |
618 | ||
61331168 | 619 | #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86) |
539eb11e | 620 | /* TSC halts in C3, so notify users */ |
ddb25f9a AK |
621 | if (tsc_halts_in_c(ACPI_STATE_C3)) |
622 | mark_tsc_unstable("TSC halts in C3"); | |
539eb11e | 623 | #endif |
2aa44d05 IM |
624 | /* Compute time (ticks) that we were actually asleep */ |
625 | sleep_ticks = ticks_elapsed(t1, t2); | |
626 | /* Tell the scheduler how much we idled: */ | |
627 | sched_clock_idle_wakeup_event(sleep_ticks*PM_TIMER_TICK_NS); | |
628 | ||
1da177e4 LT |
629 | /* Re-enable interrupts */ |
630 | local_irq_enable(); | |
2aa44d05 IM |
631 | /* Do not account our idle-switching overhead: */ |
632 | sleep_ticks -= cx->latency_ticks + C3_OVERHEAD; | |
633 | ||
495ab9c0 | 634 | current_thread_info()->status |= TS_POLLING; |
e9e2cdb4 | 635 | acpi_state_timer_broadcast(pr, cx, 0); |
1da177e4 LT |
636 | break; |
637 | ||
638 | default: | |
639 | local_irq_enable(); | |
640 | return; | |
641 | } | |
a3c6598f DB |
642 | cx->usage++; |
643 | if ((cx->type != ACPI_STATE_C1) && (sleep_ticks > 0)) | |
644 | cx->time += sleep_ticks; | |
1da177e4 LT |
645 | |
646 | next_state = pr->power.state; | |
647 | ||
1e483969 DSL |
648 | #ifdef CONFIG_HOTPLUG_CPU |
649 | /* Don't do promotion/demotion */ | |
650 | if ((cx->type == ACPI_STATE_C1) && (num_online_cpus() > 1) && | |
cee324b1 | 651 | !pr->flags.has_cst && !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED)) { |
1e483969 DSL |
652 | next_state = cx; |
653 | goto end; | |
654 | } | |
655 | #endif | |
656 | ||
1da177e4 LT |
657 | /* |
658 | * Promotion? | |
659 | * ---------- | |
660 | * Track the number of longs (time asleep is greater than threshold) | |
661 | * and promote when the count threshold is reached. Note that bus | |
662 | * mastering activity may prevent promotions. | |
663 | * Do not promote above max_cstate. | |
664 | */ | |
665 | if (cx->promotion.state && | |
666 | ((cx->promotion.state - pr->power.states) <= max_cstate)) { | |
5c87579e | 667 | if (sleep_ticks > cx->promotion.threshold.ticks && |
f011e2e2 MG |
668 | cx->promotion.state->latency <= |
669 | pm_qos_requirement(PM_QOS_CPU_DMA_LATENCY)) { | |
1da177e4 | 670 | cx->promotion.count++; |
4be44fcd LB |
671 | cx->demotion.count = 0; |
672 | if (cx->promotion.count >= | |
673 | cx->promotion.threshold.count) { | |
1da177e4 | 674 | if (pr->flags.bm_check) { |
4be44fcd LB |
675 | if (! |
676 | (pr->power.bm_activity & cx-> | |
677 | promotion.threshold.bm)) { | |
678 | next_state = | |
679 | cx->promotion.state; | |
1da177e4 LT |
680 | goto end; |
681 | } | |
4be44fcd | 682 | } else { |
1da177e4 LT |
683 | next_state = cx->promotion.state; |
684 | goto end; | |
685 | } | |
686 | } | |
687 | } | |
688 | } | |
689 | ||
690 | /* | |
691 | * Demotion? | |
692 | * --------- | |
693 | * Track the number of shorts (time asleep is less than time threshold) | |
694 | * and demote when the usage threshold is reached. | |
695 | */ | |
696 | if (cx->demotion.state) { | |
697 | if (sleep_ticks < cx->demotion.threshold.ticks) { | |
698 | cx->demotion.count++; | |
699 | cx->promotion.count = 0; | |
700 | if (cx->demotion.count >= cx->demotion.threshold.count) { | |
701 | next_state = cx->demotion.state; | |
702 | goto end; | |
703 | } | |
704 | } | |
705 | } | |
706 | ||
4be44fcd | 707 | end: |
1da177e4 LT |
708 | /* |
709 | * Demote if current state exceeds max_cstate | |
5c87579e | 710 | * or if the latency of the current state is unacceptable |
1da177e4 | 711 | */ |
5c87579e | 712 | if ((pr->power.state - pr->power.states) > max_cstate || |
f011e2e2 MG |
713 | pr->power.state->latency > |
714 | pm_qos_requirement(PM_QOS_CPU_DMA_LATENCY)) { | |
1da177e4 LT |
715 | if (cx->demotion.state) |
716 | next_state = cx->demotion.state; | |
717 | } | |
718 | ||
719 | /* | |
720 | * New Cx State? | |
721 | * ------------- | |
722 | * If we're going to start using a new Cx state we must clean up | |
723 | * from the previous and prepare to use the new. | |
724 | */ | |
725 | if (next_state != pr->power.state) | |
726 | acpi_processor_power_activate(pr, next_state); | |
1da177e4 LT |
727 | } |
728 | ||
4be44fcd | 729 | static int acpi_processor_set_power_policy(struct acpi_processor *pr) |
1da177e4 LT |
730 | { |
731 | unsigned int i; | |
732 | unsigned int state_is_set = 0; | |
733 | struct acpi_processor_cx *lower = NULL; | |
734 | struct acpi_processor_cx *higher = NULL; | |
735 | struct acpi_processor_cx *cx; | |
736 | ||
1da177e4 LT |
737 | |
738 | if (!pr) | |
d550d98d | 739 | return -EINVAL; |
1da177e4 LT |
740 | |
741 | /* | |
742 | * This function sets the default Cx state policy (OS idle handler). | |
743 | * Our scheme is to promote quickly to C2 but more conservatively | |
744 | * to C3. We're favoring C2 for its characteristics of low latency | |
745 | * (quick response), good power savings, and ability to allow bus | |
746 | * mastering activity. Note that the Cx state policy is completely | |
747 | * customizable and can be altered dynamically. | |
748 | */ | |
749 | ||
750 | /* startup state */ | |
4be44fcd | 751 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) { |
1da177e4 LT |
752 | cx = &pr->power.states[i]; |
753 | if (!cx->valid) | |
754 | continue; | |
755 | ||
756 | if (!state_is_set) | |
757 | pr->power.state = cx; | |
758 | state_is_set++; | |
759 | break; | |
4be44fcd | 760 | } |
1da177e4 LT |
761 | |
762 | if (!state_is_set) | |
d550d98d | 763 | return -ENODEV; |
1da177e4 LT |
764 | |
765 | /* demotion */ | |
4be44fcd | 766 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) { |
1da177e4 LT |
767 | cx = &pr->power.states[i]; |
768 | if (!cx->valid) | |
769 | continue; | |
770 | ||
771 | if (lower) { | |
772 | cx->demotion.state = lower; | |
773 | cx->demotion.threshold.ticks = cx->latency_ticks; | |
774 | cx->demotion.threshold.count = 1; | |
775 | if (cx->type == ACPI_STATE_C3) | |
776 | cx->demotion.threshold.bm = bm_history; | |
777 | } | |
778 | ||
779 | lower = cx; | |
780 | } | |
781 | ||
782 | /* promotion */ | |
783 | for (i = (ACPI_PROCESSOR_MAX_POWER - 1); i > 0; i--) { | |
784 | cx = &pr->power.states[i]; | |
785 | if (!cx->valid) | |
786 | continue; | |
787 | ||
788 | if (higher) { | |
4be44fcd | 789 | cx->promotion.state = higher; |
1da177e4 LT |
790 | cx->promotion.threshold.ticks = cx->latency_ticks; |
791 | if (cx->type >= ACPI_STATE_C2) | |
792 | cx->promotion.threshold.count = 4; | |
793 | else | |
794 | cx->promotion.threshold.count = 10; | |
795 | if (higher->type == ACPI_STATE_C3) | |
796 | cx->promotion.threshold.bm = bm_history; | |
797 | } | |
798 | ||
799 | higher = cx; | |
800 | } | |
801 | ||
d550d98d | 802 | return 0; |
1da177e4 | 803 | } |
4f86d3a8 | 804 | #endif /* !CONFIG_CPU_IDLE */ |
1da177e4 | 805 | |
4be44fcd | 806 | static int acpi_processor_get_power_info_fadt(struct acpi_processor *pr) |
1da177e4 | 807 | { |
1da177e4 LT |
808 | |
809 | if (!pr) | |
d550d98d | 810 | return -EINVAL; |
1da177e4 LT |
811 | |
812 | if (!pr->pblk) | |
d550d98d | 813 | return -ENODEV; |
1da177e4 | 814 | |
1da177e4 | 815 | /* if info is obtained from pblk/fadt, type equals state */ |
1da177e4 LT |
816 | pr->power.states[ACPI_STATE_C2].type = ACPI_STATE_C2; |
817 | pr->power.states[ACPI_STATE_C3].type = ACPI_STATE_C3; | |
818 | ||
4c033552 VP |
819 | #ifndef CONFIG_HOTPLUG_CPU |
820 | /* | |
821 | * Check for P_LVL2_UP flag before entering C2 and above on | |
4f86d3a8 | 822 | * an SMP system. |
4c033552 | 823 | */ |
ad71860a | 824 | if ((num_online_cpus() > 1) && |
cee324b1 | 825 | !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED)) |
d550d98d | 826 | return -ENODEV; |
4c033552 VP |
827 | #endif |
828 | ||
1da177e4 LT |
829 | /* determine C2 and C3 address from pblk */ |
830 | pr->power.states[ACPI_STATE_C2].address = pr->pblk + 4; | |
831 | pr->power.states[ACPI_STATE_C3].address = pr->pblk + 5; | |
832 | ||
833 | /* determine latencies from FADT */ | |
cee324b1 AS |
834 | pr->power.states[ACPI_STATE_C2].latency = acpi_gbl_FADT.C2latency; |
835 | pr->power.states[ACPI_STATE_C3].latency = acpi_gbl_FADT.C3latency; | |
1da177e4 LT |
836 | |
837 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
838 | "lvl2[0x%08x] lvl3[0x%08x]\n", | |
839 | pr->power.states[ACPI_STATE_C2].address, | |
840 | pr->power.states[ACPI_STATE_C3].address)); | |
841 | ||
d550d98d | 842 | return 0; |
1da177e4 LT |
843 | } |
844 | ||
991528d7 | 845 | static int acpi_processor_get_power_info_default(struct acpi_processor *pr) |
acf05f4b | 846 | { |
991528d7 VP |
847 | if (!pr->power.states[ACPI_STATE_C1].valid) { |
848 | /* set the first C-State to C1 */ | |
849 | /* all processors need to support C1 */ | |
850 | pr->power.states[ACPI_STATE_C1].type = ACPI_STATE_C1; | |
851 | pr->power.states[ACPI_STATE_C1].valid = 1; | |
0fda6b40 | 852 | pr->power.states[ACPI_STATE_C1].entry_method = ACPI_CSTATE_HALT; |
991528d7 VP |
853 | } |
854 | /* the C0 state only exists as a filler in our array */ | |
acf05f4b | 855 | pr->power.states[ACPI_STATE_C0].valid = 1; |
d550d98d | 856 | return 0; |
acf05f4b VP |
857 | } |
858 | ||
4be44fcd | 859 | static int acpi_processor_get_power_info_cst(struct acpi_processor *pr) |
1da177e4 | 860 | { |
4be44fcd LB |
861 | acpi_status status = 0; |
862 | acpi_integer count; | |
cf824788 | 863 | int current_count; |
4be44fcd LB |
864 | int i; |
865 | struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; | |
866 | union acpi_object *cst; | |
1da177e4 | 867 | |
1da177e4 | 868 | |
1da177e4 | 869 | if (nocst) |
d550d98d | 870 | return -ENODEV; |
1da177e4 | 871 | |
991528d7 | 872 | current_count = 0; |
1da177e4 LT |
873 | |
874 | status = acpi_evaluate_object(pr->handle, "_CST", NULL, &buffer); | |
875 | if (ACPI_FAILURE(status)) { | |
876 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, "No _CST, giving up\n")); | |
d550d98d | 877 | return -ENODEV; |
4be44fcd | 878 | } |
1da177e4 | 879 | |
50dd0969 | 880 | cst = buffer.pointer; |
1da177e4 LT |
881 | |
882 | /* There must be at least 2 elements */ | |
883 | if (!cst || (cst->type != ACPI_TYPE_PACKAGE) || cst->package.count < 2) { | |
6468463a | 884 | printk(KERN_ERR PREFIX "not enough elements in _CST\n"); |
1da177e4 LT |
885 | status = -EFAULT; |
886 | goto end; | |
887 | } | |
888 | ||
889 | count = cst->package.elements[0].integer.value; | |
890 | ||
891 | /* Validate number of power states. */ | |
892 | if (count < 1 || count != cst->package.count - 1) { | |
6468463a | 893 | printk(KERN_ERR PREFIX "count given by _CST is not valid\n"); |
1da177e4 LT |
894 | status = -EFAULT; |
895 | goto end; | |
896 | } | |
897 | ||
1da177e4 LT |
898 | /* Tell driver that at least _CST is supported. */ |
899 | pr->flags.has_cst = 1; | |
900 | ||
901 | for (i = 1; i <= count; i++) { | |
902 | union acpi_object *element; | |
903 | union acpi_object *obj; | |
904 | struct acpi_power_register *reg; | |
905 | struct acpi_processor_cx cx; | |
906 | ||
907 | memset(&cx, 0, sizeof(cx)); | |
908 | ||
50dd0969 | 909 | element = &(cst->package.elements[i]); |
1da177e4 LT |
910 | if (element->type != ACPI_TYPE_PACKAGE) |
911 | continue; | |
912 | ||
913 | if (element->package.count != 4) | |
914 | continue; | |
915 | ||
50dd0969 | 916 | obj = &(element->package.elements[0]); |
1da177e4 LT |
917 | |
918 | if (obj->type != ACPI_TYPE_BUFFER) | |
919 | continue; | |
920 | ||
4be44fcd | 921 | reg = (struct acpi_power_register *)obj->buffer.pointer; |
1da177e4 LT |
922 | |
923 | if (reg->space_id != ACPI_ADR_SPACE_SYSTEM_IO && | |
4be44fcd | 924 | (reg->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE)) |
1da177e4 LT |
925 | continue; |
926 | ||
1da177e4 | 927 | /* There should be an easy way to extract an integer... */ |
50dd0969 | 928 | obj = &(element->package.elements[1]); |
1da177e4 LT |
929 | if (obj->type != ACPI_TYPE_INTEGER) |
930 | continue; | |
931 | ||
932 | cx.type = obj->integer.value; | |
991528d7 VP |
933 | /* |
934 | * Some buggy BIOSes won't list C1 in _CST - | |
935 | * Let acpi_processor_get_power_info_default() handle them later | |
936 | */ | |
937 | if (i == 1 && cx.type != ACPI_STATE_C1) | |
938 | current_count++; | |
939 | ||
940 | cx.address = reg->address; | |
941 | cx.index = current_count + 1; | |
942 | ||
bc71bec9 | 943 | cx.entry_method = ACPI_CSTATE_SYSTEMIO; |
991528d7 VP |
944 | if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE) { |
945 | if (acpi_processor_ffh_cstate_probe | |
946 | (pr->id, &cx, reg) == 0) { | |
bc71bec9 | 947 | cx.entry_method = ACPI_CSTATE_FFH; |
948 | } else if (cx.type == ACPI_STATE_C1) { | |
991528d7 VP |
949 | /* |
950 | * C1 is a special case where FIXED_HARDWARE | |
951 | * can be handled in non-MWAIT way as well. | |
952 | * In that case, save this _CST entry info. | |
991528d7 VP |
953 | * Otherwise, ignore this info and continue. |
954 | */ | |
bc71bec9 | 955 | cx.entry_method = ACPI_CSTATE_HALT; |
4fcb2fcd | 956 | snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI HLT"); |
bc71bec9 | 957 | } else { |
991528d7 VP |
958 | continue; |
959 | } | |
da5e09a1 ZY |
960 | if (cx.type == ACPI_STATE_C1 && |
961 | (idle_halt || idle_nomwait)) { | |
c1e3b377 ZY |
962 | /* |
963 | * In most cases the C1 space_id obtained from | |
964 | * _CST object is FIXED_HARDWARE access mode. | |
965 | * But when the option of idle=halt is added, | |
966 | * the entry_method type should be changed from | |
967 | * CSTATE_FFH to CSTATE_HALT. | |
da5e09a1 ZY |
968 | * When the option of idle=nomwait is added, |
969 | * the C1 entry_method type should be | |
970 | * CSTATE_HALT. | |
c1e3b377 ZY |
971 | */ |
972 | cx.entry_method = ACPI_CSTATE_HALT; | |
973 | snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI HLT"); | |
974 | } | |
4fcb2fcd VP |
975 | } else { |
976 | snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI IOPORT 0x%x", | |
977 | cx.address); | |
991528d7 | 978 | } |
1da177e4 | 979 | |
0fda6b40 VP |
980 | if (cx.type == ACPI_STATE_C1) { |
981 | cx.valid = 1; | |
982 | } | |
4fcb2fcd | 983 | |
50dd0969 | 984 | obj = &(element->package.elements[2]); |
1da177e4 LT |
985 | if (obj->type != ACPI_TYPE_INTEGER) |
986 | continue; | |
987 | ||
988 | cx.latency = obj->integer.value; | |
989 | ||
50dd0969 | 990 | obj = &(element->package.elements[3]); |
1da177e4 LT |
991 | if (obj->type != ACPI_TYPE_INTEGER) |
992 | continue; | |
993 | ||
994 | cx.power = obj->integer.value; | |
995 | ||
cf824788 JM |
996 | current_count++; |
997 | memcpy(&(pr->power.states[current_count]), &cx, sizeof(cx)); | |
998 | ||
999 | /* | |
1000 | * We support total ACPI_PROCESSOR_MAX_POWER - 1 | |
1001 | * (From 1 through ACPI_PROCESSOR_MAX_POWER - 1) | |
1002 | */ | |
1003 | if (current_count >= (ACPI_PROCESSOR_MAX_POWER - 1)) { | |
1004 | printk(KERN_WARNING | |
1005 | "Limiting number of power states to max (%d)\n", | |
1006 | ACPI_PROCESSOR_MAX_POWER); | |
1007 | printk(KERN_WARNING | |
1008 | "Please increase ACPI_PROCESSOR_MAX_POWER if needed.\n"); | |
1009 | break; | |
1010 | } | |
1da177e4 LT |
1011 | } |
1012 | ||
4be44fcd | 1013 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Found %d power states\n", |
cf824788 | 1014 | current_count)); |
1da177e4 LT |
1015 | |
1016 | /* Validate number of power states discovered */ | |
cf824788 | 1017 | if (current_count < 2) |
6d93c648 | 1018 | status = -EFAULT; |
1da177e4 | 1019 | |
4be44fcd | 1020 | end: |
02438d87 | 1021 | kfree(buffer.pointer); |
1da177e4 | 1022 | |
d550d98d | 1023 | return status; |
1da177e4 LT |
1024 | } |
1025 | ||
1da177e4 LT |
1026 | static void acpi_processor_power_verify_c2(struct acpi_processor_cx *cx) |
1027 | { | |
1da177e4 LT |
1028 | |
1029 | if (!cx->address) | |
d550d98d | 1030 | return; |
1da177e4 LT |
1031 | |
1032 | /* | |
1033 | * C2 latency must be less than or equal to 100 | |
1034 | * microseconds. | |
1035 | */ | |
1036 | else if (cx->latency > ACPI_PROCESSOR_MAX_C2_LATENCY) { | |
1037 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
4be44fcd | 1038 | "latency too large [%d]\n", cx->latency)); |
d550d98d | 1039 | return; |
1da177e4 LT |
1040 | } |
1041 | ||
1da177e4 LT |
1042 | /* |
1043 | * Otherwise we've met all of our C2 requirements. | |
1044 | * Normalize the C2 latency to expidite policy | |
1045 | */ | |
1046 | cx->valid = 1; | |
4f86d3a8 LB |
1047 | |
1048 | #ifndef CONFIG_CPU_IDLE | |
1da177e4 | 1049 | cx->latency_ticks = US_TO_PM_TIMER_TICKS(cx->latency); |
4f86d3a8 LB |
1050 | #else |
1051 | cx->latency_ticks = cx->latency; | |
1052 | #endif | |
1da177e4 | 1053 | |
d550d98d | 1054 | return; |
1da177e4 LT |
1055 | } |
1056 | ||
4be44fcd LB |
1057 | static void acpi_processor_power_verify_c3(struct acpi_processor *pr, |
1058 | struct acpi_processor_cx *cx) | |
1da177e4 | 1059 | { |
02df8b93 VP |
1060 | static int bm_check_flag; |
1061 | ||
1da177e4 LT |
1062 | |
1063 | if (!cx->address) | |
d550d98d | 1064 | return; |
1da177e4 LT |
1065 | |
1066 | /* | |
1067 | * C3 latency must be less than or equal to 1000 | |
1068 | * microseconds. | |
1069 | */ | |
1070 | else if (cx->latency > ACPI_PROCESSOR_MAX_C3_LATENCY) { | |
1071 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
4be44fcd | 1072 | "latency too large [%d]\n", cx->latency)); |
d550d98d | 1073 | return; |
1da177e4 LT |
1074 | } |
1075 | ||
1da177e4 LT |
1076 | /* |
1077 | * PIIX4 Erratum #18: We don't support C3 when Type-F (fast) | |
1078 | * DMA transfers are used by any ISA device to avoid livelock. | |
1079 | * Note that we could disable Type-F DMA (as recommended by | |
1080 | * the erratum), but this is known to disrupt certain ISA | |
1081 | * devices thus we take the conservative approach. | |
1082 | */ | |
1083 | else if (errata.piix4.fdma) { | |
1084 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
4be44fcd | 1085 | "C3 not supported on PIIX4 with Type-F DMA\n")); |
d550d98d | 1086 | return; |
1da177e4 LT |
1087 | } |
1088 | ||
02df8b93 VP |
1089 | /* All the logic here assumes flags.bm_check is same across all CPUs */ |
1090 | if (!bm_check_flag) { | |
1091 | /* Determine whether bm_check is needed based on CPU */ | |
1092 | acpi_processor_power_init_bm_check(&(pr->flags), pr->id); | |
1093 | bm_check_flag = pr->flags.bm_check; | |
1094 | } else { | |
1095 | pr->flags.bm_check = bm_check_flag; | |
1096 | } | |
1097 | ||
1098 | if (pr->flags.bm_check) { | |
02df8b93 | 1099 | if (!pr->flags.bm_control) { |
ed3110ef VP |
1100 | if (pr->flags.has_cst != 1) { |
1101 | /* bus mastering control is necessary */ | |
1102 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
1103 | "C3 support requires BM control\n")); | |
1104 | return; | |
1105 | } else { | |
1106 | /* Here we enter C3 without bus mastering */ | |
1107 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
1108 | "C3 support without BM control\n")); | |
1109 | } | |
02df8b93 VP |
1110 | } |
1111 | } else { | |
02df8b93 VP |
1112 | /* |
1113 | * WBINVD should be set in fadt, for C3 state to be | |
1114 | * supported on when bm_check is not required. | |
1115 | */ | |
cee324b1 | 1116 | if (!(acpi_gbl_FADT.flags & ACPI_FADT_WBINVD)) { |
02df8b93 | 1117 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, |
4be44fcd LB |
1118 | "Cache invalidation should work properly" |
1119 | " for C3 to be enabled on SMP systems\n")); | |
d550d98d | 1120 | return; |
02df8b93 | 1121 | } |
d8c71b6d | 1122 | acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 0); |
02df8b93 VP |
1123 | } |
1124 | ||
1da177e4 LT |
1125 | /* |
1126 | * Otherwise we've met all of our C3 requirements. | |
1127 | * Normalize the C3 latency to expidite policy. Enable | |
1128 | * checking of bus mastering status (bm_check) so we can | |
1129 | * use this in our C3 policy | |
1130 | */ | |
1131 | cx->valid = 1; | |
4f86d3a8 LB |
1132 | |
1133 | #ifndef CONFIG_CPU_IDLE | |
1da177e4 | 1134 | cx->latency_ticks = US_TO_PM_TIMER_TICKS(cx->latency); |
4f86d3a8 LB |
1135 | #else |
1136 | cx->latency_ticks = cx->latency; | |
1137 | #endif | |
1da177e4 | 1138 | |
d550d98d | 1139 | return; |
1da177e4 LT |
1140 | } |
1141 | ||
1da177e4 LT |
1142 | static int acpi_processor_power_verify(struct acpi_processor *pr) |
1143 | { | |
1144 | unsigned int i; | |
1145 | unsigned int working = 0; | |
6eb0a0fd | 1146 | |
169a0abb | 1147 | pr->power.timer_broadcast_on_state = INT_MAX; |
6eb0a0fd | 1148 | |
4be44fcd | 1149 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) { |
1da177e4 LT |
1150 | struct acpi_processor_cx *cx = &pr->power.states[i]; |
1151 | ||
1152 | switch (cx->type) { | |
1153 | case ACPI_STATE_C1: | |
1154 | cx->valid = 1; | |
1155 | break; | |
1156 | ||
1157 | case ACPI_STATE_C2: | |
1158 | acpi_processor_power_verify_c2(cx); | |
296d93cd | 1159 | if (cx->valid) |
169a0abb | 1160 | acpi_timer_check_state(i, pr, cx); |
1da177e4 LT |
1161 | break; |
1162 | ||
1163 | case ACPI_STATE_C3: | |
1164 | acpi_processor_power_verify_c3(pr, cx); | |
296d93cd | 1165 | if (cx->valid) |
169a0abb | 1166 | acpi_timer_check_state(i, pr, cx); |
1da177e4 LT |
1167 | break; |
1168 | } | |
1169 | ||
1170 | if (cx->valid) | |
1171 | working++; | |
1172 | } | |
bd663347 | 1173 | |
169a0abb | 1174 | acpi_propagate_timer_broadcast(pr); |
1da177e4 LT |
1175 | |
1176 | return (working); | |
1177 | } | |
1178 | ||
4be44fcd | 1179 | static int acpi_processor_get_power_info(struct acpi_processor *pr) |
1da177e4 LT |
1180 | { |
1181 | unsigned int i; | |
1182 | int result; | |
1183 | ||
1da177e4 LT |
1184 | |
1185 | /* NOTE: the idle thread may not be running while calling | |
1186 | * this function */ | |
1187 | ||
991528d7 VP |
1188 | /* Zero initialize all the C-states info. */ |
1189 | memset(pr->power.states, 0, sizeof(pr->power.states)); | |
1190 | ||
1da177e4 | 1191 | result = acpi_processor_get_power_info_cst(pr); |
6d93c648 | 1192 | if (result == -ENODEV) |
c5a114f1 | 1193 | result = acpi_processor_get_power_info_fadt(pr); |
6d93c648 | 1194 | |
991528d7 VP |
1195 | if (result) |
1196 | return result; | |
1197 | ||
1198 | acpi_processor_get_power_info_default(pr); | |
1199 | ||
cf824788 | 1200 | pr->power.count = acpi_processor_power_verify(pr); |
1da177e4 | 1201 | |
4f86d3a8 | 1202 | #ifndef CONFIG_CPU_IDLE |
1da177e4 LT |
1203 | /* |
1204 | * Set Default Policy | |
1205 | * ------------------ | |
1206 | * Now that we know which states are supported, set the default | |
1207 | * policy. Note that this policy can be changed dynamically | |
1208 | * (e.g. encourage deeper sleeps to conserve battery life when | |
1209 | * not on AC). | |
1210 | */ | |
1211 | result = acpi_processor_set_power_policy(pr); | |
1212 | if (result) | |
d550d98d | 1213 | return result; |
4f86d3a8 | 1214 | #endif |
1da177e4 LT |
1215 | |
1216 | /* | |
1217 | * if one state of type C2 or C3 is available, mark this | |
1218 | * CPU as being "idle manageable" | |
1219 | */ | |
1220 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) { | |
acf05f4b | 1221 | if (pr->power.states[i].valid) { |
1da177e4 | 1222 | pr->power.count = i; |
2203d6ed LT |
1223 | if (pr->power.states[i].type >= ACPI_STATE_C2) |
1224 | pr->flags.power = 1; | |
acf05f4b | 1225 | } |
1da177e4 LT |
1226 | } |
1227 | ||
d550d98d | 1228 | return 0; |
1da177e4 LT |
1229 | } |
1230 | ||
1da177e4 LT |
1231 | static int acpi_processor_power_seq_show(struct seq_file *seq, void *offset) |
1232 | { | |
50dd0969 | 1233 | struct acpi_processor *pr = seq->private; |
4be44fcd | 1234 | unsigned int i; |
1da177e4 | 1235 | |
1da177e4 LT |
1236 | |
1237 | if (!pr) | |
1238 | goto end; | |
1239 | ||
1240 | seq_printf(seq, "active state: C%zd\n" | |
4be44fcd | 1241 | "max_cstate: C%d\n" |
5c87579e AV |
1242 | "bus master activity: %08x\n" |
1243 | "maximum allowed latency: %d usec\n", | |
4be44fcd | 1244 | pr->power.state ? pr->power.state - pr->power.states : 0, |
5c87579e | 1245 | max_cstate, (unsigned)pr->power.bm_activity, |
f011e2e2 | 1246 | pm_qos_requirement(PM_QOS_CPU_DMA_LATENCY)); |
1da177e4 LT |
1247 | |
1248 | seq_puts(seq, "states:\n"); | |
1249 | ||
1250 | for (i = 1; i <= pr->power.count; i++) { | |
1251 | seq_printf(seq, " %cC%d: ", | |
4be44fcd LB |
1252 | (&pr->power.states[i] == |
1253 | pr->power.state ? '*' : ' '), i); | |
1da177e4 LT |
1254 | |
1255 | if (!pr->power.states[i].valid) { | |
1256 | seq_puts(seq, "<not supported>\n"); | |
1257 | continue; | |
1258 | } | |
1259 | ||
1260 | switch (pr->power.states[i].type) { | |
1261 | case ACPI_STATE_C1: | |
1262 | seq_printf(seq, "type[C1] "); | |
1263 | break; | |
1264 | case ACPI_STATE_C2: | |
1265 | seq_printf(seq, "type[C2] "); | |
1266 | break; | |
1267 | case ACPI_STATE_C3: | |
1268 | seq_printf(seq, "type[C3] "); | |
1269 | break; | |
1270 | default: | |
1271 | seq_printf(seq, "type[--] "); | |
1272 | break; | |
1273 | } | |
1274 | ||
1275 | if (pr->power.states[i].promotion.state) | |
1276 | seq_printf(seq, "promotion[C%zd] ", | |
4be44fcd LB |
1277 | (pr->power.states[i].promotion.state - |
1278 | pr->power.states)); | |
1da177e4 LT |
1279 | else |
1280 | seq_puts(seq, "promotion[--] "); | |
1281 | ||
1282 | if (pr->power.states[i].demotion.state) | |
1283 | seq_printf(seq, "demotion[C%zd] ", | |
4be44fcd LB |
1284 | (pr->power.states[i].demotion.state - |
1285 | pr->power.states)); | |
1da177e4 LT |
1286 | else |
1287 | seq_puts(seq, "demotion[--] "); | |
1288 | ||
a3c6598f | 1289 | seq_printf(seq, "latency[%03d] usage[%08d] duration[%020llu]\n", |
4be44fcd | 1290 | pr->power.states[i].latency, |
a3c6598f | 1291 | pr->power.states[i].usage, |
b0b7eaaf | 1292 | (unsigned long long)pr->power.states[i].time); |
1da177e4 LT |
1293 | } |
1294 | ||
4be44fcd | 1295 | end: |
d550d98d | 1296 | return 0; |
1da177e4 LT |
1297 | } |
1298 | ||
1299 | static int acpi_processor_power_open_fs(struct inode *inode, struct file *file) | |
1300 | { | |
1301 | return single_open(file, acpi_processor_power_seq_show, | |
4be44fcd | 1302 | PDE(inode)->data); |
1da177e4 LT |
1303 | } |
1304 | ||
d7508032 | 1305 | static const struct file_operations acpi_processor_power_fops = { |
cf7acfab | 1306 | .owner = THIS_MODULE, |
4be44fcd LB |
1307 | .open = acpi_processor_power_open_fs, |
1308 | .read = seq_read, | |
1309 | .llseek = seq_lseek, | |
1310 | .release = single_release, | |
1da177e4 LT |
1311 | }; |
1312 | ||
4f86d3a8 LB |
1313 | #ifndef CONFIG_CPU_IDLE |
1314 | ||
1315 | int acpi_processor_cst_has_changed(struct acpi_processor *pr) | |
1316 | { | |
1317 | int result = 0; | |
1318 | ||
36a91358 VP |
1319 | if (boot_option_idle_override) |
1320 | return 0; | |
4f86d3a8 LB |
1321 | |
1322 | if (!pr) | |
1323 | return -EINVAL; | |
1324 | ||
1325 | if (nocst) { | |
1326 | return -ENODEV; | |
1327 | } | |
1328 | ||
1329 | if (!pr->flags.power_setup_done) | |
1330 | return -ENODEV; | |
1331 | ||
1332 | /* Fall back to the default idle loop */ | |
1333 | pm_idle = pm_idle_save; | |
1334 | synchronize_sched(); /* Relies on interrupts forcing exit from idle. */ | |
1335 | ||
1336 | pr->flags.power = 0; | |
1337 | result = acpi_processor_get_power_info(pr); | |
1338 | if ((pr->flags.power == 1) && (pr->flags.power_setup_done)) | |
1339 | pm_idle = acpi_processor_idle; | |
1340 | ||
1341 | return result; | |
1342 | } | |
1343 | ||
1fec74a9 | 1344 | #ifdef CONFIG_SMP |
5c87579e AV |
1345 | static void smp_callback(void *v) |
1346 | { | |
1347 | /* we already woke the CPU up, nothing more to do */ | |
1348 | } | |
1349 | ||
1350 | /* | |
1351 | * This function gets called when a part of the kernel has a new latency | |
1352 | * requirement. This means we need to get all processors out of their C-state, | |
1353 | * and then recalculate a new suitable C-state. Just do a cross-cpu IPI; that | |
1354 | * wakes them all right up. | |
1355 | */ | |
1356 | static int acpi_processor_latency_notify(struct notifier_block *b, | |
1357 | unsigned long l, void *v) | |
1358 | { | |
8691e5a8 | 1359 | smp_call_function(smp_callback, NULL, 1); |
5c87579e AV |
1360 | return NOTIFY_OK; |
1361 | } | |
1362 | ||
1363 | static struct notifier_block acpi_processor_latency_notifier = { | |
1364 | .notifier_call = acpi_processor_latency_notify, | |
1365 | }; | |
4f86d3a8 LB |
1366 | |
1367 | #endif | |
1368 | ||
1369 | #else /* CONFIG_CPU_IDLE */ | |
1370 | ||
1371 | /** | |
1372 | * acpi_idle_bm_check - checks if bus master activity was detected | |
1373 | */ | |
1374 | static int acpi_idle_bm_check(void) | |
1375 | { | |
1376 | u32 bm_status = 0; | |
1377 | ||
1378 | acpi_get_register(ACPI_BITREG_BUS_MASTER_STATUS, &bm_status); | |
1379 | if (bm_status) | |
1380 | acpi_set_register(ACPI_BITREG_BUS_MASTER_STATUS, 1); | |
1381 | /* | |
1382 | * PIIX4 Erratum #18: Note that BM_STS doesn't always reflect | |
1383 | * the true state of bus mastering activity; forcing us to | |
1384 | * manually check the BMIDEA bit of each IDE channel. | |
1385 | */ | |
1386 | else if (errata.piix4.bmisx) { | |
1387 | if ((inb_p(errata.piix4.bmisx + 0x02) & 0x01) | |
1388 | || (inb_p(errata.piix4.bmisx + 0x0A) & 0x01)) | |
1389 | bm_status = 1; | |
1390 | } | |
1391 | return bm_status; | |
1392 | } | |
1393 | ||
1394 | /** | |
1395 | * acpi_idle_update_bm_rld - updates the BM_RLD bit depending on target state | |
1396 | * @pr: the processor | |
1397 | * @target: the new target state | |
1398 | */ | |
1399 | static inline void acpi_idle_update_bm_rld(struct acpi_processor *pr, | |
1400 | struct acpi_processor_cx *target) | |
1401 | { | |
1402 | if (pr->flags.bm_rld_set && target->type != ACPI_STATE_C3) { | |
1403 | acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 0); | |
1404 | pr->flags.bm_rld_set = 0; | |
1405 | } | |
1406 | ||
1407 | if (!pr->flags.bm_rld_set && target->type == ACPI_STATE_C3) { | |
1408 | acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 1); | |
1409 | pr->flags.bm_rld_set = 1; | |
1410 | } | |
1411 | } | |
1412 | ||
1413 | /** | |
1414 | * acpi_idle_do_entry - a helper function that does C2 and C3 type entry | |
1415 | * @cx: cstate data | |
bc71bec9 | 1416 | * |
1417 | * Caller disables interrupt before call and enables interrupt after return. | |
4f86d3a8 LB |
1418 | */ |
1419 | static inline void acpi_idle_do_entry(struct acpi_processor_cx *cx) | |
1420 | { | |
bc71bec9 | 1421 | if (cx->entry_method == ACPI_CSTATE_FFH) { |
4f86d3a8 LB |
1422 | /* Call into architectural FFH based C-state */ |
1423 | acpi_processor_ffh_cstate_enter(cx); | |
bc71bec9 | 1424 | } else if (cx->entry_method == ACPI_CSTATE_HALT) { |
1425 | acpi_safe_halt(); | |
4f86d3a8 LB |
1426 | } else { |
1427 | int unused; | |
1428 | /* IO port based C-state */ | |
1429 | inb(cx->address); | |
1430 | /* Dummy wait op - must do something useless after P_LVL2 read | |
1431 | because chipsets cannot guarantee that STPCLK# signal | |
1432 | gets asserted in time to freeze execution properly. */ | |
1433 | unused = inl(acpi_gbl_FADT.xpm_timer_block.address); | |
1434 | } | |
1435 | } | |
1436 | ||
1437 | /** | |
1438 | * acpi_idle_enter_c1 - enters an ACPI C1 state-type | |
1439 | * @dev: the target CPU | |
1440 | * @state: the state data | |
1441 | * | |
1442 | * This is equivalent to the HALT instruction. | |
1443 | */ | |
1444 | static int acpi_idle_enter_c1(struct cpuidle_device *dev, | |
1445 | struct cpuidle_state *state) | |
1446 | { | |
9b12e18c | 1447 | u32 t1, t2; |
4f86d3a8 LB |
1448 | struct acpi_processor *pr; |
1449 | struct acpi_processor_cx *cx = cpuidle_get_statedata(state); | |
9b12e18c | 1450 | |
706546d0 | 1451 | pr = __get_cpu_var(processors); |
4f86d3a8 LB |
1452 | |
1453 | if (unlikely(!pr)) | |
1454 | return 0; | |
1455 | ||
2e906655 | 1456 | local_irq_disable(); |
b077fbad VP |
1457 | |
1458 | /* Do not access any ACPI IO ports in suspend path */ | |
1459 | if (acpi_idle_suspend) { | |
1460 | acpi_safe_halt(); | |
1461 | local_irq_enable(); | |
1462 | return 0; | |
1463 | } | |
1464 | ||
4f86d3a8 LB |
1465 | if (pr->flags.bm_check) |
1466 | acpi_idle_update_bm_rld(pr, cx); | |
1467 | ||
9b12e18c | 1468 | t1 = inl(acpi_gbl_FADT.xpm_timer_block.address); |
bc71bec9 | 1469 | acpi_idle_do_entry(cx); |
9b12e18c | 1470 | t2 = inl(acpi_gbl_FADT.xpm_timer_block.address); |
4f86d3a8 | 1471 | |
2e906655 | 1472 | local_irq_enable(); |
4f86d3a8 LB |
1473 | cx->usage++; |
1474 | ||
9b12e18c | 1475 | return ticks_elapsed_in_us(t1, t2); |
4f86d3a8 LB |
1476 | } |
1477 | ||
1478 | /** | |
1479 | * acpi_idle_enter_simple - enters an ACPI state without BM handling | |
1480 | * @dev: the target CPU | |
1481 | * @state: the state data | |
1482 | */ | |
1483 | static int acpi_idle_enter_simple(struct cpuidle_device *dev, | |
1484 | struct cpuidle_state *state) | |
1485 | { | |
1486 | struct acpi_processor *pr; | |
1487 | struct acpi_processor_cx *cx = cpuidle_get_statedata(state); | |
1488 | u32 t1, t2; | |
50629118 VP |
1489 | int sleep_ticks = 0; |
1490 | ||
706546d0 | 1491 | pr = __get_cpu_var(processors); |
4f86d3a8 LB |
1492 | |
1493 | if (unlikely(!pr)) | |
1494 | return 0; | |
1495 | ||
e196441b LB |
1496 | if (acpi_idle_suspend) |
1497 | return(acpi_idle_enter_c1(dev, state)); | |
1498 | ||
4f86d3a8 LB |
1499 | local_irq_disable(); |
1500 | current_thread_info()->status &= ~TS_POLLING; | |
1501 | /* | |
1502 | * TS_POLLING-cleared state must be visible before we test | |
1503 | * NEED_RESCHED: | |
1504 | */ | |
1505 | smp_mb(); | |
1506 | ||
1507 | if (unlikely(need_resched())) { | |
1508 | current_thread_info()->status |= TS_POLLING; | |
1509 | local_irq_enable(); | |
1510 | return 0; | |
1511 | } | |
1512 | ||
e17bcb43 TG |
1513 | /* |
1514 | * Must be done before busmaster disable as we might need to | |
1515 | * access HPET ! | |
1516 | */ | |
1517 | acpi_state_timer_broadcast(pr, cx, 1); | |
1518 | ||
1519 | if (pr->flags.bm_check) | |
1520 | acpi_idle_update_bm_rld(pr, cx); | |
1521 | ||
4f86d3a8 LB |
1522 | if (cx->type == ACPI_STATE_C3) |
1523 | ACPI_FLUSH_CPU_CACHE(); | |
1524 | ||
1525 | t1 = inl(acpi_gbl_FADT.xpm_timer_block.address); | |
50629118 VP |
1526 | /* Tell the scheduler that we are going deep-idle: */ |
1527 | sched_clock_idle_sleep_event(); | |
4f86d3a8 LB |
1528 | acpi_idle_do_entry(cx); |
1529 | t2 = inl(acpi_gbl_FADT.xpm_timer_block.address); | |
1530 | ||
61331168 | 1531 | #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86) |
4f86d3a8 | 1532 | /* TSC could halt in idle, so notify users */ |
ddb25f9a AK |
1533 | if (tsc_halts_in_c(cx->type)) |
1534 | mark_tsc_unstable("TSC halts in idle");; | |
4f86d3a8 | 1535 | #endif |
50629118 VP |
1536 | sleep_ticks = ticks_elapsed(t1, t2); |
1537 | ||
1538 | /* Tell the scheduler how much we idled: */ | |
1539 | sched_clock_idle_wakeup_event(sleep_ticks*PM_TIMER_TICK_NS); | |
4f86d3a8 LB |
1540 | |
1541 | local_irq_enable(); | |
1542 | current_thread_info()->status |= TS_POLLING; | |
1543 | ||
1544 | cx->usage++; | |
1545 | ||
1546 | acpi_state_timer_broadcast(pr, cx, 0); | |
50629118 | 1547 | cx->time += sleep_ticks; |
4f86d3a8 LB |
1548 | return ticks_elapsed_in_us(t1, t2); |
1549 | } | |
1550 | ||
1551 | static int c3_cpu_count; | |
1552 | static DEFINE_SPINLOCK(c3_lock); | |
1553 | ||
1554 | /** | |
1555 | * acpi_idle_enter_bm - enters C3 with proper BM handling | |
1556 | * @dev: the target CPU | |
1557 | * @state: the state data | |
1558 | * | |
1559 | * If BM is detected, the deepest non-C3 idle state is entered instead. | |
1560 | */ | |
1561 | static int acpi_idle_enter_bm(struct cpuidle_device *dev, | |
1562 | struct cpuidle_state *state) | |
1563 | { | |
1564 | struct acpi_processor *pr; | |
1565 | struct acpi_processor_cx *cx = cpuidle_get_statedata(state); | |
1566 | u32 t1, t2; | |
50629118 VP |
1567 | int sleep_ticks = 0; |
1568 | ||
706546d0 | 1569 | pr = __get_cpu_var(processors); |
4f86d3a8 LB |
1570 | |
1571 | if (unlikely(!pr)) | |
1572 | return 0; | |
1573 | ||
e196441b LB |
1574 | if (acpi_idle_suspend) |
1575 | return(acpi_idle_enter_c1(dev, state)); | |
1576 | ||
ddc081a1 VP |
1577 | if (acpi_idle_bm_check()) { |
1578 | if (dev->safe_state) { | |
1579 | return dev->safe_state->enter(dev, dev->safe_state); | |
1580 | } else { | |
2e906655 | 1581 | local_irq_disable(); |
ddc081a1 | 1582 | acpi_safe_halt(); |
2e906655 | 1583 | local_irq_enable(); |
ddc081a1 VP |
1584 | return 0; |
1585 | } | |
1586 | } | |
1587 | ||
4f86d3a8 LB |
1588 | local_irq_disable(); |
1589 | current_thread_info()->status &= ~TS_POLLING; | |
1590 | /* | |
1591 | * TS_POLLING-cleared state must be visible before we test | |
1592 | * NEED_RESCHED: | |
1593 | */ | |
1594 | smp_mb(); | |
1595 | ||
1596 | if (unlikely(need_resched())) { | |
1597 | current_thread_info()->status |= TS_POLLING; | |
1598 | local_irq_enable(); | |
1599 | return 0; | |
1600 | } | |
1601 | ||
996520c1 VP |
1602 | acpi_unlazy_tlb(smp_processor_id()); |
1603 | ||
50629118 VP |
1604 | /* Tell the scheduler that we are going deep-idle: */ |
1605 | sched_clock_idle_sleep_event(); | |
4f86d3a8 LB |
1606 | /* |
1607 | * Must be done before busmaster disable as we might need to | |
1608 | * access HPET ! | |
1609 | */ | |
1610 | acpi_state_timer_broadcast(pr, cx, 1); | |
1611 | ||
ddc081a1 | 1612 | acpi_idle_update_bm_rld(pr, cx); |
4f86d3a8 | 1613 | |
ddc081a1 VP |
1614 | /* |
1615 | * disable bus master | |
1616 | * bm_check implies we need ARB_DIS | |
1617 | * !bm_check implies we need cache flush | |
1618 | * bm_control implies whether we can do ARB_DIS | |
1619 | * | |
1620 | * That leaves a case where bm_check is set and bm_control is | |
1621 | * not set. In that case we cannot do much, we enter C3 | |
1622 | * without doing anything. | |
1623 | */ | |
1624 | if (pr->flags.bm_check && pr->flags.bm_control) { | |
4f86d3a8 LB |
1625 | spin_lock(&c3_lock); |
1626 | c3_cpu_count++; | |
1627 | /* Disable bus master arbitration when all CPUs are in C3 */ | |
1628 | if (c3_cpu_count == num_online_cpus()) | |
1629 | acpi_set_register(ACPI_BITREG_ARB_DISABLE, 1); | |
1630 | spin_unlock(&c3_lock); | |
ddc081a1 VP |
1631 | } else if (!pr->flags.bm_check) { |
1632 | ACPI_FLUSH_CPU_CACHE(); | |
1633 | } | |
4f86d3a8 | 1634 | |
ddc081a1 VP |
1635 | t1 = inl(acpi_gbl_FADT.xpm_timer_block.address); |
1636 | acpi_idle_do_entry(cx); | |
1637 | t2 = inl(acpi_gbl_FADT.xpm_timer_block.address); | |
4f86d3a8 | 1638 | |
ddc081a1 VP |
1639 | /* Re-enable bus master arbitration */ |
1640 | if (pr->flags.bm_check && pr->flags.bm_control) { | |
4f86d3a8 | 1641 | spin_lock(&c3_lock); |
ddc081a1 | 1642 | acpi_set_register(ACPI_BITREG_ARB_DISABLE, 0); |
4f86d3a8 LB |
1643 | c3_cpu_count--; |
1644 | spin_unlock(&c3_lock); | |
1645 | } | |
1646 | ||
61331168 | 1647 | #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86) |
4f86d3a8 | 1648 | /* TSC could halt in idle, so notify users */ |
ddb25f9a AK |
1649 | if (tsc_halts_in_c(ACPI_STATE_C3)) |
1650 | mark_tsc_unstable("TSC halts in idle"); | |
4f86d3a8 | 1651 | #endif |
50629118 VP |
1652 | sleep_ticks = ticks_elapsed(t1, t2); |
1653 | /* Tell the scheduler how much we idled: */ | |
1654 | sched_clock_idle_wakeup_event(sleep_ticks*PM_TIMER_TICK_NS); | |
4f86d3a8 LB |
1655 | |
1656 | local_irq_enable(); | |
1657 | current_thread_info()->status |= TS_POLLING; | |
1658 | ||
1659 | cx->usage++; | |
1660 | ||
1661 | acpi_state_timer_broadcast(pr, cx, 0); | |
50629118 | 1662 | cx->time += sleep_ticks; |
4f86d3a8 LB |
1663 | return ticks_elapsed_in_us(t1, t2); |
1664 | } | |
1665 | ||
1666 | struct cpuidle_driver acpi_idle_driver = { | |
1667 | .name = "acpi_idle", | |
1668 | .owner = THIS_MODULE, | |
1669 | }; | |
1670 | ||
1671 | /** | |
1672 | * acpi_processor_setup_cpuidle - prepares and configures CPUIDLE | |
1673 | * @pr: the ACPI processor | |
1674 | */ | |
1675 | static int acpi_processor_setup_cpuidle(struct acpi_processor *pr) | |
1676 | { | |
9a0b8415 | 1677 | int i, count = CPUIDLE_DRIVER_STATE_START; |
4f86d3a8 LB |
1678 | struct acpi_processor_cx *cx; |
1679 | struct cpuidle_state *state; | |
1680 | struct cpuidle_device *dev = &pr->power.dev; | |
1681 | ||
1682 | if (!pr->flags.power_setup_done) | |
1683 | return -EINVAL; | |
1684 | ||
1685 | if (pr->flags.power == 0) { | |
1686 | return -EINVAL; | |
1687 | } | |
1688 | ||
dcb84f33 | 1689 | dev->cpu = pr->id; |
4fcb2fcd VP |
1690 | for (i = 0; i < CPUIDLE_STATE_MAX; i++) { |
1691 | dev->states[i].name[0] = '\0'; | |
1692 | dev->states[i].desc[0] = '\0'; | |
1693 | } | |
1694 | ||
4f86d3a8 LB |
1695 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER && i <= max_cstate; i++) { |
1696 | cx = &pr->power.states[i]; | |
1697 | state = &dev->states[count]; | |
1698 | ||
1699 | if (!cx->valid) | |
1700 | continue; | |
1701 | ||
1702 | #ifdef CONFIG_HOTPLUG_CPU | |
1703 | if ((cx->type != ACPI_STATE_C1) && (num_online_cpus() > 1) && | |
1704 | !pr->flags.has_cst && | |
1705 | !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED)) | |
1706 | continue; | |
1fec74a9 | 1707 | #endif |
4f86d3a8 LB |
1708 | cpuidle_set_statedata(state, cx); |
1709 | ||
1710 | snprintf(state->name, CPUIDLE_NAME_LEN, "C%d", i); | |
4fcb2fcd | 1711 | strncpy(state->desc, cx->desc, CPUIDLE_DESC_LEN); |
4f86d3a8 | 1712 | state->exit_latency = cx->latency; |
4963f620 | 1713 | state->target_residency = cx->latency * latency_factor; |
4f86d3a8 LB |
1714 | state->power_usage = cx->power; |
1715 | ||
1716 | state->flags = 0; | |
1717 | switch (cx->type) { | |
1718 | case ACPI_STATE_C1: | |
1719 | state->flags |= CPUIDLE_FLAG_SHALLOW; | |
8e92b660 VP |
1720 | if (cx->entry_method == ACPI_CSTATE_FFH) |
1721 | state->flags |= CPUIDLE_FLAG_TIME_VALID; | |
1722 | ||
4f86d3a8 | 1723 | state->enter = acpi_idle_enter_c1; |
ddc081a1 | 1724 | dev->safe_state = state; |
4f86d3a8 LB |
1725 | break; |
1726 | ||
1727 | case ACPI_STATE_C2: | |
1728 | state->flags |= CPUIDLE_FLAG_BALANCED; | |
1729 | state->flags |= CPUIDLE_FLAG_TIME_VALID; | |
1730 | state->enter = acpi_idle_enter_simple; | |
ddc081a1 | 1731 | dev->safe_state = state; |
4f86d3a8 LB |
1732 | break; |
1733 | ||
1734 | case ACPI_STATE_C3: | |
1735 | state->flags |= CPUIDLE_FLAG_DEEP; | |
1736 | state->flags |= CPUIDLE_FLAG_TIME_VALID; | |
1737 | state->flags |= CPUIDLE_FLAG_CHECK_BM; | |
1738 | state->enter = pr->flags.bm_check ? | |
1739 | acpi_idle_enter_bm : | |
1740 | acpi_idle_enter_simple; | |
1741 | break; | |
1742 | } | |
1743 | ||
1744 | count++; | |
9a0b8415 | 1745 | if (count == CPUIDLE_STATE_MAX) |
1746 | break; | |
4f86d3a8 LB |
1747 | } |
1748 | ||
1749 | dev->state_count = count; | |
1750 | ||
1751 | if (!count) | |
1752 | return -EINVAL; | |
1753 | ||
4f86d3a8 LB |
1754 | return 0; |
1755 | } | |
1756 | ||
1757 | int acpi_processor_cst_has_changed(struct acpi_processor *pr) | |
1758 | { | |
dcb84f33 | 1759 | int ret = 0; |
4f86d3a8 | 1760 | |
36a91358 VP |
1761 | if (boot_option_idle_override) |
1762 | return 0; | |
1763 | ||
4f86d3a8 LB |
1764 | if (!pr) |
1765 | return -EINVAL; | |
1766 | ||
1767 | if (nocst) { | |
1768 | return -ENODEV; | |
1769 | } | |
1770 | ||
1771 | if (!pr->flags.power_setup_done) | |
1772 | return -ENODEV; | |
1773 | ||
1774 | cpuidle_pause_and_lock(); | |
1775 | cpuidle_disable_device(&pr->power.dev); | |
1776 | acpi_processor_get_power_info(pr); | |
dcb84f33 VP |
1777 | if (pr->flags.power) { |
1778 | acpi_processor_setup_cpuidle(pr); | |
1779 | ret = cpuidle_enable_device(&pr->power.dev); | |
1780 | } | |
4f86d3a8 LB |
1781 | cpuidle_resume_and_unlock(); |
1782 | ||
1783 | return ret; | |
1784 | } | |
1785 | ||
1786 | #endif /* CONFIG_CPU_IDLE */ | |
5c87579e | 1787 | |
7af8b660 | 1788 | int __cpuinit acpi_processor_power_init(struct acpi_processor *pr, |
4be44fcd | 1789 | struct acpi_device *device) |
1da177e4 | 1790 | { |
4be44fcd | 1791 | acpi_status status = 0; |
b6835052 | 1792 | static int first_run; |
4be44fcd | 1793 | struct proc_dir_entry *entry = NULL; |
1da177e4 LT |
1794 | unsigned int i; |
1795 | ||
36a91358 VP |
1796 | if (boot_option_idle_override) |
1797 | return 0; | |
1da177e4 LT |
1798 | |
1799 | if (!first_run) { | |
c1e3b377 ZY |
1800 | if (idle_halt) { |
1801 | /* | |
1802 | * When the boot option of "idle=halt" is added, halt | |
1803 | * is used for CPU IDLE. | |
1804 | * In such case C2/C3 is meaningless. So the max_cstate | |
1805 | * is set to one. | |
1806 | */ | |
1807 | max_cstate = 1; | |
1808 | } | |
1da177e4 | 1809 | dmi_check_system(processor_power_dmi_table); |
c1c30634 | 1810 | max_cstate = acpi_processor_cstate_check(max_cstate); |
1da177e4 | 1811 | if (max_cstate < ACPI_C_STATES_MAX) |
4be44fcd LB |
1812 | printk(KERN_NOTICE |
1813 | "ACPI: processor limited to max C-state %d\n", | |
1814 | max_cstate); | |
1da177e4 | 1815 | first_run++; |
f011e2e2 MG |
1816 | #if !defined(CONFIG_CPU_IDLE) && defined(CONFIG_SMP) |
1817 | pm_qos_add_notifier(PM_QOS_CPU_DMA_LATENCY, | |
1818 | &acpi_processor_latency_notifier); | |
1fec74a9 | 1819 | #endif |
1da177e4 LT |
1820 | } |
1821 | ||
02df8b93 | 1822 | if (!pr) |
d550d98d | 1823 | return -EINVAL; |
02df8b93 | 1824 | |
cee324b1 | 1825 | if (acpi_gbl_FADT.cst_control && !nocst) { |
4be44fcd | 1826 | status = |
cee324b1 | 1827 | acpi_os_write_port(acpi_gbl_FADT.smi_command, acpi_gbl_FADT.cst_control, 8); |
1da177e4 | 1828 | if (ACPI_FAILURE(status)) { |
a6fc6720 TR |
1829 | ACPI_EXCEPTION((AE_INFO, status, |
1830 | "Notifying BIOS of _CST ability failed")); | |
1da177e4 LT |
1831 | } |
1832 | } | |
1833 | ||
1834 | acpi_processor_get_power_info(pr); | |
4f86d3a8 | 1835 | pr->flags.power_setup_done = 1; |
1da177e4 LT |
1836 | |
1837 | /* | |
1838 | * Install the idle handler if processor power management is supported. | |
1839 | * Note that we use previously set idle handler will be used on | |
1840 | * platforms that only support C1. | |
1841 | */ | |
36a91358 | 1842 | if (pr->flags.power) { |
4f86d3a8 LB |
1843 | #ifdef CONFIG_CPU_IDLE |
1844 | acpi_processor_setup_cpuidle(pr); | |
4f86d3a8 LB |
1845 | if (cpuidle_register_device(&pr->power.dev)) |
1846 | return -EIO; | |
1847 | #endif | |
1848 | ||
1da177e4 LT |
1849 | printk(KERN_INFO PREFIX "CPU%d (power states:", pr->id); |
1850 | for (i = 1; i <= pr->power.count; i++) | |
1851 | if (pr->power.states[i].valid) | |
4be44fcd LB |
1852 | printk(" C%d[C%d]", i, |
1853 | pr->power.states[i].type); | |
1da177e4 LT |
1854 | printk(")\n"); |
1855 | ||
4f86d3a8 | 1856 | #ifndef CONFIG_CPU_IDLE |
1da177e4 LT |
1857 | if (pr->id == 0) { |
1858 | pm_idle_save = pm_idle; | |
1859 | pm_idle = acpi_processor_idle; | |
1860 | } | |
4f86d3a8 | 1861 | #endif |
1da177e4 LT |
1862 | } |
1863 | ||
1864 | /* 'power' [R] */ | |
cf7acfab DL |
1865 | entry = proc_create_data(ACPI_PROCESSOR_FILE_POWER, |
1866 | S_IRUGO, acpi_device_dir(device), | |
1867 | &acpi_processor_power_fops, | |
1868 | acpi_driver_data(device)); | |
1da177e4 | 1869 | if (!entry) |
a6fc6720 | 1870 | return -EIO; |
d550d98d | 1871 | return 0; |
1da177e4 LT |
1872 | } |
1873 | ||
4be44fcd LB |
1874 | int acpi_processor_power_exit(struct acpi_processor *pr, |
1875 | struct acpi_device *device) | |
1da177e4 | 1876 | { |
36a91358 VP |
1877 | if (boot_option_idle_override) |
1878 | return 0; | |
1879 | ||
4f86d3a8 | 1880 | #ifdef CONFIG_CPU_IDLE |
dcb84f33 | 1881 | cpuidle_unregister_device(&pr->power.dev); |
4f86d3a8 | 1882 | #endif |
1da177e4 LT |
1883 | pr->flags.power_setup_done = 0; |
1884 | ||
1885 | if (acpi_device_dir(device)) | |
4be44fcd LB |
1886 | remove_proc_entry(ACPI_PROCESSOR_FILE_POWER, |
1887 | acpi_device_dir(device)); | |
1da177e4 | 1888 | |
4f86d3a8 LB |
1889 | #ifndef CONFIG_CPU_IDLE |
1890 | ||
1da177e4 LT |
1891 | /* Unregister the idle handler when processor #0 is removed. */ |
1892 | if (pr->id == 0) { | |
1893 | pm_idle = pm_idle_save; | |
1894 | ||
1895 | /* | |
1896 | * We are about to unload the current idle thread pm callback | |
1897 | * (pm_idle), Wait for all processors to update cached/local | |
1898 | * copies of pm_idle before proceeding. | |
1899 | */ | |
1900 | cpu_idle_wait(); | |
1fec74a9 | 1901 | #ifdef CONFIG_SMP |
f011e2e2 MG |
1902 | pm_qos_remove_notifier(PM_QOS_CPU_DMA_LATENCY, |
1903 | &acpi_processor_latency_notifier); | |
1fec74a9 | 1904 | #endif |
1da177e4 | 1905 | } |
4f86d3a8 | 1906 | #endif |
1da177e4 | 1907 | |
d550d98d | 1908 | return 0; |
1da177e4 | 1909 | } |