Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * processor_idle - idle state submodule to the ACPI processor driver | |
3 | * | |
4 | * Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com> | |
5 | * Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com> | |
c5ab81ca | 6 | * Copyright (C) 2004, 2005 Dominik Brodowski <linux@brodo.de> |
1da177e4 LT |
7 | * Copyright (C) 2004 Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> |
8 | * - Added processor hotplug support | |
02df8b93 VP |
9 | * Copyright (C) 2005 Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> |
10 | * - Added support for C3 on SMP | |
1da177e4 LT |
11 | * |
12 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or modify | |
15 | * it under the terms of the GNU General Public License as published by | |
16 | * the Free Software Foundation; either version 2 of the License, or (at | |
17 | * your option) any later version. | |
18 | * | |
19 | * This program is distributed in the hope that it will be useful, but | |
20 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
22 | * General Public License for more details. | |
23 | * | |
24 | * You should have received a copy of the GNU General Public License along | |
25 | * with this program; if not, write to the Free Software Foundation, Inc., | |
26 | * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. | |
27 | * | |
28 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
29 | */ | |
30 | ||
31 | #include <linux/kernel.h> | |
32 | #include <linux/module.h> | |
33 | #include <linux/init.h> | |
34 | #include <linux/cpufreq.h> | |
35 | #include <linux/proc_fs.h> | |
36 | #include <linux/seq_file.h> | |
37 | #include <linux/acpi.h> | |
38 | #include <linux/dmi.h> | |
39 | #include <linux/moduleparam.h> | |
4e57b681 | 40 | #include <linux/sched.h> /* need_resched() */ |
f011e2e2 | 41 | #include <linux/pm_qos_params.h> |
e9e2cdb4 | 42 | #include <linux/clockchips.h> |
4f86d3a8 | 43 | #include <linux/cpuidle.h> |
ba84be23 | 44 | #include <linux/irqflags.h> |
1da177e4 | 45 | |
3434933b TG |
46 | /* |
47 | * Include the apic definitions for x86 to have the APIC timer related defines | |
48 | * available also for UP (on SMP it gets magically included via linux/smp.h). | |
49 | * asm/acpi.h is not an option, as it would require more include magic. Also | |
50 | * creating an empty asm-ia64/apic.h would just trade pest vs. cholera. | |
51 | */ | |
52 | #ifdef CONFIG_X86 | |
53 | #include <asm/apic.h> | |
54 | #endif | |
55 | ||
1da177e4 LT |
56 | #include <asm/io.h> |
57 | #include <asm/uaccess.h> | |
58 | ||
59 | #include <acpi/acpi_bus.h> | |
60 | #include <acpi/processor.h> | |
c1e3b377 | 61 | #include <asm/processor.h> |
1da177e4 | 62 | |
1da177e4 | 63 | #define ACPI_PROCESSOR_CLASS "processor" |
1da177e4 | 64 | #define _COMPONENT ACPI_PROCESSOR_COMPONENT |
f52fd66d | 65 | ACPI_MODULE_NAME("processor_idle"); |
1da177e4 | 66 | #define ACPI_PROCESSOR_FILE_POWER "power" |
2aa44d05 | 67 | #define PM_TIMER_TICK_NS (1000000000ULL/PM_TIMER_FREQUENCY) |
4f86d3a8 LB |
68 | #define C2_OVERHEAD 1 /* 1us */ |
69 | #define C3_OVERHEAD 1 /* 1us */ | |
4f86d3a8 | 70 | #define PM_TIMER_TICKS_TO_US(p) (((p) * 1000)/(PM_TIMER_FREQUENCY/1000)) |
1da177e4 | 71 | |
4f86d3a8 LB |
72 | static unsigned int max_cstate __read_mostly = ACPI_PROCESSOR_MAX_POWER; |
73 | module_param(max_cstate, uint, 0000); | |
b6835052 | 74 | static unsigned int nocst __read_mostly; |
1da177e4 LT |
75 | module_param(nocst, uint, 0000); |
76 | ||
25de5718 | 77 | static unsigned int latency_factor __read_mostly = 2; |
4963f620 | 78 | module_param(latency_factor, uint, 0644); |
1da177e4 | 79 | |
ff69f2bb | 80 | static s64 us_to_pm_timer_ticks(s64 t) |
81 | { | |
82 | return div64_u64(t * PM_TIMER_FREQUENCY, 1000000); | |
83 | } | |
1da177e4 LT |
84 | /* |
85 | * IBM ThinkPad R40e crashes mysteriously when going into C2 or C3. | |
86 | * For now disable this. Probably a bug somewhere else. | |
87 | * | |
88 | * To skip this limit, boot/load with a large max_cstate limit. | |
89 | */ | |
1855256c | 90 | static int set_max_cstate(const struct dmi_system_id *id) |
1da177e4 LT |
91 | { |
92 | if (max_cstate > ACPI_PROCESSOR_MAX_POWER) | |
93 | return 0; | |
94 | ||
3d35600a | 95 | printk(KERN_NOTICE PREFIX "%s detected - limiting to C%ld max_cstate." |
4be44fcd LB |
96 | " Override with \"processor.max_cstate=%d\"\n", id->ident, |
97 | (long)id->driver_data, ACPI_PROCESSOR_MAX_POWER + 1); | |
1da177e4 | 98 | |
3d35600a | 99 | max_cstate = (long)id->driver_data; |
1da177e4 LT |
100 | |
101 | return 0; | |
102 | } | |
103 | ||
7ded5689 AR |
104 | /* Actually this shouldn't be __cpuinitdata, would be better to fix the |
105 | callers to only run once -AK */ | |
106 | static struct dmi_system_id __cpuinitdata processor_power_dmi_table[] = { | |
876c184b TR |
107 | { set_max_cstate, "Clevo 5600D", { |
108 | DMI_MATCH(DMI_BIOS_VENDOR,"Phoenix Technologies LTD"), | |
109 | DMI_MATCH(DMI_BIOS_VERSION,"SHE845M0.86C.0013.D.0302131307")}, | |
4be44fcd | 110 | (void *)2}, |
1da177e4 LT |
111 | {}, |
112 | }; | |
113 | ||
4f86d3a8 | 114 | |
2e906655 | 115 | /* |
116 | * Callers should disable interrupts before the call and enable | |
117 | * interrupts after return. | |
118 | */ | |
ddc081a1 VP |
119 | static void acpi_safe_halt(void) |
120 | { | |
121 | current_thread_info()->status &= ~TS_POLLING; | |
122 | /* | |
123 | * TS_POLLING-cleared state must be visible before we | |
124 | * test NEED_RESCHED: | |
125 | */ | |
126 | smp_mb(); | |
71e93d15 | 127 | if (!need_resched()) { |
ddc081a1 | 128 | safe_halt(); |
71e93d15 VP |
129 | local_irq_disable(); |
130 | } | |
ddc081a1 VP |
131 | current_thread_info()->status |= TS_POLLING; |
132 | } | |
133 | ||
169a0abb TG |
134 | #ifdef ARCH_APICTIMER_STOPS_ON_C3 |
135 | ||
136 | /* | |
137 | * Some BIOS implementations switch to C3 in the published C2 state. | |
296d93cd LT |
138 | * This seems to be a common problem on AMD boxen, but other vendors |
139 | * are affected too. We pick the most conservative approach: we assume | |
140 | * that the local APIC stops in both C2 and C3. | |
169a0abb TG |
141 | */ |
142 | static void acpi_timer_check_state(int state, struct acpi_processor *pr, | |
143 | struct acpi_processor_cx *cx) | |
144 | { | |
145 | struct acpi_processor_power *pwr = &pr->power; | |
e585bef8 | 146 | u8 type = local_apic_timer_c2_ok ? ACPI_STATE_C3 : ACPI_STATE_C2; |
169a0abb | 147 | |
db954b58 VP |
148 | if (cpu_has(&cpu_data(pr->id), X86_FEATURE_ARAT)) |
149 | return; | |
150 | ||
169a0abb TG |
151 | /* |
152 | * Check, if one of the previous states already marked the lapic | |
153 | * unstable | |
154 | */ | |
155 | if (pwr->timer_broadcast_on_state < state) | |
156 | return; | |
157 | ||
e585bef8 | 158 | if (cx->type >= type) |
296d93cd | 159 | pr->power.timer_broadcast_on_state = state; |
169a0abb TG |
160 | } |
161 | ||
162 | static void acpi_propagate_timer_broadcast(struct acpi_processor *pr) | |
163 | { | |
e9e2cdb4 TG |
164 | unsigned long reason; |
165 | ||
166 | reason = pr->power.timer_broadcast_on_state < INT_MAX ? | |
167 | CLOCK_EVT_NOTIFY_BROADCAST_ON : CLOCK_EVT_NOTIFY_BROADCAST_OFF; | |
168 | ||
169 | clockevents_notify(reason, &pr->id); | |
e9e2cdb4 TG |
170 | } |
171 | ||
172 | /* Power(C) State timer broadcast control */ | |
173 | static void acpi_state_timer_broadcast(struct acpi_processor *pr, | |
174 | struct acpi_processor_cx *cx, | |
175 | int broadcast) | |
176 | { | |
e9e2cdb4 TG |
177 | int state = cx - pr->power.states; |
178 | ||
179 | if (state >= pr->power.timer_broadcast_on_state) { | |
180 | unsigned long reason; | |
181 | ||
182 | reason = broadcast ? CLOCK_EVT_NOTIFY_BROADCAST_ENTER : | |
183 | CLOCK_EVT_NOTIFY_BROADCAST_EXIT; | |
184 | clockevents_notify(reason, &pr->id); | |
185 | } | |
169a0abb TG |
186 | } |
187 | ||
188 | #else | |
189 | ||
190 | static void acpi_timer_check_state(int state, struct acpi_processor *pr, | |
191 | struct acpi_processor_cx *cstate) { } | |
192 | static void acpi_propagate_timer_broadcast(struct acpi_processor *pr) { } | |
e9e2cdb4 TG |
193 | static void acpi_state_timer_broadcast(struct acpi_processor *pr, |
194 | struct acpi_processor_cx *cx, | |
195 | int broadcast) | |
196 | { | |
197 | } | |
169a0abb TG |
198 | |
199 | #endif | |
200 | ||
b04e7bdb TG |
201 | /* |
202 | * Suspend / resume control | |
203 | */ | |
204 | static int acpi_idle_suspend; | |
815ab0fd LB |
205 | static u32 saved_bm_rld; |
206 | ||
207 | static void acpi_idle_bm_rld_save(void) | |
208 | { | |
209 | acpi_read_bit_register(ACPI_BITREG_BUS_MASTER_RLD, &saved_bm_rld); | |
210 | } | |
211 | static void acpi_idle_bm_rld_restore(void) | |
212 | { | |
213 | u32 resumed_bm_rld; | |
214 | ||
215 | acpi_read_bit_register(ACPI_BITREG_BUS_MASTER_RLD, &resumed_bm_rld); | |
216 | ||
217 | if (resumed_bm_rld != saved_bm_rld) | |
218 | acpi_write_bit_register(ACPI_BITREG_BUS_MASTER_RLD, saved_bm_rld); | |
219 | } | |
b04e7bdb TG |
220 | |
221 | int acpi_processor_suspend(struct acpi_device * device, pm_message_t state) | |
222 | { | |
815ab0fd LB |
223 | if (acpi_idle_suspend == 1) |
224 | return 0; | |
225 | ||
226 | acpi_idle_bm_rld_save(); | |
b04e7bdb TG |
227 | acpi_idle_suspend = 1; |
228 | return 0; | |
229 | } | |
230 | ||
231 | int acpi_processor_resume(struct acpi_device * device) | |
232 | { | |
815ab0fd LB |
233 | if (acpi_idle_suspend == 0) |
234 | return 0; | |
235 | ||
236 | acpi_idle_bm_rld_restore(); | |
b04e7bdb TG |
237 | acpi_idle_suspend = 0; |
238 | return 0; | |
239 | } | |
240 | ||
61331168 | 241 | #if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86) |
520daf72 | 242 | static void tsc_check_state(int state) |
ddb25f9a AK |
243 | { |
244 | switch (boot_cpu_data.x86_vendor) { | |
245 | case X86_VENDOR_AMD: | |
40fb1715 | 246 | case X86_VENDOR_INTEL: |
ddb25f9a AK |
247 | /* |
248 | * AMD Fam10h TSC will tick in all | |
249 | * C/P/S0/S1 states when this bit is set. | |
250 | */ | |
40fb1715 | 251 | if (boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) |
520daf72 | 252 | return; |
40fb1715 | 253 | |
ddb25f9a | 254 | /*FALL THROUGH*/ |
ddb25f9a | 255 | default: |
520daf72 LB |
256 | /* TSC could halt in idle, so notify users */ |
257 | if (state > ACPI_STATE_C1) | |
258 | mark_tsc_unstable("TSC halts in idle"); | |
ddb25f9a AK |
259 | } |
260 | } | |
520daf72 LB |
261 | #else |
262 | static void tsc_check_state(int state) { return; } | |
ddb25f9a AK |
263 | #endif |
264 | ||
4be44fcd | 265 | static int acpi_processor_get_power_info_fadt(struct acpi_processor *pr) |
1da177e4 | 266 | { |
1da177e4 LT |
267 | |
268 | if (!pr) | |
d550d98d | 269 | return -EINVAL; |
1da177e4 LT |
270 | |
271 | if (!pr->pblk) | |
d550d98d | 272 | return -ENODEV; |
1da177e4 | 273 | |
1da177e4 | 274 | /* if info is obtained from pblk/fadt, type equals state */ |
1da177e4 LT |
275 | pr->power.states[ACPI_STATE_C2].type = ACPI_STATE_C2; |
276 | pr->power.states[ACPI_STATE_C3].type = ACPI_STATE_C3; | |
277 | ||
4c033552 VP |
278 | #ifndef CONFIG_HOTPLUG_CPU |
279 | /* | |
280 | * Check for P_LVL2_UP flag before entering C2 and above on | |
4f86d3a8 | 281 | * an SMP system. |
4c033552 | 282 | */ |
ad71860a | 283 | if ((num_online_cpus() > 1) && |
cee324b1 | 284 | !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED)) |
d550d98d | 285 | return -ENODEV; |
4c033552 VP |
286 | #endif |
287 | ||
1da177e4 LT |
288 | /* determine C2 and C3 address from pblk */ |
289 | pr->power.states[ACPI_STATE_C2].address = pr->pblk + 4; | |
290 | pr->power.states[ACPI_STATE_C3].address = pr->pblk + 5; | |
291 | ||
292 | /* determine latencies from FADT */ | |
cee324b1 AS |
293 | pr->power.states[ACPI_STATE_C2].latency = acpi_gbl_FADT.C2latency; |
294 | pr->power.states[ACPI_STATE_C3].latency = acpi_gbl_FADT.C3latency; | |
1da177e4 LT |
295 | |
296 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
297 | "lvl2[0x%08x] lvl3[0x%08x]\n", | |
298 | pr->power.states[ACPI_STATE_C2].address, | |
299 | pr->power.states[ACPI_STATE_C3].address)); | |
300 | ||
d550d98d | 301 | return 0; |
1da177e4 LT |
302 | } |
303 | ||
991528d7 | 304 | static int acpi_processor_get_power_info_default(struct acpi_processor *pr) |
acf05f4b | 305 | { |
991528d7 VP |
306 | if (!pr->power.states[ACPI_STATE_C1].valid) { |
307 | /* set the first C-State to C1 */ | |
308 | /* all processors need to support C1 */ | |
309 | pr->power.states[ACPI_STATE_C1].type = ACPI_STATE_C1; | |
310 | pr->power.states[ACPI_STATE_C1].valid = 1; | |
0fda6b40 | 311 | pr->power.states[ACPI_STATE_C1].entry_method = ACPI_CSTATE_HALT; |
991528d7 VP |
312 | } |
313 | /* the C0 state only exists as a filler in our array */ | |
acf05f4b | 314 | pr->power.states[ACPI_STATE_C0].valid = 1; |
d550d98d | 315 | return 0; |
acf05f4b VP |
316 | } |
317 | ||
4be44fcd | 318 | static int acpi_processor_get_power_info_cst(struct acpi_processor *pr) |
1da177e4 | 319 | { |
4be44fcd LB |
320 | acpi_status status = 0; |
321 | acpi_integer count; | |
cf824788 | 322 | int current_count; |
4be44fcd LB |
323 | int i; |
324 | struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; | |
325 | union acpi_object *cst; | |
1da177e4 | 326 | |
1da177e4 | 327 | |
1da177e4 | 328 | if (nocst) |
d550d98d | 329 | return -ENODEV; |
1da177e4 | 330 | |
991528d7 | 331 | current_count = 0; |
1da177e4 LT |
332 | |
333 | status = acpi_evaluate_object(pr->handle, "_CST", NULL, &buffer); | |
334 | if (ACPI_FAILURE(status)) { | |
335 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, "No _CST, giving up\n")); | |
d550d98d | 336 | return -ENODEV; |
4be44fcd | 337 | } |
1da177e4 | 338 | |
50dd0969 | 339 | cst = buffer.pointer; |
1da177e4 LT |
340 | |
341 | /* There must be at least 2 elements */ | |
342 | if (!cst || (cst->type != ACPI_TYPE_PACKAGE) || cst->package.count < 2) { | |
6468463a | 343 | printk(KERN_ERR PREFIX "not enough elements in _CST\n"); |
1da177e4 LT |
344 | status = -EFAULT; |
345 | goto end; | |
346 | } | |
347 | ||
348 | count = cst->package.elements[0].integer.value; | |
349 | ||
350 | /* Validate number of power states. */ | |
351 | if (count < 1 || count != cst->package.count - 1) { | |
6468463a | 352 | printk(KERN_ERR PREFIX "count given by _CST is not valid\n"); |
1da177e4 LT |
353 | status = -EFAULT; |
354 | goto end; | |
355 | } | |
356 | ||
1da177e4 LT |
357 | /* Tell driver that at least _CST is supported. */ |
358 | pr->flags.has_cst = 1; | |
359 | ||
360 | for (i = 1; i <= count; i++) { | |
361 | union acpi_object *element; | |
362 | union acpi_object *obj; | |
363 | struct acpi_power_register *reg; | |
364 | struct acpi_processor_cx cx; | |
365 | ||
366 | memset(&cx, 0, sizeof(cx)); | |
367 | ||
50dd0969 | 368 | element = &(cst->package.elements[i]); |
1da177e4 LT |
369 | if (element->type != ACPI_TYPE_PACKAGE) |
370 | continue; | |
371 | ||
372 | if (element->package.count != 4) | |
373 | continue; | |
374 | ||
50dd0969 | 375 | obj = &(element->package.elements[0]); |
1da177e4 LT |
376 | |
377 | if (obj->type != ACPI_TYPE_BUFFER) | |
378 | continue; | |
379 | ||
4be44fcd | 380 | reg = (struct acpi_power_register *)obj->buffer.pointer; |
1da177e4 LT |
381 | |
382 | if (reg->space_id != ACPI_ADR_SPACE_SYSTEM_IO && | |
4be44fcd | 383 | (reg->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE)) |
1da177e4 LT |
384 | continue; |
385 | ||
1da177e4 | 386 | /* There should be an easy way to extract an integer... */ |
50dd0969 | 387 | obj = &(element->package.elements[1]); |
1da177e4 LT |
388 | if (obj->type != ACPI_TYPE_INTEGER) |
389 | continue; | |
390 | ||
391 | cx.type = obj->integer.value; | |
991528d7 VP |
392 | /* |
393 | * Some buggy BIOSes won't list C1 in _CST - | |
394 | * Let acpi_processor_get_power_info_default() handle them later | |
395 | */ | |
396 | if (i == 1 && cx.type != ACPI_STATE_C1) | |
397 | current_count++; | |
398 | ||
399 | cx.address = reg->address; | |
400 | cx.index = current_count + 1; | |
401 | ||
bc71bec9 | 402 | cx.entry_method = ACPI_CSTATE_SYSTEMIO; |
991528d7 VP |
403 | if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE) { |
404 | if (acpi_processor_ffh_cstate_probe | |
405 | (pr->id, &cx, reg) == 0) { | |
bc71bec9 | 406 | cx.entry_method = ACPI_CSTATE_FFH; |
407 | } else if (cx.type == ACPI_STATE_C1) { | |
991528d7 VP |
408 | /* |
409 | * C1 is a special case where FIXED_HARDWARE | |
410 | * can be handled in non-MWAIT way as well. | |
411 | * In that case, save this _CST entry info. | |
991528d7 VP |
412 | * Otherwise, ignore this info and continue. |
413 | */ | |
bc71bec9 | 414 | cx.entry_method = ACPI_CSTATE_HALT; |
4fcb2fcd | 415 | snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI HLT"); |
bc71bec9 | 416 | } else { |
991528d7 VP |
417 | continue; |
418 | } | |
da5e09a1 ZY |
419 | if (cx.type == ACPI_STATE_C1 && |
420 | (idle_halt || idle_nomwait)) { | |
c1e3b377 ZY |
421 | /* |
422 | * In most cases the C1 space_id obtained from | |
423 | * _CST object is FIXED_HARDWARE access mode. | |
424 | * But when the option of idle=halt is added, | |
425 | * the entry_method type should be changed from | |
426 | * CSTATE_FFH to CSTATE_HALT. | |
da5e09a1 ZY |
427 | * When the option of idle=nomwait is added, |
428 | * the C1 entry_method type should be | |
429 | * CSTATE_HALT. | |
c1e3b377 ZY |
430 | */ |
431 | cx.entry_method = ACPI_CSTATE_HALT; | |
432 | snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI HLT"); | |
433 | } | |
4fcb2fcd VP |
434 | } else { |
435 | snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI IOPORT 0x%x", | |
436 | cx.address); | |
991528d7 | 437 | } |
1da177e4 | 438 | |
0fda6b40 VP |
439 | if (cx.type == ACPI_STATE_C1) { |
440 | cx.valid = 1; | |
441 | } | |
4fcb2fcd | 442 | |
50dd0969 | 443 | obj = &(element->package.elements[2]); |
1da177e4 LT |
444 | if (obj->type != ACPI_TYPE_INTEGER) |
445 | continue; | |
446 | ||
447 | cx.latency = obj->integer.value; | |
448 | ||
50dd0969 | 449 | obj = &(element->package.elements[3]); |
1da177e4 LT |
450 | if (obj->type != ACPI_TYPE_INTEGER) |
451 | continue; | |
452 | ||
453 | cx.power = obj->integer.value; | |
454 | ||
cf824788 JM |
455 | current_count++; |
456 | memcpy(&(pr->power.states[current_count]), &cx, sizeof(cx)); | |
457 | ||
458 | /* | |
459 | * We support total ACPI_PROCESSOR_MAX_POWER - 1 | |
460 | * (From 1 through ACPI_PROCESSOR_MAX_POWER - 1) | |
461 | */ | |
462 | if (current_count >= (ACPI_PROCESSOR_MAX_POWER - 1)) { | |
463 | printk(KERN_WARNING | |
464 | "Limiting number of power states to max (%d)\n", | |
465 | ACPI_PROCESSOR_MAX_POWER); | |
466 | printk(KERN_WARNING | |
467 | "Please increase ACPI_PROCESSOR_MAX_POWER if needed.\n"); | |
468 | break; | |
469 | } | |
1da177e4 LT |
470 | } |
471 | ||
4be44fcd | 472 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Found %d power states\n", |
cf824788 | 473 | current_count)); |
1da177e4 LT |
474 | |
475 | /* Validate number of power states discovered */ | |
cf824788 | 476 | if (current_count < 2) |
6d93c648 | 477 | status = -EFAULT; |
1da177e4 | 478 | |
4be44fcd | 479 | end: |
02438d87 | 480 | kfree(buffer.pointer); |
1da177e4 | 481 | |
d550d98d | 482 | return status; |
1da177e4 LT |
483 | } |
484 | ||
1da177e4 LT |
485 | static void acpi_processor_power_verify_c2(struct acpi_processor_cx *cx) |
486 | { | |
1da177e4 LT |
487 | |
488 | if (!cx->address) | |
d550d98d | 489 | return; |
1da177e4 LT |
490 | |
491 | /* | |
492 | * C2 latency must be less than or equal to 100 | |
493 | * microseconds. | |
494 | */ | |
495 | else if (cx->latency > ACPI_PROCESSOR_MAX_C2_LATENCY) { | |
496 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
4be44fcd | 497 | "latency too large [%d]\n", cx->latency)); |
d550d98d | 498 | return; |
1da177e4 LT |
499 | } |
500 | ||
1da177e4 LT |
501 | /* |
502 | * Otherwise we've met all of our C2 requirements. | |
503 | * Normalize the C2 latency to expidite policy | |
504 | */ | |
505 | cx->valid = 1; | |
4f86d3a8 | 506 | |
4f86d3a8 | 507 | cx->latency_ticks = cx->latency; |
1da177e4 | 508 | |
d550d98d | 509 | return; |
1da177e4 LT |
510 | } |
511 | ||
4be44fcd LB |
512 | static void acpi_processor_power_verify_c3(struct acpi_processor *pr, |
513 | struct acpi_processor_cx *cx) | |
1da177e4 | 514 | { |
02df8b93 VP |
515 | static int bm_check_flag; |
516 | ||
1da177e4 LT |
517 | |
518 | if (!cx->address) | |
d550d98d | 519 | return; |
1da177e4 LT |
520 | |
521 | /* | |
522 | * C3 latency must be less than or equal to 1000 | |
523 | * microseconds. | |
524 | */ | |
525 | else if (cx->latency > ACPI_PROCESSOR_MAX_C3_LATENCY) { | |
526 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
4be44fcd | 527 | "latency too large [%d]\n", cx->latency)); |
d550d98d | 528 | return; |
1da177e4 LT |
529 | } |
530 | ||
1da177e4 LT |
531 | /* |
532 | * PIIX4 Erratum #18: We don't support C3 when Type-F (fast) | |
533 | * DMA transfers are used by any ISA device to avoid livelock. | |
534 | * Note that we could disable Type-F DMA (as recommended by | |
535 | * the erratum), but this is known to disrupt certain ISA | |
536 | * devices thus we take the conservative approach. | |
537 | */ | |
538 | else if (errata.piix4.fdma) { | |
539 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
4be44fcd | 540 | "C3 not supported on PIIX4 with Type-F DMA\n")); |
d550d98d | 541 | return; |
1da177e4 LT |
542 | } |
543 | ||
02df8b93 VP |
544 | /* All the logic here assumes flags.bm_check is same across all CPUs */ |
545 | if (!bm_check_flag) { | |
546 | /* Determine whether bm_check is needed based on CPU */ | |
547 | acpi_processor_power_init_bm_check(&(pr->flags), pr->id); | |
548 | bm_check_flag = pr->flags.bm_check; | |
549 | } else { | |
550 | pr->flags.bm_check = bm_check_flag; | |
551 | } | |
552 | ||
553 | if (pr->flags.bm_check) { | |
02df8b93 | 554 | if (!pr->flags.bm_control) { |
ed3110ef VP |
555 | if (pr->flags.has_cst != 1) { |
556 | /* bus mastering control is necessary */ | |
557 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
558 | "C3 support requires BM control\n")); | |
559 | return; | |
560 | } else { | |
561 | /* Here we enter C3 without bus mastering */ | |
562 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, | |
563 | "C3 support without BM control\n")); | |
564 | } | |
02df8b93 VP |
565 | } |
566 | } else { | |
02df8b93 VP |
567 | /* |
568 | * WBINVD should be set in fadt, for C3 state to be | |
569 | * supported on when bm_check is not required. | |
570 | */ | |
cee324b1 | 571 | if (!(acpi_gbl_FADT.flags & ACPI_FADT_WBINVD)) { |
02df8b93 | 572 | ACPI_DEBUG_PRINT((ACPI_DB_INFO, |
4be44fcd LB |
573 | "Cache invalidation should work properly" |
574 | " for C3 to be enabled on SMP systems\n")); | |
d550d98d | 575 | return; |
02df8b93 | 576 | } |
02df8b93 VP |
577 | } |
578 | ||
1da177e4 LT |
579 | /* |
580 | * Otherwise we've met all of our C3 requirements. | |
581 | * Normalize the C3 latency to expidite policy. Enable | |
582 | * checking of bus mastering status (bm_check) so we can | |
583 | * use this in our C3 policy | |
584 | */ | |
585 | cx->valid = 1; | |
4f86d3a8 | 586 | |
4f86d3a8 | 587 | cx->latency_ticks = cx->latency; |
31878dd8 LB |
588 | /* |
589 | * On older chipsets, BM_RLD needs to be set | |
590 | * in order for Bus Master activity to wake the | |
591 | * system from C3. Newer chipsets handle DMA | |
592 | * during C3 automatically and BM_RLD is a NOP. | |
593 | * In either case, the proper way to | |
594 | * handle BM_RLD is to set it and leave it set. | |
595 | */ | |
50ffba1b | 596 | acpi_write_bit_register(ACPI_BITREG_BUS_MASTER_RLD, 1); |
1da177e4 | 597 | |
d550d98d | 598 | return; |
1da177e4 LT |
599 | } |
600 | ||
1da177e4 LT |
601 | static int acpi_processor_power_verify(struct acpi_processor *pr) |
602 | { | |
603 | unsigned int i; | |
604 | unsigned int working = 0; | |
6eb0a0fd | 605 | |
169a0abb | 606 | pr->power.timer_broadcast_on_state = INT_MAX; |
6eb0a0fd | 607 | |
a0bf284b | 608 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER && i <= max_cstate; i++) { |
1da177e4 LT |
609 | struct acpi_processor_cx *cx = &pr->power.states[i]; |
610 | ||
611 | switch (cx->type) { | |
612 | case ACPI_STATE_C1: | |
613 | cx->valid = 1; | |
614 | break; | |
615 | ||
616 | case ACPI_STATE_C2: | |
617 | acpi_processor_power_verify_c2(cx); | |
296d93cd | 618 | if (cx->valid) |
169a0abb | 619 | acpi_timer_check_state(i, pr, cx); |
1da177e4 LT |
620 | break; |
621 | ||
622 | case ACPI_STATE_C3: | |
623 | acpi_processor_power_verify_c3(pr, cx); | |
296d93cd | 624 | if (cx->valid) |
169a0abb | 625 | acpi_timer_check_state(i, pr, cx); |
1da177e4 LT |
626 | break; |
627 | } | |
520daf72 LB |
628 | if (cx->valid) |
629 | tsc_check_state(cx->type); | |
1da177e4 LT |
630 | |
631 | if (cx->valid) | |
632 | working++; | |
633 | } | |
bd663347 | 634 | |
169a0abb | 635 | acpi_propagate_timer_broadcast(pr); |
1da177e4 LT |
636 | |
637 | return (working); | |
638 | } | |
639 | ||
4be44fcd | 640 | static int acpi_processor_get_power_info(struct acpi_processor *pr) |
1da177e4 LT |
641 | { |
642 | unsigned int i; | |
643 | int result; | |
644 | ||
1da177e4 LT |
645 | |
646 | /* NOTE: the idle thread may not be running while calling | |
647 | * this function */ | |
648 | ||
991528d7 VP |
649 | /* Zero initialize all the C-states info. */ |
650 | memset(pr->power.states, 0, sizeof(pr->power.states)); | |
651 | ||
1da177e4 | 652 | result = acpi_processor_get_power_info_cst(pr); |
6d93c648 | 653 | if (result == -ENODEV) |
c5a114f1 | 654 | result = acpi_processor_get_power_info_fadt(pr); |
6d93c648 | 655 | |
991528d7 VP |
656 | if (result) |
657 | return result; | |
658 | ||
659 | acpi_processor_get_power_info_default(pr); | |
660 | ||
cf824788 | 661 | pr->power.count = acpi_processor_power_verify(pr); |
1da177e4 | 662 | |
1da177e4 LT |
663 | /* |
664 | * if one state of type C2 or C3 is available, mark this | |
665 | * CPU as being "idle manageable" | |
666 | */ | |
667 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) { | |
acf05f4b | 668 | if (pr->power.states[i].valid) { |
1da177e4 | 669 | pr->power.count = i; |
2203d6ed LT |
670 | if (pr->power.states[i].type >= ACPI_STATE_C2) |
671 | pr->flags.power = 1; | |
acf05f4b | 672 | } |
1da177e4 LT |
673 | } |
674 | ||
d550d98d | 675 | return 0; |
1da177e4 LT |
676 | } |
677 | ||
1da177e4 LT |
678 | static int acpi_processor_power_seq_show(struct seq_file *seq, void *offset) |
679 | { | |
50dd0969 | 680 | struct acpi_processor *pr = seq->private; |
4be44fcd | 681 | unsigned int i; |
1da177e4 | 682 | |
1da177e4 LT |
683 | |
684 | if (!pr) | |
685 | goto end; | |
686 | ||
687 | seq_printf(seq, "active state: C%zd\n" | |
4be44fcd | 688 | "max_cstate: C%d\n" |
5c87579e | 689 | "maximum allowed latency: %d usec\n", |
4be44fcd | 690 | pr->power.state ? pr->power.state - pr->power.states : 0, |
92614610 | 691 | max_cstate, pm_qos_requirement(PM_QOS_CPU_DMA_LATENCY)); |
1da177e4 LT |
692 | |
693 | seq_puts(seq, "states:\n"); | |
694 | ||
695 | for (i = 1; i <= pr->power.count; i++) { | |
696 | seq_printf(seq, " %cC%d: ", | |
4be44fcd LB |
697 | (&pr->power.states[i] == |
698 | pr->power.state ? '*' : ' '), i); | |
1da177e4 LT |
699 | |
700 | if (!pr->power.states[i].valid) { | |
701 | seq_puts(seq, "<not supported>\n"); | |
702 | continue; | |
703 | } | |
704 | ||
705 | switch (pr->power.states[i].type) { | |
706 | case ACPI_STATE_C1: | |
707 | seq_printf(seq, "type[C1] "); | |
708 | break; | |
709 | case ACPI_STATE_C2: | |
710 | seq_printf(seq, "type[C2] "); | |
711 | break; | |
712 | case ACPI_STATE_C3: | |
713 | seq_printf(seq, "type[C3] "); | |
714 | break; | |
715 | default: | |
716 | seq_printf(seq, "type[--] "); | |
717 | break; | |
718 | } | |
719 | ||
720 | if (pr->power.states[i].promotion.state) | |
721 | seq_printf(seq, "promotion[C%zd] ", | |
4be44fcd LB |
722 | (pr->power.states[i].promotion.state - |
723 | pr->power.states)); | |
1da177e4 LT |
724 | else |
725 | seq_puts(seq, "promotion[--] "); | |
726 | ||
727 | if (pr->power.states[i].demotion.state) | |
728 | seq_printf(seq, "demotion[C%zd] ", | |
4be44fcd LB |
729 | (pr->power.states[i].demotion.state - |
730 | pr->power.states)); | |
1da177e4 LT |
731 | else |
732 | seq_puts(seq, "demotion[--] "); | |
733 | ||
a3c6598f | 734 | seq_printf(seq, "latency[%03d] usage[%08d] duration[%020llu]\n", |
4be44fcd | 735 | pr->power.states[i].latency, |
a3c6598f | 736 | pr->power.states[i].usage, |
b0b7eaaf | 737 | (unsigned long long)pr->power.states[i].time); |
1da177e4 LT |
738 | } |
739 | ||
4be44fcd | 740 | end: |
d550d98d | 741 | return 0; |
1da177e4 LT |
742 | } |
743 | ||
744 | static int acpi_processor_power_open_fs(struct inode *inode, struct file *file) | |
745 | { | |
746 | return single_open(file, acpi_processor_power_seq_show, | |
4be44fcd | 747 | PDE(inode)->data); |
1da177e4 LT |
748 | } |
749 | ||
d7508032 | 750 | static const struct file_operations acpi_processor_power_fops = { |
cf7acfab | 751 | .owner = THIS_MODULE, |
4be44fcd LB |
752 | .open = acpi_processor_power_open_fs, |
753 | .read = seq_read, | |
754 | .llseek = seq_lseek, | |
755 | .release = single_release, | |
1da177e4 LT |
756 | }; |
757 | ||
4f86d3a8 LB |
758 | |
759 | /** | |
760 | * acpi_idle_bm_check - checks if bus master activity was detected | |
761 | */ | |
762 | static int acpi_idle_bm_check(void) | |
763 | { | |
764 | u32 bm_status = 0; | |
765 | ||
50ffba1b | 766 | acpi_read_bit_register(ACPI_BITREG_BUS_MASTER_STATUS, &bm_status); |
4f86d3a8 | 767 | if (bm_status) |
50ffba1b | 768 | acpi_write_bit_register(ACPI_BITREG_BUS_MASTER_STATUS, 1); |
4f86d3a8 LB |
769 | /* |
770 | * PIIX4 Erratum #18: Note that BM_STS doesn't always reflect | |
771 | * the true state of bus mastering activity; forcing us to | |
772 | * manually check the BMIDEA bit of each IDE channel. | |
773 | */ | |
774 | else if (errata.piix4.bmisx) { | |
775 | if ((inb_p(errata.piix4.bmisx + 0x02) & 0x01) | |
776 | || (inb_p(errata.piix4.bmisx + 0x0A) & 0x01)) | |
777 | bm_status = 1; | |
778 | } | |
779 | return bm_status; | |
780 | } | |
781 | ||
4f86d3a8 LB |
782 | /** |
783 | * acpi_idle_do_entry - a helper function that does C2 and C3 type entry | |
784 | * @cx: cstate data | |
bc71bec9 | 785 | * |
786 | * Caller disables interrupt before call and enables interrupt after return. | |
4f86d3a8 LB |
787 | */ |
788 | static inline void acpi_idle_do_entry(struct acpi_processor_cx *cx) | |
789 | { | |
dcf30997 SR |
790 | /* Don't trace irqs off for idle */ |
791 | stop_critical_timings(); | |
bc71bec9 | 792 | if (cx->entry_method == ACPI_CSTATE_FFH) { |
4f86d3a8 LB |
793 | /* Call into architectural FFH based C-state */ |
794 | acpi_processor_ffh_cstate_enter(cx); | |
bc71bec9 | 795 | } else if (cx->entry_method == ACPI_CSTATE_HALT) { |
796 | acpi_safe_halt(); | |
4f86d3a8 LB |
797 | } else { |
798 | int unused; | |
799 | /* IO port based C-state */ | |
800 | inb(cx->address); | |
801 | /* Dummy wait op - must do something useless after P_LVL2 read | |
802 | because chipsets cannot guarantee that STPCLK# signal | |
803 | gets asserted in time to freeze execution properly. */ | |
804 | unused = inl(acpi_gbl_FADT.xpm_timer_block.address); | |
805 | } | |
dcf30997 | 806 | start_critical_timings(); |
4f86d3a8 LB |
807 | } |
808 | ||
809 | /** | |
810 | * acpi_idle_enter_c1 - enters an ACPI C1 state-type | |
811 | * @dev: the target CPU | |
812 | * @state: the state data | |
813 | * | |
814 | * This is equivalent to the HALT instruction. | |
815 | */ | |
816 | static int acpi_idle_enter_c1(struct cpuidle_device *dev, | |
817 | struct cpuidle_state *state) | |
818 | { | |
ff69f2bb | 819 | ktime_t kt1, kt2; |
820 | s64 idle_time; | |
4f86d3a8 LB |
821 | struct acpi_processor *pr; |
822 | struct acpi_processor_cx *cx = cpuidle_get_statedata(state); | |
9b12e18c | 823 | |
706546d0 | 824 | pr = __get_cpu_var(processors); |
4f86d3a8 LB |
825 | |
826 | if (unlikely(!pr)) | |
827 | return 0; | |
828 | ||
2e906655 | 829 | local_irq_disable(); |
b077fbad VP |
830 | |
831 | /* Do not access any ACPI IO ports in suspend path */ | |
832 | if (acpi_idle_suspend) { | |
833 | acpi_safe_halt(); | |
834 | local_irq_enable(); | |
835 | return 0; | |
836 | } | |
837 | ||
ff69f2bb | 838 | kt1 = ktime_get_real(); |
bc71bec9 | 839 | acpi_idle_do_entry(cx); |
ff69f2bb | 840 | kt2 = ktime_get_real(); |
841 | idle_time = ktime_to_us(ktime_sub(kt2, kt1)); | |
4f86d3a8 | 842 | |
2e906655 | 843 | local_irq_enable(); |
4f86d3a8 LB |
844 | cx->usage++; |
845 | ||
ff69f2bb | 846 | return idle_time; |
4f86d3a8 LB |
847 | } |
848 | ||
849 | /** | |
850 | * acpi_idle_enter_simple - enters an ACPI state without BM handling | |
851 | * @dev: the target CPU | |
852 | * @state: the state data | |
853 | */ | |
854 | static int acpi_idle_enter_simple(struct cpuidle_device *dev, | |
855 | struct cpuidle_state *state) | |
856 | { | |
857 | struct acpi_processor *pr; | |
858 | struct acpi_processor_cx *cx = cpuidle_get_statedata(state); | |
ff69f2bb | 859 | ktime_t kt1, kt2; |
860 | s64 idle_time; | |
861 | s64 sleep_ticks = 0; | |
50629118 | 862 | |
706546d0 | 863 | pr = __get_cpu_var(processors); |
4f86d3a8 LB |
864 | |
865 | if (unlikely(!pr)) | |
866 | return 0; | |
867 | ||
e196441b LB |
868 | if (acpi_idle_suspend) |
869 | return(acpi_idle_enter_c1(dev, state)); | |
870 | ||
4f86d3a8 LB |
871 | local_irq_disable(); |
872 | current_thread_info()->status &= ~TS_POLLING; | |
873 | /* | |
874 | * TS_POLLING-cleared state must be visible before we test | |
875 | * NEED_RESCHED: | |
876 | */ | |
877 | smp_mb(); | |
878 | ||
879 | if (unlikely(need_resched())) { | |
880 | current_thread_info()->status |= TS_POLLING; | |
881 | local_irq_enable(); | |
882 | return 0; | |
883 | } | |
884 | ||
e17bcb43 TG |
885 | /* |
886 | * Must be done before busmaster disable as we might need to | |
887 | * access HPET ! | |
888 | */ | |
889 | acpi_state_timer_broadcast(pr, cx, 1); | |
890 | ||
4f86d3a8 LB |
891 | if (cx->type == ACPI_STATE_C3) |
892 | ACPI_FLUSH_CPU_CACHE(); | |
893 | ||
ff69f2bb | 894 | kt1 = ktime_get_real(); |
50629118 VP |
895 | /* Tell the scheduler that we are going deep-idle: */ |
896 | sched_clock_idle_sleep_event(); | |
4f86d3a8 | 897 | acpi_idle_do_entry(cx); |
ff69f2bb | 898 | kt2 = ktime_get_real(); |
899 | idle_time = ktime_to_us(ktime_sub(kt2, kt1)); | |
4f86d3a8 | 900 | |
ff69f2bb | 901 | sleep_ticks = us_to_pm_timer_ticks(idle_time); |
50629118 VP |
902 | |
903 | /* Tell the scheduler how much we idled: */ | |
904 | sched_clock_idle_wakeup_event(sleep_ticks*PM_TIMER_TICK_NS); | |
4f86d3a8 LB |
905 | |
906 | local_irq_enable(); | |
907 | current_thread_info()->status |= TS_POLLING; | |
908 | ||
909 | cx->usage++; | |
910 | ||
911 | acpi_state_timer_broadcast(pr, cx, 0); | |
50629118 | 912 | cx->time += sleep_ticks; |
ff69f2bb | 913 | return idle_time; |
4f86d3a8 LB |
914 | } |
915 | ||
916 | static int c3_cpu_count; | |
917 | static DEFINE_SPINLOCK(c3_lock); | |
918 | ||
919 | /** | |
920 | * acpi_idle_enter_bm - enters C3 with proper BM handling | |
921 | * @dev: the target CPU | |
922 | * @state: the state data | |
923 | * | |
924 | * If BM is detected, the deepest non-C3 idle state is entered instead. | |
925 | */ | |
926 | static int acpi_idle_enter_bm(struct cpuidle_device *dev, | |
927 | struct cpuidle_state *state) | |
928 | { | |
929 | struct acpi_processor *pr; | |
930 | struct acpi_processor_cx *cx = cpuidle_get_statedata(state); | |
ff69f2bb | 931 | ktime_t kt1, kt2; |
932 | s64 idle_time; | |
933 | s64 sleep_ticks = 0; | |
934 | ||
50629118 | 935 | |
706546d0 | 936 | pr = __get_cpu_var(processors); |
4f86d3a8 LB |
937 | |
938 | if (unlikely(!pr)) | |
939 | return 0; | |
940 | ||
e196441b LB |
941 | if (acpi_idle_suspend) |
942 | return(acpi_idle_enter_c1(dev, state)); | |
943 | ||
ddc081a1 VP |
944 | if (acpi_idle_bm_check()) { |
945 | if (dev->safe_state) { | |
addbad46 | 946 | dev->last_state = dev->safe_state; |
ddc081a1 VP |
947 | return dev->safe_state->enter(dev, dev->safe_state); |
948 | } else { | |
2e906655 | 949 | local_irq_disable(); |
ddc081a1 | 950 | acpi_safe_halt(); |
2e906655 | 951 | local_irq_enable(); |
ddc081a1 VP |
952 | return 0; |
953 | } | |
954 | } | |
955 | ||
4f86d3a8 LB |
956 | local_irq_disable(); |
957 | current_thread_info()->status &= ~TS_POLLING; | |
958 | /* | |
959 | * TS_POLLING-cleared state must be visible before we test | |
960 | * NEED_RESCHED: | |
961 | */ | |
962 | smp_mb(); | |
963 | ||
964 | if (unlikely(need_resched())) { | |
965 | current_thread_info()->status |= TS_POLLING; | |
966 | local_irq_enable(); | |
967 | return 0; | |
968 | } | |
969 | ||
996520c1 VP |
970 | acpi_unlazy_tlb(smp_processor_id()); |
971 | ||
50629118 VP |
972 | /* Tell the scheduler that we are going deep-idle: */ |
973 | sched_clock_idle_sleep_event(); | |
4f86d3a8 LB |
974 | /* |
975 | * Must be done before busmaster disable as we might need to | |
976 | * access HPET ! | |
977 | */ | |
978 | acpi_state_timer_broadcast(pr, cx, 1); | |
979 | ||
f461ddea | 980 | kt1 = ktime_get_real(); |
ddc081a1 VP |
981 | /* |
982 | * disable bus master | |
983 | * bm_check implies we need ARB_DIS | |
984 | * !bm_check implies we need cache flush | |
985 | * bm_control implies whether we can do ARB_DIS | |
986 | * | |
987 | * That leaves a case where bm_check is set and bm_control is | |
988 | * not set. In that case we cannot do much, we enter C3 | |
989 | * without doing anything. | |
990 | */ | |
991 | if (pr->flags.bm_check && pr->flags.bm_control) { | |
4f86d3a8 LB |
992 | spin_lock(&c3_lock); |
993 | c3_cpu_count++; | |
994 | /* Disable bus master arbitration when all CPUs are in C3 */ | |
995 | if (c3_cpu_count == num_online_cpus()) | |
50ffba1b | 996 | acpi_write_bit_register(ACPI_BITREG_ARB_DISABLE, 1); |
4f86d3a8 | 997 | spin_unlock(&c3_lock); |
ddc081a1 VP |
998 | } else if (!pr->flags.bm_check) { |
999 | ACPI_FLUSH_CPU_CACHE(); | |
1000 | } | |
4f86d3a8 | 1001 | |
ddc081a1 | 1002 | acpi_idle_do_entry(cx); |
4f86d3a8 | 1003 | |
ddc081a1 VP |
1004 | /* Re-enable bus master arbitration */ |
1005 | if (pr->flags.bm_check && pr->flags.bm_control) { | |
4f86d3a8 | 1006 | spin_lock(&c3_lock); |
50ffba1b | 1007 | acpi_write_bit_register(ACPI_BITREG_ARB_DISABLE, 0); |
4f86d3a8 LB |
1008 | c3_cpu_count--; |
1009 | spin_unlock(&c3_lock); | |
1010 | } | |
f461ddea LB |
1011 | kt2 = ktime_get_real(); |
1012 | idle_time = ktime_to_us(ktime_sub(kt2, kt1)); | |
4f86d3a8 | 1013 | |
ff69f2bb | 1014 | sleep_ticks = us_to_pm_timer_ticks(idle_time); |
50629118 VP |
1015 | /* Tell the scheduler how much we idled: */ |
1016 | sched_clock_idle_wakeup_event(sleep_ticks*PM_TIMER_TICK_NS); | |
4f86d3a8 LB |
1017 | |
1018 | local_irq_enable(); | |
1019 | current_thread_info()->status |= TS_POLLING; | |
1020 | ||
1021 | cx->usage++; | |
1022 | ||
1023 | acpi_state_timer_broadcast(pr, cx, 0); | |
50629118 | 1024 | cx->time += sleep_ticks; |
ff69f2bb | 1025 | return idle_time; |
4f86d3a8 LB |
1026 | } |
1027 | ||
1028 | struct cpuidle_driver acpi_idle_driver = { | |
1029 | .name = "acpi_idle", | |
1030 | .owner = THIS_MODULE, | |
1031 | }; | |
1032 | ||
1033 | /** | |
1034 | * acpi_processor_setup_cpuidle - prepares and configures CPUIDLE | |
1035 | * @pr: the ACPI processor | |
1036 | */ | |
1037 | static int acpi_processor_setup_cpuidle(struct acpi_processor *pr) | |
1038 | { | |
9a0b8415 | 1039 | int i, count = CPUIDLE_DRIVER_STATE_START; |
4f86d3a8 LB |
1040 | struct acpi_processor_cx *cx; |
1041 | struct cpuidle_state *state; | |
1042 | struct cpuidle_device *dev = &pr->power.dev; | |
1043 | ||
1044 | if (!pr->flags.power_setup_done) | |
1045 | return -EINVAL; | |
1046 | ||
1047 | if (pr->flags.power == 0) { | |
1048 | return -EINVAL; | |
1049 | } | |
1050 | ||
dcb84f33 | 1051 | dev->cpu = pr->id; |
4fcb2fcd VP |
1052 | for (i = 0; i < CPUIDLE_STATE_MAX; i++) { |
1053 | dev->states[i].name[0] = '\0'; | |
1054 | dev->states[i].desc[0] = '\0'; | |
1055 | } | |
1056 | ||
615dfd93 LB |
1057 | if (max_cstate == 0) |
1058 | max_cstate = 1; | |
1059 | ||
4f86d3a8 LB |
1060 | for (i = 1; i < ACPI_PROCESSOR_MAX_POWER && i <= max_cstate; i++) { |
1061 | cx = &pr->power.states[i]; | |
1062 | state = &dev->states[count]; | |
1063 | ||
1064 | if (!cx->valid) | |
1065 | continue; | |
1066 | ||
1067 | #ifdef CONFIG_HOTPLUG_CPU | |
1068 | if ((cx->type != ACPI_STATE_C1) && (num_online_cpus() > 1) && | |
1069 | !pr->flags.has_cst && | |
1070 | !(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED)) | |
1071 | continue; | |
1fec74a9 | 1072 | #endif |
4f86d3a8 LB |
1073 | cpuidle_set_statedata(state, cx); |
1074 | ||
1075 | snprintf(state->name, CPUIDLE_NAME_LEN, "C%d", i); | |
4fcb2fcd | 1076 | strncpy(state->desc, cx->desc, CPUIDLE_DESC_LEN); |
4f86d3a8 | 1077 | state->exit_latency = cx->latency; |
4963f620 | 1078 | state->target_residency = cx->latency * latency_factor; |
4f86d3a8 LB |
1079 | state->power_usage = cx->power; |
1080 | ||
1081 | state->flags = 0; | |
1082 | switch (cx->type) { | |
1083 | case ACPI_STATE_C1: | |
1084 | state->flags |= CPUIDLE_FLAG_SHALLOW; | |
8e92b660 VP |
1085 | if (cx->entry_method == ACPI_CSTATE_FFH) |
1086 | state->flags |= CPUIDLE_FLAG_TIME_VALID; | |
1087 | ||
4f86d3a8 | 1088 | state->enter = acpi_idle_enter_c1; |
ddc081a1 | 1089 | dev->safe_state = state; |
4f86d3a8 LB |
1090 | break; |
1091 | ||
1092 | case ACPI_STATE_C2: | |
1093 | state->flags |= CPUIDLE_FLAG_BALANCED; | |
1094 | state->flags |= CPUIDLE_FLAG_TIME_VALID; | |
1095 | state->enter = acpi_idle_enter_simple; | |
ddc081a1 | 1096 | dev->safe_state = state; |
4f86d3a8 LB |
1097 | break; |
1098 | ||
1099 | case ACPI_STATE_C3: | |
1100 | state->flags |= CPUIDLE_FLAG_DEEP; | |
1101 | state->flags |= CPUIDLE_FLAG_TIME_VALID; | |
1102 | state->flags |= CPUIDLE_FLAG_CHECK_BM; | |
1103 | state->enter = pr->flags.bm_check ? | |
1104 | acpi_idle_enter_bm : | |
1105 | acpi_idle_enter_simple; | |
1106 | break; | |
1107 | } | |
1108 | ||
1109 | count++; | |
9a0b8415 | 1110 | if (count == CPUIDLE_STATE_MAX) |
1111 | break; | |
4f86d3a8 LB |
1112 | } |
1113 | ||
1114 | dev->state_count = count; | |
1115 | ||
1116 | if (!count) | |
1117 | return -EINVAL; | |
1118 | ||
4f86d3a8 LB |
1119 | return 0; |
1120 | } | |
1121 | ||
1122 | int acpi_processor_cst_has_changed(struct acpi_processor *pr) | |
1123 | { | |
dcb84f33 | 1124 | int ret = 0; |
4f86d3a8 | 1125 | |
36a91358 VP |
1126 | if (boot_option_idle_override) |
1127 | return 0; | |
1128 | ||
4f86d3a8 LB |
1129 | if (!pr) |
1130 | return -EINVAL; | |
1131 | ||
1132 | if (nocst) { | |
1133 | return -ENODEV; | |
1134 | } | |
1135 | ||
1136 | if (!pr->flags.power_setup_done) | |
1137 | return -ENODEV; | |
1138 | ||
1139 | cpuidle_pause_and_lock(); | |
1140 | cpuidle_disable_device(&pr->power.dev); | |
1141 | acpi_processor_get_power_info(pr); | |
dcb84f33 VP |
1142 | if (pr->flags.power) { |
1143 | acpi_processor_setup_cpuidle(pr); | |
1144 | ret = cpuidle_enable_device(&pr->power.dev); | |
1145 | } | |
4f86d3a8 LB |
1146 | cpuidle_resume_and_unlock(); |
1147 | ||
1148 | return ret; | |
1149 | } | |
1150 | ||
7af8b660 | 1151 | int __cpuinit acpi_processor_power_init(struct acpi_processor *pr, |
4be44fcd | 1152 | struct acpi_device *device) |
1da177e4 | 1153 | { |
4be44fcd | 1154 | acpi_status status = 0; |
b6835052 | 1155 | static int first_run; |
4be44fcd | 1156 | struct proc_dir_entry *entry = NULL; |
1da177e4 LT |
1157 | unsigned int i; |
1158 | ||
36a91358 VP |
1159 | if (boot_option_idle_override) |
1160 | return 0; | |
1da177e4 LT |
1161 | |
1162 | if (!first_run) { | |
c1e3b377 ZY |
1163 | if (idle_halt) { |
1164 | /* | |
1165 | * When the boot option of "idle=halt" is added, halt | |
1166 | * is used for CPU IDLE. | |
1167 | * In such case C2/C3 is meaningless. So the max_cstate | |
1168 | * is set to one. | |
1169 | */ | |
1170 | max_cstate = 1; | |
1171 | } | |
1da177e4 | 1172 | dmi_check_system(processor_power_dmi_table); |
c1c30634 | 1173 | max_cstate = acpi_processor_cstate_check(max_cstate); |
1da177e4 | 1174 | if (max_cstate < ACPI_C_STATES_MAX) |
4be44fcd LB |
1175 | printk(KERN_NOTICE |
1176 | "ACPI: processor limited to max C-state %d\n", | |
1177 | max_cstate); | |
1da177e4 LT |
1178 | first_run++; |
1179 | } | |
1180 | ||
02df8b93 | 1181 | if (!pr) |
d550d98d | 1182 | return -EINVAL; |
02df8b93 | 1183 | |
cee324b1 | 1184 | if (acpi_gbl_FADT.cst_control && !nocst) { |
4be44fcd | 1185 | status = |
cee324b1 | 1186 | acpi_os_write_port(acpi_gbl_FADT.smi_command, acpi_gbl_FADT.cst_control, 8); |
1da177e4 | 1187 | if (ACPI_FAILURE(status)) { |
a6fc6720 TR |
1188 | ACPI_EXCEPTION((AE_INFO, status, |
1189 | "Notifying BIOS of _CST ability failed")); | |
1da177e4 LT |
1190 | } |
1191 | } | |
1192 | ||
1193 | acpi_processor_get_power_info(pr); | |
4f86d3a8 | 1194 | pr->flags.power_setup_done = 1; |
1da177e4 LT |
1195 | |
1196 | /* | |
1197 | * Install the idle handler if processor power management is supported. | |
1198 | * Note that we use previously set idle handler will be used on | |
1199 | * platforms that only support C1. | |
1200 | */ | |
36a91358 | 1201 | if (pr->flags.power) { |
4f86d3a8 | 1202 | acpi_processor_setup_cpuidle(pr); |
4f86d3a8 LB |
1203 | if (cpuidle_register_device(&pr->power.dev)) |
1204 | return -EIO; | |
4f86d3a8 | 1205 | |
1da177e4 LT |
1206 | printk(KERN_INFO PREFIX "CPU%d (power states:", pr->id); |
1207 | for (i = 1; i <= pr->power.count; i++) | |
1208 | if (pr->power.states[i].valid) | |
4be44fcd LB |
1209 | printk(" C%d[C%d]", i, |
1210 | pr->power.states[i].type); | |
1da177e4 | 1211 | printk(")\n"); |
1da177e4 LT |
1212 | } |
1213 | ||
1214 | /* 'power' [R] */ | |
cf7acfab DL |
1215 | entry = proc_create_data(ACPI_PROCESSOR_FILE_POWER, |
1216 | S_IRUGO, acpi_device_dir(device), | |
1217 | &acpi_processor_power_fops, | |
1218 | acpi_driver_data(device)); | |
1da177e4 | 1219 | if (!entry) |
a6fc6720 | 1220 | return -EIO; |
d550d98d | 1221 | return 0; |
1da177e4 LT |
1222 | } |
1223 | ||
4be44fcd LB |
1224 | int acpi_processor_power_exit(struct acpi_processor *pr, |
1225 | struct acpi_device *device) | |
1da177e4 | 1226 | { |
36a91358 VP |
1227 | if (boot_option_idle_override) |
1228 | return 0; | |
1229 | ||
dcb84f33 | 1230 | cpuidle_unregister_device(&pr->power.dev); |
1da177e4 LT |
1231 | pr->flags.power_setup_done = 0; |
1232 | ||
1233 | if (acpi_device_dir(device)) | |
4be44fcd LB |
1234 | remove_proc_entry(ACPI_PROCESSOR_FILE_POWER, |
1235 | acpi_device_dir(device)); | |
1da177e4 | 1236 | |
d550d98d | 1237 | return 0; |
1da177e4 | 1238 | } |