2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
21 #include <linux/kvm_host.h>
22 #include <linux/module.h>
23 #include <linux/kernel.h>
25 #include <linux/highmem.h>
26 #include <linux/sched.h>
27 #include <linux/moduleparam.h>
28 #include <linux/ftrace_event.h>
29 #include "kvm_cache_regs.h"
35 #include <asm/virtext.h>
40 #define __ex(x) __kvm_handle_fault_on_reboot(x)
42 MODULE_AUTHOR("Qumranet");
43 MODULE_LICENSE("GPL");
45 static int __read_mostly bypass_guest_pf
= 1;
46 module_param(bypass_guest_pf
, bool, S_IRUGO
);
48 static int __read_mostly enable_vpid
= 1;
49 module_param_named(vpid
, enable_vpid
, bool, 0444);
51 static int __read_mostly flexpriority_enabled
= 1;
52 module_param_named(flexpriority
, flexpriority_enabled
, bool, S_IRUGO
);
54 static int __read_mostly enable_ept
= 1;
55 module_param_named(ept
, enable_ept
, bool, S_IRUGO
);
57 static int __read_mostly enable_unrestricted_guest
= 1;
58 module_param_named(unrestricted_guest
,
59 enable_unrestricted_guest
, bool, S_IRUGO
);
61 static int __read_mostly emulate_invalid_guest_state
= 0;
62 module_param(emulate_invalid_guest_state
, bool, S_IRUGO
);
72 struct list_head local_vcpus_link
;
73 unsigned long host_rsp
;
76 u32 idt_vectoring_info
;
77 struct kvm_msr_entry
*guest_msrs
;
78 struct kvm_msr_entry
*host_msrs
;
83 int msr_offset_kernel_gs_base
;
88 u16 fs_sel
, gs_sel
, ldt_sel
;
89 int gs_ldt_reload_needed
;
91 int guest_efer_loaded
;
96 struct kvm_save_segment
{
101 } tr
, es
, ds
, fs
, gs
;
109 bool emulation_required
;
110 enum emulation_result invalid_state_emulation_result
;
112 /* Support for vnmi-less CPUs */
113 int soft_vnmi_blocked
;
115 s64 vnmi_blocked_time
;
119 static inline struct vcpu_vmx
*to_vmx(struct kvm_vcpu
*vcpu
)
121 return container_of(vcpu
, struct vcpu_vmx
, vcpu
);
124 static int init_rmode(struct kvm
*kvm
);
125 static u64
construct_eptp(unsigned long root_hpa
);
127 static DEFINE_PER_CPU(struct vmcs
*, vmxarea
);
128 static DEFINE_PER_CPU(struct vmcs
*, current_vmcs
);
129 static DEFINE_PER_CPU(struct list_head
, vcpus_on_cpu
);
131 static unsigned long *vmx_io_bitmap_a
;
132 static unsigned long *vmx_io_bitmap_b
;
133 static unsigned long *vmx_msr_bitmap_legacy
;
134 static unsigned long *vmx_msr_bitmap_longmode
;
136 static DECLARE_BITMAP(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
137 static DEFINE_SPINLOCK(vmx_vpid_lock
);
139 static struct vmcs_config
{
143 u32 pin_based_exec_ctrl
;
144 u32 cpu_based_exec_ctrl
;
145 u32 cpu_based_2nd_exec_ctrl
;
150 static struct vmx_capability
{
155 #define VMX_SEGMENT_FIELD(seg) \
156 [VCPU_SREG_##seg] = { \
157 .selector = GUEST_##seg##_SELECTOR, \
158 .base = GUEST_##seg##_BASE, \
159 .limit = GUEST_##seg##_LIMIT, \
160 .ar_bytes = GUEST_##seg##_AR_BYTES, \
163 static struct kvm_vmx_segment_field
{
168 } kvm_vmx_segment_fields
[] = {
169 VMX_SEGMENT_FIELD(CS
),
170 VMX_SEGMENT_FIELD(DS
),
171 VMX_SEGMENT_FIELD(ES
),
172 VMX_SEGMENT_FIELD(FS
),
173 VMX_SEGMENT_FIELD(GS
),
174 VMX_SEGMENT_FIELD(SS
),
175 VMX_SEGMENT_FIELD(TR
),
176 VMX_SEGMENT_FIELD(LDTR
),
179 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
);
182 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
183 * away by decrementing the array size.
185 static const u32 vmx_msr_index
[] = {
187 MSR_SYSCALL_MASK
, MSR_LSTAR
, MSR_CSTAR
, MSR_KERNEL_GS_BASE
,
189 MSR_EFER
, MSR_K6_STAR
,
191 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
193 static void load_msrs(struct kvm_msr_entry
*e
, int n
)
197 for (i
= 0; i
< n
; ++i
)
198 wrmsrl(e
[i
].index
, e
[i
].data
);
201 static void save_msrs(struct kvm_msr_entry
*e
, int n
)
205 for (i
= 0; i
< n
; ++i
)
206 rdmsrl(e
[i
].index
, e
[i
].data
);
209 static inline int is_page_fault(u32 intr_info
)
211 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
212 INTR_INFO_VALID_MASK
)) ==
213 (INTR_TYPE_HARD_EXCEPTION
| PF_VECTOR
| INTR_INFO_VALID_MASK
);
216 static inline int is_no_device(u32 intr_info
)
218 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
219 INTR_INFO_VALID_MASK
)) ==
220 (INTR_TYPE_HARD_EXCEPTION
| NM_VECTOR
| INTR_INFO_VALID_MASK
);
223 static inline int is_invalid_opcode(u32 intr_info
)
225 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
226 INTR_INFO_VALID_MASK
)) ==
227 (INTR_TYPE_HARD_EXCEPTION
| UD_VECTOR
| INTR_INFO_VALID_MASK
);
230 static inline int is_external_interrupt(u32 intr_info
)
232 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
233 == (INTR_TYPE_EXT_INTR
| INTR_INFO_VALID_MASK
);
236 static inline int is_machine_check(u32 intr_info
)
238 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
239 INTR_INFO_VALID_MASK
)) ==
240 (INTR_TYPE_HARD_EXCEPTION
| MC_VECTOR
| INTR_INFO_VALID_MASK
);
243 static inline int cpu_has_vmx_msr_bitmap(void)
245 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_USE_MSR_BITMAPS
;
248 static inline int cpu_has_vmx_tpr_shadow(void)
250 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
;
253 static inline int vm_need_tpr_shadow(struct kvm
*kvm
)
255 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm
));
258 static inline int cpu_has_secondary_exec_ctrls(void)
260 return vmcs_config
.cpu_based_exec_ctrl
&
261 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
264 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
266 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
267 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
270 static inline bool cpu_has_vmx_flexpriority(void)
272 return cpu_has_vmx_tpr_shadow() &&
273 cpu_has_vmx_virtualize_apic_accesses();
276 static inline bool cpu_has_vmx_ept_execute_only(void)
278 return !!(vmx_capability
.ept
& VMX_EPT_EXECUTE_ONLY_BIT
);
281 static inline bool cpu_has_vmx_eptp_uncacheable(void)
283 return !!(vmx_capability
.ept
& VMX_EPTP_UC_BIT
);
286 static inline bool cpu_has_vmx_eptp_writeback(void)
288 return !!(vmx_capability
.ept
& VMX_EPTP_WB_BIT
);
291 static inline bool cpu_has_vmx_ept_2m_page(void)
293 return !!(vmx_capability
.ept
& VMX_EPT_2MB_PAGE_BIT
);
296 static inline int cpu_has_vmx_invept_individual_addr(void)
298 return !!(vmx_capability
.ept
& VMX_EPT_EXTENT_INDIVIDUAL_BIT
);
301 static inline int cpu_has_vmx_invept_context(void)
303 return !!(vmx_capability
.ept
& VMX_EPT_EXTENT_CONTEXT_BIT
);
306 static inline int cpu_has_vmx_invept_global(void)
308 return !!(vmx_capability
.ept
& VMX_EPT_EXTENT_GLOBAL_BIT
);
311 static inline int cpu_has_vmx_ept(void)
313 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
314 SECONDARY_EXEC_ENABLE_EPT
;
317 static inline int cpu_has_vmx_unrestricted_guest(void)
319 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
320 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
323 static inline int vm_need_virtualize_apic_accesses(struct kvm
*kvm
)
325 return flexpriority_enabled
&&
326 (cpu_has_vmx_virtualize_apic_accesses()) &&
327 (irqchip_in_kernel(kvm
));
330 static inline int cpu_has_vmx_vpid(void)
332 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
333 SECONDARY_EXEC_ENABLE_VPID
;
336 static inline int cpu_has_virtual_nmis(void)
338 return vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_VIRTUAL_NMIS
;
341 static inline bool report_flexpriority(void)
343 return flexpriority_enabled
;
346 static int __find_msr_index(struct vcpu_vmx
*vmx
, u32 msr
)
350 for (i
= 0; i
< vmx
->nmsrs
; ++i
)
351 if (vmx
->guest_msrs
[i
].index
== msr
)
356 static inline void __invvpid(int ext
, u16 vpid
, gva_t gva
)
362 } operand
= { vpid
, 0, gva
};
364 asm volatile (__ex(ASM_VMX_INVVPID
)
365 /* CF==1 or ZF==1 --> rc = -1 */
367 : : "a"(&operand
), "c"(ext
) : "cc", "memory");
370 static inline void __invept(int ext
, u64 eptp
, gpa_t gpa
)
374 } operand
= {eptp
, gpa
};
376 asm volatile (__ex(ASM_VMX_INVEPT
)
377 /* CF==1 or ZF==1 --> rc = -1 */
378 "; ja 1f ; ud2 ; 1:\n"
379 : : "a" (&operand
), "c" (ext
) : "cc", "memory");
382 static struct kvm_msr_entry
*find_msr_entry(struct vcpu_vmx
*vmx
, u32 msr
)
386 i
= __find_msr_index(vmx
, msr
);
388 return &vmx
->guest_msrs
[i
];
392 static void vmcs_clear(struct vmcs
*vmcs
)
394 u64 phys_addr
= __pa(vmcs
);
397 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX
) "; setna %0"
398 : "=g"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
401 printk(KERN_ERR
"kvm: vmclear fail: %p/%llx\n",
405 static void __vcpu_clear(void *arg
)
407 struct vcpu_vmx
*vmx
= arg
;
408 int cpu
= raw_smp_processor_id();
410 if (vmx
->vcpu
.cpu
== cpu
)
411 vmcs_clear(vmx
->vmcs
);
412 if (per_cpu(current_vmcs
, cpu
) == vmx
->vmcs
)
413 per_cpu(current_vmcs
, cpu
) = NULL
;
414 rdtscll(vmx
->vcpu
.arch
.host_tsc
);
415 list_del(&vmx
->local_vcpus_link
);
420 static void vcpu_clear(struct vcpu_vmx
*vmx
)
422 if (vmx
->vcpu
.cpu
== -1)
424 smp_call_function_single(vmx
->vcpu
.cpu
, __vcpu_clear
, vmx
, 1);
427 static inline void vpid_sync_vcpu_all(struct vcpu_vmx
*vmx
)
432 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT
, vmx
->vpid
, 0);
435 static inline void ept_sync_global(void)
437 if (cpu_has_vmx_invept_global())
438 __invept(VMX_EPT_EXTENT_GLOBAL
, 0, 0);
441 static inline void ept_sync_context(u64 eptp
)
444 if (cpu_has_vmx_invept_context())
445 __invept(VMX_EPT_EXTENT_CONTEXT
, eptp
, 0);
451 static inline void ept_sync_individual_addr(u64 eptp
, gpa_t gpa
)
454 if (cpu_has_vmx_invept_individual_addr())
455 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR
,
458 ept_sync_context(eptp
);
462 static unsigned long vmcs_readl(unsigned long field
)
466 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX
)
467 : "=a"(value
) : "d"(field
) : "cc");
471 static u16
vmcs_read16(unsigned long field
)
473 return vmcs_readl(field
);
476 static u32
vmcs_read32(unsigned long field
)
478 return vmcs_readl(field
);
481 static u64
vmcs_read64(unsigned long field
)
484 return vmcs_readl(field
);
486 return vmcs_readl(field
) | ((u64
)vmcs_readl(field
+1) << 32);
490 static noinline
void vmwrite_error(unsigned long field
, unsigned long value
)
492 printk(KERN_ERR
"vmwrite error: reg %lx value %lx (err %d)\n",
493 field
, value
, vmcs_read32(VM_INSTRUCTION_ERROR
));
497 static void vmcs_writel(unsigned long field
, unsigned long value
)
501 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX
) "; setna %0"
502 : "=q"(error
) : "a"(value
), "d"(field
) : "cc");
504 vmwrite_error(field
, value
);
507 static void vmcs_write16(unsigned long field
, u16 value
)
509 vmcs_writel(field
, value
);
512 static void vmcs_write32(unsigned long field
, u32 value
)
514 vmcs_writel(field
, value
);
517 static void vmcs_write64(unsigned long field
, u64 value
)
519 vmcs_writel(field
, value
);
520 #ifndef CONFIG_X86_64
522 vmcs_writel(field
+1, value
>> 32);
526 static void vmcs_clear_bits(unsigned long field
, u32 mask
)
528 vmcs_writel(field
, vmcs_readl(field
) & ~mask
);
531 static void vmcs_set_bits(unsigned long field
, u32 mask
)
533 vmcs_writel(field
, vmcs_readl(field
) | mask
);
536 static void update_exception_bitmap(struct kvm_vcpu
*vcpu
)
540 eb
= (1u << PF_VECTOR
) | (1u << UD_VECTOR
) | (1u << MC_VECTOR
);
541 if (!vcpu
->fpu_active
)
542 eb
|= 1u << NM_VECTOR
;
543 if (vcpu
->guest_debug
& KVM_GUESTDBG_ENABLE
) {
544 if (vcpu
->guest_debug
&
545 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
546 eb
|= 1u << DB_VECTOR
;
547 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
548 eb
|= 1u << BP_VECTOR
;
550 if (to_vmx(vcpu
)->rmode
.vm86_active
)
553 eb
&= ~(1u << PF_VECTOR
); /* bypass_guest_pf = 0 */
554 vmcs_write32(EXCEPTION_BITMAP
, eb
);
557 static void reload_tss(void)
560 * VT restores TR but not its size. Useless.
562 struct descriptor_table gdt
;
563 struct desc_struct
*descs
;
566 descs
= (void *)gdt
.base
;
567 descs
[GDT_ENTRY_TSS
].type
= 9; /* available TSS */
571 static void load_transition_efer(struct vcpu_vmx
*vmx
)
573 int efer_offset
= vmx
->msr_offset_efer
;
580 host_efer
= vmx
->host_msrs
[efer_offset
].data
;
581 guest_efer
= vmx
->guest_msrs
[efer_offset
].data
;
584 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
587 ignore_bits
= EFER_NX
| EFER_SCE
;
589 ignore_bits
|= EFER_LMA
| EFER_LME
;
590 /* SCE is meaningful only in long mode on Intel */
591 if (guest_efer
& EFER_LMA
)
592 ignore_bits
&= ~(u64
)EFER_SCE
;
594 if ((guest_efer
& ~ignore_bits
) == (host_efer
& ~ignore_bits
))
597 vmx
->host_state
.guest_efer_loaded
= 1;
598 guest_efer
&= ~ignore_bits
;
599 guest_efer
|= host_efer
& ignore_bits
;
600 wrmsrl(MSR_EFER
, guest_efer
);
601 vmx
->vcpu
.stat
.efer_reload
++;
604 static void reload_host_efer(struct vcpu_vmx
*vmx
)
606 if (vmx
->host_state
.guest_efer_loaded
) {
607 vmx
->host_state
.guest_efer_loaded
= 0;
608 load_msrs(vmx
->host_msrs
+ vmx
->msr_offset_efer
, 1);
612 static void vmx_save_host_state(struct kvm_vcpu
*vcpu
)
614 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
616 if (vmx
->host_state
.loaded
)
619 vmx
->host_state
.loaded
= 1;
621 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
622 * allow segment selectors with cpl > 0 or ti == 1.
624 vmx
->host_state
.ldt_sel
= kvm_read_ldt();
625 vmx
->host_state
.gs_ldt_reload_needed
= vmx
->host_state
.ldt_sel
;
626 vmx
->host_state
.fs_sel
= kvm_read_fs();
627 if (!(vmx
->host_state
.fs_sel
& 7)) {
628 vmcs_write16(HOST_FS_SELECTOR
, vmx
->host_state
.fs_sel
);
629 vmx
->host_state
.fs_reload_needed
= 0;
631 vmcs_write16(HOST_FS_SELECTOR
, 0);
632 vmx
->host_state
.fs_reload_needed
= 1;
634 vmx
->host_state
.gs_sel
= kvm_read_gs();
635 if (!(vmx
->host_state
.gs_sel
& 7))
636 vmcs_write16(HOST_GS_SELECTOR
, vmx
->host_state
.gs_sel
);
638 vmcs_write16(HOST_GS_SELECTOR
, 0);
639 vmx
->host_state
.gs_ldt_reload_needed
= 1;
643 vmcs_writel(HOST_FS_BASE
, read_msr(MSR_FS_BASE
));
644 vmcs_writel(HOST_GS_BASE
, read_msr(MSR_GS_BASE
));
646 vmcs_writel(HOST_FS_BASE
, segment_base(vmx
->host_state
.fs_sel
));
647 vmcs_writel(HOST_GS_BASE
, segment_base(vmx
->host_state
.gs_sel
));
651 if (is_long_mode(&vmx
->vcpu
))
652 save_msrs(vmx
->host_msrs
+
653 vmx
->msr_offset_kernel_gs_base
, 1);
656 load_msrs(vmx
->guest_msrs
, vmx
->save_nmsrs
);
657 load_transition_efer(vmx
);
660 static void __vmx_load_host_state(struct vcpu_vmx
*vmx
)
664 if (!vmx
->host_state
.loaded
)
667 ++vmx
->vcpu
.stat
.host_state_reload
;
668 vmx
->host_state
.loaded
= 0;
669 if (vmx
->host_state
.fs_reload_needed
)
670 kvm_load_fs(vmx
->host_state
.fs_sel
);
671 if (vmx
->host_state
.gs_ldt_reload_needed
) {
672 kvm_load_ldt(vmx
->host_state
.ldt_sel
);
674 * If we have to reload gs, we must take care to
675 * preserve our gs base.
677 local_irq_save(flags
);
678 kvm_load_gs(vmx
->host_state
.gs_sel
);
680 wrmsrl(MSR_GS_BASE
, vmcs_readl(HOST_GS_BASE
));
682 local_irq_restore(flags
);
685 save_msrs(vmx
->guest_msrs
, vmx
->save_nmsrs
);
686 load_msrs(vmx
->host_msrs
, vmx
->save_nmsrs
);
687 reload_host_efer(vmx
);
690 static void vmx_load_host_state(struct vcpu_vmx
*vmx
)
693 __vmx_load_host_state(vmx
);
698 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
699 * vcpu mutex is already taken.
701 static void vmx_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
703 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
704 u64 phys_addr
= __pa(vmx
->vmcs
);
705 u64 tsc_this
, delta
, new_offset
;
707 if (vcpu
->cpu
!= cpu
) {
709 kvm_migrate_timers(vcpu
);
710 vpid_sync_vcpu_all(vmx
);
712 list_add(&vmx
->local_vcpus_link
,
713 &per_cpu(vcpus_on_cpu
, cpu
));
717 if (per_cpu(current_vmcs
, cpu
) != vmx
->vmcs
) {
720 per_cpu(current_vmcs
, cpu
) = vmx
->vmcs
;
721 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX
) "; setna %0"
722 : "=g"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
725 printk(KERN_ERR
"kvm: vmptrld %p/%llx fail\n",
726 vmx
->vmcs
, phys_addr
);
729 if (vcpu
->cpu
!= cpu
) {
730 struct descriptor_table dt
;
731 unsigned long sysenter_esp
;
735 * Linux uses per-cpu TSS and GDT, so set these when switching
738 vmcs_writel(HOST_TR_BASE
, kvm_read_tr_base()); /* 22.2.4 */
740 vmcs_writel(HOST_GDTR_BASE
, dt
.base
); /* 22.2.4 */
742 rdmsrl(MSR_IA32_SYSENTER_ESP
, sysenter_esp
);
743 vmcs_writel(HOST_IA32_SYSENTER_ESP
, sysenter_esp
); /* 22.2.3 */
746 * Make sure the time stamp counter is monotonous.
749 if (tsc_this
< vcpu
->arch
.host_tsc
) {
750 delta
= vcpu
->arch
.host_tsc
- tsc_this
;
751 new_offset
= vmcs_read64(TSC_OFFSET
) + delta
;
752 vmcs_write64(TSC_OFFSET
, new_offset
);
757 static void vmx_vcpu_put(struct kvm_vcpu
*vcpu
)
759 __vmx_load_host_state(to_vmx(vcpu
));
762 static void vmx_fpu_activate(struct kvm_vcpu
*vcpu
)
764 if (vcpu
->fpu_active
)
766 vcpu
->fpu_active
= 1;
767 vmcs_clear_bits(GUEST_CR0
, X86_CR0_TS
);
768 if (vcpu
->arch
.cr0
& X86_CR0_TS
)
769 vmcs_set_bits(GUEST_CR0
, X86_CR0_TS
);
770 update_exception_bitmap(vcpu
);
773 static void vmx_fpu_deactivate(struct kvm_vcpu
*vcpu
)
775 if (!vcpu
->fpu_active
)
777 vcpu
->fpu_active
= 0;
778 vmcs_set_bits(GUEST_CR0
, X86_CR0_TS
);
779 update_exception_bitmap(vcpu
);
782 static unsigned long vmx_get_rflags(struct kvm_vcpu
*vcpu
)
784 return vmcs_readl(GUEST_RFLAGS
);
787 static void vmx_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
789 if (to_vmx(vcpu
)->rmode
.vm86_active
)
790 rflags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
791 vmcs_writel(GUEST_RFLAGS
, rflags
);
794 static u32
vmx_get_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
796 u32 interruptibility
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
799 if (interruptibility
& GUEST_INTR_STATE_STI
)
800 ret
|= X86_SHADOW_INT_STI
;
801 if (interruptibility
& GUEST_INTR_STATE_MOV_SS
)
802 ret
|= X86_SHADOW_INT_MOV_SS
;
807 static void vmx_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
809 u32 interruptibility_old
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
810 u32 interruptibility
= interruptibility_old
;
812 interruptibility
&= ~(GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
);
814 if (mask
& X86_SHADOW_INT_MOV_SS
)
815 interruptibility
|= GUEST_INTR_STATE_MOV_SS
;
816 if (mask
& X86_SHADOW_INT_STI
)
817 interruptibility
|= GUEST_INTR_STATE_STI
;
819 if ((interruptibility
!= interruptibility_old
))
820 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, interruptibility
);
823 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
827 rip
= kvm_rip_read(vcpu
);
828 rip
+= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
829 kvm_rip_write(vcpu
, rip
);
831 /* skipping an emulated instruction also counts */
832 vmx_set_interrupt_shadow(vcpu
, 0);
835 static void vmx_queue_exception(struct kvm_vcpu
*vcpu
, unsigned nr
,
836 bool has_error_code
, u32 error_code
)
838 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
839 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
841 if (has_error_code
) {
842 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
, error_code
);
843 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
846 if (vmx
->rmode
.vm86_active
) {
847 vmx
->rmode
.irq
.pending
= true;
848 vmx
->rmode
.irq
.vector
= nr
;
849 vmx
->rmode
.irq
.rip
= kvm_rip_read(vcpu
);
850 if (kvm_exception_is_soft(nr
))
851 vmx
->rmode
.irq
.rip
+=
852 vmx
->vcpu
.arch
.event_exit_inst_len
;
853 intr_info
|= INTR_TYPE_SOFT_INTR
;
854 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
855 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
, 1);
856 kvm_rip_write(vcpu
, vmx
->rmode
.irq
.rip
- 1);
860 if (kvm_exception_is_soft(nr
)) {
861 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
862 vmx
->vcpu
.arch
.event_exit_inst_len
);
863 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
865 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
867 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
871 * Swap MSR entry in host/guest MSR entry array.
874 static void move_msr_up(struct vcpu_vmx
*vmx
, int from
, int to
)
876 struct kvm_msr_entry tmp
;
878 tmp
= vmx
->guest_msrs
[to
];
879 vmx
->guest_msrs
[to
] = vmx
->guest_msrs
[from
];
880 vmx
->guest_msrs
[from
] = tmp
;
881 tmp
= vmx
->host_msrs
[to
];
882 vmx
->host_msrs
[to
] = vmx
->host_msrs
[from
];
883 vmx
->host_msrs
[from
] = tmp
;
888 * Set up the vmcs to automatically save and restore system
889 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
890 * mode, as fiddling with msrs is very expensive.
892 static void setup_msrs(struct vcpu_vmx
*vmx
)
895 unsigned long *msr_bitmap
;
897 vmx_load_host_state(vmx
);
900 if (is_long_mode(&vmx
->vcpu
)) {
903 index
= __find_msr_index(vmx
, MSR_SYSCALL_MASK
);
905 move_msr_up(vmx
, index
, save_nmsrs
++);
906 index
= __find_msr_index(vmx
, MSR_LSTAR
);
908 move_msr_up(vmx
, index
, save_nmsrs
++);
909 index
= __find_msr_index(vmx
, MSR_CSTAR
);
911 move_msr_up(vmx
, index
, save_nmsrs
++);
912 index
= __find_msr_index(vmx
, MSR_KERNEL_GS_BASE
);
914 move_msr_up(vmx
, index
, save_nmsrs
++);
916 * MSR_K6_STAR is only needed on long mode guests, and only
917 * if efer.sce is enabled.
919 index
= __find_msr_index(vmx
, MSR_K6_STAR
);
920 if ((index
>= 0) && (vmx
->vcpu
.arch
.shadow_efer
& EFER_SCE
))
921 move_msr_up(vmx
, index
, save_nmsrs
++);
924 vmx
->save_nmsrs
= save_nmsrs
;
927 vmx
->msr_offset_kernel_gs_base
=
928 __find_msr_index(vmx
, MSR_KERNEL_GS_BASE
);
930 vmx
->msr_offset_efer
= __find_msr_index(vmx
, MSR_EFER
);
932 if (cpu_has_vmx_msr_bitmap()) {
933 if (is_long_mode(&vmx
->vcpu
))
934 msr_bitmap
= vmx_msr_bitmap_longmode
;
936 msr_bitmap
= vmx_msr_bitmap_legacy
;
938 vmcs_write64(MSR_BITMAP
, __pa(msr_bitmap
));
943 * reads and returns guest's timestamp counter "register"
944 * guest_tsc = host_tsc + tsc_offset -- 21.3
946 static u64
guest_read_tsc(void)
948 u64 host_tsc
, tsc_offset
;
951 tsc_offset
= vmcs_read64(TSC_OFFSET
);
952 return host_tsc
+ tsc_offset
;
956 * writes 'guest_tsc' into guest's timestamp counter "register"
957 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
959 static void guest_write_tsc(u64 guest_tsc
, u64 host_tsc
)
961 vmcs_write64(TSC_OFFSET
, guest_tsc
- host_tsc
);
965 * Reads an msr value (of 'msr_index') into 'pdata'.
966 * Returns 0 on success, non-0 otherwise.
967 * Assumes vcpu_load() was already called.
969 static int vmx_get_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
972 struct kvm_msr_entry
*msr
;
975 printk(KERN_ERR
"BUG: get_msr called with NULL pdata\n");
982 data
= vmcs_readl(GUEST_FS_BASE
);
985 data
= vmcs_readl(GUEST_GS_BASE
);
988 return kvm_get_msr_common(vcpu
, msr_index
, pdata
);
991 data
= guest_read_tsc();
993 case MSR_IA32_SYSENTER_CS
:
994 data
= vmcs_read32(GUEST_SYSENTER_CS
);
996 case MSR_IA32_SYSENTER_EIP
:
997 data
= vmcs_readl(GUEST_SYSENTER_EIP
);
999 case MSR_IA32_SYSENTER_ESP
:
1000 data
= vmcs_readl(GUEST_SYSENTER_ESP
);
1003 vmx_load_host_state(to_vmx(vcpu
));
1004 msr
= find_msr_entry(to_vmx(vcpu
), msr_index
);
1009 return kvm_get_msr_common(vcpu
, msr_index
, pdata
);
1017 * Writes msr value into into the appropriate "register".
1018 * Returns 0 on success, non-0 otherwise.
1019 * Assumes vcpu_load() was already called.
1021 static int vmx_set_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64 data
)
1023 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1024 struct kvm_msr_entry
*msr
;
1028 switch (msr_index
) {
1030 vmx_load_host_state(vmx
);
1031 ret
= kvm_set_msr_common(vcpu
, msr_index
, data
);
1033 #ifdef CONFIG_X86_64
1035 vmcs_writel(GUEST_FS_BASE
, data
);
1038 vmcs_writel(GUEST_GS_BASE
, data
);
1041 case MSR_IA32_SYSENTER_CS
:
1042 vmcs_write32(GUEST_SYSENTER_CS
, data
);
1044 case MSR_IA32_SYSENTER_EIP
:
1045 vmcs_writel(GUEST_SYSENTER_EIP
, data
);
1047 case MSR_IA32_SYSENTER_ESP
:
1048 vmcs_writel(GUEST_SYSENTER_ESP
, data
);
1052 guest_write_tsc(data
, host_tsc
);
1054 case MSR_IA32_CR_PAT
:
1055 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
1056 vmcs_write64(GUEST_IA32_PAT
, data
);
1057 vcpu
->arch
.pat
= data
;
1060 /* Otherwise falls through to kvm_set_msr_common */
1062 vmx_load_host_state(vmx
);
1063 msr
= find_msr_entry(vmx
, msr_index
);
1068 ret
= kvm_set_msr_common(vcpu
, msr_index
, data
);
1074 static void vmx_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
1076 __set_bit(reg
, (unsigned long *)&vcpu
->arch
.regs_avail
);
1079 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = vmcs_readl(GUEST_RSP
);
1082 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = vmcs_readl(GUEST_RIP
);
1084 case VCPU_EXREG_PDPTR
:
1086 ept_save_pdptrs(vcpu
);
1093 static int set_guest_debug(struct kvm_vcpu
*vcpu
, struct kvm_guest_debug
*dbg
)
1095 int old_debug
= vcpu
->guest_debug
;
1096 unsigned long flags
;
1098 vcpu
->guest_debug
= dbg
->control
;
1099 if (!(vcpu
->guest_debug
& KVM_GUESTDBG_ENABLE
))
1100 vcpu
->guest_debug
= 0;
1102 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
)
1103 vmcs_writel(GUEST_DR7
, dbg
->arch
.debugreg
[7]);
1105 vmcs_writel(GUEST_DR7
, vcpu
->arch
.dr7
);
1107 flags
= vmcs_readl(GUEST_RFLAGS
);
1108 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
1109 flags
|= X86_EFLAGS_TF
| X86_EFLAGS_RF
;
1110 else if (old_debug
& KVM_GUESTDBG_SINGLESTEP
)
1111 flags
&= ~(X86_EFLAGS_TF
| X86_EFLAGS_RF
);
1112 vmcs_writel(GUEST_RFLAGS
, flags
);
1114 update_exception_bitmap(vcpu
);
1119 static __init
int cpu_has_kvm_support(void)
1121 return cpu_has_vmx();
1124 static __init
int vmx_disabled_by_bios(void)
1128 rdmsrl(MSR_IA32_FEATURE_CONTROL
, msr
);
1129 return (msr
& (FEATURE_CONTROL_LOCKED
|
1130 FEATURE_CONTROL_VMXON_ENABLED
))
1131 == FEATURE_CONTROL_LOCKED
;
1132 /* locked but not enabled */
1135 static void hardware_enable(void *garbage
)
1137 int cpu
= raw_smp_processor_id();
1138 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
1141 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu
, cpu
));
1142 rdmsrl(MSR_IA32_FEATURE_CONTROL
, old
);
1143 if ((old
& (FEATURE_CONTROL_LOCKED
|
1144 FEATURE_CONTROL_VMXON_ENABLED
))
1145 != (FEATURE_CONTROL_LOCKED
|
1146 FEATURE_CONTROL_VMXON_ENABLED
))
1147 /* enable and lock */
1148 wrmsrl(MSR_IA32_FEATURE_CONTROL
, old
|
1149 FEATURE_CONTROL_LOCKED
|
1150 FEATURE_CONTROL_VMXON_ENABLED
);
1151 write_cr4(read_cr4() | X86_CR4_VMXE
); /* FIXME: not cpu hotplug safe */
1152 asm volatile (ASM_VMX_VMXON_RAX
1153 : : "a"(&phys_addr
), "m"(phys_addr
)
1157 static void vmclear_local_vcpus(void)
1159 int cpu
= raw_smp_processor_id();
1160 struct vcpu_vmx
*vmx
, *n
;
1162 list_for_each_entry_safe(vmx
, n
, &per_cpu(vcpus_on_cpu
, cpu
),
1168 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1171 static void kvm_cpu_vmxoff(void)
1173 asm volatile (__ex(ASM_VMX_VMXOFF
) : : : "cc");
1174 write_cr4(read_cr4() & ~X86_CR4_VMXE
);
1177 static void hardware_disable(void *garbage
)
1179 vmclear_local_vcpus();
1183 static __init
int adjust_vmx_controls(u32 ctl_min
, u32 ctl_opt
,
1184 u32 msr
, u32
*result
)
1186 u32 vmx_msr_low
, vmx_msr_high
;
1187 u32 ctl
= ctl_min
| ctl_opt
;
1189 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
1191 ctl
&= vmx_msr_high
; /* bit == 0 in high word ==> must be zero */
1192 ctl
|= vmx_msr_low
; /* bit == 1 in low word ==> must be one */
1194 /* Ensure minimum (required) set of control bits are supported. */
1202 static __init
int setup_vmcs_config(struct vmcs_config
*vmcs_conf
)
1204 u32 vmx_msr_low
, vmx_msr_high
;
1205 u32 min
, opt
, min2
, opt2
;
1206 u32 _pin_based_exec_control
= 0;
1207 u32 _cpu_based_exec_control
= 0;
1208 u32 _cpu_based_2nd_exec_control
= 0;
1209 u32 _vmexit_control
= 0;
1210 u32 _vmentry_control
= 0;
1212 min
= PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
;
1213 opt
= PIN_BASED_VIRTUAL_NMIS
;
1214 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PINBASED_CTLS
,
1215 &_pin_based_exec_control
) < 0)
1218 min
= CPU_BASED_HLT_EXITING
|
1219 #ifdef CONFIG_X86_64
1220 CPU_BASED_CR8_LOAD_EXITING
|
1221 CPU_BASED_CR8_STORE_EXITING
|
1223 CPU_BASED_CR3_LOAD_EXITING
|
1224 CPU_BASED_CR3_STORE_EXITING
|
1225 CPU_BASED_USE_IO_BITMAPS
|
1226 CPU_BASED_MOV_DR_EXITING
|
1227 CPU_BASED_USE_TSC_OFFSETING
|
1228 CPU_BASED_INVLPG_EXITING
;
1229 opt
= CPU_BASED_TPR_SHADOW
|
1230 CPU_BASED_USE_MSR_BITMAPS
|
1231 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
1232 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
1233 &_cpu_based_exec_control
) < 0)
1235 #ifdef CONFIG_X86_64
1236 if ((_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
1237 _cpu_based_exec_control
&= ~CPU_BASED_CR8_LOAD_EXITING
&
1238 ~CPU_BASED_CR8_STORE_EXITING
;
1240 if (_cpu_based_exec_control
& CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) {
1242 opt2
= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
1243 SECONDARY_EXEC_WBINVD_EXITING
|
1244 SECONDARY_EXEC_ENABLE_VPID
|
1245 SECONDARY_EXEC_ENABLE_EPT
|
1246 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
1247 if (adjust_vmx_controls(min2
, opt2
,
1248 MSR_IA32_VMX_PROCBASED_CTLS2
,
1249 &_cpu_based_2nd_exec_control
) < 0)
1252 #ifndef CONFIG_X86_64
1253 if (!(_cpu_based_2nd_exec_control
&
1254 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
1255 _cpu_based_exec_control
&= ~CPU_BASED_TPR_SHADOW
;
1257 if (_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) {
1258 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1260 min
&= ~(CPU_BASED_CR3_LOAD_EXITING
|
1261 CPU_BASED_CR3_STORE_EXITING
|
1262 CPU_BASED_INVLPG_EXITING
);
1263 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
1264 &_cpu_based_exec_control
) < 0)
1266 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP
,
1267 vmx_capability
.ept
, vmx_capability
.vpid
);
1271 #ifdef CONFIG_X86_64
1272 min
|= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
1274 opt
= VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_LOAD_IA32_PAT
;
1275 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_EXIT_CTLS
,
1276 &_vmexit_control
) < 0)
1280 opt
= VM_ENTRY_LOAD_IA32_PAT
;
1281 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_ENTRY_CTLS
,
1282 &_vmentry_control
) < 0)
1285 rdmsr(MSR_IA32_VMX_BASIC
, vmx_msr_low
, vmx_msr_high
);
1287 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1288 if ((vmx_msr_high
& 0x1fff) > PAGE_SIZE
)
1291 #ifdef CONFIG_X86_64
1292 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1293 if (vmx_msr_high
& (1u<<16))
1297 /* Require Write-Back (WB) memory type for VMCS accesses. */
1298 if (((vmx_msr_high
>> 18) & 15) != 6)
1301 vmcs_conf
->size
= vmx_msr_high
& 0x1fff;
1302 vmcs_conf
->order
= get_order(vmcs_config
.size
);
1303 vmcs_conf
->revision_id
= vmx_msr_low
;
1305 vmcs_conf
->pin_based_exec_ctrl
= _pin_based_exec_control
;
1306 vmcs_conf
->cpu_based_exec_ctrl
= _cpu_based_exec_control
;
1307 vmcs_conf
->cpu_based_2nd_exec_ctrl
= _cpu_based_2nd_exec_control
;
1308 vmcs_conf
->vmexit_ctrl
= _vmexit_control
;
1309 vmcs_conf
->vmentry_ctrl
= _vmentry_control
;
1314 static struct vmcs
*alloc_vmcs_cpu(int cpu
)
1316 int node
= cpu_to_node(cpu
);
1320 pages
= alloc_pages_exact_node(node
, GFP_KERNEL
, vmcs_config
.order
);
1323 vmcs
= page_address(pages
);
1324 memset(vmcs
, 0, vmcs_config
.size
);
1325 vmcs
->revision_id
= vmcs_config
.revision_id
; /* vmcs revision id */
1329 static struct vmcs
*alloc_vmcs(void)
1331 return alloc_vmcs_cpu(raw_smp_processor_id());
1334 static void free_vmcs(struct vmcs
*vmcs
)
1336 free_pages((unsigned long)vmcs
, vmcs_config
.order
);
1339 static void free_kvm_area(void)
1343 for_each_online_cpu(cpu
)
1344 free_vmcs(per_cpu(vmxarea
, cpu
));
1347 static __init
int alloc_kvm_area(void)
1351 for_each_online_cpu(cpu
) {
1354 vmcs
= alloc_vmcs_cpu(cpu
);
1360 per_cpu(vmxarea
, cpu
) = vmcs
;
1365 static __init
int hardware_setup(void)
1367 if (setup_vmcs_config(&vmcs_config
) < 0)
1370 if (boot_cpu_has(X86_FEATURE_NX
))
1371 kvm_enable_efer_bits(EFER_NX
);
1373 if (!cpu_has_vmx_vpid())
1376 if (!cpu_has_vmx_ept()) {
1378 enable_unrestricted_guest
= 0;
1381 if (!cpu_has_vmx_unrestricted_guest())
1382 enable_unrestricted_guest
= 0;
1384 if (!cpu_has_vmx_flexpriority())
1385 flexpriority_enabled
= 0;
1387 if (!cpu_has_vmx_tpr_shadow())
1388 kvm_x86_ops
->update_cr8_intercept
= NULL
;
1390 if (enable_ept
&& !cpu_has_vmx_ept_2m_page())
1391 kvm_disable_largepages();
1393 return alloc_kvm_area();
1396 static __exit
void hardware_unsetup(void)
1401 static void fix_pmode_dataseg(int seg
, struct kvm_save_segment
*save
)
1403 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
1405 if (vmcs_readl(sf
->base
) == save
->base
&& (save
->base
& AR_S_MASK
)) {
1406 vmcs_write16(sf
->selector
, save
->selector
);
1407 vmcs_writel(sf
->base
, save
->base
);
1408 vmcs_write32(sf
->limit
, save
->limit
);
1409 vmcs_write32(sf
->ar_bytes
, save
->ar
);
1411 u32 dpl
= (vmcs_read16(sf
->selector
) & SELECTOR_RPL_MASK
)
1413 vmcs_write32(sf
->ar_bytes
, 0x93 | dpl
);
1417 static void enter_pmode(struct kvm_vcpu
*vcpu
)
1419 unsigned long flags
;
1420 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1422 vmx
->emulation_required
= 1;
1423 vmx
->rmode
.vm86_active
= 0;
1425 vmcs_writel(GUEST_TR_BASE
, vmx
->rmode
.tr
.base
);
1426 vmcs_write32(GUEST_TR_LIMIT
, vmx
->rmode
.tr
.limit
);
1427 vmcs_write32(GUEST_TR_AR_BYTES
, vmx
->rmode
.tr
.ar
);
1429 flags
= vmcs_readl(GUEST_RFLAGS
);
1430 flags
&= ~(X86_EFLAGS_IOPL
| X86_EFLAGS_VM
);
1431 flags
|= (vmx
->rmode
.save_iopl
<< IOPL_SHIFT
);
1432 vmcs_writel(GUEST_RFLAGS
, flags
);
1434 vmcs_writel(GUEST_CR4
, (vmcs_readl(GUEST_CR4
) & ~X86_CR4_VME
) |
1435 (vmcs_readl(CR4_READ_SHADOW
) & X86_CR4_VME
));
1437 update_exception_bitmap(vcpu
);
1439 if (emulate_invalid_guest_state
)
1442 fix_pmode_dataseg(VCPU_SREG_ES
, &vmx
->rmode
.es
);
1443 fix_pmode_dataseg(VCPU_SREG_DS
, &vmx
->rmode
.ds
);
1444 fix_pmode_dataseg(VCPU_SREG_GS
, &vmx
->rmode
.gs
);
1445 fix_pmode_dataseg(VCPU_SREG_FS
, &vmx
->rmode
.fs
);
1447 vmcs_write16(GUEST_SS_SELECTOR
, 0);
1448 vmcs_write32(GUEST_SS_AR_BYTES
, 0x93);
1450 vmcs_write16(GUEST_CS_SELECTOR
,
1451 vmcs_read16(GUEST_CS_SELECTOR
) & ~SELECTOR_RPL_MASK
);
1452 vmcs_write32(GUEST_CS_AR_BYTES
, 0x9b);
1455 static gva_t
rmode_tss_base(struct kvm
*kvm
)
1457 if (!kvm
->arch
.tss_addr
) {
1458 gfn_t base_gfn
= kvm
->memslots
[0].base_gfn
+
1459 kvm
->memslots
[0].npages
- 3;
1460 return base_gfn
<< PAGE_SHIFT
;
1462 return kvm
->arch
.tss_addr
;
1465 static void fix_rmode_seg(int seg
, struct kvm_save_segment
*save
)
1467 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
1469 save
->selector
= vmcs_read16(sf
->selector
);
1470 save
->base
= vmcs_readl(sf
->base
);
1471 save
->limit
= vmcs_read32(sf
->limit
);
1472 save
->ar
= vmcs_read32(sf
->ar_bytes
);
1473 vmcs_write16(sf
->selector
, save
->base
>> 4);
1474 vmcs_write32(sf
->base
, save
->base
& 0xfffff);
1475 vmcs_write32(sf
->limit
, 0xffff);
1476 vmcs_write32(sf
->ar_bytes
, 0xf3);
1479 static void enter_rmode(struct kvm_vcpu
*vcpu
)
1481 unsigned long flags
;
1482 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1484 if (enable_unrestricted_guest
)
1487 vmx
->emulation_required
= 1;
1488 vmx
->rmode
.vm86_active
= 1;
1490 vmx
->rmode
.tr
.base
= vmcs_readl(GUEST_TR_BASE
);
1491 vmcs_writel(GUEST_TR_BASE
, rmode_tss_base(vcpu
->kvm
));
1493 vmx
->rmode
.tr
.limit
= vmcs_read32(GUEST_TR_LIMIT
);
1494 vmcs_write32(GUEST_TR_LIMIT
, RMODE_TSS_SIZE
- 1);
1496 vmx
->rmode
.tr
.ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
1497 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
1499 flags
= vmcs_readl(GUEST_RFLAGS
);
1500 vmx
->rmode
.save_iopl
1501 = (flags
& X86_EFLAGS_IOPL
) >> IOPL_SHIFT
;
1503 flags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
1505 vmcs_writel(GUEST_RFLAGS
, flags
);
1506 vmcs_writel(GUEST_CR4
, vmcs_readl(GUEST_CR4
) | X86_CR4_VME
);
1507 update_exception_bitmap(vcpu
);
1509 if (emulate_invalid_guest_state
)
1510 goto continue_rmode
;
1512 vmcs_write16(GUEST_SS_SELECTOR
, vmcs_readl(GUEST_SS_BASE
) >> 4);
1513 vmcs_write32(GUEST_SS_LIMIT
, 0xffff);
1514 vmcs_write32(GUEST_SS_AR_BYTES
, 0xf3);
1516 vmcs_write32(GUEST_CS_AR_BYTES
, 0xf3);
1517 vmcs_write32(GUEST_CS_LIMIT
, 0xffff);
1518 if (vmcs_readl(GUEST_CS_BASE
) == 0xffff0000)
1519 vmcs_writel(GUEST_CS_BASE
, 0xf0000);
1520 vmcs_write16(GUEST_CS_SELECTOR
, vmcs_readl(GUEST_CS_BASE
) >> 4);
1522 fix_rmode_seg(VCPU_SREG_ES
, &vmx
->rmode
.es
);
1523 fix_rmode_seg(VCPU_SREG_DS
, &vmx
->rmode
.ds
);
1524 fix_rmode_seg(VCPU_SREG_GS
, &vmx
->rmode
.gs
);
1525 fix_rmode_seg(VCPU_SREG_FS
, &vmx
->rmode
.fs
);
1528 kvm_mmu_reset_context(vcpu
);
1529 init_rmode(vcpu
->kvm
);
1532 static void vmx_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
1534 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1535 struct kvm_msr_entry
*msr
= find_msr_entry(vmx
, MSR_EFER
);
1537 vcpu
->arch
.shadow_efer
= efer
;
1540 if (efer
& EFER_LMA
) {
1541 vmcs_write32(VM_ENTRY_CONTROLS
,
1542 vmcs_read32(VM_ENTRY_CONTROLS
) |
1543 VM_ENTRY_IA32E_MODE
);
1546 vmcs_write32(VM_ENTRY_CONTROLS
,
1547 vmcs_read32(VM_ENTRY_CONTROLS
) &
1548 ~VM_ENTRY_IA32E_MODE
);
1550 msr
->data
= efer
& ~EFER_LME
;
1555 #ifdef CONFIG_X86_64
1557 static void enter_lmode(struct kvm_vcpu
*vcpu
)
1561 guest_tr_ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
1562 if ((guest_tr_ar
& AR_TYPE_MASK
) != AR_TYPE_BUSY_64_TSS
) {
1563 printk(KERN_DEBUG
"%s: tss fixup for long mode. \n",
1565 vmcs_write32(GUEST_TR_AR_BYTES
,
1566 (guest_tr_ar
& ~AR_TYPE_MASK
)
1567 | AR_TYPE_BUSY_64_TSS
);
1569 vcpu
->arch
.shadow_efer
|= EFER_LMA
;
1570 vmx_set_efer(vcpu
, vcpu
->arch
.shadow_efer
);
1573 static void exit_lmode(struct kvm_vcpu
*vcpu
)
1575 vcpu
->arch
.shadow_efer
&= ~EFER_LMA
;
1577 vmcs_write32(VM_ENTRY_CONTROLS
,
1578 vmcs_read32(VM_ENTRY_CONTROLS
)
1579 & ~VM_ENTRY_IA32E_MODE
);
1584 static void vmx_flush_tlb(struct kvm_vcpu
*vcpu
)
1586 vpid_sync_vcpu_all(to_vmx(vcpu
));
1588 ept_sync_context(construct_eptp(vcpu
->arch
.mmu
.root_hpa
));
1591 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
1593 vcpu
->arch
.cr4
&= KVM_GUEST_CR4_MASK
;
1594 vcpu
->arch
.cr4
|= vmcs_readl(GUEST_CR4
) & ~KVM_GUEST_CR4_MASK
;
1597 static void ept_load_pdptrs(struct kvm_vcpu
*vcpu
)
1599 if (!test_bit(VCPU_EXREG_PDPTR
,
1600 (unsigned long *)&vcpu
->arch
.regs_dirty
))
1603 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
1604 vmcs_write64(GUEST_PDPTR0
, vcpu
->arch
.pdptrs
[0]);
1605 vmcs_write64(GUEST_PDPTR1
, vcpu
->arch
.pdptrs
[1]);
1606 vmcs_write64(GUEST_PDPTR2
, vcpu
->arch
.pdptrs
[2]);
1607 vmcs_write64(GUEST_PDPTR3
, vcpu
->arch
.pdptrs
[3]);
1611 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
)
1613 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
1614 vcpu
->arch
.pdptrs
[0] = vmcs_read64(GUEST_PDPTR0
);
1615 vcpu
->arch
.pdptrs
[1] = vmcs_read64(GUEST_PDPTR1
);
1616 vcpu
->arch
.pdptrs
[2] = vmcs_read64(GUEST_PDPTR2
);
1617 vcpu
->arch
.pdptrs
[3] = vmcs_read64(GUEST_PDPTR3
);
1620 __set_bit(VCPU_EXREG_PDPTR
,
1621 (unsigned long *)&vcpu
->arch
.regs_avail
);
1622 __set_bit(VCPU_EXREG_PDPTR
,
1623 (unsigned long *)&vcpu
->arch
.regs_dirty
);
1626 static void vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
);
1628 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0
,
1630 struct kvm_vcpu
*vcpu
)
1632 if (!(cr0
& X86_CR0_PG
)) {
1633 /* From paging/starting to nonpaging */
1634 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
1635 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) |
1636 (CPU_BASED_CR3_LOAD_EXITING
|
1637 CPU_BASED_CR3_STORE_EXITING
));
1638 vcpu
->arch
.cr0
= cr0
;
1639 vmx_set_cr4(vcpu
, vcpu
->arch
.cr4
);
1640 *hw_cr0
&= ~X86_CR0_WP
;
1641 } else if (!is_paging(vcpu
)) {
1642 /* From nonpaging to paging */
1643 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
1644 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) &
1645 ~(CPU_BASED_CR3_LOAD_EXITING
|
1646 CPU_BASED_CR3_STORE_EXITING
));
1647 vcpu
->arch
.cr0
= cr0
;
1648 vmx_set_cr4(vcpu
, vcpu
->arch
.cr4
);
1649 if (!(vcpu
->arch
.cr0
& X86_CR0_WP
))
1650 *hw_cr0
&= ~X86_CR0_WP
;
1654 static void ept_update_paging_mode_cr4(unsigned long *hw_cr4
,
1655 struct kvm_vcpu
*vcpu
)
1657 if (!is_paging(vcpu
)) {
1658 *hw_cr4
&= ~X86_CR4_PAE
;
1659 *hw_cr4
|= X86_CR4_PSE
;
1660 } else if (!(vcpu
->arch
.cr4
& X86_CR4_PAE
))
1661 *hw_cr4
&= ~X86_CR4_PAE
;
1664 static void vmx_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
1666 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1667 unsigned long hw_cr0
;
1669 if (enable_unrestricted_guest
)
1670 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST
)
1671 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST
;
1673 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK
) | KVM_VM_CR0_ALWAYS_ON
;
1675 vmx_fpu_deactivate(vcpu
);
1677 if (vmx
->rmode
.vm86_active
&& (cr0
& X86_CR0_PE
))
1680 if (!vmx
->rmode
.vm86_active
&& !(cr0
& X86_CR0_PE
))
1683 #ifdef CONFIG_X86_64
1684 if (vcpu
->arch
.shadow_efer
& EFER_LME
) {
1685 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
))
1687 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
))
1693 ept_update_paging_mode_cr0(&hw_cr0
, cr0
, vcpu
);
1695 vmcs_writel(CR0_READ_SHADOW
, cr0
);
1696 vmcs_writel(GUEST_CR0
, hw_cr0
);
1697 vcpu
->arch
.cr0
= cr0
;
1699 if (!(cr0
& X86_CR0_TS
) || !(cr0
& X86_CR0_PE
))
1700 vmx_fpu_activate(vcpu
);
1703 static u64
construct_eptp(unsigned long root_hpa
)
1707 /* TODO write the value reading from MSR */
1708 eptp
= VMX_EPT_DEFAULT_MT
|
1709 VMX_EPT_DEFAULT_GAW
<< VMX_EPT_GAW_EPTP_SHIFT
;
1710 eptp
|= (root_hpa
& PAGE_MASK
);
1715 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
)
1717 unsigned long guest_cr3
;
1722 eptp
= construct_eptp(cr3
);
1723 vmcs_write64(EPT_POINTER
, eptp
);
1724 guest_cr3
= is_paging(vcpu
) ? vcpu
->arch
.cr3
:
1725 vcpu
->kvm
->arch
.ept_identity_map_addr
;
1728 vmx_flush_tlb(vcpu
);
1729 vmcs_writel(GUEST_CR3
, guest_cr3
);
1730 if (vcpu
->arch
.cr0
& X86_CR0_PE
)
1731 vmx_fpu_deactivate(vcpu
);
1734 static void vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
1736 unsigned long hw_cr4
= cr4
| (to_vmx(vcpu
)->rmode
.vm86_active
?
1737 KVM_RMODE_VM_CR4_ALWAYS_ON
: KVM_PMODE_VM_CR4_ALWAYS_ON
);
1739 vcpu
->arch
.cr4
= cr4
;
1741 ept_update_paging_mode_cr4(&hw_cr4
, vcpu
);
1743 vmcs_writel(CR4_READ_SHADOW
, cr4
);
1744 vmcs_writel(GUEST_CR4
, hw_cr4
);
1747 static u64
vmx_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
1749 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
1751 return vmcs_readl(sf
->base
);
1754 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
1755 struct kvm_segment
*var
, int seg
)
1757 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
1760 var
->base
= vmcs_readl(sf
->base
);
1761 var
->limit
= vmcs_read32(sf
->limit
);
1762 var
->selector
= vmcs_read16(sf
->selector
);
1763 ar
= vmcs_read32(sf
->ar_bytes
);
1764 if ((ar
& AR_UNUSABLE_MASK
) && !emulate_invalid_guest_state
)
1766 var
->type
= ar
& 15;
1767 var
->s
= (ar
>> 4) & 1;
1768 var
->dpl
= (ar
>> 5) & 3;
1769 var
->present
= (ar
>> 7) & 1;
1770 var
->avl
= (ar
>> 12) & 1;
1771 var
->l
= (ar
>> 13) & 1;
1772 var
->db
= (ar
>> 14) & 1;
1773 var
->g
= (ar
>> 15) & 1;
1774 var
->unusable
= (ar
>> 16) & 1;
1777 static int vmx_get_cpl(struct kvm_vcpu
*vcpu
)
1779 if (!(vcpu
->arch
.cr0
& X86_CR0_PE
)) /* if real mode */
1782 if (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
) /* if virtual 8086 */
1785 return vmcs_read16(GUEST_CS_SELECTOR
) & 3;
1788 static u32
vmx_segment_access_rights(struct kvm_segment
*var
)
1795 ar
= var
->type
& 15;
1796 ar
|= (var
->s
& 1) << 4;
1797 ar
|= (var
->dpl
& 3) << 5;
1798 ar
|= (var
->present
& 1) << 7;
1799 ar
|= (var
->avl
& 1) << 12;
1800 ar
|= (var
->l
& 1) << 13;
1801 ar
|= (var
->db
& 1) << 14;
1802 ar
|= (var
->g
& 1) << 15;
1804 if (ar
== 0) /* a 0 value means unusable */
1805 ar
= AR_UNUSABLE_MASK
;
1810 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
1811 struct kvm_segment
*var
, int seg
)
1813 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1814 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
1817 if (vmx
->rmode
.vm86_active
&& seg
== VCPU_SREG_TR
) {
1818 vmx
->rmode
.tr
.selector
= var
->selector
;
1819 vmx
->rmode
.tr
.base
= var
->base
;
1820 vmx
->rmode
.tr
.limit
= var
->limit
;
1821 vmx
->rmode
.tr
.ar
= vmx_segment_access_rights(var
);
1824 vmcs_writel(sf
->base
, var
->base
);
1825 vmcs_write32(sf
->limit
, var
->limit
);
1826 vmcs_write16(sf
->selector
, var
->selector
);
1827 if (vmx
->rmode
.vm86_active
&& var
->s
) {
1829 * Hack real-mode segments into vm86 compatibility.
1831 if (var
->base
== 0xffff0000 && var
->selector
== 0xf000)
1832 vmcs_writel(sf
->base
, 0xf0000);
1835 ar
= vmx_segment_access_rights(var
);
1838 * Fix the "Accessed" bit in AR field of segment registers for older
1840 * IA32 arch specifies that at the time of processor reset the
1841 * "Accessed" bit in the AR field of segment registers is 1. And qemu
1842 * is setting it to 0 in the usedland code. This causes invalid guest
1843 * state vmexit when "unrestricted guest" mode is turned on.
1844 * Fix for this setup issue in cpu_reset is being pushed in the qemu
1845 * tree. Newer qemu binaries with that qemu fix would not need this
1848 if (enable_unrestricted_guest
&& (seg
!= VCPU_SREG_LDTR
))
1849 ar
|= 0x1; /* Accessed */
1851 vmcs_write32(sf
->ar_bytes
, ar
);
1854 static void vmx_get_cs_db_l_bits(struct kvm_vcpu
*vcpu
, int *db
, int *l
)
1856 u32 ar
= vmcs_read32(GUEST_CS_AR_BYTES
);
1858 *db
= (ar
>> 14) & 1;
1859 *l
= (ar
>> 13) & 1;
1862 static void vmx_get_idt(struct kvm_vcpu
*vcpu
, struct descriptor_table
*dt
)
1864 dt
->limit
= vmcs_read32(GUEST_IDTR_LIMIT
);
1865 dt
->base
= vmcs_readl(GUEST_IDTR_BASE
);
1868 static void vmx_set_idt(struct kvm_vcpu
*vcpu
, struct descriptor_table
*dt
)
1870 vmcs_write32(GUEST_IDTR_LIMIT
, dt
->limit
);
1871 vmcs_writel(GUEST_IDTR_BASE
, dt
->base
);
1874 static void vmx_get_gdt(struct kvm_vcpu
*vcpu
, struct descriptor_table
*dt
)
1876 dt
->limit
= vmcs_read32(GUEST_GDTR_LIMIT
);
1877 dt
->base
= vmcs_readl(GUEST_GDTR_BASE
);
1880 static void vmx_set_gdt(struct kvm_vcpu
*vcpu
, struct descriptor_table
*dt
)
1882 vmcs_write32(GUEST_GDTR_LIMIT
, dt
->limit
);
1883 vmcs_writel(GUEST_GDTR_BASE
, dt
->base
);
1886 static bool rmode_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
1888 struct kvm_segment var
;
1891 vmx_get_segment(vcpu
, &var
, seg
);
1892 ar
= vmx_segment_access_rights(&var
);
1894 if (var
.base
!= (var
.selector
<< 4))
1896 if (var
.limit
!= 0xffff)
1904 static bool code_segment_valid(struct kvm_vcpu
*vcpu
)
1906 struct kvm_segment cs
;
1907 unsigned int cs_rpl
;
1909 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
1910 cs_rpl
= cs
.selector
& SELECTOR_RPL_MASK
;
1914 if (~cs
.type
& (AR_TYPE_CODE_MASK
|AR_TYPE_ACCESSES_MASK
))
1918 if (cs
.type
& AR_TYPE_WRITEABLE_MASK
) {
1919 if (cs
.dpl
> cs_rpl
)
1922 if (cs
.dpl
!= cs_rpl
)
1928 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
1932 static bool stack_segment_valid(struct kvm_vcpu
*vcpu
)
1934 struct kvm_segment ss
;
1935 unsigned int ss_rpl
;
1937 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
1938 ss_rpl
= ss
.selector
& SELECTOR_RPL_MASK
;
1942 if (ss
.type
!= 3 && ss
.type
!= 7)
1946 if (ss
.dpl
!= ss_rpl
) /* DPL != RPL */
1954 static bool data_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
1956 struct kvm_segment var
;
1959 vmx_get_segment(vcpu
, &var
, seg
);
1960 rpl
= var
.selector
& SELECTOR_RPL_MASK
;
1968 if (~var
.type
& (AR_TYPE_CODE_MASK
|AR_TYPE_WRITEABLE_MASK
)) {
1969 if (var
.dpl
< rpl
) /* DPL < RPL */
1973 /* TODO: Add other members to kvm_segment_field to allow checking for other access
1979 static bool tr_valid(struct kvm_vcpu
*vcpu
)
1981 struct kvm_segment tr
;
1983 vmx_get_segment(vcpu
, &tr
, VCPU_SREG_TR
);
1987 if (tr
.selector
& SELECTOR_TI_MASK
) /* TI = 1 */
1989 if (tr
.type
!= 3 && tr
.type
!= 11) /* TODO: Check if guest is in IA32e mode */
1997 static bool ldtr_valid(struct kvm_vcpu
*vcpu
)
1999 struct kvm_segment ldtr
;
2001 vmx_get_segment(vcpu
, &ldtr
, VCPU_SREG_LDTR
);
2005 if (ldtr
.selector
& SELECTOR_TI_MASK
) /* TI = 1 */
2015 static bool cs_ss_rpl_check(struct kvm_vcpu
*vcpu
)
2017 struct kvm_segment cs
, ss
;
2019 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
2020 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
2022 return ((cs
.selector
& SELECTOR_RPL_MASK
) ==
2023 (ss
.selector
& SELECTOR_RPL_MASK
));
2027 * Check if guest state is valid. Returns true if valid, false if
2029 * We assume that registers are always usable
2031 static bool guest_state_valid(struct kvm_vcpu
*vcpu
)
2033 /* real mode guest state checks */
2034 if (!(vcpu
->arch
.cr0
& X86_CR0_PE
)) {
2035 if (!rmode_segment_valid(vcpu
, VCPU_SREG_CS
))
2037 if (!rmode_segment_valid(vcpu
, VCPU_SREG_SS
))
2039 if (!rmode_segment_valid(vcpu
, VCPU_SREG_DS
))
2041 if (!rmode_segment_valid(vcpu
, VCPU_SREG_ES
))
2043 if (!rmode_segment_valid(vcpu
, VCPU_SREG_FS
))
2045 if (!rmode_segment_valid(vcpu
, VCPU_SREG_GS
))
2048 /* protected mode guest state checks */
2049 if (!cs_ss_rpl_check(vcpu
))
2051 if (!code_segment_valid(vcpu
))
2053 if (!stack_segment_valid(vcpu
))
2055 if (!data_segment_valid(vcpu
, VCPU_SREG_DS
))
2057 if (!data_segment_valid(vcpu
, VCPU_SREG_ES
))
2059 if (!data_segment_valid(vcpu
, VCPU_SREG_FS
))
2061 if (!data_segment_valid(vcpu
, VCPU_SREG_GS
))
2063 if (!tr_valid(vcpu
))
2065 if (!ldtr_valid(vcpu
))
2069 * - Add checks on RIP
2070 * - Add checks on RFLAGS
2076 static int init_rmode_tss(struct kvm
*kvm
)
2078 gfn_t fn
= rmode_tss_base(kvm
) >> PAGE_SHIFT
;
2083 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
2086 data
= TSS_BASE_SIZE
+ TSS_REDIRECTION_SIZE
;
2087 r
= kvm_write_guest_page(kvm
, fn
++, &data
,
2088 TSS_IOPB_BASE_OFFSET
, sizeof(u16
));
2091 r
= kvm_clear_guest_page(kvm
, fn
++, 0, PAGE_SIZE
);
2094 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
2098 r
= kvm_write_guest_page(kvm
, fn
, &data
,
2099 RMODE_TSS_SIZE
- 2 * PAGE_SIZE
- 1,
2109 static int init_rmode_identity_map(struct kvm
*kvm
)
2112 pfn_t identity_map_pfn
;
2117 if (unlikely(!kvm
->arch
.ept_identity_pagetable
)) {
2118 printk(KERN_ERR
"EPT: identity-mapping pagetable "
2119 "haven't been allocated!\n");
2122 if (likely(kvm
->arch
.ept_identity_pagetable_done
))
2125 identity_map_pfn
= kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
;
2126 r
= kvm_clear_guest_page(kvm
, identity_map_pfn
, 0, PAGE_SIZE
);
2129 /* Set up identity-mapping pagetable for EPT in real mode */
2130 for (i
= 0; i
< PT32_ENT_PER_PAGE
; i
++) {
2131 tmp
= (i
<< 22) + (_PAGE_PRESENT
| _PAGE_RW
| _PAGE_USER
|
2132 _PAGE_ACCESSED
| _PAGE_DIRTY
| _PAGE_PSE
);
2133 r
= kvm_write_guest_page(kvm
, identity_map_pfn
,
2134 &tmp
, i
* sizeof(tmp
), sizeof(tmp
));
2138 kvm
->arch
.ept_identity_pagetable_done
= true;
2144 static void seg_setup(int seg
)
2146 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
2149 vmcs_write16(sf
->selector
, 0);
2150 vmcs_writel(sf
->base
, 0);
2151 vmcs_write32(sf
->limit
, 0xffff);
2152 if (enable_unrestricted_guest
) {
2154 if (seg
== VCPU_SREG_CS
)
2155 ar
|= 0x08; /* code segment */
2159 vmcs_write32(sf
->ar_bytes
, ar
);
2162 static int alloc_apic_access_page(struct kvm
*kvm
)
2164 struct kvm_userspace_memory_region kvm_userspace_mem
;
2167 down_write(&kvm
->slots_lock
);
2168 if (kvm
->arch
.apic_access_page
)
2170 kvm_userspace_mem
.slot
= APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
;
2171 kvm_userspace_mem
.flags
= 0;
2172 kvm_userspace_mem
.guest_phys_addr
= 0xfee00000ULL
;
2173 kvm_userspace_mem
.memory_size
= PAGE_SIZE
;
2174 r
= __kvm_set_memory_region(kvm
, &kvm_userspace_mem
, 0);
2178 kvm
->arch
.apic_access_page
= gfn_to_page(kvm
, 0xfee00);
2180 up_write(&kvm
->slots_lock
);
2184 static int alloc_identity_pagetable(struct kvm
*kvm
)
2186 struct kvm_userspace_memory_region kvm_userspace_mem
;
2189 down_write(&kvm
->slots_lock
);
2190 if (kvm
->arch
.ept_identity_pagetable
)
2192 kvm_userspace_mem
.slot
= IDENTITY_PAGETABLE_PRIVATE_MEMSLOT
;
2193 kvm_userspace_mem
.flags
= 0;
2194 kvm_userspace_mem
.guest_phys_addr
=
2195 kvm
->arch
.ept_identity_map_addr
;
2196 kvm_userspace_mem
.memory_size
= PAGE_SIZE
;
2197 r
= __kvm_set_memory_region(kvm
, &kvm_userspace_mem
, 0);
2201 kvm
->arch
.ept_identity_pagetable
= gfn_to_page(kvm
,
2202 kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
);
2204 up_write(&kvm
->slots_lock
);
2208 static void allocate_vpid(struct vcpu_vmx
*vmx
)
2215 spin_lock(&vmx_vpid_lock
);
2216 vpid
= find_first_zero_bit(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
2217 if (vpid
< VMX_NR_VPIDS
) {
2219 __set_bit(vpid
, vmx_vpid_bitmap
);
2221 spin_unlock(&vmx_vpid_lock
);
2224 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap
, u32 msr
)
2226 int f
= sizeof(unsigned long);
2228 if (!cpu_has_vmx_msr_bitmap())
2232 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2233 * have the write-low and read-high bitmap offsets the wrong way round.
2234 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2236 if (msr
<= 0x1fff) {
2237 __clear_bit(msr
, msr_bitmap
+ 0x000 / f
); /* read-low */
2238 __clear_bit(msr
, msr_bitmap
+ 0x800 / f
); /* write-low */
2239 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
2241 __clear_bit(msr
, msr_bitmap
+ 0x400 / f
); /* read-high */
2242 __clear_bit(msr
, msr_bitmap
+ 0xc00 / f
); /* write-high */
2246 static void vmx_disable_intercept_for_msr(u32 msr
, bool longmode_only
)
2249 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy
, msr
);
2250 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode
, msr
);
2254 * Sets up the vmcs for emulated real mode.
2256 static int vmx_vcpu_setup(struct vcpu_vmx
*vmx
)
2258 u32 host_sysenter_cs
, msr_low
, msr_high
;
2260 u64 host_pat
, tsc_this
, tsc_base
;
2262 struct descriptor_table dt
;
2264 unsigned long kvm_vmx_return
;
2268 vmcs_write64(IO_BITMAP_A
, __pa(vmx_io_bitmap_a
));
2269 vmcs_write64(IO_BITMAP_B
, __pa(vmx_io_bitmap_b
));
2271 if (cpu_has_vmx_msr_bitmap())
2272 vmcs_write64(MSR_BITMAP
, __pa(vmx_msr_bitmap_legacy
));
2274 vmcs_write64(VMCS_LINK_POINTER
, -1ull); /* 22.3.1.5 */
2277 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
,
2278 vmcs_config
.pin_based_exec_ctrl
);
2280 exec_control
= vmcs_config
.cpu_based_exec_ctrl
;
2281 if (!vm_need_tpr_shadow(vmx
->vcpu
.kvm
)) {
2282 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
2283 #ifdef CONFIG_X86_64
2284 exec_control
|= CPU_BASED_CR8_STORE_EXITING
|
2285 CPU_BASED_CR8_LOAD_EXITING
;
2289 exec_control
|= CPU_BASED_CR3_STORE_EXITING
|
2290 CPU_BASED_CR3_LOAD_EXITING
|
2291 CPU_BASED_INVLPG_EXITING
;
2292 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, exec_control
);
2294 if (cpu_has_secondary_exec_ctrls()) {
2295 exec_control
= vmcs_config
.cpu_based_2nd_exec_ctrl
;
2296 if (!vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
))
2298 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
2300 exec_control
&= ~SECONDARY_EXEC_ENABLE_VPID
;
2302 exec_control
&= ~SECONDARY_EXEC_ENABLE_EPT
;
2303 if (!enable_unrestricted_guest
)
2304 exec_control
&= ~SECONDARY_EXEC_UNRESTRICTED_GUEST
;
2305 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
2308 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
, !!bypass_guest_pf
);
2309 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
, !!bypass_guest_pf
);
2310 vmcs_write32(CR3_TARGET_COUNT
, 0); /* 22.2.1 */
2312 vmcs_writel(HOST_CR0
, read_cr0()); /* 22.2.3 */
2313 vmcs_writel(HOST_CR4
, read_cr4()); /* 22.2.3, 22.2.5 */
2314 vmcs_writel(HOST_CR3
, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2316 vmcs_write16(HOST_CS_SELECTOR
, __KERNEL_CS
); /* 22.2.4 */
2317 vmcs_write16(HOST_DS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
2318 vmcs_write16(HOST_ES_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
2319 vmcs_write16(HOST_FS_SELECTOR
, kvm_read_fs()); /* 22.2.4 */
2320 vmcs_write16(HOST_GS_SELECTOR
, kvm_read_gs()); /* 22.2.4 */
2321 vmcs_write16(HOST_SS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
2322 #ifdef CONFIG_X86_64
2323 rdmsrl(MSR_FS_BASE
, a
);
2324 vmcs_writel(HOST_FS_BASE
, a
); /* 22.2.4 */
2325 rdmsrl(MSR_GS_BASE
, a
);
2326 vmcs_writel(HOST_GS_BASE
, a
); /* 22.2.4 */
2328 vmcs_writel(HOST_FS_BASE
, 0); /* 22.2.4 */
2329 vmcs_writel(HOST_GS_BASE
, 0); /* 22.2.4 */
2332 vmcs_write16(HOST_TR_SELECTOR
, GDT_ENTRY_TSS
*8); /* 22.2.4 */
2335 vmcs_writel(HOST_IDTR_BASE
, dt
.base
); /* 22.2.4 */
2337 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return
));
2338 vmcs_writel(HOST_RIP
, kvm_vmx_return
); /* 22.2.5 */
2339 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
2340 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, 0);
2341 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, 0);
2343 rdmsr(MSR_IA32_SYSENTER_CS
, host_sysenter_cs
, junk
);
2344 vmcs_write32(HOST_IA32_SYSENTER_CS
, host_sysenter_cs
);
2345 rdmsrl(MSR_IA32_SYSENTER_ESP
, a
);
2346 vmcs_writel(HOST_IA32_SYSENTER_ESP
, a
); /* 22.2.3 */
2347 rdmsrl(MSR_IA32_SYSENTER_EIP
, a
);
2348 vmcs_writel(HOST_IA32_SYSENTER_EIP
, a
); /* 22.2.3 */
2350 if (vmcs_config
.vmexit_ctrl
& VM_EXIT_LOAD_IA32_PAT
) {
2351 rdmsr(MSR_IA32_CR_PAT
, msr_low
, msr_high
);
2352 host_pat
= msr_low
| ((u64
) msr_high
<< 32);
2353 vmcs_write64(HOST_IA32_PAT
, host_pat
);
2355 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
2356 rdmsr(MSR_IA32_CR_PAT
, msr_low
, msr_high
);
2357 host_pat
= msr_low
| ((u64
) msr_high
<< 32);
2358 /* Write the default value follow host pat */
2359 vmcs_write64(GUEST_IA32_PAT
, host_pat
);
2360 /* Keep arch.pat sync with GUEST_IA32_PAT */
2361 vmx
->vcpu
.arch
.pat
= host_pat
;
2364 for (i
= 0; i
< NR_VMX_MSR
; ++i
) {
2365 u32 index
= vmx_msr_index
[i
];
2366 u32 data_low
, data_high
;
2370 if (rdmsr_safe(index
, &data_low
, &data_high
) < 0)
2372 if (wrmsr_safe(index
, data_low
, data_high
) < 0)
2374 data
= data_low
| ((u64
)data_high
<< 32);
2375 vmx
->host_msrs
[j
].index
= index
;
2376 vmx
->host_msrs
[j
].reserved
= 0;
2377 vmx
->host_msrs
[j
].data
= data
;
2378 vmx
->guest_msrs
[j
] = vmx
->host_msrs
[j
];
2382 vmcs_write32(VM_EXIT_CONTROLS
, vmcs_config
.vmexit_ctrl
);
2384 /* 22.2.1, 20.8.1 */
2385 vmcs_write32(VM_ENTRY_CONTROLS
, vmcs_config
.vmentry_ctrl
);
2387 vmcs_writel(CR0_GUEST_HOST_MASK
, ~0UL);
2388 vmcs_writel(CR4_GUEST_HOST_MASK
, KVM_GUEST_CR4_MASK
);
2390 tsc_base
= vmx
->vcpu
.kvm
->arch
.vm_init_tsc
;
2392 if (tsc_this
< vmx
->vcpu
.kvm
->arch
.vm_init_tsc
)
2393 tsc_base
= tsc_this
;
2395 guest_write_tsc(0, tsc_base
);
2400 static int init_rmode(struct kvm
*kvm
)
2402 if (!init_rmode_tss(kvm
))
2404 if (!init_rmode_identity_map(kvm
))
2409 static int vmx_vcpu_reset(struct kvm_vcpu
*vcpu
)
2411 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2415 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
));
2416 down_read(&vcpu
->kvm
->slots_lock
);
2417 if (!init_rmode(vmx
->vcpu
.kvm
)) {
2422 vmx
->rmode
.vm86_active
= 0;
2424 vmx
->soft_vnmi_blocked
= 0;
2426 vmx
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = get_rdx_init_val();
2427 kvm_set_cr8(&vmx
->vcpu
, 0);
2428 msr
= 0xfee00000 | MSR_IA32_APICBASE_ENABLE
;
2429 if (kvm_vcpu_is_bsp(&vmx
->vcpu
))
2430 msr
|= MSR_IA32_APICBASE_BSP
;
2431 kvm_set_apic_base(&vmx
->vcpu
, msr
);
2433 fx_init(&vmx
->vcpu
);
2435 seg_setup(VCPU_SREG_CS
);
2437 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2438 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2440 if (kvm_vcpu_is_bsp(&vmx
->vcpu
)) {
2441 vmcs_write16(GUEST_CS_SELECTOR
, 0xf000);
2442 vmcs_writel(GUEST_CS_BASE
, 0x000f0000);
2444 vmcs_write16(GUEST_CS_SELECTOR
, vmx
->vcpu
.arch
.sipi_vector
<< 8);
2445 vmcs_writel(GUEST_CS_BASE
, vmx
->vcpu
.arch
.sipi_vector
<< 12);
2448 seg_setup(VCPU_SREG_DS
);
2449 seg_setup(VCPU_SREG_ES
);
2450 seg_setup(VCPU_SREG_FS
);
2451 seg_setup(VCPU_SREG_GS
);
2452 seg_setup(VCPU_SREG_SS
);
2454 vmcs_write16(GUEST_TR_SELECTOR
, 0);
2455 vmcs_writel(GUEST_TR_BASE
, 0);
2456 vmcs_write32(GUEST_TR_LIMIT
, 0xffff);
2457 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
2459 vmcs_write16(GUEST_LDTR_SELECTOR
, 0);
2460 vmcs_writel(GUEST_LDTR_BASE
, 0);
2461 vmcs_write32(GUEST_LDTR_LIMIT
, 0xffff);
2462 vmcs_write32(GUEST_LDTR_AR_BYTES
, 0x00082);
2464 vmcs_write32(GUEST_SYSENTER_CS
, 0);
2465 vmcs_writel(GUEST_SYSENTER_ESP
, 0);
2466 vmcs_writel(GUEST_SYSENTER_EIP
, 0);
2468 vmcs_writel(GUEST_RFLAGS
, 0x02);
2469 if (kvm_vcpu_is_bsp(&vmx
->vcpu
))
2470 kvm_rip_write(vcpu
, 0xfff0);
2472 kvm_rip_write(vcpu
, 0);
2473 kvm_register_write(vcpu
, VCPU_REGS_RSP
, 0);
2475 vmcs_writel(GUEST_DR7
, 0x400);
2477 vmcs_writel(GUEST_GDTR_BASE
, 0);
2478 vmcs_write32(GUEST_GDTR_LIMIT
, 0xffff);
2480 vmcs_writel(GUEST_IDTR_BASE
, 0);
2481 vmcs_write32(GUEST_IDTR_LIMIT
, 0xffff);
2483 vmcs_write32(GUEST_ACTIVITY_STATE
, 0);
2484 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, 0);
2485 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS
, 0);
2487 /* Special registers */
2488 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
2492 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0); /* 22.2.1 */
2494 if (cpu_has_vmx_tpr_shadow()) {
2495 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, 0);
2496 if (vm_need_tpr_shadow(vmx
->vcpu
.kvm
))
2497 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
2498 page_to_phys(vmx
->vcpu
.arch
.apic
->regs_page
));
2499 vmcs_write32(TPR_THRESHOLD
, 0);
2502 if (vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
))
2503 vmcs_write64(APIC_ACCESS_ADDR
,
2504 page_to_phys(vmx
->vcpu
.kvm
->arch
.apic_access_page
));
2507 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
2509 vmx
->vcpu
.arch
.cr0
= 0x60000010;
2510 vmx_set_cr0(&vmx
->vcpu
, vmx
->vcpu
.arch
.cr0
); /* enter rmode */
2511 vmx_set_cr4(&vmx
->vcpu
, 0);
2512 vmx_set_efer(&vmx
->vcpu
, 0);
2513 vmx_fpu_activate(&vmx
->vcpu
);
2514 update_exception_bitmap(&vmx
->vcpu
);
2516 vpid_sync_vcpu_all(vmx
);
2520 /* HACK: Don't enable emulation on guest boot/reset */
2521 vmx
->emulation_required
= 0;
2524 up_read(&vcpu
->kvm
->slots_lock
);
2528 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
2530 u32 cpu_based_vm_exec_control
;
2532 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
2533 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_INTR_PENDING
;
2534 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
2537 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
2539 u32 cpu_based_vm_exec_control
;
2541 if (!cpu_has_virtual_nmis()) {
2542 enable_irq_window(vcpu
);
2546 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
2547 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_NMI_PENDING
;
2548 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
2551 static void vmx_inject_irq(struct kvm_vcpu
*vcpu
)
2553 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2555 int irq
= vcpu
->arch
.interrupt
.nr
;
2557 trace_kvm_inj_virq(irq
);
2559 ++vcpu
->stat
.irq_injections
;
2560 if (vmx
->rmode
.vm86_active
) {
2561 vmx
->rmode
.irq
.pending
= true;
2562 vmx
->rmode
.irq
.vector
= irq
;
2563 vmx
->rmode
.irq
.rip
= kvm_rip_read(vcpu
);
2564 if (vcpu
->arch
.interrupt
.soft
)
2565 vmx
->rmode
.irq
.rip
+=
2566 vmx
->vcpu
.arch
.event_exit_inst_len
;
2567 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
2568 irq
| INTR_TYPE_SOFT_INTR
| INTR_INFO_VALID_MASK
);
2569 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
, 1);
2570 kvm_rip_write(vcpu
, vmx
->rmode
.irq
.rip
- 1);
2573 intr
= irq
| INTR_INFO_VALID_MASK
;
2574 if (vcpu
->arch
.interrupt
.soft
) {
2575 intr
|= INTR_TYPE_SOFT_INTR
;
2576 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
2577 vmx
->vcpu
.arch
.event_exit_inst_len
);
2579 intr
|= INTR_TYPE_EXT_INTR
;
2580 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr
);
2583 static void vmx_inject_nmi(struct kvm_vcpu
*vcpu
)
2585 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2587 if (!cpu_has_virtual_nmis()) {
2589 * Tracking the NMI-blocked state in software is built upon
2590 * finding the next open IRQ window. This, in turn, depends on
2591 * well-behaving guests: They have to keep IRQs disabled at
2592 * least as long as the NMI handler runs. Otherwise we may
2593 * cause NMI nesting, maybe breaking the guest. But as this is
2594 * highly unlikely, we can live with the residual risk.
2596 vmx
->soft_vnmi_blocked
= 1;
2597 vmx
->vnmi_blocked_time
= 0;
2600 ++vcpu
->stat
.nmi_injections
;
2601 if (vmx
->rmode
.vm86_active
) {
2602 vmx
->rmode
.irq
.pending
= true;
2603 vmx
->rmode
.irq
.vector
= NMI_VECTOR
;
2604 vmx
->rmode
.irq
.rip
= kvm_rip_read(vcpu
);
2605 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
2606 NMI_VECTOR
| INTR_TYPE_SOFT_INTR
|
2607 INTR_INFO_VALID_MASK
);
2608 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
, 1);
2609 kvm_rip_write(vcpu
, vmx
->rmode
.irq
.rip
- 1);
2612 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
2613 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
);
2616 static int vmx_nmi_allowed(struct kvm_vcpu
*vcpu
)
2618 if (!cpu_has_virtual_nmis() && to_vmx(vcpu
)->soft_vnmi_blocked
)
2621 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
2622 (GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
|
2623 GUEST_INTR_STATE_NMI
));
2626 static int vmx_interrupt_allowed(struct kvm_vcpu
*vcpu
)
2628 return (vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_IF
) &&
2629 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
2630 (GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
));
2633 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
2636 struct kvm_userspace_memory_region tss_mem
= {
2637 .slot
= TSS_PRIVATE_MEMSLOT
,
2638 .guest_phys_addr
= addr
,
2639 .memory_size
= PAGE_SIZE
* 3,
2643 ret
= kvm_set_memory_region(kvm
, &tss_mem
, 0);
2646 kvm
->arch
.tss_addr
= addr
;
2650 static int handle_rmode_exception(struct kvm_vcpu
*vcpu
,
2651 int vec
, u32 err_code
)
2654 * Instruction with address size override prefix opcode 0x67
2655 * Cause the #SS fault with 0 error code in VM86 mode.
2657 if (((vec
== GP_VECTOR
) || (vec
== SS_VECTOR
)) && err_code
== 0)
2658 if (emulate_instruction(vcpu
, NULL
, 0, 0, 0) == EMULATE_DONE
)
2661 * Forward all other exceptions that are valid in real mode.
2662 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2663 * the required debugging infrastructure rework.
2667 if (vcpu
->guest_debug
&
2668 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
2670 kvm_queue_exception(vcpu
, vec
);
2673 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
2684 kvm_queue_exception(vcpu
, vec
);
2691 * Trigger machine check on the host. We assume all the MSRs are already set up
2692 * by the CPU and that we still run on the same CPU as the MCE occurred on.
2693 * We pass a fake environment to the machine check handler because we want
2694 * the guest to be always treated like user space, no matter what context
2695 * it used internally.
2697 static void kvm_machine_check(void)
2699 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
2700 struct pt_regs regs
= {
2701 .cs
= 3, /* Fake ring 3 no matter what the guest ran on */
2702 .flags
= X86_EFLAGS_IF
,
2705 do_machine_check(®s
, 0);
2709 static int handle_machine_check(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
2711 /* already handled by vcpu_run */
2715 static int handle_exception(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
2717 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2718 u32 intr_info
, ex_no
, error_code
;
2719 unsigned long cr2
, rip
, dr6
;
2721 enum emulation_result er
;
2723 vect_info
= vmx
->idt_vectoring_info
;
2724 intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
2726 if (is_machine_check(intr_info
))
2727 return handle_machine_check(vcpu
, kvm_run
);
2729 if ((vect_info
& VECTORING_INFO_VALID_MASK
) &&
2730 !is_page_fault(intr_info
))
2731 printk(KERN_ERR
"%s: unexpected, vectoring info 0x%x "
2732 "intr info 0x%x\n", __func__
, vect_info
, intr_info
);
2734 if ((intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
)
2735 return 1; /* already handled by vmx_vcpu_run() */
2737 if (is_no_device(intr_info
)) {
2738 vmx_fpu_activate(vcpu
);
2742 if (is_invalid_opcode(intr_info
)) {
2743 er
= emulate_instruction(vcpu
, kvm_run
, 0, 0, EMULTYPE_TRAP_UD
);
2744 if (er
!= EMULATE_DONE
)
2745 kvm_queue_exception(vcpu
, UD_VECTOR
);
2750 rip
= kvm_rip_read(vcpu
);
2751 if (intr_info
& INTR_INFO_DELIVER_CODE_MASK
)
2752 error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
2753 if (is_page_fault(intr_info
)) {
2754 /* EPT won't cause page fault directly */
2757 cr2
= vmcs_readl(EXIT_QUALIFICATION
);
2758 trace_kvm_page_fault(cr2
, error_code
);
2760 if (kvm_event_needs_reinjection(vcpu
))
2761 kvm_mmu_unprotect_page_virt(vcpu
, cr2
);
2762 return kvm_mmu_page_fault(vcpu
, cr2
, error_code
);
2765 if (vmx
->rmode
.vm86_active
&&
2766 handle_rmode_exception(vcpu
, intr_info
& INTR_INFO_VECTOR_MASK
,
2768 if (vcpu
->arch
.halt_request
) {
2769 vcpu
->arch
.halt_request
= 0;
2770 return kvm_emulate_halt(vcpu
);
2775 ex_no
= intr_info
& INTR_INFO_VECTOR_MASK
;
2778 dr6
= vmcs_readl(EXIT_QUALIFICATION
);
2779 if (!(vcpu
->guest_debug
&
2780 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))) {
2781 vcpu
->arch
.dr6
= dr6
| DR6_FIXED_1
;
2782 kvm_queue_exception(vcpu
, DB_VECTOR
);
2785 kvm_run
->debug
.arch
.dr6
= dr6
| DR6_FIXED_1
;
2786 kvm_run
->debug
.arch
.dr7
= vmcs_readl(GUEST_DR7
);
2789 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
2790 kvm_run
->debug
.arch
.pc
= vmcs_readl(GUEST_CS_BASE
) + rip
;
2791 kvm_run
->debug
.arch
.exception
= ex_no
;
2794 kvm_run
->exit_reason
= KVM_EXIT_EXCEPTION
;
2795 kvm_run
->ex
.exception
= ex_no
;
2796 kvm_run
->ex
.error_code
= error_code
;
2802 static int handle_external_interrupt(struct kvm_vcpu
*vcpu
,
2803 struct kvm_run
*kvm_run
)
2805 ++vcpu
->stat
.irq_exits
;
2809 static int handle_triple_fault(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
2811 kvm_run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
2815 static int handle_io(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
2817 unsigned long exit_qualification
;
2818 int size
, in
, string
;
2821 ++vcpu
->stat
.io_exits
;
2822 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
2823 string
= (exit_qualification
& 16) != 0;
2826 if (emulate_instruction(vcpu
,
2827 kvm_run
, 0, 0, 0) == EMULATE_DO_MMIO
)
2832 size
= (exit_qualification
& 7) + 1;
2833 in
= (exit_qualification
& 8) != 0;
2834 port
= exit_qualification
>> 16;
2836 skip_emulated_instruction(vcpu
);
2837 return kvm_emulate_pio(vcpu
, kvm_run
, in
, size
, port
);
2841 vmx_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
2844 * Patch in the VMCALL instruction:
2846 hypercall
[0] = 0x0f;
2847 hypercall
[1] = 0x01;
2848 hypercall
[2] = 0xc1;
2851 static int handle_cr(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
2853 unsigned long exit_qualification
, val
;
2857 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
2858 cr
= exit_qualification
& 15;
2859 reg
= (exit_qualification
>> 8) & 15;
2860 switch ((exit_qualification
>> 4) & 3) {
2861 case 0: /* mov to cr */
2862 val
= kvm_register_read(vcpu
, reg
);
2863 trace_kvm_cr_write(cr
, val
);
2866 kvm_set_cr0(vcpu
, val
);
2867 skip_emulated_instruction(vcpu
);
2870 kvm_set_cr3(vcpu
, val
);
2871 skip_emulated_instruction(vcpu
);
2874 kvm_set_cr4(vcpu
, val
);
2875 skip_emulated_instruction(vcpu
);
2878 u8 cr8_prev
= kvm_get_cr8(vcpu
);
2879 u8 cr8
= kvm_register_read(vcpu
, reg
);
2880 kvm_set_cr8(vcpu
, cr8
);
2881 skip_emulated_instruction(vcpu
);
2882 if (irqchip_in_kernel(vcpu
->kvm
))
2884 if (cr8_prev
<= cr8
)
2886 kvm_run
->exit_reason
= KVM_EXIT_SET_TPR
;
2892 vmx_fpu_deactivate(vcpu
);
2893 vcpu
->arch
.cr0
&= ~X86_CR0_TS
;
2894 vmcs_writel(CR0_READ_SHADOW
, vcpu
->arch
.cr0
);
2895 vmx_fpu_activate(vcpu
);
2896 skip_emulated_instruction(vcpu
);
2898 case 1: /*mov from cr*/
2901 kvm_register_write(vcpu
, reg
, vcpu
->arch
.cr3
);
2902 trace_kvm_cr_read(cr
, vcpu
->arch
.cr3
);
2903 skip_emulated_instruction(vcpu
);
2906 val
= kvm_get_cr8(vcpu
);
2907 kvm_register_write(vcpu
, reg
, val
);
2908 trace_kvm_cr_read(cr
, val
);
2909 skip_emulated_instruction(vcpu
);
2914 kvm_lmsw(vcpu
, (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f);
2916 skip_emulated_instruction(vcpu
);
2921 kvm_run
->exit_reason
= 0;
2922 pr_unimpl(vcpu
, "unhandled control register: op %d cr %d\n",
2923 (int)(exit_qualification
>> 4) & 3, cr
);
2927 static int handle_dr(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
2929 unsigned long exit_qualification
;
2933 dr
= vmcs_readl(GUEST_DR7
);
2936 * As the vm-exit takes precedence over the debug trap, we
2937 * need to emulate the latter, either for the host or the
2938 * guest debugging itself.
2940 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
) {
2941 kvm_run
->debug
.arch
.dr6
= vcpu
->arch
.dr6
;
2942 kvm_run
->debug
.arch
.dr7
= dr
;
2943 kvm_run
->debug
.arch
.pc
=
2944 vmcs_readl(GUEST_CS_BASE
) +
2945 vmcs_readl(GUEST_RIP
);
2946 kvm_run
->debug
.arch
.exception
= DB_VECTOR
;
2947 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
2950 vcpu
->arch
.dr7
&= ~DR7_GD
;
2951 vcpu
->arch
.dr6
|= DR6_BD
;
2952 vmcs_writel(GUEST_DR7
, vcpu
->arch
.dr7
);
2953 kvm_queue_exception(vcpu
, DB_VECTOR
);
2958 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
2959 dr
= exit_qualification
& DEBUG_REG_ACCESS_NUM
;
2960 reg
= DEBUG_REG_ACCESS_REG(exit_qualification
);
2961 if (exit_qualification
& TYPE_MOV_FROM_DR
) {
2964 val
= vcpu
->arch
.db
[dr
];
2967 val
= vcpu
->arch
.dr6
;
2970 val
= vcpu
->arch
.dr7
;
2975 kvm_register_write(vcpu
, reg
, val
);
2977 val
= vcpu
->arch
.regs
[reg
];
2980 vcpu
->arch
.db
[dr
] = val
;
2981 if (!(vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
))
2982 vcpu
->arch
.eff_db
[dr
] = val
;
2985 if (vcpu
->arch
.cr4
& X86_CR4_DE
)
2986 kvm_queue_exception(vcpu
, UD_VECTOR
);
2989 if (val
& 0xffffffff00000000ULL
) {
2990 kvm_queue_exception(vcpu
, GP_VECTOR
);
2993 vcpu
->arch
.dr6
= (val
& DR6_VOLATILE
) | DR6_FIXED_1
;
2996 if (val
& 0xffffffff00000000ULL
) {
2997 kvm_queue_exception(vcpu
, GP_VECTOR
);
3000 vcpu
->arch
.dr7
= (val
& DR7_VOLATILE
) | DR7_FIXED_1
;
3001 if (!(vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
)) {
3002 vmcs_writel(GUEST_DR7
, vcpu
->arch
.dr7
);
3003 vcpu
->arch
.switch_db_regs
=
3004 (val
& DR7_BP_EN_MASK
);
3009 skip_emulated_instruction(vcpu
);
3013 static int handle_cpuid(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
3015 kvm_emulate_cpuid(vcpu
);
3019 static int handle_rdmsr(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
3021 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
3024 if (vmx_get_msr(vcpu
, ecx
, &data
)) {
3025 kvm_inject_gp(vcpu
, 0);
3029 trace_kvm_msr_read(ecx
, data
);
3031 /* FIXME: handling of bits 32:63 of rax, rdx */
3032 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = data
& -1u;
3033 vcpu
->arch
.regs
[VCPU_REGS_RDX
] = (data
>> 32) & -1u;
3034 skip_emulated_instruction(vcpu
);
3038 static int handle_wrmsr(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
3040 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
3041 u64 data
= (vcpu
->arch
.regs
[VCPU_REGS_RAX
] & -1u)
3042 | ((u64
)(vcpu
->arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
3044 trace_kvm_msr_write(ecx
, data
);
3046 if (vmx_set_msr(vcpu
, ecx
, data
) != 0) {
3047 kvm_inject_gp(vcpu
, 0);
3051 skip_emulated_instruction(vcpu
);
3055 static int handle_tpr_below_threshold(struct kvm_vcpu
*vcpu
,
3056 struct kvm_run
*kvm_run
)
3061 static int handle_interrupt_window(struct kvm_vcpu
*vcpu
,
3062 struct kvm_run
*kvm_run
)
3064 u32 cpu_based_vm_exec_control
;
3066 /* clear pending irq */
3067 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
3068 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
3069 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
3071 ++vcpu
->stat
.irq_window_exits
;
3074 * If the user space waits to inject interrupts, exit as soon as
3077 if (!irqchip_in_kernel(vcpu
->kvm
) &&
3078 kvm_run
->request_interrupt_window
&&
3079 !kvm_cpu_has_interrupt(vcpu
)) {
3080 kvm_run
->exit_reason
= KVM_EXIT_IRQ_WINDOW_OPEN
;
3086 static int handle_halt(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
3088 skip_emulated_instruction(vcpu
);
3089 return kvm_emulate_halt(vcpu
);
3092 static int handle_vmcall(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
3094 skip_emulated_instruction(vcpu
);
3095 kvm_emulate_hypercall(vcpu
);
3099 static int handle_vmx_insn(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
3101 kvm_queue_exception(vcpu
, UD_VECTOR
);
3105 static int handle_invlpg(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
3107 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
3109 kvm_mmu_invlpg(vcpu
, exit_qualification
);
3110 skip_emulated_instruction(vcpu
);
3114 static int handle_wbinvd(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
3116 skip_emulated_instruction(vcpu
);
3117 /* TODO: Add support for VT-d/pass-through device */
3121 static int handle_apic_access(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
3123 unsigned long exit_qualification
;
3124 enum emulation_result er
;
3125 unsigned long offset
;
3127 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
3128 offset
= exit_qualification
& 0xffful
;
3130 er
= emulate_instruction(vcpu
, kvm_run
, 0, 0, 0);
3132 if (er
!= EMULATE_DONE
) {
3134 "Fail to handle apic access vmexit! Offset is 0x%lx\n",
3141 static int handle_task_switch(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
3143 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3144 unsigned long exit_qualification
;
3146 int reason
, type
, idt_v
;
3148 idt_v
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
);
3149 type
= (vmx
->idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
);
3151 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
3153 reason
= (u32
)exit_qualification
>> 30;
3154 if (reason
== TASK_SWITCH_GATE
&& idt_v
) {
3156 case INTR_TYPE_NMI_INTR
:
3157 vcpu
->arch
.nmi_injected
= false;
3158 if (cpu_has_virtual_nmis())
3159 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
3160 GUEST_INTR_STATE_NMI
);
3162 case INTR_TYPE_EXT_INTR
:
3163 case INTR_TYPE_SOFT_INTR
:
3164 kvm_clear_interrupt_queue(vcpu
);
3166 case INTR_TYPE_HARD_EXCEPTION
:
3167 case INTR_TYPE_SOFT_EXCEPTION
:
3168 kvm_clear_exception_queue(vcpu
);
3174 tss_selector
= exit_qualification
;
3176 if (!idt_v
|| (type
!= INTR_TYPE_HARD_EXCEPTION
&&
3177 type
!= INTR_TYPE_EXT_INTR
&&
3178 type
!= INTR_TYPE_NMI_INTR
))
3179 skip_emulated_instruction(vcpu
);
3181 if (!kvm_task_switch(vcpu
, tss_selector
, reason
))
3184 /* clear all local breakpoint enable flags */
3185 vmcs_writel(GUEST_DR7
, vmcs_readl(GUEST_DR7
) & ~55);
3188 * TODO: What about debug traps on tss switch?
3189 * Are we supposed to inject them and update dr6?
3195 static int handle_ept_violation(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
3197 unsigned long exit_qualification
;
3201 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
3203 if (exit_qualification
& (1 << 6)) {
3204 printk(KERN_ERR
"EPT: GPA exceeds GAW!\n");
3208 gla_validity
= (exit_qualification
>> 7) & 0x3;
3209 if (gla_validity
!= 0x3 && gla_validity
!= 0x1 && gla_validity
!= 0) {
3210 printk(KERN_ERR
"EPT: Handling EPT violation failed!\n");
3211 printk(KERN_ERR
"EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3212 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS
),
3213 vmcs_readl(GUEST_LINEAR_ADDRESS
));
3214 printk(KERN_ERR
"EPT: Exit qualification is 0x%lx\n",
3215 (long unsigned int)exit_qualification
);
3216 kvm_run
->exit_reason
= KVM_EXIT_UNKNOWN
;
3217 kvm_run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_VIOLATION
;
3221 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
3222 trace_kvm_page_fault(gpa
, exit_qualification
);
3223 return kvm_mmu_page_fault(vcpu
, gpa
& PAGE_MASK
, 0);
3226 static u64
ept_rsvd_mask(u64 spte
, int level
)
3231 for (i
= 51; i
> boot_cpu_data
.x86_phys_bits
; i
--)
3232 mask
|= (1ULL << i
);
3235 /* bits 7:3 reserved */
3237 else if (level
== 2) {
3238 if (spte
& (1ULL << 7))
3239 /* 2MB ref, bits 20:12 reserved */
3242 /* bits 6:3 reserved */
3249 static void ept_misconfig_inspect_spte(struct kvm_vcpu
*vcpu
, u64 spte
,
3252 printk(KERN_ERR
"%s: spte 0x%llx level %d\n", __func__
, spte
, level
);
3254 /* 010b (write-only) */
3255 WARN_ON((spte
& 0x7) == 0x2);
3257 /* 110b (write/execute) */
3258 WARN_ON((spte
& 0x7) == 0x6);
3260 /* 100b (execute-only) and value not supported by logical processor */
3261 if (!cpu_has_vmx_ept_execute_only())
3262 WARN_ON((spte
& 0x7) == 0x4);
3266 u64 rsvd_bits
= spte
& ept_rsvd_mask(spte
, level
);
3268 if (rsvd_bits
!= 0) {
3269 printk(KERN_ERR
"%s: rsvd_bits = 0x%llx\n",
3270 __func__
, rsvd_bits
);
3274 if (level
== 1 || (level
== 2 && (spte
& (1ULL << 7)))) {
3275 u64 ept_mem_type
= (spte
& 0x38) >> 3;
3277 if (ept_mem_type
== 2 || ept_mem_type
== 3 ||
3278 ept_mem_type
== 7) {
3279 printk(KERN_ERR
"%s: ept_mem_type=0x%llx\n",
3280 __func__
, ept_mem_type
);
3287 static int handle_ept_misconfig(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
3293 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
3295 printk(KERN_ERR
"EPT: Misconfiguration.\n");
3296 printk(KERN_ERR
"EPT: GPA: 0x%llx\n", gpa
);
3298 nr_sptes
= kvm_mmu_get_spte_hierarchy(vcpu
, gpa
, sptes
);
3300 for (i
= PT64_ROOT_LEVEL
; i
> PT64_ROOT_LEVEL
- nr_sptes
; --i
)
3301 ept_misconfig_inspect_spte(vcpu
, sptes
[i
-1], i
);
3303 kvm_run
->exit_reason
= KVM_EXIT_UNKNOWN
;
3304 kvm_run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
3309 static int handle_nmi_window(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
3311 u32 cpu_based_vm_exec_control
;
3313 /* clear pending NMI */
3314 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
3315 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
3316 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
3317 ++vcpu
->stat
.nmi_window_exits
;
3322 static void handle_invalid_guest_state(struct kvm_vcpu
*vcpu
,
3323 struct kvm_run
*kvm_run
)
3325 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3326 enum emulation_result err
= EMULATE_DONE
;
3331 while (!guest_state_valid(vcpu
)) {
3332 err
= emulate_instruction(vcpu
, kvm_run
, 0, 0, 0);
3334 if (err
== EMULATE_DO_MMIO
)
3337 if (err
!= EMULATE_DONE
) {
3338 kvm_report_emulation_failure(vcpu
, "emulation failure");
3342 if (signal_pending(current
))
3349 local_irq_disable();
3351 vmx
->invalid_state_emulation_result
= err
;
3355 * The exit handlers return 1 if the exit was handled fully and guest execution
3356 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3357 * to be done to userspace and return 0.
3359 static int (*kvm_vmx_exit_handlers
[])(struct kvm_vcpu
*vcpu
,
3360 struct kvm_run
*kvm_run
) = {
3361 [EXIT_REASON_EXCEPTION_NMI
] = handle_exception
,
3362 [EXIT_REASON_EXTERNAL_INTERRUPT
] = handle_external_interrupt
,
3363 [EXIT_REASON_TRIPLE_FAULT
] = handle_triple_fault
,
3364 [EXIT_REASON_NMI_WINDOW
] = handle_nmi_window
,
3365 [EXIT_REASON_IO_INSTRUCTION
] = handle_io
,
3366 [EXIT_REASON_CR_ACCESS
] = handle_cr
,
3367 [EXIT_REASON_DR_ACCESS
] = handle_dr
,
3368 [EXIT_REASON_CPUID
] = handle_cpuid
,
3369 [EXIT_REASON_MSR_READ
] = handle_rdmsr
,
3370 [EXIT_REASON_MSR_WRITE
] = handle_wrmsr
,
3371 [EXIT_REASON_PENDING_INTERRUPT
] = handle_interrupt_window
,
3372 [EXIT_REASON_HLT
] = handle_halt
,
3373 [EXIT_REASON_INVLPG
] = handle_invlpg
,
3374 [EXIT_REASON_VMCALL
] = handle_vmcall
,
3375 [EXIT_REASON_VMCLEAR
] = handle_vmx_insn
,
3376 [EXIT_REASON_VMLAUNCH
] = handle_vmx_insn
,
3377 [EXIT_REASON_VMPTRLD
] = handle_vmx_insn
,
3378 [EXIT_REASON_VMPTRST
] = handle_vmx_insn
,
3379 [EXIT_REASON_VMREAD
] = handle_vmx_insn
,
3380 [EXIT_REASON_VMRESUME
] = handle_vmx_insn
,
3381 [EXIT_REASON_VMWRITE
] = handle_vmx_insn
,
3382 [EXIT_REASON_VMOFF
] = handle_vmx_insn
,
3383 [EXIT_REASON_VMON
] = handle_vmx_insn
,
3384 [EXIT_REASON_TPR_BELOW_THRESHOLD
] = handle_tpr_below_threshold
,
3385 [EXIT_REASON_APIC_ACCESS
] = handle_apic_access
,
3386 [EXIT_REASON_WBINVD
] = handle_wbinvd
,
3387 [EXIT_REASON_TASK_SWITCH
] = handle_task_switch
,
3388 [EXIT_REASON_MCE_DURING_VMENTRY
] = handle_machine_check
,
3389 [EXIT_REASON_EPT_VIOLATION
] = handle_ept_violation
,
3390 [EXIT_REASON_EPT_MISCONFIG
] = handle_ept_misconfig
,
3393 static const int kvm_vmx_max_exit_handlers
=
3394 ARRAY_SIZE(kvm_vmx_exit_handlers
);
3397 * The guest has exited. See if we can fix it or if we need userspace
3400 static int vmx_handle_exit(struct kvm_run
*kvm_run
, struct kvm_vcpu
*vcpu
)
3402 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3403 u32 exit_reason
= vmx
->exit_reason
;
3404 u32 vectoring_info
= vmx
->idt_vectoring_info
;
3406 trace_kvm_exit(exit_reason
, kvm_rip_read(vcpu
));
3408 /* If we need to emulate an MMIO from handle_invalid_guest_state
3409 * we just return 0 */
3410 if (vmx
->emulation_required
&& emulate_invalid_guest_state
) {
3411 if (guest_state_valid(vcpu
))
3412 vmx
->emulation_required
= 0;
3413 return vmx
->invalid_state_emulation_result
!= EMULATE_DO_MMIO
;
3416 /* Access CR3 don't cause VMExit in paging mode, so we need
3417 * to sync with guest real CR3. */
3418 if (enable_ept
&& is_paging(vcpu
))
3419 vcpu
->arch
.cr3
= vmcs_readl(GUEST_CR3
);
3421 if (unlikely(vmx
->fail
)) {
3422 kvm_run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
3423 kvm_run
->fail_entry
.hardware_entry_failure_reason
3424 = vmcs_read32(VM_INSTRUCTION_ERROR
);
3428 if ((vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
3429 (exit_reason
!= EXIT_REASON_EXCEPTION_NMI
&&
3430 exit_reason
!= EXIT_REASON_EPT_VIOLATION
&&
3431 exit_reason
!= EXIT_REASON_TASK_SWITCH
))
3432 printk(KERN_WARNING
"%s: unexpected, valid vectoring info "
3433 "(0x%x) and exit reason is 0x%x\n",
3434 __func__
, vectoring_info
, exit_reason
);
3436 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
)) {
3437 if (vmx_interrupt_allowed(vcpu
)) {
3438 vmx
->soft_vnmi_blocked
= 0;
3439 } else if (vmx
->vnmi_blocked_time
> 1000000000LL &&
3440 vcpu
->arch
.nmi_pending
) {
3442 * This CPU don't support us in finding the end of an
3443 * NMI-blocked window if the guest runs with IRQs
3444 * disabled. So we pull the trigger after 1 s of
3445 * futile waiting, but inform the user about this.
3447 printk(KERN_WARNING
"%s: Breaking out of NMI-blocked "
3448 "state on VCPU %d after 1 s timeout\n",
3449 __func__
, vcpu
->vcpu_id
);
3450 vmx
->soft_vnmi_blocked
= 0;
3454 if (exit_reason
< kvm_vmx_max_exit_handlers
3455 && kvm_vmx_exit_handlers
[exit_reason
])
3456 return kvm_vmx_exit_handlers
[exit_reason
](vcpu
, kvm_run
);
3458 kvm_run
->exit_reason
= KVM_EXIT_UNKNOWN
;
3459 kvm_run
->hw
.hardware_exit_reason
= exit_reason
;
3464 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
3466 if (irr
== -1 || tpr
< irr
) {
3467 vmcs_write32(TPR_THRESHOLD
, 0);
3471 vmcs_write32(TPR_THRESHOLD
, irr
);
3474 static void vmx_complete_interrupts(struct vcpu_vmx
*vmx
)
3477 u32 idt_vectoring_info
= vmx
->idt_vectoring_info
;
3481 bool idtv_info_valid
;
3483 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
3485 vmx
->exit_reason
= vmcs_read32(VM_EXIT_REASON
);
3487 /* Handle machine checks before interrupts are enabled */
3488 if ((vmx
->exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
)
3489 || (vmx
->exit_reason
== EXIT_REASON_EXCEPTION_NMI
3490 && is_machine_check(exit_intr_info
)))
3491 kvm_machine_check();
3493 /* We need to handle NMIs before interrupts are enabled */
3494 if ((exit_intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
&&
3495 (exit_intr_info
& INTR_INFO_VALID_MASK
))
3498 idtv_info_valid
= idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
3500 if (cpu_has_virtual_nmis()) {
3501 unblock_nmi
= (exit_intr_info
& INTR_INFO_UNBLOCK_NMI
) != 0;
3502 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
3504 * SDM 3: 27.7.1.2 (September 2008)
3505 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3506 * a guest IRET fault.
3507 * SDM 3: 23.2.2 (September 2008)
3508 * Bit 12 is undefined in any of the following cases:
3509 * If the VM exit sets the valid bit in the IDT-vectoring
3510 * information field.
3511 * If the VM exit is due to a double fault.
3513 if ((exit_intr_info
& INTR_INFO_VALID_MASK
) && unblock_nmi
&&
3514 vector
!= DF_VECTOR
&& !idtv_info_valid
)
3515 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
3516 GUEST_INTR_STATE_NMI
);
3517 } else if (unlikely(vmx
->soft_vnmi_blocked
))
3518 vmx
->vnmi_blocked_time
+=
3519 ktime_to_ns(ktime_sub(ktime_get(), vmx
->entry_time
));
3521 vmx
->vcpu
.arch
.nmi_injected
= false;
3522 kvm_clear_exception_queue(&vmx
->vcpu
);
3523 kvm_clear_interrupt_queue(&vmx
->vcpu
);
3525 if (!idtv_info_valid
)
3528 vector
= idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
;
3529 type
= idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
;
3532 case INTR_TYPE_NMI_INTR
:
3533 vmx
->vcpu
.arch
.nmi_injected
= true;
3535 * SDM 3: 27.7.1.2 (September 2008)
3536 * Clear bit "block by NMI" before VM entry if a NMI
3539 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
3540 GUEST_INTR_STATE_NMI
);
3542 case INTR_TYPE_SOFT_EXCEPTION
:
3543 vmx
->vcpu
.arch
.event_exit_inst_len
=
3544 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
3546 case INTR_TYPE_HARD_EXCEPTION
:
3547 if (idt_vectoring_info
& VECTORING_INFO_DELIVER_CODE_MASK
) {
3548 u32 err
= vmcs_read32(IDT_VECTORING_ERROR_CODE
);
3549 kvm_queue_exception_e(&vmx
->vcpu
, vector
, err
);
3551 kvm_queue_exception(&vmx
->vcpu
, vector
);
3553 case INTR_TYPE_SOFT_INTR
:
3554 vmx
->vcpu
.arch
.event_exit_inst_len
=
3555 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
3557 case INTR_TYPE_EXT_INTR
:
3558 kvm_queue_interrupt(&vmx
->vcpu
, vector
,
3559 type
== INTR_TYPE_SOFT_INTR
);
3567 * Failure to inject an interrupt should give us the information
3568 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
3569 * when fetching the interrupt redirection bitmap in the real-mode
3570 * tss, this doesn't happen. So we do it ourselves.
3572 static void fixup_rmode_irq(struct vcpu_vmx
*vmx
)
3574 vmx
->rmode
.irq
.pending
= 0;
3575 if (kvm_rip_read(&vmx
->vcpu
) + 1 != vmx
->rmode
.irq
.rip
)
3577 kvm_rip_write(&vmx
->vcpu
, vmx
->rmode
.irq
.rip
);
3578 if (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) {
3579 vmx
->idt_vectoring_info
&= ~VECTORING_INFO_TYPE_MASK
;
3580 vmx
->idt_vectoring_info
|= INTR_TYPE_EXT_INTR
;
3583 vmx
->idt_vectoring_info
=
3584 VECTORING_INFO_VALID_MASK
3585 | INTR_TYPE_EXT_INTR
3586 | vmx
->rmode
.irq
.vector
;
3589 #ifdef CONFIG_X86_64
3597 static void vmx_vcpu_run(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
3599 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3601 if (enable_ept
&& is_paging(vcpu
)) {
3602 vmcs_writel(GUEST_CR3
, vcpu
->arch
.cr3
);
3603 ept_load_pdptrs(vcpu
);
3605 /* Record the guest's net vcpu time for enforced NMI injections. */
3606 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
))
3607 vmx
->entry_time
= ktime_get();
3609 /* Handle invalid guest state instead of entering VMX */
3610 if (vmx
->emulation_required
&& emulate_invalid_guest_state
) {
3611 handle_invalid_guest_state(vcpu
, kvm_run
);
3615 if (test_bit(VCPU_REGS_RSP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
3616 vmcs_writel(GUEST_RSP
, vcpu
->arch
.regs
[VCPU_REGS_RSP
]);
3617 if (test_bit(VCPU_REGS_RIP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
3618 vmcs_writel(GUEST_RIP
, vcpu
->arch
.regs
[VCPU_REGS_RIP
]);
3620 /* When single-stepping over STI and MOV SS, we must clear the
3621 * corresponding interruptibility bits in the guest state. Otherwise
3622 * vmentry fails as it then expects bit 14 (BS) in pending debug
3623 * exceptions being set, but that's not correct for the guest debugging
3625 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
3626 vmx_set_interrupt_shadow(vcpu
, 0);
3629 * Loading guest fpu may have cleared host cr0.ts
3631 vmcs_writel(HOST_CR0
, read_cr0());
3633 set_debugreg(vcpu
->arch
.dr6
, 6);
3636 /* Store host registers */
3637 "push %%"R
"dx; push %%"R
"bp;"
3639 "cmp %%"R
"sp, %c[host_rsp](%0) \n\t"
3641 "mov %%"R
"sp, %c[host_rsp](%0) \n\t"
3642 __ex(ASM_VMX_VMWRITE_RSP_RDX
) "\n\t"
3644 /* Reload cr2 if changed */
3645 "mov %c[cr2](%0), %%"R
"ax \n\t"
3646 "mov %%cr2, %%"R
"dx \n\t"
3647 "cmp %%"R
"ax, %%"R
"dx \n\t"
3649 "mov %%"R
"ax, %%cr2 \n\t"
3651 /* Check if vmlaunch of vmresume is needed */
3652 "cmpl $0, %c[launched](%0) \n\t"
3653 /* Load guest registers. Don't clobber flags. */
3654 "mov %c[rax](%0), %%"R
"ax \n\t"
3655 "mov %c[rbx](%0), %%"R
"bx \n\t"
3656 "mov %c[rdx](%0), %%"R
"dx \n\t"
3657 "mov %c[rsi](%0), %%"R
"si \n\t"
3658 "mov %c[rdi](%0), %%"R
"di \n\t"
3659 "mov %c[rbp](%0), %%"R
"bp \n\t"
3660 #ifdef CONFIG_X86_64
3661 "mov %c[r8](%0), %%r8 \n\t"
3662 "mov %c[r9](%0), %%r9 \n\t"
3663 "mov %c[r10](%0), %%r10 \n\t"
3664 "mov %c[r11](%0), %%r11 \n\t"
3665 "mov %c[r12](%0), %%r12 \n\t"
3666 "mov %c[r13](%0), %%r13 \n\t"
3667 "mov %c[r14](%0), %%r14 \n\t"
3668 "mov %c[r15](%0), %%r15 \n\t"
3670 "mov %c[rcx](%0), %%"R
"cx \n\t" /* kills %0 (ecx) */
3672 /* Enter guest mode */
3673 "jne .Llaunched \n\t"
3674 __ex(ASM_VMX_VMLAUNCH
) "\n\t"
3675 "jmp .Lkvm_vmx_return \n\t"
3676 ".Llaunched: " __ex(ASM_VMX_VMRESUME
) "\n\t"
3677 ".Lkvm_vmx_return: "
3678 /* Save guest registers, load host registers, keep flags */
3679 "xchg %0, (%%"R
"sp) \n\t"
3680 "mov %%"R
"ax, %c[rax](%0) \n\t"
3681 "mov %%"R
"bx, %c[rbx](%0) \n\t"
3682 "push"Q
" (%%"R
"sp); pop"Q
" %c[rcx](%0) \n\t"
3683 "mov %%"R
"dx, %c[rdx](%0) \n\t"
3684 "mov %%"R
"si, %c[rsi](%0) \n\t"
3685 "mov %%"R
"di, %c[rdi](%0) \n\t"
3686 "mov %%"R
"bp, %c[rbp](%0) \n\t"
3687 #ifdef CONFIG_X86_64
3688 "mov %%r8, %c[r8](%0) \n\t"
3689 "mov %%r9, %c[r9](%0) \n\t"
3690 "mov %%r10, %c[r10](%0) \n\t"
3691 "mov %%r11, %c[r11](%0) \n\t"
3692 "mov %%r12, %c[r12](%0) \n\t"
3693 "mov %%r13, %c[r13](%0) \n\t"
3694 "mov %%r14, %c[r14](%0) \n\t"
3695 "mov %%r15, %c[r15](%0) \n\t"
3697 "mov %%cr2, %%"R
"ax \n\t"
3698 "mov %%"R
"ax, %c[cr2](%0) \n\t"
3700 "pop %%"R
"bp; pop %%"R
"bp; pop %%"R
"dx \n\t"
3701 "setbe %c[fail](%0) \n\t"
3702 : : "c"(vmx
), "d"((unsigned long)HOST_RSP
),
3703 [launched
]"i"(offsetof(struct vcpu_vmx
, launched
)),
3704 [fail
]"i"(offsetof(struct vcpu_vmx
, fail
)),
3705 [host_rsp
]"i"(offsetof(struct vcpu_vmx
, host_rsp
)),
3706 [rax
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RAX
])),
3707 [rbx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
3708 [rcx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
3709 [rdx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
3710 [rsi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
3711 [rdi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
3712 [rbp
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBP
])),
3713 #ifdef CONFIG_X86_64
3714 [r8
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
3715 [r9
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
3716 [r10
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
3717 [r11
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
3718 [r12
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
3719 [r13
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
3720 [r14
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
3721 [r15
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R15
])),
3723 [cr2
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.cr2
))
3725 , R
"bx", R
"di", R
"si"
3726 #ifdef CONFIG_X86_64
3727 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3731 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
)
3732 | (1 << VCPU_EXREG_PDPTR
));
3733 vcpu
->arch
.regs_dirty
= 0;
3735 get_debugreg(vcpu
->arch
.dr6
, 6);
3737 vmx
->idt_vectoring_info
= vmcs_read32(IDT_VECTORING_INFO_FIELD
);
3738 if (vmx
->rmode
.irq
.pending
)
3739 fixup_rmode_irq(vmx
);
3741 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS
));
3744 vmx_complete_interrupts(vmx
);
3750 static void vmx_free_vmcs(struct kvm_vcpu
*vcpu
)
3752 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3756 free_vmcs(vmx
->vmcs
);
3761 static void vmx_free_vcpu(struct kvm_vcpu
*vcpu
)
3763 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3765 spin_lock(&vmx_vpid_lock
);
3767 __clear_bit(vmx
->vpid
, vmx_vpid_bitmap
);
3768 spin_unlock(&vmx_vpid_lock
);
3769 vmx_free_vmcs(vcpu
);
3770 kfree(vmx
->host_msrs
);
3771 kfree(vmx
->guest_msrs
);
3772 kvm_vcpu_uninit(vcpu
);
3773 kmem_cache_free(kvm_vcpu_cache
, vmx
);
3776 static struct kvm_vcpu
*vmx_create_vcpu(struct kvm
*kvm
, unsigned int id
)
3779 struct vcpu_vmx
*vmx
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
3783 return ERR_PTR(-ENOMEM
);
3787 err
= kvm_vcpu_init(&vmx
->vcpu
, kvm
, id
);
3791 vmx
->guest_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
3792 if (!vmx
->guest_msrs
) {
3797 vmx
->host_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
3798 if (!vmx
->host_msrs
)
3799 goto free_guest_msrs
;
3801 vmx
->vmcs
= alloc_vmcs();
3805 vmcs_clear(vmx
->vmcs
);
3808 vmx_vcpu_load(&vmx
->vcpu
, cpu
);
3809 err
= vmx_vcpu_setup(vmx
);
3810 vmx_vcpu_put(&vmx
->vcpu
);
3814 if (vm_need_virtualize_apic_accesses(kvm
))
3815 if (alloc_apic_access_page(kvm
) != 0)
3819 if (!kvm
->arch
.ept_identity_map_addr
)
3820 kvm
->arch
.ept_identity_map_addr
=
3821 VMX_EPT_IDENTITY_PAGETABLE_ADDR
;
3822 if (alloc_identity_pagetable(kvm
) != 0)
3829 free_vmcs(vmx
->vmcs
);
3831 kfree(vmx
->host_msrs
);
3833 kfree(vmx
->guest_msrs
);
3835 kvm_vcpu_uninit(&vmx
->vcpu
);
3837 kmem_cache_free(kvm_vcpu_cache
, vmx
);
3838 return ERR_PTR(err
);
3841 static void __init
vmx_check_processor_compat(void *rtn
)
3843 struct vmcs_config vmcs_conf
;
3846 if (setup_vmcs_config(&vmcs_conf
) < 0)
3848 if (memcmp(&vmcs_config
, &vmcs_conf
, sizeof(struct vmcs_config
)) != 0) {
3849 printk(KERN_ERR
"kvm: CPU %d feature inconsistency!\n",
3850 smp_processor_id());
3855 static int get_ept_level(void)
3857 return VMX_EPT_DEFAULT_GAW
+ 1;
3860 static u64
vmx_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
3864 /* For VT-d and EPT combination
3865 * 1. MMIO: always map as UC
3867 * a. VT-d without snooping control feature: can't guarantee the
3868 * result, try to trust guest.
3869 * b. VT-d with snooping control feature: snooping control feature of
3870 * VT-d engine can guarantee the cache correctness. Just set it
3871 * to WB to keep consistent with host. So the same as item 3.
3872 * 3. EPT without VT-d: always map as WB and set IGMT=1 to keep
3873 * consistent with host MTRR
3876 ret
= MTRR_TYPE_UNCACHABLE
<< VMX_EPT_MT_EPTE_SHIFT
;
3877 else if (vcpu
->kvm
->arch
.iommu_domain
&&
3878 !(vcpu
->kvm
->arch
.iommu_flags
& KVM_IOMMU_CACHE_COHERENCY
))
3879 ret
= kvm_get_guest_memory_type(vcpu
, gfn
) <<
3880 VMX_EPT_MT_EPTE_SHIFT
;
3882 ret
= (MTRR_TYPE_WRBACK
<< VMX_EPT_MT_EPTE_SHIFT
)
3888 static const struct trace_print_flags vmx_exit_reasons_str
[] = {
3889 { EXIT_REASON_EXCEPTION_NMI
, "exception" },
3890 { EXIT_REASON_EXTERNAL_INTERRUPT
, "ext_irq" },
3891 { EXIT_REASON_TRIPLE_FAULT
, "triple_fault" },
3892 { EXIT_REASON_NMI_WINDOW
, "nmi_window" },
3893 { EXIT_REASON_IO_INSTRUCTION
, "io_instruction" },
3894 { EXIT_REASON_CR_ACCESS
, "cr_access" },
3895 { EXIT_REASON_DR_ACCESS
, "dr_access" },
3896 { EXIT_REASON_CPUID
, "cpuid" },
3897 { EXIT_REASON_MSR_READ
, "rdmsr" },
3898 { EXIT_REASON_MSR_WRITE
, "wrmsr" },
3899 { EXIT_REASON_PENDING_INTERRUPT
, "interrupt_window" },
3900 { EXIT_REASON_HLT
, "halt" },
3901 { EXIT_REASON_INVLPG
, "invlpg" },
3902 { EXIT_REASON_VMCALL
, "hypercall" },
3903 { EXIT_REASON_TPR_BELOW_THRESHOLD
, "tpr_below_thres" },
3904 { EXIT_REASON_APIC_ACCESS
, "apic_access" },
3905 { EXIT_REASON_WBINVD
, "wbinvd" },
3906 { EXIT_REASON_TASK_SWITCH
, "task_switch" },
3907 { EXIT_REASON_EPT_VIOLATION
, "ept_violation" },
3911 static bool vmx_gb_page_enable(void)
3916 static struct kvm_x86_ops vmx_x86_ops
= {
3917 .cpu_has_kvm_support
= cpu_has_kvm_support
,
3918 .disabled_by_bios
= vmx_disabled_by_bios
,
3919 .hardware_setup
= hardware_setup
,
3920 .hardware_unsetup
= hardware_unsetup
,
3921 .check_processor_compatibility
= vmx_check_processor_compat
,
3922 .hardware_enable
= hardware_enable
,
3923 .hardware_disable
= hardware_disable
,
3924 .cpu_has_accelerated_tpr
= report_flexpriority
,
3926 .vcpu_create
= vmx_create_vcpu
,
3927 .vcpu_free
= vmx_free_vcpu
,
3928 .vcpu_reset
= vmx_vcpu_reset
,
3930 .prepare_guest_switch
= vmx_save_host_state
,
3931 .vcpu_load
= vmx_vcpu_load
,
3932 .vcpu_put
= vmx_vcpu_put
,
3934 .set_guest_debug
= set_guest_debug
,
3935 .get_msr
= vmx_get_msr
,
3936 .set_msr
= vmx_set_msr
,
3937 .get_segment_base
= vmx_get_segment_base
,
3938 .get_segment
= vmx_get_segment
,
3939 .set_segment
= vmx_set_segment
,
3940 .get_cpl
= vmx_get_cpl
,
3941 .get_cs_db_l_bits
= vmx_get_cs_db_l_bits
,
3942 .decache_cr4_guest_bits
= vmx_decache_cr4_guest_bits
,
3943 .set_cr0
= vmx_set_cr0
,
3944 .set_cr3
= vmx_set_cr3
,
3945 .set_cr4
= vmx_set_cr4
,
3946 .set_efer
= vmx_set_efer
,
3947 .get_idt
= vmx_get_idt
,
3948 .set_idt
= vmx_set_idt
,
3949 .get_gdt
= vmx_get_gdt
,
3950 .set_gdt
= vmx_set_gdt
,
3951 .cache_reg
= vmx_cache_reg
,
3952 .get_rflags
= vmx_get_rflags
,
3953 .set_rflags
= vmx_set_rflags
,
3955 .tlb_flush
= vmx_flush_tlb
,
3957 .run
= vmx_vcpu_run
,
3958 .handle_exit
= vmx_handle_exit
,
3959 .skip_emulated_instruction
= skip_emulated_instruction
,
3960 .set_interrupt_shadow
= vmx_set_interrupt_shadow
,
3961 .get_interrupt_shadow
= vmx_get_interrupt_shadow
,
3962 .patch_hypercall
= vmx_patch_hypercall
,
3963 .set_irq
= vmx_inject_irq
,
3964 .set_nmi
= vmx_inject_nmi
,
3965 .queue_exception
= vmx_queue_exception
,
3966 .interrupt_allowed
= vmx_interrupt_allowed
,
3967 .nmi_allowed
= vmx_nmi_allowed
,
3968 .enable_nmi_window
= enable_nmi_window
,
3969 .enable_irq_window
= enable_irq_window
,
3970 .update_cr8_intercept
= update_cr8_intercept
,
3972 .set_tss_addr
= vmx_set_tss_addr
,
3973 .get_tdp_level
= get_ept_level
,
3974 .get_mt_mask
= vmx_get_mt_mask
,
3976 .exit_reasons_str
= vmx_exit_reasons_str
,
3977 .gb_page_enable
= vmx_gb_page_enable
,
3980 static int __init
vmx_init(void)
3984 vmx_io_bitmap_a
= (unsigned long *)__get_free_page(GFP_KERNEL
);
3985 if (!vmx_io_bitmap_a
)
3988 vmx_io_bitmap_b
= (unsigned long *)__get_free_page(GFP_KERNEL
);
3989 if (!vmx_io_bitmap_b
) {
3994 vmx_msr_bitmap_legacy
= (unsigned long *)__get_free_page(GFP_KERNEL
);
3995 if (!vmx_msr_bitmap_legacy
) {
4000 vmx_msr_bitmap_longmode
= (unsigned long *)__get_free_page(GFP_KERNEL
);
4001 if (!vmx_msr_bitmap_longmode
) {
4007 * Allow direct access to the PC debug port (it is often used for I/O
4008 * delays, but the vmexits simply slow things down).
4010 memset(vmx_io_bitmap_a
, 0xff, PAGE_SIZE
);
4011 clear_bit(0x80, vmx_io_bitmap_a
);
4013 memset(vmx_io_bitmap_b
, 0xff, PAGE_SIZE
);
4015 memset(vmx_msr_bitmap_legacy
, 0xff, PAGE_SIZE
);
4016 memset(vmx_msr_bitmap_longmode
, 0xff, PAGE_SIZE
);
4018 set_bit(0, vmx_vpid_bitmap
); /* 0 is reserved for host */
4020 r
= kvm_init(&vmx_x86_ops
, sizeof(struct vcpu_vmx
), THIS_MODULE
);
4024 vmx_disable_intercept_for_msr(MSR_FS_BASE
, false);
4025 vmx_disable_intercept_for_msr(MSR_GS_BASE
, false);
4026 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE
, true);
4027 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS
, false);
4028 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP
, false);
4029 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP
, false);
4032 bypass_guest_pf
= 0;
4033 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK
|
4034 VMX_EPT_WRITABLE_MASK
);
4035 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4036 VMX_EPT_EXECUTABLE_MASK
);
4041 if (bypass_guest_pf
)
4042 kvm_mmu_set_nonpresent_ptes(~0xffeull
, 0ull);
4049 free_page((unsigned long)vmx_msr_bitmap_longmode
);
4051 free_page((unsigned long)vmx_msr_bitmap_legacy
);
4053 free_page((unsigned long)vmx_io_bitmap_b
);
4055 free_page((unsigned long)vmx_io_bitmap_a
);
4059 static void __exit
vmx_exit(void)
4061 free_page((unsigned long)vmx_msr_bitmap_legacy
);
4062 free_page((unsigned long)vmx_msr_bitmap_longmode
);
4063 free_page((unsigned long)vmx_io_bitmap_b
);
4064 free_page((unsigned long)vmx_io_bitmap_a
);
4069 module_init(vmx_init
)
4070 module_exit(vmx_exit
)