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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/kernel/entry-armv.S | |
3 | * | |
4 | * Copyright (C) 1996,1997,1998 Russell King. | |
5 | * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk) | |
afeb90ca | 6 | * nommu support by Hyok S. Choi (hyok.choi@samsung.com) |
1da177e4 LT |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * Low-level vector interface routines | |
13 | * | |
70b6f2b4 NP |
14 | * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction |
15 | * that causes it to save wrong values... Be aware! | |
1da177e4 | 16 | */ |
1da177e4 | 17 | |
f09b9979 | 18 | #include <asm/memory.h> |
1da177e4 | 19 | #include <asm/glue.h> |
1da177e4 | 20 | #include <asm/vfpmacros.h> |
bce495d8 | 21 | #include <asm/arch/entry-macro.S> |
d6551e88 | 22 | #include <asm/thread_notify.h> |
1da177e4 LT |
23 | |
24 | #include "entry-header.S" | |
25 | ||
187a51ad RK |
26 | /* |
27 | * Interrupt handling. Preserves r7, r8, r9 | |
28 | */ | |
29 | .macro irq_handler | |
f80dff9d | 30 | get_irqnr_preamble r5, lr |
187a51ad RK |
31 | 1: get_irqnr_and_base r0, r6, r5, lr |
32 | movne r1, sp | |
33 | @ | |
34 | @ routine called with r0 = irq number, r1 = struct pt_regs * | |
35 | @ | |
36 | adrne lr, 1b | |
37 | bne asm_do_IRQ | |
791be9b9 RK |
38 | |
39 | #ifdef CONFIG_SMP | |
40 | /* | |
41 | * XXX | |
42 | * | |
43 | * this macro assumes that irqstat (r6) and base (r5) are | |
44 | * preserved from get_irqnr_and_base above | |
45 | */ | |
46 | test_for_ipi r0, r6, r5, lr | |
47 | movne r0, sp | |
48 | adrne lr, 1b | |
49 | bne do_IPI | |
37ee16ae RK |
50 | |
51 | #ifdef CONFIG_LOCAL_TIMERS | |
52 | test_for_ltirq r0, r6, r5, lr | |
53 | movne r0, sp | |
54 | adrne lr, 1b | |
55 | bne do_local_timer | |
56 | #endif | |
791be9b9 RK |
57 | #endif |
58 | ||
187a51ad RK |
59 | .endm |
60 | ||
785d3cd2 NP |
61 | #ifdef CONFIG_KPROBES |
62 | .section .kprobes.text,"ax",%progbits | |
63 | #else | |
64 | .text | |
65 | #endif | |
66 | ||
1da177e4 LT |
67 | /* |
68 | * Invalid mode handlers | |
69 | */ | |
ccea7a19 RK |
70 | .macro inv_entry, reason |
71 | sub sp, sp, #S_FRAME_SIZE | |
72 | stmib sp, {r1 - lr} | |
1da177e4 LT |
73 | mov r1, #\reason |
74 | .endm | |
75 | ||
76 | __pabt_invalid: | |
ccea7a19 RK |
77 | inv_entry BAD_PREFETCH |
78 | b common_invalid | |
1da177e4 LT |
79 | |
80 | __dabt_invalid: | |
ccea7a19 RK |
81 | inv_entry BAD_DATA |
82 | b common_invalid | |
1da177e4 LT |
83 | |
84 | __irq_invalid: | |
ccea7a19 RK |
85 | inv_entry BAD_IRQ |
86 | b common_invalid | |
1da177e4 LT |
87 | |
88 | __und_invalid: | |
ccea7a19 RK |
89 | inv_entry BAD_UNDEFINSTR |
90 | ||
91 | @ | |
92 | @ XXX fall through to common_invalid | |
93 | @ | |
94 | ||
95 | @ | |
96 | @ common_invalid - generic code for failed exception (re-entrant version of handlers) | |
97 | @ | |
98 | common_invalid: | |
99 | zero_fp | |
100 | ||
101 | ldmia r0, {r4 - r6} | |
102 | add r0, sp, #S_PC @ here for interlock avoidance | |
103 | mov r7, #-1 @ "" "" "" "" | |
104 | str r4, [sp] @ save preserved r0 | |
105 | stmia r0, {r5 - r7} @ lr_<exception>, | |
106 | @ cpsr_<exception>, "old_r0" | |
1da177e4 | 107 | |
1da177e4 | 108 | mov r0, sp |
1da177e4 LT |
109 | b bad_mode |
110 | ||
111 | /* | |
112 | * SVC mode handlers | |
113 | */ | |
2dede2d8 NP |
114 | |
115 | #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) | |
116 | #define SPFIX(code...) code | |
117 | #else | |
118 | #define SPFIX(code...) | |
119 | #endif | |
120 | ||
d30a0c8b NP |
121 | .macro svc_entry, stack_hole=0 |
122 | sub sp, sp, #(S_FRAME_SIZE + \stack_hole) | |
2dede2d8 NP |
123 | SPFIX( tst sp, #4 ) |
124 | SPFIX( bicne sp, sp, #4 ) | |
ccea7a19 RK |
125 | stmib sp, {r1 - r12} |
126 | ||
127 | ldmia r0, {r1 - r3} | |
128 | add r5, sp, #S_SP @ here for interlock avoidance | |
129 | mov r4, #-1 @ "" "" "" "" | |
d30a0c8b | 130 | add r0, sp, #(S_FRAME_SIZE + \stack_hole) |
2dede2d8 | 131 | SPFIX( addne r0, r0, #4 ) |
ccea7a19 RK |
132 | str r1, [sp] @ save the "real" r0 copied |
133 | @ from the exception stack | |
134 | ||
1da177e4 LT |
135 | mov r1, lr |
136 | ||
137 | @ | |
138 | @ We are now ready to fill in the remaining blanks on the stack: | |
139 | @ | |
140 | @ r0 - sp_svc | |
141 | @ r1 - lr_svc | |
142 | @ r2 - lr_<exception>, already fixed up for correct return/restart | |
143 | @ r3 - spsr_<exception> | |
144 | @ r4 - orig_r0 (see pt_regs definition in ptrace.h) | |
145 | @ | |
146 | stmia r5, {r0 - r4} | |
147 | .endm | |
148 | ||
149 | .align 5 | |
150 | __dabt_svc: | |
ccea7a19 | 151 | svc_entry |
1da177e4 LT |
152 | |
153 | @ | |
154 | @ get ready to re-enable interrupts if appropriate | |
155 | @ | |
156 | mrs r9, cpsr | |
157 | tst r3, #PSR_I_BIT | |
158 | biceq r9, r9, #PSR_I_BIT | |
159 | ||
160 | @ | |
161 | @ Call the processor-specific abort handler: | |
162 | @ | |
163 | @ r2 - aborted context pc | |
164 | @ r3 - aborted context cpsr | |
165 | @ | |
166 | @ The abort handler must return the aborted address in r0, and | |
167 | @ the fault status register in r1. r9 must be preserved. | |
168 | @ | |
48d7927b | 169 | #ifdef MULTI_DABORT |
1da177e4 LT |
170 | ldr r4, .LCprocfns |
171 | mov lr, pc | |
48d7927b | 172 | ldr pc, [r4, #PROCESSOR_DABT_FUNC] |
1da177e4 | 173 | #else |
48d7927b | 174 | bl CPU_DABORT_HANDLER |
1da177e4 LT |
175 | #endif |
176 | ||
177 | @ | |
178 | @ set desired IRQ state, then call main handler | |
179 | @ | |
180 | msr cpsr_c, r9 | |
181 | mov r2, sp | |
182 | bl do_DataAbort | |
183 | ||
184 | @ | |
185 | @ IRQs off again before pulling preserved data off the stack | |
186 | @ | |
1ec42c0c | 187 | disable_irq |
1da177e4 LT |
188 | |
189 | @ | |
190 | @ restore SPSR and restart the instruction | |
191 | @ | |
192 | ldr r0, [sp, #S_PSR] | |
193 | msr spsr_cxsf, r0 | |
194 | ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr | |
195 | ||
196 | .align 5 | |
197 | __irq_svc: | |
ccea7a19 RK |
198 | svc_entry |
199 | ||
7ad1bcb2 RK |
200 | #ifdef CONFIG_TRACE_IRQFLAGS |
201 | bl trace_hardirqs_off | |
202 | #endif | |
1da177e4 | 203 | #ifdef CONFIG_PREEMPT |
706fdd9f RK |
204 | get_thread_info tsk |
205 | ldr r8, [tsk, #TI_PREEMPT] @ get preempt count | |
206 | add r7, r8, #1 @ increment it | |
207 | str r7, [tsk, #TI_PREEMPT] | |
1da177e4 | 208 | #endif |
ccea7a19 | 209 | |
187a51ad | 210 | irq_handler |
1da177e4 | 211 | #ifdef CONFIG_PREEMPT |
706fdd9f | 212 | ldr r0, [tsk, #TI_FLAGS] @ get flags |
1da177e4 LT |
213 | tst r0, #_TIF_NEED_RESCHED |
214 | blne svc_preempt | |
215 | preempt_return: | |
706fdd9f RK |
216 | ldr r0, [tsk, #TI_PREEMPT] @ read preempt value |
217 | str r8, [tsk, #TI_PREEMPT] @ restore preempt count | |
1da177e4 | 218 | teq r0, r7 |
1da177e4 LT |
219 | strne r0, [r0, -r0] @ bug() |
220 | #endif | |
221 | ldr r0, [sp, #S_PSR] @ irqs are already disabled | |
222 | msr spsr_cxsf, r0 | |
7ad1bcb2 RK |
223 | #ifdef CONFIG_TRACE_IRQFLAGS |
224 | tst r0, #PSR_I_BIT | |
225 | bleq trace_hardirqs_on | |
226 | #endif | |
1da177e4 LT |
227 | ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr |
228 | ||
229 | .ltorg | |
230 | ||
231 | #ifdef CONFIG_PREEMPT | |
232 | svc_preempt: | |
706fdd9f | 233 | teq r8, #0 @ was preempt count = 0 |
1da177e4 LT |
234 | ldreq r6, .LCirq_stat |
235 | movne pc, lr @ no | |
236 | ldr r0, [r6, #4] @ local_irq_count | |
237 | ldr r1, [r6, #8] @ local_bh_count | |
238 | adds r0, r0, r1 | |
239 | movne pc, lr | |
240 | mov r7, #0 @ preempt_schedule_irq | |
706fdd9f | 241 | str r7, [tsk, #TI_PREEMPT] @ expects preempt_count == 0 |
1da177e4 | 242 | 1: bl preempt_schedule_irq @ irq en/disable is done inside |
706fdd9f | 243 | ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS |
1da177e4 LT |
244 | tst r0, #_TIF_NEED_RESCHED |
245 | beq preempt_return @ go again | |
246 | b 1b | |
247 | #endif | |
248 | ||
249 | .align 5 | |
250 | __und_svc: | |
d30a0c8b NP |
251 | #ifdef CONFIG_KPROBES |
252 | @ If a kprobe is about to simulate a "stmdb sp..." instruction, | |
253 | @ it obviously needs free stack space which then will belong to | |
254 | @ the saved context. | |
255 | svc_entry 64 | |
256 | #else | |
ccea7a19 | 257 | svc_entry |
d30a0c8b | 258 | #endif |
1da177e4 LT |
259 | |
260 | @ | |
261 | @ call emulation code, which returns using r9 if it has emulated | |
262 | @ the instruction, or the more conventional lr if we are to treat | |
263 | @ this as a real undefined instruction | |
264 | @ | |
265 | @ r0 - instruction | |
266 | @ | |
267 | ldr r0, [r2, #-4] | |
268 | adr r9, 1f | |
269 | bl call_fpe | |
270 | ||
271 | mov r0, sp @ struct pt_regs *regs | |
272 | bl do_undefinstr | |
273 | ||
274 | @ | |
275 | @ IRQs off again before pulling preserved data off the stack | |
276 | @ | |
1ec42c0c | 277 | 1: disable_irq |
1da177e4 LT |
278 | |
279 | @ | |
280 | @ restore SPSR and restart the instruction | |
281 | @ | |
282 | ldr lr, [sp, #S_PSR] @ Get SVC cpsr | |
283 | msr spsr_cxsf, lr | |
284 | ldmia sp, {r0 - pc}^ @ Restore SVC registers | |
285 | ||
286 | .align 5 | |
287 | __pabt_svc: | |
ccea7a19 | 288 | svc_entry |
1da177e4 LT |
289 | |
290 | @ | |
291 | @ re-enable interrupts if appropriate | |
292 | @ | |
293 | mrs r9, cpsr | |
294 | tst r3, #PSR_I_BIT | |
295 | biceq r9, r9, #PSR_I_BIT | |
1da177e4 LT |
296 | |
297 | @ | |
298 | @ set args, then call main handler | |
299 | @ | |
300 | @ r0 - address of faulting instruction | |
301 | @ r1 - pointer to registers on stack | |
302 | @ | |
48d7927b PB |
303 | #ifdef MULTI_PABORT |
304 | mov r0, r2 @ pass address of aborted instruction. | |
305 | ldr r4, .LCprocfns | |
306 | mov lr, pc | |
307 | ldr pc, [r4, #PROCESSOR_PABT_FUNC] | |
308 | #else | |
309 | CPU_PABORT_HANDLER(r0, r2) | |
310 | #endif | |
311 | msr cpsr_c, r9 @ Maybe enable interrupts | |
1da177e4 LT |
312 | mov r1, sp @ regs |
313 | bl do_PrefetchAbort @ call abort handler | |
314 | ||
315 | @ | |
316 | @ IRQs off again before pulling preserved data off the stack | |
317 | @ | |
1ec42c0c | 318 | disable_irq |
1da177e4 LT |
319 | |
320 | @ | |
321 | @ restore SPSR and restart the instruction | |
322 | @ | |
323 | ldr r0, [sp, #S_PSR] | |
324 | msr spsr_cxsf, r0 | |
325 | ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr | |
326 | ||
327 | .align 5 | |
49f680ea RK |
328 | .LCcralign: |
329 | .word cr_alignment | |
48d7927b | 330 | #ifdef MULTI_DABORT |
1da177e4 LT |
331 | .LCprocfns: |
332 | .word processor | |
333 | #endif | |
334 | .LCfp: | |
335 | .word fp_enter | |
336 | #ifdef CONFIG_PREEMPT | |
337 | .LCirq_stat: | |
338 | .word irq_stat | |
339 | #endif | |
340 | ||
341 | /* | |
342 | * User mode handlers | |
2dede2d8 NP |
343 | * |
344 | * EABI note: sp_svc is always 64-bit aligned here, so should S_FRAME_SIZE | |
1da177e4 | 345 | */ |
2dede2d8 NP |
346 | |
347 | #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (S_FRAME_SIZE & 7) | |
348 | #error "sizeof(struct pt_regs) must be a multiple of 8" | |
349 | #endif | |
350 | ||
ccea7a19 RK |
351 | .macro usr_entry |
352 | sub sp, sp, #S_FRAME_SIZE | |
353 | stmib sp, {r1 - r12} | |
354 | ||
355 | ldmia r0, {r1 - r3} | |
356 | add r0, sp, #S_PC @ here for interlock avoidance | |
357 | mov r4, #-1 @ "" "" "" "" | |
358 | ||
359 | str r1, [sp] @ save the "real" r0 copied | |
360 | @ from the exception stack | |
1da177e4 LT |
361 | |
362 | @ | |
363 | @ We are now ready to fill in the remaining blanks on the stack: | |
364 | @ | |
365 | @ r2 - lr_<exception>, already fixed up for correct return/restart | |
366 | @ r3 - spsr_<exception> | |
367 | @ r4 - orig_r0 (see pt_regs definition in ptrace.h) | |
368 | @ | |
369 | @ Also, separately save sp_usr and lr_usr | |
370 | @ | |
ccea7a19 RK |
371 | stmia r0, {r2 - r4} |
372 | stmdb r0, {sp, lr}^ | |
1da177e4 LT |
373 | |
374 | @ | |
375 | @ Enable the alignment trap while in kernel mode | |
376 | @ | |
49f680ea | 377 | alignment_trap r0 |
1da177e4 LT |
378 | |
379 | @ | |
380 | @ Clear FP to mark the first stack frame | |
381 | @ | |
382 | zero_fp | |
383 | .endm | |
384 | ||
b49c0f24 NP |
385 | .macro kuser_cmpxchg_check |
386 | #if __LINUX_ARM_ARCH__ < 6 && !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG) | |
387 | #ifndef CONFIG_MMU | |
388 | #warning "NPTL on non MMU needs fixing" | |
389 | #else | |
390 | @ Make sure our user space atomic helper is restarted | |
391 | @ if it was interrupted in a critical region. Here we | |
392 | @ perform a quick test inline since it should be false | |
393 | @ 99.9999% of the time. The rest is done out of line. | |
394 | cmp r2, #TASK_SIZE | |
395 | blhs kuser_cmpxchg_fixup | |
396 | #endif | |
397 | #endif | |
398 | .endm | |
399 | ||
1da177e4 LT |
400 | .align 5 |
401 | __dabt_usr: | |
ccea7a19 | 402 | usr_entry |
b49c0f24 | 403 | kuser_cmpxchg_check |
1da177e4 LT |
404 | |
405 | @ | |
406 | @ Call the processor-specific abort handler: | |
407 | @ | |
408 | @ r2 - aborted context pc | |
409 | @ r3 - aborted context cpsr | |
410 | @ | |
411 | @ The abort handler must return the aborted address in r0, and | |
412 | @ the fault status register in r1. | |
413 | @ | |
48d7927b | 414 | #ifdef MULTI_DABORT |
1da177e4 LT |
415 | ldr r4, .LCprocfns |
416 | mov lr, pc | |
48d7927b | 417 | ldr pc, [r4, #PROCESSOR_DABT_FUNC] |
1da177e4 | 418 | #else |
48d7927b | 419 | bl CPU_DABORT_HANDLER |
1da177e4 LT |
420 | #endif |
421 | ||
422 | @ | |
423 | @ IRQs on, then call the main handler | |
424 | @ | |
1ec42c0c | 425 | enable_irq |
1da177e4 LT |
426 | mov r2, sp |
427 | adr lr, ret_from_exception | |
428 | b do_DataAbort | |
429 | ||
430 | .align 5 | |
431 | __irq_usr: | |
ccea7a19 | 432 | usr_entry |
b49c0f24 | 433 | kuser_cmpxchg_check |
1da177e4 | 434 | |
7ad1bcb2 RK |
435 | #ifdef CONFIG_TRACE_IRQFLAGS |
436 | bl trace_hardirqs_off | |
437 | #endif | |
706fdd9f | 438 | get_thread_info tsk |
1da177e4 | 439 | #ifdef CONFIG_PREEMPT |
706fdd9f RK |
440 | ldr r8, [tsk, #TI_PREEMPT] @ get preempt count |
441 | add r7, r8, #1 @ increment it | |
442 | str r7, [tsk, #TI_PREEMPT] | |
1da177e4 | 443 | #endif |
ccea7a19 | 444 | |
187a51ad | 445 | irq_handler |
1da177e4 | 446 | #ifdef CONFIG_PREEMPT |
706fdd9f RK |
447 | ldr r0, [tsk, #TI_PREEMPT] |
448 | str r8, [tsk, #TI_PREEMPT] | |
1da177e4 | 449 | teq r0, r7 |
1da177e4 | 450 | strne r0, [r0, -r0] |
1da177e4 | 451 | #endif |
7ad1bcb2 RK |
452 | #ifdef CONFIG_TRACE_IRQFLAGS |
453 | bl trace_hardirqs_on | |
454 | #endif | |
ccea7a19 | 455 | |
1da177e4 LT |
456 | mov why, #0 |
457 | b ret_to_user | |
458 | ||
459 | .ltorg | |
460 | ||
461 | .align 5 | |
462 | __und_usr: | |
ccea7a19 | 463 | usr_entry |
1da177e4 | 464 | |
1da177e4 LT |
465 | @ |
466 | @ fall through to the emulation code, which returns using r9 if | |
467 | @ it has emulated the instruction, or the more conventional lr | |
468 | @ if we are to treat this as a real undefined instruction | |
469 | @ | |
470 | @ r0 - instruction | |
471 | @ | |
1da177e4 | 472 | adr r9, ret_from_exception |
db6ccbb6 | 473 | adr lr, __und_usr_unknown |
cb170a45 PB |
474 | tst r3, #PSR_T_BIT @ Thumb mode? |
475 | subeq r4, r2, #4 @ ARM instr at LR - 4 | |
476 | subne r4, r2, #2 @ Thumb instr at LR - 2 | |
477 | 1: ldreqt r0, [r4] | |
478 | beq call_fpe | |
479 | @ Thumb instruction | |
480 | #if __LINUX_ARM_ARCH__ >= 7 | |
481 | 2: ldrht r5, [r4], #2 | |
482 | and r0, r5, #0xf800 @ mask bits 111x x... .... .... | |
483 | cmp r0, #0xe800 @ 32bit instruction if xx != 0 | |
484 | blo __und_usr_unknown | |
485 | 3: ldrht r0, [r4] | |
486 | add r2, r2, #2 @ r2 is PC + 2, make it PC + 4 | |
487 | orr r0, r0, r5, lsl #16 | |
488 | #else | |
489 | b __und_usr_unknown | |
490 | #endif | |
491 | ||
1da177e4 LT |
492 | @ |
493 | @ fallthrough to call_fpe | |
494 | @ | |
495 | ||
496 | /* | |
497 | * The out of line fixup for the ldrt above. | |
498 | */ | |
499 | .section .fixup, "ax" | |
cb170a45 | 500 | 4: mov pc, r9 |
1da177e4 LT |
501 | .previous |
502 | .section __ex_table,"a" | |
cb170a45 PB |
503 | .long 1b, 4b |
504 | #if __LINUX_ARM_ARCH__ >= 7 | |
505 | .long 2b, 4b | |
506 | .long 3b, 4b | |
507 | #endif | |
1da177e4 LT |
508 | .previous |
509 | ||
510 | /* | |
511 | * Check whether the instruction is a co-processor instruction. | |
512 | * If yes, we need to call the relevant co-processor handler. | |
513 | * | |
514 | * Note that we don't do a full check here for the co-processor | |
515 | * instructions; all instructions with bit 27 set are well | |
516 | * defined. The only instructions that should fault are the | |
517 | * co-processor instructions. However, we have to watch out | |
518 | * for the ARM6/ARM7 SWI bug. | |
519 | * | |
b5872db4 CM |
520 | * NEON is a special case that has to be handled here. Not all |
521 | * NEON instructions are co-processor instructions, so we have | |
522 | * to make a special case of checking for them. Plus, there's | |
523 | * five groups of them, so we have a table of mask/opcode pairs | |
524 | * to check against, and if any match then we branch off into the | |
525 | * NEON handler code. | |
526 | * | |
1da177e4 LT |
527 | * Emulators may wish to make use of the following registers: |
528 | * r0 = instruction opcode. | |
529 | * r2 = PC+4 | |
db6ccbb6 | 530 | * r9 = normal "successful" return address |
1da177e4 | 531 | * r10 = this threads thread_info structure. |
db6ccbb6 | 532 | * lr = unrecognised instruction return address |
1da177e4 | 533 | */ |
cb170a45 PB |
534 | @ |
535 | @ Fall-through from Thumb-2 __und_usr | |
536 | @ | |
537 | #ifdef CONFIG_NEON | |
538 | adr r6, .LCneon_thumb_opcodes | |
539 | b 2f | |
540 | #endif | |
1da177e4 | 541 | call_fpe: |
b5872db4 | 542 | #ifdef CONFIG_NEON |
cb170a45 | 543 | adr r6, .LCneon_arm_opcodes |
b5872db4 CM |
544 | 2: |
545 | ldr r7, [r6], #4 @ mask value | |
546 | cmp r7, #0 @ end mask? | |
547 | beq 1f | |
548 | and r8, r0, r7 | |
549 | ldr r7, [r6], #4 @ opcode bits matching in mask | |
550 | cmp r8, r7 @ NEON instruction? | |
551 | bne 2b | |
552 | get_thread_info r10 | |
553 | mov r7, #1 | |
554 | strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used | |
555 | strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used | |
556 | b do_vfp @ let VFP handler handle this | |
557 | 1: | |
558 | #endif | |
1da177e4 | 559 | tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27 |
cb170a45 | 560 | tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2 |
1da177e4 LT |
561 | #if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710) |
562 | and r8, r0, #0x0f000000 @ mask out op-code bits | |
563 | teqne r8, #0x0f000000 @ SWI (ARM6/7 bug)? | |
564 | #endif | |
565 | moveq pc, lr | |
566 | get_thread_info r10 @ get current thread | |
567 | and r8, r0, #0x00000f00 @ mask out CP number | |
568 | mov r7, #1 | |
569 | add r6, r10, #TI_USED_CP | |
570 | strb r7, [r6, r8, lsr #8] @ set appropriate used_cp[] | |
571 | #ifdef CONFIG_IWMMXT | |
572 | @ Test if we need to give access to iWMMXt coprocessors | |
573 | ldr r5, [r10, #TI_FLAGS] | |
574 | rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only | |
575 | movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1) | |
576 | bcs iwmmxt_task_enable | |
577 | #endif | |
1da177e4 LT |
578 | add pc, pc, r8, lsr #6 |
579 | mov r0, r0 | |
580 | ||
581 | mov pc, lr @ CP#0 | |
582 | b do_fpe @ CP#1 (FPE) | |
583 | b do_fpe @ CP#2 (FPE) | |
584 | mov pc, lr @ CP#3 | |
c17fad11 LB |
585 | #ifdef CONFIG_CRUNCH |
586 | b crunch_task_enable @ CP#4 (MaverickCrunch) | |
587 | b crunch_task_enable @ CP#5 (MaverickCrunch) | |
588 | b crunch_task_enable @ CP#6 (MaverickCrunch) | |
589 | #else | |
1da177e4 LT |
590 | mov pc, lr @ CP#4 |
591 | mov pc, lr @ CP#5 | |
592 | mov pc, lr @ CP#6 | |
c17fad11 | 593 | #endif |
1da177e4 LT |
594 | mov pc, lr @ CP#7 |
595 | mov pc, lr @ CP#8 | |
596 | mov pc, lr @ CP#9 | |
597 | #ifdef CONFIG_VFP | |
598 | b do_vfp @ CP#10 (VFP) | |
599 | b do_vfp @ CP#11 (VFP) | |
600 | #else | |
601 | mov pc, lr @ CP#10 (VFP) | |
602 | mov pc, lr @ CP#11 (VFP) | |
603 | #endif | |
604 | mov pc, lr @ CP#12 | |
605 | mov pc, lr @ CP#13 | |
606 | mov pc, lr @ CP#14 (Debug) | |
607 | mov pc, lr @ CP#15 (Control) | |
608 | ||
b5872db4 CM |
609 | #ifdef CONFIG_NEON |
610 | .align 6 | |
611 | ||
cb170a45 | 612 | .LCneon_arm_opcodes: |
b5872db4 CM |
613 | .word 0xfe000000 @ mask |
614 | .word 0xf2000000 @ opcode | |
615 | ||
616 | .word 0xff100000 @ mask | |
617 | .word 0xf4000000 @ opcode | |
618 | ||
cb170a45 PB |
619 | .word 0x00000000 @ mask |
620 | .word 0x00000000 @ opcode | |
621 | ||
622 | .LCneon_thumb_opcodes: | |
623 | .word 0xef000000 @ mask | |
624 | .word 0xef000000 @ opcode | |
625 | ||
626 | .word 0xff100000 @ mask | |
627 | .word 0xf9000000 @ opcode | |
628 | ||
b5872db4 CM |
629 | .word 0x00000000 @ mask |
630 | .word 0x00000000 @ opcode | |
631 | #endif | |
632 | ||
1da177e4 | 633 | do_fpe: |
5d25ac03 | 634 | enable_irq |
1da177e4 LT |
635 | ldr r4, .LCfp |
636 | add r10, r10, #TI_FPSTATE @ r10 = workspace | |
637 | ldr pc, [r4] @ Call FP module USR entry point | |
638 | ||
639 | /* | |
640 | * The FP module is called with these registers set: | |
641 | * r0 = instruction | |
642 | * r2 = PC+4 | |
643 | * r9 = normal "successful" return address | |
644 | * r10 = FP workspace | |
645 | * lr = unrecognised FP instruction return address | |
646 | */ | |
647 | ||
648 | .data | |
649 | ENTRY(fp_enter) | |
db6ccbb6 | 650 | .word no_fp |
785d3cd2 | 651 | .previous |
1da177e4 | 652 | |
db6ccbb6 RK |
653 | no_fp: mov pc, lr |
654 | ||
655 | __und_usr_unknown: | |
1da177e4 LT |
656 | mov r0, sp |
657 | adr lr, ret_from_exception | |
658 | b do_undefinstr | |
659 | ||
660 | .align 5 | |
661 | __pabt_usr: | |
ccea7a19 | 662 | usr_entry |
1da177e4 | 663 | |
48d7927b PB |
664 | #ifdef MULTI_PABORT |
665 | mov r0, r2 @ pass address of aborted instruction. | |
666 | ldr r4, .LCprocfns | |
667 | mov lr, pc | |
668 | ldr pc, [r4, #PROCESSOR_PABT_FUNC] | |
669 | #else | |
670 | CPU_PABORT_HANDLER(r0, r2) | |
671 | #endif | |
1ec42c0c | 672 | enable_irq @ Enable interrupts |
1da177e4 LT |
673 | mov r1, sp @ regs |
674 | bl do_PrefetchAbort @ call abort handler | |
675 | /* fall through */ | |
676 | /* | |
677 | * This is the return code to user mode for abort handlers | |
678 | */ | |
679 | ENTRY(ret_from_exception) | |
680 | get_thread_info tsk | |
681 | mov why, #0 | |
682 | b ret_to_user | |
683 | ||
684 | /* | |
685 | * Register switch for ARMv3 and ARMv4 processors | |
686 | * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info | |
687 | * previous and next are guaranteed not to be the same. | |
688 | */ | |
689 | ENTRY(__switch_to) | |
690 | add ip, r1, #TI_CPU_SAVE | |
691 | ldr r3, [r2, #TI_TP_VALUE] | |
692 | stmia ip!, {r4 - sl, fp, sp, lr} @ Store most regs on stack | |
d6551e88 RK |
693 | #ifdef CONFIG_MMU |
694 | ldr r6, [r2, #TI_CPU_DOMAIN] | |
afeb90ca | 695 | #endif |
b876386e | 696 | #if __LINUX_ARM_ARCH__ >= 6 |
43cc1981 | 697 | #ifdef CONFIG_CPU_32v6K |
b876386e RK |
698 | clrex |
699 | #else | |
73394322 | 700 | strex r5, r4, [ip] @ Clear exclusive monitor |
b876386e RK |
701 | #endif |
702 | #endif | |
4b0e07a5 | 703 | #if defined(CONFIG_HAS_TLS_REG) |
2d2669b6 | 704 | mcr p15, 0, r3, c13, c0, 3 @ set TLS register |
4b0e07a5 | 705 | #elif !defined(CONFIG_TLS_REG_EMUL) |
1da177e4 | 706 | mov r4, #0xffff0fff |
2d2669b6 NP |
707 | str r3, [r4, #-15] @ TLS val at 0xffff0ff0 |
708 | #endif | |
afeb90ca | 709 | #ifdef CONFIG_MMU |
1da177e4 | 710 | mcr p15, 0, r6, c3, c0, 0 @ Set domain register |
1da177e4 | 711 | #endif |
d6551e88 RK |
712 | mov r5, r0 |
713 | add r4, r2, #TI_CPU_SAVE | |
714 | ldr r0, =thread_notify_head | |
715 | mov r1, #THREAD_NOTIFY_SWITCH | |
716 | bl atomic_notifier_call_chain | |
717 | mov r0, r5 | |
718 | ldmia r4, {r4 - sl, fp, sp, pc} @ Load all regs saved previously | |
1da177e4 LT |
719 | |
720 | __INIT | |
2d2669b6 NP |
721 | |
722 | /* | |
723 | * User helpers. | |
724 | * | |
725 | * These are segment of kernel provided user code reachable from user space | |
726 | * at a fixed address in kernel memory. This is used to provide user space | |
727 | * with some operations which require kernel help because of unimplemented | |
728 | * native feature and/or instructions in many ARM CPUs. The idea is for | |
729 | * this code to be executed directly in user mode for best efficiency but | |
730 | * which is too intimate with the kernel counter part to be left to user | |
731 | * libraries. In fact this code might even differ from one CPU to another | |
732 | * depending on the available instruction set and restrictions like on | |
733 | * SMP systems. In other words, the kernel reserves the right to change | |
734 | * this code as needed without warning. Only the entry points and their | |
735 | * results are guaranteed to be stable. | |
736 | * | |
737 | * Each segment is 32-byte aligned and will be moved to the top of the high | |
738 | * vector page. New segments (if ever needed) must be added in front of | |
739 | * existing ones. This mechanism should be used only for things that are | |
740 | * really small and justified, and not be abused freely. | |
741 | * | |
742 | * User space is expected to implement those things inline when optimizing | |
743 | * for a processor that has the necessary native support, but only if such | |
744 | * resulting binaries are already to be incompatible with earlier ARM | |
745 | * processors due to the use of unsupported instructions other than what | |
746 | * is provided here. In other words don't make binaries unable to run on | |
747 | * earlier processors just for the sake of not using these kernel helpers | |
748 | * if your compiled code is not going to use the new instructions for other | |
749 | * purpose. | |
750 | */ | |
751 | ||
ba9b5d76 NP |
752 | .macro usr_ret, reg |
753 | #ifdef CONFIG_ARM_THUMB | |
754 | bx \reg | |
755 | #else | |
756 | mov pc, \reg | |
757 | #endif | |
758 | .endm | |
759 | ||
2d2669b6 NP |
760 | .align 5 |
761 | .globl __kuser_helper_start | |
762 | __kuser_helper_start: | |
763 | ||
7c612bfd NP |
764 | /* |
765 | * Reference prototype: | |
766 | * | |
767 | * void __kernel_memory_barrier(void) | |
768 | * | |
769 | * Input: | |
770 | * | |
771 | * lr = return address | |
772 | * | |
773 | * Output: | |
774 | * | |
775 | * none | |
776 | * | |
777 | * Clobbered: | |
778 | * | |
b49c0f24 | 779 | * none |
7c612bfd NP |
780 | * |
781 | * Definition and user space usage example: | |
782 | * | |
783 | * typedef void (__kernel_dmb_t)(void); | |
784 | * #define __kernel_dmb (*(__kernel_dmb_t *)0xffff0fa0) | |
785 | * | |
786 | * Apply any needed memory barrier to preserve consistency with data modified | |
787 | * manually and __kuser_cmpxchg usage. | |
788 | * | |
789 | * This could be used as follows: | |
790 | * | |
791 | * #define __kernel_dmb() \ | |
792 | * asm volatile ( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #95" \ | |
6896eec0 | 793 | * : : : "r0", "lr","cc" ) |
7c612bfd NP |
794 | */ |
795 | ||
796 | __kuser_memory_barrier: @ 0xffff0fa0 | |
797 | ||
798 | #if __LINUX_ARM_ARCH__ >= 6 && defined(CONFIG_SMP) | |
799 | mcr p15, 0, r0, c7, c10, 5 @ dmb | |
800 | #endif | |
ba9b5d76 | 801 | usr_ret lr |
7c612bfd NP |
802 | |
803 | .align 5 | |
804 | ||
2d2669b6 NP |
805 | /* |
806 | * Reference prototype: | |
807 | * | |
808 | * int __kernel_cmpxchg(int oldval, int newval, int *ptr) | |
809 | * | |
810 | * Input: | |
811 | * | |
812 | * r0 = oldval | |
813 | * r1 = newval | |
814 | * r2 = ptr | |
815 | * lr = return address | |
816 | * | |
817 | * Output: | |
818 | * | |
819 | * r0 = returned value (zero or non-zero) | |
820 | * C flag = set if r0 == 0, clear if r0 != 0 | |
821 | * | |
822 | * Clobbered: | |
823 | * | |
824 | * r3, ip, flags | |
825 | * | |
826 | * Definition and user space usage example: | |
827 | * | |
828 | * typedef int (__kernel_cmpxchg_t)(int oldval, int newval, int *ptr); | |
829 | * #define __kernel_cmpxchg (*(__kernel_cmpxchg_t *)0xffff0fc0) | |
830 | * | |
831 | * Atomically store newval in *ptr if *ptr is equal to oldval for user space. | |
832 | * Return zero if *ptr was changed or non-zero if no exchange happened. | |
833 | * The C flag is also set if *ptr was changed to allow for assembly | |
834 | * optimization in the calling code. | |
835 | * | |
5964eae8 NP |
836 | * Notes: |
837 | * | |
838 | * - This routine already includes memory barriers as needed. | |
839 | * | |
2d2669b6 NP |
840 | * For example, a user space atomic_add implementation could look like this: |
841 | * | |
842 | * #define atomic_add(ptr, val) \ | |
843 | * ({ register unsigned int *__ptr asm("r2") = (ptr); \ | |
844 | * register unsigned int __result asm("r1"); \ | |
845 | * asm volatile ( \ | |
846 | * "1: @ atomic_add\n\t" \ | |
847 | * "ldr r0, [r2]\n\t" \ | |
848 | * "mov r3, #0xffff0fff\n\t" \ | |
849 | * "add lr, pc, #4\n\t" \ | |
850 | * "add r1, r0, %2\n\t" \ | |
851 | * "add pc, r3, #(0xffff0fc0 - 0xffff0fff)\n\t" \ | |
852 | * "bcc 1b" \ | |
853 | * : "=&r" (__result) \ | |
854 | * : "r" (__ptr), "rIL" (val) \ | |
855 | * : "r0","r3","ip","lr","cc","memory" ); \ | |
856 | * __result; }) | |
857 | */ | |
858 | ||
859 | __kuser_cmpxchg: @ 0xffff0fc0 | |
860 | ||
dcef1f63 | 861 | #if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG) |
2d2669b6 | 862 | |
dcef1f63 NP |
863 | /* |
864 | * Poor you. No fast solution possible... | |
865 | * The kernel itself must perform the operation. | |
866 | * A special ghost syscall is used for that (see traps.c). | |
867 | */ | |
5e097445 NP |
868 | stmfd sp!, {r7, lr} |
869 | mov r7, #0xff00 @ 0xfff0 into r7 for EABI | |
870 | orr r7, r7, #0xf0 | |
dcef1f63 | 871 | swi #0x9ffff0 |
5e097445 | 872 | ldmfd sp!, {r7, pc} |
dcef1f63 NP |
873 | |
874 | #elif __LINUX_ARM_ARCH__ < 6 | |
2d2669b6 | 875 | |
b49c0f24 NP |
876 | #ifdef CONFIG_MMU |
877 | ||
2d2669b6 | 878 | /* |
b49c0f24 NP |
879 | * The only thing that can break atomicity in this cmpxchg |
880 | * implementation is either an IRQ or a data abort exception | |
881 | * causing another process/thread to be scheduled in the middle | |
882 | * of the critical sequence. To prevent this, code is added to | |
883 | * the IRQ and data abort exception handlers to set the pc back | |
884 | * to the beginning of the critical section if it is found to be | |
885 | * within that critical section (see kuser_cmpxchg_fixup). | |
2d2669b6 | 886 | */ |
b49c0f24 NP |
887 | 1: ldr r3, [r2] @ load current val |
888 | subs r3, r3, r0 @ compare with oldval | |
889 | 2: streq r1, [r2] @ store newval if eq | |
890 | rsbs r0, r3, #0 @ set return val and C flag | |
891 | usr_ret lr | |
892 | ||
893 | .text | |
894 | kuser_cmpxchg_fixup: | |
895 | @ Called from kuser_cmpxchg_check macro. | |
896 | @ r2 = address of interrupted insn (must be preserved). | |
897 | @ sp = saved regs. r7 and r8 are clobbered. | |
898 | @ 1b = first critical insn, 2b = last critical insn. | |
899 | @ If r2 >= 1b and r2 <= 2b then saved pc_usr is set to 1b. | |
900 | mov r7, #0xffff0fff | |
901 | sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg))) | |
902 | subs r8, r2, r7 | |
903 | rsbcss r8, r8, #(2b - 1b) | |
904 | strcs r7, [sp, #S_PC] | |
905 | mov pc, lr | |
906 | .previous | |
907 | ||
49bca4c2 NP |
908 | #else |
909 | #warning "NPTL on non MMU needs fixing" | |
910 | mov r0, #-1 | |
911 | adds r0, r0, #0 | |
ba9b5d76 | 912 | usr_ret lr |
b49c0f24 | 913 | #endif |
2d2669b6 NP |
914 | |
915 | #else | |
916 | ||
7c612bfd NP |
917 | #ifdef CONFIG_SMP |
918 | mcr p15, 0, r0, c7, c10, 5 @ dmb | |
919 | #endif | |
b49c0f24 | 920 | 1: ldrex r3, [r2] |
2d2669b6 NP |
921 | subs r3, r3, r0 |
922 | strexeq r3, r1, [r2] | |
b49c0f24 NP |
923 | teqeq r3, #1 |
924 | beq 1b | |
2d2669b6 | 925 | rsbs r0, r3, #0 |
b49c0f24 | 926 | /* beware -- each __kuser slot must be 8 instructions max */ |
7c612bfd | 927 | #ifdef CONFIG_SMP |
b49c0f24 NP |
928 | b __kuser_memory_barrier |
929 | #else | |
ba9b5d76 | 930 | usr_ret lr |
b49c0f24 | 931 | #endif |
2d2669b6 NP |
932 | |
933 | #endif | |
934 | ||
935 | .align 5 | |
936 | ||
937 | /* | |
938 | * Reference prototype: | |
939 | * | |
940 | * int __kernel_get_tls(void) | |
941 | * | |
942 | * Input: | |
943 | * | |
944 | * lr = return address | |
945 | * | |
946 | * Output: | |
947 | * | |
948 | * r0 = TLS value | |
949 | * | |
950 | * Clobbered: | |
951 | * | |
b49c0f24 | 952 | * none |
2d2669b6 NP |
953 | * |
954 | * Definition and user space usage example: | |
955 | * | |
956 | * typedef int (__kernel_get_tls_t)(void); | |
957 | * #define __kernel_get_tls (*(__kernel_get_tls_t *)0xffff0fe0) | |
958 | * | |
959 | * Get the TLS value as previously set via the __ARM_NR_set_tls syscall. | |
960 | * | |
961 | * This could be used as follows: | |
962 | * | |
963 | * #define __kernel_get_tls() \ | |
964 | * ({ register unsigned int __val asm("r0"); \ | |
965 | * asm( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #31" \ | |
966 | * : "=r" (__val) : : "lr","cc" ); \ | |
967 | * __val; }) | |
968 | */ | |
969 | ||
970 | __kuser_get_tls: @ 0xffff0fe0 | |
971 | ||
4b0e07a5 | 972 | #if !defined(CONFIG_HAS_TLS_REG) && !defined(CONFIG_TLS_REG_EMUL) |
2d2669b6 | 973 | ldr r0, [pc, #(16 - 8)] @ TLS stored at 0xffff0ff0 |
2d2669b6 | 974 | #else |
2d2669b6 | 975 | mrc p15, 0, r0, c13, c0, 3 @ read TLS register |
2d2669b6 | 976 | #endif |
ba9b5d76 | 977 | usr_ret lr |
2d2669b6 NP |
978 | |
979 | .rep 5 | |
980 | .word 0 @ pad up to __kuser_helper_version | |
981 | .endr | |
982 | ||
983 | /* | |
984 | * Reference declaration: | |
985 | * | |
986 | * extern unsigned int __kernel_helper_version; | |
987 | * | |
988 | * Definition and user space usage example: | |
989 | * | |
990 | * #define __kernel_helper_version (*(unsigned int *)0xffff0ffc) | |
991 | * | |
992 | * User space may read this to determine the curent number of helpers | |
993 | * available. | |
994 | */ | |
995 | ||
996 | __kuser_helper_version: @ 0xffff0ffc | |
997 | .word ((__kuser_helper_end - __kuser_helper_start) >> 5) | |
998 | ||
999 | .globl __kuser_helper_end | |
1000 | __kuser_helper_end: | |
1001 | ||
1002 | ||
1da177e4 LT |
1003 | /* |
1004 | * Vector stubs. | |
1005 | * | |
7933523d RK |
1006 | * This code is copied to 0xffff0200 so we can use branches in the |
1007 | * vectors, rather than ldr's. Note that this code must not | |
1008 | * exceed 0x300 bytes. | |
1da177e4 LT |
1009 | * |
1010 | * Common stub entry macro: | |
1011 | * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC | |
ccea7a19 RK |
1012 | * |
1013 | * SP points to a minimal amount of processor-private memory, the address | |
1014 | * of which is copied into r0 for the mode specific abort handler. | |
1da177e4 | 1015 | */ |
b7ec4795 | 1016 | .macro vector_stub, name, mode, correction=0 |
1da177e4 LT |
1017 | .align 5 |
1018 | ||
1019 | vector_\name: | |
1da177e4 LT |
1020 | .if \correction |
1021 | sub lr, lr, #\correction | |
1022 | .endif | |
ccea7a19 RK |
1023 | |
1024 | @ | |
1025 | @ Save r0, lr_<exception> (parent PC) and spsr_<exception> | |
1026 | @ (parent CPSR) | |
1027 | @ | |
1028 | stmia sp, {r0, lr} @ save r0, lr | |
1da177e4 | 1029 | mrs lr, spsr |
ccea7a19 RK |
1030 | str lr, [sp, #8] @ save spsr |
1031 | ||
1da177e4 | 1032 | @ |
ccea7a19 | 1033 | @ Prepare for SVC32 mode. IRQs remain disabled. |
1da177e4 | 1034 | @ |
ccea7a19 | 1035 | mrs r0, cpsr |
b7ec4795 | 1036 | eor r0, r0, #(\mode ^ SVC_MODE) |
ccea7a19 | 1037 | msr spsr_cxsf, r0 |
1da177e4 | 1038 | |
ccea7a19 RK |
1039 | @ |
1040 | @ the branch table must immediately follow this code | |
1041 | @ | |
ccea7a19 | 1042 | and lr, lr, #0x0f |
b7ec4795 | 1043 | mov r0, sp |
1da177e4 | 1044 | ldr lr, [pc, lr, lsl #2] |
ccea7a19 | 1045 | movs pc, lr @ branch to handler in SVC mode |
1da177e4 LT |
1046 | .endm |
1047 | ||
7933523d | 1048 | .globl __stubs_start |
1da177e4 LT |
1049 | __stubs_start: |
1050 | /* | |
1051 | * Interrupt dispatcher | |
1052 | */ | |
b7ec4795 | 1053 | vector_stub irq, IRQ_MODE, 4 |
1da177e4 LT |
1054 | |
1055 | .long __irq_usr @ 0 (USR_26 / USR_32) | |
1056 | .long __irq_invalid @ 1 (FIQ_26 / FIQ_32) | |
1057 | .long __irq_invalid @ 2 (IRQ_26 / IRQ_32) | |
1058 | .long __irq_svc @ 3 (SVC_26 / SVC_32) | |
1059 | .long __irq_invalid @ 4 | |
1060 | .long __irq_invalid @ 5 | |
1061 | .long __irq_invalid @ 6 | |
1062 | .long __irq_invalid @ 7 | |
1063 | .long __irq_invalid @ 8 | |
1064 | .long __irq_invalid @ 9 | |
1065 | .long __irq_invalid @ a | |
1066 | .long __irq_invalid @ b | |
1067 | .long __irq_invalid @ c | |
1068 | .long __irq_invalid @ d | |
1069 | .long __irq_invalid @ e | |
1070 | .long __irq_invalid @ f | |
1071 | ||
1072 | /* | |
1073 | * Data abort dispatcher | |
1074 | * Enter in ABT mode, spsr = USR CPSR, lr = USR PC | |
1075 | */ | |
b7ec4795 | 1076 | vector_stub dabt, ABT_MODE, 8 |
1da177e4 LT |
1077 | |
1078 | .long __dabt_usr @ 0 (USR_26 / USR_32) | |
1079 | .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32) | |
1080 | .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32) | |
1081 | .long __dabt_svc @ 3 (SVC_26 / SVC_32) | |
1082 | .long __dabt_invalid @ 4 | |
1083 | .long __dabt_invalid @ 5 | |
1084 | .long __dabt_invalid @ 6 | |
1085 | .long __dabt_invalid @ 7 | |
1086 | .long __dabt_invalid @ 8 | |
1087 | .long __dabt_invalid @ 9 | |
1088 | .long __dabt_invalid @ a | |
1089 | .long __dabt_invalid @ b | |
1090 | .long __dabt_invalid @ c | |
1091 | .long __dabt_invalid @ d | |
1092 | .long __dabt_invalid @ e | |
1093 | .long __dabt_invalid @ f | |
1094 | ||
1095 | /* | |
1096 | * Prefetch abort dispatcher | |
1097 | * Enter in ABT mode, spsr = USR CPSR, lr = USR PC | |
1098 | */ | |
b7ec4795 | 1099 | vector_stub pabt, ABT_MODE, 4 |
1da177e4 LT |
1100 | |
1101 | .long __pabt_usr @ 0 (USR_26 / USR_32) | |
1102 | .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32) | |
1103 | .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32) | |
1104 | .long __pabt_svc @ 3 (SVC_26 / SVC_32) | |
1105 | .long __pabt_invalid @ 4 | |
1106 | .long __pabt_invalid @ 5 | |
1107 | .long __pabt_invalid @ 6 | |
1108 | .long __pabt_invalid @ 7 | |
1109 | .long __pabt_invalid @ 8 | |
1110 | .long __pabt_invalid @ 9 | |
1111 | .long __pabt_invalid @ a | |
1112 | .long __pabt_invalid @ b | |
1113 | .long __pabt_invalid @ c | |
1114 | .long __pabt_invalid @ d | |
1115 | .long __pabt_invalid @ e | |
1116 | .long __pabt_invalid @ f | |
1117 | ||
1118 | /* | |
1119 | * Undef instr entry dispatcher | |
1120 | * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC | |
1121 | */ | |
b7ec4795 | 1122 | vector_stub und, UND_MODE |
1da177e4 LT |
1123 | |
1124 | .long __und_usr @ 0 (USR_26 / USR_32) | |
1125 | .long __und_invalid @ 1 (FIQ_26 / FIQ_32) | |
1126 | .long __und_invalid @ 2 (IRQ_26 / IRQ_32) | |
1127 | .long __und_svc @ 3 (SVC_26 / SVC_32) | |
1128 | .long __und_invalid @ 4 | |
1129 | .long __und_invalid @ 5 | |
1130 | .long __und_invalid @ 6 | |
1131 | .long __und_invalid @ 7 | |
1132 | .long __und_invalid @ 8 | |
1133 | .long __und_invalid @ 9 | |
1134 | .long __und_invalid @ a | |
1135 | .long __und_invalid @ b | |
1136 | .long __und_invalid @ c | |
1137 | .long __und_invalid @ d | |
1138 | .long __und_invalid @ e | |
1139 | .long __und_invalid @ f | |
1140 | ||
1141 | .align 5 | |
1142 | ||
1143 | /*============================================================================= | |
1144 | * Undefined FIQs | |
1145 | *----------------------------------------------------------------------------- | |
1146 | * Enter in FIQ mode, spsr = ANY CPSR, lr = ANY PC | |
1147 | * MUST PRESERVE SVC SPSR, but need to switch to SVC mode to show our msg. | |
1148 | * Basically to switch modes, we *HAVE* to clobber one register... brain | |
1149 | * damage alert! I don't think that we can execute any code in here in any | |
1150 | * other mode than FIQ... Ok you can switch to another mode, but you can't | |
1151 | * get out of that mode without clobbering one register. | |
1152 | */ | |
1153 | vector_fiq: | |
1154 | disable_fiq | |
1155 | subs pc, lr, #4 | |
1156 | ||
1157 | /*============================================================================= | |
1158 | * Address exception handler | |
1159 | *----------------------------------------------------------------------------- | |
1160 | * These aren't too critical. | |
1161 | * (they're not supposed to happen, and won't happen in 32-bit data mode). | |
1162 | */ | |
1163 | ||
1164 | vector_addrexcptn: | |
1165 | b vector_addrexcptn | |
1166 | ||
1167 | /* | |
1168 | * We group all the following data together to optimise | |
1169 | * for CPUs with separate I & D caches. | |
1170 | */ | |
1171 | .align 5 | |
1172 | ||
1173 | .LCvswi: | |
1174 | .word vector_swi | |
1175 | ||
7933523d | 1176 | .globl __stubs_end |
1da177e4 LT |
1177 | __stubs_end: |
1178 | ||
7933523d | 1179 | .equ stubs_offset, __vectors_start + 0x200 - __stubs_start |
1da177e4 | 1180 | |
7933523d RK |
1181 | .globl __vectors_start |
1182 | __vectors_start: | |
1da177e4 | 1183 | swi SYS_ERROR0 |
7933523d RK |
1184 | b vector_und + stubs_offset |
1185 | ldr pc, .LCvswi + stubs_offset | |
1186 | b vector_pabt + stubs_offset | |
1187 | b vector_dabt + stubs_offset | |
1188 | b vector_addrexcptn + stubs_offset | |
1189 | b vector_irq + stubs_offset | |
1190 | b vector_fiq + stubs_offset | |
1191 | ||
1192 | .globl __vectors_end | |
1193 | __vectors_end: | |
1da177e4 LT |
1194 | |
1195 | .data | |
1196 | ||
1da177e4 LT |
1197 | .globl cr_alignment |
1198 | .globl cr_no_alignment | |
1199 | cr_alignment: | |
1200 | .space 4 | |
1201 | cr_no_alignment: | |
1202 | .space 4 |