Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/boot/compressed/head.S | |
3 | * | |
4 | * Copyright (C) 1996-2002 Russell King | |
10c2df65 | 5 | * Copyright (C) 2004 Hyok S. Choi (MPU support) |
1da177e4 LT |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
1da177e4 LT |
11 | #include <linux/linkage.h> |
12 | ||
13 | /* | |
14 | * Debugging stuff | |
15 | * | |
16 | * Note that these macros must not contain any code which is not | |
17 | * 100% relocatable. Any attempt to do so will result in a crash. | |
18 | * Please select one of the following when turning on debugging. | |
19 | */ | |
20 | #ifdef DEBUG | |
5cd0c344 | 21 | |
5cd0c344 | 22 | #if defined(CONFIG_DEBUG_ICEDCC) |
7d95ded9 | 23 | |
dfad549d | 24 | #if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) || defined(CONFIG_CPU_V7) |
4e6d488a | 25 | .macro loadsp, rb, tmp |
7d95ded9 TL |
26 | .endm |
27 | .macro writeb, ch, rb | |
28 | mcr p14, 0, \ch, c0, c5, 0 | |
29 | .endm | |
c633c3cf | 30 | #elif defined(CONFIG_CPU_XSCALE) |
4e6d488a | 31 | .macro loadsp, rb, tmp |
c633c3cf JCPV |
32 | .endm |
33 | .macro writeb, ch, rb | |
34 | mcr p14, 0, \ch, c8, c0, 0 | |
35 | .endm | |
7d95ded9 | 36 | #else |
4e6d488a | 37 | .macro loadsp, rb, tmp |
1da177e4 | 38 | .endm |
224b5be6 | 39 | .macro writeb, ch, rb |
41a9e680 | 40 | mcr p14, 0, \ch, c1, c0, 0 |
1da177e4 | 41 | .endm |
7d95ded9 TL |
42 | #endif |
43 | ||
5cd0c344 | 44 | #else |
224b5be6 | 45 | |
a09e64fb | 46 | #include <mach/debug-macro.S> |
224b5be6 | 47 | |
5cd0c344 RK |
48 | .macro writeb, ch, rb |
49 | senduart \ch, \rb | |
1da177e4 | 50 | .endm |
5cd0c344 | 51 | |
224b5be6 | 52 | #if defined(CONFIG_ARCH_SA1100) |
4e6d488a | 53 | .macro loadsp, rb, tmp |
1da177e4 | 54 | mov \rb, #0x80000000 @ physical base address |
224b5be6 | 55 | #ifdef CONFIG_DEBUG_LL_SER3 |
1da177e4 | 56 | add \rb, \rb, #0x00050000 @ Ser3 |
224b5be6 | 57 | #else |
1da177e4 | 58 | add \rb, \rb, #0x00010000 @ Ser1 |
224b5be6 | 59 | #endif |
1da177e4 | 60 | .endm |
1da177e4 | 61 | #elif defined(CONFIG_ARCH_S3C2410) |
4e6d488a | 62 | .macro loadsp, rb, tmp |
1da177e4 | 63 | mov \rb, #0x50000000 |
c7657846 | 64 | add \rb, \rb, #0x4000 * CONFIG_S3C_LOWLEVEL_UART_PORT |
1da177e4 | 65 | .endm |
1da177e4 | 66 | #else |
4e6d488a TL |
67 | .macro loadsp, rb, tmp |
68 | addruart \rb, \tmp | |
224b5be6 | 69 | .endm |
1da177e4 | 70 | #endif |
5cd0c344 | 71 | #endif |
1da177e4 LT |
72 | #endif |
73 | ||
74 | .macro kputc,val | |
75 | mov r0, \val | |
76 | bl putc | |
77 | .endm | |
78 | ||
79 | .macro kphex,val,len | |
80 | mov r0, \val | |
81 | mov r1, #\len | |
82 | bl phex | |
83 | .endm | |
84 | ||
85 | .macro debug_reloc_start | |
86 | #ifdef DEBUG | |
87 | kputc #'\n' | |
88 | kphex r6, 8 /* processor id */ | |
89 | kputc #':' | |
90 | kphex r7, 8 /* architecture id */ | |
f12d0d7c | 91 | #ifdef CONFIG_CPU_CP15 |
1da177e4 LT |
92 | kputc #':' |
93 | mrc p15, 0, r0, c1, c0 | |
94 | kphex r0, 8 /* control reg */ | |
f12d0d7c | 95 | #endif |
1da177e4 LT |
96 | kputc #'\n' |
97 | kphex r5, 8 /* decompressed kernel start */ | |
98 | kputc #'-' | |
f4619025 | 99 | kphex r9, 8 /* decompressed kernel end */ |
1da177e4 LT |
100 | kputc #'>' |
101 | kphex r4, 8 /* kernel execution address */ | |
102 | kputc #'\n' | |
103 | #endif | |
104 | .endm | |
105 | ||
106 | .macro debug_reloc_end | |
107 | #ifdef DEBUG | |
108 | kphex r5, 8 /* end of kernel */ | |
109 | kputc #'\n' | |
110 | mov r0, r4 | |
111 | bl memdump /* dump 256 bytes at start of kernel */ | |
112 | #endif | |
113 | .endm | |
114 | ||
115 | .section ".start", #alloc, #execinstr | |
116 | /* | |
117 | * sort out different calling conventions | |
118 | */ | |
119 | .align | |
26e5ca93 | 120 | .arm @ Always enter in ARM state |
1da177e4 LT |
121 | start: |
122 | .type start,#function | |
b11fe388 | 123 | .rept 7 |
1da177e4 LT |
124 | mov r0, r0 |
125 | .endr | |
b11fe388 NP |
126 | ARM( mov r0, r0 ) |
127 | ARM( b 1f ) | |
128 | THUMB( adr r12, BSYM(1f) ) | |
129 | THUMB( bx r12 ) | |
1da177e4 | 130 | |
1da177e4 LT |
131 | .word 0x016f2818 @ Magic numbers to help the loader |
132 | .word start @ absolute load/run zImage address | |
133 | .word _edata @ zImage end address | |
26e5ca93 | 134 | THUMB( .thumb ) |
1da177e4 | 135 | 1: mov r7, r1 @ save architecture ID |
f4619025 | 136 | mov r8, r2 @ save atags pointer |
1da177e4 LT |
137 | |
138 | #ifndef __ARM_ARCH_2__ | |
139 | /* | |
140 | * Booting from Angel - need to enter SVC mode and disable | |
141 | * FIQs/IRQs (numeric definitions from angel arm.h source). | |
142 | * We only do this if we were in user mode on entry. | |
143 | */ | |
144 | mrs r2, cpsr @ get current mode | |
145 | tst r2, #3 @ not user? | |
146 | bne not_angel | |
147 | mov r0, #0x17 @ angel_SWIreason_EnterSVC | |
0e056f20 CM |
148 | ARM( swi 0x123456 ) @ angel_SWI_ARM |
149 | THUMB( svc 0xab ) @ angel_SWI_THUMB | |
1da177e4 LT |
150 | not_angel: |
151 | mrs r2, cpsr @ turn off interrupts to | |
152 | orr r2, r2, #0xc0 @ prevent angel from running | |
153 | msr cpsr_c, r2 | |
154 | #else | |
155 | teqp pc, #0x0c000003 @ turn off interrupts | |
156 | #endif | |
157 | ||
158 | /* | |
159 | * Note that some cache flushing and other stuff may | |
160 | * be needed here - is there an Angel SWI call for this? | |
161 | */ | |
162 | ||
163 | /* | |
164 | * some architecture specific code can be inserted | |
f4619025 | 165 | * by the linker here, but it should preserve r7, r8, and r9. |
1da177e4 LT |
166 | */ |
167 | ||
168 | .text | |
6d7d0ae5 | 169 | |
e69edc79 EM |
170 | #ifdef CONFIG_AUTO_ZRELADDR |
171 | @ determine final kernel image address | |
bfa64c4a DM |
172 | mov r4, pc |
173 | and r4, r4, #0xf8000000 | |
e69edc79 EM |
174 | add r4, r4, #TEXT_OFFSET |
175 | #else | |
9e84ed63 | 176 | ldr r4, =zreladdr |
e69edc79 | 177 | #endif |
1da177e4 | 178 | |
6d7d0ae5 NP |
179 | bl cache_on |
180 | ||
181 | restart: adr r0, LC0 | |
182 | ldmia r0, {r1, r2, r3, r5, r6, r9, r11, r12} | |
183 | ldr sp, [r0, #32] | |
184 | ||
185 | /* | |
186 | * We might be running at a different address. We need | |
187 | * to fix up various pointers. | |
188 | */ | |
189 | sub r0, r0, r1 @ calculate the delta offset | |
190 | add r5, r5, r0 @ _start | |
191 | add r6, r6, r0 @ _edata | |
1da177e4 | 192 | |
6d7d0ae5 NP |
193 | #ifndef CONFIG_ZBOOT_ROM |
194 | /* malloc space is above the relocated stack (64k max) */ | |
195 | add sp, sp, r0 | |
196 | add r10, sp, #0x10000 | |
197 | #else | |
1da177e4 | 198 | /* |
6d7d0ae5 NP |
199 | * With ZBOOT_ROM the bss/stack is non relocatable, |
200 | * but someone could still run this code from RAM, | |
201 | * in which case our reference is _edata. | |
1da177e4 | 202 | */ |
6d7d0ae5 NP |
203 | mov r10, r6 |
204 | #endif | |
205 | ||
206 | /* | |
207 | * Check to see if we will overwrite ourselves. | |
208 | * r4 = final kernel address | |
209 | * r5 = start of this image | |
210 | * r9 = size of decompressed image | |
211 | * r10 = end of this image, including bss/stack/malloc space if non XIP | |
212 | * We basically want: | |
213 | * r4 >= r10 -> OK | |
214 | * r4 + image length <= r5 -> OK | |
215 | */ | |
216 | cmp r4, r10 | |
217 | bhs wont_overwrite | |
218 | add r10, r4, r9 | |
219 | cmp r10, r5 | |
220 | bls wont_overwrite | |
221 | ||
222 | /* | |
223 | * Relocate ourselves past the end of the decompressed kernel. | |
224 | * r5 = start of this image | |
225 | * r6 = _edata | |
226 | * r10 = end of the decompressed kernel | |
227 | * Because we always copy ahead, we need to do it from the end and go | |
228 | * backward in case the source and destination overlap. | |
229 | */ | |
230 | /* Round up to next 256-byte boundary. */ | |
231 | add r10, r10, #256 | |
232 | bic r10, r10, #255 | |
233 | ||
234 | sub r9, r6, r5 @ size to copy | |
235 | add r9, r9, #31 @ rounded up to a multiple | |
236 | bic r9, r9, #31 @ ... of 32 bytes | |
237 | add r6, r9, r5 | |
238 | add r9, r9, r10 | |
239 | ||
240 | 1: ldmdb r6!, {r0 - r3, r10 - r12, lr} | |
241 | cmp r6, r5 | |
242 | stmdb r9!, {r0 - r3, r10 - r12, lr} | |
243 | bhi 1b | |
244 | ||
245 | /* Preserve offset to relocated code. */ | |
246 | sub r6, r9, r6 | |
247 | ||
248 | bl cache_clean_flush | |
249 | ||
250 | adr r0, BSYM(restart) | |
251 | add r0, r0, r6 | |
252 | mov pc, r0 | |
253 | ||
254 | wont_overwrite: | |
255 | /* | |
256 | * If delta is zero, we are running at the address we were linked at. | |
257 | * r0 = delta | |
258 | * r2 = BSS start | |
259 | * r3 = BSS end | |
260 | * r4 = kernel execution address | |
261 | * r7 = architecture ID | |
262 | * r8 = atags pointer | |
263 | * r11 = GOT start | |
264 | * r12 = GOT end | |
265 | * sp = stack pointer | |
266 | */ | |
267 | teq r0, #0 | |
268 | beq not_relocated | |
98e12b5a | 269 | add r11, r11, r0 |
6d7d0ae5 | 270 | add r12, r12, r0 |
1da177e4 LT |
271 | |
272 | #ifndef CONFIG_ZBOOT_ROM | |
273 | /* | |
274 | * If we're running fully PIC === CONFIG_ZBOOT_ROM = n, | |
275 | * we need to fix up pointers into the BSS region. | |
6d7d0ae5 | 276 | * Note that the stack pointer has already been fixed up. |
1da177e4 LT |
277 | */ |
278 | add r2, r2, r0 | |
279 | add r3, r3, r0 | |
1da177e4 LT |
280 | |
281 | /* | |
282 | * Relocate all entries in the GOT table. | |
283 | */ | |
98e12b5a | 284 | 1: ldr r1, [r11, #0] @ relocate entries in the GOT |
1da177e4 | 285 | add r1, r1, r0 @ table. This fixes up the |
98e12b5a | 286 | str r1, [r11], #4 @ C references. |
6d7d0ae5 | 287 | cmp r11, r12 |
1da177e4 LT |
288 | blo 1b |
289 | #else | |
290 | ||
291 | /* | |
292 | * Relocate entries in the GOT table. We only relocate | |
293 | * the entries that are outside the (relocated) BSS region. | |
294 | */ | |
98e12b5a | 295 | 1: ldr r1, [r11, #0] @ relocate entries in the GOT |
1da177e4 LT |
296 | cmp r1, r2 @ entry < bss_start || |
297 | cmphs r3, r1 @ _end < entry | |
298 | addlo r1, r1, r0 @ table. This fixes up the | |
98e12b5a | 299 | str r1, [r11], #4 @ C references. |
6d7d0ae5 | 300 | cmp r11, r12 |
1da177e4 LT |
301 | blo 1b |
302 | #endif | |
303 | ||
304 | not_relocated: mov r0, #0 | |
305 | 1: str r0, [r2], #4 @ clear bss | |
306 | str r0, [r2], #4 | |
307 | str r0, [r2], #4 | |
308 | str r0, [r2], #4 | |
309 | cmp r2, r3 | |
310 | blo 1b | |
311 | ||
1da177e4 | 312 | /* |
6d7d0ae5 NP |
313 | * The C runtime environment should now be setup sufficiently. |
314 | * Set up some pointers, and start decompressing. | |
315 | * r4 = kernel execution address | |
316 | * r7 = architecture ID | |
317 | * r8 = atags pointer | |
1da177e4 | 318 | */ |
6d7d0ae5 NP |
319 | mov r0, r4 |
320 | mov r1, sp @ malloc space above stack | |
321 | add r2, sp, #0x10000 @ 64k max | |
1da177e4 LT |
322 | mov r3, r7 |
323 | bl decompress_kernel | |
1da177e4 | 324 | bl cache_clean_flush |
6d7d0ae5 NP |
325 | bl cache_off |
326 | mov r0, #0 @ must be zero | |
327 | mov r1, r7 @ restore architecture number | |
328 | mov r2, r8 @ restore atags pointer | |
329 | mov pc, r4 @ call kernel | |
1da177e4 | 330 | |
88987ef9 | 331 | .align 2 |
1da177e4 LT |
332 | .type LC0, #object |
333 | LC0: .word LC0 @ r1 | |
334 | .word __bss_start @ r2 | |
335 | .word _end @ r3 | |
1da177e4 | 336 | .word _start @ r5 |
6d7d0ae5 NP |
337 | .word _edata @ r6 |
338 | .word _image_size @ r9 | |
98e12b5a | 339 | .word _got_start @ r11 |
1da177e4 | 340 | .word _got_end @ ip |
88237c25 | 341 | .word user_stack_end @ sp |
1da177e4 LT |
342 | .size LC0, . - LC0 |
343 | ||
344 | #ifdef CONFIG_ARCH_RPC | |
345 | .globl params | |
db7b2b4b | 346 | params: ldr r0, =0x10000100 @ params_phys for RPC |
1da177e4 LT |
347 | mov pc, lr |
348 | .ltorg | |
349 | .align | |
350 | #endif | |
351 | ||
352 | /* | |
353 | * Turn on the cache. We need to setup some page tables so that we | |
354 | * can have both the I and D caches on. | |
355 | * | |
356 | * We place the page tables 16k down from the kernel execution address, | |
357 | * and we hope that nothing else is using it. If we're using it, we | |
358 | * will go pop! | |
359 | * | |
360 | * On entry, | |
361 | * r4 = kernel execution address | |
1da177e4 | 362 | * r7 = architecture number |
f4619025 | 363 | * r8 = atags pointer |
1da177e4 | 364 | * On exit, |
21b2841d | 365 | * r0, r1, r2, r3, r9, r10, r12 corrupted |
1da177e4 | 366 | * This routine must preserve: |
6d7d0ae5 | 367 | * r4, r7, r8 |
1da177e4 LT |
368 | */ |
369 | .align 5 | |
370 | cache_on: mov r3, #8 @ cache_on function | |
371 | b call_cache_fn | |
372 | ||
10c2df65 HC |
373 | /* |
374 | * Initialize the highest priority protection region, PR7 | |
375 | * to cover all 32bit address and cacheable and bufferable. | |
376 | */ | |
377 | __armv4_mpu_cache_on: | |
378 | mov r0, #0x3f @ 4G, the whole | |
379 | mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting | |
380 | mcr p15, 0, r0, c6, c7, 1 | |
381 | ||
382 | mov r0, #0x80 @ PR7 | |
383 | mcr p15, 0, r0, c2, c0, 0 @ D-cache on | |
384 | mcr p15, 0, r0, c2, c0, 1 @ I-cache on | |
385 | mcr p15, 0, r0, c3, c0, 0 @ write-buffer on | |
386 | ||
387 | mov r0, #0xc000 | |
388 | mcr p15, 0, r0, c5, c0, 1 @ I-access permission | |
389 | mcr p15, 0, r0, c5, c0, 0 @ D-access permission | |
390 | ||
391 | mov r0, #0 | |
392 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer | |
393 | mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache | |
394 | mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache | |
395 | mrc p15, 0, r0, c1, c0, 0 @ read control reg | |
396 | @ ...I .... ..D. WC.M | |
397 | orr r0, r0, #0x002d @ .... .... ..1. 11.1 | |
398 | orr r0, r0, #0x1000 @ ...1 .... .... .... | |
399 | ||
400 | mcr p15, 0, r0, c1, c0, 0 @ write control reg | |
401 | ||
402 | mov r0, #0 | |
403 | mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache | |
404 | mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache | |
405 | mov pc, lr | |
406 | ||
407 | __armv3_mpu_cache_on: | |
408 | mov r0, #0x3f @ 4G, the whole | |
409 | mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting | |
410 | ||
411 | mov r0, #0x80 @ PR7 | |
412 | mcr p15, 0, r0, c2, c0, 0 @ cache on | |
413 | mcr p15, 0, r0, c3, c0, 0 @ write-buffer on | |
414 | ||
415 | mov r0, #0xc000 | |
416 | mcr p15, 0, r0, c5, c0, 0 @ access permission | |
417 | ||
418 | mov r0, #0 | |
419 | mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 | |
4a8d57a5 UKK |
420 | /* |
421 | * ?? ARMv3 MMU does not allow reading the control register, | |
422 | * does this really work on ARMv3 MPU? | |
423 | */ | |
10c2df65 HC |
424 | mrc p15, 0, r0, c1, c0, 0 @ read control reg |
425 | @ .... .... .... WC.M | |
426 | orr r0, r0, #0x000d @ .... .... .... 11.1 | |
4a8d57a5 | 427 | /* ?? this overwrites the value constructed above? */ |
10c2df65 HC |
428 | mov r0, #0 |
429 | mcr p15, 0, r0, c1, c0, 0 @ write control reg | |
430 | ||
4a8d57a5 | 431 | /* ?? invalidate for the second time? */ |
10c2df65 HC |
432 | mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 |
433 | mov pc, lr | |
434 | ||
1da177e4 LT |
435 | __setup_mmu: sub r3, r4, #16384 @ Page directory size |
436 | bic r3, r3, #0xff @ Align the pointer | |
437 | bic r3, r3, #0x3f00 | |
438 | /* | |
439 | * Initialise the page tables, turning on the cacheable and bufferable | |
440 | * bits for the RAM area only. | |
441 | */ | |
442 | mov r0, r3 | |
f4619025 RK |
443 | mov r9, r0, lsr #18 |
444 | mov r9, r9, lsl #18 @ start of RAM | |
445 | add r10, r9, #0x10000000 @ a reasonable RAM size | |
1da177e4 LT |
446 | mov r1, #0x12 |
447 | orr r1, r1, #3 << 10 | |
448 | add r2, r3, #16384 | |
265d5e48 | 449 | 1: cmp r1, r9 @ if virt > start of RAM |
1da177e4 | 450 | orrhs r1, r1, #0x0c @ set cacheable, bufferable |
f4619025 | 451 | cmp r1, r10 @ if virt > end of RAM |
1da177e4 LT |
452 | bichs r1, r1, #0x0c @ clear cacheable, bufferable |
453 | str r1, [r0], #4 @ 1:1 mapping | |
454 | add r1, r1, #1048576 | |
455 | teq r0, r2 | |
456 | bne 1b | |
457 | /* | |
458 | * If ever we are running from Flash, then we surely want the cache | |
459 | * to be enabled also for our execution instance... We map 2MB of it | |
460 | * so there is no map overlap problem for up to 1 MB compressed kernel. | |
461 | * If the execution is in RAM then we would only be duplicating the above. | |
462 | */ | |
463 | mov r1, #0x1e | |
464 | orr r1, r1, #3 << 10 | |
bfa64c4a DM |
465 | mov r2, pc |
466 | mov r2, r2, lsr #20 | |
1da177e4 LT |
467 | orr r1, r1, r2, lsl #20 |
468 | add r0, r3, r2, lsl #2 | |
469 | str r1, [r0], #4 | |
470 | add r1, r1, #1048576 | |
471 | str r1, [r0] | |
472 | mov pc, lr | |
93ed3970 | 473 | ENDPROC(__setup_mmu) |
1da177e4 | 474 | |
c76b6b41 | 475 | __armv4_mmu_cache_on: |
1da177e4 | 476 | mov r12, lr |
8bdca0ac | 477 | #ifdef CONFIG_MMU |
1da177e4 LT |
478 | bl __setup_mmu |
479 | mov r0, #0 | |
480 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer | |
481 | mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs | |
482 | mrc p15, 0, r0, c1, c0, 0 @ read control reg | |
483 | orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement | |
484 | orr r0, r0, #0x0030 | |
26584853 CM |
485 | #ifdef CONFIG_CPU_ENDIAN_BE8 |
486 | orr r0, r0, #1 << 25 @ big-endian page tables | |
487 | #endif | |
c76b6b41 | 488 | bl __common_mmu_cache_on |
1da177e4 LT |
489 | mov r0, #0 |
490 | mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs | |
8bdca0ac | 491 | #endif |
1da177e4 LT |
492 | mov pc, r12 |
493 | ||
7d09e854 CM |
494 | __armv7_mmu_cache_on: |
495 | mov r12, lr | |
8bdca0ac | 496 | #ifdef CONFIG_MMU |
7d09e854 CM |
497 | mrc p15, 0, r11, c0, c1, 4 @ read ID_MMFR0 |
498 | tst r11, #0xf @ VMSA | |
499 | blne __setup_mmu | |
500 | mov r0, #0 | |
501 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer | |
502 | tst r11, #0xf @ VMSA | |
503 | mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs | |
8bdca0ac | 504 | #endif |
7d09e854 CM |
505 | mrc p15, 0, r0, c1, c0, 0 @ read control reg |
506 | orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement | |
507 | orr r0, r0, #0x003c @ write buffer | |
8bdca0ac | 508 | #ifdef CONFIG_MMU |
26584853 CM |
509 | #ifdef CONFIG_CPU_ENDIAN_BE8 |
510 | orr r0, r0, #1 << 25 @ big-endian page tables | |
511 | #endif | |
7d09e854 CM |
512 | orrne r0, r0, #1 @ MMU enabled |
513 | movne r1, #-1 | |
514 | mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer | |
515 | mcrne p15, 0, r1, c3, c0, 0 @ load domain access control | |
8bdca0ac | 516 | #endif |
7d09e854 CM |
517 | mcr p15, 0, r0, c1, c0, 0 @ load control register |
518 | mrc p15, 0, r0, c1, c0, 0 @ and read it back | |
519 | mov r0, #0 | |
520 | mcr p15, 0, r0, c7, c5, 4 @ ISB | |
521 | mov pc, r12 | |
522 | ||
28853ac8 PZ |
523 | __fa526_cache_on: |
524 | mov r12, lr | |
525 | bl __setup_mmu | |
526 | mov r0, #0 | |
527 | mcr p15, 0, r0, c7, c7, 0 @ Invalidate whole cache | |
528 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer | |
529 | mcr p15, 0, r0, c8, c7, 0 @ flush UTLB | |
530 | mrc p15, 0, r0, c1, c0, 0 @ read control reg | |
531 | orr r0, r0, #0x1000 @ I-cache enable | |
532 | bl __common_mmu_cache_on | |
533 | mov r0, #0 | |
534 | mcr p15, 0, r0, c8, c7, 0 @ flush UTLB | |
535 | mov pc, r12 | |
536 | ||
c76b6b41 | 537 | __arm6_mmu_cache_on: |
1da177e4 LT |
538 | mov r12, lr |
539 | bl __setup_mmu | |
540 | mov r0, #0 | |
541 | mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 | |
542 | mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3 | |
543 | mov r0, #0x30 | |
c76b6b41 | 544 | bl __common_mmu_cache_on |
1da177e4 LT |
545 | mov r0, #0 |
546 | mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3 | |
547 | mov pc, r12 | |
548 | ||
c76b6b41 | 549 | __common_mmu_cache_on: |
0e056f20 | 550 | #ifndef CONFIG_THUMB2_KERNEL |
1da177e4 LT |
551 | #ifndef DEBUG |
552 | orr r0, r0, #0x000d @ Write buffer, mmu | |
553 | #endif | |
554 | mov r1, #-1 | |
555 | mcr p15, 0, r3, c2, c0, 0 @ load page table pointer | |
556 | mcr p15, 0, r1, c3, c0, 0 @ load domain access control | |
2dc7667b NP |
557 | b 1f |
558 | .align 5 @ cache line aligned | |
559 | 1: mcr p15, 0, r0, c1, c0, 0 @ load control register | |
560 | mrc p15, 0, r0, c1, c0, 0 @ and read it back to | |
561 | sub pc, lr, r0, lsr #32 @ properly flush pipeline | |
0e056f20 | 562 | #endif |
1da177e4 | 563 | |
1da177e4 LT |
564 | /* |
565 | * Here follow the relocatable cache support functions for the | |
566 | * various processors. This is a generic hook for locating an | |
567 | * entry and jumping to an instruction at the specified offset | |
568 | * from the start of the block. Please note this is all position | |
569 | * independent code. | |
570 | * | |
571 | * r1 = corrupted | |
572 | * r2 = corrupted | |
573 | * r3 = block offset | |
98e12b5a | 574 | * r9 = corrupted |
1da177e4 LT |
575 | * r12 = corrupted |
576 | */ | |
577 | ||
578 | call_cache_fn: adr r12, proc_types | |
f12d0d7c | 579 | #ifdef CONFIG_CPU_CP15 |
98e12b5a | 580 | mrc p15, 0, r9, c0, c0 @ get processor ID |
f12d0d7c | 581 | #else |
98e12b5a | 582 | ldr r9, =CONFIG_PROCESSOR_ID |
f12d0d7c | 583 | #endif |
1da177e4 LT |
584 | 1: ldr r1, [r12, #0] @ get value |
585 | ldr r2, [r12, #4] @ get mask | |
98e12b5a | 586 | eor r1, r1, r9 @ (real ^ match) |
1da177e4 | 587 | tst r1, r2 @ & mask |
0e056f20 CM |
588 | ARM( addeq pc, r12, r3 ) @ call cache function |
589 | THUMB( addeq r12, r3 ) | |
590 | THUMB( moveq pc, r12 ) @ call cache function | |
1da177e4 LT |
591 | add r12, r12, #4*5 |
592 | b 1b | |
593 | ||
594 | /* | |
595 | * Table for cache operations. This is basically: | |
596 | * - CPU ID match | |
597 | * - CPU ID mask | |
598 | * - 'cache on' method instruction | |
599 | * - 'cache off' method instruction | |
600 | * - 'cache flush' method instruction | |
601 | * | |
602 | * We match an entry using: ((real_id ^ match) & mask) == 0 | |
603 | * | |
604 | * Writethrough caches generally only need 'on' and 'off' | |
605 | * methods. Writeback caches _must_ have the flush method | |
606 | * defined. | |
607 | */ | |
88987ef9 | 608 | .align 2 |
1da177e4 LT |
609 | .type proc_types,#object |
610 | proc_types: | |
611 | .word 0x41560600 @ ARM6/610 | |
612 | .word 0xffffffe0 | |
0e056f20 CM |
613 | W(b) __arm6_mmu_cache_off @ works, but slow |
614 | W(b) __arm6_mmu_cache_off | |
1da177e4 | 615 | mov pc, lr |
0e056f20 | 616 | THUMB( nop ) |
c76b6b41 HC |
617 | @ b __arm6_mmu_cache_on @ untested |
618 | @ b __arm6_mmu_cache_off | |
619 | @ b __armv3_mmu_cache_flush | |
1da177e4 LT |
620 | |
621 | .word 0x00000000 @ old ARM ID | |
622 | .word 0x0000f000 | |
623 | mov pc, lr | |
0e056f20 | 624 | THUMB( nop ) |
1da177e4 | 625 | mov pc, lr |
0e056f20 | 626 | THUMB( nop ) |
1da177e4 | 627 | mov pc, lr |
0e056f20 | 628 | THUMB( nop ) |
1da177e4 LT |
629 | |
630 | .word 0x41007000 @ ARM7/710 | |
631 | .word 0xfff8fe00 | |
0e056f20 CM |
632 | W(b) __arm7_mmu_cache_off |
633 | W(b) __arm7_mmu_cache_off | |
1da177e4 | 634 | mov pc, lr |
0e056f20 | 635 | THUMB( nop ) |
1da177e4 LT |
636 | |
637 | .word 0x41807200 @ ARM720T (writethrough) | |
638 | .word 0xffffff00 | |
0e056f20 CM |
639 | W(b) __armv4_mmu_cache_on |
640 | W(b) __armv4_mmu_cache_off | |
1da177e4 | 641 | mov pc, lr |
0e056f20 | 642 | THUMB( nop ) |
1da177e4 | 643 | |
10c2df65 HC |
644 | .word 0x41007400 @ ARM74x |
645 | .word 0xff00ff00 | |
0e056f20 CM |
646 | W(b) __armv3_mpu_cache_on |
647 | W(b) __armv3_mpu_cache_off | |
648 | W(b) __armv3_mpu_cache_flush | |
10c2df65 HC |
649 | |
650 | .word 0x41009400 @ ARM94x | |
651 | .word 0xff00ff00 | |
0e056f20 CM |
652 | W(b) __armv4_mpu_cache_on |
653 | W(b) __armv4_mpu_cache_off | |
654 | W(b) __armv4_mpu_cache_flush | |
10c2df65 | 655 | |
1da177e4 LT |
656 | .word 0x00007000 @ ARM7 IDs |
657 | .word 0x0000f000 | |
658 | mov pc, lr | |
0e056f20 | 659 | THUMB( nop ) |
1da177e4 | 660 | mov pc, lr |
0e056f20 | 661 | THUMB( nop ) |
1da177e4 | 662 | mov pc, lr |
0e056f20 | 663 | THUMB( nop ) |
1da177e4 LT |
664 | |
665 | @ Everything from here on will be the new ID system. | |
666 | ||
667 | .word 0x4401a100 @ sa110 / sa1100 | |
668 | .word 0xffffffe0 | |
0e056f20 CM |
669 | W(b) __armv4_mmu_cache_on |
670 | W(b) __armv4_mmu_cache_off | |
671 | W(b) __armv4_mmu_cache_flush | |
1da177e4 LT |
672 | |
673 | .word 0x6901b110 @ sa1110 | |
674 | .word 0xfffffff0 | |
0e056f20 CM |
675 | W(b) __armv4_mmu_cache_on |
676 | W(b) __armv4_mmu_cache_off | |
677 | W(b) __armv4_mmu_cache_flush | |
1da177e4 | 678 | |
4157d317 HZ |
679 | .word 0x56056900 |
680 | .word 0xffffff00 @ PXA9xx | |
0e056f20 CM |
681 | W(b) __armv4_mmu_cache_on |
682 | W(b) __armv4_mmu_cache_off | |
683 | W(b) __armv4_mmu_cache_flush | |
49cbe786 EM |
684 | |
685 | .word 0x56158000 @ PXA168 | |
686 | .word 0xfffff000 | |
0e056f20 CM |
687 | W(b) __armv4_mmu_cache_on |
688 | W(b) __armv4_mmu_cache_off | |
689 | W(b) __armv5tej_mmu_cache_flush | |
49cbe786 | 690 | |
2e2023fe NP |
691 | .word 0x56050000 @ Feroceon |
692 | .word 0xff0f0000 | |
0e056f20 CM |
693 | W(b) __armv4_mmu_cache_on |
694 | W(b) __armv4_mmu_cache_off | |
695 | W(b) __armv5tej_mmu_cache_flush | |
3ebb5a2b | 696 | |
5587931c JS |
697 | #ifdef CONFIG_CPU_FEROCEON_OLD_ID |
698 | /* this conflicts with the standard ARMv5TE entry */ | |
699 | .long 0x41009260 @ Old Feroceon | |
700 | .long 0xff00fff0 | |
701 | b __armv4_mmu_cache_on | |
702 | b __armv4_mmu_cache_off | |
703 | b __armv5tej_mmu_cache_flush | |
704 | #endif | |
705 | ||
28853ac8 PZ |
706 | .word 0x66015261 @ FA526 |
707 | .word 0xff01fff1 | |
0e056f20 CM |
708 | W(b) __fa526_cache_on |
709 | W(b) __armv4_mmu_cache_off | |
710 | W(b) __fa526_cache_flush | |
28853ac8 | 711 | |
1da177e4 LT |
712 | @ These match on the architecture ID |
713 | ||
714 | .word 0x00020000 @ ARMv4T | |
715 | .word 0x000f0000 | |
0e056f20 CM |
716 | W(b) __armv4_mmu_cache_on |
717 | W(b) __armv4_mmu_cache_off | |
718 | W(b) __armv4_mmu_cache_flush | |
1da177e4 LT |
719 | |
720 | .word 0x00050000 @ ARMv5TE | |
721 | .word 0x000f0000 | |
0e056f20 CM |
722 | W(b) __armv4_mmu_cache_on |
723 | W(b) __armv4_mmu_cache_off | |
724 | W(b) __armv4_mmu_cache_flush | |
1da177e4 LT |
725 | |
726 | .word 0x00060000 @ ARMv5TEJ | |
727 | .word 0x000f0000 | |
0e056f20 CM |
728 | W(b) __armv4_mmu_cache_on |
729 | W(b) __armv4_mmu_cache_off | |
75216859 | 730 | W(b) __armv5tej_mmu_cache_flush |
1da177e4 | 731 | |
45a7b9cf | 732 | .word 0x0007b000 @ ARMv6 |
7d09e854 | 733 | .word 0x000ff000 |
0e056f20 CM |
734 | W(b) __armv4_mmu_cache_on |
735 | W(b) __armv4_mmu_cache_off | |
736 | W(b) __armv6_mmu_cache_flush | |
1da177e4 | 737 | |
edabd38e SB |
738 | .word 0x560f5810 @ Marvell PJ4 ARMv6 |
739 | .word 0xff0ffff0 | |
740 | W(b) __armv4_mmu_cache_on | |
741 | W(b) __armv4_mmu_cache_off | |
742 | W(b) __armv6_mmu_cache_flush | |
743 | ||
7d09e854 CM |
744 | .word 0x000f0000 @ new CPU Id |
745 | .word 0x000f0000 | |
0e056f20 CM |
746 | W(b) __armv7_mmu_cache_on |
747 | W(b) __armv7_mmu_cache_off | |
748 | W(b) __armv7_mmu_cache_flush | |
7d09e854 | 749 | |
1da177e4 LT |
750 | .word 0 @ unrecognised type |
751 | .word 0 | |
752 | mov pc, lr | |
0e056f20 | 753 | THUMB( nop ) |
1da177e4 | 754 | mov pc, lr |
0e056f20 | 755 | THUMB( nop ) |
1da177e4 | 756 | mov pc, lr |
0e056f20 | 757 | THUMB( nop ) |
1da177e4 LT |
758 | |
759 | .size proc_types, . - proc_types | |
760 | ||
761 | /* | |
762 | * Turn off the Cache and MMU. ARMv3 does not support | |
763 | * reading the control register, but ARMv4 does. | |
764 | * | |
21b2841d UKK |
765 | * On exit, |
766 | * r0, r1, r2, r3, r9, r12 corrupted | |
767 | * This routine must preserve: | |
6d7d0ae5 | 768 | * r4, r7, r8 |
1da177e4 LT |
769 | */ |
770 | .align 5 | |
771 | cache_off: mov r3, #12 @ cache_off function | |
772 | b call_cache_fn | |
773 | ||
10c2df65 HC |
774 | __armv4_mpu_cache_off: |
775 | mrc p15, 0, r0, c1, c0 | |
776 | bic r0, r0, #0x000d | |
777 | mcr p15, 0, r0, c1, c0 @ turn MPU and cache off | |
778 | mov r0, #0 | |
779 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer | |
780 | mcr p15, 0, r0, c7, c6, 0 @ flush D-Cache | |
781 | mcr p15, 0, r0, c7, c5, 0 @ flush I-Cache | |
782 | mov pc, lr | |
783 | ||
784 | __armv3_mpu_cache_off: | |
785 | mrc p15, 0, r0, c1, c0 | |
786 | bic r0, r0, #0x000d | |
787 | mcr p15, 0, r0, c1, c0, 0 @ turn MPU and cache off | |
788 | mov r0, #0 | |
789 | mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 | |
790 | mov pc, lr | |
791 | ||
c76b6b41 | 792 | __armv4_mmu_cache_off: |
8bdca0ac | 793 | #ifdef CONFIG_MMU |
1da177e4 LT |
794 | mrc p15, 0, r0, c1, c0 |
795 | bic r0, r0, #0x000d | |
796 | mcr p15, 0, r0, c1, c0 @ turn MMU and cache off | |
797 | mov r0, #0 | |
798 | mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4 | |
799 | mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4 | |
8bdca0ac | 800 | #endif |
1da177e4 LT |
801 | mov pc, lr |
802 | ||
7d09e854 CM |
803 | __armv7_mmu_cache_off: |
804 | mrc p15, 0, r0, c1, c0 | |
8bdca0ac | 805 | #ifdef CONFIG_MMU |
7d09e854 | 806 | bic r0, r0, #0x000d |
8bdca0ac CM |
807 | #else |
808 | bic r0, r0, #0x000c | |
809 | #endif | |
7d09e854 CM |
810 | mcr p15, 0, r0, c1, c0 @ turn MMU and cache off |
811 | mov r12, lr | |
812 | bl __armv7_mmu_cache_flush | |
813 | mov r0, #0 | |
8bdca0ac | 814 | #ifdef CONFIG_MMU |
7d09e854 | 815 | mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB |
8bdca0ac | 816 | #endif |
c30c2f99 CM |
817 | mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC |
818 | mcr p15, 0, r0, c7, c10, 4 @ DSB | |
819 | mcr p15, 0, r0, c7, c5, 4 @ ISB | |
7d09e854 CM |
820 | mov pc, r12 |
821 | ||
c76b6b41 | 822 | __arm6_mmu_cache_off: |
1da177e4 | 823 | mov r0, #0x00000030 @ ARM6 control reg. |
c76b6b41 | 824 | b __armv3_mmu_cache_off |
1da177e4 | 825 | |
c76b6b41 | 826 | __arm7_mmu_cache_off: |
1da177e4 | 827 | mov r0, #0x00000070 @ ARM7 control reg. |
c76b6b41 | 828 | b __armv3_mmu_cache_off |
1da177e4 | 829 | |
c76b6b41 | 830 | __armv3_mmu_cache_off: |
1da177e4 LT |
831 | mcr p15, 0, r0, c1, c0, 0 @ turn MMU and cache off |
832 | mov r0, #0 | |
833 | mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 | |
834 | mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3 | |
835 | mov pc, lr | |
836 | ||
837 | /* | |
838 | * Clean and flush the cache to maintain consistency. | |
839 | * | |
1da177e4 | 840 | * On exit, |
21b2841d | 841 | * r1, r2, r3, r9, r10, r11, r12 corrupted |
1da177e4 | 842 | * This routine must preserve: |
6d7d0ae5 | 843 | * r4, r6, r7, r8 |
1da177e4 LT |
844 | */ |
845 | .align 5 | |
846 | cache_clean_flush: | |
847 | mov r3, #16 | |
848 | b call_cache_fn | |
849 | ||
10c2df65 HC |
850 | __armv4_mpu_cache_flush: |
851 | mov r2, #1 | |
852 | mov r3, #0 | |
853 | mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache | |
854 | mov r1, #7 << 5 @ 8 segments | |
855 | 1: orr r3, r1, #63 << 26 @ 64 entries | |
856 | 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index | |
857 | subs r3, r3, #1 << 26 | |
858 | bcs 2b @ entries 63 to 0 | |
859 | subs r1, r1, #1 << 5 | |
860 | bcs 1b @ segments 7 to 0 | |
861 | ||
862 | teq r2, #0 | |
863 | mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache | |
864 | mcr p15, 0, ip, c7, c10, 4 @ drain WB | |
865 | mov pc, lr | |
866 | ||
28853ac8 PZ |
867 | __fa526_cache_flush: |
868 | mov r1, #0 | |
869 | mcr p15, 0, r1, c7, c14, 0 @ clean and invalidate D cache | |
870 | mcr p15, 0, r1, c7, c5, 0 @ flush I cache | |
871 | mcr p15, 0, r1, c7, c10, 4 @ drain WB | |
872 | mov pc, lr | |
10c2df65 | 873 | |
c76b6b41 | 874 | __armv6_mmu_cache_flush: |
1da177e4 LT |
875 | mov r1, #0 |
876 | mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D | |
877 | mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB | |
878 | mcr p15, 0, r1, c7, c15, 0 @ clean+invalidate unified | |
879 | mcr p15, 0, r1, c7, c10, 4 @ drain WB | |
880 | mov pc, lr | |
881 | ||
7d09e854 CM |
882 | __armv7_mmu_cache_flush: |
883 | mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1 | |
884 | tst r10, #0xf << 16 @ hierarchical cache (ARMv7) | |
7d09e854 | 885 | mov r10, #0 |
c30c2f99 | 886 | beq hierarchical |
7d09e854 CM |
887 | mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D |
888 | b iflush | |
889 | hierarchical: | |
c30c2f99 | 890 | mcr p15, 0, r10, c7, c10, 5 @ DMB |
0e056f20 | 891 | stmfd sp!, {r0-r7, r9-r11} |
7d09e854 CM |
892 | mrc p15, 1, r0, c0, c0, 1 @ read clidr |
893 | ands r3, r0, #0x7000000 @ extract loc from clidr | |
894 | mov r3, r3, lsr #23 @ left align loc bit field | |
895 | beq finished @ if loc is 0, then no need to clean | |
896 | mov r10, #0 @ start clean at cache level 0 | |
897 | loop1: | |
898 | add r2, r10, r10, lsr #1 @ work out 3x current cache level | |
899 | mov r1, r0, lsr r2 @ extract cache type bits from clidr | |
900 | and r1, r1, #7 @ mask of the bits for current cache only | |
901 | cmp r1, #2 @ see what cache we have at this level | |
902 | blt skip @ skip if no cache, or just i-cache | |
903 | mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr | |
904 | mcr p15, 0, r10, c7, c5, 4 @ isb to sych the new cssr&csidr | |
905 | mrc p15, 1, r1, c0, c0, 0 @ read the new csidr | |
906 | and r2, r1, #7 @ extract the length of the cache lines | |
907 | add r2, r2, #4 @ add 4 (line length offset) | |
908 | ldr r4, =0x3ff | |
909 | ands r4, r4, r1, lsr #3 @ find maximum number on the way size | |
000b5025 | 910 | clz r5, r4 @ find bit position of way size increment |
7d09e854 CM |
911 | ldr r7, =0x7fff |
912 | ands r7, r7, r1, lsr #13 @ extract max number of the index size | |
913 | loop2: | |
914 | mov r9, r4 @ create working copy of max way size | |
915 | loop3: | |
0e056f20 CM |
916 | ARM( orr r11, r10, r9, lsl r5 ) @ factor way and cache number into r11 |
917 | ARM( orr r11, r11, r7, lsl r2 ) @ factor index number into r11 | |
918 | THUMB( lsl r6, r9, r5 ) | |
919 | THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11 | |
920 | THUMB( lsl r6, r7, r2 ) | |
921 | THUMB( orr r11, r11, r6 ) @ factor index number into r11 | |
7d09e854 CM |
922 | mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way |
923 | subs r9, r9, #1 @ decrement the way | |
924 | bge loop3 | |
925 | subs r7, r7, #1 @ decrement the index | |
926 | bge loop2 | |
927 | skip: | |
928 | add r10, r10, #2 @ increment cache number | |
929 | cmp r3, r10 | |
930 | bgt loop1 | |
931 | finished: | |
0e056f20 | 932 | ldmfd sp!, {r0-r7, r9-r11} |
7d09e854 CM |
933 | mov r10, #0 @ swith back to cache level 0 |
934 | mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr | |
7d09e854 | 935 | iflush: |
c30c2f99 | 936 | mcr p15, 0, r10, c7, c10, 4 @ DSB |
7d09e854 | 937 | mcr p15, 0, r10, c7, c5, 0 @ invalidate I+BTB |
c30c2f99 CM |
938 | mcr p15, 0, r10, c7, c10, 4 @ DSB |
939 | mcr p15, 0, r10, c7, c5, 4 @ ISB | |
7d09e854 CM |
940 | mov pc, lr |
941 | ||
15754bf9 NP |
942 | __armv5tej_mmu_cache_flush: |
943 | 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache | |
944 | bne 1b | |
945 | mcr p15, 0, r0, c7, c5, 0 @ flush I cache | |
946 | mcr p15, 0, r0, c7, c10, 4 @ drain WB | |
947 | mov pc, lr | |
948 | ||
c76b6b41 | 949 | __armv4_mmu_cache_flush: |
1da177e4 LT |
950 | mov r2, #64*1024 @ default: 32K dcache size (*2) |
951 | mov r11, #32 @ default: 32 byte line size | |
952 | mrc p15, 0, r3, c0, c0, 1 @ read cache type | |
98e12b5a | 953 | teq r3, r9 @ cache ID register present? |
1da177e4 LT |
954 | beq no_cache_id |
955 | mov r1, r3, lsr #18 | |
956 | and r1, r1, #7 | |
957 | mov r2, #1024 | |
958 | mov r2, r2, lsl r1 @ base dcache size *2 | |
959 | tst r3, #1 << 14 @ test M bit | |
960 | addne r2, r2, r2, lsr #1 @ +1/2 size if M == 1 | |
961 | mov r3, r3, lsr #12 | |
962 | and r3, r3, #3 | |
963 | mov r11, #8 | |
964 | mov r11, r11, lsl r3 @ cache line size in bytes | |
965 | no_cache_id: | |
0e056f20 CM |
966 | mov r1, pc |
967 | bic r1, r1, #63 @ align to longest cache line | |
1da177e4 | 968 | add r2, r1, r2 |
0e056f20 CM |
969 | 1: |
970 | ARM( ldr r3, [r1], r11 ) @ s/w flush D cache | |
971 | THUMB( ldr r3, [r1] ) @ s/w flush D cache | |
972 | THUMB( add r1, r1, r11 ) | |
1da177e4 LT |
973 | teq r1, r2 |
974 | bne 1b | |
975 | ||
976 | mcr p15, 0, r1, c7, c5, 0 @ flush I cache | |
977 | mcr p15, 0, r1, c7, c6, 0 @ flush D cache | |
978 | mcr p15, 0, r1, c7, c10, 4 @ drain WB | |
979 | mov pc, lr | |
980 | ||
c76b6b41 | 981 | __armv3_mmu_cache_flush: |
10c2df65 | 982 | __armv3_mpu_cache_flush: |
1da177e4 | 983 | mov r1, #0 |
63fa7187 | 984 | mcr p15, 0, r1, c7, c0, 0 @ invalidate whole cache v3 |
1da177e4 LT |
985 | mov pc, lr |
986 | ||
987 | /* | |
988 | * Various debugging routines for printing hex characters and | |
989 | * memory, which again must be relocatable. | |
990 | */ | |
991 | #ifdef DEBUG | |
88987ef9 | 992 | .align 2 |
1da177e4 LT |
993 | .type phexbuf,#object |
994 | phexbuf: .space 12 | |
995 | .size phexbuf, . - phexbuf | |
996 | ||
be6f9f00 | 997 | @ phex corrupts {r0, r1, r2, r3} |
1da177e4 LT |
998 | phex: adr r3, phexbuf |
999 | mov r2, #0 | |
1000 | strb r2, [r3, r1] | |
1001 | 1: subs r1, r1, #1 | |
1002 | movmi r0, r3 | |
1003 | bmi puts | |
1004 | and r2, r0, #15 | |
1005 | mov r0, r0, lsr #4 | |
1006 | cmp r2, #10 | |
1007 | addge r2, r2, #7 | |
1008 | add r2, r2, #'0' | |
1009 | strb r2, [r3, r1] | |
1010 | b 1b | |
1011 | ||
be6f9f00 | 1012 | @ puts corrupts {r0, r1, r2, r3} |
4e6d488a | 1013 | puts: loadsp r3, r1 |
1da177e4 LT |
1014 | 1: ldrb r2, [r0], #1 |
1015 | teq r2, #0 | |
1016 | moveq pc, lr | |
5cd0c344 | 1017 | 2: writeb r2, r3 |
1da177e4 LT |
1018 | mov r1, #0x00020000 |
1019 | 3: subs r1, r1, #1 | |
1020 | bne 3b | |
1021 | teq r2, #'\n' | |
1022 | moveq r2, #'\r' | |
1023 | beq 2b | |
1024 | teq r0, #0 | |
1025 | bne 1b | |
1026 | mov pc, lr | |
be6f9f00 | 1027 | @ putc corrupts {r0, r1, r2, r3} |
1da177e4 LT |
1028 | putc: |
1029 | mov r2, r0 | |
1030 | mov r0, #0 | |
4e6d488a | 1031 | loadsp r3, r1 |
1da177e4 LT |
1032 | b 2b |
1033 | ||
be6f9f00 | 1034 | @ memdump corrupts {r0, r1, r2, r3, r10, r11, r12, lr} |
1da177e4 LT |
1035 | memdump: mov r12, r0 |
1036 | mov r10, lr | |
1037 | mov r11, #0 | |
1038 | 2: mov r0, r11, lsl #2 | |
1039 | add r0, r0, r12 | |
1040 | mov r1, #8 | |
1041 | bl phex | |
1042 | mov r0, #':' | |
1043 | bl putc | |
1044 | 1: mov r0, #' ' | |
1045 | bl putc | |
1046 | ldr r0, [r12, r11, lsl #2] | |
1047 | mov r1, #8 | |
1048 | bl phex | |
1049 | and r0, r11, #7 | |
1050 | teq r0, #3 | |
1051 | moveq r0, #' ' | |
1052 | bleq putc | |
1053 | and r0, r11, #7 | |
1054 | add r11, r11, #1 | |
1055 | teq r0, #7 | |
1056 | bne 1b | |
1057 | mov r0, #'\n' | |
1058 | bl putc | |
1059 | cmp r11, #64 | |
1060 | blt 2b | |
1061 | mov pc, r10 | |
1062 | #endif | |
1063 | ||
92c83ff1 | 1064 | .ltorg |
1da177e4 LT |
1065 | |
1066 | .align | |
b0c4d4ee | 1067 | .section ".stack", "aw", %nobits |
1da177e4 | 1068 | user_stack: .space 4096 |
88237c25 | 1069 | user_stack_end: |