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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/boot/compressed/head.S | |
3 | * | |
4 | * Copyright (C) 1996-2002 Russell King | |
10c2df65 | 5 | * Copyright (C) 2004 Hyok S. Choi (MPU support) |
1da177e4 LT |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
1da177e4 LT |
11 | #include <linux/linkage.h> |
12 | ||
13 | /* | |
14 | * Debugging stuff | |
15 | * | |
16 | * Note that these macros must not contain any code which is not | |
17 | * 100% relocatable. Any attempt to do so will result in a crash. | |
18 | * Please select one of the following when turning on debugging. | |
19 | */ | |
20 | #ifdef DEBUG | |
5cd0c344 | 21 | |
5cd0c344 | 22 | #if defined(CONFIG_DEBUG_ICEDCC) |
1da177e4 LT |
23 | .macro loadsp, rb |
24 | .endm | |
224b5be6 | 25 | .macro writeb, ch, rb |
5cd0c344 | 26 | mcr p14, 0, \ch, c0, c1, 0 |
1da177e4 | 27 | .endm |
5cd0c344 | 28 | #else |
224b5be6 RK |
29 | |
30 | #include <asm/arch/debug-macro.S> | |
31 | ||
5cd0c344 RK |
32 | .macro writeb, ch, rb |
33 | senduart \ch, \rb | |
1da177e4 | 34 | .endm |
5cd0c344 | 35 | |
224b5be6 | 36 | #if defined(CONFIG_ARCH_SA1100) |
1da177e4 LT |
37 | .macro loadsp, rb |
38 | mov \rb, #0x80000000 @ physical base address | |
224b5be6 | 39 | #ifdef CONFIG_DEBUG_LL_SER3 |
1da177e4 | 40 | add \rb, \rb, #0x00050000 @ Ser3 |
224b5be6 | 41 | #else |
1da177e4 | 42 | add \rb, \rb, #0x00010000 @ Ser1 |
224b5be6 | 43 | #endif |
1da177e4 | 44 | .endm |
1da177e4 | 45 | #elif defined(CONFIG_ARCH_S3C2410) |
5cd0c344 | 46 | .macro loadsp, rb |
1da177e4 LT |
47 | mov \rb, #0x50000000 |
48 | add \rb, \rb, #0x4000 * CONFIG_S3C2410_LOWLEVEL_UART_PORT | |
49 | .endm | |
1da177e4 | 50 | #else |
224b5be6 RK |
51 | .macro loadsp, rb |
52 | addruart \rb | |
53 | .endm | |
1da177e4 | 54 | #endif |
5cd0c344 | 55 | #endif |
1da177e4 LT |
56 | #endif |
57 | ||
58 | .macro kputc,val | |
59 | mov r0, \val | |
60 | bl putc | |
61 | .endm | |
62 | ||
63 | .macro kphex,val,len | |
64 | mov r0, \val | |
65 | mov r1, #\len | |
66 | bl phex | |
67 | .endm | |
68 | ||
69 | .macro debug_reloc_start | |
70 | #ifdef DEBUG | |
71 | kputc #'\n' | |
72 | kphex r6, 8 /* processor id */ | |
73 | kputc #':' | |
74 | kphex r7, 8 /* architecture id */ | |
75 | kputc #':' | |
76 | mrc p15, 0, r0, c1, c0 | |
77 | kphex r0, 8 /* control reg */ | |
78 | kputc #'\n' | |
79 | kphex r5, 8 /* decompressed kernel start */ | |
80 | kputc #'-' | |
f4619025 | 81 | kphex r9, 8 /* decompressed kernel end */ |
1da177e4 LT |
82 | kputc #'>' |
83 | kphex r4, 8 /* kernel execution address */ | |
84 | kputc #'\n' | |
85 | #endif | |
86 | .endm | |
87 | ||
88 | .macro debug_reloc_end | |
89 | #ifdef DEBUG | |
90 | kphex r5, 8 /* end of kernel */ | |
91 | kputc #'\n' | |
92 | mov r0, r4 | |
93 | bl memdump /* dump 256 bytes at start of kernel */ | |
94 | #endif | |
95 | .endm | |
96 | ||
97 | .section ".start", #alloc, #execinstr | |
98 | /* | |
99 | * sort out different calling conventions | |
100 | */ | |
101 | .align | |
102 | start: | |
103 | .type start,#function | |
104 | .rept 8 | |
105 | mov r0, r0 | |
106 | .endr | |
107 | ||
108 | b 1f | |
109 | .word 0x016f2818 @ Magic numbers to help the loader | |
110 | .word start @ absolute load/run zImage address | |
111 | .word _edata @ zImage end address | |
112 | 1: mov r7, r1 @ save architecture ID | |
f4619025 | 113 | mov r8, r2 @ save atags pointer |
1da177e4 LT |
114 | |
115 | #ifndef __ARM_ARCH_2__ | |
116 | /* | |
117 | * Booting from Angel - need to enter SVC mode and disable | |
118 | * FIQs/IRQs (numeric definitions from angel arm.h source). | |
119 | * We only do this if we were in user mode on entry. | |
120 | */ | |
121 | mrs r2, cpsr @ get current mode | |
122 | tst r2, #3 @ not user? | |
123 | bne not_angel | |
124 | mov r0, #0x17 @ angel_SWIreason_EnterSVC | |
125 | swi 0x123456 @ angel_SWI_ARM | |
126 | not_angel: | |
127 | mrs r2, cpsr @ turn off interrupts to | |
128 | orr r2, r2, #0xc0 @ prevent angel from running | |
129 | msr cpsr_c, r2 | |
130 | #else | |
131 | teqp pc, #0x0c000003 @ turn off interrupts | |
132 | #endif | |
133 | ||
134 | /* | |
135 | * Note that some cache flushing and other stuff may | |
136 | * be needed here - is there an Angel SWI call for this? | |
137 | */ | |
138 | ||
139 | /* | |
140 | * some architecture specific code can be inserted | |
f4619025 | 141 | * by the linker here, but it should preserve r7, r8, and r9. |
1da177e4 LT |
142 | */ |
143 | ||
144 | .text | |
145 | adr r0, LC0 | |
146 | ldmia r0, {r1, r2, r3, r4, r5, r6, ip, sp} | |
147 | subs r0, r0, r1 @ calculate the delta offset | |
148 | ||
149 | @ if delta is zero, we are | |
150 | beq not_relocated @ running at the address we | |
151 | @ were linked at. | |
152 | ||
153 | /* | |
154 | * We're running at a different address. We need to fix | |
155 | * up various pointers: | |
156 | * r5 - zImage base address | |
157 | * r6 - GOT start | |
158 | * ip - GOT end | |
159 | */ | |
160 | add r5, r5, r0 | |
161 | add r6, r6, r0 | |
162 | add ip, ip, r0 | |
163 | ||
164 | #ifndef CONFIG_ZBOOT_ROM | |
165 | /* | |
166 | * If we're running fully PIC === CONFIG_ZBOOT_ROM = n, | |
167 | * we need to fix up pointers into the BSS region. | |
168 | * r2 - BSS start | |
169 | * r3 - BSS end | |
170 | * sp - stack pointer | |
171 | */ | |
172 | add r2, r2, r0 | |
173 | add r3, r3, r0 | |
174 | add sp, sp, r0 | |
175 | ||
176 | /* | |
177 | * Relocate all entries in the GOT table. | |
178 | */ | |
179 | 1: ldr r1, [r6, #0] @ relocate entries in the GOT | |
180 | add r1, r1, r0 @ table. This fixes up the | |
181 | str r1, [r6], #4 @ C references. | |
182 | cmp r6, ip | |
183 | blo 1b | |
184 | #else | |
185 | ||
186 | /* | |
187 | * Relocate entries in the GOT table. We only relocate | |
188 | * the entries that are outside the (relocated) BSS region. | |
189 | */ | |
190 | 1: ldr r1, [r6, #0] @ relocate entries in the GOT | |
191 | cmp r1, r2 @ entry < bss_start || | |
192 | cmphs r3, r1 @ _end < entry | |
193 | addlo r1, r1, r0 @ table. This fixes up the | |
194 | str r1, [r6], #4 @ C references. | |
195 | cmp r6, ip | |
196 | blo 1b | |
197 | #endif | |
198 | ||
199 | not_relocated: mov r0, #0 | |
200 | 1: str r0, [r2], #4 @ clear bss | |
201 | str r0, [r2], #4 | |
202 | str r0, [r2], #4 | |
203 | str r0, [r2], #4 | |
204 | cmp r2, r3 | |
205 | blo 1b | |
206 | ||
207 | /* | |
208 | * The C runtime environment should now be setup | |
209 | * sufficiently. Turn the cache on, set up some | |
210 | * pointers, and start decompressing. | |
211 | */ | |
212 | bl cache_on | |
213 | ||
214 | mov r1, sp @ malloc space above stack | |
215 | add r2, sp, #0x10000 @ 64k max | |
216 | ||
217 | /* | |
218 | * Check to see if we will overwrite ourselves. | |
219 | * r4 = final kernel address | |
220 | * r5 = start of this image | |
221 | * r2 = end of malloc space (and therefore this image) | |
222 | * We basically want: | |
223 | * r4 >= r2 -> OK | |
224 | * r4 + image length <= r5 -> OK | |
225 | */ | |
226 | cmp r4, r2 | |
227 | bhs wont_overwrite | |
228 | add r0, r4, #4096*1024 @ 4MB largest kernel size | |
229 | cmp r0, r5 | |
230 | bls wont_overwrite | |
231 | ||
232 | mov r5, r2 @ decompress after malloc space | |
233 | mov r0, r5 | |
234 | mov r3, r7 | |
235 | bl decompress_kernel | |
236 | ||
237 | add r0, r0, #127 | |
238 | bic r0, r0, #127 @ align the kernel length | |
239 | /* | |
240 | * r0 = decompressed kernel length | |
241 | * r1-r3 = unused | |
242 | * r4 = kernel execution address | |
243 | * r5 = decompressed kernel start | |
244 | * r6 = processor ID | |
245 | * r7 = architecture ID | |
f4619025 RK |
246 | * r8 = atags pointer |
247 | * r9-r14 = corrupted | |
1da177e4 LT |
248 | */ |
249 | add r1, r5, r0 @ end of decompressed kernel | |
250 | adr r2, reloc_start | |
251 | ldr r3, LC1 | |
252 | add r3, r2, r3 | |
f4619025 RK |
253 | 1: ldmia r2!, {r9 - r14} @ copy relocation code |
254 | stmia r1!, {r9 - r14} | |
255 | ldmia r2!, {r9 - r14} | |
256 | stmia r1!, {r9 - r14} | |
1da177e4 LT |
257 | cmp r2, r3 |
258 | blo 1b | |
259 | ||
260 | bl cache_clean_flush | |
261 | add pc, r5, r0 @ call relocation code | |
262 | ||
263 | /* | |
264 | * We're not in danger of overwriting ourselves. Do this the simple way. | |
265 | * | |
266 | * r4 = kernel execution address | |
267 | * r7 = architecture ID | |
268 | */ | |
269 | wont_overwrite: mov r0, r4 | |
270 | mov r3, r7 | |
271 | bl decompress_kernel | |
272 | b call_kernel | |
273 | ||
274 | .type LC0, #object | |
275 | LC0: .word LC0 @ r1 | |
276 | .word __bss_start @ r2 | |
277 | .word _end @ r3 | |
278 | .word zreladdr @ r4 | |
279 | .word _start @ r5 | |
280 | .word _got_start @ r6 | |
281 | .word _got_end @ ip | |
282 | .word user_stack+4096 @ sp | |
283 | LC1: .word reloc_end - reloc_start | |
284 | .size LC0, . - LC0 | |
285 | ||
286 | #ifdef CONFIG_ARCH_RPC | |
287 | .globl params | |
288 | params: ldr r0, =params_phys | |
289 | mov pc, lr | |
290 | .ltorg | |
291 | .align | |
292 | #endif | |
293 | ||
294 | /* | |
295 | * Turn on the cache. We need to setup some page tables so that we | |
296 | * can have both the I and D caches on. | |
297 | * | |
298 | * We place the page tables 16k down from the kernel execution address, | |
299 | * and we hope that nothing else is using it. If we're using it, we | |
300 | * will go pop! | |
301 | * | |
302 | * On entry, | |
303 | * r4 = kernel execution address | |
304 | * r6 = processor ID | |
305 | * r7 = architecture number | |
f4619025 RK |
306 | * r8 = atags pointer |
307 | * r9 = run-time address of "start" (???) | |
1da177e4 | 308 | * On exit, |
f4619025 | 309 | * r1, r2, r3, r9, r10, r12 corrupted |
1da177e4 | 310 | * This routine must preserve: |
f4619025 | 311 | * r4, r5, r6, r7, r8 |
1da177e4 LT |
312 | */ |
313 | .align 5 | |
314 | cache_on: mov r3, #8 @ cache_on function | |
315 | b call_cache_fn | |
316 | ||
10c2df65 HC |
317 | /* |
318 | * Initialize the highest priority protection region, PR7 | |
319 | * to cover all 32bit address and cacheable and bufferable. | |
320 | */ | |
321 | __armv4_mpu_cache_on: | |
322 | mov r0, #0x3f @ 4G, the whole | |
323 | mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting | |
324 | mcr p15, 0, r0, c6, c7, 1 | |
325 | ||
326 | mov r0, #0x80 @ PR7 | |
327 | mcr p15, 0, r0, c2, c0, 0 @ D-cache on | |
328 | mcr p15, 0, r0, c2, c0, 1 @ I-cache on | |
329 | mcr p15, 0, r0, c3, c0, 0 @ write-buffer on | |
330 | ||
331 | mov r0, #0xc000 | |
332 | mcr p15, 0, r0, c5, c0, 1 @ I-access permission | |
333 | mcr p15, 0, r0, c5, c0, 0 @ D-access permission | |
334 | ||
335 | mov r0, #0 | |
336 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer | |
337 | mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache | |
338 | mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache | |
339 | mrc p15, 0, r0, c1, c0, 0 @ read control reg | |
340 | @ ...I .... ..D. WC.M | |
341 | orr r0, r0, #0x002d @ .... .... ..1. 11.1 | |
342 | orr r0, r0, #0x1000 @ ...1 .... .... .... | |
343 | ||
344 | mcr p15, 0, r0, c1, c0, 0 @ write control reg | |
345 | ||
346 | mov r0, #0 | |
347 | mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache | |
348 | mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache | |
349 | mov pc, lr | |
350 | ||
351 | __armv3_mpu_cache_on: | |
352 | mov r0, #0x3f @ 4G, the whole | |
353 | mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting | |
354 | ||
355 | mov r0, #0x80 @ PR7 | |
356 | mcr p15, 0, r0, c2, c0, 0 @ cache on | |
357 | mcr p15, 0, r0, c3, c0, 0 @ write-buffer on | |
358 | ||
359 | mov r0, #0xc000 | |
360 | mcr p15, 0, r0, c5, c0, 0 @ access permission | |
361 | ||
362 | mov r0, #0 | |
363 | mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 | |
364 | mrc p15, 0, r0, c1, c0, 0 @ read control reg | |
365 | @ .... .... .... WC.M | |
366 | orr r0, r0, #0x000d @ .... .... .... 11.1 | |
367 | mov r0, #0 | |
368 | mcr p15, 0, r0, c1, c0, 0 @ write control reg | |
369 | ||
370 | mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 | |
371 | mov pc, lr | |
372 | ||
1da177e4 LT |
373 | __setup_mmu: sub r3, r4, #16384 @ Page directory size |
374 | bic r3, r3, #0xff @ Align the pointer | |
375 | bic r3, r3, #0x3f00 | |
376 | /* | |
377 | * Initialise the page tables, turning on the cacheable and bufferable | |
378 | * bits for the RAM area only. | |
379 | */ | |
380 | mov r0, r3 | |
f4619025 RK |
381 | mov r9, r0, lsr #18 |
382 | mov r9, r9, lsl #18 @ start of RAM | |
383 | add r10, r9, #0x10000000 @ a reasonable RAM size | |
1da177e4 LT |
384 | mov r1, #0x12 |
385 | orr r1, r1, #3 << 10 | |
386 | add r2, r3, #16384 | |
265d5e48 | 387 | 1: cmp r1, r9 @ if virt > start of RAM |
1da177e4 | 388 | orrhs r1, r1, #0x0c @ set cacheable, bufferable |
f4619025 | 389 | cmp r1, r10 @ if virt > end of RAM |
1da177e4 LT |
390 | bichs r1, r1, #0x0c @ clear cacheable, bufferable |
391 | str r1, [r0], #4 @ 1:1 mapping | |
392 | add r1, r1, #1048576 | |
393 | teq r0, r2 | |
394 | bne 1b | |
395 | /* | |
396 | * If ever we are running from Flash, then we surely want the cache | |
397 | * to be enabled also for our execution instance... We map 2MB of it | |
398 | * so there is no map overlap problem for up to 1 MB compressed kernel. | |
399 | * If the execution is in RAM then we would only be duplicating the above. | |
400 | */ | |
401 | mov r1, #0x1e | |
402 | orr r1, r1, #3 << 10 | |
403 | mov r2, pc, lsr #20 | |
404 | orr r1, r1, r2, lsl #20 | |
405 | add r0, r3, r2, lsl #2 | |
406 | str r1, [r0], #4 | |
407 | add r1, r1, #1048576 | |
408 | str r1, [r0] | |
409 | mov pc, lr | |
410 | ||
c76b6b41 | 411 | __armv4_mmu_cache_on: |
1da177e4 LT |
412 | mov r12, lr |
413 | bl __setup_mmu | |
414 | mov r0, #0 | |
415 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer | |
416 | mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs | |
417 | mrc p15, 0, r0, c1, c0, 0 @ read control reg | |
418 | orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement | |
419 | orr r0, r0, #0x0030 | |
c76b6b41 | 420 | bl __common_mmu_cache_on |
1da177e4 LT |
421 | mov r0, #0 |
422 | mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs | |
423 | mov pc, r12 | |
424 | ||
c76b6b41 | 425 | __arm6_mmu_cache_on: |
1da177e4 LT |
426 | mov r12, lr |
427 | bl __setup_mmu | |
428 | mov r0, #0 | |
429 | mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 | |
430 | mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3 | |
431 | mov r0, #0x30 | |
c76b6b41 | 432 | bl __common_mmu_cache_on |
1da177e4 LT |
433 | mov r0, #0 |
434 | mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3 | |
435 | mov pc, r12 | |
436 | ||
c76b6b41 | 437 | __common_mmu_cache_on: |
1da177e4 LT |
438 | #ifndef DEBUG |
439 | orr r0, r0, #0x000d @ Write buffer, mmu | |
440 | #endif | |
441 | mov r1, #-1 | |
442 | mcr p15, 0, r3, c2, c0, 0 @ load page table pointer | |
443 | mcr p15, 0, r1, c3, c0, 0 @ load domain access control | |
2dc7667b NP |
444 | b 1f |
445 | .align 5 @ cache line aligned | |
446 | 1: mcr p15, 0, r0, c1, c0, 0 @ load control register | |
447 | mrc p15, 0, r0, c1, c0, 0 @ and read it back to | |
448 | sub pc, lr, r0, lsr #32 @ properly flush pipeline | |
1da177e4 LT |
449 | |
450 | /* | |
451 | * All code following this line is relocatable. It is relocated by | |
452 | * the above code to the end of the decompressed kernel image and | |
453 | * executed there. During this time, we have no stacks. | |
454 | * | |
455 | * r0 = decompressed kernel length | |
456 | * r1-r3 = unused | |
457 | * r4 = kernel execution address | |
458 | * r5 = decompressed kernel start | |
459 | * r6 = processor ID | |
460 | * r7 = architecture ID | |
f4619025 RK |
461 | * r8 = atags pointer |
462 | * r9-r14 = corrupted | |
1da177e4 LT |
463 | */ |
464 | .align 5 | |
f4619025 | 465 | reloc_start: add r9, r5, r0 |
1da177e4 LT |
466 | debug_reloc_start |
467 | mov r1, r4 | |
468 | 1: | |
469 | .rept 4 | |
f4619025 RK |
470 | ldmia r5!, {r0, r2, r3, r10 - r14} @ relocate kernel |
471 | stmia r1!, {r0, r2, r3, r10 - r14} | |
1da177e4 LT |
472 | .endr |
473 | ||
f4619025 | 474 | cmp r5, r9 |
1da177e4 LT |
475 | blo 1b |
476 | debug_reloc_end | |
477 | ||
478 | call_kernel: bl cache_clean_flush | |
479 | bl cache_off | |
f4619025 | 480 | mov r0, #0 @ must be zero |
1da177e4 | 481 | mov r1, r7 @ restore architecture number |
f4619025 | 482 | mov r2, r8 @ restore atags pointer |
1da177e4 LT |
483 | mov pc, r4 @ call kernel |
484 | ||
485 | /* | |
486 | * Here follow the relocatable cache support functions for the | |
487 | * various processors. This is a generic hook for locating an | |
488 | * entry and jumping to an instruction at the specified offset | |
489 | * from the start of the block. Please note this is all position | |
490 | * independent code. | |
491 | * | |
492 | * r1 = corrupted | |
493 | * r2 = corrupted | |
494 | * r3 = block offset | |
495 | * r6 = corrupted | |
496 | * r12 = corrupted | |
497 | */ | |
498 | ||
499 | call_cache_fn: adr r12, proc_types | |
500 | mrc p15, 0, r6, c0, c0 @ get processor ID | |
501 | 1: ldr r1, [r12, #0] @ get value | |
502 | ldr r2, [r12, #4] @ get mask | |
503 | eor r1, r1, r6 @ (real ^ match) | |
504 | tst r1, r2 @ & mask | |
505 | addeq pc, r12, r3 @ call cache function | |
506 | add r12, r12, #4*5 | |
507 | b 1b | |
508 | ||
509 | /* | |
510 | * Table for cache operations. This is basically: | |
511 | * - CPU ID match | |
512 | * - CPU ID mask | |
513 | * - 'cache on' method instruction | |
514 | * - 'cache off' method instruction | |
515 | * - 'cache flush' method instruction | |
516 | * | |
517 | * We match an entry using: ((real_id ^ match) & mask) == 0 | |
518 | * | |
519 | * Writethrough caches generally only need 'on' and 'off' | |
520 | * methods. Writeback caches _must_ have the flush method | |
521 | * defined. | |
522 | */ | |
523 | .type proc_types,#object | |
524 | proc_types: | |
525 | .word 0x41560600 @ ARM6/610 | |
526 | .word 0xffffffe0 | |
c76b6b41 HC |
527 | b __arm6_mmu_cache_off @ works, but slow |
528 | b __arm6_mmu_cache_off | |
1da177e4 | 529 | mov pc, lr |
c76b6b41 HC |
530 | @ b __arm6_mmu_cache_on @ untested |
531 | @ b __arm6_mmu_cache_off | |
532 | @ b __armv3_mmu_cache_flush | |
1da177e4 LT |
533 | |
534 | .word 0x00000000 @ old ARM ID | |
535 | .word 0x0000f000 | |
536 | mov pc, lr | |
537 | mov pc, lr | |
538 | mov pc, lr | |
539 | ||
540 | .word 0x41007000 @ ARM7/710 | |
541 | .word 0xfff8fe00 | |
c76b6b41 HC |
542 | b __arm7_mmu_cache_off |
543 | b __arm7_mmu_cache_off | |
1da177e4 LT |
544 | mov pc, lr |
545 | ||
546 | .word 0x41807200 @ ARM720T (writethrough) | |
547 | .word 0xffffff00 | |
c76b6b41 HC |
548 | b __armv4_mmu_cache_on |
549 | b __armv4_mmu_cache_off | |
1da177e4 LT |
550 | mov pc, lr |
551 | ||
10c2df65 HC |
552 | .word 0x41007400 @ ARM74x |
553 | .word 0xff00ff00 | |
554 | b __armv3_mpu_cache_on | |
555 | b __armv3_mpu_cache_off | |
556 | b __armv3_mpu_cache_flush | |
557 | ||
558 | .word 0x41009400 @ ARM94x | |
559 | .word 0xff00ff00 | |
560 | b __armv4_mpu_cache_on | |
561 | b __armv4_mpu_cache_off | |
562 | b __armv4_mpu_cache_flush | |
563 | ||
1da177e4 LT |
564 | .word 0x00007000 @ ARM7 IDs |
565 | .word 0x0000f000 | |
566 | mov pc, lr | |
567 | mov pc, lr | |
568 | mov pc, lr | |
569 | ||
570 | @ Everything from here on will be the new ID system. | |
571 | ||
572 | .word 0x4401a100 @ sa110 / sa1100 | |
573 | .word 0xffffffe0 | |
c76b6b41 HC |
574 | b __armv4_mmu_cache_on |
575 | b __armv4_mmu_cache_off | |
576 | b __armv4_mmu_cache_flush | |
1da177e4 LT |
577 | |
578 | .word 0x6901b110 @ sa1110 | |
579 | .word 0xfffffff0 | |
c76b6b41 HC |
580 | b __armv4_mmu_cache_on |
581 | b __armv4_mmu_cache_off | |
582 | b __armv4_mmu_cache_flush | |
1da177e4 LT |
583 | |
584 | @ These match on the architecture ID | |
585 | ||
586 | .word 0x00020000 @ ARMv4T | |
587 | .word 0x000f0000 | |
c76b6b41 HC |
588 | b __armv4_mmu_cache_on |
589 | b __armv4_mmu_cache_off | |
590 | b __armv4_mmu_cache_flush | |
1da177e4 LT |
591 | |
592 | .word 0x00050000 @ ARMv5TE | |
593 | .word 0x000f0000 | |
c76b6b41 HC |
594 | b __armv4_mmu_cache_on |
595 | b __armv4_mmu_cache_off | |
596 | b __armv4_mmu_cache_flush | |
1da177e4 LT |
597 | |
598 | .word 0x00060000 @ ARMv5TEJ | |
599 | .word 0x000f0000 | |
c76b6b41 HC |
600 | b __armv4_mmu_cache_on |
601 | b __armv4_mmu_cache_off | |
602 | b __armv4_mmu_cache_flush | |
1da177e4 | 603 | |
45a7b9cf CM |
604 | .word 0x0007b000 @ ARMv6 |
605 | .word 0x0007f000 | |
c76b6b41 HC |
606 | b __armv4_mmu_cache_on |
607 | b __armv4_mmu_cache_off | |
608 | b __armv6_mmu_cache_flush | |
1da177e4 LT |
609 | |
610 | .word 0 @ unrecognised type | |
611 | .word 0 | |
612 | mov pc, lr | |
613 | mov pc, lr | |
614 | mov pc, lr | |
615 | ||
616 | .size proc_types, . - proc_types | |
617 | ||
618 | /* | |
619 | * Turn off the Cache and MMU. ARMv3 does not support | |
620 | * reading the control register, but ARMv4 does. | |
621 | * | |
622 | * On entry, r6 = processor ID | |
623 | * On exit, r0, r1, r2, r3, r12 corrupted | |
624 | * This routine must preserve: r4, r6, r7 | |
625 | */ | |
626 | .align 5 | |
627 | cache_off: mov r3, #12 @ cache_off function | |
628 | b call_cache_fn | |
629 | ||
10c2df65 HC |
630 | __armv4_mpu_cache_off: |
631 | mrc p15, 0, r0, c1, c0 | |
632 | bic r0, r0, #0x000d | |
633 | mcr p15, 0, r0, c1, c0 @ turn MPU and cache off | |
634 | mov r0, #0 | |
635 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer | |
636 | mcr p15, 0, r0, c7, c6, 0 @ flush D-Cache | |
637 | mcr p15, 0, r0, c7, c5, 0 @ flush I-Cache | |
638 | mov pc, lr | |
639 | ||
640 | __armv3_mpu_cache_off: | |
641 | mrc p15, 0, r0, c1, c0 | |
642 | bic r0, r0, #0x000d | |
643 | mcr p15, 0, r0, c1, c0, 0 @ turn MPU and cache off | |
644 | mov r0, #0 | |
645 | mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 | |
646 | mov pc, lr | |
647 | ||
c76b6b41 | 648 | __armv4_mmu_cache_off: |
1da177e4 LT |
649 | mrc p15, 0, r0, c1, c0 |
650 | bic r0, r0, #0x000d | |
651 | mcr p15, 0, r0, c1, c0 @ turn MMU and cache off | |
652 | mov r0, #0 | |
653 | mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4 | |
654 | mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4 | |
655 | mov pc, lr | |
656 | ||
c76b6b41 | 657 | __arm6_mmu_cache_off: |
1da177e4 | 658 | mov r0, #0x00000030 @ ARM6 control reg. |
c76b6b41 | 659 | b __armv3_mmu_cache_off |
1da177e4 | 660 | |
c76b6b41 | 661 | __arm7_mmu_cache_off: |
1da177e4 | 662 | mov r0, #0x00000070 @ ARM7 control reg. |
c76b6b41 | 663 | b __armv3_mmu_cache_off |
1da177e4 | 664 | |
c76b6b41 | 665 | __armv3_mmu_cache_off: |
1da177e4 LT |
666 | mcr p15, 0, r0, c1, c0, 0 @ turn MMU and cache off |
667 | mov r0, #0 | |
668 | mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 | |
669 | mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3 | |
670 | mov pc, lr | |
671 | ||
672 | /* | |
673 | * Clean and flush the cache to maintain consistency. | |
674 | * | |
675 | * On entry, | |
676 | * r6 = processor ID | |
677 | * On exit, | |
678 | * r1, r2, r3, r11, r12 corrupted | |
679 | * This routine must preserve: | |
680 | * r0, r4, r5, r6, r7 | |
681 | */ | |
682 | .align 5 | |
683 | cache_clean_flush: | |
684 | mov r3, #16 | |
685 | b call_cache_fn | |
686 | ||
10c2df65 HC |
687 | __armv4_mpu_cache_flush: |
688 | mov r2, #1 | |
689 | mov r3, #0 | |
690 | mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache | |
691 | mov r1, #7 << 5 @ 8 segments | |
692 | 1: orr r3, r1, #63 << 26 @ 64 entries | |
693 | 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index | |
694 | subs r3, r3, #1 << 26 | |
695 | bcs 2b @ entries 63 to 0 | |
696 | subs r1, r1, #1 << 5 | |
697 | bcs 1b @ segments 7 to 0 | |
698 | ||
699 | teq r2, #0 | |
700 | mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache | |
701 | mcr p15, 0, ip, c7, c10, 4 @ drain WB | |
702 | mov pc, lr | |
703 | ||
704 | ||
c76b6b41 | 705 | __armv6_mmu_cache_flush: |
1da177e4 LT |
706 | mov r1, #0 |
707 | mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D | |
708 | mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB | |
709 | mcr p15, 0, r1, c7, c15, 0 @ clean+invalidate unified | |
710 | mcr p15, 0, r1, c7, c10, 4 @ drain WB | |
711 | mov pc, lr | |
712 | ||
c76b6b41 | 713 | __armv4_mmu_cache_flush: |
1da177e4 LT |
714 | mov r2, #64*1024 @ default: 32K dcache size (*2) |
715 | mov r11, #32 @ default: 32 byte line size | |
716 | mrc p15, 0, r3, c0, c0, 1 @ read cache type | |
717 | teq r3, r6 @ cache ID register present? | |
718 | beq no_cache_id | |
719 | mov r1, r3, lsr #18 | |
720 | and r1, r1, #7 | |
721 | mov r2, #1024 | |
722 | mov r2, r2, lsl r1 @ base dcache size *2 | |
723 | tst r3, #1 << 14 @ test M bit | |
724 | addne r2, r2, r2, lsr #1 @ +1/2 size if M == 1 | |
725 | mov r3, r3, lsr #12 | |
726 | and r3, r3, #3 | |
727 | mov r11, #8 | |
728 | mov r11, r11, lsl r3 @ cache line size in bytes | |
729 | no_cache_id: | |
730 | bic r1, pc, #63 @ align to longest cache line | |
731 | add r2, r1, r2 | |
732 | 1: ldr r3, [r1], r11 @ s/w flush D cache | |
733 | teq r1, r2 | |
734 | bne 1b | |
735 | ||
736 | mcr p15, 0, r1, c7, c5, 0 @ flush I cache | |
737 | mcr p15, 0, r1, c7, c6, 0 @ flush D cache | |
738 | mcr p15, 0, r1, c7, c10, 4 @ drain WB | |
739 | mov pc, lr | |
740 | ||
c76b6b41 | 741 | __armv3_mmu_cache_flush: |
10c2df65 | 742 | __armv3_mpu_cache_flush: |
1da177e4 LT |
743 | mov r1, #0 |
744 | mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 | |
745 | mov pc, lr | |
746 | ||
747 | /* | |
748 | * Various debugging routines for printing hex characters and | |
749 | * memory, which again must be relocatable. | |
750 | */ | |
751 | #ifdef DEBUG | |
752 | .type phexbuf,#object | |
753 | phexbuf: .space 12 | |
754 | .size phexbuf, . - phexbuf | |
755 | ||
756 | phex: adr r3, phexbuf | |
757 | mov r2, #0 | |
758 | strb r2, [r3, r1] | |
759 | 1: subs r1, r1, #1 | |
760 | movmi r0, r3 | |
761 | bmi puts | |
762 | and r2, r0, #15 | |
763 | mov r0, r0, lsr #4 | |
764 | cmp r2, #10 | |
765 | addge r2, r2, #7 | |
766 | add r2, r2, #'0' | |
767 | strb r2, [r3, r1] | |
768 | b 1b | |
769 | ||
770 | puts: loadsp r3 | |
771 | 1: ldrb r2, [r0], #1 | |
772 | teq r2, #0 | |
773 | moveq pc, lr | |
5cd0c344 | 774 | 2: writeb r2, r3 |
1da177e4 LT |
775 | mov r1, #0x00020000 |
776 | 3: subs r1, r1, #1 | |
777 | bne 3b | |
778 | teq r2, #'\n' | |
779 | moveq r2, #'\r' | |
780 | beq 2b | |
781 | teq r0, #0 | |
782 | bne 1b | |
783 | mov pc, lr | |
784 | putc: | |
785 | mov r2, r0 | |
786 | mov r0, #0 | |
787 | loadsp r3 | |
788 | b 2b | |
789 | ||
790 | memdump: mov r12, r0 | |
791 | mov r10, lr | |
792 | mov r11, #0 | |
793 | 2: mov r0, r11, lsl #2 | |
794 | add r0, r0, r12 | |
795 | mov r1, #8 | |
796 | bl phex | |
797 | mov r0, #':' | |
798 | bl putc | |
799 | 1: mov r0, #' ' | |
800 | bl putc | |
801 | ldr r0, [r12, r11, lsl #2] | |
802 | mov r1, #8 | |
803 | bl phex | |
804 | and r0, r11, #7 | |
805 | teq r0, #3 | |
806 | moveq r0, #' ' | |
807 | bleq putc | |
808 | and r0, r11, #7 | |
809 | add r11, r11, #1 | |
810 | teq r0, #7 | |
811 | bne 1b | |
812 | mov r0, #'\n' | |
813 | bl putc | |
814 | cmp r11, #64 | |
815 | blt 2b | |
816 | mov pc, r10 | |
817 | #endif | |
818 | ||
819 | reloc_end: | |
820 | ||
821 | .align | |
822 | .section ".stack", "w" | |
823 | user_stack: .space 4096 |