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ARM: zImage: __armv3_mpu_cache_flush: respect should-be-zero specification
authorUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Tue, 26 Jan 2010 21:18:09 +0000 (22:18 +0100)
committerUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Thu, 17 Jun 2010 09:10:03 +0000 (11:10 +0200)
commit63fa71872bdec70f4a82e562fc34f8d87e174774
treecb39d230589ee6451ecb45151e5b0069e27bf02ftree | snapshot (tar.gz zip)
parent4a8d57a54fb21f32ee17e0a61ca54c7a6f8f83dacommit | diff
ARM: zImage: __armv3_mpu_cache_flush: respect should-be-zero specification

Probably the register content for cache operations is "don't care" in
practice, but as r1 is explicitly zeroed, use that one.

Acked-by: Eric Miao <eric.miao@canonical.com>
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
arch/arm/boot/compressed/head.S diff | blob | blame | history
kernel source for telekom puls (alcatel/mediatek)