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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/boot/compressed/head.S | |
3 | * | |
4 | * Copyright (C) 1996-2002 Russell King | |
10c2df65 | 5 | * Copyright (C) 2004 Hyok S. Choi (MPU support) |
1da177e4 LT |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
1da177e4 LT |
11 | #include <linux/linkage.h> |
12 | ||
13 | /* | |
14 | * Debugging stuff | |
15 | * | |
16 | * Note that these macros must not contain any code which is not | |
17 | * 100% relocatable. Any attempt to do so will result in a crash. | |
18 | * Please select one of the following when turning on debugging. | |
19 | */ | |
20 | #ifdef DEBUG | |
5cd0c344 | 21 | |
5cd0c344 | 22 | #if defined(CONFIG_DEBUG_ICEDCC) |
7d95ded9 TL |
23 | |
24 | #ifdef CONFIG_CPU_V6 | |
25 | .macro loadsp, rb | |
26 | .endm | |
27 | .macro writeb, ch, rb | |
28 | mcr p14, 0, \ch, c0, c5, 0 | |
29 | .endm | |
30 | #else | |
1da177e4 LT |
31 | .macro loadsp, rb |
32 | .endm | |
224b5be6 | 33 | .macro writeb, ch, rb |
5cd0c344 | 34 | mcr p14, 0, \ch, c0, c1, 0 |
1da177e4 | 35 | .endm |
7d95ded9 TL |
36 | #endif |
37 | ||
5cd0c344 | 38 | #else |
224b5be6 RK |
39 | |
40 | #include <asm/arch/debug-macro.S> | |
41 | ||
5cd0c344 RK |
42 | .macro writeb, ch, rb |
43 | senduart \ch, \rb | |
1da177e4 | 44 | .endm |
5cd0c344 | 45 | |
224b5be6 | 46 | #if defined(CONFIG_ARCH_SA1100) |
1da177e4 LT |
47 | .macro loadsp, rb |
48 | mov \rb, #0x80000000 @ physical base address | |
224b5be6 | 49 | #ifdef CONFIG_DEBUG_LL_SER3 |
1da177e4 | 50 | add \rb, \rb, #0x00050000 @ Ser3 |
224b5be6 | 51 | #else |
1da177e4 | 52 | add \rb, \rb, #0x00010000 @ Ser1 |
224b5be6 | 53 | #endif |
1da177e4 | 54 | .endm |
1da177e4 | 55 | #elif defined(CONFIG_ARCH_S3C2410) |
5cd0c344 | 56 | .macro loadsp, rb |
1da177e4 LT |
57 | mov \rb, #0x50000000 |
58 | add \rb, \rb, #0x4000 * CONFIG_S3C2410_LOWLEVEL_UART_PORT | |
59 | .endm | |
1da177e4 | 60 | #else |
224b5be6 RK |
61 | .macro loadsp, rb |
62 | addruart \rb | |
63 | .endm | |
1da177e4 | 64 | #endif |
5cd0c344 | 65 | #endif |
1da177e4 LT |
66 | #endif |
67 | ||
68 | .macro kputc,val | |
69 | mov r0, \val | |
70 | bl putc | |
71 | .endm | |
72 | ||
73 | .macro kphex,val,len | |
74 | mov r0, \val | |
75 | mov r1, #\len | |
76 | bl phex | |
77 | .endm | |
78 | ||
79 | .macro debug_reloc_start | |
80 | #ifdef DEBUG | |
81 | kputc #'\n' | |
82 | kphex r6, 8 /* processor id */ | |
83 | kputc #':' | |
84 | kphex r7, 8 /* architecture id */ | |
85 | kputc #':' | |
86 | mrc p15, 0, r0, c1, c0 | |
87 | kphex r0, 8 /* control reg */ | |
88 | kputc #'\n' | |
89 | kphex r5, 8 /* decompressed kernel start */ | |
90 | kputc #'-' | |
f4619025 | 91 | kphex r9, 8 /* decompressed kernel end */ |
1da177e4 LT |
92 | kputc #'>' |
93 | kphex r4, 8 /* kernel execution address */ | |
94 | kputc #'\n' | |
95 | #endif | |
96 | .endm | |
97 | ||
98 | .macro debug_reloc_end | |
99 | #ifdef DEBUG | |
100 | kphex r5, 8 /* end of kernel */ | |
101 | kputc #'\n' | |
102 | mov r0, r4 | |
103 | bl memdump /* dump 256 bytes at start of kernel */ | |
104 | #endif | |
105 | .endm | |
106 | ||
107 | .section ".start", #alloc, #execinstr | |
108 | /* | |
109 | * sort out different calling conventions | |
110 | */ | |
111 | .align | |
112 | start: | |
113 | .type start,#function | |
114 | .rept 8 | |
115 | mov r0, r0 | |
116 | .endr | |
117 | ||
118 | b 1f | |
119 | .word 0x016f2818 @ Magic numbers to help the loader | |
120 | .word start @ absolute load/run zImage address | |
121 | .word _edata @ zImage end address | |
122 | 1: mov r7, r1 @ save architecture ID | |
f4619025 | 123 | mov r8, r2 @ save atags pointer |
1da177e4 LT |
124 | |
125 | #ifndef __ARM_ARCH_2__ | |
126 | /* | |
127 | * Booting from Angel - need to enter SVC mode and disable | |
128 | * FIQs/IRQs (numeric definitions from angel arm.h source). | |
129 | * We only do this if we were in user mode on entry. | |
130 | */ | |
131 | mrs r2, cpsr @ get current mode | |
132 | tst r2, #3 @ not user? | |
133 | bne not_angel | |
134 | mov r0, #0x17 @ angel_SWIreason_EnterSVC | |
135 | swi 0x123456 @ angel_SWI_ARM | |
136 | not_angel: | |
137 | mrs r2, cpsr @ turn off interrupts to | |
138 | orr r2, r2, #0xc0 @ prevent angel from running | |
139 | msr cpsr_c, r2 | |
140 | #else | |
141 | teqp pc, #0x0c000003 @ turn off interrupts | |
142 | #endif | |
143 | ||
144 | /* | |
145 | * Note that some cache flushing and other stuff may | |
146 | * be needed here - is there an Angel SWI call for this? | |
147 | */ | |
148 | ||
149 | /* | |
150 | * some architecture specific code can be inserted | |
f4619025 | 151 | * by the linker here, but it should preserve r7, r8, and r9. |
1da177e4 LT |
152 | */ |
153 | ||
154 | .text | |
155 | adr r0, LC0 | |
156 | ldmia r0, {r1, r2, r3, r4, r5, r6, ip, sp} | |
157 | subs r0, r0, r1 @ calculate the delta offset | |
158 | ||
159 | @ if delta is zero, we are | |
160 | beq not_relocated @ running at the address we | |
161 | @ were linked at. | |
162 | ||
163 | /* | |
164 | * We're running at a different address. We need to fix | |
165 | * up various pointers: | |
166 | * r5 - zImage base address | |
167 | * r6 - GOT start | |
168 | * ip - GOT end | |
169 | */ | |
170 | add r5, r5, r0 | |
171 | add r6, r6, r0 | |
172 | add ip, ip, r0 | |
173 | ||
174 | #ifndef CONFIG_ZBOOT_ROM | |
175 | /* | |
176 | * If we're running fully PIC === CONFIG_ZBOOT_ROM = n, | |
177 | * we need to fix up pointers into the BSS region. | |
178 | * r2 - BSS start | |
179 | * r3 - BSS end | |
180 | * sp - stack pointer | |
181 | */ | |
182 | add r2, r2, r0 | |
183 | add r3, r3, r0 | |
184 | add sp, sp, r0 | |
185 | ||
186 | /* | |
187 | * Relocate all entries in the GOT table. | |
188 | */ | |
189 | 1: ldr r1, [r6, #0] @ relocate entries in the GOT | |
190 | add r1, r1, r0 @ table. This fixes up the | |
191 | str r1, [r6], #4 @ C references. | |
192 | cmp r6, ip | |
193 | blo 1b | |
194 | #else | |
195 | ||
196 | /* | |
197 | * Relocate entries in the GOT table. We only relocate | |
198 | * the entries that are outside the (relocated) BSS region. | |
199 | */ | |
200 | 1: ldr r1, [r6, #0] @ relocate entries in the GOT | |
201 | cmp r1, r2 @ entry < bss_start || | |
202 | cmphs r3, r1 @ _end < entry | |
203 | addlo r1, r1, r0 @ table. This fixes up the | |
204 | str r1, [r6], #4 @ C references. | |
205 | cmp r6, ip | |
206 | blo 1b | |
207 | #endif | |
208 | ||
209 | not_relocated: mov r0, #0 | |
210 | 1: str r0, [r2], #4 @ clear bss | |
211 | str r0, [r2], #4 | |
212 | str r0, [r2], #4 | |
213 | str r0, [r2], #4 | |
214 | cmp r2, r3 | |
215 | blo 1b | |
216 | ||
217 | /* | |
218 | * The C runtime environment should now be setup | |
219 | * sufficiently. Turn the cache on, set up some | |
220 | * pointers, and start decompressing. | |
221 | */ | |
222 | bl cache_on | |
223 | ||
224 | mov r1, sp @ malloc space above stack | |
225 | add r2, sp, #0x10000 @ 64k max | |
226 | ||
227 | /* | |
228 | * Check to see if we will overwrite ourselves. | |
229 | * r4 = final kernel address | |
230 | * r5 = start of this image | |
231 | * r2 = end of malloc space (and therefore this image) | |
232 | * We basically want: | |
233 | * r4 >= r2 -> OK | |
234 | * r4 + image length <= r5 -> OK | |
235 | */ | |
236 | cmp r4, r2 | |
237 | bhs wont_overwrite | |
238 | add r0, r4, #4096*1024 @ 4MB largest kernel size | |
239 | cmp r0, r5 | |
240 | bls wont_overwrite | |
241 | ||
242 | mov r5, r2 @ decompress after malloc space | |
243 | mov r0, r5 | |
244 | mov r3, r7 | |
245 | bl decompress_kernel | |
246 | ||
247 | add r0, r0, #127 | |
248 | bic r0, r0, #127 @ align the kernel length | |
249 | /* | |
250 | * r0 = decompressed kernel length | |
251 | * r1-r3 = unused | |
252 | * r4 = kernel execution address | |
253 | * r5 = decompressed kernel start | |
254 | * r6 = processor ID | |
255 | * r7 = architecture ID | |
f4619025 RK |
256 | * r8 = atags pointer |
257 | * r9-r14 = corrupted | |
1da177e4 LT |
258 | */ |
259 | add r1, r5, r0 @ end of decompressed kernel | |
260 | adr r2, reloc_start | |
261 | ldr r3, LC1 | |
262 | add r3, r2, r3 | |
f4619025 RK |
263 | 1: ldmia r2!, {r9 - r14} @ copy relocation code |
264 | stmia r1!, {r9 - r14} | |
265 | ldmia r2!, {r9 - r14} | |
266 | stmia r1!, {r9 - r14} | |
1da177e4 LT |
267 | cmp r2, r3 |
268 | blo 1b | |
269 | ||
270 | bl cache_clean_flush | |
271 | add pc, r5, r0 @ call relocation code | |
272 | ||
273 | /* | |
274 | * We're not in danger of overwriting ourselves. Do this the simple way. | |
275 | * | |
276 | * r4 = kernel execution address | |
277 | * r7 = architecture ID | |
278 | */ | |
279 | wont_overwrite: mov r0, r4 | |
280 | mov r3, r7 | |
281 | bl decompress_kernel | |
282 | b call_kernel | |
283 | ||
284 | .type LC0, #object | |
285 | LC0: .word LC0 @ r1 | |
286 | .word __bss_start @ r2 | |
287 | .word _end @ r3 | |
288 | .word zreladdr @ r4 | |
289 | .word _start @ r5 | |
290 | .word _got_start @ r6 | |
291 | .word _got_end @ ip | |
292 | .word user_stack+4096 @ sp | |
293 | LC1: .word reloc_end - reloc_start | |
294 | .size LC0, . - LC0 | |
295 | ||
296 | #ifdef CONFIG_ARCH_RPC | |
297 | .globl params | |
298 | params: ldr r0, =params_phys | |
299 | mov pc, lr | |
300 | .ltorg | |
301 | .align | |
302 | #endif | |
303 | ||
304 | /* | |
305 | * Turn on the cache. We need to setup some page tables so that we | |
306 | * can have both the I and D caches on. | |
307 | * | |
308 | * We place the page tables 16k down from the kernel execution address, | |
309 | * and we hope that nothing else is using it. If we're using it, we | |
310 | * will go pop! | |
311 | * | |
312 | * On entry, | |
313 | * r4 = kernel execution address | |
314 | * r6 = processor ID | |
315 | * r7 = architecture number | |
f4619025 RK |
316 | * r8 = atags pointer |
317 | * r9 = run-time address of "start" (???) | |
1da177e4 | 318 | * On exit, |
f4619025 | 319 | * r1, r2, r3, r9, r10, r12 corrupted |
1da177e4 | 320 | * This routine must preserve: |
f4619025 | 321 | * r4, r5, r6, r7, r8 |
1da177e4 LT |
322 | */ |
323 | .align 5 | |
324 | cache_on: mov r3, #8 @ cache_on function | |
325 | b call_cache_fn | |
326 | ||
10c2df65 HC |
327 | /* |
328 | * Initialize the highest priority protection region, PR7 | |
329 | * to cover all 32bit address and cacheable and bufferable. | |
330 | */ | |
331 | __armv4_mpu_cache_on: | |
332 | mov r0, #0x3f @ 4G, the whole | |
333 | mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting | |
334 | mcr p15, 0, r0, c6, c7, 1 | |
335 | ||
336 | mov r0, #0x80 @ PR7 | |
337 | mcr p15, 0, r0, c2, c0, 0 @ D-cache on | |
338 | mcr p15, 0, r0, c2, c0, 1 @ I-cache on | |
339 | mcr p15, 0, r0, c3, c0, 0 @ write-buffer on | |
340 | ||
341 | mov r0, #0xc000 | |
342 | mcr p15, 0, r0, c5, c0, 1 @ I-access permission | |
343 | mcr p15, 0, r0, c5, c0, 0 @ D-access permission | |
344 | ||
345 | mov r0, #0 | |
346 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer | |
347 | mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache | |
348 | mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache | |
349 | mrc p15, 0, r0, c1, c0, 0 @ read control reg | |
350 | @ ...I .... ..D. WC.M | |
351 | orr r0, r0, #0x002d @ .... .... ..1. 11.1 | |
352 | orr r0, r0, #0x1000 @ ...1 .... .... .... | |
353 | ||
354 | mcr p15, 0, r0, c1, c0, 0 @ write control reg | |
355 | ||
356 | mov r0, #0 | |
357 | mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache | |
358 | mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache | |
359 | mov pc, lr | |
360 | ||
361 | __armv3_mpu_cache_on: | |
362 | mov r0, #0x3f @ 4G, the whole | |
363 | mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting | |
364 | ||
365 | mov r0, #0x80 @ PR7 | |
366 | mcr p15, 0, r0, c2, c0, 0 @ cache on | |
367 | mcr p15, 0, r0, c3, c0, 0 @ write-buffer on | |
368 | ||
369 | mov r0, #0xc000 | |
370 | mcr p15, 0, r0, c5, c0, 0 @ access permission | |
371 | ||
372 | mov r0, #0 | |
373 | mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 | |
374 | mrc p15, 0, r0, c1, c0, 0 @ read control reg | |
375 | @ .... .... .... WC.M | |
376 | orr r0, r0, #0x000d @ .... .... .... 11.1 | |
377 | mov r0, #0 | |
378 | mcr p15, 0, r0, c1, c0, 0 @ write control reg | |
379 | ||
380 | mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 | |
381 | mov pc, lr | |
382 | ||
1da177e4 LT |
383 | __setup_mmu: sub r3, r4, #16384 @ Page directory size |
384 | bic r3, r3, #0xff @ Align the pointer | |
385 | bic r3, r3, #0x3f00 | |
386 | /* | |
387 | * Initialise the page tables, turning on the cacheable and bufferable | |
388 | * bits for the RAM area only. | |
389 | */ | |
390 | mov r0, r3 | |
f4619025 RK |
391 | mov r9, r0, lsr #18 |
392 | mov r9, r9, lsl #18 @ start of RAM | |
393 | add r10, r9, #0x10000000 @ a reasonable RAM size | |
1da177e4 LT |
394 | mov r1, #0x12 |
395 | orr r1, r1, #3 << 10 | |
396 | add r2, r3, #16384 | |
265d5e48 | 397 | 1: cmp r1, r9 @ if virt > start of RAM |
1da177e4 | 398 | orrhs r1, r1, #0x0c @ set cacheable, bufferable |
f4619025 | 399 | cmp r1, r10 @ if virt > end of RAM |
1da177e4 LT |
400 | bichs r1, r1, #0x0c @ clear cacheable, bufferable |
401 | str r1, [r0], #4 @ 1:1 mapping | |
402 | add r1, r1, #1048576 | |
403 | teq r0, r2 | |
404 | bne 1b | |
405 | /* | |
406 | * If ever we are running from Flash, then we surely want the cache | |
407 | * to be enabled also for our execution instance... We map 2MB of it | |
408 | * so there is no map overlap problem for up to 1 MB compressed kernel. | |
409 | * If the execution is in RAM then we would only be duplicating the above. | |
410 | */ | |
411 | mov r1, #0x1e | |
412 | orr r1, r1, #3 << 10 | |
413 | mov r2, pc, lsr #20 | |
414 | orr r1, r1, r2, lsl #20 | |
415 | add r0, r3, r2, lsl #2 | |
416 | str r1, [r0], #4 | |
417 | add r1, r1, #1048576 | |
418 | str r1, [r0] | |
419 | mov pc, lr | |
420 | ||
c76b6b41 | 421 | __armv4_mmu_cache_on: |
1da177e4 LT |
422 | mov r12, lr |
423 | bl __setup_mmu | |
424 | mov r0, #0 | |
425 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer | |
426 | mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs | |
427 | mrc p15, 0, r0, c1, c0, 0 @ read control reg | |
428 | orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement | |
429 | orr r0, r0, #0x0030 | |
c76b6b41 | 430 | bl __common_mmu_cache_on |
1da177e4 LT |
431 | mov r0, #0 |
432 | mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs | |
433 | mov pc, r12 | |
434 | ||
c76b6b41 | 435 | __arm6_mmu_cache_on: |
1da177e4 LT |
436 | mov r12, lr |
437 | bl __setup_mmu | |
438 | mov r0, #0 | |
439 | mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 | |
440 | mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3 | |
441 | mov r0, #0x30 | |
c76b6b41 | 442 | bl __common_mmu_cache_on |
1da177e4 LT |
443 | mov r0, #0 |
444 | mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3 | |
445 | mov pc, r12 | |
446 | ||
c76b6b41 | 447 | __common_mmu_cache_on: |
1da177e4 LT |
448 | #ifndef DEBUG |
449 | orr r0, r0, #0x000d @ Write buffer, mmu | |
450 | #endif | |
451 | mov r1, #-1 | |
452 | mcr p15, 0, r3, c2, c0, 0 @ load page table pointer | |
453 | mcr p15, 0, r1, c3, c0, 0 @ load domain access control | |
2dc7667b NP |
454 | b 1f |
455 | .align 5 @ cache line aligned | |
456 | 1: mcr p15, 0, r0, c1, c0, 0 @ load control register | |
457 | mrc p15, 0, r0, c1, c0, 0 @ and read it back to | |
458 | sub pc, lr, r0, lsr #32 @ properly flush pipeline | |
1da177e4 LT |
459 | |
460 | /* | |
461 | * All code following this line is relocatable. It is relocated by | |
462 | * the above code to the end of the decompressed kernel image and | |
463 | * executed there. During this time, we have no stacks. | |
464 | * | |
465 | * r0 = decompressed kernel length | |
466 | * r1-r3 = unused | |
467 | * r4 = kernel execution address | |
468 | * r5 = decompressed kernel start | |
469 | * r6 = processor ID | |
470 | * r7 = architecture ID | |
f4619025 RK |
471 | * r8 = atags pointer |
472 | * r9-r14 = corrupted | |
1da177e4 LT |
473 | */ |
474 | .align 5 | |
f4619025 | 475 | reloc_start: add r9, r5, r0 |
1da177e4 LT |
476 | debug_reloc_start |
477 | mov r1, r4 | |
478 | 1: | |
479 | .rept 4 | |
f4619025 RK |
480 | ldmia r5!, {r0, r2, r3, r10 - r14} @ relocate kernel |
481 | stmia r1!, {r0, r2, r3, r10 - r14} | |
1da177e4 LT |
482 | .endr |
483 | ||
f4619025 | 484 | cmp r5, r9 |
1da177e4 LT |
485 | blo 1b |
486 | debug_reloc_end | |
487 | ||
488 | call_kernel: bl cache_clean_flush | |
489 | bl cache_off | |
f4619025 | 490 | mov r0, #0 @ must be zero |
1da177e4 | 491 | mov r1, r7 @ restore architecture number |
f4619025 | 492 | mov r2, r8 @ restore atags pointer |
1da177e4 LT |
493 | mov pc, r4 @ call kernel |
494 | ||
495 | /* | |
496 | * Here follow the relocatable cache support functions for the | |
497 | * various processors. This is a generic hook for locating an | |
498 | * entry and jumping to an instruction at the specified offset | |
499 | * from the start of the block. Please note this is all position | |
500 | * independent code. | |
501 | * | |
502 | * r1 = corrupted | |
503 | * r2 = corrupted | |
504 | * r3 = block offset | |
505 | * r6 = corrupted | |
506 | * r12 = corrupted | |
507 | */ | |
508 | ||
509 | call_cache_fn: adr r12, proc_types | |
510 | mrc p15, 0, r6, c0, c0 @ get processor ID | |
511 | 1: ldr r1, [r12, #0] @ get value | |
512 | ldr r2, [r12, #4] @ get mask | |
513 | eor r1, r1, r6 @ (real ^ match) | |
514 | tst r1, r2 @ & mask | |
515 | addeq pc, r12, r3 @ call cache function | |
516 | add r12, r12, #4*5 | |
517 | b 1b | |
518 | ||
519 | /* | |
520 | * Table for cache operations. This is basically: | |
521 | * - CPU ID match | |
522 | * - CPU ID mask | |
523 | * - 'cache on' method instruction | |
524 | * - 'cache off' method instruction | |
525 | * - 'cache flush' method instruction | |
526 | * | |
527 | * We match an entry using: ((real_id ^ match) & mask) == 0 | |
528 | * | |
529 | * Writethrough caches generally only need 'on' and 'off' | |
530 | * methods. Writeback caches _must_ have the flush method | |
531 | * defined. | |
532 | */ | |
533 | .type proc_types,#object | |
534 | proc_types: | |
535 | .word 0x41560600 @ ARM6/610 | |
536 | .word 0xffffffe0 | |
c76b6b41 HC |
537 | b __arm6_mmu_cache_off @ works, but slow |
538 | b __arm6_mmu_cache_off | |
1da177e4 | 539 | mov pc, lr |
c76b6b41 HC |
540 | @ b __arm6_mmu_cache_on @ untested |
541 | @ b __arm6_mmu_cache_off | |
542 | @ b __armv3_mmu_cache_flush | |
1da177e4 LT |
543 | |
544 | .word 0x00000000 @ old ARM ID | |
545 | .word 0x0000f000 | |
546 | mov pc, lr | |
547 | mov pc, lr | |
548 | mov pc, lr | |
549 | ||
550 | .word 0x41007000 @ ARM7/710 | |
551 | .word 0xfff8fe00 | |
c76b6b41 HC |
552 | b __arm7_mmu_cache_off |
553 | b __arm7_mmu_cache_off | |
1da177e4 LT |
554 | mov pc, lr |
555 | ||
556 | .word 0x41807200 @ ARM720T (writethrough) | |
557 | .word 0xffffff00 | |
c76b6b41 HC |
558 | b __armv4_mmu_cache_on |
559 | b __armv4_mmu_cache_off | |
1da177e4 LT |
560 | mov pc, lr |
561 | ||
10c2df65 HC |
562 | .word 0x41007400 @ ARM74x |
563 | .word 0xff00ff00 | |
564 | b __armv3_mpu_cache_on | |
565 | b __armv3_mpu_cache_off | |
566 | b __armv3_mpu_cache_flush | |
567 | ||
568 | .word 0x41009400 @ ARM94x | |
569 | .word 0xff00ff00 | |
570 | b __armv4_mpu_cache_on | |
571 | b __armv4_mpu_cache_off | |
572 | b __armv4_mpu_cache_flush | |
573 | ||
1da177e4 LT |
574 | .word 0x00007000 @ ARM7 IDs |
575 | .word 0x0000f000 | |
576 | mov pc, lr | |
577 | mov pc, lr | |
578 | mov pc, lr | |
579 | ||
580 | @ Everything from here on will be the new ID system. | |
581 | ||
582 | .word 0x4401a100 @ sa110 / sa1100 | |
583 | .word 0xffffffe0 | |
c76b6b41 HC |
584 | b __armv4_mmu_cache_on |
585 | b __armv4_mmu_cache_off | |
586 | b __armv4_mmu_cache_flush | |
1da177e4 LT |
587 | |
588 | .word 0x6901b110 @ sa1110 | |
589 | .word 0xfffffff0 | |
c76b6b41 HC |
590 | b __armv4_mmu_cache_on |
591 | b __armv4_mmu_cache_off | |
592 | b __armv4_mmu_cache_flush | |
1da177e4 LT |
593 | |
594 | @ These match on the architecture ID | |
595 | ||
596 | .word 0x00020000 @ ARMv4T | |
597 | .word 0x000f0000 | |
c76b6b41 HC |
598 | b __armv4_mmu_cache_on |
599 | b __armv4_mmu_cache_off | |
600 | b __armv4_mmu_cache_flush | |
1da177e4 LT |
601 | |
602 | .word 0x00050000 @ ARMv5TE | |
603 | .word 0x000f0000 | |
c76b6b41 HC |
604 | b __armv4_mmu_cache_on |
605 | b __armv4_mmu_cache_off | |
606 | b __armv4_mmu_cache_flush | |
1da177e4 LT |
607 | |
608 | .word 0x00060000 @ ARMv5TEJ | |
609 | .word 0x000f0000 | |
c76b6b41 HC |
610 | b __armv4_mmu_cache_on |
611 | b __armv4_mmu_cache_off | |
612 | b __armv4_mmu_cache_flush | |
1da177e4 | 613 | |
45a7b9cf CM |
614 | .word 0x0007b000 @ ARMv6 |
615 | .word 0x0007f000 | |
c76b6b41 HC |
616 | b __armv4_mmu_cache_on |
617 | b __armv4_mmu_cache_off | |
618 | b __armv6_mmu_cache_flush | |
1da177e4 LT |
619 | |
620 | .word 0 @ unrecognised type | |
621 | .word 0 | |
622 | mov pc, lr | |
623 | mov pc, lr | |
624 | mov pc, lr | |
625 | ||
626 | .size proc_types, . - proc_types | |
627 | ||
628 | /* | |
629 | * Turn off the Cache and MMU. ARMv3 does not support | |
630 | * reading the control register, but ARMv4 does. | |
631 | * | |
632 | * On entry, r6 = processor ID | |
633 | * On exit, r0, r1, r2, r3, r12 corrupted | |
634 | * This routine must preserve: r4, r6, r7 | |
635 | */ | |
636 | .align 5 | |
637 | cache_off: mov r3, #12 @ cache_off function | |
638 | b call_cache_fn | |
639 | ||
10c2df65 HC |
640 | __armv4_mpu_cache_off: |
641 | mrc p15, 0, r0, c1, c0 | |
642 | bic r0, r0, #0x000d | |
643 | mcr p15, 0, r0, c1, c0 @ turn MPU and cache off | |
644 | mov r0, #0 | |
645 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer | |
646 | mcr p15, 0, r0, c7, c6, 0 @ flush D-Cache | |
647 | mcr p15, 0, r0, c7, c5, 0 @ flush I-Cache | |
648 | mov pc, lr | |
649 | ||
650 | __armv3_mpu_cache_off: | |
651 | mrc p15, 0, r0, c1, c0 | |
652 | bic r0, r0, #0x000d | |
653 | mcr p15, 0, r0, c1, c0, 0 @ turn MPU and cache off | |
654 | mov r0, #0 | |
655 | mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 | |
656 | mov pc, lr | |
657 | ||
c76b6b41 | 658 | __armv4_mmu_cache_off: |
1da177e4 LT |
659 | mrc p15, 0, r0, c1, c0 |
660 | bic r0, r0, #0x000d | |
661 | mcr p15, 0, r0, c1, c0 @ turn MMU and cache off | |
662 | mov r0, #0 | |
663 | mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4 | |
664 | mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4 | |
665 | mov pc, lr | |
666 | ||
c76b6b41 | 667 | __arm6_mmu_cache_off: |
1da177e4 | 668 | mov r0, #0x00000030 @ ARM6 control reg. |
c76b6b41 | 669 | b __armv3_mmu_cache_off |
1da177e4 | 670 | |
c76b6b41 | 671 | __arm7_mmu_cache_off: |
1da177e4 | 672 | mov r0, #0x00000070 @ ARM7 control reg. |
c76b6b41 | 673 | b __armv3_mmu_cache_off |
1da177e4 | 674 | |
c76b6b41 | 675 | __armv3_mmu_cache_off: |
1da177e4 LT |
676 | mcr p15, 0, r0, c1, c0, 0 @ turn MMU and cache off |
677 | mov r0, #0 | |
678 | mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 | |
679 | mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3 | |
680 | mov pc, lr | |
681 | ||
682 | /* | |
683 | * Clean and flush the cache to maintain consistency. | |
684 | * | |
685 | * On entry, | |
686 | * r6 = processor ID | |
687 | * On exit, | |
688 | * r1, r2, r3, r11, r12 corrupted | |
689 | * This routine must preserve: | |
690 | * r0, r4, r5, r6, r7 | |
691 | */ | |
692 | .align 5 | |
693 | cache_clean_flush: | |
694 | mov r3, #16 | |
695 | b call_cache_fn | |
696 | ||
10c2df65 HC |
697 | __armv4_mpu_cache_flush: |
698 | mov r2, #1 | |
699 | mov r3, #0 | |
700 | mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache | |
701 | mov r1, #7 << 5 @ 8 segments | |
702 | 1: orr r3, r1, #63 << 26 @ 64 entries | |
703 | 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index | |
704 | subs r3, r3, #1 << 26 | |
705 | bcs 2b @ entries 63 to 0 | |
706 | subs r1, r1, #1 << 5 | |
707 | bcs 1b @ segments 7 to 0 | |
708 | ||
709 | teq r2, #0 | |
710 | mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache | |
711 | mcr p15, 0, ip, c7, c10, 4 @ drain WB | |
712 | mov pc, lr | |
713 | ||
714 | ||
c76b6b41 | 715 | __armv6_mmu_cache_flush: |
1da177e4 LT |
716 | mov r1, #0 |
717 | mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D | |
718 | mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB | |
719 | mcr p15, 0, r1, c7, c15, 0 @ clean+invalidate unified | |
720 | mcr p15, 0, r1, c7, c10, 4 @ drain WB | |
721 | mov pc, lr | |
722 | ||
c76b6b41 | 723 | __armv4_mmu_cache_flush: |
1da177e4 LT |
724 | mov r2, #64*1024 @ default: 32K dcache size (*2) |
725 | mov r11, #32 @ default: 32 byte line size | |
726 | mrc p15, 0, r3, c0, c0, 1 @ read cache type | |
727 | teq r3, r6 @ cache ID register present? | |
728 | beq no_cache_id | |
729 | mov r1, r3, lsr #18 | |
730 | and r1, r1, #7 | |
731 | mov r2, #1024 | |
732 | mov r2, r2, lsl r1 @ base dcache size *2 | |
733 | tst r3, #1 << 14 @ test M bit | |
734 | addne r2, r2, r2, lsr #1 @ +1/2 size if M == 1 | |
735 | mov r3, r3, lsr #12 | |
736 | and r3, r3, #3 | |
737 | mov r11, #8 | |
738 | mov r11, r11, lsl r3 @ cache line size in bytes | |
739 | no_cache_id: | |
740 | bic r1, pc, #63 @ align to longest cache line | |
741 | add r2, r1, r2 | |
742 | 1: ldr r3, [r1], r11 @ s/w flush D cache | |
743 | teq r1, r2 | |
744 | bne 1b | |
745 | ||
746 | mcr p15, 0, r1, c7, c5, 0 @ flush I cache | |
747 | mcr p15, 0, r1, c7, c6, 0 @ flush D cache | |
748 | mcr p15, 0, r1, c7, c10, 4 @ drain WB | |
749 | mov pc, lr | |
750 | ||
c76b6b41 | 751 | __armv3_mmu_cache_flush: |
10c2df65 | 752 | __armv3_mpu_cache_flush: |
1da177e4 LT |
753 | mov r1, #0 |
754 | mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 | |
755 | mov pc, lr | |
756 | ||
757 | /* | |
758 | * Various debugging routines for printing hex characters and | |
759 | * memory, which again must be relocatable. | |
760 | */ | |
761 | #ifdef DEBUG | |
762 | .type phexbuf,#object | |
763 | phexbuf: .space 12 | |
764 | .size phexbuf, . - phexbuf | |
765 | ||
766 | phex: adr r3, phexbuf | |
767 | mov r2, #0 | |
768 | strb r2, [r3, r1] | |
769 | 1: subs r1, r1, #1 | |
770 | movmi r0, r3 | |
771 | bmi puts | |
772 | and r2, r0, #15 | |
773 | mov r0, r0, lsr #4 | |
774 | cmp r2, #10 | |
775 | addge r2, r2, #7 | |
776 | add r2, r2, #'0' | |
777 | strb r2, [r3, r1] | |
778 | b 1b | |
779 | ||
780 | puts: loadsp r3 | |
781 | 1: ldrb r2, [r0], #1 | |
782 | teq r2, #0 | |
783 | moveq pc, lr | |
5cd0c344 | 784 | 2: writeb r2, r3 |
1da177e4 LT |
785 | mov r1, #0x00020000 |
786 | 3: subs r1, r1, #1 | |
787 | bne 3b | |
788 | teq r2, #'\n' | |
789 | moveq r2, #'\r' | |
790 | beq 2b | |
791 | teq r0, #0 | |
792 | bne 1b | |
793 | mov pc, lr | |
794 | putc: | |
795 | mov r2, r0 | |
796 | mov r0, #0 | |
797 | loadsp r3 | |
798 | b 2b | |
799 | ||
800 | memdump: mov r12, r0 | |
801 | mov r10, lr | |
802 | mov r11, #0 | |
803 | 2: mov r0, r11, lsl #2 | |
804 | add r0, r0, r12 | |
805 | mov r1, #8 | |
806 | bl phex | |
807 | mov r0, #':' | |
808 | bl putc | |
809 | 1: mov r0, #' ' | |
810 | bl putc | |
811 | ldr r0, [r12, r11, lsl #2] | |
812 | mov r1, #8 | |
813 | bl phex | |
814 | and r0, r11, #7 | |
815 | teq r0, #3 | |
816 | moveq r0, #' ' | |
817 | bleq putc | |
818 | and r0, r11, #7 | |
819 | add r11, r11, #1 | |
820 | teq r0, #7 | |
821 | bne 1b | |
822 | mov r0, #'\n' | |
823 | bl putc | |
824 | cmp r11, #64 | |
825 | blt 2b | |
826 | mov pc, r10 | |
827 | #endif | |
828 | ||
829 | reloc_end: | |
830 | ||
831 | .align | |
832 | .section ".stack", "w" | |
833 | user_stack: .space 4096 |