genirq: Add irq disabled flag to irq_data state
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / kernel / irq / chip.c
CommitLineData
dd87eb3a
TG
1/*
2 * linux/kernel/irq/chip.c
3 *
4 * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar
5 * Copyright (C) 2005-2006, Thomas Gleixner, Russell King
6 *
7 * This file contains the core interrupt handling code, for irq-chip
8 * based architectures.
9 *
10 * Detailed information is available in Documentation/DocBook/genericirq
11 */
12
13#include <linux/irq.h>
7fe3730d 14#include <linux/msi.h>
dd87eb3a
TG
15#include <linux/module.h>
16#include <linux/interrupt.h>
17#include <linux/kernel_stat.h>
18
19#include "internals.h"
20
21/**
a0cd9ca2 22 * irq_set_chip - set the irq chip for an irq
dd87eb3a
TG
23 * @irq: irq number
24 * @chip: pointer to irq chip description structure
25 */
a0cd9ca2 26int irq_set_chip(unsigned int irq, struct irq_chip *chip)
dd87eb3a 27{
dd87eb3a 28 unsigned long flags;
02725e74 29 struct irq_desc *desc = irq_get_desc_lock(irq, &flags);
dd87eb3a 30
02725e74 31 if (!desc)
dd87eb3a 32 return -EINVAL;
dd87eb3a
TG
33
34 if (!chip)
35 chip = &no_irq_chip;
36
dd87eb3a 37 irq_chip_set_defaults(chip);
6b8ff312 38 desc->irq_data.chip = chip;
02725e74 39 irq_put_desc_unlock(desc, flags);
d72274e5
DD
40 /*
41 * For !CONFIG_SPARSE_IRQ make the irq show up in
42 * allocated_irqs. For the CONFIG_SPARSE_IRQ case, it is
43 * already marked, and this call is harmless.
44 */
45 irq_reserve_irq(irq);
dd87eb3a
TG
46 return 0;
47}
a0cd9ca2 48EXPORT_SYMBOL(irq_set_chip);
dd87eb3a
TG
49
50/**
a0cd9ca2 51 * irq_set_type - set the irq trigger type for an irq
dd87eb3a 52 * @irq: irq number
0c5d1eb7 53 * @type: IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h
dd87eb3a 54 */
a0cd9ca2 55int irq_set_irq_type(unsigned int irq, unsigned int type)
dd87eb3a 56{
dd87eb3a 57 unsigned long flags;
02725e74
TG
58 struct irq_desc *desc = irq_get_desc_buslock(irq, &flags);
59 int ret = 0;
dd87eb3a 60
02725e74
TG
61 if (!desc)
62 return -EINVAL;
dd87eb3a 63
f2b662da 64 type &= IRQ_TYPE_SENSE_MASK;
02725e74
TG
65 if (type != IRQ_TYPE_NONE)
66 ret = __irq_set_trigger(desc, irq, type);
67 irq_put_desc_busunlock(desc, flags);
dd87eb3a
TG
68 return ret;
69}
a0cd9ca2 70EXPORT_SYMBOL(irq_set_irq_type);
dd87eb3a
TG
71
72/**
a0cd9ca2 73 * irq_set_handler_data - set irq handler data for an irq
dd87eb3a
TG
74 * @irq: Interrupt number
75 * @data: Pointer to interrupt specific data
76 *
77 * Set the hardware irq controller data for an irq
78 */
a0cd9ca2 79int irq_set_handler_data(unsigned int irq, void *data)
dd87eb3a 80{
dd87eb3a 81 unsigned long flags;
02725e74 82 struct irq_desc *desc = irq_get_desc_lock(irq, &flags);
dd87eb3a 83
02725e74 84 if (!desc)
dd87eb3a 85 return -EINVAL;
6b8ff312 86 desc->irq_data.handler_data = data;
02725e74 87 irq_put_desc_unlock(desc, flags);
dd87eb3a
TG
88 return 0;
89}
a0cd9ca2 90EXPORT_SYMBOL(irq_set_handler_data);
dd87eb3a 91
5b912c10 92/**
a0cd9ca2 93 * irq_set_msi_desc - set MSI descriptor data for an irq
5b912c10 94 * @irq: Interrupt number
472900b8 95 * @entry: Pointer to MSI descriptor data
5b912c10 96 *
24b26d42 97 * Set the MSI descriptor entry for an irq
5b912c10 98 */
a0cd9ca2 99int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry)
5b912c10 100{
5b912c10 101 unsigned long flags;
02725e74 102 struct irq_desc *desc = irq_get_desc_lock(irq, &flags);
5b912c10 103
02725e74 104 if (!desc)
5b912c10 105 return -EINVAL;
6b8ff312 106 desc->irq_data.msi_desc = entry;
7fe3730d
ME
107 if (entry)
108 entry->irq = irq;
02725e74 109 irq_put_desc_unlock(desc, flags);
5b912c10
EB
110 return 0;
111}
112
dd87eb3a 113/**
a0cd9ca2 114 * irq_set_chip_data - set irq chip data for an irq
dd87eb3a
TG
115 * @irq: Interrupt number
116 * @data: Pointer to chip specific data
117 *
118 * Set the hardware irq chip data for an irq
119 */
a0cd9ca2 120int irq_set_chip_data(unsigned int irq, void *data)
dd87eb3a 121{
dd87eb3a 122 unsigned long flags;
02725e74 123 struct irq_desc *desc = irq_get_desc_lock(irq, &flags);
dd87eb3a 124
02725e74 125 if (!desc)
dd87eb3a 126 return -EINVAL;
6b8ff312 127 desc->irq_data.chip_data = data;
02725e74 128 irq_put_desc_unlock(desc, flags);
dd87eb3a
TG
129 return 0;
130}
a0cd9ca2 131EXPORT_SYMBOL(irq_set_chip_data);
dd87eb3a 132
f303a6dd
TG
133struct irq_data *irq_get_irq_data(unsigned int irq)
134{
135 struct irq_desc *desc = irq_to_desc(irq);
136
137 return desc ? &desc->irq_data : NULL;
138}
139EXPORT_SYMBOL_GPL(irq_get_irq_data);
140
c1594b77
TG
141static void irq_state_clr_disabled(struct irq_desc *desc)
142{
143 desc->istate &= ~IRQS_DISABLED;
801a0e9a 144 irqd_clear(&desc->irq_data, IRQD_IRQ_DISABLED);
c1594b77
TG
145 irq_compat_clr_disabled(desc);
146}
147
148static void irq_state_set_disabled(struct irq_desc *desc)
149{
150 desc->istate |= IRQS_DISABLED;
801a0e9a 151 irqd_set(&desc->irq_data, IRQD_IRQ_DISABLED);
c1594b77
TG
152 irq_compat_set_disabled(desc);
153}
154
6e40262e
TG
155static void irq_state_clr_masked(struct irq_desc *desc)
156{
157 desc->istate &= ~IRQS_MASKED;
158 irq_compat_clr_masked(desc);
159}
160
161static void irq_state_set_masked(struct irq_desc *desc)
162{
163 desc->istate |= IRQS_MASKED;
164 irq_compat_set_masked(desc);
165}
166
46999238
TG
167int irq_startup(struct irq_desc *desc)
168{
c1594b77 169 irq_state_clr_disabled(desc);
46999238
TG
170 desc->depth = 0;
171
3aae994f
TG
172 if (desc->irq_data.chip->irq_startup) {
173 int ret = desc->irq_data.chip->irq_startup(&desc->irq_data);
6e40262e 174 irq_state_clr_masked(desc);
3aae994f
TG
175 return ret;
176 }
46999238 177
87923470 178 irq_enable(desc);
46999238
TG
179 return 0;
180}
181
182void irq_shutdown(struct irq_desc *desc)
183{
c1594b77 184 irq_state_set_disabled(desc);
46999238 185 desc->depth = 1;
50f7c032
TG
186 if (desc->irq_data.chip->irq_shutdown)
187 desc->irq_data.chip->irq_shutdown(&desc->irq_data);
188 if (desc->irq_data.chip->irq_disable)
189 desc->irq_data.chip->irq_disable(&desc->irq_data);
190 else
191 desc->irq_data.chip->irq_mask(&desc->irq_data);
6e40262e 192 irq_state_set_masked(desc);
46999238
TG
193}
194
87923470
TG
195void irq_enable(struct irq_desc *desc)
196{
c1594b77 197 irq_state_clr_disabled(desc);
50f7c032
TG
198 if (desc->irq_data.chip->irq_enable)
199 desc->irq_data.chip->irq_enable(&desc->irq_data);
200 else
201 desc->irq_data.chip->irq_unmask(&desc->irq_data);
6e40262e 202 irq_state_clr_masked(desc);
dd87eb3a
TG
203}
204
50f7c032 205void irq_disable(struct irq_desc *desc)
89d694b9 206{
c1594b77 207 irq_state_set_disabled(desc);
50f7c032
TG
208 if (desc->irq_data.chip->irq_disable) {
209 desc->irq_data.chip->irq_disable(&desc->irq_data);
a61d8258 210 irq_state_set_masked(desc);
50f7c032 211 }
89d694b9
TG
212}
213
bd151412 214#ifndef CONFIG_GENERIC_HARDIRQS_NO_DEPRECATED
3876ec9e 215/* Temporary migration helpers */
e2c0f8ff
TG
216static void compat_irq_mask(struct irq_data *data)
217{
218 data->chip->mask(data->irq);
219}
220
0eda58b7
TG
221static void compat_irq_unmask(struct irq_data *data)
222{
223 data->chip->unmask(data->irq);
224}
225
22a49163
TG
226static void compat_irq_ack(struct irq_data *data)
227{
228 data->chip->ack(data->irq);
229}
230
9205e31d
TG
231static void compat_irq_mask_ack(struct irq_data *data)
232{
233 data->chip->mask_ack(data->irq);
234}
235
0c5c1557
TG
236static void compat_irq_eoi(struct irq_data *data)
237{
238 data->chip->eoi(data->irq);
239}
240
c5f75634
TG
241static void compat_irq_enable(struct irq_data *data)
242{
243 data->chip->enable(data->irq);
244}
245
bc310dda
TG
246static void compat_irq_disable(struct irq_data *data)
247{
248 data->chip->disable(data->irq);
249}
250
251static void compat_irq_shutdown(struct irq_data *data)
252{
253 data->chip->shutdown(data->irq);
254}
255
37e12df7
TG
256static unsigned int compat_irq_startup(struct irq_data *data)
257{
258 return data->chip->startup(data->irq);
259}
260
c96b3b3c
TG
261static int compat_irq_set_affinity(struct irq_data *data,
262 const struct cpumask *dest, bool force)
263{
264 return data->chip->set_affinity(data->irq, dest);
265}
266
b2ba2c30
TG
267static int compat_irq_set_type(struct irq_data *data, unsigned int type)
268{
269 return data->chip->set_type(data->irq, type);
270}
271
2f7e99bb
TG
272static int compat_irq_set_wake(struct irq_data *data, unsigned int on)
273{
274 return data->chip->set_wake(data->irq, on);
275}
276
21e2b8c6
TG
277static int compat_irq_retrigger(struct irq_data *data)
278{
279 return data->chip->retrigger(data->irq);
280}
281
3876ec9e
TG
282static void compat_bus_lock(struct irq_data *data)
283{
284 data->chip->bus_lock(data->irq);
285}
286
287static void compat_bus_sync_unlock(struct irq_data *data)
288{
289 data->chip->bus_sync_unlock(data->irq);
290}
bd151412 291#endif
3876ec9e 292
dd87eb3a
TG
293/*
294 * Fixup enable/disable function pointers
295 */
296void irq_chip_set_defaults(struct irq_chip *chip)
297{
bd151412 298#ifndef CONFIG_GENERIC_HARDIRQS_NO_DEPRECATED
c5f75634
TG
299 if (chip->enable)
300 chip->irq_enable = compat_irq_enable;
bc310dda
TG
301 if (chip->disable)
302 chip->irq_disable = compat_irq_disable;
303 if (chip->shutdown)
304 chip->irq_shutdown = compat_irq_shutdown;
37e12df7
TG
305 if (chip->startup)
306 chip->irq_startup = compat_irq_startup;
b86432b4
ZY
307 if (!chip->end)
308 chip->end = dummy_irq_chip.end;
3876ec9e
TG
309 if (chip->bus_lock)
310 chip->irq_bus_lock = compat_bus_lock;
311 if (chip->bus_sync_unlock)
312 chip->irq_bus_sync_unlock = compat_bus_sync_unlock;
e2c0f8ff
TG
313 if (chip->mask)
314 chip->irq_mask = compat_irq_mask;
0eda58b7
TG
315 if (chip->unmask)
316 chip->irq_unmask = compat_irq_unmask;
22a49163
TG
317 if (chip->ack)
318 chip->irq_ack = compat_irq_ack;
9205e31d
TG
319 if (chip->mask_ack)
320 chip->irq_mask_ack = compat_irq_mask_ack;
0c5c1557
TG
321 if (chip->eoi)
322 chip->irq_eoi = compat_irq_eoi;
c96b3b3c
TG
323 if (chip->set_affinity)
324 chip->irq_set_affinity = compat_irq_set_affinity;
b2ba2c30
TG
325 if (chip->set_type)
326 chip->irq_set_type = compat_irq_set_type;
2f7e99bb
TG
327 if (chip->set_wake)
328 chip->irq_set_wake = compat_irq_set_wake;
21e2b8c6
TG
329 if (chip->retrigger)
330 chip->irq_retrigger = compat_irq_retrigger;
bd151412 331#endif
dd87eb3a
TG
332}
333
9205e31d 334static inline void mask_ack_irq(struct irq_desc *desc)
dd87eb3a 335{
9205e31d
TG
336 if (desc->irq_data.chip->irq_mask_ack)
337 desc->irq_data.chip->irq_mask_ack(&desc->irq_data);
dd87eb3a 338 else {
e2c0f8ff 339 desc->irq_data.chip->irq_mask(&desc->irq_data);
22a49163
TG
340 if (desc->irq_data.chip->irq_ack)
341 desc->irq_data.chip->irq_ack(&desc->irq_data);
dd87eb3a 342 }
6e40262e 343 irq_state_set_masked(desc);
0b1adaa0
TG
344}
345
d4d5e089 346void mask_irq(struct irq_desc *desc)
0b1adaa0 347{
e2c0f8ff
TG
348 if (desc->irq_data.chip->irq_mask) {
349 desc->irq_data.chip->irq_mask(&desc->irq_data);
6e40262e 350 irq_state_set_masked(desc);
0b1adaa0
TG
351 }
352}
353
d4d5e089 354void unmask_irq(struct irq_desc *desc)
0b1adaa0 355{
0eda58b7
TG
356 if (desc->irq_data.chip->irq_unmask) {
357 desc->irq_data.chip->irq_unmask(&desc->irq_data);
6e40262e 358 irq_state_clr_masked(desc);
0b1adaa0 359 }
dd87eb3a
TG
360}
361
399b5da2
TG
362/*
363 * handle_nested_irq - Handle a nested irq from a irq thread
364 * @irq: the interrupt number
365 *
366 * Handle interrupts which are nested into a threaded interrupt
367 * handler. The handler function is called inside the calling
368 * threads context.
369 */
370void handle_nested_irq(unsigned int irq)
371{
372 struct irq_desc *desc = irq_to_desc(irq);
373 struct irqaction *action;
374 irqreturn_t action_ret;
375
376 might_sleep();
377
239007b8 378 raw_spin_lock_irq(&desc->lock);
399b5da2
TG
379
380 kstat_incr_irqs_this_cpu(irq, desc);
381
382 action = desc->action;
c1594b77 383 if (unlikely(!action || (desc->istate & IRQS_DISABLED)))
399b5da2
TG
384 goto out_unlock;
385
009b4c3b
TG
386 irq_compat_set_progress(desc);
387 desc->istate |= IRQS_INPROGRESS;
239007b8 388 raw_spin_unlock_irq(&desc->lock);
399b5da2
TG
389
390 action_ret = action->thread_fn(action->irq, action->dev_id);
391 if (!noirqdebug)
392 note_interrupt(irq, desc, action_ret);
393
239007b8 394 raw_spin_lock_irq(&desc->lock);
009b4c3b
TG
395 desc->istate &= ~IRQS_INPROGRESS;
396 irq_compat_clr_progress(desc);
399b5da2
TG
397
398out_unlock:
239007b8 399 raw_spin_unlock_irq(&desc->lock);
399b5da2
TG
400}
401EXPORT_SYMBOL_GPL(handle_nested_irq);
402
fe200ae4
TG
403static bool irq_check_poll(struct irq_desc *desc)
404{
6954b75b 405 if (!(desc->istate & IRQS_POLL_INPROGRESS))
fe200ae4
TG
406 return false;
407 return irq_wait_for_poll(desc);
408}
409
dd87eb3a
TG
410/**
411 * handle_simple_irq - Simple and software-decoded IRQs.
412 * @irq: the interrupt number
413 * @desc: the interrupt description structure for this irq
dd87eb3a
TG
414 *
415 * Simple interrupts are either sent from a demultiplexing interrupt
416 * handler or come from hardware, where no interrupt hardware control
417 * is necessary.
418 *
419 * Note: The caller is expected to handle the ack, clear, mask and
420 * unmask issues if necessary.
421 */
7ad5b3a5 422void
7d12e780 423handle_simple_irq(unsigned int irq, struct irq_desc *desc)
dd87eb3a 424{
239007b8 425 raw_spin_lock(&desc->lock);
dd87eb3a 426
009b4c3b 427 if (unlikely(desc->istate & IRQS_INPROGRESS))
fe200ae4
TG
428 if (!irq_check_poll(desc))
429 goto out_unlock;
430
163ef309 431 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
d6c88a50 432 kstat_incr_irqs_this_cpu(irq, desc);
dd87eb3a 433
c1594b77 434 if (unlikely(!desc->action || (desc->istate & IRQS_DISABLED)))
dd87eb3a
TG
435 goto out_unlock;
436
107781e7 437 handle_irq_event(desc);
dd87eb3a 438
dd87eb3a 439out_unlock:
239007b8 440 raw_spin_unlock(&desc->lock);
dd87eb3a
TG
441}
442
443/**
444 * handle_level_irq - Level type irq handler
445 * @irq: the interrupt number
446 * @desc: the interrupt description structure for this irq
dd87eb3a
TG
447 *
448 * Level type interrupts are active as long as the hardware line has
449 * the active level. This may require to mask the interrupt and unmask
450 * it after the associated handler has acknowledged the device, so the
451 * interrupt line is back to inactive.
452 */
7ad5b3a5 453void
7d12e780 454handle_level_irq(unsigned int irq, struct irq_desc *desc)
dd87eb3a 455{
239007b8 456 raw_spin_lock(&desc->lock);
9205e31d 457 mask_ack_irq(desc);
dd87eb3a 458
009b4c3b 459 if (unlikely(desc->istate & IRQS_INPROGRESS))
fe200ae4
TG
460 if (!irq_check_poll(desc))
461 goto out_unlock;
462
163ef309 463 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
d6c88a50 464 kstat_incr_irqs_this_cpu(irq, desc);
dd87eb3a
TG
465
466 /*
467 * If its disabled or no action available
468 * keep it masked and get out of here
469 */
c1594b77 470 if (unlikely(!desc->action || (desc->istate & IRQS_DISABLED)))
86998aa6 471 goto out_unlock;
dd87eb3a 472
1529866c 473 handle_irq_event(desc);
b25c340c 474
c1594b77 475 if (!(desc->istate & (IRQS_DISABLED | IRQS_ONESHOT)))
0eda58b7 476 unmask_irq(desc);
86998aa6 477out_unlock:
239007b8 478 raw_spin_unlock(&desc->lock);
dd87eb3a 479}
14819ea1 480EXPORT_SYMBOL_GPL(handle_level_irq);
dd87eb3a 481
78129576
TG
482#ifdef CONFIG_IRQ_PREFLOW_FASTEOI
483static inline void preflow_handler(struct irq_desc *desc)
484{
485 if (desc->preflow_handler)
486 desc->preflow_handler(&desc->irq_data);
487}
488#else
489static inline void preflow_handler(struct irq_desc *desc) { }
490#endif
491
dd87eb3a 492/**
47c2a3aa 493 * handle_fasteoi_irq - irq handler for transparent controllers
dd87eb3a
TG
494 * @irq: the interrupt number
495 * @desc: the interrupt description structure for this irq
dd87eb3a 496 *
47c2a3aa 497 * Only a single callback will be issued to the chip: an ->eoi()
dd87eb3a
TG
498 * call when the interrupt has been serviced. This enables support
499 * for modern forms of interrupt handlers, which handle the flow
500 * details in hardware, transparently.
501 */
7ad5b3a5 502void
7d12e780 503handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc)
dd87eb3a 504{
239007b8 505 raw_spin_lock(&desc->lock);
dd87eb3a 506
009b4c3b 507 if (unlikely(desc->istate & IRQS_INPROGRESS))
fe200ae4
TG
508 if (!irq_check_poll(desc))
509 goto out;
dd87eb3a 510
163ef309 511 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
d6c88a50 512 kstat_incr_irqs_this_cpu(irq, desc);
dd87eb3a
TG
513
514 /*
515 * If its disabled or no action available
76d21601 516 * then mask it and get out of here:
dd87eb3a 517 */
c1594b77 518 if (unlikely(!desc->action || (desc->istate & IRQS_DISABLED))) {
2a0d6fb3
TG
519 irq_compat_set_pending(desc);
520 desc->istate |= IRQS_PENDING;
e2c0f8ff 521 mask_irq(desc);
dd87eb3a 522 goto out;
98bb244b 523 }
c69e3758
TG
524
525 if (desc->istate & IRQS_ONESHOT)
526 mask_irq(desc);
527
78129576 528 preflow_handler(desc);
a7ae4de5 529 handle_irq_event(desc);
77694b40
TG
530
531out_eoi:
0c5c1557 532 desc->irq_data.chip->irq_eoi(&desc->irq_data);
77694b40 533out_unlock:
239007b8 534 raw_spin_unlock(&desc->lock);
77694b40
TG
535 return;
536out:
537 if (!(desc->irq_data.chip->flags & IRQCHIP_EOI_IF_HANDLED))
538 goto out_eoi;
539 goto out_unlock;
dd87eb3a
TG
540}
541
542/**
543 * handle_edge_irq - edge type IRQ handler
544 * @irq: the interrupt number
545 * @desc: the interrupt description structure for this irq
dd87eb3a
TG
546 *
547 * Interrupt occures on the falling and/or rising edge of a hardware
548 * signal. The occurence is latched into the irq controller hardware
549 * and must be acked in order to be reenabled. After the ack another
550 * interrupt can happen on the same source even before the first one
dfff0615 551 * is handled by the associated event handler. If this happens it
dd87eb3a
TG
552 * might be necessary to disable (mask) the interrupt depending on the
553 * controller hardware. This requires to reenable the interrupt inside
554 * of the loop which handles the interrupts which have arrived while
555 * the handler was running. If all pending interrupts are handled, the
556 * loop is left.
557 */
7ad5b3a5 558void
7d12e780 559handle_edge_irq(unsigned int irq, struct irq_desc *desc)
dd87eb3a 560{
239007b8 561 raw_spin_lock(&desc->lock);
dd87eb3a 562
163ef309 563 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
dd87eb3a
TG
564 /*
565 * If we're currently running this IRQ, or its disabled,
566 * we shouldn't process the IRQ. Mark it pending, handle
567 * the necessary masking and go out
568 */
c1594b77
TG
569 if (unlikely((desc->istate & (IRQS_DISABLED | IRQS_INPROGRESS) ||
570 !desc->action))) {
fe200ae4 571 if (!irq_check_poll(desc)) {
2a0d6fb3
TG
572 irq_compat_set_pending(desc);
573 desc->istate |= IRQS_PENDING;
fe200ae4
TG
574 mask_ack_irq(desc);
575 goto out_unlock;
576 }
dd87eb3a 577 }
d6c88a50 578 kstat_incr_irqs_this_cpu(irq, desc);
dd87eb3a
TG
579
580 /* Start handling the irq */
22a49163 581 desc->irq_data.chip->irq_ack(&desc->irq_data);
dd87eb3a 582
dd87eb3a 583 do {
a60a5dc2 584 if (unlikely(!desc->action)) {
e2c0f8ff 585 mask_irq(desc);
dd87eb3a
TG
586 goto out_unlock;
587 }
588
589 /*
590 * When another irq arrived while we were handling
591 * one, we could have masked the irq.
592 * Renable it, if it was not disabled in meantime.
593 */
2a0d6fb3 594 if (unlikely(desc->istate & IRQS_PENDING)) {
c1594b77 595 if (!(desc->istate & IRQS_DISABLED) &&
6e40262e 596 (desc->istate & IRQS_MASKED))
c1594b77 597 unmask_irq(desc);
dd87eb3a
TG
598 }
599
a60a5dc2 600 handle_irq_event(desc);
dd87eb3a 601
2a0d6fb3 602 } while ((desc->istate & IRQS_PENDING) &&
c1594b77 603 !(desc->istate & IRQS_DISABLED));
dd87eb3a 604
dd87eb3a 605out_unlock:
239007b8 606 raw_spin_unlock(&desc->lock);
dd87eb3a
TG
607}
608
dd87eb3a 609/**
24b26d42 610 * handle_percpu_irq - Per CPU local irq handler
dd87eb3a
TG
611 * @irq: the interrupt number
612 * @desc: the interrupt description structure for this irq
dd87eb3a
TG
613 *
614 * Per CPU interrupts on SMP machines without locking requirements
615 */
7ad5b3a5 616void
7d12e780 617handle_percpu_irq(unsigned int irq, struct irq_desc *desc)
dd87eb3a 618{
35e857cb 619 struct irq_chip *chip = irq_desc_get_chip(desc);
dd87eb3a 620
d6c88a50 621 kstat_incr_irqs_this_cpu(irq, desc);
dd87eb3a 622
849f061c
TG
623 if (chip->irq_ack)
624 chip->irq_ack(&desc->irq_data);
dd87eb3a 625
849f061c 626 handle_irq_event_percpu(desc, desc->action);
dd87eb3a 627
849f061c
TG
628 if (chip->irq_eoi)
629 chip->irq_eoi(&desc->irq_data);
dd87eb3a
TG
630}
631
dd87eb3a 632void
3836ca08 633__irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained,
a460e745 634 const char *name)
dd87eb3a 635{
dd87eb3a 636 unsigned long flags;
02725e74 637 struct irq_desc *desc = irq_get_desc_buslock(irq, &flags);
dd87eb3a 638
02725e74 639 if (!desc)
dd87eb3a 640 return;
dd87eb3a 641
091738a2 642 if (!handle) {
dd87eb3a 643 handle = handle_bad_irq;
091738a2
TG
644 } else {
645 if (WARN_ON(desc->irq_data.chip == &no_irq_chip))
02725e74 646 goto out;
f8b5473f 647 }
dd87eb3a 648
dd87eb3a
TG
649 /* Uninstall? */
650 if (handle == handle_bad_irq) {
6b8ff312 651 if (desc->irq_data.chip != &no_irq_chip)
9205e31d 652 mask_ack_irq(desc);
801a0e9a 653 irq_state_set_disabled(desc);
dd87eb3a
TG
654 desc->depth = 1;
655 }
656 desc->handle_irq = handle;
a460e745 657 desc->name = name;
dd87eb3a
TG
658
659 if (handle != handle_bad_irq && is_chained) {
1ccb4e61
TG
660 irq_settings_set_noprobe(desc);
661 irq_settings_set_norequest(desc);
46999238 662 irq_startup(desc);
dd87eb3a 663 }
02725e74
TG
664out:
665 irq_put_desc_busunlock(desc, flags);
dd87eb3a 666}
3836ca08 667EXPORT_SYMBOL_GPL(__irq_set_handler);
dd87eb3a
TG
668
669void
3836ca08 670irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip,
a460e745 671 irq_flow_handler_t handle, const char *name)
dd87eb3a 672{
35e857cb 673 irq_set_chip(irq, chip);
3836ca08 674 __irq_set_handler(irq, handle, 0, name);
dd87eb3a 675}
46f4f8f6 676
44247184 677void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set)
46f4f8f6 678{
46f4f8f6 679 unsigned long flags;
02725e74 680 struct irq_desc *desc = irq_get_desc_lock(irq, &flags);
46f4f8f6 681
44247184 682 if (!desc)
46f4f8f6 683 return;
a005677b
TG
684 irq_settings_clr_and_set(desc, clr, set);
685
876dbd4c 686 irqd_clear(&desc->irq_data, IRQD_NO_BALANCING | IRQD_PER_CPU |
e1ef8241 687 IRQD_TRIGGER_MASK | IRQD_LEVEL | IRQD_MOVE_PCNTXT);
a005677b
TG
688 if (irq_settings_has_no_balance_set(desc))
689 irqd_set(&desc->irq_data, IRQD_NO_BALANCING);
690 if (irq_settings_is_per_cpu(desc))
691 irqd_set(&desc->irq_data, IRQD_PER_CPU);
e1ef8241
TG
692 if (irq_settings_can_move_pcntxt(desc))
693 irqd_set(&desc->irq_data, IRQD_MOVE_PCNTXT);
a005677b 694
876dbd4c
TG
695 irqd_set(&desc->irq_data, irq_settings_get_trigger_mask(desc));
696
02725e74 697 irq_put_desc_unlock(desc, flags);
46f4f8f6 698}