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sky2: align IP header on Rx if possible
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
793b883e 25#include <linux/crc32.h>
cd28ab6a
SH		 26#include <linux/kernel.h>
27#include <linux/version.h>
28#include <linux/module.h>
29#include <linux/netdevice.h>
d0bbccfa 30#include <linux/dma-mapping.h>
cd28ab6a
SH		 31#include <linux/etherdevice.h>
32#include <linux/ethtool.h>
33#include <linux/pci.h>
34#include <linux/ip.h>
c9bdd4b5 35#include <net/ip.h>
cd28ab6a
SH		 36#include <linux/tcp.h>
37#include <linux/in.h>
38#include <linux/delay.h>
91c86df5 39#include <linux/workqueue.h>
d1f13708 40#include <linux/if_vlan.h>
d70cd51a 41#include <linux/prefetch.h>
3cf26753 42#include <linux/debugfs.h>
ef743d33 43#include <linux/mii.h>
cd28ab6a
SH		 44
45#include <asm/irq.h>
46
d1f13708
SH		 47#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48#define SKY2_VLAN_TAG_USED 1
49#endif
50
cd28ab6a
SH		 51#include "sky2.h"
52
53#define DRV_NAME "sky2"
1e354787 54#define DRV_VERSION "1.20"
cd28ab6a
SH		 55#define PFX DRV_NAME " "
56
57/*
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
14d0263f 60 * similar to Tigon3.
cd28ab6a
SH		 61 */
62
14d0263f 63#define RX_LE_SIZE 1024
cd28ab6a 64#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 65#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 66#define RX_DEF_PENDING RX_MAX_PENDING
793b883e
SH		 67
68#define TX_RING_SIZE 512
69#define TX_DEF_PENDING (TX_RING_SIZE - 1)
70#define TX_MIN_PENDING 64
b19666d9 71#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
cd28ab6a 72
793b883e 73#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a 74#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
cd28ab6a
SH		 75#define TX_WATCHDOG (5 * HZ)
76#define NAPI_WEIGHT 64
77#define PHY_RETRIES 1000
78
f4331a6d
SH		 79#define SKY2_EEPROM_MAGIC 0x9955aabb
80
81
cb5d9547
SH		 82#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
83
cd28ab6a 84static const u32 default_msg =
793b883e
SH		 85 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
86 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 87 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 88
793b883e 89static int debug = -1; /* defaults above */
cd28ab6a
SH		 90module_param(debug, int, 0);
91MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
92
14d0263f 93static int copybreak __read_mostly = 128;
bdb5c58e
SH		 94module_param(copybreak, int, 0);
95MODULE_PARM_DESC(copybreak, "Receive copy threshold");
96
fb2690a9
SH		 97static int disable_msi = 0;
98module_param(disable_msi, int, 0);
99MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
100
cd28ab6a 101static const struct pci_device_id sky2_id_table[] = {
e5b74c7d
SH		 102 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
2d2a3871 104 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
f1a0b6f5 107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
e5b74c7d
SH		 108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
05745c4a 120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
e5b74c7d 121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
5a37a68d 122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
05745c4a 123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
e5b74c7d
SH		 124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
05745c4a 129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
e5b74c7d
SH		 130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
f1a0b6f5
SH		 133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
69161611 135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
5a37a68d 136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
cd28ab6a
SH		 137 { 0 }
138};
793b883e 139
cd28ab6a
SH		 140MODULE_DEVICE_TABLE(pci, sky2_id_table);
141
142/* Avoid conditionals by using array */
143static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
144static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 145static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 146
92f965e8
SH		 147/* This driver supports yukon2 chipset only */
148static const char *yukon2_name[] = {
149 "XL", /* 0xb3 */
150 "EC Ultra", /* 0xb4 */
93745494 151 "Extreme", /* 0xb5 */
92f965e8
SH		 152 "EC", /* 0xb6 */
153 "FE", /* 0xb7 */
05745c4a 154 "FE+", /* 0xb8 */
793b883e
SH		 155};
156
d1b139c0
SH		 157static void sky2_set_multicast(struct net_device *dev);
158
af043aa5 159/* Access to PHY via serial interconnect */
ef743d33 160static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 161{
162 int i;
163
164 gma_write16(hw, port, GM_SMI_DATA, val);
165 gma_write16(hw, port, GM_SMI_CTRL,
166 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
167
168 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 169 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
170 if (ctrl == 0xffff)
171 goto io_error;
172
173 if (!(ctrl & GM_SMI_CT_BUSY))
ef743d33 174 return 0;
af043aa5
SH		 175
176 udelay(10);
cd28ab6a 177 }
ef743d33 178
af043aa5 179 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 180 return -ETIMEDOUT;
af043aa5
SH		 181
182io_error:
183 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
184 return -EIO;
cd28ab6a
SH		 185}
186
ef743d33 187static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 188{
189 int i;
190
793b883e 191 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 192 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
193
194 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 195 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
196 if (ctrl == 0xffff)
197 goto io_error;
198
199 if (ctrl & GM_SMI_CT_RD_VAL) {
ef743d33
SH		 200 *val = gma_read16(hw, port, GM_SMI_DATA);
201 return 0;
202 }
203
af043aa5 204 udelay(10);
cd28ab6a
SH		 205 }
206
af043aa5 207 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
ef743d33 208 return -ETIMEDOUT;
af043aa5
SH		 209io_error:
210 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
211 return -EIO;
ef743d33
SH		 212}
213
af043aa5 214static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
ef743d33
SH		 215{
216 u16 v;
af043aa5 217 __gm_phy_read(hw, port, reg, &v);
ef743d33 218 return v;
cd28ab6a
SH		 219}
220
5afa0a9c 221
ae306cca
SH		 222static void sky2_power_on(struct sky2_hw *hw)
223{
224 /* switch power to VCC (WA for VAUX problem) */
225 sky2_write8(hw, B0_POWER_CTRL,
226 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
5afa0a9c 227
ae306cca
SH		 228 /* disable Core Clock Division, */
229 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
d3bcfbeb 230
ae306cca
SH		 231 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
232 /* enable bits are inverted */
233 sky2_write8(hw, B2_Y2_CLK_GATE,
234 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
235 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
236 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
237 else
238 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
977bdf06 239
ea76e635 240 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
fc99fe06 241 u32 reg;
5afa0a9c 242
b32f40c4 243 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
b2345773 244
b32f40c4 245 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
fc99fe06
SH		 246 /* set all bits to 0 except bits 15..12 and 8 */
247 reg &= P_ASPM_CONTROL_MSK;
b32f40c4 248 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
fc99fe06 249
b32f40c4 250 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
fc99fe06
SH		 251 /* set all bits to 0 except bits 28 & 27 */
252 reg &= P_CTL_TIM_VMAIN_AV_MSK;
b32f40c4 253 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
fc99fe06 254
b32f40c4 255 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
8f70920f
SH		 256
257 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
258 reg = sky2_read32(hw, B2_GP_IO);
259 reg |= GLB_GPIO_STAT_RACE_DIS;
260 sky2_write32(hw, B2_GP_IO, reg);
b2345773
SH		 261
262 sky2_read32(hw, B2_GP_IO);
5afa0a9c 263 }
ae306cca 264}
5afa0a9c 265
ae306cca
SH		 266static void sky2_power_aux(struct sky2_hw *hw)
267{
268 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
269 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
270 else
271 /* enable bits are inverted */
272 sky2_write8(hw, B2_Y2_CLK_GATE,
273 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
274 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
275 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
276
277 /* switch power to VAUX */
278 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
279 sky2_write8(hw, B0_POWER_CTRL,
280 (PC_VAUX_ENA | PC_VCC_ENA |
281 PC_VAUX_ON | PC_VCC_OFF));
5afa0a9c
SH		 282}
283
d3bcfbeb 284static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 285{
286 u16 reg;
287
288 /* disable all GMAC IRQ's */
289 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
793b883e 290
cd28ab6a
SH		 291 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
292 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
293 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
294 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
295
296 reg = gma_read16(hw, port, GM_RX_CTRL);
297 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
298 gma_write16(hw, port, GM_RX_CTRL, reg);
299}
300
16ad91e1
SH		 301/* flow control to advertise bits */
302static const u16 copper_fc_adv[] = {
303 [FC_NONE] = 0,
304 [FC_TX] = PHY_M_AN_ASP,
305 [FC_RX] = PHY_M_AN_PC,
306 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
307};
308
309/* flow control to advertise bits when using 1000BaseX */
310static const u16 fiber_fc_adv[] = {
df3fe1f3 311 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
16ad91e1
SH		 312 [FC_TX] = PHY_M_P_ASYM_MD_X,
313 [FC_RX] = PHY_M_P_SYM_MD_X,
df3fe1f3 314 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
16ad91e1
SH		 315};
316
317/* flow control to GMA disable bits */
318static const u16 gm_fc_disable[] = {
319 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
320 [FC_TX] = GM_GPCR_FC_RX_DIS,
321 [FC_RX] = GM_GPCR_FC_TX_DIS,
322 [FC_BOTH] = 0,
323};
324
325
cd28ab6a
SH		 326static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
327{
328 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 329 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 330
ea76e635
SH		 331 if (sky2->autoneg == AUTONEG_ENABLE &&
332 !(hw->flags & SKY2_HW_NEWER_PHY)) {
cd28ab6a
SH		 333 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
334
335 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 336 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 337 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
338
53419c68 339 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
cd28ab6a 340 if (hw->chip_id == CHIP_ID_YUKON_EC)
53419c68 341 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 342 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
343 else
53419c68
SH		 344 /* set master & slave downshift counter to 1x */
345 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
cd28ab6a
SH		 346
347 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
348 }
349
350 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 351 if (sky2_is_copper(hw)) {
05745c4a 352 if (!(hw->flags & SKY2_HW_GIGABIT)) {
cd28ab6a
SH		 353 /* enable automatic crossover */
354 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
6d3105d5
SH		 355
356 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
357 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
358 u16 spec;
359
360 /* Enable Class A driver for FE+ A0 */
361 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
362 spec |= PHY_M_FESC_SEL_CL_A;
363 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
364 }
cd28ab6a
SH		 365 } else {
366 /* disable energy detect */
367 ctrl &= ~PHY_M_PC_EN_DET_MSK;
368
369 /* enable automatic crossover */
370 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
371
53419c68 372 /* downshift on PHY 88E1112 and 88E1149 is changed */
93745494 373 if (sky2->autoneg == AUTONEG_ENABLE
ea76e635 374 && (hw->flags & SKY2_HW_NEWER_PHY)) {
53419c68 375 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 376 ctrl &= ~PHY_M_PC_DSC_MSK;
377 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
378 }
379 }
cd28ab6a
SH		 380 } else {
381 /* workaround for deviation #4.88 (CRC errors) */
382 /* disable Automatic Crossover */
383
384 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 385 }
cd28ab6a 386
b89165f2
SH		 387 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
388
389 /* special setup for PHY 88E1112 Fiber */
ea76e635 390 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
b89165f2 391 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 392
b89165f2
SH		 393 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
394 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
395 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
396 ctrl &= ~PHY_M_MAC_MD_MSK;
397 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
398 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
399
400 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 401 /* select page 1 to access Fiber registers */
402 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 403
404 /* for SFP-module set SIGDET polarity to low */
405 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
406 ctrl |= PHY_M_FIB_SIGD_POL;
34dd962b 407 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
cd28ab6a 408 }
b89165f2
SH		 409
410 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 411 }
412
7800fddc 413 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 414 ct1000 = 0;
415 adv = PHY_AN_CSMA;
2eaba1a2 416 reg = 0;
cd28ab6a
SH		 417
418 if (sky2->autoneg == AUTONEG_ENABLE) {
b89165f2 419 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 420 if (sky2->advertising & ADVERTISED_1000baseT_Full)
421 ct1000 |= PHY_M_1000C_AFD;
422 if (sky2->advertising & ADVERTISED_1000baseT_Half)
423 ct1000 |= PHY_M_1000C_AHD;
424 if (sky2->advertising & ADVERTISED_100baseT_Full)
425 adv |= PHY_M_AN_100_FD;
426 if (sky2->advertising & ADVERTISED_100baseT_Half)
427 adv |= PHY_M_AN_100_HD;
428 if (sky2->advertising & ADVERTISED_10baseT_Full)
429 adv |= PHY_M_AN_10_FD;
430 if (sky2->advertising & ADVERTISED_10baseT_Half)
431 adv |= PHY_M_AN_10_HD;
709c6e7b 432
16ad91e1 433 adv |= copper_fc_adv[sky2->flow_mode];
b89165f2
SH		 434 } else { /* special defines for FIBER (88E1040S only) */
435 if (sky2->advertising & ADVERTISED_1000baseT_Full)
436 adv |= PHY_M_AN_1000X_AFD;
437 if (sky2->advertising & ADVERTISED_1000baseT_Half)
438 adv |= PHY_M_AN_1000X_AHD;
cd28ab6a 439
16ad91e1 440 adv |= fiber_fc_adv[sky2->flow_mode];
709c6e7b 441 }
cd28ab6a
SH		 442
443 /* Restart Auto-negotiation */
444 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
445 } else {
446 /* forced speed/duplex settings */
447 ct1000 = PHY_M_1000C_MSE;
448
2eaba1a2
SH		 449 /* Disable auto update for duplex flow control and speed */
450 reg |= GM_GPCR_AU_ALL_DIS;
cd28ab6a
SH		 451
452 switch (sky2->speed) {
453 case SPEED_1000:
454 ctrl |= PHY_CT_SP1000;
2eaba1a2 455 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 456 break;
457 case SPEED_100:
458 ctrl |= PHY_CT_SP100;
2eaba1a2 459 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 460 break;
461 }
462
2eaba1a2
SH		 463 if (sky2->duplex == DUPLEX_FULL) {
464 reg |= GM_GPCR_DUP_FULL;
465 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 466 } else if (sky2->speed < SPEED_1000)
467 sky2->flow_mode = FC_NONE;
2eaba1a2 468
2eaba1a2 469
16ad91e1 470 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 471
472 /* Forward pause packets to GMAC? */
16ad91e1 473 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 474 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
475 else
476 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 477 }
478
2eaba1a2
SH		 479 gma_write16(hw, port, GM_GP_CTRL, reg);
480
05745c4a 481 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a
SH		 482 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
483
484 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
485 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
486
487 /* Setup Phy LED's */
488 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
489 ledover = 0;
490
491 switch (hw->chip_id) {
492 case CHIP_ID_YUKON_FE:
493 /* on 88E3082 these bits are at 11..9 (shifted left) */
494 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
495
496 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
497
498 /* delete ACT LED control bits */
499 ctrl &= ~PHY_M_FELP_LED1_MSK;
500 /* change ACT LED control to blink mode */
501 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
502 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
503 break;
504
05745c4a
SH		 505 case CHIP_ID_YUKON_FE_P:
506 /* Enable Link Partner Next Page */
507 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
508 ctrl |= PHY_M_PC_ENA_LIP_NP;
509
510 /* disable Energy Detect and enable scrambler */
511 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
512 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
513
514 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
515 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
516 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
517 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
518
519 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
520 break;
521
cd28ab6a 522 case CHIP_ID_YUKON_XL:
793b883e 523 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 524
525 /* select page 3 to access LED control register */
526 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
527
528 /* set LED Function Control register */
ed6d32c7
SH		 529 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
530 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
531 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
532 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
533 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 534
535 /* set Polarity Control register */
536 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 537 (PHY_M_POLC_LS1_P_MIX(4) |
538 PHY_M_POLC_IS0_P_MIX(4) |
539 PHY_M_POLC_LOS_CTRL(2) |
540 PHY_M_POLC_INIT_CTRL(2) |
541 PHY_M_POLC_STA1_CTRL(2) |
542 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 543
544 /* restore page register */
793b883e 545 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 546 break;
93745494 547
ed6d32c7 548 case CHIP_ID_YUKON_EC_U:
93745494 549 case CHIP_ID_YUKON_EX:
ed6d32c7
SH		 550 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
551
552 /* select page 3 to access LED control register */
553 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
554
555 /* set LED Function Control register */
556 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
557 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
558 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
559 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
560 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
561
562 /* set Blink Rate in LED Timer Control Register */
563 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
564 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
565 /* restore page register */
566 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
567 break;
cd28ab6a
SH		 568
569 default:
570 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
571 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
572 /* turn off the Rx LED (LED_RX) */
0efdf262 573 ledover &= ~PHY_M_LED_MO_RX;
cd28ab6a
SH		 574 }
575
9467a8fc
SH		 576 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
577 hw->chip_rev == CHIP_REV_YU_EC_U_A1) {
977bdf06 578 /* apply fixes in PHY AFE */
ed6d32c7
SH		 579 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
580
977bdf06 581 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 582 gm_phy_write(hw, port, 0x18, 0xaa99);
583 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 584
977bdf06 585 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
ed6d32c7
SH		 586 gm_phy_write(hw, port, 0x18, 0xa204);
587 gm_phy_write(hw, port, 0x17, 0x2002);
977bdf06
SH		 588
589 /* set page register to 0 */
9467a8fc 590 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
05745c4a
SH		 591 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
592 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
593 /* apply workaround for integrated resistors calibration */
594 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
595 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
93745494 596 } else if (hw->chip_id != CHIP_ID_YUKON_EX) {
05745c4a 597 /* no effect on Yukon-XL */
977bdf06 598 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 599
977bdf06
SH		 600 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
601 /* turn on 100 Mbps LED (LED_LINK100) */
0efdf262 602 ledover |= PHY_M_LED_MO_100;
977bdf06 603 }
cd28ab6a 604
977bdf06
SH		 605 if (ledover)
606 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
607
608 }
2eaba1a2 609
d571b694 610 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 611 if (sky2->autoneg == AUTONEG_ENABLE)
612 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
613 else
614 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
615}
616
d3bcfbeb
SH		 617static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
618{
619 u32 reg1;
ff35164e
SH		 620 static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
621 static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
d3bcfbeb 622
b32f40c4 623 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
ff35164e 624 /* Turn on/off phy power saving */
d3bcfbeb 625 if (onoff)
d3bcfbeb
SH		 626 reg1 &= ~phy_power[port];
627 else
628 reg1 |= phy_power[port];
629
ff35164e
SH		 630 if (onoff && hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
631 reg1 |= coma_mode[port];
632
b32f40c4
SH		 633 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
634 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
167f53d0 635
d3bcfbeb
SH		 636 udelay(100);
637}
638
1b537565
SH		 639/* Force a renegotiation */
640static void sky2_phy_reinit(struct sky2_port *sky2)
641{
e07b1aa8 642 spin_lock_bh(&sky2->phy_lock);
1b537565 643 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 644 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 645}
646
e3173832
SH		 647/* Put device in state to listen for Wake On Lan */
648static void sky2_wol_init(struct sky2_port *sky2)
649{
650 struct sky2_hw *hw = sky2->hw;
651 unsigned port = sky2->port;
652 enum flow_control save_mode;
653 u16 ctrl;
654 u32 reg1;
655
656 /* Bring hardware out of reset */
657 sky2_write16(hw, B0_CTST, CS_RST_CLR);
658 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
659
660 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
661 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
662
663 /* Force to 10/100
664 * sky2_reset will re-enable on resume
665 */
666 save_mode = sky2->flow_mode;
667 ctrl = sky2->advertising;
668
669 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
670 sky2->flow_mode = FC_NONE;
671 sky2_phy_power(hw, port, 1);
672 sky2_phy_reinit(sky2);
673
674 sky2->flow_mode = save_mode;
675 sky2->advertising = ctrl;
676
677 /* Set GMAC to no flow control and auto update for speed/duplex */
678 gma_write16(hw, port, GM_GP_CTRL,
679 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
680 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
681
682 /* Set WOL address */
683 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
684 sky2->netdev->dev_addr, ETH_ALEN);
685
686 /* Turn on appropriate WOL control bits */
687 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
688 ctrl = 0;
689 if (sky2->wol & WAKE_PHY)
690 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
691 else
692 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
693
694 if (sky2->wol & WAKE_MAGIC)
695 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
696 else
697 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
698
699 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
700 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
701
702 /* Turn on legacy PCI-Express PME mode */
b32f40c4 703 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
e3173832 704 reg1 |= PCI_Y2_PME_LEGACY;
b32f40c4 705 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
e3173832
SH		 706
707 /* block receiver */
708 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
709
710}
711
69161611
SH		 712static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
713{
05745c4a
SH		 714 struct net_device *dev = hw->dev[port];
715
716 if (dev->mtu <= ETH_DATA_LEN)
69161611 717 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
05745c4a
SH		 718 TX_JUMBO_DIS | TX_STFW_ENA);
719
720 else if (hw->chip_id != CHIP_ID_YUKON_EC_U)
721 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
722 TX_STFW_ENA | TX_JUMBO_ENA);
723 else {
724 /* set Tx GMAC FIFO Almost Empty Threshold */
725 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
726 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
69161611 727
05745c4a
SH		 728 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
729 TX_JUMBO_ENA | TX_STFW_DIS);
69161611 730
05745c4a
SH		 731 /* Can't do offload because of lack of store/forward */
732 dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM);
69161611
SH		 733 }
734}
735
cd28ab6a
SH		 736static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
737{
738 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
739 u16 reg;
25cccecc 740 u32 rx_reg;
cd28ab6a
SH		 741 int i;
742 const u8 *addr = hw->dev[port]->dev_addr;
743
f350339c
SH		 744 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
745 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
cd28ab6a
SH		 746
747 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
748
793b883e 749 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 750 /* WA DEV_472 -- looks like crossed wires on port 2 */
751 /* clear GMAC 1 Control reset */
752 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
753 do {
754 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
755 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
756 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
757 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
758 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
759 }
760
793b883e 761 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 762
2eaba1a2
SH		 763 /* Enable Transmit FIFO Underrun */
764 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
765
e07b1aa8 766 spin_lock_bh(&sky2->phy_lock);
cd28ab6a 767 sky2_phy_init(hw, port);
e07b1aa8 768 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 769
770 /* MIB clear */
771 reg = gma_read16(hw, port, GM_PHY_ADDR);
772 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
773
43f2f104
SH		 774 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
775 gma_read16(hw, port, i);
cd28ab6a
SH		 776 gma_write16(hw, port, GM_PHY_ADDR, reg);
777
778 /* transmit control */
779 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
780
781 /* receive control reg: unicast + multicast + no FCS */
782 gma_write16(hw, port, GM_RX_CTRL,
793b883e 783 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 784
785 /* transmit flow control */
786 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
787
788 /* transmit parameter */
789 gma_write16(hw, port, GM_TX_PARAM,
790 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
791 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
792 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
793 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
794
795 /* serial mode register */
796 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 797 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 798
6b1a3aef 799 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 800 reg |= GM_SMOD_JUMBO_ENA;
801
802 gma_write16(hw, port, GM_SERIAL_MODE, reg);
803
cd28ab6a
SH		 804 /* virtual address for data */
805 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
806
793b883e
SH		 807 /* physical address: used for pause frames */
808 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
809
810 /* ignore counter overflows */
cd28ab6a
SH		 811 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
812 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
813 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
814
815 /* Configure Rx MAC FIFO */
816 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
25cccecc 817 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
05745c4a
SH		 818 if (hw->chip_id == CHIP_ID_YUKON_EX ||
819 hw->chip_id == CHIP_ID_YUKON_FE_P)
25cccecc 820 rx_reg |= GMF_RX_OVER_ON;
69161611 821
25cccecc 822 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
cd28ab6a 823
798fdd07
SH		 824 if (hw->chip_id == CHIP_ID_YUKON_XL) {
825 /* Hardware errata - clear flush mask */
826 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
827 } else {
828 /* Flush Rx MAC FIFO on any flow control or error */
829 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
830 }
cd28ab6a 831
8df9a876 832 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
05745c4a
SH		 833 reg = RX_GMF_FL_THR_DEF + 1;
834 /* Another magic mystery workaround from sk98lin */
835 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
836 hw->chip_rev == CHIP_REV_YU_FE2_A0)
837 reg = 0x178;
838 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
cd28ab6a
SH		 839
840 /* Configure Tx MAC FIFO */
841 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
842 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 843
e0c28116
SH		 844 /* On chips without ram buffer, pause is controled by MAC level */
845 if (sky2_read8(hw, B2_E_0) == 0) {
8df9a876 846 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
5a5b1ea0 847 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
b628ed98 848
69161611 849 sky2_set_tx_stfwd(hw, port);
5a5b1ea0
SH		 850 }
851
e970d1f8
SH		 852 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
853 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
854 /* disable dynamic watermark */
855 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
856 reg &= ~TX_DYN_WM_ENA;
857 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
858 }
cd28ab6a
SH		 859}
860
67712901
SH		 861/* Assign Ram Buffer allocation to queue */
862static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 863{
67712901
SH		 864 u32 end;
865
866 /* convert from K bytes to qwords used for hw register */
867 start *= 1024/8;
868 space *= 1024/8;
869 end = start + space - 1;
793b883e 870
cd28ab6a
SH		 871 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
872 sky2_write32(hw, RB_ADDR(q, RB_START), start);
873 sky2_write32(hw, RB_ADDR(q, RB_END), end);
874 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
875 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
876
877 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 878 u32 tp = space - space/4;
793b883e 879
1c28f6ba
SH		 880 /* On receive queue's set the thresholds
881 * give receiver priority when > 3/4 full
882 * send pause when down to 2K
883 */
884 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
885 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 886
1c28f6ba
SH		 887 tp = space - 2048/8;
888 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
889 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 890 } else {
891 /* Enable store & forward on Tx queue's because
892 * Tx FIFO is only 1K on Yukon
893 */
894 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
895 }
896
897 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 898 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 899}
900
cd28ab6a 901/* Setup Bus Memory Interface */
af4ed7e6 902static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 903{
904 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
905 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
906 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 907 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 908}
909
cd28ab6a
SH		 910/* Setup prefetch unit registers. This is the interface between
911 * hardware and driver list elements
912 */
8cc048e3 913static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 914 u64 addr, u32 last)
915{
cd28ab6a
SH		 916 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
917 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
918 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
919 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
920 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
921 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 922
923 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 924}
925
793b883e
SH		 926static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
927{
928 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
929
cb5d9547 930 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
291ea614 931 le->ctrl = 0;
793b883e
SH		 932 return le;
933}
cd28ab6a 934
88f5f0ca
SH		 935static void tx_init(struct sky2_port *sky2)
936{
937 struct sky2_tx_le *le;
938
939 sky2->tx_prod = sky2->tx_cons = 0;
940 sky2->tx_tcpsum = 0;
941 sky2->tx_last_mss = 0;
942
943 le = get_tx_le(sky2);
944 le->addr = 0;
945 le->opcode = OP_ADDR64 | HW_OWNER;
88f5f0ca
SH		 946}
947
291ea614
SH		 948static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
949 struct sky2_tx_le *le)
950{
951 return sky2->tx_ring + (le - sky2->tx_le);
952}
953
290d4de5
SH		 954/* Update chip's next pointer */
955static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 956{
50432cb5 957 /* Make sure write' to descriptors are complete before we tell hardware */
762c2de2 958 wmb();
50432cb5
SH		 959 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
960
961 /* Synchronize I/O on since next processor may write to tail */
962 mmiowb();
cd28ab6a
SH		 963}
964
793b883e 965
cd28ab6a
SH		 966static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
967{
968 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 969 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 970 le->ctrl = 0;
cd28ab6a
SH		 971 return le;
972}
973
14d0263f
SH		 974/* Build description to hardware for one receive segment */
975static void sky2_rx_add(struct sky2_port *sky2, u8 op,
976 dma_addr_t map, unsigned len)
cd28ab6a
SH		 977{
978 struct sky2_rx_le *le;
979
86c6887e 980 if (sizeof(dma_addr_t) > sizeof(u32)) {
cd28ab6a 981 le = sky2_next_rx(sky2);
86c6887e 982 le->addr = cpu_to_le32(upper_32_bits(map));
cd28ab6a
SH		 983 le->opcode = OP_ADDR64 | HW_OWNER;
984 }
793b883e 985
cd28ab6a 986 le = sky2_next_rx(sky2);
734d1868
SH		 987 le->addr = cpu_to_le32((u32) map);
988 le->length = cpu_to_le16(len);
14d0263f 989 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 990}
991
14d0263f
SH		 992/* Build description to hardware for one possibly fragmented skb */
993static void sky2_rx_submit(struct sky2_port *sky2,
994 const struct rx_ring_info *re)
995{
996 int i;
997
998 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
999
1000 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1001 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1002}
1003
1004
1005static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
1006 unsigned size)
1007{
1008 struct sk_buff *skb = re->skb;
1009 int i;
1010
1011 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
1012 pci_unmap_len_set(re, data_size, size);
1013
1014 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1015 re->frag_addr[i] = pci_map_page(pdev,
1016 skb_shinfo(skb)->frags[i].page,
1017 skb_shinfo(skb)->frags[i].page_offset,
1018 skb_shinfo(skb)->frags[i].size,
1019 PCI_DMA_FROMDEVICE);
1020}
1021
1022static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1023{
1024 struct sk_buff *skb = re->skb;
1025 int i;
1026
1027 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1028 PCI_DMA_FROMDEVICE);
1029
1030 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1031 pci_unmap_page(pdev, re->frag_addr[i],
1032 skb_shinfo(skb)->frags[i].size,
1033 PCI_DMA_FROMDEVICE);
1034}
793b883e 1035
cd28ab6a
SH		 1036/* Tell chip where to start receive checksum.
1037 * Actually has two checksums, but set both same to avoid possible byte
1038 * order problems.
1039 */
793b883e 1040static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a 1041{
ea76e635 1042 struct sky2_rx_le *le = sky2_next_rx(sky2);
793b883e 1043
ea76e635
SH		 1044 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1045 le->ctrl = 0;
1046 le->opcode = OP_TCPSTART | HW_OWNER;
cd28ab6a 1047
ea76e635
SH		 1048 sky2_write32(sky2->hw,
1049 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1050 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 1051}
1052
6b1a3aef
SH		 1053/*
1054 * The RX Stop command will not work for Yukon-2 if the BMU does not
1055 * reach the end of packet and since we can't make sure that we have
1056 * incoming data, we must reset the BMU while it is not doing a DMA
1057 * transfer. Since it is possible that the RX path is still active,
1058 * the RX RAM buffer will be stopped first, so any possible incoming
1059 * data will not trigger a DMA. After the RAM buffer is stopped, the
1060 * BMU is polled until any DMA in progress is ended and only then it
1061 * will be reset.
1062 */
1063static void sky2_rx_stop(struct sky2_port *sky2)
1064{
1065 struct sky2_hw *hw = sky2->hw;
1066 unsigned rxq = rxqaddr[sky2->port];
1067 int i;
1068
1069 /* disable the RAM Buffer receive queue */
1070 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1071
1072 for (i = 0; i < 0xffff; i++)
1073 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1074 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1075 goto stopped;
1076
1077 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1078 sky2->netdev->name);
1079stopped:
1080 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1081
1082 /* reset the Rx prefetch unit */
1083 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
50432cb5 1084 mmiowb();
6b1a3aef 1085}
793b883e 1086
d571b694 1087/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 1088static void sky2_rx_clean(struct sky2_port *sky2)
1089{
1090 unsigned i;
1091
1092 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 1093 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 1094 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 1095
1096 if (re->skb) {
14d0263f 1097 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 1098 kfree_skb(re->skb);
1099 re->skb = NULL;
1100 }
1101 }
1102}
1103
ef743d33
SH		 1104/* Basic MII support */
1105static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1106{
1107 struct mii_ioctl_data *data = if_mii(ifr);
1108 struct sky2_port *sky2 = netdev_priv(dev);
1109 struct sky2_hw *hw = sky2->hw;
1110 int err = -EOPNOTSUPP;
1111
1112 if (!netif_running(dev))
1113 return -ENODEV; /* Phy still in reset */
1114
d89e1343 1115 switch (cmd) {
ef743d33
SH		 1116 case SIOCGMIIPHY:
1117 data->phy_id = PHY_ADDR_MARV;
1118
1119 /* fallthru */
1120 case SIOCGMIIREG: {
1121 u16 val = 0;
91c86df5 1122
e07b1aa8 1123 spin_lock_bh(&sky2->phy_lock);
ef743d33 1124 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 1125 spin_unlock_bh(&sky2->phy_lock);
91c86df5 1126
ef743d33
SH		 1127 data->val_out = val;
1128 break;
1129 }
1130
1131 case SIOCSMIIREG:
1132 if (!capable(CAP_NET_ADMIN))
1133 return -EPERM;
1134
e07b1aa8 1135 spin_lock_bh(&sky2->phy_lock);
ef743d33
SH		 1136 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1137 data->val_in);
e07b1aa8 1138 spin_unlock_bh(&sky2->phy_lock);
ef743d33
SH		 1139 break;
1140 }
1141 return err;
1142}
1143
d1f13708
SH		 1144#ifdef SKY2_VLAN_TAG_USED
1145static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1146{
1147 struct sky2_port *sky2 = netdev_priv(dev);
1148 struct sky2_hw *hw = sky2->hw;
1149 u16 port = sky2->port;
d1f13708 1150
2bb8c262 1151 netif_tx_lock_bh(dev);
bea3348e 1152 napi_disable(&hw->napi);
d1f13708 1153
d1f13708 1154 sky2->vlgrp = grp;
3d4e66f5
SH		 1155 if (grp) {
1156 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1157 RX_VLAN_STRIP_ON);
1158 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1159 TX_VLAN_TAG_ON);
1160 } else {
1161 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1162 RX_VLAN_STRIP_OFF);
1163 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1164 TX_VLAN_TAG_OFF);
1165 }
d1f13708 1166
d1d08d12 1167 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 1168 napi_enable(&hw->napi);
2bb8c262 1169 netif_tx_unlock_bh(dev);
d1f13708
SH		 1170}
1171#endif
1172
82788c7a 1173/*
14d0263f
SH		 1174 * Allocate an skb for receiving. If the MTU is large enough
1175 * make the skb non-linear with a fragment list of pages.
82788c7a 1176 */
14d0263f 1177static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1178{
1179 struct sk_buff *skb;
14d0263f 1180 int i;
82788c7a 1181
f03b8654
SH		 1182 if (sky2->hw->flags & SKY2_HW_FIFO_HANG_CHECK) {
1183 unsigned char *start;
1184 /*
1185 * Workaround for a bug in FIFO that cause hang
1186 * if the FIFO if the receive buffer is not 64 byte aligned.
1187 * The buffer returned from netdev_alloc_skb is
1188 * aligned except if slab debugging is enabled.
1189 */
1190 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + 8);
1191 if (!skb)
1192 goto nomem;
1193 start = PTR_ALIGN(skb->data, 8);
1194 skb_reserve(skb, start - skb->data);
1195 } else {
1196 skb = netdev_alloc_skb(sky2->netdev,
1197 sky2->rx_data_size + NET_IP_ALIGN);
1198 if (!skb)
1199 goto nomem;
1200 skb_reserve(skb, NET_IP_ALIGN);
1201 }
14d0263f
SH		 1202
1203 for (i = 0; i < sky2->rx_nfrags; i++) {
1204 struct page *page = alloc_page(GFP_ATOMIC);
1205
1206 if (!page)
1207 goto free_partial;
1208 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1209 }
1210
1211 return skb;
14d0263f
SH		 1212free_partial:
1213 kfree_skb(skb);
1214nomem:
1215 return NULL;
82788c7a
SH		 1216}
1217
55c9dd35
SH		 1218static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1219{
1220 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1221}
1222
cd28ab6a
SH		 1223/*
1224 * Allocate and setup receiver buffer pool.
14d0263f
SH		 1225 * Normal case this ends up creating one list element for skb
1226 * in the receive ring. Worst case if using large MTU and each
1227 * allocation falls on a different 64 bit region, that results
1228 * in 6 list elements per ring entry.
1229 * One element is used for checksum enable/disable, and one
1230 * extra to avoid wrap.
cd28ab6a 1231 */
6b1a3aef 1232static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1233{
6b1a3aef 1234 struct sky2_hw *hw = sky2->hw;
14d0263f 1235 struct rx_ring_info *re;
6b1a3aef 1236 unsigned rxq = rxqaddr[sky2->port];
14d0263f 1237 unsigned i, size, space, thresh;
cd28ab6a 1238
6b1a3aef 1239 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1240 sky2_qset(hw, rxq);
977bdf06 1241
c3905bc4
SH		 1242 /* On PCI express lowering the watermark gives better performance */
1243 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1244 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1245
1246 /* These chips have no ram buffer?
1247 * MAC Rx RAM Read is controlled by hardware */
8df9a876 1248 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
c3905bc4
SH		 1249 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1250 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
f449c7c1 1251 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
977bdf06 1252
6b1a3aef
SH		 1253 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1254
ea76e635
SH		 1255 if (!(hw->flags & SKY2_HW_NEW_LE))
1256 rx_set_checksum(sky2);
14d0263f
SH		 1257
1258 /* Space needed for frame data + headers rounded up */
f957da2a 1259 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
14d0263f
SH		 1260
1261 /* Stopping point for hardware truncation */
1262 thresh = (size - 8) / sizeof(u32);
1263
1264 /* Account for overhead of skb - to avoid order > 0 allocation */
1265 space = SKB_DATA_ALIGN(size) + NET_SKB_PAD
1266 + sizeof(struct skb_shared_info);
1267
1268 sky2->rx_nfrags = space >> PAGE_SHIFT;
1269 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1270
1271 if (sky2->rx_nfrags != 0) {
1272 /* Compute residue after pages */
1273 space = sky2->rx_nfrags << PAGE_SHIFT;
1274
1275 if (space < size)
1276 size -= space;
1277 else
1278 size = 0;
1279
1280 /* Optimize to handle small packets and headers */
1281 if (size < copybreak)
1282 size = copybreak;
1283 if (size < ETH_HLEN)
1284 size = ETH_HLEN;
1285 }
1286 sky2->rx_data_size = size;
1287
1288 /* Fill Rx ring */
793b883e 1289 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1290 re = sky2->rx_ring + i;
cd28ab6a 1291
14d0263f 1292 re->skb = sky2_rx_alloc(sky2);
cd28ab6a
SH		 1293 if (!re->skb)
1294 goto nomem;
1295
14d0263f
SH		 1296 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1297 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1298 }
1299
a1433ac4
SH		 1300 /*
1301 * The receiver hangs if it receives frames larger than the
1302 * packet buffer. As a workaround, truncate oversize frames, but
1303 * the register is limited to 9 bits, so if you do frames > 2052
1304 * you better get the MTU right!
1305 */
a1433ac4
SH		 1306 if (thresh > 0x1ff)
1307 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1308 else {
1309 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1310 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1311 }
1312
6b1a3aef 1313 /* Tell chip about available buffers */
55c9dd35 1314 sky2_rx_update(sky2, rxq);
cd28ab6a
SH		 1315 return 0;
1316nomem:
1317 sky2_rx_clean(sky2);
1318 return -ENOMEM;
1319}
1320
1321/* Bring up network interface. */
1322static int sky2_up(struct net_device *dev)
1323{
1324 struct sky2_port *sky2 = netdev_priv(dev);
1325 struct sky2_hw *hw = sky2->hw;
1326 unsigned port = sky2->port;
e0c28116 1327 u32 imask, ramsize;
ee7abb04 1328 int cap, err = -ENOMEM;
843a46f4 1329 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1330
ee7abb04
SH		 1331 /*
1332 * On dual port PCI-X card, there is an problem where status
1333 * can be received out of order due to split transactions
843a46f4 1334 */
ee7abb04
SH		 1335 if (otherdev && netif_running(otherdev) &&
1336 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
ee7abb04
SH		 1337 u16 cmd;
1338
b32f40c4 1339 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
ee7abb04 1340 cmd &= ~PCI_X_CMD_MAX_SPLIT;
b32f40c4
SH		 1341 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1342
ee7abb04 1343 }
843a46f4 1344
cd28ab6a
SH		 1345 if (netif_msg_ifup(sky2))
1346 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1347
55d7b4e6
SH		 1348 netif_carrier_off(dev);
1349
cd28ab6a
SH		 1350 /* must be power of 2 */
1351 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 1352 TX_RING_SIZE *
1353 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 1354 &sky2->tx_le_map);
1355 if (!sky2->tx_le)
1356 goto err_out;
1357
6cdbbdf3 1358 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 1359 GFP_KERNEL);
1360 if (!sky2->tx_ring)
1361 goto err_out;
88f5f0ca
SH		 1362
1363 tx_init(sky2);
cd28ab6a
SH		 1364
1365 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1366 &sky2->rx_le_map);
1367 if (!sky2->rx_le)
1368 goto err_out;
1369 memset(sky2->rx_le, 0, RX_LE_BYTES);
1370
291ea614 1371 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
cd28ab6a
SH		 1372 GFP_KERNEL);
1373 if (!sky2->rx_ring)
1374 goto err_out;
1375
d3bcfbeb
SH		 1376 sky2_phy_power(hw, port, 1);
1377
cd28ab6a
SH		 1378 sky2_mac_init(hw, port);
1379
e0c28116
SH		 1380 /* Register is number of 4K blocks on internal RAM buffer. */
1381 ramsize = sky2_read8(hw, B2_E_0) * 4;
1382 if (ramsize > 0) {
67712901 1383 u32 rxspace;
cd28ab6a 1384
e0c28116 1385 pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
67712901
SH		 1386 if (ramsize < 16)
1387 rxspace = ramsize / 2;
1388 else
1389 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1390
67712901
SH		 1391 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1392 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1393
1394 /* Make sure SyncQ is disabled */
1395 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1396 RB_RST_SET);
1397 }
793b883e 1398
af4ed7e6 1399 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1400
69161611
SH		 1401 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1402 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1403 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1404
977bdf06 1405 /* Set almost empty threshold */
c2716fb4
SH		 1406 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1407 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
b628ed98 1408 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
5a5b1ea0 1409
6b1a3aef
SH		 1410 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1411 TX_RING_SIZE - 1);
cd28ab6a 1412
6b1a3aef 1413 err = sky2_rx_start(sky2);
6de16237 1414 if (err)
cd28ab6a
SH		 1415 goto err_out;
1416
cd28ab6a 1417 /* Enable interrupts from phy/mac for port */
e07b1aa8 1418 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1419 imask |= portirq_msk[port];
e07b1aa8
SH		 1420 sky2_write32(hw, B0_IMSK, imask);
1421
cd28ab6a
SH		 1422 return 0;
1423
1424err_out:
1b537565 1425 if (sky2->rx_le) {
cd28ab6a
SH		 1426 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1427 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1428 sky2->rx_le = NULL;
1429 }
1430 if (sky2->tx_le) {
cd28ab6a
SH		 1431 pci_free_consistent(hw->pdev,
1432 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1433 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1434 sky2->tx_le = NULL;
1435 }
1436 kfree(sky2->tx_ring);
1437 kfree(sky2->rx_ring);
cd28ab6a 1438
1b537565
SH		 1439 sky2->tx_ring = NULL;
1440 sky2->rx_ring = NULL;
cd28ab6a
SH		 1441 return err;
1442}
1443
793b883e
SH		 1444/* Modular subtraction in ring */
1445static inline int tx_dist(unsigned tail, unsigned head)
1446{
cb5d9547 1447 return (head - tail) & (TX_RING_SIZE - 1);
793b883e 1448}
cd28ab6a 1449
793b883e
SH		 1450/* Number of list elements available for next tx */
1451static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1452{
793b883e 1453 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1454}
1455
793b883e 1456/* Estimate of number of transmit list elements required */
28bd181a 1457static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1458{
793b883e
SH		 1459 unsigned count;
1460
1461 count = sizeof(dma_addr_t) / sizeof(u32);
1462 count += skb_shinfo(skb)->nr_frags * count;
1463
89114afd 1464 if (skb_is_gso(skb))
793b883e
SH		 1465 ++count;
1466
84fa7933 1467 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1468 ++count;
1469
1470 return count;
cd28ab6a
SH		 1471}
1472
793b883e
SH		 1473/*
1474 * Put one packet in ring for transmit.
1475 * A single packet can generate multiple list elements, and
1476 * the number of ring elements will probably be less than the number
1477 * of list elements used.
1478 */
cd28ab6a
SH		 1479static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1480{
1481 struct sky2_port *sky2 = netdev_priv(dev);
1482 struct sky2_hw *hw = sky2->hw;
d1f13708 1483 struct sky2_tx_le *le = NULL;
6cdbbdf3 1484 struct tx_ring_info *re;
cd28ab6a
SH		 1485 unsigned i, len;
1486 dma_addr_t mapping;
cd28ab6a
SH		 1487 u16 mss;
1488 u8 ctrl;
1489
2bb8c262
SH		 1490 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1491 return NETDEV_TX_BUSY;
cd28ab6a 1492
793b883e 1493 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 1494 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1495 dev->name, sky2->tx_prod, skb->len);
1496
cd28ab6a
SH		 1497 len = skb_headlen(skb);
1498 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
793b883e 1499
86c6887e
SH		 1500 /* Send high bits if needed */
1501 if (sizeof(dma_addr_t) > sizeof(u32)) {
793b883e 1502 le = get_tx_le(sky2);
86c6887e 1503 le->addr = cpu_to_le32(upper_32_bits(mapping));
793b883e 1504 le->opcode = OP_ADDR64 | HW_OWNER;
793b883e 1505 }
cd28ab6a
SH		 1506
1507 /* Check for TCP Segmentation Offload */
7967168c 1508 mss = skb_shinfo(skb)->gso_size;
793b883e 1509 if (mss != 0) {
ea76e635
SH		 1510
1511 if (!(hw->flags & SKY2_HW_NEW_LE))
69161611
SH		 1512 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1513
1514 if (mss != sky2->tx_last_mss) {
1515 le = get_tx_le(sky2);
1516 le->addr = cpu_to_le32(mss);
ea76e635
SH		 1517
1518 if (hw->flags & SKY2_HW_NEW_LE)
69161611
SH		 1519 le->opcode = OP_MSS | HW_OWNER;
1520 else
1521 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd
SH		 1522 sky2->tx_last_mss = mss;
1523 }
cd28ab6a
SH		 1524 }
1525
cd28ab6a 1526 ctrl = 0;
d1f13708
SH		 1527#ifdef SKY2_VLAN_TAG_USED
1528 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1529 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1530 if (!le) {
1531 le = get_tx_le(sky2);
f65b138c 1532 le->addr = 0;
d1f13708 1533 le->opcode = OP_VLAN|HW_OWNER;
d1f13708
SH		 1534 } else
1535 le->opcode |= OP_VLAN;
1536 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1537 ctrl |= INS_VLAN;
1538 }
1539#endif
1540
1541 /* Handle TCP checksum offload */
84fa7933 1542 if (skb->ip_summed == CHECKSUM_PARTIAL) {
69161611 1543 /* On Yukon EX (some versions) encoding change. */
ea76e635 1544 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
69161611
SH		 1545 ctrl |= CALSUM; /* auto checksum */
1546 else {
1547 const unsigned offset = skb_transport_offset(skb);
1548 u32 tcpsum;
1549
1550 tcpsum = offset << 16; /* sum start */
1551 tcpsum |= offset + skb->csum_offset; /* sum write */
1552
1553 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1554 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1555 ctrl |= UDPTCP;
1556
1557 if (tcpsum != sky2->tx_tcpsum) {
1558 sky2->tx_tcpsum = tcpsum;
1559
1560 le = get_tx_le(sky2);
1561 le->addr = cpu_to_le32(tcpsum);
1562 le->length = 0; /* initial checksum value */
1563 le->ctrl = 1; /* one packet */
1564 le->opcode = OP_TCPLISW | HW_OWNER;
1565 }
1d179332 1566 }
cd28ab6a
SH		 1567 }
1568
1569 le = get_tx_le(sky2);
f65b138c 1570 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1571 le->length = cpu_to_le16(len);
1572 le->ctrl = ctrl;
793b883e 1573 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1574
291ea614 1575 re = tx_le_re(sky2, le);
cd28ab6a 1576 re->skb = skb;
6cdbbdf3 1577 pci_unmap_addr_set(re, mapaddr, mapping);
291ea614 1578 pci_unmap_len_set(re, maplen, len);
cd28ab6a
SH		 1579
1580 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1581 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1582
1583 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1584 frag->size, PCI_DMA_TODEVICE);
86c6887e
SH		 1585
1586 if (sizeof(dma_addr_t) > sizeof(u32)) {
793b883e 1587 le = get_tx_le(sky2);
86c6887e 1588 le->addr = cpu_to_le32(upper_32_bits(mapping));
793b883e
SH		 1589 le->ctrl = 0;
1590 le->opcode = OP_ADDR64 | HW_OWNER;
cd28ab6a
SH		 1591 }
1592
1593 le = get_tx_le(sky2);
f65b138c 1594 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1595 le->length = cpu_to_le16(frag->size);
1596 le->ctrl = ctrl;
793b883e 1597 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1598
291ea614
SH		 1599 re = tx_le_re(sky2, le);
1600 re->skb = skb;
1601 pci_unmap_addr_set(re, mapaddr, mapping);
1602 pci_unmap_len_set(re, maplen, frag->size);
cd28ab6a 1603 }
6cdbbdf3 1604
cd28ab6a
SH		 1605 le->ctrl |= EOP;
1606
97bda706
SH		 1607 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1608 netif_stop_queue(dev);
b19666d9 1609
290d4de5 1610 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1611
cd28ab6a
SH		 1612 dev->trans_start = jiffies;
1613 return NETDEV_TX_OK;
1614}
1615
cd28ab6a 1616/*
793b883e
SH		 1617 * Free ring elements from starting at tx_cons until "done"
1618 *
1619 * NB: the hardware will tell us about partial completion of multi-part
291ea614 1620 * buffers so make sure not to free skb to early.
cd28ab6a 1621 */
d11c13e7 1622static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1623{
d11c13e7 1624 struct net_device *dev = sky2->netdev;
af2a58ac 1625 struct pci_dev *pdev = sky2->hw->pdev;
291ea614 1626 unsigned idx;
cd28ab6a 1627
0e3ff6aa 1628 BUG_ON(done >= TX_RING_SIZE);
2224795d 1629
291ea614
SH		 1630 for (idx = sky2->tx_cons; idx != done;
1631 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1632 struct sky2_tx_le *le = sky2->tx_le + idx;
1633 struct tx_ring_info *re = sky2->tx_ring + idx;
1634
1635 switch(le->opcode & ~HW_OWNER) {
1636 case OP_LARGESEND:
1637 case OP_PACKET:
1638 pci_unmap_single(pdev,
1639 pci_unmap_addr(re, mapaddr),
1640 pci_unmap_len(re, maplen),
1641 PCI_DMA_TODEVICE);
af2a58ac 1642 break;
291ea614
SH		 1643 case OP_BUFFER:
1644 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1645 pci_unmap_len(re, maplen),
734d1868 1646 PCI_DMA_TODEVICE);
291ea614
SH		 1647 break;
1648 }
1649
1650 if (le->ctrl & EOP) {
1651 if (unlikely(netif_msg_tx_done(sky2)))
1652 printk(KERN_DEBUG "%s: tx done %u\n",
1653 dev->name, idx);
3cf26753 1654
7138a0f5
SH		 1655 dev->stats.tx_packets++;
1656 dev->stats.tx_bytes += re->skb->len;
2bf56fe2 1657
794b2bd2 1658 dev_kfree_skb_any(re->skb);
3cf26753 1659 sky2->tx_next = RING_NEXT(idx, TX_RING_SIZE);
cd28ab6a 1660 }
793b883e 1661 }
793b883e 1662
291ea614 1663 sky2->tx_cons = idx;
50432cb5
SH		 1664 smp_mb();
1665
22e11703 1666 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
cd28ab6a 1667 netif_wake_queue(dev);
cd28ab6a
SH		 1668}
1669
1670/* Cleanup all untransmitted buffers, assume transmitter not running */
2bb8c262 1671static void sky2_tx_clean(struct net_device *dev)
cd28ab6a 1672{
2bb8c262
SH		 1673 struct sky2_port *sky2 = netdev_priv(dev);
1674
1675 netif_tx_lock_bh(dev);
d11c13e7 1676 sky2_tx_complete(sky2, sky2->tx_prod);
2bb8c262 1677 netif_tx_unlock_bh(dev);
cd28ab6a
SH		 1678}
1679
1680/* Network shutdown */
1681static int sky2_down(struct net_device *dev)
1682{
1683 struct sky2_port *sky2 = netdev_priv(dev);
1684 struct sky2_hw *hw = sky2->hw;
1685 unsigned port = sky2->port;
1686 u16 ctrl;
e07b1aa8 1687 u32 imask;
cd28ab6a 1688
1b537565
SH		 1689 /* Never really got started! */
1690 if (!sky2->tx_le)
1691 return 0;
1692
cd28ab6a
SH		 1693 if (netif_msg_ifdown(sky2))
1694 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1695
018d1c66 1696 /* Stop more packets from being queued */
cd28ab6a
SH		 1697 netif_stop_queue(dev);
1698
ebc646f6
SH		 1699 /* Disable port IRQ */
1700 imask = sky2_read32(hw, B0_IMSK);
1701 imask &= ~portirq_msk[port];
1702 sky2_write32(hw, B0_IMSK, imask);
1703
6de16237
SH		 1704 synchronize_irq(hw->pdev->irq);
1705
d3bcfbeb 1706 sky2_gmac_reset(hw, port);
793b883e 1707
cd28ab6a
SH		 1708 /* Stop transmitter */
1709 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1710 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1711
1712 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1713 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1714
1715 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1716 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1717 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1718
6de16237
SH		 1719 /* Make sure no packets are pending */
1720 napi_synchronize(&hw->napi);
1721
cd28ab6a
SH		 1722 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1723
1724 /* Workaround shared GMAC reset */
793b883e
SH		 1725 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1726 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1727 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1728
1729 /* Disable Force Sync bit and Enable Alloc bit */
1730 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1731 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1732
1733 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1734 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1735 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1736
1737 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1738 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1739 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1740
1741 /* Reset the Tx prefetch units */
1742 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1743 PREF_UNIT_RST_SET);
1744
1745 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1746
6b1a3aef 1747 sky2_rx_stop(sky2);
cd28ab6a
SH		 1748
1749 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1750 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1751
d3bcfbeb
SH		 1752 sky2_phy_power(hw, port, 0);
1753
55d7b4e6
SH		 1754 netif_carrier_off(dev);
1755
d571b694 1756 /* turn off LED's */
cd28ab6a
SH		 1757 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1758
2bb8c262 1759 sky2_tx_clean(dev);
cd28ab6a
SH		 1760 sky2_rx_clean(sky2);
1761
1762 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1763 sky2->rx_le, sky2->rx_le_map);
1764 kfree(sky2->rx_ring);
1765
1766 pci_free_consistent(hw->pdev,
1767 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1768 sky2->tx_le, sky2->tx_le_map);
1769 kfree(sky2->tx_ring);
1770
1b537565
SH		 1771 sky2->tx_le = NULL;
1772 sky2->rx_le = NULL;
1773
1774 sky2->rx_ring = NULL;
1775 sky2->tx_ring = NULL;
1776
cd28ab6a
SH		 1777 return 0;
1778}
1779
1780static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1781{
ea76e635 1782 if (hw->flags & SKY2_HW_FIBRE_PHY)
793b883e
SH		 1783 return SPEED_1000;
1784
05745c4a
SH		 1785 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1786 if (aux & PHY_M_PS_SPEED_100)
1787 return SPEED_100;
1788 else
1789 return SPEED_10;
1790 }
cd28ab6a
SH		 1791
1792 switch (aux & PHY_M_PS_SPEED_MSK) {
1793 case PHY_M_PS_SPEED_1000:
1794 return SPEED_1000;
1795 case PHY_M_PS_SPEED_100:
1796 return SPEED_100;
1797 default:
1798 return SPEED_10;
1799 }
1800}
1801
1802static void sky2_link_up(struct sky2_port *sky2)
1803{
1804 struct sky2_hw *hw = sky2->hw;
1805 unsigned port = sky2->port;
1806 u16 reg;
16ad91e1
SH		 1807 static const char *fc_name[] = {
1808 [FC_NONE] = "none",
1809 [FC_TX] = "tx",
1810 [FC_RX] = "rx",
1811 [FC_BOTH] = "both",
1812 };
cd28ab6a 1813
cd28ab6a 1814 /* enable Rx/Tx */
2eaba1a2 1815 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 1816 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1817 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 1818
1819 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1820
1821 netif_carrier_on(sky2->netdev);
cd28ab6a 1822
75e80683 1823 mod_timer(&hw->watchdog_timer, jiffies + 1);
32c2c300 1824
cd28ab6a 1825 /* Turn on link LED */
793b883e 1826 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1827 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1828
1829 if (netif_msg_link(sky2))
1830 printk(KERN_INFO PFX
d571b694 1831 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1832 sky2->netdev->name, sky2->speed,
1833 sky2->duplex == DUPLEX_FULL ? "full" : "half",
16ad91e1 1834 fc_name[sky2->flow_status]);
cd28ab6a
SH		 1835}
1836
1837static void sky2_link_down(struct sky2_port *sky2)
1838{
1839 struct sky2_hw *hw = sky2->hw;
1840 unsigned port = sky2->port;
1841 u16 reg;
1842
1843 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1844
1845 reg = gma_read16(hw, port, GM_GP_CTRL);
1846 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1847 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 1848
cd28ab6a 1849 netif_carrier_off(sky2->netdev);
cd28ab6a
SH		 1850
1851 /* Turn on link LED */
1852 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1853
1854 if (netif_msg_link(sky2))
1855 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2eaba1a2 1856
cd28ab6a
SH		 1857 sky2_phy_init(hw, port);
1858}
1859
16ad91e1
SH		 1860static enum flow_control sky2_flow(int rx, int tx)
1861{
1862 if (rx)
1863 return tx ? FC_BOTH : FC_RX;
1864 else
1865 return tx ? FC_TX : FC_NONE;
1866}
1867
793b883e
SH		 1868static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1869{
1870 struct sky2_hw *hw = sky2->hw;
1871 unsigned port = sky2->port;
da4c1ff4 1872 u16 advert, lpa;
793b883e 1873
da4c1ff4 1874 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
793b883e 1875 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
793b883e
SH		 1876 if (lpa & PHY_M_AN_RF) {
1877 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1878 return -1;
1879 }
1880
793b883e
SH		 1881 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1882 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1883 sky2->netdev->name);
1884 return -1;
1885 }
1886
793b883e 1887 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 1888 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e 1889
da4c1ff4
SH		 1890 /* Since the pause result bits seem to in different positions on
1891 * different chips. look at registers.
1892 */
ea76e635 1893 if (hw->flags & SKY2_HW_FIBRE_PHY) {
da4c1ff4
SH		 1894 /* Shift for bits in fiber PHY */
1895 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
1896 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
1897
1898 if (advert & ADVERTISE_1000XPAUSE)
1899 advert |= ADVERTISE_PAUSE_CAP;
1900 if (advert & ADVERTISE_1000XPSE_ASYM)
1901 advert |= ADVERTISE_PAUSE_ASYM;
1902 if (lpa & LPA_1000XPAUSE)
1903 lpa |= LPA_PAUSE_CAP;
1904 if (lpa & LPA_1000XPAUSE_ASYM)
1905 lpa |= LPA_PAUSE_ASYM;
1906 }
793b883e 1907
da4c1ff4
SH		 1908 sky2->flow_status = FC_NONE;
1909 if (advert & ADVERTISE_PAUSE_CAP) {
1910 if (lpa & LPA_PAUSE_CAP)
1911 sky2->flow_status = FC_BOTH;
1912 else if (advert & ADVERTISE_PAUSE_ASYM)
1913 sky2->flow_status = FC_RX;
1914 } else if (advert & ADVERTISE_PAUSE_ASYM) {
1915 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
1916 sky2->flow_status = FC_TX;
1917 }
793b883e 1918
16ad91e1 1919 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
93745494 1920 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
16ad91e1 1921 sky2->flow_status = FC_NONE;
2eaba1a2 1922
da4c1ff4 1923 if (sky2->flow_status & FC_TX)
793b883e
SH		 1924 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1925 else
1926 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1927
1928 return 0;
1929}
cd28ab6a 1930
e07b1aa8
SH		 1931/* Interrupt from PHY */
1932static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 1933{
e07b1aa8
SH		 1934 struct net_device *dev = hw->dev[port];
1935 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 1936 u16 istatus, phystat;
1937
ebc646f6
SH		 1938 if (!netif_running(dev))
1939 return;
1940
e07b1aa8
SH		 1941 spin_lock(&sky2->phy_lock);
1942 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1943 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1944
cd28ab6a
SH		 1945 if (netif_msg_intr(sky2))
1946 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1947 sky2->netdev->name, istatus, phystat);
1948
2eaba1a2 1949 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
793b883e
SH		 1950 if (sky2_autoneg_done(sky2, phystat) == 0)
1951 sky2_link_up(sky2);
1952 goto out;
1953 }
cd28ab6a 1954
793b883e
SH		 1955 if (istatus & PHY_M_IS_LSP_CHANGE)
1956 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 1957
793b883e
SH		 1958 if (istatus & PHY_M_IS_DUP_CHANGE)
1959 sky2->duplex =
1960 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 1961
793b883e
SH		 1962 if (istatus & PHY_M_IS_LST_CHANGE) {
1963 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 1964 sky2_link_up(sky2);
793b883e
SH		 1965 else
1966 sky2_link_down(sky2);
cd28ab6a 1967 }
793b883e 1968out:
e07b1aa8 1969 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 1970}
1971
62335ab0 1972/* Transmit timeout is only called if we are running, carrier is up
302d1252
SH		 1973 * and tx queue is full (stopped).
1974 */
cd28ab6a
SH		 1975static void sky2_tx_timeout(struct net_device *dev)
1976{
1977 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3 1978 struct sky2_hw *hw = sky2->hw;
cd28ab6a
SH		 1979
1980 if (netif_msg_timer(sky2))
1981 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1982
8f24664d 1983 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
62335ab0
SH		 1984 dev->name, sky2->tx_cons, sky2->tx_prod,
1985 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
1986 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
8f24664d 1987
81906791
SH		 1988 /* can't restart safely under softirq */
1989 schedule_work(&hw->restart_work);
cd28ab6a
SH		 1990}
1991
1992static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1993{
6b1a3aef
SH		 1994 struct sky2_port *sky2 = netdev_priv(dev);
1995 struct sky2_hw *hw = sky2->hw;
b628ed98 1996 unsigned port = sky2->port;
6b1a3aef
SH		 1997 int err;
1998 u16 ctl, mode;
e07b1aa8 1999 u32 imask;
cd28ab6a
SH		 2000
2001 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2002 return -EINVAL;
2003
05745c4a
SH		 2004 if (new_mtu > ETH_DATA_LEN &&
2005 (hw->chip_id == CHIP_ID_YUKON_FE ||
2006 hw->chip_id == CHIP_ID_YUKON_FE_P))
d2adf4f6
SH		 2007 return -EINVAL;
2008
6b1a3aef
SH		 2009 if (!netif_running(dev)) {
2010 dev->mtu = new_mtu;
2011 return 0;
2012 }
2013
e07b1aa8 2014 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef
SH		 2015 sky2_write32(hw, B0_IMSK, 0);
2016
018d1c66
SH		 2017 dev->trans_start = jiffies; /* prevent tx timeout */
2018 netif_stop_queue(dev);
bea3348e 2019 napi_disable(&hw->napi);
018d1c66 2020
e07b1aa8
SH		 2021 synchronize_irq(hw->pdev->irq);
2022
e0c28116 2023 if (sky2_read8(hw, B2_E_0) == 0)
69161611 2024 sky2_set_tx_stfwd(hw, port);
b628ed98
SH		 2025
2026 ctl = gma_read16(hw, port, GM_GP_CTRL);
2027 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
6b1a3aef
SH		 2028 sky2_rx_stop(sky2);
2029 sky2_rx_clean(sky2);
cd28ab6a
SH		 2030
2031 dev->mtu = new_mtu;
14d0263f 2032
6b1a3aef
SH		 2033 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2034 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2035
2036 if (dev->mtu > ETH_DATA_LEN)
2037 mode |= GM_SMOD_JUMBO_ENA;
2038
b628ed98 2039 gma_write16(hw, port, GM_SERIAL_MODE, mode);
cd28ab6a 2040
b628ed98 2041 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 2042
6b1a3aef 2043 err = sky2_rx_start(sky2);
e07b1aa8 2044 sky2_write32(hw, B0_IMSK, imask);
018d1c66 2045
d1d08d12 2046 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e
SH		 2047 napi_enable(&hw->napi);
2048
1b537565
SH		 2049 if (err)
2050 dev_close(dev);
2051 else {
b628ed98 2052 gma_write16(hw, port, GM_GP_CTRL, ctl);
1b537565 2053
1b537565
SH		 2054 netif_wake_queue(dev);
2055 }
2056
cd28ab6a
SH		 2057 return err;
2058}
2059
14d0263f
SH		 2060/* For small just reuse existing skb for next receive */
2061static struct sk_buff *receive_copy(struct sky2_port *sky2,
2062 const struct rx_ring_info *re,
2063 unsigned length)
2064{
2065 struct sk_buff *skb;
2066
2067 skb = netdev_alloc_skb(sky2->netdev, length + 2);
2068 if (likely(skb)) {
2069 skb_reserve(skb, 2);
2070 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2071 length, PCI_DMA_FROMDEVICE);
d626f62b 2072 skb_copy_from_linear_data(re->skb, skb->data, length);
14d0263f
SH		 2073 skb->ip_summed = re->skb->ip_summed;
2074 skb->csum = re->skb->csum;
2075 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2076 length, PCI_DMA_FROMDEVICE);
2077 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 2078 skb_put(skb, length);
14d0263f
SH		 2079 }
2080 return skb;
2081}
2082
2083/* Adjust length of skb with fragments to match received data */
2084static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2085 unsigned int length)
2086{
2087 int i, num_frags;
2088 unsigned int size;
2089
2090 /* put header into skb */
2091 size = min(length, hdr_space);
2092 skb->tail += size;
2093 skb->len += size;
2094 length -= size;
2095
2096 num_frags = skb_shinfo(skb)->nr_frags;
2097 for (i = 0; i < num_frags; i++) {
2098 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2099
2100 if (length == 0) {
2101 /* don't need this page */
2102 __free_page(frag->page);
2103 --skb_shinfo(skb)->nr_frags;
2104 } else {
2105 size = min(length, (unsigned) PAGE_SIZE);
2106
2107 frag->size = size;
2108 skb->data_len += size;
2109 skb->truesize += size;
2110 skb->len += size;
2111 length -= size;
2112 }
2113 }
2114}
2115
2116/* Normal packet - take skb from ring element and put in a new one */
2117static struct sk_buff *receive_new(struct sky2_port *sky2,
2118 struct rx_ring_info *re,
2119 unsigned int length)
2120{
2121 struct sk_buff *skb, *nskb;
2122 unsigned hdr_space = sky2->rx_data_size;
2123
14d0263f
SH		 2124 /* Don't be tricky about reusing pages (yet) */
2125 nskb = sky2_rx_alloc(sky2);
2126 if (unlikely(!nskb))
2127 return NULL;
2128
2129 skb = re->skb;
2130 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2131
2132 prefetch(skb->data);
2133 re->skb = nskb;
2134 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
2135
2136 if (skb_shinfo(skb)->nr_frags)
2137 skb_put_frags(skb, hdr_space, length);
2138 else
489b10c1 2139 skb_put(skb, length);
14d0263f
SH		 2140 return skb;
2141}
2142
cd28ab6a
SH		 2143/*
2144 * Receive one packet.
d571b694 2145 * For larger packets, get new buffer.
cd28ab6a 2146 */
497d7c86 2147static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 2148 u16 length, u32 status)
2149{
497d7c86 2150 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 2151 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 2152 struct sk_buff *skb = NULL;
d6532232
SH		 2153 u16 count = (status & GMR_FS_LEN) >> 16;
2154
2155#ifdef SKY2_VLAN_TAG_USED
2156 /* Account for vlan tag */
2157 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2158 count -= VLAN_HLEN;
2159#endif
cd28ab6a
SH		 2160
2161 if (unlikely(netif_msg_rx_status(sky2)))
2162 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
497d7c86 2163 dev->name, sky2->rx_next, status, length);
cd28ab6a 2164
793b883e 2165 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 2166 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 2167
3b12e014
SH		 2168 /* This chip has hardware problems that generates bogus status.
2169 * So do only marginal checking and expect higher level protocols
2170 * to handle crap frames.
2171 */
2172 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2173 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2174 length != count)
2175 goto okay;
2176
42eeea01 2177 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 2178 goto error;
2179
42eeea01
SH		 2180 if (!(status & GMR_FS_RX_OK))
2181 goto resubmit;
2182
d6532232
SH		 2183 /* if length reported by DMA does not match PHY, packet was truncated */
2184 if (length != count)
3b12e014 2185 goto len_error;
71749531 2186
3b12e014 2187okay:
14d0263f
SH		 2188 if (length < copybreak)
2189 skb = receive_copy(sky2, re, length);
2190 else
2191 skb = receive_new(sky2, re, length);
793b883e 2192resubmit:
14d0263f 2193 sky2_rx_submit(sky2, re);
79e57d32 2194
cd28ab6a
SH		 2195 return skb;
2196
3b12e014 2197len_error:
71749531
SH		 2198 /* Truncation of overlength packets
2199 causes PHY length to not match MAC length */
7138a0f5 2200 ++dev->stats.rx_length_errors;
d6532232 2201 if (netif_msg_rx_err(sky2) && net_ratelimit())
3b12e014
SH		 2202 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2203 dev->name, status, length);
d6532232 2204 goto resubmit;
71749531 2205
cd28ab6a 2206error:
7138a0f5 2207 ++dev->stats.rx_errors;
b6d77734 2208 if (status & GMR_FS_RX_FF_OV) {
7138a0f5 2209 dev->stats.rx_over_errors++;
b6d77734
SH		 2210 goto resubmit;
2211 }
6e15b712 2212
3be92a70 2213 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a 2214 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
497d7c86 2215 dev->name, status, length);
793b883e
SH		 2216
2217 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
7138a0f5 2218 dev->stats.rx_length_errors++;
cd28ab6a 2219 if (status & GMR_FS_FRAGMENT)
7138a0f5 2220 dev->stats.rx_frame_errors++;
cd28ab6a 2221 if (status & GMR_FS_CRC_ERR)
7138a0f5 2222 dev->stats.rx_crc_errors++;
79e57d32 2223
793b883e 2224 goto resubmit;
cd28ab6a
SH		 2225}
2226
e07b1aa8
SH		 2227/* Transmit complete */
2228static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2229{
e07b1aa8 2230 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2231
e07b1aa8 2232 if (netif_running(dev)) {
2bb8c262 2233 netif_tx_lock(dev);
e07b1aa8 2234 sky2_tx_complete(sky2, last);
2bb8c262 2235 netif_tx_unlock(dev);
2224795d 2236 }
cd28ab6a
SH		 2237}
2238
e07b1aa8 2239/* Process status response ring */
26691830 2240static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
cd28ab6a 2241{
e07b1aa8 2242 int work_done = 0;
55c9dd35 2243 unsigned rx[2] = { 0, 0 };
a8fd6266 2244
af2a58ac 2245 rmb();
26691830 2246 do {
55c9dd35 2247 struct sky2_port *sky2;
13210ce5 2248 struct sky2_status_le *le = hw->st_le + hw->st_idx;
ab5adecb 2249 unsigned port;
13210ce5 2250 struct net_device *dev;
cd28ab6a 2251 struct sk_buff *skb;
cd28ab6a
SH		 2252 u32 status;
2253 u16 length;
ab5adecb
SH		 2254 u8 opcode = le->opcode;
2255
2256 if (!(opcode & HW_OWNER))
2257 break;
cd28ab6a 2258
cb5d9547 2259 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 2260
ab5adecb 2261 port = le->css & CSS_LINK_BIT;
69161611 2262 dev = hw->dev[port];
13210ce5 2263 sky2 = netdev_priv(dev);
f65b138c
SH		 2264 length = le16_to_cpu(le->length);
2265 status = le32_to_cpu(le->status);
cd28ab6a 2266
ab5adecb
SH		 2267 le->opcode = 0;
2268 switch (opcode & ~HW_OWNER) {
cd28ab6a 2269 case OP_RXSTAT:
55c9dd35 2270 ++rx[port];
497d7c86 2271 skb = sky2_receive(dev, length, status);
3225b919 2272 if (unlikely(!skb)) {
7138a0f5 2273 dev->stats.rx_dropped++;
55c9dd35 2274 break;
3225b919 2275 }
13210ce5 2276
69161611 2277 /* This chip reports checksum status differently */
05745c4a 2278 if (hw->flags & SKY2_HW_NEW_LE) {
69161611
SH		 2279 if (sky2->rx_csum &&
2280 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2281 (le->css & CSS_TCPUDPCSOK))
2282 skb->ip_summed = CHECKSUM_UNNECESSARY;
2283 else
2284 skb->ip_summed = CHECKSUM_NONE;
2285 }
2286
13210ce5 2287 skb->protocol = eth_type_trans(skb, dev);
7138a0f5
SH		 2288 dev->stats.rx_packets++;
2289 dev->stats.rx_bytes += skb->len;
13210ce5
SH		 2290 dev->last_rx = jiffies;
2291
d1f13708
SH		 2292#ifdef SKY2_VLAN_TAG_USED
2293 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2294 vlan_hwaccel_receive_skb(skb,
2295 sky2->vlgrp,
2296 be16_to_cpu(sky2->rx_tag));
2297 } else
2298#endif
cd28ab6a 2299 netif_receive_skb(skb);
13210ce5 2300
22e11703 2301 /* Stop after net poll weight */
13210ce5
SH		 2302 if (++work_done >= to_do)
2303 goto exit_loop;
cd28ab6a
SH		 2304 break;
2305
d1f13708
SH		 2306#ifdef SKY2_VLAN_TAG_USED
2307 case OP_RXVLAN:
2308 sky2->rx_tag = length;
2309 break;
2310
2311 case OP_RXCHKSVLAN:
2312 sky2->rx_tag = length;
2313 /* fall through */
2314#endif
cd28ab6a 2315 case OP_RXCHKS:
87418307
SH		 2316 if (!sky2->rx_csum)
2317 break;
2318
05745c4a
SH		 2319 /* If this happens then driver assuming wrong format */
2320 if (unlikely(hw->flags & SKY2_HW_NEW_LE)) {
2321 if (net_ratelimit())
2322 printk(KERN_NOTICE "%s: unexpected"
2323 " checksum status\n",
2324 dev->name);
69161611 2325 break;
05745c4a 2326 }
69161611 2327
87418307
SH		 2328 /* Both checksum counters are programmed to start at
2329 * the same offset, so unless there is a problem they
2330 * should match. This failure is an early indication that
2331 * hardware receive checksumming won't work.
2332 */
2333 if (likely(status >> 16 == (status & 0xffff))) {
2334 skb = sky2->rx_ring[sky2->rx_next].skb;
2335 skb->ip_summed = CHECKSUM_COMPLETE;
2336 skb->csum = status & 0xffff;
2337 } else {
2338 printk(KERN_NOTICE PFX "%s: hardware receive "
2339 "checksum problem (status = %#x)\n",
2340 dev->name, status);
2341 sky2->rx_csum = 0;
2342 sky2_write32(sky2->hw,
69161611 2343 Q_ADDR(rxqaddr[port], Q_CSR),
87418307
SH		 2344 BMU_DIS_RX_CHKSUM);
2345 }
cd28ab6a
SH		 2346 break;
2347
2348 case OP_TXINDEXLE:
13b97b74 2349 /* TX index reports status for both ports */
f55925d7
SH		 2350 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2351 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2352 if (hw->dev[1])
2353 sky2_tx_done(hw->dev[1],
2354 ((status >> 24) & 0xff)
2355 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2356 break;
2357
cd28ab6a
SH		 2358 default:
2359 if (net_ratelimit())
793b883e 2360 printk(KERN_WARNING PFX
ab5adecb 2361 "unknown status opcode 0x%x\n", opcode);
cd28ab6a 2362 }
26691830 2363 } while (hw->st_idx != idx);
cd28ab6a 2364
fe2a24df
SH		 2365 /* Fully processed status ring so clear irq */
2366 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2367
13210ce5 2368exit_loop:
55c9dd35
SH		 2369 if (rx[0])
2370 sky2_rx_update(netdev_priv(hw->dev[0]), Q_R1);
22e11703 2371
55c9dd35
SH		 2372 if (rx[1])
2373 sky2_rx_update(netdev_priv(hw->dev[1]), Q_R2);
22e11703 2374
e07b1aa8 2375 return work_done;
cd28ab6a
SH		 2376}
2377
2378static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2379{
2380 struct net_device *dev = hw->dev[port];
2381
3be92a70
SH		 2382 if (net_ratelimit())
2383 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2384 dev->name, status);
cd28ab6a
SH		 2385
2386 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2387 if (net_ratelimit())
2388 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2389 dev->name);
cd28ab6a
SH		 2390 /* Clear IRQ */
2391 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2392 }
2393
2394 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2395 if (net_ratelimit())
2396 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2397 dev->name);
cd28ab6a
SH		 2398
2399 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2400 }
2401
2402 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2403 if (net_ratelimit())
2404 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2405 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2406 }
2407
2408 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2409 if (net_ratelimit())
2410 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2411 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2412 }
2413
2414 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2415 if (net_ratelimit())
2416 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2417 dev->name);
cd28ab6a
SH		 2418 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2419 }
2420}
2421
2422static void sky2_hw_intr(struct sky2_hw *hw)
2423{
555382cb 2424 struct pci_dev *pdev = hw->pdev;
cd28ab6a 2425 u32 status = sky2_read32(hw, B0_HWE_ISRC);
555382cb
SH		 2426 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2427
2428 status &= hwmsk;
cd28ab6a 2429
793b883e 2430 if (status & Y2_IS_TIST_OV)
cd28ab6a 2431 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2432
2433 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2434 u16 pci_err;
2435
b32f40c4 2436 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70 2437 if (net_ratelimit())
555382cb 2438 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
b02a9258 2439 pci_err);
cd28ab6a 2440
b32f40c4 2441 sky2_pci_write16(hw, PCI_STATUS,
167f53d0 2442 pci_err | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 2443 }
2444
2445 if (status & Y2_IS_PCI_EXP) {
d571b694 2446 /* PCI-Express uncorrectable Error occurred */
555382cb 2447 u32 err;
cd28ab6a 2448
7782c8c4
SH		 2449 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2450 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2451 0xfffffffful);
3be92a70 2452 if (net_ratelimit())
555382cb 2453 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
cf06ffb4 2454
7782c8c4 2455 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
cd28ab6a
SH		 2456 }
2457
2458 if (status & Y2_HWE_L1_MASK)
2459 sky2_hw_error(hw, 0, status);
2460 status >>= 8;
2461 if (status & Y2_HWE_L1_MASK)
2462 sky2_hw_error(hw, 1, status);
2463}
2464
2465static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2466{
2467 struct net_device *dev = hw->dev[port];
2468 struct sky2_port *sky2 = netdev_priv(dev);
2469 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2470
2471 if (netif_msg_intr(sky2))
2472 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2473 dev->name, status);
2474
a3caeada
SH		 2475 if (status & GM_IS_RX_CO_OV)
2476 gma_read16(hw, port, GM_RX_IRQ_SRC);
2477
2478 if (status & GM_IS_TX_CO_OV)
2479 gma_read16(hw, port, GM_TX_IRQ_SRC);
2480
cd28ab6a 2481 if (status & GM_IS_RX_FF_OR) {
7138a0f5 2482 ++dev->stats.rx_fifo_errors;
cd28ab6a
SH		 2483 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2484 }
2485
2486 if (status & GM_IS_TX_FF_UR) {
7138a0f5 2487 ++dev->stats.tx_fifo_errors;
cd28ab6a
SH		 2488 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2489 }
cd28ab6a
SH		 2490}
2491
40b01727
SH		 2492/* This should never happen it is a bug. */
2493static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2494 u16 q, unsigned ring_size)
d257924e
SH		 2495{
2496 struct net_device *dev = hw->dev[port];
2497 struct sky2_port *sky2 = netdev_priv(dev);
40b01727
SH		 2498 unsigned idx;
2499 const u64 *le = (q == Q_R1 || q == Q_R2)
2500 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
d257924e 2501
40b01727
SH		 2502 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2503 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2504 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2505 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
d257924e 2506
40b01727 2507 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
d257924e 2508}
cd28ab6a 2509
75e80683
SH		 2510static int sky2_rx_hung(struct net_device *dev)
2511{
2512 struct sky2_port *sky2 = netdev_priv(dev);
2513 struct sky2_hw *hw = sky2->hw;
2514 unsigned port = sky2->port;
2515 unsigned rxq = rxqaddr[port];
2516 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2517 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2518 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2519 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2520
2521 /* If idle and MAC or PCI is stuck */
2522 if (sky2->check.last == dev->last_rx &&
2523 ((mac_rp == sky2->check.mac_rp &&
2524 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2525 /* Check if the PCI RX hang */
2526 (fifo_rp == sky2->check.fifo_rp &&
2527 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2528 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2529 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2530 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2531 return 1;
2532 } else {
2533 sky2->check.last = dev->last_rx;
2534 sky2->check.mac_rp = mac_rp;
2535 sky2->check.mac_lev = mac_lev;
2536 sky2->check.fifo_rp = fifo_rp;
2537 sky2->check.fifo_lev = fifo_lev;
2538 return 0;
2539 }
2540}
2541
32c2c300 2542static void sky2_watchdog(unsigned long arg)
d27ed387 2543{
01bd7564 2544 struct sky2_hw *hw = (struct sky2_hw *) arg;
d27ed387 2545
75e80683 2546 /* Check for lost IRQ once a second */
32c2c300 2547 if (sky2_read32(hw, B0_ISRC)) {
bea3348e 2548 napi_schedule(&hw->napi);
75e80683
SH		 2549 } else {
2550 int i, active = 0;
2551
2552 for (i = 0; i < hw->ports; i++) {
bea3348e 2553 struct net_device *dev = hw->dev[i];
75e80683
SH		 2554 if (!netif_running(dev))
2555 continue;
2556 ++active;
2557
2558 /* For chips with Rx FIFO, check if stuck */
e0c28116 2559 if ((hw->flags & SKY2_HW_FIFO_HANG_CHECK) &&
75e80683
SH		 2560 sky2_rx_hung(dev)) {
2561 pr_info(PFX "%s: receiver hang detected\n",
2562 dev->name);
2563 schedule_work(&hw->restart_work);
2564 return;
2565 }
2566 }
2567
2568 if (active == 0)
2569 return;
32c2c300 2570 }
01bd7564 2571
75e80683 2572 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
d27ed387
SH		 2573}
2574
40b01727
SH		 2575/* Hardware/software error handling */
2576static void sky2_err_intr(struct sky2_hw *hw, u32 status)
cd28ab6a 2577{
40b01727
SH		 2578 if (net_ratelimit())
2579 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
cd28ab6a 2580
1e5f1283
SH		 2581 if (status & Y2_IS_HW_ERR)
2582 sky2_hw_intr(hw);
d257924e 2583
1e5f1283
SH		 2584 if (status & Y2_IS_IRQ_MAC1)
2585 sky2_mac_intr(hw, 0);
cd28ab6a 2586
1e5f1283
SH		 2587 if (status & Y2_IS_IRQ_MAC2)
2588 sky2_mac_intr(hw, 1);
cd28ab6a 2589
1e5f1283 2590 if (status & Y2_IS_CHK_RX1)
40b01727 2591 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
d257924e 2592
1e5f1283 2593 if (status & Y2_IS_CHK_RX2)
40b01727 2594 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
d257924e 2595
1e5f1283 2596 if (status & Y2_IS_CHK_TXA1)
40b01727 2597 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
d257924e 2598
1e5f1283 2599 if (status & Y2_IS_CHK_TXA2)
40b01727
SH		 2600 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2601}
2602
bea3348e 2603static int sky2_poll(struct napi_struct *napi, int work_limit)
40b01727 2604{
bea3348e 2605 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
40b01727 2606 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
6f535763 2607 int work_done = 0;
26691830 2608 u16 idx;
40b01727
SH		 2609
2610 if (unlikely(status & Y2_IS_ERROR))
2611 sky2_err_intr(hw, status);
2612
2613 if (status & Y2_IS_IRQ_PHY1)
2614 sky2_phy_intr(hw, 0);
2615
2616 if (status & Y2_IS_IRQ_PHY2)
2617 sky2_phy_intr(hw, 1);
cd28ab6a 2618
26691830
SH		 2619 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2620 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
6f535763
DM		 2621
2622 if (work_done >= work_limit)
26691830
SH		 2623 goto done;
2624 }
6f535763 2625
26691830
SH		 2626 /* Bug/Errata workaround?
2627 * Need to kick the TX irq moderation timer.
2628 */
2629 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_START) {
2630 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2631 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
fe2a24df 2632 }
26691830
SH		 2633 napi_complete(napi);
2634 sky2_read32(hw, B0_Y2_SP_LISR);
2635done:
6f535763 2636
bea3348e 2637 return work_done;
e07b1aa8
SH		 2638}
2639
7d12e780 2640static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2641{
2642 struct sky2_hw *hw = dev_id;
e07b1aa8
SH		 2643 u32 status;
2644
2645 /* Reading this mask interrupts as side effect */
2646 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2647 if (status == 0 || status == ~0)
2648 return IRQ_NONE;
793b883e 2649
e07b1aa8 2650 prefetch(&hw->st_le[hw->st_idx]);
bea3348e
SH		 2651
2652 napi_schedule(&hw->napi);
793b883e 2653
cd28ab6a
SH		 2654 return IRQ_HANDLED;
2655}
2656
2657#ifdef CONFIG_NET_POLL_CONTROLLER
2658static void sky2_netpoll(struct net_device *dev)
2659{
2660 struct sky2_port *sky2 = netdev_priv(dev);
2661
bea3348e 2662 napi_schedule(&sky2->hw->napi);
cd28ab6a
SH		 2663}
2664#endif
2665
2666/* Chip internal frequency for clock calculations */
05745c4a 2667static u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2668{
793b883e 2669 switch (hw->chip_id) {
cd28ab6a 2670 case CHIP_ID_YUKON_EC:
5a5b1ea0 2671 case CHIP_ID_YUKON_EC_U:
93745494 2672 case CHIP_ID_YUKON_EX:
05745c4a
SH		 2673 return 125;
2674
cd28ab6a 2675 case CHIP_ID_YUKON_FE:
05745c4a
SH		 2676 return 100;
2677
2678 case CHIP_ID_YUKON_FE_P:
2679 return 50;
2680
2681 case CHIP_ID_YUKON_XL:
2682 return 156;
2683
2684 default:
2685 BUG();
cd28ab6a
SH		 2686 }
2687}
2688
fb17358f 2689static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2690{
fb17358f 2691 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2692}
2693
fb17358f 2694static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2695{
fb17358f 2696 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2697}
2698
fb17358f 2699
e3173832 2700static int __devinit sky2_init(struct sky2_hw *hw)
cd28ab6a 2701{
b89165f2 2702 u8 t8;
cd28ab6a 2703
167f53d0 2704 /* Enable all clocks and check for bad PCI access */
b32f40c4 2705 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
451af335 2706
cd28ab6a 2707 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2708
cd28ab6a 2709 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
ea76e635
SH		 2710 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2711
2712 switch(hw->chip_id) {
2713 case CHIP_ID_YUKON_XL:
2714 hw->flags = SKY2_HW_GIGABIT
e0c28116
SH		 2715 | SKY2_HW_NEWER_PHY;
2716 if (hw->chip_rev < 3)
2717 hw->flags |= SKY2_HW_FIFO_HANG_CHECK;
2718
ea76e635
SH		 2719 break;
2720
2721 case CHIP_ID_YUKON_EC_U:
2722 hw->flags = SKY2_HW_GIGABIT
2723 | SKY2_HW_NEWER_PHY
2724 | SKY2_HW_ADV_POWER_CTL;
2725 break;
2726
2727 case CHIP_ID_YUKON_EX:
2728 hw->flags = SKY2_HW_GIGABIT
2729 | SKY2_HW_NEWER_PHY
2730 | SKY2_HW_NEW_LE
2731 | SKY2_HW_ADV_POWER_CTL;
2732
2733 /* New transmit checksum */
2734 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2735 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2736 break;
2737
2738 case CHIP_ID_YUKON_EC:
2739 /* This rev is really old, and requires untested workarounds */
2740 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2741 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2742 return -EOPNOTSUPP;
2743 }
e0c28116 2744 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_FIFO_HANG_CHECK;
ea76e635
SH		 2745 break;
2746
2747 case CHIP_ID_YUKON_FE:
ea76e635
SH		 2748 break;
2749
05745c4a
SH		 2750 case CHIP_ID_YUKON_FE_P:
2751 hw->flags = SKY2_HW_NEWER_PHY
2752 | SKY2_HW_NEW_LE
2753 | SKY2_HW_AUTO_TX_SUM
2754 | SKY2_HW_ADV_POWER_CTL;
2755 break;
ea76e635 2756 default:
b02a9258
SH		 2757 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2758 hw->chip_id);
cd28ab6a
SH		 2759 return -EOPNOTSUPP;
2760 }
2761
ea76e635
SH		 2762 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2763 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
2764 hw->flags |= SKY2_HW_FIBRE_PHY;
290d4de5 2765
290d4de5 2766
e3173832
SH		 2767 hw->ports = 1;
2768 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2769 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2770 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2771 ++hw->ports;
2772 }
2773
2774 return 0;
2775}
2776
2777static void sky2_reset(struct sky2_hw *hw)
2778{
555382cb 2779 struct pci_dev *pdev = hw->pdev;
e3173832 2780 u16 status;
555382cb
SH		 2781 int i, cap;
2782 u32 hwe_mask = Y2_HWE_ALL_MASK;
e3173832 2783
cd28ab6a 2784 /* disable ASF */
4f44d8ba
SH		 2785 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2786 status = sky2_read16(hw, HCU_CCSR);
2787 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2788 HCU_CCSR_UC_STATE_MSK);
2789 sky2_write16(hw, HCU_CCSR, status);
2790 } else
2791 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2792 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
cd28ab6a
SH		 2793
2794 /* do a SW reset */
2795 sky2_write8(hw, B0_CTST, CS_RST_SET);
2796 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2797
ac93a394
SH		 2798 /* allow writes to PCI config */
2799 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2800
cd28ab6a 2801 /* clear PCI errors, if any */
b32f40c4 2802 status = sky2_pci_read16(hw, PCI_STATUS);
167f53d0 2803 status |= PCI_STATUS_ERROR_BITS;
b32f40c4 2804 sky2_pci_write16(hw, PCI_STATUS, status);
cd28ab6a
SH		 2805
2806 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2807
555382cb
SH		 2808 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2809 if (cap) {
7782c8c4
SH		 2810 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2811 0xfffffffful);
555382cb
SH		 2812
2813 /* If error bit is stuck on ignore it */
2814 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
2815 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
7782c8c4 2816 else
555382cb
SH		 2817 hwe_mask |= Y2_IS_PCI_EXP;
2818 }
cd28ab6a 2819
ae306cca 2820 sky2_power_on(hw);
cd28ab6a
SH		 2821
2822 for (i = 0; i < hw->ports; i++) {
2823 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2824 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
69161611
SH		 2825
2826 if (hw->chip_id == CHIP_ID_YUKON_EX)
2827 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
2828 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
2829 | GMC_BYP_RETR_ON);
cd28ab6a
SH		 2830 }
2831
793b883e
SH		 2832 /* Clear I2C IRQ noise */
2833 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2834
2835 /* turn off hardware timer (unused) */
2836 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2837 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2838
cd28ab6a
SH		 2839 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2840
69634ee7
SH		 2841 /* Turn off descriptor polling */
2842 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2843
2844 /* Turn off receive timestamp */
2845 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2846 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2847
2848 /* enable the Tx Arbiters */
2849 for (i = 0; i < hw->ports; i++)
2850 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2851
2852 /* Initialize ram interface */
2853 for (i = 0; i < hw->ports; i++) {
793b883e 2854 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2855
2856 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2857 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2858 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2859 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2860 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2861 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2862 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2863 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2864 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2865 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2866 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2867 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2868 }
2869
555382cb 2870 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
cd28ab6a 2871
cd28ab6a 2872 for (i = 0; i < hw->ports; i++)
d3bcfbeb 2873 sky2_gmac_reset(hw, i);
cd28ab6a 2874
cd28ab6a
SH		 2875 memset(hw->st_le, 0, STATUS_LE_BYTES);
2876 hw->st_idx = 0;
2877
2878 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2879 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2880
2881 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 2882 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 2883
2884 /* Set the list last index */
793b883e 2885 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 2886
290d4de5
SH		 2887 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2888 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 2889
290d4de5
SH		 2890 /* set Status-FIFO ISR watermark */
2891 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2892 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2893 else
2894 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 2895
290d4de5 2896 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 2897 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2898 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 2899
793b883e 2900 /* enable status unit */
cd28ab6a
SH		 2901 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2902
2903 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2904 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2905 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
e3173832
SH		 2906}
2907
81906791
SH		 2908static void sky2_restart(struct work_struct *work)
2909{
2910 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
2911 struct net_device *dev;
2912 int i, err;
2913
81906791 2914 rtnl_lock();
81906791
SH		 2915 for (i = 0; i < hw->ports; i++) {
2916 dev = hw->dev[i];
2917 if (netif_running(dev))
2918 sky2_down(dev);
2919 }
2920
8cfcbe99
SH		 2921 napi_disable(&hw->napi);
2922 sky2_write32(hw, B0_IMSK, 0);
81906791
SH		 2923 sky2_reset(hw);
2924 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 2925 napi_enable(&hw->napi);
81906791
SH		 2926
2927 for (i = 0; i < hw->ports; i++) {
2928 dev = hw->dev[i];
2929 if (netif_running(dev)) {
2930 err = sky2_up(dev);
2931 if (err) {
2932 printk(KERN_INFO PFX "%s: could not restart %d\n",
2933 dev->name, err);
2934 dev_close(dev);
2935 }
2936 }
2937 }
2938
81906791
SH		 2939 rtnl_unlock();
2940}
2941
e3173832
SH		 2942static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
2943{
2944 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
2945}
2946
2947static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2948{
2949 const struct sky2_port *sky2 = netdev_priv(dev);
2950
2951 wol->supported = sky2_wol_supported(sky2->hw);
2952 wol->wolopts = sky2->wol;
2953}
2954
2955static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2956{
2957 struct sky2_port *sky2 = netdev_priv(dev);
2958 struct sky2_hw *hw = sky2->hw;
cd28ab6a 2959
e3173832
SH		 2960 if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
2961 return -EOPNOTSUPP;
2962
2963 sky2->wol = wol->wolopts;
2964
05745c4a
SH		 2965 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
2966 hw->chip_id == CHIP_ID_YUKON_EX ||
2967 hw->chip_id == CHIP_ID_YUKON_FE_P)
e3173832
SH		 2968 sky2_write32(hw, B0_CTST, sky2->wol
2969 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
2970
2971 if (!netif_running(dev))
2972 sky2_wol_init(sky2);
cd28ab6a
SH		 2973 return 0;
2974}
2975
28bd181a 2976static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 2977{
b89165f2
SH		 2978 if (sky2_is_copper(hw)) {
2979 u32 modes = SUPPORTED_10baseT_Half
2980 | SUPPORTED_10baseT_Full
2981 | SUPPORTED_100baseT_Half
2982 | SUPPORTED_100baseT_Full
2983 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 2984
ea76e635 2985 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a 2986 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 2987 | SUPPORTED_1000baseT_Full;
2988 return modes;
cd28ab6a 2989 } else
b89165f2
SH		 2990 return SUPPORTED_1000baseT_Half
2991 | SUPPORTED_1000baseT_Full
2992 | SUPPORTED_Autoneg
2993 | SUPPORTED_FIBRE;
cd28ab6a
SH		 2994}
2995
793b883e 2996static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 2997{
2998 struct sky2_port *sky2 = netdev_priv(dev);
2999 struct sky2_hw *hw = sky2->hw;
3000
3001 ecmd->transceiver = XCVR_INTERNAL;
3002 ecmd->supported = sky2_supported_modes(hw);
3003 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 3004 if (sky2_is_copper(hw)) {
cd28ab6a 3005 ecmd->port = PORT_TP;
b89165f2
SH		 3006 ecmd->speed = sky2->speed;
3007 } else {
3008 ecmd->speed = SPEED_1000;
cd28ab6a 3009 ecmd->port = PORT_FIBRE;
b89165f2 3010 }
cd28ab6a
SH		 3011
3012 ecmd->advertising = sky2->advertising;
3013 ecmd->autoneg = sky2->autoneg;
cd28ab6a
SH		 3014 ecmd->duplex = sky2->duplex;
3015 return 0;
3016}
3017
3018static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3019{
3020 struct sky2_port *sky2 = netdev_priv(dev);
3021 const struct sky2_hw *hw = sky2->hw;
3022 u32 supported = sky2_supported_modes(hw);
3023
3024 if (ecmd->autoneg == AUTONEG_ENABLE) {
3025 ecmd->advertising = supported;
3026 sky2->duplex = -1;
3027 sky2->speed = -1;
3028 } else {
3029 u32 setting;
3030
793b883e 3031 switch (ecmd->speed) {
cd28ab6a
SH		 3032 case SPEED_1000:
3033 if (ecmd->duplex == DUPLEX_FULL)
3034 setting = SUPPORTED_1000baseT_Full;
3035 else if (ecmd->duplex == DUPLEX_HALF)
3036 setting = SUPPORTED_1000baseT_Half;
3037 else
3038 return -EINVAL;
3039 break;
3040 case SPEED_100:
3041 if (ecmd->duplex == DUPLEX_FULL)
3042 setting = SUPPORTED_100baseT_Full;
3043 else if (ecmd->duplex == DUPLEX_HALF)
3044 setting = SUPPORTED_100baseT_Half;
3045 else
3046 return -EINVAL;
3047 break;
3048
3049 case SPEED_10:
3050 if (ecmd->duplex == DUPLEX_FULL)
3051 setting = SUPPORTED_10baseT_Full;
3052 else if (ecmd->duplex == DUPLEX_HALF)
3053 setting = SUPPORTED_10baseT_Half;
3054 else
3055 return -EINVAL;
3056 break;
3057 default:
3058 return -EINVAL;
3059 }
3060
3061 if ((setting & supported) == 0)
3062 return -EINVAL;
3063
3064 sky2->speed = ecmd->speed;
3065 sky2->duplex = ecmd->duplex;
3066 }
3067
3068 sky2->autoneg = ecmd->autoneg;
3069 sky2->advertising = ecmd->advertising;
3070
d1b139c0 3071 if (netif_running(dev)) {
1b537565 3072 sky2_phy_reinit(sky2);
d1b139c0
SH		 3073 sky2_set_multicast(dev);
3074 }
cd28ab6a
SH		 3075
3076 return 0;
3077}
3078
3079static void sky2_get_drvinfo(struct net_device *dev,
3080 struct ethtool_drvinfo *info)
3081{
3082 struct sky2_port *sky2 = netdev_priv(dev);
3083
3084 strcpy(info->driver, DRV_NAME);
3085 strcpy(info->version, DRV_VERSION);
3086 strcpy(info->fw_version, "N/A");
3087 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3088}
3089
3090static const struct sky2_stat {
793b883e
SH		 3091 char name[ETH_GSTRING_LEN];
3092 u16 offset;
cd28ab6a
SH		 3093} sky2_stats[] = {
3094 { "tx_bytes", GM_TXO_OK_HI },
3095 { "rx_bytes", GM_RXO_OK_HI },
3096 { "tx_broadcast", GM_TXF_BC_OK },
3097 { "rx_broadcast", GM_RXF_BC_OK },
3098 { "tx_multicast", GM_TXF_MC_OK },
3099 { "rx_multicast", GM_RXF_MC_OK },
3100 { "tx_unicast", GM_TXF_UC_OK },
3101 { "rx_unicast", GM_RXF_UC_OK },
3102 { "tx_mac_pause", GM_TXF_MPAUSE },
3103 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 3104 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 3105 { "late_collision",GM_TXF_LAT_COL },
3106 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 3107 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 3108 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 3109
d2604540 3110 { "rx_short", GM_RXF_SHT },
cd28ab6a 3111 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 3112 { "rx_64_byte_packets", GM_RXF_64B },
3113 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3114 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3115 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3116 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3117 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3118 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 3119 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 3120 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3121 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 3122 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 3123
3124 { "tx_64_byte_packets", GM_TXF_64B },
3125 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3126 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3127 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3128 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3129 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3130 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3131 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 3132};
3133
cd28ab6a
SH		 3134static u32 sky2_get_rx_csum(struct net_device *dev)
3135{
3136 struct sky2_port *sky2 = netdev_priv(dev);
3137
3138 return sky2->rx_csum;
3139}
3140
3141static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3142{
3143 struct sky2_port *sky2 = netdev_priv(dev);
3144
3145 sky2->rx_csum = data;
793b883e 3146
cd28ab6a
SH		 3147 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3148 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3149
3150 return 0;
3151}
3152
3153static u32 sky2_get_msglevel(struct net_device *netdev)
3154{
3155 struct sky2_port *sky2 = netdev_priv(netdev);
3156 return sky2->msg_enable;
3157}
3158
9a7ae0a9
SH		 3159static int sky2_nway_reset(struct net_device *dev)
3160{
3161 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 3162
16ad91e1 3163 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
9a7ae0a9
SH		 3164 return -EINVAL;
3165
1b537565 3166 sky2_phy_reinit(sky2);
d1b139c0 3167 sky2_set_multicast(dev);
9a7ae0a9
SH		 3168
3169 return 0;
3170}
3171
793b883e 3172static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 3173{
3174 struct sky2_hw *hw = sky2->hw;
3175 unsigned port = sky2->port;
3176 int i;
3177
3178 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 3179 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 3180 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 3181 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 3182
793b883e 3183 for (i = 2; i < count; i++)
cd28ab6a
SH		 3184 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3185}
3186
cd28ab6a
SH		 3187static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3188{
3189 struct sky2_port *sky2 = netdev_priv(netdev);
3190 sky2->msg_enable = value;
3191}
3192
b9f2c044 3193static int sky2_get_sset_count(struct net_device *dev, int sset)
cd28ab6a 3194{
b9f2c044
JG		 3195 switch (sset) {
3196 case ETH_SS_STATS:
3197 return ARRAY_SIZE(sky2_stats);
3198 default:
3199 return -EOPNOTSUPP;
3200 }
cd28ab6a
SH		 3201}
3202
3203static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 3204 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 3205{
3206 struct sky2_port *sky2 = netdev_priv(dev);
3207
793b883e 3208 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 3209}
3210
793b883e 3211static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 3212{
3213 int i;
3214
3215 switch (stringset) {
3216 case ETH_SS_STATS:
3217 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3218 memcpy(data + i * ETH_GSTRING_LEN,
3219 sky2_stats[i].name, ETH_GSTRING_LEN);
3220 break;
3221 }
3222}
3223
cd28ab6a
SH		 3224static int sky2_set_mac_address(struct net_device *dev, void *p)
3225{
3226 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 3227 struct sky2_hw *hw = sky2->hw;
3228 unsigned port = sky2->port;
3229 const struct sockaddr *addr = p;
cd28ab6a
SH		 3230
3231 if (!is_valid_ether_addr(addr->sa_data))
3232 return -EADDRNOTAVAIL;
3233
cd28ab6a 3234 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 3235 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 3236 dev->dev_addr, ETH_ALEN);
a8ab1ec0 3237 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 3238 dev->dev_addr, ETH_ALEN);
1b537565 3239
a8ab1ec0
SH		 3240 /* virtual address for data */
3241 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3242
3243 /* physical address: used for pause frames */
3244 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 3245
3246 return 0;
cd28ab6a
SH		 3247}
3248
a052b52f
SH		 3249static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3250{
3251 u32 bit;
3252
3253 bit = ether_crc(ETH_ALEN, addr) & 63;
3254 filter[bit >> 3] |= 1 << (bit & 7);
3255}
3256
cd28ab6a
SH		 3257static void sky2_set_multicast(struct net_device *dev)
3258{
3259 struct sky2_port *sky2 = netdev_priv(dev);
3260 struct sky2_hw *hw = sky2->hw;
3261 unsigned port = sky2->port;
3262 struct dev_mc_list *list = dev->mc_list;
3263 u16 reg;
3264 u8 filter[8];
a052b52f
SH		 3265 int rx_pause;
3266 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 3267
a052b52f 3268 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 3269 memset(filter, 0, sizeof(filter));
3270
3271 reg = gma_read16(hw, port, GM_RX_CTRL);
3272 reg |= GM_RXCR_UCF_ENA;
3273
d571b694 3274 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 3275 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 3276 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 3277 memset(filter, 0xff, sizeof(filter));
a052b52f 3278 else if (dev->mc_count == 0 && !rx_pause)
cd28ab6a
SH		 3279 reg &= ~GM_RXCR_MCF_ENA;
3280 else {
3281 int i;
3282 reg |= GM_RXCR_MCF_ENA;
3283
a052b52f
SH		 3284 if (rx_pause)
3285 sky2_add_filter(filter, pause_mc_addr);
3286
3287 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3288 sky2_add_filter(filter, list->dmi_addr);
cd28ab6a
SH		 3289 }
3290
cd28ab6a 3291 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 3292 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 3293 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 3294 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 3295 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 3296 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 3297 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 3298 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 3299
3300 gma_write16(hw, port, GM_RX_CTRL, reg);
3301}
3302
3303/* Can have one global because blinking is controlled by
3304 * ethtool and that is always under RTNL mutex
3305 */
91c86df5 3306static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
cd28ab6a 3307{
793b883e
SH		 3308 u16 pg;
3309
793b883e
SH		 3310 switch (hw->chip_id) {
3311 case CHIP_ID_YUKON_XL:
3312 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3313 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3314 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3315 on ? (PHY_M_LEDC_LOS_CTRL(1) |
3316 PHY_M_LEDC_INIT_CTRL(7) |
3317 PHY_M_LEDC_STA1_CTRL(7) |
3318 PHY_M_LEDC_STA0_CTRL(7))
3319 : 0);
3320
3321 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3322 break;
3323
3324 default:
3325 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
0efdf262
SH		 3326 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3327 on ? PHY_M_LED_ALL : 0);
793b883e 3328 }
cd28ab6a
SH		 3329}
3330
3331/* blink LED's for finding board */
3332static int sky2_phys_id(struct net_device *dev, u32 data)
3333{
3334 struct sky2_port *sky2 = netdev_priv(dev);
3335 struct sky2_hw *hw = sky2->hw;
3336 unsigned port = sky2->port;
793b883e 3337 u16 ledctrl, ledover = 0;
cd28ab6a 3338 long ms;
91c86df5 3339 int interrupted;
cd28ab6a
SH		 3340 int onoff = 1;
3341
793b883e 3342 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
cd28ab6a
SH		 3343 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
3344 else
3345 ms = data * 1000;
3346
3347 /* save initial values */
e07b1aa8 3348 spin_lock_bh(&sky2->phy_lock);
793b883e
SH		 3349 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3350 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3351 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3352 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
3353 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3354 } else {
3355 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
3356 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
3357 }
cd28ab6a 3358
91c86df5
SH		 3359 interrupted = 0;
3360 while (!interrupted && ms > 0) {
cd28ab6a
SH		 3361 sky2_led(hw, port, onoff);
3362 onoff = !onoff;
3363
e07b1aa8 3364 spin_unlock_bh(&sky2->phy_lock);
91c86df5 3365 interrupted = msleep_interruptible(250);
e07b1aa8 3366 spin_lock_bh(&sky2->phy_lock);
91c86df5 3367
cd28ab6a
SH		 3368 ms -= 250;
3369 }
3370
3371 /* resume regularly scheduled programming */
793b883e
SH		 3372 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3373 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3374 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3375 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
3376 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3377 } else {
3378 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
3379 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
3380 }
e07b1aa8 3381 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 3382
3383 return 0;
3384}
3385
3386static void sky2_get_pauseparam(struct net_device *dev,
3387 struct ethtool_pauseparam *ecmd)
3388{
3389 struct sky2_port *sky2 = netdev_priv(dev);
3390
16ad91e1
SH		 3391 switch (sky2->flow_mode) {
3392 case FC_NONE:
3393 ecmd->tx_pause = ecmd->rx_pause = 0;
3394 break;
3395 case FC_TX:
3396 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3397 break;
3398 case FC_RX:
3399 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3400 break;
3401 case FC_BOTH:
3402 ecmd->tx_pause = ecmd->rx_pause = 1;
3403 }
3404
cd28ab6a
SH		 3405 ecmd->autoneg = sky2->autoneg;
3406}
3407
3408static int sky2_set_pauseparam(struct net_device *dev,
3409 struct ethtool_pauseparam *ecmd)
3410{
3411 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 3412
3413 sky2->autoneg = ecmd->autoneg;
16ad91e1 3414 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3415
16ad91e1
SH		 3416 if (netif_running(dev))
3417 sky2_phy_reinit(sky2);
cd28ab6a 3418
2eaba1a2 3419 return 0;
cd28ab6a
SH		 3420}
3421
fb17358f
SH		 3422static int sky2_get_coalesce(struct net_device *dev,
3423 struct ethtool_coalesce *ecmd)
3424{
3425 struct sky2_port *sky2 = netdev_priv(dev);
3426 struct sky2_hw *hw = sky2->hw;
3427
3428 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3429 ecmd->tx_coalesce_usecs = 0;
3430 else {
3431 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3432 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3433 }
3434 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3435
3436 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3437 ecmd->rx_coalesce_usecs = 0;
3438 else {
3439 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3440 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3441 }
3442 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3443
3444 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3445 ecmd->rx_coalesce_usecs_irq = 0;
3446 else {
3447 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3448 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3449 }
3450
3451 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3452
3453 return 0;
3454}
3455
3456/* Note: this affect both ports */
3457static int sky2_set_coalesce(struct net_device *dev,
3458 struct ethtool_coalesce *ecmd)
3459{
3460 struct sky2_port *sky2 = netdev_priv(dev);
3461 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3462 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3463
77b3d6a2
SH		 3464 if (ecmd->tx_coalesce_usecs > tmax ||
3465 ecmd->rx_coalesce_usecs > tmax ||
3466 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3467 return -EINVAL;
3468
ff81fbbe 3469 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
fb17358f 3470 return -EINVAL;
ff81fbbe 3471 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3472 return -EINVAL;
ff81fbbe 3473 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 3474 return -EINVAL;
3475
3476 if (ecmd->tx_coalesce_usecs == 0)
3477 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3478 else {
3479 sky2_write32(hw, STAT_TX_TIMER_INI,
3480 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3481 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3482 }
3483 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3484
3485 if (ecmd->rx_coalesce_usecs == 0)
3486 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3487 else {
3488 sky2_write32(hw, STAT_LEV_TIMER_INI,
3489 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3490 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3491 }
3492 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3493
3494 if (ecmd->rx_coalesce_usecs_irq == 0)
3495 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3496 else {
d28d4870 3497 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3498 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3499 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3500 }
3501 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3502 return 0;
3503}
3504
793b883e
SH		 3505static void sky2_get_ringparam(struct net_device *dev,
3506 struct ethtool_ringparam *ering)
3507{
3508 struct sky2_port *sky2 = netdev_priv(dev);
3509
3510 ering->rx_max_pending = RX_MAX_PENDING;
3511 ering->rx_mini_max_pending = 0;
3512 ering->rx_jumbo_max_pending = 0;
3513 ering->tx_max_pending = TX_RING_SIZE - 1;
3514
3515 ering->rx_pending = sky2->rx_pending;
3516 ering->rx_mini_pending = 0;
3517 ering->rx_jumbo_pending = 0;
3518 ering->tx_pending = sky2->tx_pending;
3519}
3520
3521static int sky2_set_ringparam(struct net_device *dev,
3522 struct ethtool_ringparam *ering)
3523{
3524 struct sky2_port *sky2 = netdev_priv(dev);
3525 int err = 0;
3526
3527 if (ering->rx_pending > RX_MAX_PENDING ||
3528 ering->rx_pending < 8 ||
3529 ering->tx_pending < MAX_SKB_TX_LE ||
3530 ering->tx_pending > TX_RING_SIZE - 1)
3531 return -EINVAL;
3532
3533 if (netif_running(dev))
3534 sky2_down(dev);
3535
3536 sky2->rx_pending = ering->rx_pending;
3537 sky2->tx_pending = ering->tx_pending;
3538
1b537565 3539 if (netif_running(dev)) {
793b883e 3540 err = sky2_up(dev);
1b537565
SH		 3541 if (err)
3542 dev_close(dev);
6ed995bb
SH		 3543 else
3544 sky2_set_multicast(dev);
1b537565 3545 }
793b883e
SH		 3546
3547 return err;
3548}
3549
793b883e
SH		 3550static int sky2_get_regs_len(struct net_device *dev)
3551{
6e4cbb34 3552 return 0x4000;
793b883e
SH		 3553}
3554
3555/*
3556 * Returns copy of control register region
3ead5db7 3557 * Note: ethtool_get_regs always provides full size (16k) buffer
793b883e
SH		 3558 */
3559static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3560 void *p)
3561{
3562 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3563 const void __iomem *io = sky2->hw->regs;
295b54c4 3564 unsigned int b;
793b883e
SH		 3565
3566 regs->version = 1;
793b883e 3567
295b54c4
SH		 3568 for (b = 0; b < 128; b++) {
3569 /* This complicated switch statement is to make sure and
3570 * only access regions that are unreserved.
3571 * Some blocks are only valid on dual port cards.
3572 * and block 3 has some special diagnostic registers that
3573 * are poison.
3574 */
3575 switch (b) {
3576 case 3:
3577 /* skip diagnostic ram region */
3578 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
3579 break;
3ead5db7 3580
295b54c4
SH		 3581 /* dual port cards only */
3582 case 5: /* Tx Arbiter 2 */
3583 case 9: /* RX2 */
3584 case 14 ... 15: /* TX2 */
3585 case 17: case 19: /* Ram Buffer 2 */
3586 case 22 ... 23: /* Tx Ram Buffer 2 */
3587 case 25: /* Rx MAC Fifo 1 */
3588 case 27: /* Tx MAC Fifo 2 */
3589 case 31: /* GPHY 2 */
3590 case 40 ... 47: /* Pattern Ram 2 */
3591 case 52: case 54: /* TCP Segmentation 2 */
3592 case 112 ... 116: /* GMAC 2 */
3593 if (sky2->hw->ports == 1)
3594 goto reserved;
3595 /* fall through */
3596 case 0: /* Control */
3597 case 2: /* Mac address */
3598 case 4: /* Tx Arbiter 1 */
3599 case 7: /* PCI express reg */
3600 case 8: /* RX1 */
3601 case 12 ... 13: /* TX1 */
3602 case 16: case 18:/* Rx Ram Buffer 1 */
3603 case 20 ... 21: /* Tx Ram Buffer 1 */
3604 case 24: /* Rx MAC Fifo 1 */
3605 case 26: /* Tx MAC Fifo 1 */
3606 case 28 ... 29: /* Descriptor and status unit */
3607 case 30: /* GPHY 1*/
3608 case 32 ... 39: /* Pattern Ram 1 */
3609 case 48: case 50: /* TCP Segmentation 1 */
3610 case 56 ... 60: /* PCI space */
3611 case 80 ... 84: /* GMAC 1 */
3612 memcpy_fromio(p, io, 128);
3613 break;
3614 default:
3615reserved:
3616 memset(p, 0, 128);
3617 }
3ead5db7 3618
295b54c4
SH		 3619 p += 128;
3620 io += 128;
3621 }
793b883e 3622}
cd28ab6a 3623
b628ed98
SH		 3624/* In order to do Jumbo packets on these chips, need to turn off the
3625 * transmit store/forward. Therefore checksum offload won't work.
3626 */
3627static int no_tx_offload(struct net_device *dev)
3628{
3629 const struct sky2_port *sky2 = netdev_priv(dev);
3630 const struct sky2_hw *hw = sky2->hw;
3631
69161611 3632 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
b628ed98
SH		 3633}
3634
3635static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3636{
3637 if (data && no_tx_offload(dev))
3638 return -EINVAL;
3639
3640 return ethtool_op_set_tx_csum(dev, data);
3641}
3642
3643
3644static int sky2_set_tso(struct net_device *dev, u32 data)
3645{
3646 if (data && no_tx_offload(dev))
3647 return -EINVAL;
3648
3649 return ethtool_op_set_tso(dev, data);
3650}
3651
f4331a6d
SH		 3652static int sky2_get_eeprom_len(struct net_device *dev)
3653{
3654 struct sky2_port *sky2 = netdev_priv(dev);
b32f40c4 3655 struct sky2_hw *hw = sky2->hw;
f4331a6d
SH		 3656 u16 reg2;
3657
b32f40c4 3658 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
f4331a6d
SH		 3659 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3660}
3661
b32f40c4 3662static u32 sky2_vpd_read(struct sky2_hw *hw, int cap, u16 offset)
f4331a6d 3663{
167f53d0 3664 u32 val;
f4331a6d 3665
b32f40c4 3666 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
167f53d0
SH		 3667
3668 do {
b32f40c4 3669 offset = sky2_pci_read16(hw, cap + PCI_VPD_ADDR);
167f53d0
SH		 3670 } while (!(offset & PCI_VPD_ADDR_F));
3671
b32f40c4 3672 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
167f53d0 3673 return val;
f4331a6d
SH		 3674}
3675
b32f40c4 3676static void sky2_vpd_write(struct sky2_hw *hw, int cap, u16 offset, u32 val)
f4331a6d 3677{
b32f40c4
SH		 3678 sky2_pci_write16(hw, cap + PCI_VPD_DATA, val);
3679 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
f4331a6d 3680 do {
b32f40c4 3681 offset = sky2_pci_read16(hw, cap + PCI_VPD_ADDR);
167f53d0 3682 } while (offset & PCI_VPD_ADDR_F);
f4331a6d
SH		 3683}
3684
3685static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3686 u8 *data)
3687{
3688 struct sky2_port *sky2 = netdev_priv(dev);
3689 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3690 int length = eeprom->len;
3691 u16 offset = eeprom->offset;
3692
3693 if (!cap)
3694 return -EINVAL;
3695
3696 eeprom->magic = SKY2_EEPROM_MAGIC;
3697
3698 while (length > 0) {
b32f40c4 3699 u32 val = sky2_vpd_read(sky2->hw, cap, offset);
f4331a6d
SH		 3700 int n = min_t(int, length, sizeof(val));
3701
3702 memcpy(data, &val, n);
3703 length -= n;
3704 data += n;
3705 offset += n;
3706 }
3707 return 0;
3708}
3709
3710static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3711 u8 *data)
3712{
3713 struct sky2_port *sky2 = netdev_priv(dev);
3714 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3715 int length = eeprom->len;
3716 u16 offset = eeprom->offset;
3717
3718 if (!cap)
3719 return -EINVAL;
3720
3721 if (eeprom->magic != SKY2_EEPROM_MAGIC)
3722 return -EINVAL;
3723
3724 while (length > 0) {
3725 u32 val;
3726 int n = min_t(int, length, sizeof(val));
3727
3728 if (n < sizeof(val))
b32f40c4 3729 val = sky2_vpd_read(sky2->hw, cap, offset);
f4331a6d
SH		 3730 memcpy(&val, data, n);
3731
b32f40c4 3732 sky2_vpd_write(sky2->hw, cap, offset, val);
f4331a6d
SH		 3733
3734 length -= n;
3735 data += n;
3736 offset += n;
3737 }
3738 return 0;
3739}
3740
3741
7282d491 3742static const struct ethtool_ops sky2_ethtool_ops = {
f4331a6d
SH		 3743 .get_settings = sky2_get_settings,
3744 .set_settings = sky2_set_settings,
3745 .get_drvinfo = sky2_get_drvinfo,
3746 .get_wol = sky2_get_wol,
3747 .set_wol = sky2_set_wol,
3748 .get_msglevel = sky2_get_msglevel,
3749 .set_msglevel = sky2_set_msglevel,
3750 .nway_reset = sky2_nway_reset,
3751 .get_regs_len = sky2_get_regs_len,
3752 .get_regs = sky2_get_regs,
3753 .get_link = ethtool_op_get_link,
3754 .get_eeprom_len = sky2_get_eeprom_len,
3755 .get_eeprom = sky2_get_eeprom,
3756 .set_eeprom = sky2_set_eeprom,
f4331a6d 3757 .set_sg = ethtool_op_set_sg,
f4331a6d 3758 .set_tx_csum = sky2_set_tx_csum,
f4331a6d
SH		 3759 .set_tso = sky2_set_tso,
3760 .get_rx_csum = sky2_get_rx_csum,
3761 .set_rx_csum = sky2_set_rx_csum,
3762 .get_strings = sky2_get_strings,
3763 .get_coalesce = sky2_get_coalesce,
3764 .set_coalesce = sky2_set_coalesce,
3765 .get_ringparam = sky2_get_ringparam,
3766 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 3767 .get_pauseparam = sky2_get_pauseparam,
3768 .set_pauseparam = sky2_set_pauseparam,
f4331a6d 3769 .phys_id = sky2_phys_id,
b9f2c044 3770 .get_sset_count = sky2_get_sset_count,
cd28ab6a
SH		 3771 .get_ethtool_stats = sky2_get_ethtool_stats,
3772};
3773
3cf26753
SH		 3774#ifdef CONFIG_SKY2_DEBUG
3775
3776static struct dentry *sky2_debug;
3777
3778static int sky2_debug_show(struct seq_file *seq, void *v)
3779{
3780 struct net_device *dev = seq->private;
3781 const struct sky2_port *sky2 = netdev_priv(dev);
bea3348e 3782 struct sky2_hw *hw = sky2->hw;
3cf26753
SH		 3783 unsigned port = sky2->port;
3784 unsigned idx, last;
3785 int sop;
3786
3787 if (!netif_running(dev))
3788 return -ENETDOWN;
3789
3790 seq_printf(seq, "IRQ src=%x mask=%x control=%x\n",
3791 sky2_read32(hw, B0_ISRC),
3792 sky2_read32(hw, B0_IMSK),
3793 sky2_read32(hw, B0_Y2_SP_ICR));
3794
bea3348e 3795 napi_disable(&hw->napi);
3cf26753
SH		 3796 last = sky2_read16(hw, STAT_PUT_IDX);
3797
3798 if (hw->st_idx == last)
3799 seq_puts(seq, "Status ring (empty)\n");
3800 else {
3801 seq_puts(seq, "Status ring\n");
3802 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
3803 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
3804 const struct sky2_status_le *le = hw->st_le + idx;
3805 seq_printf(seq, "[%d] %#x %d %#x\n",
3806 idx, le->opcode, le->length, le->status);
3807 }
3808 seq_puts(seq, "\n");
3809 }
3810
3811 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
3812 sky2->tx_cons, sky2->tx_prod,
3813 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
3814 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
3815
3816 /* Dump contents of tx ring */
3817 sop = 1;
3818 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < TX_RING_SIZE;
3819 idx = RING_NEXT(idx, TX_RING_SIZE)) {
3820 const struct sky2_tx_le *le = sky2->tx_le + idx;
3821 u32 a = le32_to_cpu(le->addr);
3822
3823 if (sop)
3824 seq_printf(seq, "%u:", idx);
3825 sop = 0;
3826
3827 switch(le->opcode & ~HW_OWNER) {
3828 case OP_ADDR64:
3829 seq_printf(seq, " %#x:", a);
3830 break;
3831 case OP_LRGLEN:
3832 seq_printf(seq, " mtu=%d", a);
3833 break;
3834 case OP_VLAN:
3835 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
3836 break;
3837 case OP_TCPLISW:
3838 seq_printf(seq, " csum=%#x", a);
3839 break;
3840 case OP_LARGESEND:
3841 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
3842 break;
3843 case OP_PACKET:
3844 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
3845 break;
3846 case OP_BUFFER:
3847 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
3848 break;
3849 default:
3850 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
3851 a, le16_to_cpu(le->length));
3852 }
3853
3854 if (le->ctrl & EOP) {
3855 seq_putc(seq, '\n');
3856 sop = 1;
3857 }
3858 }
3859
3860 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
3861 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
3862 last = sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
3863 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
3864
d1d08d12 3865 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 3866 napi_enable(&hw->napi);
3cf26753
SH		 3867 return 0;
3868}
3869
3870static int sky2_debug_open(struct inode *inode, struct file *file)
3871{
3872 return single_open(file, sky2_debug_show, inode->i_private);
3873}
3874
3875static const struct file_operations sky2_debug_fops = {
3876 .owner = THIS_MODULE,
3877 .open = sky2_debug_open,
3878 .read = seq_read,
3879 .llseek = seq_lseek,
3880 .release = single_release,
3881};
3882
3883/*
3884 * Use network device events to create/remove/rename
3885 * debugfs file entries
3886 */
3887static int sky2_device_event(struct notifier_block *unused,
3888 unsigned long event, void *ptr)
3889{
3890 struct net_device *dev = ptr;
5b296bc9 3891 struct sky2_port *sky2 = netdev_priv(dev);
3cf26753 3892
5b296bc9
SH		 3893 if (dev->open != sky2_up || !sky2_debug)
3894 return NOTIFY_DONE;
3cf26753 3895
5b296bc9
SH		 3896 switch(event) {
3897 case NETDEV_CHANGENAME:
3898 if (sky2->debugfs) {
3899 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
3900 sky2_debug, dev->name);
3901 }
3902 break;
3cf26753 3903
5b296bc9
SH		 3904 case NETDEV_GOING_DOWN:
3905 if (sky2->debugfs) {
3906 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
3907 dev->name);
3908 debugfs_remove(sky2->debugfs);
3909 sky2->debugfs = NULL;
3cf26753 3910 }
5b296bc9
SH		 3911 break;
3912
3913 case NETDEV_UP:
3914 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
3915 sky2_debug, dev,
3916 &sky2_debug_fops);
3917 if (IS_ERR(sky2->debugfs))
3918 sky2->debugfs = NULL;
3cf26753
SH		 3919 }
3920
3921 return NOTIFY_DONE;
3922}
3923
3924static struct notifier_block sky2_notifier = {
3925 .notifier_call = sky2_device_event,
3926};
3927
3928
3929static __init void sky2_debug_init(void)
3930{
3931 struct dentry *ent;
3932
3933 ent = debugfs_create_dir("sky2", NULL);
3934 if (!ent || IS_ERR(ent))
3935 return;
3936
3937 sky2_debug = ent;
3938 register_netdevice_notifier(&sky2_notifier);
3939}
3940
3941static __exit void sky2_debug_cleanup(void)
3942{
3943 if (sky2_debug) {
3944 unregister_netdevice_notifier(&sky2_notifier);
3945 debugfs_remove(sky2_debug);
3946 sky2_debug = NULL;
3947 }
3948}
3949
3950#else
3951#define sky2_debug_init()
3952#define sky2_debug_cleanup()
3953#endif
3954
3955
cd28ab6a
SH		 3956/* Initialize network device */
3957static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
e3173832 3958 unsigned port,
be63a21c 3959 int highmem, int wol)
cd28ab6a
SH		 3960{
3961 struct sky2_port *sky2;
3962 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3963
3964 if (!dev) {
898eb71c 3965 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
cd28ab6a
SH		 3966 return NULL;
3967 }
3968
cd28ab6a 3969 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 3970 dev->irq = hw->pdev->irq;
cd28ab6a
SH		 3971 dev->open = sky2_up;
3972 dev->stop = sky2_down;
ef743d33 3973 dev->do_ioctl = sky2_ioctl;
cd28ab6a 3974 dev->hard_start_xmit = sky2_xmit_frame;
cd28ab6a
SH		 3975 dev->set_multicast_list = sky2_set_multicast;
3976 dev->set_mac_address = sky2_set_mac_address;
3977 dev->change_mtu = sky2_change_mtu;
3978 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3979 dev->tx_timeout = sky2_tx_timeout;
3980 dev->watchdog_timeo = TX_WATCHDOG;
cd28ab6a 3981#ifdef CONFIG_NET_POLL_CONTROLLER
a5e68c02
SH		 3982 if (port == 0)
3983 dev->poll_controller = sky2_netpoll;
cd28ab6a 3984#endif
cd28ab6a
SH		 3985
3986 sky2 = netdev_priv(dev);
3987 sky2->netdev = dev;
3988 sky2->hw = hw;
3989 sky2->msg_enable = netif_msg_init(debug, default_msg);
3990
cd28ab6a
SH		 3991 /* Auto speed and flow control */
3992 sky2->autoneg = AUTONEG_ENABLE;
16ad91e1
SH		 3993 sky2->flow_mode = FC_BOTH;
3994
cd28ab6a
SH		 3995 sky2->duplex = -1;
3996 sky2->speed = -1;
3997 sky2->advertising = sky2_supported_modes(hw);
8b31cfbc 3998 sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);
be63a21c 3999 sky2->wol = wol;
75d070c5 4000
e07b1aa8 4001 spin_lock_init(&sky2->phy_lock);
793b883e 4002 sky2->tx_pending = TX_DEF_PENDING;
290d4de5 4003 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 4004
4005 hw->dev[port] = dev;
4006
4007 sky2->port = port;
4008
4a50a876 4009 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a
SH		 4010 if (highmem)
4011 dev->features |= NETIF_F_HIGHDMA;
cd28ab6a 4012
d1f13708 4013#ifdef SKY2_VLAN_TAG_USED
d6c9bc1e
SH		 4014 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4015 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4016 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4017 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4018 dev->vlan_rx_register = sky2_vlan_rx_register;
4019 }
d1f13708
SH		 4020#endif
4021
cd28ab6a 4022 /* read the mac address */
793b883e 4023 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 4024 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a 4025
cd28ab6a
SH		 4026 return dev;
4027}
4028
28bd181a 4029static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 4030{
4031 const struct sky2_port *sky2 = netdev_priv(dev);
0795af57 4032 DECLARE_MAC_BUF(mac);
cd28ab6a
SH		 4033
4034 if (netif_msg_probe(sky2))
0795af57
JP		 4035 printk(KERN_INFO PFX "%s: addr %s\n",
4036 dev->name, print_mac(mac, dev->dev_addr));
cd28ab6a
SH		 4037}
4038
fb2690a9 4039/* Handle software interrupt used during MSI test */
7d12e780 4040static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 4041{
4042 struct sky2_hw *hw = dev_id;
4043 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4044
4045 if (status == 0)
4046 return IRQ_NONE;
4047
4048 if (status & Y2_IS_IRQ_SW) {
ea76e635 4049 hw->flags |= SKY2_HW_USE_MSI;
fb2690a9
SH		 4050 wake_up(&hw->msi_wait);
4051 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4052 }
4053 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4054
4055 return IRQ_HANDLED;
4056}
4057
4058/* Test interrupt path by forcing a a software IRQ */
4059static int __devinit sky2_test_msi(struct sky2_hw *hw)
4060{
4061 struct pci_dev *pdev = hw->pdev;
4062 int err;
4063
bb507fe1
SH		 4064 init_waitqueue_head (&hw->msi_wait);
4065
fb2690a9
SH		 4066 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4067
b0a20ded 4068 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9 4069 if (err) {
b02a9258 4070 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
fb2690a9
SH		 4071 return err;
4072 }
4073
fb2690a9 4074 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 4075 sky2_read8(hw, B0_CTST);
fb2690a9 4076
ea76e635 4077 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
fb2690a9 4078
ea76e635 4079 if (!(hw->flags & SKY2_HW_USE_MSI)) {
fb2690a9 4080 /* MSI test failed, go back to INTx mode */
b02a9258
SH		 4081 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4082 "switching to INTx mode.\n");
fb2690a9
SH		 4083
4084 err = -EOPNOTSUPP;
4085 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4086 }
4087
4088 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 4089 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 4090
4091 free_irq(pdev->irq, hw);
4092
4093 return err;
4094}
4095
be63a21c
SH		 4096static int __devinit pci_wake_enabled(struct pci_dev *dev)
4097{
4098 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
4099 u16 value;
4100
4101 if (!pm)
4102 return 0;
4103 if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
4104 return 0;
4105 return value & PCI_PM_CTRL_PME_ENABLE;
4106}
4107
cd28ab6a
SH		 4108static int __devinit sky2_probe(struct pci_dev *pdev,
4109 const struct pci_device_id *ent)
4110{
7f60c64b 4111 struct net_device *dev;
cd28ab6a 4112 struct sky2_hw *hw;
be63a21c 4113 int err, using_dac = 0, wol_default;
cd28ab6a 4114
793b883e
SH		 4115 err = pci_enable_device(pdev);
4116 if (err) {
b02a9258 4117 dev_err(&pdev->dev, "cannot enable PCI device\n");
cd28ab6a
SH		 4118 goto err_out;
4119 }
4120
793b883e
SH		 4121 err = pci_request_regions(pdev, DRV_NAME);
4122 if (err) {
b02a9258 4123 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
44a1d2e5 4124 goto err_out_disable;
cd28ab6a
SH		 4125 }
4126
4127 pci_set_master(pdev);
4128
d1f3d4dd
SH		 4129 if (sizeof(dma_addr_t) > sizeof(u32) &&
4130 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
4131 using_dac = 1;
4132 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
4133 if (err < 0) {
b02a9258
SH		 4134 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4135 "for consistent allocations\n");
d1f3d4dd
SH		 4136 goto err_out_free_regions;
4137 }
d1f3d4dd 4138 } else {
cd28ab6a
SH		 4139 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
4140 if (err) {
b02a9258 4141 dev_err(&pdev->dev, "no usable DMA configuration\n");
cd28ab6a
SH		 4142 goto err_out_free_regions;
4143 }
4144 }
d1f3d4dd 4145
be63a21c
SH		 4146 wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
4147
cd28ab6a 4148 err = -ENOMEM;
6aad85d6 4149 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a 4150 if (!hw) {
b02a9258 4151 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
cd28ab6a
SH		 4152 goto err_out_free_regions;
4153 }
4154
cd28ab6a 4155 hw->pdev = pdev;
cd28ab6a
SH		 4156
4157 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4158 if (!hw->regs) {
b02a9258 4159 dev_err(&pdev->dev, "cannot map device registers\n");
cd28ab6a
SH		 4160 goto err_out_free_hw;
4161 }
4162
56a645cc 4163#ifdef __BIG_ENDIAN
f65b138c
SH		 4164 /* The sk98lin vendor driver uses hardware byte swapping but
4165 * this driver uses software swapping.
4166 */
56a645cc
SH		 4167 {
4168 u32 reg;
b32f40c4 4169 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
f65b138c 4170 reg &= ~PCI_REV_DESC;
b32f40c4 4171 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
56a645cc
SH		 4172 }
4173#endif
4174
08c06d8a 4175 /* ring for status responses */
167f53d0 4176 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
08c06d8a
SH		 4177 if (!hw->st_le)
4178 goto err_out_iounmap;
4179
e3173832 4180 err = sky2_init(hw);
cd28ab6a 4181 if (err)
793b883e 4182 goto err_out_iounmap;
cd28ab6a 4183
b02a9258 4184 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
7c7459d1
GKH		 4185 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
4186 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
793b883e 4187 hw->chip_id, hw->chip_rev);
cd28ab6a 4188
e3173832
SH		 4189 sky2_reset(hw);
4190
be63a21c 4191 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
7f60c64b 4192 if (!dev) {
4193 err = -ENOMEM;
cd28ab6a 4194 goto err_out_free_pci;
7f60c64b 4195 }
cd28ab6a 4196
9fa1b1f3
SH		 4197 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4198 err = sky2_test_msi(hw);
4199 if (err == -EOPNOTSUPP)
4200 pci_disable_msi(pdev);
4201 else if (err)
4202 goto err_out_free_netdev;
4203 }
4204
793b883e
SH		 4205 err = register_netdev(dev);
4206 if (err) {
b02a9258 4207 dev_err(&pdev->dev, "cannot register net device\n");
cd28ab6a
SH		 4208 goto err_out_free_netdev;
4209 }
4210
6de16237
SH		 4211 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4212
ea76e635
SH		 4213 err = request_irq(pdev->irq, sky2_intr,
4214 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
b0a20ded 4215 dev->name, hw);
9fa1b1f3 4216 if (err) {
b02a9258 4217 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
9fa1b1f3
SH		 4218 goto err_out_unregister;
4219 }
4220 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4221 napi_enable(&hw->napi);
9fa1b1f3 4222
cd28ab6a
SH		 4223 sky2_show_addr(dev);
4224
7f60c64b 4225 if (hw->ports > 1) {
4226 struct net_device *dev1;
4227
be63a21c 4228 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
b02a9258
SH		 4229 if (!dev1)
4230 dev_warn(&pdev->dev, "allocation for second device failed\n");
4231 else if ((err = register_netdev(dev1))) {
4232 dev_warn(&pdev->dev,
4233 "register of second port failed (%d)\n", err);
cd28ab6a
SH		 4234 hw->dev[1] = NULL;
4235 free_netdev(dev1);
b02a9258
SH		 4236 } else
4237 sky2_show_addr(dev1);
cd28ab6a
SH		 4238 }
4239
32c2c300 4240 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
81906791
SH		 4241 INIT_WORK(&hw->restart_work, sky2_restart);
4242
793b883e
SH		 4243 pci_set_drvdata(pdev, hw);
4244
cd28ab6a
SH		 4245 return 0;
4246
793b883e 4247err_out_unregister:
ea76e635 4248 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4249 pci_disable_msi(pdev);
793b883e 4250 unregister_netdev(dev);
cd28ab6a
SH		 4251err_out_free_netdev:
4252 free_netdev(dev);
cd28ab6a 4253err_out_free_pci:
793b883e 4254 sky2_write8(hw, B0_CTST, CS_RST_SET);
167f53d0 4255 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4256err_out_iounmap:
4257 iounmap(hw->regs);
4258err_out_free_hw:
4259 kfree(hw);
4260err_out_free_regions:
4261 pci_release_regions(pdev);
44a1d2e5 4262err_out_disable:
cd28ab6a 4263 pci_disable_device(pdev);
cd28ab6a 4264err_out:
549a68c3 4265 pci_set_drvdata(pdev, NULL);
cd28ab6a
SH		 4266 return err;
4267}
4268
4269static void __devexit sky2_remove(struct pci_dev *pdev)
4270{
793b883e 4271 struct sky2_hw *hw = pci_get_drvdata(pdev);
6de16237 4272 int i;
cd28ab6a 4273
793b883e 4274 if (!hw)
cd28ab6a
SH		 4275 return;
4276
32c2c300 4277 del_timer_sync(&hw->watchdog_timer);
6de16237 4278 cancel_work_sync(&hw->restart_work);
d27ed387 4279
b877fe28 4280 for (i = hw->ports-1; i >= 0; --i)
6de16237 4281 unregister_netdev(hw->dev[i]);
81906791 4282
d27ed387 4283 sky2_write32(hw, B0_IMSK, 0);
cd28ab6a 4284
ae306cca
SH		 4285 sky2_power_aux(hw);
4286
cd28ab6a 4287 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 4288 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 4289 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 4290
4291 free_irq(pdev->irq, hw);
ea76e635 4292 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4293 pci_disable_msi(pdev);
793b883e 4294 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4295 pci_release_regions(pdev);
4296 pci_disable_device(pdev);
793b883e 4297
b877fe28 4298 for (i = hw->ports-1; i >= 0; --i)
6de16237
SH		 4299 free_netdev(hw->dev[i]);
4300
cd28ab6a
SH		 4301 iounmap(hw->regs);
4302 kfree(hw);
5afa0a9c 4303
cd28ab6a
SH		 4304 pci_set_drvdata(pdev, NULL);
4305}
4306
4307#ifdef CONFIG_PM
4308static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4309{
793b883e 4310 struct sky2_hw *hw = pci_get_drvdata(pdev);
e3173832 4311 int i, wol = 0;
cd28ab6a 4312
549a68c3
SH		 4313 if (!hw)
4314 return 0;
4315
f05267e7 4316 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4317 struct net_device *dev = hw->dev[i];
e3173832 4318 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 4319
e3173832 4320 if (netif_running(dev))
5afa0a9c 4321 sky2_down(dev);
e3173832
SH		 4322
4323 if (sky2->wol)
4324 sky2_wol_init(sky2);
4325
4326 wol |= sky2->wol;
cd28ab6a
SH		 4327 }
4328
8ab8fca2 4329 sky2_write32(hw, B0_IMSK, 0);
6de16237 4330 napi_disable(&hw->napi);
ae306cca 4331 sky2_power_aux(hw);
e3173832 4332
d374c1c1 4333 pci_save_state(pdev);
e3173832 4334 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
ae306cca
SH		 4335 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4336
2ccc99b7 4337 return 0;
cd28ab6a
SH		 4338}
4339
4340static int sky2_resume(struct pci_dev *pdev)
4341{
793b883e 4342 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 4343 int i, err;
cd28ab6a 4344
549a68c3
SH		 4345 if (!hw)
4346 return 0;
4347
ae306cca
SH		 4348 err = pci_set_power_state(pdev, PCI_D0);
4349 if (err)
4350 goto out;
4351
4352 err = pci_restore_state(pdev);
4353 if (err)
4354 goto out;
4355
cd28ab6a 4356 pci_enable_wake(pdev, PCI_D0, 0);
1ad5b4a5
SH		 4357
4358 /* Re-enable all clocks */
05745c4a
SH		 4359 if (hw->chip_id == CHIP_ID_YUKON_EX ||
4360 hw->chip_id == CHIP_ID_YUKON_EC_U ||
4361 hw->chip_id == CHIP_ID_YUKON_FE_P)
b32f40c4 4362 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
1ad5b4a5 4363
e3173832 4364 sky2_reset(hw);
8ab8fca2 4365 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4366 napi_enable(&hw->napi);
8ab8fca2 4367
f05267e7 4368 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4369 struct net_device *dev = hw->dev[i];
6a5706b9 4370 if (netif_running(dev)) {
08c06d8a
SH		 4371 err = sky2_up(dev);
4372 if (err) {
4373 printk(KERN_ERR PFX "%s: could not up: %d\n",
4374 dev->name, err);
4375 dev_close(dev);
eb35cf60 4376 goto out;
5afa0a9c 4377 }
d1b139c0
SH		 4378
4379 sky2_set_multicast(dev);
cd28ab6a
SH		 4380 }
4381 }
eb35cf60 4382
ae306cca 4383 return 0;
08c06d8a 4384out:
b02a9258 4385 dev_err(&pdev->dev, "resume failed (%d)\n", err);
ae306cca 4386 pci_disable_device(pdev);
08c06d8a 4387 return err;
cd28ab6a
SH		 4388}
4389#endif
4390
e3173832
SH		 4391static void sky2_shutdown(struct pci_dev *pdev)
4392{
4393 struct sky2_hw *hw = pci_get_drvdata(pdev);
4394 int i, wol = 0;
4395
549a68c3
SH		 4396 if (!hw)
4397 return;
4398
5c0d6b34 4399 del_timer_sync(&hw->watchdog_timer);
e3173832
SH		 4400
4401 for (i = 0; i < hw->ports; i++) {
4402 struct net_device *dev = hw->dev[i];
4403 struct sky2_port *sky2 = netdev_priv(dev);
4404
4405 if (sky2->wol) {
4406 wol = 1;
4407 sky2_wol_init(sky2);
4408 }
4409 }
4410
4411 if (wol)
4412 sky2_power_aux(hw);
4413
4414 pci_enable_wake(pdev, PCI_D3hot, wol);
4415 pci_enable_wake(pdev, PCI_D3cold, wol);
4416
4417 pci_disable_device(pdev);
4418 pci_set_power_state(pdev, PCI_D3hot);
4419
4420}
4421
cd28ab6a 4422static struct pci_driver sky2_driver = {
793b883e
SH		 4423 .name = DRV_NAME,
4424 .id_table = sky2_id_table,
4425 .probe = sky2_probe,
4426 .remove = __devexit_p(sky2_remove),
cd28ab6a 4427#ifdef CONFIG_PM
793b883e
SH		 4428 .suspend = sky2_suspend,
4429 .resume = sky2_resume,
cd28ab6a 4430#endif
e3173832 4431 .shutdown = sky2_shutdown,
cd28ab6a
SH		 4432};
4433
4434static int __init sky2_init_module(void)
4435{
3cf26753 4436 sky2_debug_init();
50241c4c 4437 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 4438}
4439
4440static void __exit sky2_cleanup_module(void)
4441{
4442 pci_unregister_driver(&sky2_driver);
3cf26753 4443 sky2_debug_cleanup();
cd28ab6a
SH		 4444}
4445
4446module_init(sky2_init_module);
4447module_exit(sky2_cleanup_module);
4448
4449MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
65ebe634 4450MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
cd28ab6a 4451MODULE_LICENSE("GPL");
5f4f9dc1 4452MODULE_VERSION(DRV_VERSION);
kernel source for telekom puls (alcatel/mediatek)