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[NET]: Make NAPI polling independent of struct net_device objects.
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
793b883e 25#include <linux/crc32.h>
cd28ab6a
SH		 26#include <linux/kernel.h>
27#include <linux/version.h>
28#include <linux/module.h>
29#include <linux/netdevice.h>
d0bbccfa 30#include <linux/dma-mapping.h>
cd28ab6a
SH		 31#include <linux/etherdevice.h>
32#include <linux/ethtool.h>
33#include <linux/pci.h>
34#include <linux/ip.h>
c9bdd4b5 35#include <net/ip.h>
cd28ab6a
SH		 36#include <linux/tcp.h>
37#include <linux/in.h>
38#include <linux/delay.h>
91c86df5 39#include <linux/workqueue.h>
d1f13708 40#include <linux/if_vlan.h>
d70cd51a 41#include <linux/prefetch.h>
3cf26753 42#include <linux/debugfs.h>
ef743d33 43#include <linux/mii.h>
cd28ab6a
SH		 44
45#include <asm/irq.h>
46
d1f13708
SH		 47#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48#define SKY2_VLAN_TAG_USED 1
49#endif
50
cd28ab6a
SH		 51#include "sky2.h"
52
53#define DRV_NAME "sky2"
faf60e72 54#define DRV_VERSION "1.18"
cd28ab6a
SH		 55#define PFX DRV_NAME " "
56
57/*
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
14d0263f 60 * similar to Tigon3.
cd28ab6a
SH		 61 */
62
14d0263f 63#define RX_LE_SIZE 1024
cd28ab6a 64#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 65#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 66#define RX_DEF_PENDING RX_MAX_PENDING
82788c7a 67#define RX_SKB_ALIGN 8
793b883e
SH		 68
69#define TX_RING_SIZE 512
70#define TX_DEF_PENDING (TX_RING_SIZE - 1)
71#define TX_MIN_PENDING 64
b19666d9 72#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
cd28ab6a 73
793b883e 74#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a 75#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
cd28ab6a
SH		 76#define TX_WATCHDOG (5 * HZ)
77#define NAPI_WEIGHT 64
78#define PHY_RETRIES 1000
79
f4331a6d
SH		 80#define SKY2_EEPROM_MAGIC 0x9955aabb
81
82
cb5d9547
SH		 83#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
84
cd28ab6a 85static const u32 default_msg =
793b883e
SH		 86 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
87 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 88 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 89
793b883e 90static int debug = -1; /* defaults above */
cd28ab6a
SH		 91module_param(debug, int, 0);
92MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
93
14d0263f 94static int copybreak __read_mostly = 128;
bdb5c58e
SH		 95module_param(copybreak, int, 0);
96MODULE_PARM_DESC(copybreak, "Receive copy threshold");
97
fb2690a9
SH		 98static int disable_msi = 0;
99module_param(disable_msi, int, 0);
100MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
101
cd28ab6a 102static const struct pci_device_id sky2_id_table[] = {
e5b74c7d
SH		 103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
2d2a3871 105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
f1a0b6f5 108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
e5b74c7d
SH		 109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
05745c4a 121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
e5b74c7d 122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
05745c4a 123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
e5b74c7d
SH		 124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
05745c4a 129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
e5b74c7d
SH		 130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
f1a0b6f5
SH		 133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
69161611 135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
cd28ab6a
SH		 136 { 0 }
137};
793b883e 138
cd28ab6a
SH		 139MODULE_DEVICE_TABLE(pci, sky2_id_table);
140
141/* Avoid conditionals by using array */
142static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
143static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 144static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 145
92f965e8
SH		 146/* This driver supports yukon2 chipset only */
147static const char *yukon2_name[] = {
148 "XL", /* 0xb3 */
149 "EC Ultra", /* 0xb4 */
93745494 150 "Extreme", /* 0xb5 */
92f965e8
SH		 151 "EC", /* 0xb6 */
152 "FE", /* 0xb7 */
05745c4a 153 "FE+", /* 0xb8 */
793b883e
SH		 154};
155
d1b139c0
SH		 156static void sky2_set_multicast(struct net_device *dev);
157
793b883e 158/* Access to external PHY */
ef743d33 159static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 160{
161 int i;
162
163 gma_write16(hw, port, GM_SMI_DATA, val);
164 gma_write16(hw, port, GM_SMI_CTRL,
165 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
166
167 for (i = 0; i < PHY_RETRIES; i++) {
cd28ab6a 168 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
ef743d33 169 return 0;
793b883e 170 udelay(1);
cd28ab6a 171 }
ef743d33 172
793b883e 173 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 174 return -ETIMEDOUT;
cd28ab6a
SH		 175}
176
ef743d33 177static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 178{
179 int i;
180
793b883e 181 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 182 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
183
184 for (i = 0; i < PHY_RETRIES; i++) {
ef743d33
SH		 185 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
186 *val = gma_read16(hw, port, GM_SMI_DATA);
187 return 0;
188 }
189
793b883e 190 udelay(1);
cd28ab6a
SH		 191 }
192
ef743d33
SH		 193 return -ETIMEDOUT;
194}
195
196static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
197{
198 u16 v;
199
200 if (__gm_phy_read(hw, port, reg, &v) != 0)
201 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
202 return v;
cd28ab6a
SH		 203}
204
5afa0a9c 205
ae306cca
SH		 206static void sky2_power_on(struct sky2_hw *hw)
207{
208 /* switch power to VCC (WA for VAUX problem) */
209 sky2_write8(hw, B0_POWER_CTRL,
210 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
5afa0a9c 211
ae306cca
SH		 212 /* disable Core Clock Division, */
213 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
d3bcfbeb 214
ae306cca
SH		 215 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
216 /* enable bits are inverted */
217 sky2_write8(hw, B2_Y2_CLK_GATE,
218 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
219 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
220 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
221 else
222 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
977bdf06 223
ea76e635 224 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
fc99fe06 225 u32 reg;
5afa0a9c 226
b2345773
SH		 227 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
228
fc99fe06
SH		 229 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
230 /* set all bits to 0 except bits 15..12 and 8 */
231 reg &= P_ASPM_CONTROL_MSK;
232 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
233
234 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
235 /* set all bits to 0 except bits 28 & 27 */
236 reg &= P_CTL_TIM_VMAIN_AV_MSK;
237 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
238
239 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
8f70920f
SH		 240
241 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
242 reg = sky2_read32(hw, B2_GP_IO);
243 reg |= GLB_GPIO_STAT_RACE_DIS;
244 sky2_write32(hw, B2_GP_IO, reg);
b2345773
SH		 245
246 sky2_read32(hw, B2_GP_IO);
5afa0a9c 247 }
ae306cca 248}
5afa0a9c 249
ae306cca
SH		 250static void sky2_power_aux(struct sky2_hw *hw)
251{
252 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
253 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
254 else
255 /* enable bits are inverted */
256 sky2_write8(hw, B2_Y2_CLK_GATE,
257 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
258 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
259 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
260
261 /* switch power to VAUX */
262 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
263 sky2_write8(hw, B0_POWER_CTRL,
264 (PC_VAUX_ENA | PC_VCC_ENA |
265 PC_VAUX_ON | PC_VCC_OFF));
5afa0a9c
SH		 266}
267
d3bcfbeb 268static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 269{
270 u16 reg;
271
272 /* disable all GMAC IRQ's */
273 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
274 /* disable PHY IRQs */
275 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
793b883e 276
cd28ab6a
SH		 277 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
278 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
279 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
280 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
281
282 reg = gma_read16(hw, port, GM_RX_CTRL);
283 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
284 gma_write16(hw, port, GM_RX_CTRL, reg);
285}
286
16ad91e1
SH		 287/* flow control to advertise bits */
288static const u16 copper_fc_adv[] = {
289 [FC_NONE] = 0,
290 [FC_TX] = PHY_M_AN_ASP,
291 [FC_RX] = PHY_M_AN_PC,
292 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
293};
294
295/* flow control to advertise bits when using 1000BaseX */
296static const u16 fiber_fc_adv[] = {
297 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
298 [FC_TX] = PHY_M_P_ASYM_MD_X,
299 [FC_RX] = PHY_M_P_SYM_MD_X,
300 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
301};
302
303/* flow control to GMA disable bits */
304static const u16 gm_fc_disable[] = {
305 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
306 [FC_TX] = GM_GPCR_FC_RX_DIS,
307 [FC_RX] = GM_GPCR_FC_TX_DIS,
308 [FC_BOTH] = 0,
309};
310
311
cd28ab6a
SH		 312static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
313{
314 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 315 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 316
ea76e635
SH		 317 if (sky2->autoneg == AUTONEG_ENABLE &&
318 !(hw->flags & SKY2_HW_NEWER_PHY)) {
cd28ab6a
SH		 319 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
320
321 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 322 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 323 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
324
53419c68 325 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
cd28ab6a 326 if (hw->chip_id == CHIP_ID_YUKON_EC)
53419c68 327 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 328 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
329 else
53419c68
SH		 330 /* set master & slave downshift counter to 1x */
331 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
cd28ab6a
SH		 332
333 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
334 }
335
336 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 337 if (sky2_is_copper(hw)) {
05745c4a 338 if (!(hw->flags & SKY2_HW_GIGABIT)) {
cd28ab6a
SH		 339 /* enable automatic crossover */
340 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
6d3105d5
SH		 341
342 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
343 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
344 u16 spec;
345
346 /* Enable Class A driver for FE+ A0 */
347 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
348 spec |= PHY_M_FESC_SEL_CL_A;
349 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
350 }
cd28ab6a
SH		 351 } else {
352 /* disable energy detect */
353 ctrl &= ~PHY_M_PC_EN_DET_MSK;
354
355 /* enable automatic crossover */
356 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
357
53419c68 358 /* downshift on PHY 88E1112 and 88E1149 is changed */
93745494 359 if (sky2->autoneg == AUTONEG_ENABLE
ea76e635 360 && (hw->flags & SKY2_HW_NEWER_PHY)) {
53419c68 361 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 362 ctrl &= ~PHY_M_PC_DSC_MSK;
363 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
364 }
365 }
cd28ab6a
SH		 366 } else {
367 /* workaround for deviation #4.88 (CRC errors) */
368 /* disable Automatic Crossover */
369
370 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 371 }
cd28ab6a 372
b89165f2
SH		 373 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
374
375 /* special setup for PHY 88E1112 Fiber */
ea76e635 376 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
b89165f2 377 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 378
b89165f2
SH		 379 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
380 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
381 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
382 ctrl &= ~PHY_M_MAC_MD_MSK;
383 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
384 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
385
386 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 387 /* select page 1 to access Fiber registers */
388 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 389
390 /* for SFP-module set SIGDET polarity to low */
391 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
392 ctrl |= PHY_M_FIB_SIGD_POL;
34dd962b 393 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
cd28ab6a 394 }
b89165f2
SH		 395
396 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 397 }
398
7800fddc 399 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 400 ct1000 = 0;
401 adv = PHY_AN_CSMA;
2eaba1a2 402 reg = 0;
cd28ab6a
SH		 403
404 if (sky2->autoneg == AUTONEG_ENABLE) {
b89165f2 405 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 406 if (sky2->advertising & ADVERTISED_1000baseT_Full)
407 ct1000 |= PHY_M_1000C_AFD;
408 if (sky2->advertising & ADVERTISED_1000baseT_Half)
409 ct1000 |= PHY_M_1000C_AHD;
410 if (sky2->advertising & ADVERTISED_100baseT_Full)
411 adv |= PHY_M_AN_100_FD;
412 if (sky2->advertising & ADVERTISED_100baseT_Half)
413 adv |= PHY_M_AN_100_HD;
414 if (sky2->advertising & ADVERTISED_10baseT_Full)
415 adv |= PHY_M_AN_10_FD;
416 if (sky2->advertising & ADVERTISED_10baseT_Half)
417 adv |= PHY_M_AN_10_HD;
709c6e7b 418
16ad91e1 419 adv |= copper_fc_adv[sky2->flow_mode];
b89165f2
SH		 420 } else { /* special defines for FIBER (88E1040S only) */
421 if (sky2->advertising & ADVERTISED_1000baseT_Full)
422 adv |= PHY_M_AN_1000X_AFD;
423 if (sky2->advertising & ADVERTISED_1000baseT_Half)
424 adv |= PHY_M_AN_1000X_AHD;
cd28ab6a 425
16ad91e1 426 adv |= fiber_fc_adv[sky2->flow_mode];
709c6e7b 427 }
cd28ab6a
SH		 428
429 /* Restart Auto-negotiation */
430 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
431 } else {
432 /* forced speed/duplex settings */
433 ct1000 = PHY_M_1000C_MSE;
434
2eaba1a2
SH		 435 /* Disable auto update for duplex flow control and speed */
436 reg |= GM_GPCR_AU_ALL_DIS;
cd28ab6a
SH		 437
438 switch (sky2->speed) {
439 case SPEED_1000:
440 ctrl |= PHY_CT_SP1000;
2eaba1a2 441 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 442 break;
443 case SPEED_100:
444 ctrl |= PHY_CT_SP100;
2eaba1a2 445 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 446 break;
447 }
448
2eaba1a2
SH		 449 if (sky2->duplex == DUPLEX_FULL) {
450 reg |= GM_GPCR_DUP_FULL;
451 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 452 } else if (sky2->speed < SPEED_1000)
453 sky2->flow_mode = FC_NONE;
2eaba1a2 454
2eaba1a2 455
16ad91e1 456 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 457
458 /* Forward pause packets to GMAC? */
16ad91e1 459 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 460 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
461 else
462 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 463 }
464
2eaba1a2
SH		 465 gma_write16(hw, port, GM_GP_CTRL, reg);
466
05745c4a 467 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a
SH		 468 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
469
470 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
471 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
472
473 /* Setup Phy LED's */
474 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
475 ledover = 0;
476
477 switch (hw->chip_id) {
478 case CHIP_ID_YUKON_FE:
479 /* on 88E3082 these bits are at 11..9 (shifted left) */
480 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
481
482 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
483
484 /* delete ACT LED control bits */
485 ctrl &= ~PHY_M_FELP_LED1_MSK;
486 /* change ACT LED control to blink mode */
487 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
488 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
489 break;
490
05745c4a
SH		 491 case CHIP_ID_YUKON_FE_P:
492 /* Enable Link Partner Next Page */
493 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
494 ctrl |= PHY_M_PC_ENA_LIP_NP;
495
496 /* disable Energy Detect and enable scrambler */
497 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
498 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
499
500 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
501 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
502 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
503 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
504
505 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
506 break;
507
cd28ab6a 508 case CHIP_ID_YUKON_XL:
793b883e 509 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 510
511 /* select page 3 to access LED control register */
512 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
513
514 /* set LED Function Control register */
ed6d32c7
SH		 515 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
516 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
517 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
518 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
519 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 520
521 /* set Polarity Control register */
522 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 523 (PHY_M_POLC_LS1_P_MIX(4) |
524 PHY_M_POLC_IS0_P_MIX(4) |
525 PHY_M_POLC_LOS_CTRL(2) |
526 PHY_M_POLC_INIT_CTRL(2) |
527 PHY_M_POLC_STA1_CTRL(2) |
528 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 529
530 /* restore page register */
793b883e 531 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 532 break;
93745494 533
ed6d32c7 534 case CHIP_ID_YUKON_EC_U:
93745494 535 case CHIP_ID_YUKON_EX:
ed6d32c7
SH		 536 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
537
538 /* select page 3 to access LED control register */
539 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
540
541 /* set LED Function Control register */
542 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
543 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
544 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
545 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
546 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
547
548 /* set Blink Rate in LED Timer Control Register */
549 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
550 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
551 /* restore page register */
552 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
553 break;
cd28ab6a
SH		 554
555 default:
556 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
557 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
558 /* turn off the Rx LED (LED_RX) */
0efdf262 559 ledover &= ~PHY_M_LED_MO_RX;
cd28ab6a
SH		 560 }
561
9467a8fc
SH		 562 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
563 hw->chip_rev == CHIP_REV_YU_EC_U_A1) {
977bdf06 564 /* apply fixes in PHY AFE */
ed6d32c7
SH		 565 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
566
977bdf06 567 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 568 gm_phy_write(hw, port, 0x18, 0xaa99);
569 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 570
977bdf06 571 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
ed6d32c7
SH		 572 gm_phy_write(hw, port, 0x18, 0xa204);
573 gm_phy_write(hw, port, 0x17, 0x2002);
977bdf06
SH		 574
575 /* set page register to 0 */
9467a8fc 576 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
05745c4a
SH		 577 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
578 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
579 /* apply workaround for integrated resistors calibration */
580 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
581 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
93745494 582 } else if (hw->chip_id != CHIP_ID_YUKON_EX) {
05745c4a 583 /* no effect on Yukon-XL */
977bdf06 584 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 585
977bdf06
SH		 586 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
587 /* turn on 100 Mbps LED (LED_LINK100) */
0efdf262 588 ledover |= PHY_M_LED_MO_100;
977bdf06 589 }
cd28ab6a 590
977bdf06
SH		 591 if (ledover)
592 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
593
594 }
2eaba1a2 595
d571b694 596 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 597 if (sky2->autoneg == AUTONEG_ENABLE)
598 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
599 else
600 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
601}
602
d3bcfbeb
SH		 603static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
604{
605 u32 reg1;
606 static const u32 phy_power[]
607 = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
608
609 /* looks like this XL is back asswards .. */
610 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
611 onoff = !onoff;
612
aed2cec4 613 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
d3bcfbeb 614 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
d3bcfbeb
SH		 615 if (onoff)
616 /* Turn off phy power saving */
617 reg1 &= ~phy_power[port];
618 else
619 reg1 |= phy_power[port];
620
621 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
98232f85 622 sky2_pci_read32(hw, PCI_DEV_REG1);
aed2cec4 623 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
d3bcfbeb
SH		 624 udelay(100);
625}
626
1b537565
SH		 627/* Force a renegotiation */
628static void sky2_phy_reinit(struct sky2_port *sky2)
629{
e07b1aa8 630 spin_lock_bh(&sky2->phy_lock);
1b537565 631 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 632 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 633}
634
e3173832
SH		 635/* Put device in state to listen for Wake On Lan */
636static void sky2_wol_init(struct sky2_port *sky2)
637{
638 struct sky2_hw *hw = sky2->hw;
639 unsigned port = sky2->port;
640 enum flow_control save_mode;
641 u16 ctrl;
642 u32 reg1;
643
644 /* Bring hardware out of reset */
645 sky2_write16(hw, B0_CTST, CS_RST_CLR);
646 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
647
648 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
649 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
650
651 /* Force to 10/100
652 * sky2_reset will re-enable on resume
653 */
654 save_mode = sky2->flow_mode;
655 ctrl = sky2->advertising;
656
657 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
658 sky2->flow_mode = FC_NONE;
659 sky2_phy_power(hw, port, 1);
660 sky2_phy_reinit(sky2);
661
662 sky2->flow_mode = save_mode;
663 sky2->advertising = ctrl;
664
665 /* Set GMAC to no flow control and auto update for speed/duplex */
666 gma_write16(hw, port, GM_GP_CTRL,
667 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
668 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
669
670 /* Set WOL address */
671 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
672 sky2->netdev->dev_addr, ETH_ALEN);
673
674 /* Turn on appropriate WOL control bits */
675 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
676 ctrl = 0;
677 if (sky2->wol & WAKE_PHY)
678 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
679 else
680 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
681
682 if (sky2->wol & WAKE_MAGIC)
683 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
684 else
685 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
686
687 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
688 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
689
690 /* Turn on legacy PCI-Express PME mode */
691 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
692 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
693 reg1 |= PCI_Y2_PME_LEGACY;
694 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
695 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
696
697 /* block receiver */
698 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
699
700}
701
69161611
SH		 702static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
703{
05745c4a
SH		 704 struct net_device *dev = hw->dev[port];
705
706 if (dev->mtu <= ETH_DATA_LEN)
69161611 707 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
05745c4a
SH		 708 TX_JUMBO_DIS | TX_STFW_ENA);
709
710 else if (hw->chip_id != CHIP_ID_YUKON_EC_U)
711 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
712 TX_STFW_ENA | TX_JUMBO_ENA);
713 else {
714 /* set Tx GMAC FIFO Almost Empty Threshold */
715 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
716 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
69161611 717
05745c4a
SH		 718 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
719 TX_JUMBO_ENA | TX_STFW_DIS);
69161611 720
05745c4a
SH		 721 /* Can't do offload because of lack of store/forward */
722 dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM);
69161611
SH		 723 }
724}
725
cd28ab6a
SH		 726static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
727{
728 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
729 u16 reg;
25cccecc 730 u32 rx_reg;
cd28ab6a
SH		 731 int i;
732 const u8 *addr = hw->dev[port]->dev_addr;
733
f350339c
SH		 734 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
735 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
cd28ab6a
SH		 736
737 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
738
793b883e 739 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 740 /* WA DEV_472 -- looks like crossed wires on port 2 */
741 /* clear GMAC 1 Control reset */
742 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
743 do {
744 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
745 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
746 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
747 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
748 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
749 }
750
793b883e 751 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 752
2eaba1a2
SH		 753 /* Enable Transmit FIFO Underrun */
754 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
755
e07b1aa8 756 spin_lock_bh(&sky2->phy_lock);
cd28ab6a 757 sky2_phy_init(hw, port);
e07b1aa8 758 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 759
760 /* MIB clear */
761 reg = gma_read16(hw, port, GM_PHY_ADDR);
762 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
763
43f2f104
SH		 764 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
765 gma_read16(hw, port, i);
cd28ab6a
SH		 766 gma_write16(hw, port, GM_PHY_ADDR, reg);
767
768 /* transmit control */
769 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
770
771 /* receive control reg: unicast + multicast + no FCS */
772 gma_write16(hw, port, GM_RX_CTRL,
793b883e 773 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 774
775 /* transmit flow control */
776 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
777
778 /* transmit parameter */
779 gma_write16(hw, port, GM_TX_PARAM,
780 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
781 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
782 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
783 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
784
785 /* serial mode register */
786 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 787 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 788
6b1a3aef 789 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 790 reg |= GM_SMOD_JUMBO_ENA;
791
792 gma_write16(hw, port, GM_SERIAL_MODE, reg);
793
cd28ab6a
SH		 794 /* virtual address for data */
795 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
796
793b883e
SH		 797 /* physical address: used for pause frames */
798 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
799
800 /* ignore counter overflows */
cd28ab6a
SH		 801 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
802 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
803 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
804
805 /* Configure Rx MAC FIFO */
806 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
25cccecc 807 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
05745c4a
SH		 808 if (hw->chip_id == CHIP_ID_YUKON_EX ||
809 hw->chip_id == CHIP_ID_YUKON_FE_P)
25cccecc 810 rx_reg |= GMF_RX_OVER_ON;
69161611 811
25cccecc 812 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
cd28ab6a 813
d571b694 814 /* Flush Rx MAC FIFO on any flow control or error */
42eeea01 815 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
cd28ab6a 816
8df9a876 817 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
05745c4a
SH		 818 reg = RX_GMF_FL_THR_DEF + 1;
819 /* Another magic mystery workaround from sk98lin */
820 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
821 hw->chip_rev == CHIP_REV_YU_FE2_A0)
822 reg = 0x178;
823 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
cd28ab6a
SH		 824
825 /* Configure Tx MAC FIFO */
826 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
827 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 828
e0c28116
SH		 829 /* On chips without ram buffer, pause is controled by MAC level */
830 if (sky2_read8(hw, B2_E_0) == 0) {
8df9a876 831 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
5a5b1ea0 832 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
b628ed98 833
69161611 834 sky2_set_tx_stfwd(hw, port);
5a5b1ea0
SH		 835 }
836
cd28ab6a
SH		 837}
838
67712901
SH		 839/* Assign Ram Buffer allocation to queue */
840static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 841{
67712901
SH		 842 u32 end;
843
844 /* convert from K bytes to qwords used for hw register */
845 start *= 1024/8;
846 space *= 1024/8;
847 end = start + space - 1;
793b883e 848
cd28ab6a
SH		 849 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
850 sky2_write32(hw, RB_ADDR(q, RB_START), start);
851 sky2_write32(hw, RB_ADDR(q, RB_END), end);
852 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
853 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
854
855 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 856 u32 tp = space - space/4;
793b883e 857
1c28f6ba
SH		 858 /* On receive queue's set the thresholds
859 * give receiver priority when > 3/4 full
860 * send pause when down to 2K
861 */
862 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
863 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 864
1c28f6ba
SH		 865 tp = space - 2048/8;
866 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
867 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 868 } else {
869 /* Enable store & forward on Tx queue's because
870 * Tx FIFO is only 1K on Yukon
871 */
872 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
873 }
874
875 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 876 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 877}
878
cd28ab6a 879/* Setup Bus Memory Interface */
af4ed7e6 880static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 881{
882 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
883 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
884 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 885 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 886}
887
cd28ab6a
SH		 888/* Setup prefetch unit registers. This is the interface between
889 * hardware and driver list elements
890 */
8cc048e3 891static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 892 u64 addr, u32 last)
893{
cd28ab6a
SH		 894 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
895 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
896 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
897 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
898 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
899 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 900
901 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 902}
903
793b883e
SH		 904static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
905{
906 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
907
cb5d9547 908 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
291ea614 909 le->ctrl = 0;
793b883e
SH		 910 return le;
911}
cd28ab6a 912
88f5f0ca
SH		 913static void tx_init(struct sky2_port *sky2)
914{
915 struct sky2_tx_le *le;
916
917 sky2->tx_prod = sky2->tx_cons = 0;
918 sky2->tx_tcpsum = 0;
919 sky2->tx_last_mss = 0;
920
921 le = get_tx_le(sky2);
922 le->addr = 0;
923 le->opcode = OP_ADDR64 | HW_OWNER;
924 sky2->tx_addr64 = 0;
925}
926
291ea614
SH		 927static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
928 struct sky2_tx_le *le)
929{
930 return sky2->tx_ring + (le - sky2->tx_le);
931}
932
290d4de5
SH		 933/* Update chip's next pointer */
934static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 935{
50432cb5 936 /* Make sure write' to descriptors are complete before we tell hardware */
762c2de2 937 wmb();
50432cb5
SH		 938 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
939
940 /* Synchronize I/O on since next processor may write to tail */
941 mmiowb();
cd28ab6a
SH		 942}
943
793b883e 944
cd28ab6a
SH		 945static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
946{
947 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 948 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 949 le->ctrl = 0;
cd28ab6a
SH		 950 return le;
951}
952
14d0263f
SH		 953/* Build description to hardware for one receive segment */
954static void sky2_rx_add(struct sky2_port *sky2, u8 op,
955 dma_addr_t map, unsigned len)
cd28ab6a
SH		 956{
957 struct sky2_rx_le *le;
36eb0c71 958 u32 hi = upper_32_bits(map);
cd28ab6a 959
793b883e 960 if (sky2->rx_addr64 != hi) {
cd28ab6a 961 le = sky2_next_rx(sky2);
793b883e 962 le->addr = cpu_to_le32(hi);
cd28ab6a 963 le->opcode = OP_ADDR64 | HW_OWNER;
36eb0c71 964 sky2->rx_addr64 = upper_32_bits(map + len);
cd28ab6a 965 }
793b883e 966
cd28ab6a 967 le = sky2_next_rx(sky2);
734d1868
SH		 968 le->addr = cpu_to_le32((u32) map);
969 le->length = cpu_to_le16(len);
14d0263f 970 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 971}
972
14d0263f
SH		 973/* Build description to hardware for one possibly fragmented skb */
974static void sky2_rx_submit(struct sky2_port *sky2,
975 const struct rx_ring_info *re)
976{
977 int i;
978
979 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
980
981 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
982 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
983}
984
985
986static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
987 unsigned size)
988{
989 struct sk_buff *skb = re->skb;
990 int i;
991
992 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
993 pci_unmap_len_set(re, data_size, size);
994
995 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
996 re->frag_addr[i] = pci_map_page(pdev,
997 skb_shinfo(skb)->frags[i].page,
998 skb_shinfo(skb)->frags[i].page_offset,
999 skb_shinfo(skb)->frags[i].size,
1000 PCI_DMA_FROMDEVICE);
1001}
1002
1003static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1004{
1005 struct sk_buff *skb = re->skb;
1006 int i;
1007
1008 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1009 PCI_DMA_FROMDEVICE);
1010
1011 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1012 pci_unmap_page(pdev, re->frag_addr[i],
1013 skb_shinfo(skb)->frags[i].size,
1014 PCI_DMA_FROMDEVICE);
1015}
793b883e 1016
cd28ab6a
SH		 1017/* Tell chip where to start receive checksum.
1018 * Actually has two checksums, but set both same to avoid possible byte
1019 * order problems.
1020 */
793b883e 1021static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a 1022{
ea76e635 1023 struct sky2_rx_le *le = sky2_next_rx(sky2);
793b883e 1024
ea76e635
SH		 1025 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1026 le->ctrl = 0;
1027 le->opcode = OP_TCPSTART | HW_OWNER;
cd28ab6a 1028
ea76e635
SH		 1029 sky2_write32(sky2->hw,
1030 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1031 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 1032}
1033
6b1a3aef
SH		 1034/*
1035 * The RX Stop command will not work for Yukon-2 if the BMU does not
1036 * reach the end of packet and since we can't make sure that we have
1037 * incoming data, we must reset the BMU while it is not doing a DMA
1038 * transfer. Since it is possible that the RX path is still active,
1039 * the RX RAM buffer will be stopped first, so any possible incoming
1040 * data will not trigger a DMA. After the RAM buffer is stopped, the
1041 * BMU is polled until any DMA in progress is ended and only then it
1042 * will be reset.
1043 */
1044static void sky2_rx_stop(struct sky2_port *sky2)
1045{
1046 struct sky2_hw *hw = sky2->hw;
1047 unsigned rxq = rxqaddr[sky2->port];
1048 int i;
1049
1050 /* disable the RAM Buffer receive queue */
1051 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1052
1053 for (i = 0; i < 0xffff; i++)
1054 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1055 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1056 goto stopped;
1057
1058 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1059 sky2->netdev->name);
1060stopped:
1061 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1062
1063 /* reset the Rx prefetch unit */
1064 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
50432cb5 1065 mmiowb();
6b1a3aef 1066}
793b883e 1067
d571b694 1068/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 1069static void sky2_rx_clean(struct sky2_port *sky2)
1070{
1071 unsigned i;
1072
1073 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 1074 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 1075 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 1076
1077 if (re->skb) {
14d0263f 1078 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 1079 kfree_skb(re->skb);
1080 re->skb = NULL;
1081 }
1082 }
1083}
1084
ef743d33
SH		 1085/* Basic MII support */
1086static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1087{
1088 struct mii_ioctl_data *data = if_mii(ifr);
1089 struct sky2_port *sky2 = netdev_priv(dev);
1090 struct sky2_hw *hw = sky2->hw;
1091 int err = -EOPNOTSUPP;
1092
1093 if (!netif_running(dev))
1094 return -ENODEV; /* Phy still in reset */
1095
d89e1343 1096 switch (cmd) {
ef743d33
SH		 1097 case SIOCGMIIPHY:
1098 data->phy_id = PHY_ADDR_MARV;
1099
1100 /* fallthru */
1101 case SIOCGMIIREG: {
1102 u16 val = 0;
91c86df5 1103
e07b1aa8 1104 spin_lock_bh(&sky2->phy_lock);
ef743d33 1105 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 1106 spin_unlock_bh(&sky2->phy_lock);
91c86df5 1107
ef743d33
SH		 1108 data->val_out = val;
1109 break;
1110 }
1111
1112 case SIOCSMIIREG:
1113 if (!capable(CAP_NET_ADMIN))
1114 return -EPERM;
1115
e07b1aa8 1116 spin_lock_bh(&sky2->phy_lock);
ef743d33
SH		 1117 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1118 data->val_in);
e07b1aa8 1119 spin_unlock_bh(&sky2->phy_lock);
ef743d33
SH		 1120 break;
1121 }
1122 return err;
1123}
1124
d1f13708
SH		 1125#ifdef SKY2_VLAN_TAG_USED
1126static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1127{
1128 struct sky2_port *sky2 = netdev_priv(dev);
1129 struct sky2_hw *hw = sky2->hw;
1130 u16 port = sky2->port;
d1f13708 1131
2bb8c262 1132 netif_tx_lock_bh(dev);
bea3348e 1133 napi_disable(&hw->napi);
d1f13708 1134
d1f13708 1135 sky2->vlgrp = grp;
3d4e66f5
SH		 1136 if (grp) {
1137 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1138 RX_VLAN_STRIP_ON);
1139 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1140 TX_VLAN_TAG_ON);
1141 } else {
1142 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1143 RX_VLAN_STRIP_OFF);
1144 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1145 TX_VLAN_TAG_OFF);
1146 }
d1f13708 1147
bea3348e 1148 napi_enable(&hw->napi);
2bb8c262 1149 netif_tx_unlock_bh(dev);
d1f13708
SH		 1150}
1151#endif
1152
82788c7a 1153/*
14d0263f
SH		 1154 * Allocate an skb for receiving. If the MTU is large enough
1155 * make the skb non-linear with a fragment list of pages.
1156 *
82788c7a
SH		 1157 * It appears the hardware has a bug in the FIFO logic that
1158 * cause it to hang if the FIFO gets overrun and the receive buffer
497d7c86
SH		 1159 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1160 * aligned except if slab debugging is enabled.
82788c7a 1161 */
14d0263f 1162static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1163{
1164 struct sk_buff *skb;
14d0263f
SH		 1165 unsigned long p;
1166 int i;
82788c7a 1167
14d0263f
SH		 1168 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + RX_SKB_ALIGN);
1169 if (!skb)
1170 goto nomem;
1171
1172 p = (unsigned long) skb->data;
1173 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
1174
1175 for (i = 0; i < sky2->rx_nfrags; i++) {
1176 struct page *page = alloc_page(GFP_ATOMIC);
1177
1178 if (!page)
1179 goto free_partial;
1180 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1181 }
1182
1183 return skb;
14d0263f
SH		 1184free_partial:
1185 kfree_skb(skb);
1186nomem:
1187 return NULL;
82788c7a
SH		 1188}
1189
55c9dd35
SH		 1190static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1191{
1192 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1193}
1194
cd28ab6a
SH		 1195/*
1196 * Allocate and setup receiver buffer pool.
14d0263f
SH		 1197 * Normal case this ends up creating one list element for skb
1198 * in the receive ring. Worst case if using large MTU and each
1199 * allocation falls on a different 64 bit region, that results
1200 * in 6 list elements per ring entry.
1201 * One element is used for checksum enable/disable, and one
1202 * extra to avoid wrap.
cd28ab6a 1203 */
6b1a3aef 1204static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1205{
6b1a3aef 1206 struct sky2_hw *hw = sky2->hw;
14d0263f 1207 struct rx_ring_info *re;
6b1a3aef 1208 unsigned rxq = rxqaddr[sky2->port];
14d0263f 1209 unsigned i, size, space, thresh;
cd28ab6a 1210
6b1a3aef 1211 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1212 sky2_qset(hw, rxq);
977bdf06 1213
c3905bc4
SH		 1214 /* On PCI express lowering the watermark gives better performance */
1215 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1216 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1217
1218 /* These chips have no ram buffer?
1219 * MAC Rx RAM Read is controlled by hardware */
8df9a876 1220 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
c3905bc4
SH		 1221 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1222 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
f449c7c1 1223 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
977bdf06 1224
6b1a3aef
SH		 1225 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1226
ea76e635
SH		 1227 if (!(hw->flags & SKY2_HW_NEW_LE))
1228 rx_set_checksum(sky2);
14d0263f
SH		 1229
1230 /* Space needed for frame data + headers rounded up */
f957da2a 1231 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
14d0263f
SH		 1232
1233 /* Stopping point for hardware truncation */
1234 thresh = (size - 8) / sizeof(u32);
1235
1236 /* Account for overhead of skb - to avoid order > 0 allocation */
1237 space = SKB_DATA_ALIGN(size) + NET_SKB_PAD
1238 + sizeof(struct skb_shared_info);
1239
1240 sky2->rx_nfrags = space >> PAGE_SHIFT;
1241 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1242
1243 if (sky2->rx_nfrags != 0) {
1244 /* Compute residue after pages */
1245 space = sky2->rx_nfrags << PAGE_SHIFT;
1246
1247 if (space < size)
1248 size -= space;
1249 else
1250 size = 0;
1251
1252 /* Optimize to handle small packets and headers */
1253 if (size < copybreak)
1254 size = copybreak;
1255 if (size < ETH_HLEN)
1256 size = ETH_HLEN;
1257 }
1258 sky2->rx_data_size = size;
1259
1260 /* Fill Rx ring */
793b883e 1261 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1262 re = sky2->rx_ring + i;
cd28ab6a 1263
14d0263f 1264 re->skb = sky2_rx_alloc(sky2);
cd28ab6a
SH		 1265 if (!re->skb)
1266 goto nomem;
1267
14d0263f
SH		 1268 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1269 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1270 }
1271
a1433ac4
SH		 1272 /*
1273 * The receiver hangs if it receives frames larger than the
1274 * packet buffer. As a workaround, truncate oversize frames, but
1275 * the register is limited to 9 bits, so if you do frames > 2052
1276 * you better get the MTU right!
1277 */
a1433ac4
SH		 1278 if (thresh > 0x1ff)
1279 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1280 else {
1281 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1282 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1283 }
1284
6b1a3aef 1285 /* Tell chip about available buffers */
55c9dd35 1286 sky2_rx_update(sky2, rxq);
cd28ab6a
SH		 1287 return 0;
1288nomem:
1289 sky2_rx_clean(sky2);
1290 return -ENOMEM;
1291}
1292
1293/* Bring up network interface. */
1294static int sky2_up(struct net_device *dev)
1295{
1296 struct sky2_port *sky2 = netdev_priv(dev);
1297 struct sky2_hw *hw = sky2->hw;
1298 unsigned port = sky2->port;
e0c28116 1299 u32 imask, ramsize;
ee7abb04 1300 int cap, err = -ENOMEM;
843a46f4 1301 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1302
ee7abb04
SH		 1303 /*
1304 * On dual port PCI-X card, there is an problem where status
1305 * can be received out of order due to split transactions
843a46f4 1306 */
ee7abb04
SH		 1307 if (otherdev && netif_running(otherdev) &&
1308 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1309 struct sky2_port *osky2 = netdev_priv(otherdev);
1310 u16 cmd;
1311
1312 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1313 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1314 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1315
1316 sky2->rx_csum = 0;
1317 osky2->rx_csum = 0;
1318 }
843a46f4 1319
cd28ab6a
SH		 1320 if (netif_msg_ifup(sky2))
1321 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1322
55d7b4e6
SH		 1323 netif_carrier_off(dev);
1324
cd28ab6a
SH		 1325 /* must be power of 2 */
1326 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 1327 TX_RING_SIZE *
1328 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 1329 &sky2->tx_le_map);
1330 if (!sky2->tx_le)
1331 goto err_out;
1332
6cdbbdf3 1333 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 1334 GFP_KERNEL);
1335 if (!sky2->tx_ring)
1336 goto err_out;
88f5f0ca
SH		 1337
1338 tx_init(sky2);
cd28ab6a
SH		 1339
1340 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1341 &sky2->rx_le_map);
1342 if (!sky2->rx_le)
1343 goto err_out;
1344 memset(sky2->rx_le, 0, RX_LE_BYTES);
1345
291ea614 1346 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
cd28ab6a
SH		 1347 GFP_KERNEL);
1348 if (!sky2->rx_ring)
1349 goto err_out;
1350
d3bcfbeb
SH		 1351 sky2_phy_power(hw, port, 1);
1352
cd28ab6a
SH		 1353 sky2_mac_init(hw, port);
1354
e0c28116
SH		 1355 /* Register is number of 4K blocks on internal RAM buffer. */
1356 ramsize = sky2_read8(hw, B2_E_0) * 4;
1357 if (ramsize > 0) {
67712901 1358 u32 rxspace;
cd28ab6a 1359
e0c28116 1360 pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
67712901
SH		 1361 if (ramsize < 16)
1362 rxspace = ramsize / 2;
1363 else
1364 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1365
67712901
SH		 1366 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1367 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1368
1369 /* Make sure SyncQ is disabled */
1370 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1371 RB_RST_SET);
1372 }
793b883e 1373
af4ed7e6 1374 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1375
69161611
SH		 1376 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1377 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1378 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1379
977bdf06 1380 /* Set almost empty threshold */
c2716fb4
SH		 1381 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1382 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
b628ed98 1383 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
5a5b1ea0 1384
6b1a3aef
SH		 1385 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1386 TX_RING_SIZE - 1);
cd28ab6a 1387
bea3348e
SH		 1388 napi_enable(&hw->napi);
1389
6b1a3aef 1390 err = sky2_rx_start(sky2);
bea3348e
SH		 1391 if (err) {
1392 napi_disable(&hw->napi);
cd28ab6a 1393 goto err_out;
bea3348e 1394 }
cd28ab6a 1395
cd28ab6a 1396 /* Enable interrupts from phy/mac for port */
e07b1aa8 1397 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1398 imask |= portirq_msk[port];
e07b1aa8
SH		 1399 sky2_write32(hw, B0_IMSK, imask);
1400
cd28ab6a
SH		 1401 return 0;
1402
1403err_out:
1b537565 1404 if (sky2->rx_le) {
cd28ab6a
SH		 1405 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1406 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1407 sky2->rx_le = NULL;
1408 }
1409 if (sky2->tx_le) {
cd28ab6a
SH		 1410 pci_free_consistent(hw->pdev,
1411 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1412 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1413 sky2->tx_le = NULL;
1414 }
1415 kfree(sky2->tx_ring);
1416 kfree(sky2->rx_ring);
cd28ab6a 1417
1b537565
SH		 1418 sky2->tx_ring = NULL;
1419 sky2->rx_ring = NULL;
cd28ab6a
SH		 1420 return err;
1421}
1422
793b883e
SH		 1423/* Modular subtraction in ring */
1424static inline int tx_dist(unsigned tail, unsigned head)
1425{
cb5d9547 1426 return (head - tail) & (TX_RING_SIZE - 1);
793b883e 1427}
cd28ab6a 1428
793b883e
SH		 1429/* Number of list elements available for next tx */
1430static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1431{
793b883e 1432 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1433}
1434
793b883e 1435/* Estimate of number of transmit list elements required */
28bd181a 1436static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1437{
793b883e
SH		 1438 unsigned count;
1439
1440 count = sizeof(dma_addr_t) / sizeof(u32);
1441 count += skb_shinfo(skb)->nr_frags * count;
1442
89114afd 1443 if (skb_is_gso(skb))
793b883e
SH		 1444 ++count;
1445
84fa7933 1446 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1447 ++count;
1448
1449 return count;
cd28ab6a
SH		 1450}
1451
793b883e
SH		 1452/*
1453 * Put one packet in ring for transmit.
1454 * A single packet can generate multiple list elements, and
1455 * the number of ring elements will probably be less than the number
1456 * of list elements used.
1457 */
cd28ab6a
SH		 1458static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1459{
1460 struct sky2_port *sky2 = netdev_priv(dev);
1461 struct sky2_hw *hw = sky2->hw;
d1f13708 1462 struct sky2_tx_le *le = NULL;
6cdbbdf3 1463 struct tx_ring_info *re;
cd28ab6a
SH		 1464 unsigned i, len;
1465 dma_addr_t mapping;
1466 u32 addr64;
1467 u16 mss;
1468 u8 ctrl;
1469
2bb8c262
SH		 1470 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1471 return NETDEV_TX_BUSY;
cd28ab6a 1472
793b883e 1473 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 1474 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1475 dev->name, sky2->tx_prod, skb->len);
1476
cd28ab6a
SH		 1477 len = skb_headlen(skb);
1478 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
36eb0c71 1479 addr64 = upper_32_bits(mapping);
793b883e 1480
a018e330 1481 /* Send high bits if changed or crosses boundary */
36eb0c71
SH		 1482 if (addr64 != sky2->tx_addr64 ||
1483 upper_32_bits(mapping + len) != sky2->tx_addr64) {
793b883e 1484 le = get_tx_le(sky2);
f65b138c 1485 le->addr = cpu_to_le32(addr64);
793b883e 1486 le->opcode = OP_ADDR64 | HW_OWNER;
36eb0c71 1487 sky2->tx_addr64 = upper_32_bits(mapping + len);
793b883e 1488 }
cd28ab6a
SH		 1489
1490 /* Check for TCP Segmentation Offload */
7967168c 1491 mss = skb_shinfo(skb)->gso_size;
793b883e 1492 if (mss != 0) {
ea76e635
SH		 1493
1494 if (!(hw->flags & SKY2_HW_NEW_LE))
69161611
SH		 1495 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1496
1497 if (mss != sky2->tx_last_mss) {
1498 le = get_tx_le(sky2);
1499 le->addr = cpu_to_le32(mss);
ea76e635
SH		 1500
1501 if (hw->flags & SKY2_HW_NEW_LE)
69161611
SH		 1502 le->opcode = OP_MSS | HW_OWNER;
1503 else
1504 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd
SH		 1505 sky2->tx_last_mss = mss;
1506 }
cd28ab6a
SH		 1507 }
1508
cd28ab6a 1509 ctrl = 0;
d1f13708
SH		 1510#ifdef SKY2_VLAN_TAG_USED
1511 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1512 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1513 if (!le) {
1514 le = get_tx_le(sky2);
f65b138c 1515 le->addr = 0;
d1f13708 1516 le->opcode = OP_VLAN|HW_OWNER;
d1f13708
SH		 1517 } else
1518 le->opcode |= OP_VLAN;
1519 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1520 ctrl |= INS_VLAN;
1521 }
1522#endif
1523
1524 /* Handle TCP checksum offload */
84fa7933 1525 if (skb->ip_summed == CHECKSUM_PARTIAL) {
69161611 1526 /* On Yukon EX (some versions) encoding change. */
ea76e635 1527 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
69161611
SH		 1528 ctrl |= CALSUM; /* auto checksum */
1529 else {
1530 const unsigned offset = skb_transport_offset(skb);
1531 u32 tcpsum;
1532
1533 tcpsum = offset << 16; /* sum start */
1534 tcpsum |= offset + skb->csum_offset; /* sum write */
1535
1536 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1537 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1538 ctrl |= UDPTCP;
1539
1540 if (tcpsum != sky2->tx_tcpsum) {
1541 sky2->tx_tcpsum = tcpsum;
1542
1543 le = get_tx_le(sky2);
1544 le->addr = cpu_to_le32(tcpsum);
1545 le->length = 0; /* initial checksum value */
1546 le->ctrl = 1; /* one packet */
1547 le->opcode = OP_TCPLISW | HW_OWNER;
1548 }
1d179332 1549 }
cd28ab6a
SH		 1550 }
1551
1552 le = get_tx_le(sky2);
f65b138c 1553 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1554 le->length = cpu_to_le16(len);
1555 le->ctrl = ctrl;
793b883e 1556 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1557
291ea614 1558 re = tx_le_re(sky2, le);
cd28ab6a 1559 re->skb = skb;
6cdbbdf3 1560 pci_unmap_addr_set(re, mapaddr, mapping);
291ea614 1561 pci_unmap_len_set(re, maplen, len);
cd28ab6a
SH		 1562
1563 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1564 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1565
1566 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1567 frag->size, PCI_DMA_TODEVICE);
36eb0c71 1568 addr64 = upper_32_bits(mapping);
793b883e
SH		 1569 if (addr64 != sky2->tx_addr64) {
1570 le = get_tx_le(sky2);
f65b138c 1571 le->addr = cpu_to_le32(addr64);
793b883e
SH		 1572 le->ctrl = 0;
1573 le->opcode = OP_ADDR64 | HW_OWNER;
1574 sky2->tx_addr64 = addr64;
cd28ab6a
SH		 1575 }
1576
1577 le = get_tx_le(sky2);
f65b138c 1578 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1579 le->length = cpu_to_le16(frag->size);
1580 le->ctrl = ctrl;
793b883e 1581 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1582
291ea614
SH		 1583 re = tx_le_re(sky2, le);
1584 re->skb = skb;
1585 pci_unmap_addr_set(re, mapaddr, mapping);
1586 pci_unmap_len_set(re, maplen, frag->size);
cd28ab6a 1587 }
6cdbbdf3 1588
cd28ab6a
SH		 1589 le->ctrl |= EOP;
1590
97bda706
SH		 1591 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1592 netif_stop_queue(dev);
b19666d9 1593
290d4de5 1594 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1595
cd28ab6a
SH		 1596 dev->trans_start = jiffies;
1597 return NETDEV_TX_OK;
1598}
1599
cd28ab6a 1600/*
793b883e
SH		 1601 * Free ring elements from starting at tx_cons until "done"
1602 *
1603 * NB: the hardware will tell us about partial completion of multi-part
291ea614 1604 * buffers so make sure not to free skb to early.
cd28ab6a 1605 */
d11c13e7 1606static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1607{
d11c13e7 1608 struct net_device *dev = sky2->netdev;
af2a58ac 1609 struct pci_dev *pdev = sky2->hw->pdev;
291ea614 1610 unsigned idx;
cd28ab6a 1611
0e3ff6aa 1612 BUG_ON(done >= TX_RING_SIZE);
2224795d 1613
291ea614
SH		 1614 for (idx = sky2->tx_cons; idx != done;
1615 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1616 struct sky2_tx_le *le = sky2->tx_le + idx;
1617 struct tx_ring_info *re = sky2->tx_ring + idx;
1618
1619 switch(le->opcode & ~HW_OWNER) {
1620 case OP_LARGESEND:
1621 case OP_PACKET:
1622 pci_unmap_single(pdev,
1623 pci_unmap_addr(re, mapaddr),
1624 pci_unmap_len(re, maplen),
1625 PCI_DMA_TODEVICE);
af2a58ac 1626 break;
291ea614
SH		 1627 case OP_BUFFER:
1628 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1629 pci_unmap_len(re, maplen),
734d1868 1630 PCI_DMA_TODEVICE);
291ea614
SH		 1631 break;
1632 }
1633
1634 if (le->ctrl & EOP) {
1635 if (unlikely(netif_msg_tx_done(sky2)))
1636 printk(KERN_DEBUG "%s: tx done %u\n",
1637 dev->name, idx);
3cf26753 1638
2bf56fe2 1639 sky2->net_stats.tx_packets++;
1640 sky2->net_stats.tx_bytes += re->skb->len;
1641
794b2bd2 1642 dev_kfree_skb_any(re->skb);
3cf26753 1643 sky2->tx_next = RING_NEXT(idx, TX_RING_SIZE);
cd28ab6a 1644 }
793b883e 1645 }
793b883e 1646
291ea614 1647 sky2->tx_cons = idx;
50432cb5
SH		 1648 smp_mb();
1649
22e11703 1650 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
cd28ab6a 1651 netif_wake_queue(dev);
cd28ab6a
SH		 1652}
1653
1654/* Cleanup all untransmitted buffers, assume transmitter not running */
2bb8c262 1655static void sky2_tx_clean(struct net_device *dev)
cd28ab6a 1656{
2bb8c262
SH		 1657 struct sky2_port *sky2 = netdev_priv(dev);
1658
1659 netif_tx_lock_bh(dev);
d11c13e7 1660 sky2_tx_complete(sky2, sky2->tx_prod);
2bb8c262 1661 netif_tx_unlock_bh(dev);
cd28ab6a
SH		 1662}
1663
1664/* Network shutdown */
1665static int sky2_down(struct net_device *dev)
1666{
1667 struct sky2_port *sky2 = netdev_priv(dev);
1668 struct sky2_hw *hw = sky2->hw;
1669 unsigned port = sky2->port;
1670 u16 ctrl;
e07b1aa8 1671 u32 imask;
cd28ab6a 1672
1b537565
SH		 1673 /* Never really got started! */
1674 if (!sky2->tx_le)
1675 return 0;
1676
cd28ab6a
SH		 1677 if (netif_msg_ifdown(sky2))
1678 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1679
018d1c66 1680 /* Stop more packets from being queued */
cd28ab6a
SH		 1681 netif_stop_queue(dev);
1682
bea3348e
SH		 1683 napi_disable(&hw->napi);
1684
ebc646f6
SH		 1685 /* Disable port IRQ */
1686 imask = sky2_read32(hw, B0_IMSK);
1687 imask &= ~portirq_msk[port];
1688 sky2_write32(hw, B0_IMSK, imask);
1689
d3bcfbeb 1690 sky2_gmac_reset(hw, port);
793b883e 1691
cd28ab6a
SH		 1692 /* Stop transmitter */
1693 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1694 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1695
1696 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1697 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1698
1699 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1700 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1701 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1702
1703 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1704
1705 /* Workaround shared GMAC reset */
793b883e
SH		 1706 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1707 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1708 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1709
1710 /* Disable Force Sync bit and Enable Alloc bit */
1711 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1712 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1713
1714 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1715 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1716 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1717
1718 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1719 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1720 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1721
1722 /* Reset the Tx prefetch units */
1723 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1724 PREF_UNIT_RST_SET);
1725
1726 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1727
6b1a3aef 1728 sky2_rx_stop(sky2);
cd28ab6a
SH		 1729
1730 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1731 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1732
d3bcfbeb
SH		 1733 sky2_phy_power(hw, port, 0);
1734
55d7b4e6
SH		 1735 netif_carrier_off(dev);
1736
d571b694 1737 /* turn off LED's */
cd28ab6a
SH		 1738 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1739
018d1c66
SH		 1740 synchronize_irq(hw->pdev->irq);
1741
2bb8c262 1742 sky2_tx_clean(dev);
cd28ab6a
SH		 1743 sky2_rx_clean(sky2);
1744
1745 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1746 sky2->rx_le, sky2->rx_le_map);
1747 kfree(sky2->rx_ring);
1748
1749 pci_free_consistent(hw->pdev,
1750 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1751 sky2->tx_le, sky2->tx_le_map);
1752 kfree(sky2->tx_ring);
1753
1b537565
SH		 1754 sky2->tx_le = NULL;
1755 sky2->rx_le = NULL;
1756
1757 sky2->rx_ring = NULL;
1758 sky2->tx_ring = NULL;
1759
cd28ab6a
SH		 1760 return 0;
1761}
1762
1763static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1764{
ea76e635 1765 if (hw->flags & SKY2_HW_FIBRE_PHY)
793b883e
SH		 1766 return SPEED_1000;
1767
05745c4a
SH		 1768 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1769 if (aux & PHY_M_PS_SPEED_100)
1770 return SPEED_100;
1771 else
1772 return SPEED_10;
1773 }
cd28ab6a
SH		 1774
1775 switch (aux & PHY_M_PS_SPEED_MSK) {
1776 case PHY_M_PS_SPEED_1000:
1777 return SPEED_1000;
1778 case PHY_M_PS_SPEED_100:
1779 return SPEED_100;
1780 default:
1781 return SPEED_10;
1782 }
1783}
1784
1785static void sky2_link_up(struct sky2_port *sky2)
1786{
1787 struct sky2_hw *hw = sky2->hw;
1788 unsigned port = sky2->port;
1789 u16 reg;
16ad91e1
SH		 1790 static const char *fc_name[] = {
1791 [FC_NONE] = "none",
1792 [FC_TX] = "tx",
1793 [FC_RX] = "rx",
1794 [FC_BOTH] = "both",
1795 };
cd28ab6a 1796
cd28ab6a 1797 /* enable Rx/Tx */
2eaba1a2 1798 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 1799 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1800 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 1801
1802 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1803
1804 netif_carrier_on(sky2->netdev);
cd28ab6a 1805
75e80683 1806 mod_timer(&hw->watchdog_timer, jiffies + 1);
32c2c300 1807
cd28ab6a 1808 /* Turn on link LED */
793b883e 1809 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1810 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1811
ea76e635 1812 if (hw->flags & SKY2_HW_NEWER_PHY) {
793b883e 1813 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
ed6d32c7
SH		 1814 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1815
1816 switch(sky2->speed) {
1817 case SPEED_10:
1818 led |= PHY_M_LEDC_INIT_CTRL(7);
1819 break;
1820
1821 case SPEED_100:
1822 led |= PHY_M_LEDC_STA1_CTRL(7);
1823 break;
1824
1825 case SPEED_1000:
1826 led |= PHY_M_LEDC_STA0_CTRL(7);
1827 break;
1828 }
793b883e
SH		 1829
1830 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
ed6d32c7 1831 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
793b883e
SH		 1832 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1833 }
1834
cd28ab6a
SH		 1835 if (netif_msg_link(sky2))
1836 printk(KERN_INFO PFX
d571b694 1837 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1838 sky2->netdev->name, sky2->speed,
1839 sky2->duplex == DUPLEX_FULL ? "full" : "half",
16ad91e1 1840 fc_name[sky2->flow_status]);
cd28ab6a
SH		 1841}
1842
1843static void sky2_link_down(struct sky2_port *sky2)
1844{
1845 struct sky2_hw *hw = sky2->hw;
1846 unsigned port = sky2->port;
1847 u16 reg;
1848
1849 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1850
1851 reg = gma_read16(hw, port, GM_GP_CTRL);
1852 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1853 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 1854
cd28ab6a 1855 netif_carrier_off(sky2->netdev);
cd28ab6a
SH		 1856
1857 /* Turn on link LED */
1858 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1859
1860 if (netif_msg_link(sky2))
1861 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2eaba1a2 1862
cd28ab6a
SH		 1863 sky2_phy_init(hw, port);
1864}
1865
16ad91e1
SH		 1866static enum flow_control sky2_flow(int rx, int tx)
1867{
1868 if (rx)
1869 return tx ? FC_BOTH : FC_RX;
1870 else
1871 return tx ? FC_TX : FC_NONE;
1872}
1873
793b883e
SH		 1874static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1875{
1876 struct sky2_hw *hw = sky2->hw;
1877 unsigned port = sky2->port;
da4c1ff4 1878 u16 advert, lpa;
793b883e 1879
da4c1ff4 1880 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
793b883e 1881 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
793b883e
SH		 1882 if (lpa & PHY_M_AN_RF) {
1883 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1884 return -1;
1885 }
1886
793b883e
SH		 1887 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1888 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1889 sky2->netdev->name);
1890 return -1;
1891 }
1892
793b883e 1893 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 1894 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e 1895
da4c1ff4
SH		 1896 /* Since the pause result bits seem to in different positions on
1897 * different chips. look at registers.
1898 */
ea76e635 1899 if (hw->flags & SKY2_HW_FIBRE_PHY) {
da4c1ff4
SH		 1900 /* Shift for bits in fiber PHY */
1901 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
1902 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
1903
1904 if (advert & ADVERTISE_1000XPAUSE)
1905 advert |= ADVERTISE_PAUSE_CAP;
1906 if (advert & ADVERTISE_1000XPSE_ASYM)
1907 advert |= ADVERTISE_PAUSE_ASYM;
1908 if (lpa & LPA_1000XPAUSE)
1909 lpa |= LPA_PAUSE_CAP;
1910 if (lpa & LPA_1000XPAUSE_ASYM)
1911 lpa |= LPA_PAUSE_ASYM;
1912 }
793b883e 1913
da4c1ff4
SH		 1914 sky2->flow_status = FC_NONE;
1915 if (advert & ADVERTISE_PAUSE_CAP) {
1916 if (lpa & LPA_PAUSE_CAP)
1917 sky2->flow_status = FC_BOTH;
1918 else if (advert & ADVERTISE_PAUSE_ASYM)
1919 sky2->flow_status = FC_RX;
1920 } else if (advert & ADVERTISE_PAUSE_ASYM) {
1921 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
1922 sky2->flow_status = FC_TX;
1923 }
793b883e 1924
16ad91e1 1925 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
93745494 1926 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
16ad91e1 1927 sky2->flow_status = FC_NONE;
2eaba1a2 1928
da4c1ff4 1929 if (sky2->flow_status & FC_TX)
793b883e
SH		 1930 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1931 else
1932 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1933
1934 return 0;
1935}
cd28ab6a 1936
e07b1aa8
SH		 1937/* Interrupt from PHY */
1938static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 1939{
e07b1aa8
SH		 1940 struct net_device *dev = hw->dev[port];
1941 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 1942 u16 istatus, phystat;
1943
ebc646f6
SH		 1944 if (!netif_running(dev))
1945 return;
1946
e07b1aa8
SH		 1947 spin_lock(&sky2->phy_lock);
1948 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1949 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1950
cd28ab6a
SH		 1951 if (netif_msg_intr(sky2))
1952 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1953 sky2->netdev->name, istatus, phystat);
1954
2eaba1a2 1955 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
793b883e
SH		 1956 if (sky2_autoneg_done(sky2, phystat) == 0)
1957 sky2_link_up(sky2);
1958 goto out;
1959 }
cd28ab6a 1960
793b883e
SH		 1961 if (istatus & PHY_M_IS_LSP_CHANGE)
1962 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 1963
793b883e
SH		 1964 if (istatus & PHY_M_IS_DUP_CHANGE)
1965 sky2->duplex =
1966 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 1967
793b883e
SH		 1968 if (istatus & PHY_M_IS_LST_CHANGE) {
1969 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 1970 sky2_link_up(sky2);
793b883e
SH		 1971 else
1972 sky2_link_down(sky2);
cd28ab6a 1973 }
793b883e 1974out:
e07b1aa8 1975 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 1976}
1977
62335ab0 1978/* Transmit timeout is only called if we are running, carrier is up
302d1252
SH		 1979 * and tx queue is full (stopped).
1980 */
cd28ab6a
SH		 1981static void sky2_tx_timeout(struct net_device *dev)
1982{
1983 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3 1984 struct sky2_hw *hw = sky2->hw;
cd28ab6a
SH		 1985
1986 if (netif_msg_timer(sky2))
1987 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1988
8f24664d 1989 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
62335ab0
SH		 1990 dev->name, sky2->tx_cons, sky2->tx_prod,
1991 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
1992 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
8f24664d 1993
81906791
SH		 1994 /* can't restart safely under softirq */
1995 schedule_work(&hw->restart_work);
cd28ab6a
SH		 1996}
1997
1998static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1999{
6b1a3aef
SH		 2000 struct sky2_port *sky2 = netdev_priv(dev);
2001 struct sky2_hw *hw = sky2->hw;
b628ed98 2002 unsigned port = sky2->port;
6b1a3aef
SH		 2003 int err;
2004 u16 ctl, mode;
e07b1aa8 2005 u32 imask;
cd28ab6a
SH		 2006
2007 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2008 return -EINVAL;
2009
05745c4a
SH		 2010 if (new_mtu > ETH_DATA_LEN &&
2011 (hw->chip_id == CHIP_ID_YUKON_FE ||
2012 hw->chip_id == CHIP_ID_YUKON_FE_P))
d2adf4f6
SH		 2013 return -EINVAL;
2014
6b1a3aef
SH		 2015 if (!netif_running(dev)) {
2016 dev->mtu = new_mtu;
2017 return 0;
2018 }
2019
e07b1aa8 2020 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef
SH		 2021 sky2_write32(hw, B0_IMSK, 0);
2022
018d1c66
SH		 2023 dev->trans_start = jiffies; /* prevent tx timeout */
2024 netif_stop_queue(dev);
bea3348e 2025 napi_disable(&hw->napi);
018d1c66 2026
e07b1aa8
SH		 2027 synchronize_irq(hw->pdev->irq);
2028
e0c28116 2029 if (sky2_read8(hw, B2_E_0) == 0)
69161611 2030 sky2_set_tx_stfwd(hw, port);
b628ed98
SH		 2031
2032 ctl = gma_read16(hw, port, GM_GP_CTRL);
2033 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
6b1a3aef
SH		 2034 sky2_rx_stop(sky2);
2035 sky2_rx_clean(sky2);
cd28ab6a
SH		 2036
2037 dev->mtu = new_mtu;
14d0263f 2038
6b1a3aef
SH		 2039 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2040 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2041
2042 if (dev->mtu > ETH_DATA_LEN)
2043 mode |= GM_SMOD_JUMBO_ENA;
2044
b628ed98 2045 gma_write16(hw, port, GM_SERIAL_MODE, mode);
cd28ab6a 2046
b628ed98 2047 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 2048
6b1a3aef 2049 err = sky2_rx_start(sky2);
e07b1aa8 2050 sky2_write32(hw, B0_IMSK, imask);
018d1c66 2051
bea3348e
SH		 2052 /* Unconditionally re-enable NAPI because even if we
2053 * call dev_close() that will do a napi_disable().
2054 */
2055 napi_enable(&hw->napi);
2056
1b537565
SH		 2057 if (err)
2058 dev_close(dev);
2059 else {
b628ed98 2060 gma_write16(hw, port, GM_GP_CTRL, ctl);
1b537565 2061
1b537565
SH		 2062 netif_wake_queue(dev);
2063 }
2064
cd28ab6a
SH		 2065 return err;
2066}
2067
14d0263f
SH		 2068/* For small just reuse existing skb for next receive */
2069static struct sk_buff *receive_copy(struct sky2_port *sky2,
2070 const struct rx_ring_info *re,
2071 unsigned length)
2072{
2073 struct sk_buff *skb;
2074
2075 skb = netdev_alloc_skb(sky2->netdev, length + 2);
2076 if (likely(skb)) {
2077 skb_reserve(skb, 2);
2078 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2079 length, PCI_DMA_FROMDEVICE);
d626f62b 2080 skb_copy_from_linear_data(re->skb, skb->data, length);
14d0263f
SH		 2081 skb->ip_summed = re->skb->ip_summed;
2082 skb->csum = re->skb->csum;
2083 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2084 length, PCI_DMA_FROMDEVICE);
2085 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 2086 skb_put(skb, length);
14d0263f
SH		 2087 }
2088 return skb;
2089}
2090
2091/* Adjust length of skb with fragments to match received data */
2092static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2093 unsigned int length)
2094{
2095 int i, num_frags;
2096 unsigned int size;
2097
2098 /* put header into skb */
2099 size = min(length, hdr_space);
2100 skb->tail += size;
2101 skb->len += size;
2102 length -= size;
2103
2104 num_frags = skb_shinfo(skb)->nr_frags;
2105 for (i = 0; i < num_frags; i++) {
2106 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2107
2108 if (length == 0) {
2109 /* don't need this page */
2110 __free_page(frag->page);
2111 --skb_shinfo(skb)->nr_frags;
2112 } else {
2113 size = min(length, (unsigned) PAGE_SIZE);
2114
2115 frag->size = size;
2116 skb->data_len += size;
2117 skb->truesize += size;
2118 skb->len += size;
2119 length -= size;
2120 }
2121 }
2122}
2123
2124/* Normal packet - take skb from ring element and put in a new one */
2125static struct sk_buff *receive_new(struct sky2_port *sky2,
2126 struct rx_ring_info *re,
2127 unsigned int length)
2128{
2129 struct sk_buff *skb, *nskb;
2130 unsigned hdr_space = sky2->rx_data_size;
2131
14d0263f
SH		 2132 /* Don't be tricky about reusing pages (yet) */
2133 nskb = sky2_rx_alloc(sky2);
2134 if (unlikely(!nskb))
2135 return NULL;
2136
2137 skb = re->skb;
2138 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2139
2140 prefetch(skb->data);
2141 re->skb = nskb;
2142 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
2143
2144 if (skb_shinfo(skb)->nr_frags)
2145 skb_put_frags(skb, hdr_space, length);
2146 else
489b10c1 2147 skb_put(skb, length);
14d0263f
SH		 2148 return skb;
2149}
2150
cd28ab6a
SH		 2151/*
2152 * Receive one packet.
d571b694 2153 * For larger packets, get new buffer.
cd28ab6a 2154 */
497d7c86 2155static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 2156 u16 length, u32 status)
2157{
497d7c86 2158 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 2159 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 2160 struct sk_buff *skb = NULL;
d6532232
SH		 2161 u16 count = (status & GMR_FS_LEN) >> 16;
2162
2163#ifdef SKY2_VLAN_TAG_USED
2164 /* Account for vlan tag */
2165 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2166 count -= VLAN_HLEN;
2167#endif
cd28ab6a
SH		 2168
2169 if (unlikely(netif_msg_rx_status(sky2)))
2170 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
497d7c86 2171 dev->name, sky2->rx_next, status, length);
cd28ab6a 2172
793b883e 2173 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 2174 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 2175
3b12e014
SH		 2176 /* This chip has hardware problems that generates bogus status.
2177 * So do only marginal checking and expect higher level protocols
2178 * to handle crap frames.
2179 */
2180 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2181 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2182 length != count)
2183 goto okay;
2184
42eeea01 2185 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 2186 goto error;
2187
42eeea01
SH		 2188 if (!(status & GMR_FS_RX_OK))
2189 goto resubmit;
2190
d6532232
SH		 2191 /* if length reported by DMA does not match PHY, packet was truncated */
2192 if (length != count)
3b12e014 2193 goto len_error;
71749531 2194
3b12e014 2195okay:
14d0263f
SH		 2196 if (length < copybreak)
2197 skb = receive_copy(sky2, re, length);
2198 else
2199 skb = receive_new(sky2, re, length);
793b883e 2200resubmit:
14d0263f 2201 sky2_rx_submit(sky2, re);
79e57d32 2202
cd28ab6a
SH		 2203 return skb;
2204
3b12e014 2205len_error:
71749531
SH		 2206 /* Truncation of overlength packets
2207 causes PHY length to not match MAC length */
2208 ++sky2->net_stats.rx_length_errors;
d6532232 2209 if (netif_msg_rx_err(sky2) && net_ratelimit())
3b12e014
SH		 2210 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2211 dev->name, status, length);
d6532232 2212 goto resubmit;
71749531 2213
cd28ab6a 2214error:
6e15b712 2215 ++sky2->net_stats.rx_errors;
b6d77734 2216 if (status & GMR_FS_RX_FF_OV) {
a79abdc6 2217 sky2->net_stats.rx_over_errors++;
b6d77734
SH		 2218 goto resubmit;
2219 }
6e15b712 2220
3be92a70 2221 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a 2222 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
497d7c86 2223 dev->name, status, length);
793b883e
SH		 2224
2225 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
cd28ab6a
SH		 2226 sky2->net_stats.rx_length_errors++;
2227 if (status & GMR_FS_FRAGMENT)
2228 sky2->net_stats.rx_frame_errors++;
2229 if (status & GMR_FS_CRC_ERR)
2230 sky2->net_stats.rx_crc_errors++;
79e57d32 2231
793b883e 2232 goto resubmit;
cd28ab6a
SH		 2233}
2234
e07b1aa8
SH		 2235/* Transmit complete */
2236static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2237{
e07b1aa8 2238 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2239
e07b1aa8 2240 if (netif_running(dev)) {
2bb8c262 2241 netif_tx_lock(dev);
e07b1aa8 2242 sky2_tx_complete(sky2, last);
2bb8c262 2243 netif_tx_unlock(dev);
2224795d 2244 }
cd28ab6a
SH		 2245}
2246
e07b1aa8
SH		 2247/* Process status response ring */
2248static int sky2_status_intr(struct sky2_hw *hw, int to_do)
cd28ab6a 2249{
e07b1aa8 2250 int work_done = 0;
55c9dd35 2251 unsigned rx[2] = { 0, 0 };
e71ebd73 2252 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
a8fd6266 2253
af2a58ac 2254 rmb();
bea86103 2255
e71ebd73 2256 while (hw->st_idx != hwidx) {
55c9dd35 2257 struct sky2_port *sky2;
13210ce5 2258 struct sky2_status_le *le = hw->st_le + hw->st_idx;
69161611 2259 unsigned port = le->css & CSS_LINK_BIT;
13210ce5 2260 struct net_device *dev;
cd28ab6a 2261 struct sk_buff *skb;
cd28ab6a
SH		 2262 u32 status;
2263 u16 length;
2264
cb5d9547 2265 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 2266
69161611 2267 dev = hw->dev[port];
13210ce5 2268 sky2 = netdev_priv(dev);
f65b138c
SH		 2269 length = le16_to_cpu(le->length);
2270 status = le32_to_cpu(le->status);
cd28ab6a 2271
e71ebd73 2272 switch (le->opcode & ~HW_OWNER) {
cd28ab6a 2273 case OP_RXSTAT:
55c9dd35 2274 ++rx[port];
497d7c86 2275 skb = sky2_receive(dev, length, status);
3225b919
SH		 2276 if (unlikely(!skb)) {
2277 sky2->net_stats.rx_dropped++;
55c9dd35 2278 break;
3225b919 2279 }
13210ce5 2280
69161611 2281 /* This chip reports checksum status differently */
05745c4a 2282 if (hw->flags & SKY2_HW_NEW_LE) {
69161611
SH		 2283 if (sky2->rx_csum &&
2284 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2285 (le->css & CSS_TCPUDPCSOK))
2286 skb->ip_summed = CHECKSUM_UNNECESSARY;
2287 else
2288 skb->ip_summed = CHECKSUM_NONE;
2289 }
2290
13210ce5 2291 skb->protocol = eth_type_trans(skb, dev);
2bf56fe2 2292 sky2->net_stats.rx_packets++;
2293 sky2->net_stats.rx_bytes += skb->len;
13210ce5
SH		 2294 dev->last_rx = jiffies;
2295
d1f13708
SH		 2296#ifdef SKY2_VLAN_TAG_USED
2297 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2298 vlan_hwaccel_receive_skb(skb,
2299 sky2->vlgrp,
2300 be16_to_cpu(sky2->rx_tag));
2301 } else
2302#endif
cd28ab6a 2303 netif_receive_skb(skb);
13210ce5 2304
22e11703 2305 /* Stop after net poll weight */
13210ce5
SH		 2306 if (++work_done >= to_do)
2307 goto exit_loop;
cd28ab6a
SH		 2308 break;
2309
d1f13708
SH		 2310#ifdef SKY2_VLAN_TAG_USED
2311 case OP_RXVLAN:
2312 sky2->rx_tag = length;
2313 break;
2314
2315 case OP_RXCHKSVLAN:
2316 sky2->rx_tag = length;
2317 /* fall through */
2318#endif
cd28ab6a 2319 case OP_RXCHKS:
87418307
SH		 2320 if (!sky2->rx_csum)
2321 break;
2322
05745c4a
SH		 2323 /* If this happens then driver assuming wrong format */
2324 if (unlikely(hw->flags & SKY2_HW_NEW_LE)) {
2325 if (net_ratelimit())
2326 printk(KERN_NOTICE "%s: unexpected"
2327 " checksum status\n",
2328 dev->name);
69161611 2329 break;
05745c4a 2330 }
69161611 2331
87418307
SH		 2332 /* Both checksum counters are programmed to start at
2333 * the same offset, so unless there is a problem they
2334 * should match. This failure is an early indication that
2335 * hardware receive checksumming won't work.
2336 */
2337 if (likely(status >> 16 == (status & 0xffff))) {
2338 skb = sky2->rx_ring[sky2->rx_next].skb;
2339 skb->ip_summed = CHECKSUM_COMPLETE;
2340 skb->csum = status & 0xffff;
2341 } else {
2342 printk(KERN_NOTICE PFX "%s: hardware receive "
2343 "checksum problem (status = %#x)\n",
2344 dev->name, status);
2345 sky2->rx_csum = 0;
2346 sky2_write32(sky2->hw,
69161611 2347 Q_ADDR(rxqaddr[port], Q_CSR),
87418307
SH		 2348 BMU_DIS_RX_CHKSUM);
2349 }
cd28ab6a
SH		 2350 break;
2351
2352 case OP_TXINDEXLE:
13b97b74 2353 /* TX index reports status for both ports */
f55925d7
SH		 2354 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2355 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2356 if (hw->dev[1])
2357 sky2_tx_done(hw->dev[1],
2358 ((status >> 24) & 0xff)
2359 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2360 break;
2361
cd28ab6a
SH		 2362 default:
2363 if (net_ratelimit())
793b883e 2364 printk(KERN_WARNING PFX
e71ebd73 2365 "unknown status opcode 0x%x\n", le->opcode);
cd28ab6a 2366 }
13210ce5 2367 }
cd28ab6a 2368
fe2a24df
SH		 2369 /* Fully processed status ring so clear irq */
2370 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2371
13210ce5 2372exit_loop:
55c9dd35
SH		 2373 if (rx[0])
2374 sky2_rx_update(netdev_priv(hw->dev[0]), Q_R1);
22e11703 2375
55c9dd35
SH		 2376 if (rx[1])
2377 sky2_rx_update(netdev_priv(hw->dev[1]), Q_R2);
22e11703 2378
e07b1aa8 2379 return work_done;
cd28ab6a
SH		 2380}
2381
2382static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2383{
2384 struct net_device *dev = hw->dev[port];
2385
3be92a70
SH		 2386 if (net_ratelimit())
2387 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2388 dev->name, status);
cd28ab6a
SH		 2389
2390 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2391 if (net_ratelimit())
2392 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2393 dev->name);
cd28ab6a
SH		 2394 /* Clear IRQ */
2395 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2396 }
2397
2398 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2399 if (net_ratelimit())
2400 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2401 dev->name);
cd28ab6a
SH		 2402
2403 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2404 }
2405
2406 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2407 if (net_ratelimit())
2408 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2409 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2410 }
2411
2412 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2413 if (net_ratelimit())
2414 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2415 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2416 }
2417
2418 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2419 if (net_ratelimit())
2420 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2421 dev->name);
cd28ab6a
SH		 2422 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2423 }
2424}
2425
2426static void sky2_hw_intr(struct sky2_hw *hw)
2427{
2428 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2429
793b883e 2430 if (status & Y2_IS_TIST_OV)
cd28ab6a 2431 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2432
2433 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2434 u16 pci_err;
2435
56a645cc 2436 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70 2437 if (net_ratelimit())
b02a9258
SH		 2438 dev_err(&hw->pdev->dev, "PCI hardware error (0x%x)\n",
2439 pci_err);
cd28ab6a
SH		 2440
2441 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc 2442 sky2_pci_write16(hw, PCI_STATUS,
91aeb3ed 2443 pci_err | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 2444 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2445 }
2446
2447 if (status & Y2_IS_PCI_EXP) {
d571b694 2448 /* PCI-Express uncorrectable Error occurred */
793b883e
SH		 2449 u32 pex_err;
2450
7bd656d1 2451 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
cd28ab6a 2452
3be92a70 2453 if (net_ratelimit())
b02a9258
SH		 2454 dev_err(&hw->pdev->dev, "PCI Express error (0x%x)\n",
2455 pex_err);
cd28ab6a
SH		 2456
2457 /* clear the interrupt */
2458 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
7bd656d1
SH		 2459 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
2460 0xffffffffUL);
cd28ab6a
SH		 2461 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2462
7bd656d1 2463 if (pex_err & PEX_FATAL_ERRORS) {
cd28ab6a
SH		 2464 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2465 hwmsk &= ~Y2_IS_PCI_EXP;
2466 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2467 }
2468 }
2469
2470 if (status & Y2_HWE_L1_MASK)
2471 sky2_hw_error(hw, 0, status);
2472 status >>= 8;
2473 if (status & Y2_HWE_L1_MASK)
2474 sky2_hw_error(hw, 1, status);
2475}
2476
2477static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2478{
2479 struct net_device *dev = hw->dev[port];
2480 struct sky2_port *sky2 = netdev_priv(dev);
2481 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2482
2483 if (netif_msg_intr(sky2))
2484 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2485 dev->name, status);
2486
a3caeada
SH		 2487 if (status & GM_IS_RX_CO_OV)
2488 gma_read16(hw, port, GM_RX_IRQ_SRC);
2489
2490 if (status & GM_IS_TX_CO_OV)
2491 gma_read16(hw, port, GM_TX_IRQ_SRC);
2492
cd28ab6a
SH		 2493 if (status & GM_IS_RX_FF_OR) {
2494 ++sky2->net_stats.rx_fifo_errors;
2495 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2496 }
2497
2498 if (status & GM_IS_TX_FF_UR) {
2499 ++sky2->net_stats.tx_fifo_errors;
2500 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2501 }
cd28ab6a
SH		 2502}
2503
40b01727
SH		 2504/* This should never happen it is a bug. */
2505static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2506 u16 q, unsigned ring_size)
d257924e
SH		 2507{
2508 struct net_device *dev = hw->dev[port];
2509 struct sky2_port *sky2 = netdev_priv(dev);
40b01727
SH		 2510 unsigned idx;
2511 const u64 *le = (q == Q_R1 || q == Q_R2)
2512 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
d257924e 2513
40b01727
SH		 2514 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2515 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2516 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2517 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
d257924e 2518
40b01727 2519 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
d257924e 2520}
cd28ab6a 2521
75e80683
SH		 2522static int sky2_rx_hung(struct net_device *dev)
2523{
2524 struct sky2_port *sky2 = netdev_priv(dev);
2525 struct sky2_hw *hw = sky2->hw;
2526 unsigned port = sky2->port;
2527 unsigned rxq = rxqaddr[port];
2528 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2529 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2530 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2531 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2532
2533 /* If idle and MAC or PCI is stuck */
2534 if (sky2->check.last == dev->last_rx &&
2535 ((mac_rp == sky2->check.mac_rp &&
2536 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2537 /* Check if the PCI RX hang */
2538 (fifo_rp == sky2->check.fifo_rp &&
2539 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2540 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2541 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2542 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2543 return 1;
2544 } else {
2545 sky2->check.last = dev->last_rx;
2546 sky2->check.mac_rp = mac_rp;
2547 sky2->check.mac_lev = mac_lev;
2548 sky2->check.fifo_rp = fifo_rp;
2549 sky2->check.fifo_lev = fifo_lev;
2550 return 0;
2551 }
2552}
2553
32c2c300 2554static void sky2_watchdog(unsigned long arg)
d27ed387 2555{
01bd7564 2556 struct sky2_hw *hw = (struct sky2_hw *) arg;
d27ed387 2557
75e80683 2558 /* Check for lost IRQ once a second */
32c2c300 2559 if (sky2_read32(hw, B0_ISRC)) {
bea3348e 2560 napi_schedule(&hw->napi);
75e80683
SH		 2561 } else {
2562 int i, active = 0;
2563
2564 for (i = 0; i < hw->ports; i++) {
bea3348e 2565 struct net_device *dev = hw->dev[i];
75e80683
SH		 2566 if (!netif_running(dev))
2567 continue;
2568 ++active;
2569
2570 /* For chips with Rx FIFO, check if stuck */
e0c28116 2571 if ((hw->flags & SKY2_HW_FIFO_HANG_CHECK) &&
75e80683
SH		 2572 sky2_rx_hung(dev)) {
2573 pr_info(PFX "%s: receiver hang detected\n",
2574 dev->name);
2575 schedule_work(&hw->restart_work);
2576 return;
2577 }
2578 }
2579
2580 if (active == 0)
2581 return;
32c2c300 2582 }
01bd7564 2583
75e80683 2584 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
d27ed387
SH		 2585}
2586
40b01727
SH		 2587/* Hardware/software error handling */
2588static void sky2_err_intr(struct sky2_hw *hw, u32 status)
cd28ab6a 2589{
40b01727
SH		 2590 if (net_ratelimit())
2591 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
cd28ab6a 2592
1e5f1283
SH		 2593 if (status & Y2_IS_HW_ERR)
2594 sky2_hw_intr(hw);
d257924e 2595
1e5f1283
SH		 2596 if (status & Y2_IS_IRQ_MAC1)
2597 sky2_mac_intr(hw, 0);
cd28ab6a 2598
1e5f1283
SH		 2599 if (status & Y2_IS_IRQ_MAC2)
2600 sky2_mac_intr(hw, 1);
cd28ab6a 2601
1e5f1283 2602 if (status & Y2_IS_CHK_RX1)
40b01727 2603 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
d257924e 2604
1e5f1283 2605 if (status & Y2_IS_CHK_RX2)
40b01727 2606 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
d257924e 2607
1e5f1283 2608 if (status & Y2_IS_CHK_TXA1)
40b01727 2609 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
d257924e 2610
1e5f1283 2611 if (status & Y2_IS_CHK_TXA2)
40b01727
SH		 2612 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2613}
2614
bea3348e 2615static int sky2_poll(struct napi_struct *napi, int work_limit)
40b01727 2616{
bea3348e 2617 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
40b01727 2618 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
bea3348e 2619 int work_done;
40b01727
SH		 2620
2621 if (unlikely(status & Y2_IS_ERROR))
2622 sky2_err_intr(hw, status);
2623
2624 if (status & Y2_IS_IRQ_PHY1)
2625 sky2_phy_intr(hw, 0);
2626
2627 if (status & Y2_IS_IRQ_PHY2)
2628 sky2_phy_intr(hw, 1);
cd28ab6a 2629
bea3348e 2630 work_done = sky2_status_intr(hw, work_limit);
86fba634 2631
5c11ce70 2632 /* More work? */
bea3348e
SH		 2633 if (hw->st_idx == sky2_read16(hw, STAT_PUT_IDX)) {
2634 /* Bug/Errata workaround?
2635 * Need to kick the TX irq moderation timer.
2636 */
2637 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_START) {
2638 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2639 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2640 }
5c11ce70 2641
bea3348e
SH		 2642 napi_complete(napi);
2643 sky2_read32(hw, B0_Y2_SP_LISR);
fe2a24df 2644 }
bea3348e 2645 return work_done;
e07b1aa8
SH		 2646}
2647
7d12e780 2648static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2649{
2650 struct sky2_hw *hw = dev_id;
e07b1aa8
SH		 2651 u32 status;
2652
2653 /* Reading this mask interrupts as side effect */
2654 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2655 if (status == 0 || status == ~0)
2656 return IRQ_NONE;
793b883e 2657
e07b1aa8 2658 prefetch(&hw->st_le[hw->st_idx]);
bea3348e
SH		 2659
2660 napi_schedule(&hw->napi);
793b883e 2661
cd28ab6a
SH		 2662 return IRQ_HANDLED;
2663}
2664
2665#ifdef CONFIG_NET_POLL_CONTROLLER
2666static void sky2_netpoll(struct net_device *dev)
2667{
2668 struct sky2_port *sky2 = netdev_priv(dev);
2669
bea3348e 2670 napi_schedule(&sky2->hw->napi);
cd28ab6a
SH		 2671}
2672#endif
2673
2674/* Chip internal frequency for clock calculations */
05745c4a 2675static u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2676{
793b883e 2677 switch (hw->chip_id) {
cd28ab6a 2678 case CHIP_ID_YUKON_EC:
5a5b1ea0 2679 case CHIP_ID_YUKON_EC_U:
93745494 2680 case CHIP_ID_YUKON_EX:
05745c4a
SH		 2681 return 125;
2682
cd28ab6a 2683 case CHIP_ID_YUKON_FE:
05745c4a
SH		 2684 return 100;
2685
2686 case CHIP_ID_YUKON_FE_P:
2687 return 50;
2688
2689 case CHIP_ID_YUKON_XL:
2690 return 156;
2691
2692 default:
2693 BUG();
cd28ab6a
SH		 2694 }
2695}
2696
fb17358f 2697static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2698{
fb17358f 2699 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2700}
2701
fb17358f 2702static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2703{
fb17358f 2704 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2705}
2706
fb17358f 2707
e3173832 2708static int __devinit sky2_init(struct sky2_hw *hw)
cd28ab6a 2709{
b89165f2 2710 u8 t8;
cd28ab6a 2711
451af335
SH		 2712 /* Enable all clocks */
2713 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2714
cd28ab6a 2715 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2716
cd28ab6a 2717 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
ea76e635
SH		 2718 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2719
2720 switch(hw->chip_id) {
2721 case CHIP_ID_YUKON_XL:
2722 hw->flags = SKY2_HW_GIGABIT
e0c28116
SH		 2723 | SKY2_HW_NEWER_PHY;
2724 if (hw->chip_rev < 3)
2725 hw->flags |= SKY2_HW_FIFO_HANG_CHECK;
2726
ea76e635
SH		 2727 break;
2728
2729 case CHIP_ID_YUKON_EC_U:
2730 hw->flags = SKY2_HW_GIGABIT
2731 | SKY2_HW_NEWER_PHY
2732 | SKY2_HW_ADV_POWER_CTL;
2733 break;
2734
2735 case CHIP_ID_YUKON_EX:
2736 hw->flags = SKY2_HW_GIGABIT
2737 | SKY2_HW_NEWER_PHY
2738 | SKY2_HW_NEW_LE
2739 | SKY2_HW_ADV_POWER_CTL;
2740
2741 /* New transmit checksum */
2742 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2743 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2744 break;
2745
2746 case CHIP_ID_YUKON_EC:
2747 /* This rev is really old, and requires untested workarounds */
2748 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2749 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2750 return -EOPNOTSUPP;
2751 }
e0c28116 2752 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_FIFO_HANG_CHECK;
ea76e635
SH		 2753 break;
2754
2755 case CHIP_ID_YUKON_FE:
ea76e635
SH		 2756 break;
2757
05745c4a
SH		 2758 case CHIP_ID_YUKON_FE_P:
2759 hw->flags = SKY2_HW_NEWER_PHY
2760 | SKY2_HW_NEW_LE
2761 | SKY2_HW_AUTO_TX_SUM
2762 | SKY2_HW_ADV_POWER_CTL;
2763 break;
ea76e635 2764 default:
b02a9258
SH		 2765 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2766 hw->chip_id);
cd28ab6a
SH		 2767 return -EOPNOTSUPP;
2768 }
2769
ea76e635
SH		 2770 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2771 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
2772 hw->flags |= SKY2_HW_FIBRE_PHY;
290d4de5 2773
290d4de5 2774
e3173832
SH		 2775 hw->ports = 1;
2776 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2777 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2778 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2779 ++hw->ports;
2780 }
2781
2782 return 0;
2783}
2784
2785static void sky2_reset(struct sky2_hw *hw)
2786{
2787 u16 status;
2788 int i;
2789
cd28ab6a 2790 /* disable ASF */
4f44d8ba
SH		 2791 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2792 status = sky2_read16(hw, HCU_CCSR);
2793 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2794 HCU_CCSR_UC_STATE_MSK);
2795 sky2_write16(hw, HCU_CCSR, status);
2796 } else
2797 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2798 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
cd28ab6a
SH		 2799
2800 /* do a SW reset */
2801 sky2_write8(hw, B0_CTST, CS_RST_SET);
2802 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2803
2804 /* clear PCI errors, if any */
56a645cc 2805 status = sky2_pci_read16(hw, PCI_STATUS);
2d42d21f 2806
cd28ab6a 2807 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc
SH		 2808 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2809
cd28ab6a
SH		 2810
2811 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2812
2813 /* clear any PEX errors */
7bd656d1
SH		 2814 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
2815 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2816
cd28ab6a 2817
ae306cca 2818 sky2_power_on(hw);
cd28ab6a
SH		 2819
2820 for (i = 0; i < hw->ports; i++) {
2821 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2822 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
69161611
SH		 2823
2824 if (hw->chip_id == CHIP_ID_YUKON_EX)
2825 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
2826 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
2827 | GMC_BYP_RETR_ON);
cd28ab6a
SH		 2828 }
2829
2830 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2831
793b883e
SH		 2832 /* Clear I2C IRQ noise */
2833 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2834
2835 /* turn off hardware timer (unused) */
2836 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2837 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2838
cd28ab6a
SH		 2839 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2840
69634ee7
SH		 2841 /* Turn off descriptor polling */
2842 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2843
2844 /* Turn off receive timestamp */
2845 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2846 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2847
2848 /* enable the Tx Arbiters */
2849 for (i = 0; i < hw->ports; i++)
2850 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2851
2852 /* Initialize ram interface */
2853 for (i = 0; i < hw->ports; i++) {
793b883e 2854 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2855
2856 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2857 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2858 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2859 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2860 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2861 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2862 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2863 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2864 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2865 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2866 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2867 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2868 }
2869
7bd656d1 2870 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
cd28ab6a 2871
cd28ab6a 2872 for (i = 0; i < hw->ports; i++)
d3bcfbeb 2873 sky2_gmac_reset(hw, i);
cd28ab6a 2874
cd28ab6a
SH		 2875 memset(hw->st_le, 0, STATUS_LE_BYTES);
2876 hw->st_idx = 0;
2877
2878 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2879 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2880
2881 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 2882 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 2883
2884 /* Set the list last index */
793b883e 2885 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 2886
290d4de5
SH		 2887 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2888 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 2889
290d4de5
SH		 2890 /* set Status-FIFO ISR watermark */
2891 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2892 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2893 else
2894 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 2895
290d4de5 2896 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 2897 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2898 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 2899
793b883e 2900 /* enable status unit */
cd28ab6a
SH		 2901 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2902
2903 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2904 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2905 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
e3173832
SH		 2906}
2907
81906791
SH		 2908static void sky2_restart(struct work_struct *work)
2909{
2910 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
2911 struct net_device *dev;
2912 int i, err;
2913
81906791
SH		 2914 rtnl_lock();
2915 sky2_write32(hw, B0_IMSK, 0);
2916 sky2_read32(hw, B0_IMSK);
2917
81906791
SH		 2918 for (i = 0; i < hw->ports; i++) {
2919 dev = hw->dev[i];
2920 if (netif_running(dev))
2921 sky2_down(dev);
2922 }
2923
2924 sky2_reset(hw);
2925 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
81906791
SH		 2926
2927 for (i = 0; i < hw->ports; i++) {
2928 dev = hw->dev[i];
2929 if (netif_running(dev)) {
2930 err = sky2_up(dev);
2931 if (err) {
2932 printk(KERN_INFO PFX "%s: could not restart %d\n",
2933 dev->name, err);
2934 dev_close(dev);
2935 }
2936 }
2937 }
2938
81906791
SH		 2939 rtnl_unlock();
2940}
2941
e3173832
SH		 2942static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
2943{
2944 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
2945}
2946
2947static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2948{
2949 const struct sky2_port *sky2 = netdev_priv(dev);
2950
2951 wol->supported = sky2_wol_supported(sky2->hw);
2952 wol->wolopts = sky2->wol;
2953}
2954
2955static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2956{
2957 struct sky2_port *sky2 = netdev_priv(dev);
2958 struct sky2_hw *hw = sky2->hw;
cd28ab6a 2959
e3173832
SH		 2960 if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
2961 return -EOPNOTSUPP;
2962
2963 sky2->wol = wol->wolopts;
2964
05745c4a
SH		 2965 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
2966 hw->chip_id == CHIP_ID_YUKON_EX ||
2967 hw->chip_id == CHIP_ID_YUKON_FE_P)
e3173832
SH		 2968 sky2_write32(hw, B0_CTST, sky2->wol
2969 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
2970
2971 if (!netif_running(dev))
2972 sky2_wol_init(sky2);
cd28ab6a
SH		 2973 return 0;
2974}
2975
28bd181a 2976static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 2977{
b89165f2
SH		 2978 if (sky2_is_copper(hw)) {
2979 u32 modes = SUPPORTED_10baseT_Half
2980 | SUPPORTED_10baseT_Full
2981 | SUPPORTED_100baseT_Half
2982 | SUPPORTED_100baseT_Full
2983 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 2984
ea76e635 2985 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a 2986 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 2987 | SUPPORTED_1000baseT_Full;
2988 return modes;
cd28ab6a 2989 } else
b89165f2
SH		 2990 return SUPPORTED_1000baseT_Half
2991 | SUPPORTED_1000baseT_Full
2992 | SUPPORTED_Autoneg
2993 | SUPPORTED_FIBRE;
cd28ab6a
SH		 2994}
2995
793b883e 2996static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 2997{
2998 struct sky2_port *sky2 = netdev_priv(dev);
2999 struct sky2_hw *hw = sky2->hw;
3000
3001 ecmd->transceiver = XCVR_INTERNAL;
3002 ecmd->supported = sky2_supported_modes(hw);
3003 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 3004 if (sky2_is_copper(hw)) {
cd28ab6a 3005 ecmd->port = PORT_TP;
b89165f2
SH		 3006 ecmd->speed = sky2->speed;
3007 } else {
3008 ecmd->speed = SPEED_1000;
cd28ab6a 3009 ecmd->port = PORT_FIBRE;
b89165f2 3010 }
cd28ab6a
SH		 3011
3012 ecmd->advertising = sky2->advertising;
3013 ecmd->autoneg = sky2->autoneg;
cd28ab6a
SH		 3014 ecmd->duplex = sky2->duplex;
3015 return 0;
3016}
3017
3018static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3019{
3020 struct sky2_port *sky2 = netdev_priv(dev);
3021 const struct sky2_hw *hw = sky2->hw;
3022 u32 supported = sky2_supported_modes(hw);
3023
3024 if (ecmd->autoneg == AUTONEG_ENABLE) {
3025 ecmd->advertising = supported;
3026 sky2->duplex = -1;
3027 sky2->speed = -1;
3028 } else {
3029 u32 setting;
3030
793b883e 3031 switch (ecmd->speed) {
cd28ab6a
SH		 3032 case SPEED_1000:
3033 if (ecmd->duplex == DUPLEX_FULL)
3034 setting = SUPPORTED_1000baseT_Full;
3035 else if (ecmd->duplex == DUPLEX_HALF)
3036 setting = SUPPORTED_1000baseT_Half;
3037 else
3038 return -EINVAL;
3039 break;
3040 case SPEED_100:
3041 if (ecmd->duplex == DUPLEX_FULL)
3042 setting = SUPPORTED_100baseT_Full;
3043 else if (ecmd->duplex == DUPLEX_HALF)
3044 setting = SUPPORTED_100baseT_Half;
3045 else
3046 return -EINVAL;
3047 break;
3048
3049 case SPEED_10:
3050 if (ecmd->duplex == DUPLEX_FULL)
3051 setting = SUPPORTED_10baseT_Full;
3052 else if (ecmd->duplex == DUPLEX_HALF)
3053 setting = SUPPORTED_10baseT_Half;
3054 else
3055 return -EINVAL;
3056 break;
3057 default:
3058 return -EINVAL;
3059 }
3060
3061 if ((setting & supported) == 0)
3062 return -EINVAL;
3063
3064 sky2->speed = ecmd->speed;
3065 sky2->duplex = ecmd->duplex;
3066 }
3067
3068 sky2->autoneg = ecmd->autoneg;
3069 sky2->advertising = ecmd->advertising;
3070
d1b139c0 3071 if (netif_running(dev)) {
1b537565 3072 sky2_phy_reinit(sky2);
d1b139c0
SH		 3073 sky2_set_multicast(dev);
3074 }
cd28ab6a
SH		 3075
3076 return 0;
3077}
3078
3079static void sky2_get_drvinfo(struct net_device *dev,
3080 struct ethtool_drvinfo *info)
3081{
3082 struct sky2_port *sky2 = netdev_priv(dev);
3083
3084 strcpy(info->driver, DRV_NAME);
3085 strcpy(info->version, DRV_VERSION);
3086 strcpy(info->fw_version, "N/A");
3087 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3088}
3089
3090static const struct sky2_stat {
793b883e
SH		 3091 char name[ETH_GSTRING_LEN];
3092 u16 offset;
cd28ab6a
SH		 3093} sky2_stats[] = {
3094 { "tx_bytes", GM_TXO_OK_HI },
3095 { "rx_bytes", GM_RXO_OK_HI },
3096 { "tx_broadcast", GM_TXF_BC_OK },
3097 { "rx_broadcast", GM_RXF_BC_OK },
3098 { "tx_multicast", GM_TXF_MC_OK },
3099 { "rx_multicast", GM_RXF_MC_OK },
3100 { "tx_unicast", GM_TXF_UC_OK },
3101 { "rx_unicast", GM_RXF_UC_OK },
3102 { "tx_mac_pause", GM_TXF_MPAUSE },
3103 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 3104 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 3105 { "late_collision",GM_TXF_LAT_COL },
3106 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 3107 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 3108 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 3109
d2604540 3110 { "rx_short", GM_RXF_SHT },
cd28ab6a 3111 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 3112 { "rx_64_byte_packets", GM_RXF_64B },
3113 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3114 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3115 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3116 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3117 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3118 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 3119 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 3120 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3121 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 3122 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 3123
3124 { "tx_64_byte_packets", GM_TXF_64B },
3125 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3126 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3127 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3128 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3129 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3130 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3131 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 3132};
3133
cd28ab6a
SH		 3134static u32 sky2_get_rx_csum(struct net_device *dev)
3135{
3136 struct sky2_port *sky2 = netdev_priv(dev);
3137
3138 return sky2->rx_csum;
3139}
3140
3141static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3142{
3143 struct sky2_port *sky2 = netdev_priv(dev);
3144
3145 sky2->rx_csum = data;
793b883e 3146
cd28ab6a
SH		 3147 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3148 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3149
3150 return 0;
3151}
3152
3153static u32 sky2_get_msglevel(struct net_device *netdev)
3154{
3155 struct sky2_port *sky2 = netdev_priv(netdev);
3156 return sky2->msg_enable;
3157}
3158
9a7ae0a9
SH		 3159static int sky2_nway_reset(struct net_device *dev)
3160{
3161 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 3162
16ad91e1 3163 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
9a7ae0a9
SH		 3164 return -EINVAL;
3165
1b537565 3166 sky2_phy_reinit(sky2);
d1b139c0 3167 sky2_set_multicast(dev);
9a7ae0a9
SH		 3168
3169 return 0;
3170}
3171
793b883e 3172static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 3173{
3174 struct sky2_hw *hw = sky2->hw;
3175 unsigned port = sky2->port;
3176 int i;
3177
3178 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 3179 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 3180 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 3181 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 3182
793b883e 3183 for (i = 2; i < count; i++)
cd28ab6a
SH		 3184 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3185}
3186
cd28ab6a
SH		 3187static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3188{
3189 struct sky2_port *sky2 = netdev_priv(netdev);
3190 sky2->msg_enable = value;
3191}
3192
3193static int sky2_get_stats_count(struct net_device *dev)
3194{
3195 return ARRAY_SIZE(sky2_stats);
3196}
3197
3198static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 3199 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 3200{
3201 struct sky2_port *sky2 = netdev_priv(dev);
3202
793b883e 3203 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 3204}
3205
793b883e 3206static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 3207{
3208 int i;
3209
3210 switch (stringset) {
3211 case ETH_SS_STATS:
3212 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3213 memcpy(data + i * ETH_GSTRING_LEN,
3214 sky2_stats[i].name, ETH_GSTRING_LEN);
3215 break;
3216 }
3217}
3218
cd28ab6a
SH		 3219static struct net_device_stats *sky2_get_stats(struct net_device *dev)
3220{
3221 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 3222 return &sky2->net_stats;
3223}
3224
3225static int sky2_set_mac_address(struct net_device *dev, void *p)
3226{
3227 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 3228 struct sky2_hw *hw = sky2->hw;
3229 unsigned port = sky2->port;
3230 const struct sockaddr *addr = p;
cd28ab6a
SH		 3231
3232 if (!is_valid_ether_addr(addr->sa_data))
3233 return -EADDRNOTAVAIL;
3234
cd28ab6a 3235 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 3236 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 3237 dev->dev_addr, ETH_ALEN);
a8ab1ec0 3238 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 3239 dev->dev_addr, ETH_ALEN);
1b537565 3240
a8ab1ec0
SH		 3241 /* virtual address for data */
3242 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3243
3244 /* physical address: used for pause frames */
3245 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 3246
3247 return 0;
cd28ab6a
SH		 3248}
3249
a052b52f
SH		 3250static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3251{
3252 u32 bit;
3253
3254 bit = ether_crc(ETH_ALEN, addr) & 63;
3255 filter[bit >> 3] |= 1 << (bit & 7);
3256}
3257
cd28ab6a
SH		 3258static void sky2_set_multicast(struct net_device *dev)
3259{
3260 struct sky2_port *sky2 = netdev_priv(dev);
3261 struct sky2_hw *hw = sky2->hw;
3262 unsigned port = sky2->port;
3263 struct dev_mc_list *list = dev->mc_list;
3264 u16 reg;
3265 u8 filter[8];
a052b52f
SH		 3266 int rx_pause;
3267 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 3268
a052b52f 3269 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 3270 memset(filter, 0, sizeof(filter));
3271
3272 reg = gma_read16(hw, port, GM_RX_CTRL);
3273 reg |= GM_RXCR_UCF_ENA;
3274
d571b694 3275 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 3276 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 3277 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 3278 memset(filter, 0xff, sizeof(filter));
a052b52f 3279 else if (dev->mc_count == 0 && !rx_pause)
cd28ab6a
SH		 3280 reg &= ~GM_RXCR_MCF_ENA;
3281 else {
3282 int i;
3283 reg |= GM_RXCR_MCF_ENA;
3284
a052b52f
SH		 3285 if (rx_pause)
3286 sky2_add_filter(filter, pause_mc_addr);
3287
3288 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3289 sky2_add_filter(filter, list->dmi_addr);
cd28ab6a
SH		 3290 }
3291
cd28ab6a 3292 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 3293 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 3294 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 3295 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 3296 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 3297 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 3298 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 3299 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 3300
3301 gma_write16(hw, port, GM_RX_CTRL, reg);
3302}
3303
3304/* Can have one global because blinking is controlled by
3305 * ethtool and that is always under RTNL mutex
3306 */
91c86df5 3307static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
cd28ab6a 3308{
793b883e
SH		 3309 u16 pg;
3310
793b883e
SH		 3311 switch (hw->chip_id) {
3312 case CHIP_ID_YUKON_XL:
3313 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3314 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3315 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3316 on ? (PHY_M_LEDC_LOS_CTRL(1) |
3317 PHY_M_LEDC_INIT_CTRL(7) |
3318 PHY_M_LEDC_STA1_CTRL(7) |
3319 PHY_M_LEDC_STA0_CTRL(7))
3320 : 0);
3321
3322 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3323 break;
3324
3325 default:
3326 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
0efdf262
SH		 3327 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3328 on ? PHY_M_LED_ALL : 0);
793b883e 3329 }
cd28ab6a
SH		 3330}
3331
3332/* blink LED's for finding board */
3333static int sky2_phys_id(struct net_device *dev, u32 data)
3334{
3335 struct sky2_port *sky2 = netdev_priv(dev);
3336 struct sky2_hw *hw = sky2->hw;
3337 unsigned port = sky2->port;
793b883e 3338 u16 ledctrl, ledover = 0;
cd28ab6a 3339 long ms;
91c86df5 3340 int interrupted;
cd28ab6a
SH		 3341 int onoff = 1;
3342
793b883e 3343 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
cd28ab6a
SH		 3344 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
3345 else
3346 ms = data * 1000;
3347
3348 /* save initial values */
e07b1aa8 3349 spin_lock_bh(&sky2->phy_lock);
793b883e
SH		 3350 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3351 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3352 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3353 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
3354 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3355 } else {
3356 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
3357 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
3358 }
cd28ab6a 3359
91c86df5
SH		 3360 interrupted = 0;
3361 while (!interrupted && ms > 0) {
cd28ab6a
SH		 3362 sky2_led(hw, port, onoff);
3363 onoff = !onoff;
3364
e07b1aa8 3365 spin_unlock_bh(&sky2->phy_lock);
91c86df5 3366 interrupted = msleep_interruptible(250);
e07b1aa8 3367 spin_lock_bh(&sky2->phy_lock);
91c86df5 3368
cd28ab6a
SH		 3369 ms -= 250;
3370 }
3371
3372 /* resume regularly scheduled programming */
793b883e
SH		 3373 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3374 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3375 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3376 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
3377 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3378 } else {
3379 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
3380 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
3381 }
e07b1aa8 3382 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 3383
3384 return 0;
3385}
3386
3387static void sky2_get_pauseparam(struct net_device *dev,
3388 struct ethtool_pauseparam *ecmd)
3389{
3390 struct sky2_port *sky2 = netdev_priv(dev);
3391
16ad91e1
SH		 3392 switch (sky2->flow_mode) {
3393 case FC_NONE:
3394 ecmd->tx_pause = ecmd->rx_pause = 0;
3395 break;
3396 case FC_TX:
3397 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3398 break;
3399 case FC_RX:
3400 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3401 break;
3402 case FC_BOTH:
3403 ecmd->tx_pause = ecmd->rx_pause = 1;
3404 }
3405
cd28ab6a
SH		 3406 ecmd->autoneg = sky2->autoneg;
3407}
3408
3409static int sky2_set_pauseparam(struct net_device *dev,
3410 struct ethtool_pauseparam *ecmd)
3411{
3412 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 3413
3414 sky2->autoneg = ecmd->autoneg;
16ad91e1 3415 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3416
16ad91e1
SH		 3417 if (netif_running(dev))
3418 sky2_phy_reinit(sky2);
cd28ab6a 3419
2eaba1a2 3420 return 0;
cd28ab6a
SH		 3421}
3422
fb17358f
SH		 3423static int sky2_get_coalesce(struct net_device *dev,
3424 struct ethtool_coalesce *ecmd)
3425{
3426 struct sky2_port *sky2 = netdev_priv(dev);
3427 struct sky2_hw *hw = sky2->hw;
3428
3429 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3430 ecmd->tx_coalesce_usecs = 0;
3431 else {
3432 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3433 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3434 }
3435 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3436
3437 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3438 ecmd->rx_coalesce_usecs = 0;
3439 else {
3440 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3441 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3442 }
3443 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3444
3445 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3446 ecmd->rx_coalesce_usecs_irq = 0;
3447 else {
3448 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3449 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3450 }
3451
3452 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3453
3454 return 0;
3455}
3456
3457/* Note: this affect both ports */
3458static int sky2_set_coalesce(struct net_device *dev,
3459 struct ethtool_coalesce *ecmd)
3460{
3461 struct sky2_port *sky2 = netdev_priv(dev);
3462 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3463 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3464
77b3d6a2
SH		 3465 if (ecmd->tx_coalesce_usecs > tmax ||
3466 ecmd->rx_coalesce_usecs > tmax ||
3467 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3468 return -EINVAL;
3469
ff81fbbe 3470 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
fb17358f 3471 return -EINVAL;
ff81fbbe 3472 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3473 return -EINVAL;
ff81fbbe 3474 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 3475 return -EINVAL;
3476
3477 if (ecmd->tx_coalesce_usecs == 0)
3478 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3479 else {
3480 sky2_write32(hw, STAT_TX_TIMER_INI,
3481 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3482 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3483 }
3484 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3485
3486 if (ecmd->rx_coalesce_usecs == 0)
3487 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3488 else {
3489 sky2_write32(hw, STAT_LEV_TIMER_INI,
3490 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3491 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3492 }
3493 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3494
3495 if (ecmd->rx_coalesce_usecs_irq == 0)
3496 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3497 else {
d28d4870 3498 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3499 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3500 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3501 }
3502 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3503 return 0;
3504}
3505
793b883e
SH		 3506static void sky2_get_ringparam(struct net_device *dev,
3507 struct ethtool_ringparam *ering)
3508{
3509 struct sky2_port *sky2 = netdev_priv(dev);
3510
3511 ering->rx_max_pending = RX_MAX_PENDING;
3512 ering->rx_mini_max_pending = 0;
3513 ering->rx_jumbo_max_pending = 0;
3514 ering->tx_max_pending = TX_RING_SIZE - 1;
3515
3516 ering->rx_pending = sky2->rx_pending;
3517 ering->rx_mini_pending = 0;
3518 ering->rx_jumbo_pending = 0;
3519 ering->tx_pending = sky2->tx_pending;
3520}
3521
3522static int sky2_set_ringparam(struct net_device *dev,
3523 struct ethtool_ringparam *ering)
3524{
3525 struct sky2_port *sky2 = netdev_priv(dev);
3526 int err = 0;
3527
3528 if (ering->rx_pending > RX_MAX_PENDING ||
3529 ering->rx_pending < 8 ||
3530 ering->tx_pending < MAX_SKB_TX_LE ||
3531 ering->tx_pending > TX_RING_SIZE - 1)
3532 return -EINVAL;
3533
3534 if (netif_running(dev))
3535 sky2_down(dev);
3536
3537 sky2->rx_pending = ering->rx_pending;
3538 sky2->tx_pending = ering->tx_pending;
3539
1b537565 3540 if (netif_running(dev)) {
793b883e 3541 err = sky2_up(dev);
1b537565
SH		 3542 if (err)
3543 dev_close(dev);
6ed995bb
SH		 3544 else
3545 sky2_set_multicast(dev);
1b537565 3546 }
793b883e
SH		 3547
3548 return err;
3549}
3550
793b883e
SH		 3551static int sky2_get_regs_len(struct net_device *dev)
3552{
6e4cbb34 3553 return 0x4000;
793b883e
SH		 3554}
3555
3556/*
3557 * Returns copy of control register region
3ead5db7 3558 * Note: ethtool_get_regs always provides full size (16k) buffer
793b883e
SH		 3559 */
3560static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3561 void *p)
3562{
3563 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3564 const void __iomem *io = sky2->hw->regs;
793b883e
SH		 3565
3566 regs->version = 1;
6e4cbb34 3567 memset(p, 0, regs->len);
793b883e 3568
6e4cbb34
SH		 3569 memcpy_fromio(p, io, B3_RAM_ADDR);
3570
3ead5db7
SH		 3571 /* skip diagnostic ram region */
3572 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1, 0x2000 - B3_RI_WTO_R1);
3573
3574 /* copy GMAC registers */
3575 memcpy_fromio(p + BASE_GMAC_1, io + BASE_GMAC_1, 0x1000);
3576 if (sky2->hw->ports > 1)
3577 memcpy_fromio(p + BASE_GMAC_2, io + BASE_GMAC_2, 0x1000);
3578
793b883e 3579}
cd28ab6a 3580
b628ed98
SH		 3581/* In order to do Jumbo packets on these chips, need to turn off the
3582 * transmit store/forward. Therefore checksum offload won't work.
3583 */
3584static int no_tx_offload(struct net_device *dev)
3585{
3586 const struct sky2_port *sky2 = netdev_priv(dev);
3587 const struct sky2_hw *hw = sky2->hw;
3588
69161611 3589 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
b628ed98
SH		 3590}
3591
3592static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3593{
3594 if (data && no_tx_offload(dev))
3595 return -EINVAL;
3596
3597 return ethtool_op_set_tx_csum(dev, data);
3598}
3599
3600
3601static int sky2_set_tso(struct net_device *dev, u32 data)
3602{
3603 if (data && no_tx_offload(dev))
3604 return -EINVAL;
3605
3606 return ethtool_op_set_tso(dev, data);
3607}
3608
f4331a6d
SH		 3609static int sky2_get_eeprom_len(struct net_device *dev)
3610{
3611 struct sky2_port *sky2 = netdev_priv(dev);
3612 u16 reg2;
3613
3614 reg2 = sky2_pci_read32(sky2->hw, PCI_DEV_REG2);
3615 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3616}
3617
3618static u32 sky2_vpd_read(struct sky2_hw *hw, int cap, u16 offset)
3619{
3620 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
3621
3622 while (!(sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F))
3623 cpu_relax();
3624 return sky2_pci_read32(hw, cap + PCI_VPD_DATA);
3625}
3626
3627static void sky2_vpd_write(struct sky2_hw *hw, int cap, u16 offset, u32 val)
3628{
3629 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
3630 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
3631 do {
3632 cpu_relax();
3633 } while (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F);
3634}
3635
3636static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3637 u8 *data)
3638{
3639 struct sky2_port *sky2 = netdev_priv(dev);
3640 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3641 int length = eeprom->len;
3642 u16 offset = eeprom->offset;
3643
3644 if (!cap)
3645 return -EINVAL;
3646
3647 eeprom->magic = SKY2_EEPROM_MAGIC;
3648
3649 while (length > 0) {
3650 u32 val = sky2_vpd_read(sky2->hw, cap, offset);
3651 int n = min_t(int, length, sizeof(val));
3652
3653 memcpy(data, &val, n);
3654 length -= n;
3655 data += n;
3656 offset += n;
3657 }
3658 return 0;
3659}
3660
3661static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3662 u8 *data)
3663{
3664 struct sky2_port *sky2 = netdev_priv(dev);
3665 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3666 int length = eeprom->len;
3667 u16 offset = eeprom->offset;
3668
3669 if (!cap)
3670 return -EINVAL;
3671
3672 if (eeprom->magic != SKY2_EEPROM_MAGIC)
3673 return -EINVAL;
3674
3675 while (length > 0) {
3676 u32 val;
3677 int n = min_t(int, length, sizeof(val));
3678
3679 if (n < sizeof(val))
3680 val = sky2_vpd_read(sky2->hw, cap, offset);
3681 memcpy(&val, data, n);
3682
3683 sky2_vpd_write(sky2->hw, cap, offset, val);
3684
3685 length -= n;
3686 data += n;
3687 offset += n;
3688 }
3689 return 0;
3690}
3691
3692
7282d491 3693static const struct ethtool_ops sky2_ethtool_ops = {
f4331a6d
SH		 3694 .get_settings = sky2_get_settings,
3695 .set_settings = sky2_set_settings,
3696 .get_drvinfo = sky2_get_drvinfo,
3697 .get_wol = sky2_get_wol,
3698 .set_wol = sky2_set_wol,
3699 .get_msglevel = sky2_get_msglevel,
3700 .set_msglevel = sky2_set_msglevel,
3701 .nway_reset = sky2_nway_reset,
3702 .get_regs_len = sky2_get_regs_len,
3703 .get_regs = sky2_get_regs,
3704 .get_link = ethtool_op_get_link,
3705 .get_eeprom_len = sky2_get_eeprom_len,
3706 .get_eeprom = sky2_get_eeprom,
3707 .set_eeprom = sky2_set_eeprom,
3708 .get_sg = ethtool_op_get_sg,
3709 .set_sg = ethtool_op_set_sg,
3710 .get_tx_csum = ethtool_op_get_tx_csum,
3711 .set_tx_csum = sky2_set_tx_csum,
3712 .get_tso = ethtool_op_get_tso,
3713 .set_tso = sky2_set_tso,
3714 .get_rx_csum = sky2_get_rx_csum,
3715 .set_rx_csum = sky2_set_rx_csum,
3716 .get_strings = sky2_get_strings,
3717 .get_coalesce = sky2_get_coalesce,
3718 .set_coalesce = sky2_set_coalesce,
3719 .get_ringparam = sky2_get_ringparam,
3720 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 3721 .get_pauseparam = sky2_get_pauseparam,
3722 .set_pauseparam = sky2_set_pauseparam,
f4331a6d 3723 .phys_id = sky2_phys_id,
cd28ab6a
SH		 3724 .get_stats_count = sky2_get_stats_count,
3725 .get_ethtool_stats = sky2_get_ethtool_stats,
3726};
3727
3cf26753
SH		 3728#ifdef CONFIG_SKY2_DEBUG
3729
3730static struct dentry *sky2_debug;
3731
3732static int sky2_debug_show(struct seq_file *seq, void *v)
3733{
3734 struct net_device *dev = seq->private;
3735 const struct sky2_port *sky2 = netdev_priv(dev);
bea3348e 3736 struct sky2_hw *hw = sky2->hw;
3cf26753
SH		 3737 unsigned port = sky2->port;
3738 unsigned idx, last;
3739 int sop;
3740
3741 if (!netif_running(dev))
3742 return -ENETDOWN;
3743
3744 seq_printf(seq, "IRQ src=%x mask=%x control=%x\n",
3745 sky2_read32(hw, B0_ISRC),
3746 sky2_read32(hw, B0_IMSK),
3747 sky2_read32(hw, B0_Y2_SP_ICR));
3748
bea3348e 3749 napi_disable(&hw->napi);
3cf26753
SH		 3750 last = sky2_read16(hw, STAT_PUT_IDX);
3751
3752 if (hw->st_idx == last)
3753 seq_puts(seq, "Status ring (empty)\n");
3754 else {
3755 seq_puts(seq, "Status ring\n");
3756 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
3757 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
3758 const struct sky2_status_le *le = hw->st_le + idx;
3759 seq_printf(seq, "[%d] %#x %d %#x\n",
3760 idx, le->opcode, le->length, le->status);
3761 }
3762 seq_puts(seq, "\n");
3763 }
3764
3765 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
3766 sky2->tx_cons, sky2->tx_prod,
3767 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
3768 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
3769
3770 /* Dump contents of tx ring */
3771 sop = 1;
3772 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < TX_RING_SIZE;
3773 idx = RING_NEXT(idx, TX_RING_SIZE)) {
3774 const struct sky2_tx_le *le = sky2->tx_le + idx;
3775 u32 a = le32_to_cpu(le->addr);
3776
3777 if (sop)
3778 seq_printf(seq, "%u:", idx);
3779 sop = 0;
3780
3781 switch(le->opcode & ~HW_OWNER) {
3782 case OP_ADDR64:
3783 seq_printf(seq, " %#x:", a);
3784 break;
3785 case OP_LRGLEN:
3786 seq_printf(seq, " mtu=%d", a);
3787 break;
3788 case OP_VLAN:
3789 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
3790 break;
3791 case OP_TCPLISW:
3792 seq_printf(seq, " csum=%#x", a);
3793 break;
3794 case OP_LARGESEND:
3795 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
3796 break;
3797 case OP_PACKET:
3798 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
3799 break;
3800 case OP_BUFFER:
3801 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
3802 break;
3803 default:
3804 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
3805 a, le16_to_cpu(le->length));
3806 }
3807
3808 if (le->ctrl & EOP) {
3809 seq_putc(seq, '\n');
3810 sop = 1;
3811 }
3812 }
3813
3814 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
3815 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
3816 last = sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
3817 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
3818
bea3348e 3819 napi_enable(&hw->napi);
3cf26753
SH		 3820 return 0;
3821}
3822
3823static int sky2_debug_open(struct inode *inode, struct file *file)
3824{
3825 return single_open(file, sky2_debug_show, inode->i_private);
3826}
3827
3828static const struct file_operations sky2_debug_fops = {
3829 .owner = THIS_MODULE,
3830 .open = sky2_debug_open,
3831 .read = seq_read,
3832 .llseek = seq_lseek,
3833 .release = single_release,
3834};
3835
3836/*
3837 * Use network device events to create/remove/rename
3838 * debugfs file entries
3839 */
3840static int sky2_device_event(struct notifier_block *unused,
3841 unsigned long event, void *ptr)
3842{
3843 struct net_device *dev = ptr;
3844
3845 if (dev->open == sky2_up) {
3846 struct sky2_port *sky2 = netdev_priv(dev);
3847
3848 switch(event) {
3849 case NETDEV_CHANGENAME:
3850 if (!netif_running(dev))
3851 break;
3852 /* fallthrough */
3853 case NETDEV_DOWN:
3854 case NETDEV_GOING_DOWN:
3855 if (sky2->debugfs) {
3856 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
3857 dev->name);
3858 debugfs_remove(sky2->debugfs);
3859 sky2->debugfs = NULL;
3860 }
3861
3862 if (event != NETDEV_CHANGENAME)
3863 break;
3864 /* fallthrough for changename */
3865 case NETDEV_UP:
3866 if (sky2_debug) {
3867 struct dentry *d;
3868 d = debugfs_create_file(dev->name, S_IRUGO,
3869 sky2_debug, dev,
3870 &sky2_debug_fops);
3871 if (d == NULL || IS_ERR(d))
3872 printk(KERN_INFO PFX
3873 "%s: debugfs create failed\n",
3874 dev->name);
3875 else
3876 sky2->debugfs = d;
3877 }
3878 break;
3879 }
3880 }
3881
3882 return NOTIFY_DONE;
3883}
3884
3885static struct notifier_block sky2_notifier = {
3886 .notifier_call = sky2_device_event,
3887};
3888
3889
3890static __init void sky2_debug_init(void)
3891{
3892 struct dentry *ent;
3893
3894 ent = debugfs_create_dir("sky2", NULL);
3895 if (!ent || IS_ERR(ent))
3896 return;
3897
3898 sky2_debug = ent;
3899 register_netdevice_notifier(&sky2_notifier);
3900}
3901
3902static __exit void sky2_debug_cleanup(void)
3903{
3904 if (sky2_debug) {
3905 unregister_netdevice_notifier(&sky2_notifier);
3906 debugfs_remove(sky2_debug);
3907 sky2_debug = NULL;
3908 }
3909}
3910
3911#else
3912#define sky2_debug_init()
3913#define sky2_debug_cleanup()
3914#endif
3915
3916
cd28ab6a
SH		 3917/* Initialize network device */
3918static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
e3173832
SH		 3919 unsigned port,
3920 int highmem, int wol)
cd28ab6a
SH		 3921{
3922 struct sky2_port *sky2;
3923 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3924
3925 if (!dev) {
b02a9258 3926 dev_err(&hw->pdev->dev, "etherdev alloc failed");
cd28ab6a
SH		 3927 return NULL;
3928 }
3929
3930 SET_MODULE_OWNER(dev);
3931 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 3932 dev->irq = hw->pdev->irq;
cd28ab6a
SH		 3933 dev->open = sky2_up;
3934 dev->stop = sky2_down;
ef743d33 3935 dev->do_ioctl = sky2_ioctl;
cd28ab6a
SH		 3936 dev->hard_start_xmit = sky2_xmit_frame;
3937 dev->get_stats = sky2_get_stats;
3938 dev->set_multicast_list = sky2_set_multicast;
3939 dev->set_mac_address = sky2_set_mac_address;
3940 dev->change_mtu = sky2_change_mtu;
3941 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3942 dev->tx_timeout = sky2_tx_timeout;
3943 dev->watchdog_timeo = TX_WATCHDOG;
cd28ab6a 3944#ifdef CONFIG_NET_POLL_CONTROLLER
bea3348e 3945 dev->poll_controller = sky2_netpoll;
cd28ab6a 3946#endif
cd28ab6a
SH		 3947
3948 sky2 = netdev_priv(dev);
3949 sky2->netdev = dev;
3950 sky2->hw = hw;
3951 sky2->msg_enable = netif_msg_init(debug, default_msg);
3952
cd28ab6a
SH		 3953 /* Auto speed and flow control */
3954 sky2->autoneg = AUTONEG_ENABLE;
16ad91e1
SH		 3955 sky2->flow_mode = FC_BOTH;
3956
cd28ab6a
SH		 3957 sky2->duplex = -1;
3958 sky2->speed = -1;
3959 sky2->advertising = sky2_supported_modes(hw);
ee7abb04 3960 sky2->rx_csum = 1;
e3173832 3961 sky2->wol = wol;
75d070c5 3962
e07b1aa8 3963 spin_lock_init(&sky2->phy_lock);
793b883e 3964 sky2->tx_pending = TX_DEF_PENDING;
290d4de5 3965 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 3966
3967 hw->dev[port] = dev;
3968
3969 sky2->port = port;
3970
4a50a876 3971 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a
SH		 3972 if (highmem)
3973 dev->features |= NETIF_F_HIGHDMA;
cd28ab6a 3974
d1f13708 3975#ifdef SKY2_VLAN_TAG_USED
d6c9bc1e
SH		 3976 /* The workaround for FE+ status conflicts with VLAN tag detection. */
3977 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
3978 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
3979 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3980 dev->vlan_rx_register = sky2_vlan_rx_register;
3981 }
d1f13708
SH		 3982#endif
3983
cd28ab6a 3984 /* read the mac address */
793b883e 3985 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 3986 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a 3987
cd28ab6a
SH		 3988 return dev;
3989}
3990
28bd181a 3991static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 3992{
3993 const struct sky2_port *sky2 = netdev_priv(dev);
3994
3995 if (netif_msg_probe(sky2))
3996 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3997 dev->name,
3998 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3999 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
4000}
4001
fb2690a9 4002/* Handle software interrupt used during MSI test */
7d12e780 4003static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 4004{
4005 struct sky2_hw *hw = dev_id;
4006 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4007
4008 if (status == 0)
4009 return IRQ_NONE;
4010
4011 if (status & Y2_IS_IRQ_SW) {
ea76e635 4012 hw->flags |= SKY2_HW_USE_MSI;
fb2690a9
SH		 4013 wake_up(&hw->msi_wait);
4014 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4015 }
4016 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4017
4018 return IRQ_HANDLED;
4019}
4020
4021/* Test interrupt path by forcing a a software IRQ */
4022static int __devinit sky2_test_msi(struct sky2_hw *hw)
4023{
4024 struct pci_dev *pdev = hw->pdev;
4025 int err;
4026
bb507fe1
SH		 4027 init_waitqueue_head (&hw->msi_wait);
4028
fb2690a9
SH		 4029 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4030
b0a20ded 4031 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9 4032 if (err) {
b02a9258 4033 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
fb2690a9
SH		 4034 return err;
4035 }
4036
fb2690a9 4037 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 4038 sky2_read8(hw, B0_CTST);
fb2690a9 4039
ea76e635 4040 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
fb2690a9 4041
ea76e635 4042 if (!(hw->flags & SKY2_HW_USE_MSI)) {
fb2690a9 4043 /* MSI test failed, go back to INTx mode */
b02a9258
SH		 4044 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4045 "switching to INTx mode.\n");
fb2690a9
SH		 4046
4047 err = -EOPNOTSUPP;
4048 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4049 }
4050
4051 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 4052 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 4053
4054 free_irq(pdev->irq, hw);
4055
4056 return err;
4057}
4058
e3173832
SH		 4059static int __devinit pci_wake_enabled(struct pci_dev *dev)
4060{
4061 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
4062 u16 value;
4063
4064 if (!pm)
4065 return 0;
4066 if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
4067 return 0;
4068 return value & PCI_PM_CTRL_PME_ENABLE;
4069}
4070
cd28ab6a
SH		 4071static int __devinit sky2_probe(struct pci_dev *pdev,
4072 const struct pci_device_id *ent)
4073{
7f60c64b 4074 struct net_device *dev;
cd28ab6a 4075 struct sky2_hw *hw;
e3173832 4076 int err, using_dac = 0, wol_default;
cd28ab6a 4077
793b883e
SH		 4078 err = pci_enable_device(pdev);
4079 if (err) {
b02a9258 4080 dev_err(&pdev->dev, "cannot enable PCI device\n");
cd28ab6a
SH		 4081 goto err_out;
4082 }
4083
793b883e
SH		 4084 err = pci_request_regions(pdev, DRV_NAME);
4085 if (err) {
b02a9258 4086 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
44a1d2e5 4087 goto err_out_disable;
cd28ab6a
SH		 4088 }
4089
4090 pci_set_master(pdev);
4091
d1f3d4dd
SH		 4092 if (sizeof(dma_addr_t) > sizeof(u32) &&
4093 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
4094 using_dac = 1;
4095 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
4096 if (err < 0) {
b02a9258
SH		 4097 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4098 "for consistent allocations\n");
d1f3d4dd
SH		 4099 goto err_out_free_regions;
4100 }
d1f3d4dd 4101 } else {
cd28ab6a
SH		 4102 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
4103 if (err) {
b02a9258 4104 dev_err(&pdev->dev, "no usable DMA configuration\n");
cd28ab6a
SH		 4105 goto err_out_free_regions;
4106 }
4107 }
d1f3d4dd 4108
e3173832
SH		 4109 wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
4110
cd28ab6a 4111 err = -ENOMEM;
6aad85d6 4112 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a 4113 if (!hw) {
b02a9258 4114 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
cd28ab6a
SH		 4115 goto err_out_free_regions;
4116 }
4117
cd28ab6a 4118 hw->pdev = pdev;
cd28ab6a
SH		 4119
4120 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4121 if (!hw->regs) {
b02a9258 4122 dev_err(&pdev->dev, "cannot map device registers\n");
cd28ab6a
SH		 4123 goto err_out_free_hw;
4124 }
4125
56a645cc 4126#ifdef __BIG_ENDIAN
f65b138c
SH		 4127 /* The sk98lin vendor driver uses hardware byte swapping but
4128 * this driver uses software swapping.
4129 */
56a645cc
SH		 4130 {
4131 u32 reg;
56a645cc 4132 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
f65b138c 4133 reg &= ~PCI_REV_DESC;
56a645cc
SH		 4134 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
4135 }
4136#endif
4137
08c06d8a
SH		 4138 /* ring for status responses */
4139 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
4140 &hw->st_dma);
4141 if (!hw->st_le)
4142 goto err_out_iounmap;
4143
e3173832 4144 err = sky2_init(hw);
cd28ab6a 4145 if (err)
793b883e 4146 goto err_out_iounmap;
cd28ab6a 4147
b02a9258 4148 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
7c7459d1
GKH		 4149 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
4150 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
793b883e 4151 hw->chip_id, hw->chip_rev);
cd28ab6a 4152
e3173832
SH		 4153 sky2_reset(hw);
4154
4155 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
7f60c64b 4156 if (!dev) {
4157 err = -ENOMEM;
cd28ab6a 4158 goto err_out_free_pci;
7f60c64b 4159 }
bea3348e 4160 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
cd28ab6a 4161
9fa1b1f3
SH		 4162 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4163 err = sky2_test_msi(hw);
4164 if (err == -EOPNOTSUPP)
4165 pci_disable_msi(pdev);
4166 else if (err)
4167 goto err_out_free_netdev;
4168 }
4169
793b883e
SH		 4170 err = register_netdev(dev);
4171 if (err) {
b02a9258 4172 dev_err(&pdev->dev, "cannot register net device\n");
cd28ab6a
SH		 4173 goto err_out_free_netdev;
4174 }
4175
ea76e635
SH		 4176 err = request_irq(pdev->irq, sky2_intr,
4177 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
b0a20ded 4178 dev->name, hw);
9fa1b1f3 4179 if (err) {
b02a9258 4180 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
9fa1b1f3
SH		 4181 goto err_out_unregister;
4182 }
4183 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4184
cd28ab6a
SH		 4185 sky2_show_addr(dev);
4186
7f60c64b 4187 if (hw->ports > 1) {
4188 struct net_device *dev1;
4189
e3173832 4190 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
b02a9258
SH		 4191 if (!dev1)
4192 dev_warn(&pdev->dev, "allocation for second device failed\n");
4193 else if ((err = register_netdev(dev1))) {
4194 dev_warn(&pdev->dev,
4195 "register of second port failed (%d)\n", err);
cd28ab6a
SH		 4196 hw->dev[1] = NULL;
4197 free_netdev(dev1);
b02a9258
SH		 4198 } else
4199 sky2_show_addr(dev1);
cd28ab6a
SH		 4200 }
4201
32c2c300 4202 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
81906791
SH		 4203 INIT_WORK(&hw->restart_work, sky2_restart);
4204
793b883e
SH		 4205 pci_set_drvdata(pdev, hw);
4206
cd28ab6a
SH		 4207 return 0;
4208
793b883e 4209err_out_unregister:
ea76e635 4210 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4211 pci_disable_msi(pdev);
793b883e 4212 unregister_netdev(dev);
cd28ab6a
SH		 4213err_out_free_netdev:
4214 free_netdev(dev);
cd28ab6a 4215err_out_free_pci:
793b883e 4216 sky2_write8(hw, B0_CTST, CS_RST_SET);
cd28ab6a
SH		 4217 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4218err_out_iounmap:
4219 iounmap(hw->regs);
4220err_out_free_hw:
4221 kfree(hw);
4222err_out_free_regions:
4223 pci_release_regions(pdev);
44a1d2e5 4224err_out_disable:
cd28ab6a 4225 pci_disable_device(pdev);
cd28ab6a 4226err_out:
549a68c3 4227 pci_set_drvdata(pdev, NULL);
cd28ab6a
SH		 4228 return err;
4229}
4230
4231static void __devexit sky2_remove(struct pci_dev *pdev)
4232{
793b883e 4233 struct sky2_hw *hw = pci_get_drvdata(pdev);
cd28ab6a
SH		 4234 struct net_device *dev0, *dev1;
4235
793b883e 4236 if (!hw)
cd28ab6a
SH		 4237 return;
4238
32c2c300 4239 del_timer_sync(&hw->watchdog_timer);
d27ed387 4240
81906791
SH		 4241 flush_scheduled_work();
4242
d27ed387 4243 sky2_write32(hw, B0_IMSK, 0);
72cb8529
SH		 4244 synchronize_irq(hw->pdev->irq);
4245
cd28ab6a 4246 dev0 = hw->dev[0];
793b883e
SH		 4247 dev1 = hw->dev[1];
4248 if (dev1)
4249 unregister_netdev(dev1);
cd28ab6a
SH		 4250 unregister_netdev(dev0);
4251
ae306cca
SH		 4252 sky2_power_aux(hw);
4253
cd28ab6a 4254 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 4255 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 4256 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 4257
4258 free_irq(pdev->irq, hw);
ea76e635 4259 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4260 pci_disable_msi(pdev);
793b883e 4261 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4262 pci_release_regions(pdev);
4263 pci_disable_device(pdev);
793b883e 4264
cd28ab6a
SH		 4265 if (dev1)
4266 free_netdev(dev1);
4267 free_netdev(dev0);
4268 iounmap(hw->regs);
4269 kfree(hw);
5afa0a9c 4270
cd28ab6a
SH		 4271 pci_set_drvdata(pdev, NULL);
4272}
4273
4274#ifdef CONFIG_PM
4275static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4276{
793b883e 4277 struct sky2_hw *hw = pci_get_drvdata(pdev);
e3173832 4278 int i, wol = 0;
cd28ab6a 4279
549a68c3
SH		 4280 if (!hw)
4281 return 0;
4282
f05267e7 4283 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4284 struct net_device *dev = hw->dev[i];
e3173832 4285 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 4286
e3173832 4287 if (netif_running(dev))
5afa0a9c 4288 sky2_down(dev);
e3173832
SH		 4289
4290 if (sky2->wol)
4291 sky2_wol_init(sky2);
4292
4293 wol |= sky2->wol;
cd28ab6a
SH		 4294 }
4295
8ab8fca2 4296 sky2_write32(hw, B0_IMSK, 0);
ae306cca 4297 sky2_power_aux(hw);
e3173832 4298
d374c1c1 4299 pci_save_state(pdev);
e3173832 4300 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
ae306cca
SH		 4301 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4302
2ccc99b7 4303 return 0;
cd28ab6a
SH		 4304}
4305
4306static int sky2_resume(struct pci_dev *pdev)
4307{
793b883e 4308 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 4309 int i, err;
cd28ab6a 4310
549a68c3
SH		 4311 if (!hw)
4312 return 0;
4313
ae306cca
SH		 4314 err = pci_set_power_state(pdev, PCI_D0);
4315 if (err)
4316 goto out;
4317
4318 err = pci_restore_state(pdev);
4319 if (err)
4320 goto out;
4321
cd28ab6a 4322 pci_enable_wake(pdev, PCI_D0, 0);
1ad5b4a5
SH		 4323
4324 /* Re-enable all clocks */
05745c4a
SH		 4325 if (hw->chip_id == CHIP_ID_YUKON_EX ||
4326 hw->chip_id == CHIP_ID_YUKON_EC_U ||
4327 hw->chip_id == CHIP_ID_YUKON_FE_P)
1ad5b4a5
SH		 4328 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
4329
e3173832 4330 sky2_reset(hw);
cd28ab6a 4331
8ab8fca2
SH		 4332 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4333
f05267e7 4334 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4335 struct net_device *dev = hw->dev[i];
6a5706b9 4336 if (netif_running(dev)) {
08c06d8a
SH		 4337 err = sky2_up(dev);
4338 if (err) {
4339 printk(KERN_ERR PFX "%s: could not up: %d\n",
4340 dev->name, err);
4341 dev_close(dev);
eb35cf60 4342 goto out;
5afa0a9c 4343 }
d1b139c0
SH		 4344
4345 sky2_set_multicast(dev);
cd28ab6a
SH		 4346 }
4347 }
eb35cf60 4348
ae306cca 4349 return 0;
08c06d8a 4350out:
b02a9258 4351 dev_err(&pdev->dev, "resume failed (%d)\n", err);
ae306cca 4352 pci_disable_device(pdev);
08c06d8a 4353 return err;
cd28ab6a
SH		 4354}
4355#endif
4356
e3173832
SH		 4357static void sky2_shutdown(struct pci_dev *pdev)
4358{
4359 struct sky2_hw *hw = pci_get_drvdata(pdev);
4360 int i, wol = 0;
4361
549a68c3
SH		 4362 if (!hw)
4363 return;
4364
bea3348e 4365 napi_disable(&hw->napi);
e3173832
SH		 4366
4367 for (i = 0; i < hw->ports; i++) {
4368 struct net_device *dev = hw->dev[i];
4369 struct sky2_port *sky2 = netdev_priv(dev);
4370
4371 if (sky2->wol) {
4372 wol = 1;
4373 sky2_wol_init(sky2);
4374 }
4375 }
4376
4377 if (wol)
4378 sky2_power_aux(hw);
4379
4380 pci_enable_wake(pdev, PCI_D3hot, wol);
4381 pci_enable_wake(pdev, PCI_D3cold, wol);
4382
4383 pci_disable_device(pdev);
4384 pci_set_power_state(pdev, PCI_D3hot);
4385
4386}
4387
cd28ab6a 4388static struct pci_driver sky2_driver = {
793b883e
SH		 4389 .name = DRV_NAME,
4390 .id_table = sky2_id_table,
4391 .probe = sky2_probe,
4392 .remove = __devexit_p(sky2_remove),
cd28ab6a 4393#ifdef CONFIG_PM
793b883e
SH		 4394 .suspend = sky2_suspend,
4395 .resume = sky2_resume,
cd28ab6a 4396#endif
e3173832 4397 .shutdown = sky2_shutdown,
cd28ab6a
SH		 4398};
4399
4400static int __init sky2_init_module(void)
4401{
3cf26753 4402 sky2_debug_init();
50241c4c 4403 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 4404}
4405
4406static void __exit sky2_cleanup_module(void)
4407{
4408 pci_unregister_driver(&sky2_driver);
3cf26753 4409 sky2_debug_cleanup();
cd28ab6a
SH		 4410}
4411
4412module_init(sky2_init_module);
4413module_exit(sky2_cleanup_module);
4414
4415MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
65ebe634 4416MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
cd28ab6a 4417MODULE_LICENSE("GPL");
5f4f9dc1 4418MODULE_VERSION(DRV_VERSION);
kernel source for telekom puls (alcatel/mediatek)