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sky2: don't use AER routines
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
793b883e 25#include <linux/crc32.h>
cd28ab6a
SH		 26#include <linux/kernel.h>
27#include <linux/version.h>
28#include <linux/module.h>
29#include <linux/netdevice.h>
d0bbccfa 30#include <linux/dma-mapping.h>
cd28ab6a
SH		 31#include <linux/etherdevice.h>
32#include <linux/ethtool.h>
33#include <linux/pci.h>
34#include <linux/ip.h>
c9bdd4b5 35#include <net/ip.h>
cd28ab6a
SH		 36#include <linux/tcp.h>
37#include <linux/in.h>
38#include <linux/delay.h>
91c86df5 39#include <linux/workqueue.h>
d1f13708 40#include <linux/if_vlan.h>
d70cd51a 41#include <linux/prefetch.h>
3cf26753 42#include <linux/debugfs.h>
ef743d33 43#include <linux/mii.h>
cd28ab6a
SH		 44
45#include <asm/irq.h>
46
d1f13708
SH		 47#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48#define SKY2_VLAN_TAG_USED 1
49#endif
50
cd28ab6a
SH		 51#include "sky2.h"
52
53#define DRV_NAME "sky2"
1e354787 54#define DRV_VERSION "1.20"
cd28ab6a
SH		 55#define PFX DRV_NAME " "
56
57/*
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
14d0263f 60 * similar to Tigon3.
cd28ab6a
SH		 61 */
62
14d0263f 63#define RX_LE_SIZE 1024
cd28ab6a 64#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 65#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 66#define RX_DEF_PENDING RX_MAX_PENDING
82788c7a 67#define RX_SKB_ALIGN 8
793b883e
SH		 68
69#define TX_RING_SIZE 512
70#define TX_DEF_PENDING (TX_RING_SIZE - 1)
71#define TX_MIN_PENDING 64
b19666d9 72#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
cd28ab6a 73
793b883e 74#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a 75#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
cd28ab6a
SH		 76#define TX_WATCHDOG (5 * HZ)
77#define NAPI_WEIGHT 64
78#define PHY_RETRIES 1000
79
f4331a6d
SH		 80#define SKY2_EEPROM_MAGIC 0x9955aabb
81
82
cb5d9547
SH		 83#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
84
cd28ab6a 85static const u32 default_msg =
793b883e
SH		 86 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
87 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 88 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 89
793b883e 90static int debug = -1; /* defaults above */
cd28ab6a
SH		 91module_param(debug, int, 0);
92MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
93
14d0263f 94static int copybreak __read_mostly = 128;
bdb5c58e
SH		 95module_param(copybreak, int, 0);
96MODULE_PARM_DESC(copybreak, "Receive copy threshold");
97
fb2690a9
SH		 98static int disable_msi = 0;
99module_param(disable_msi, int, 0);
100MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
101
cd28ab6a 102static const struct pci_device_id sky2_id_table[] = {
e5b74c7d
SH		 103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
2d2a3871 105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
f1a0b6f5 108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
e5b74c7d
SH		 109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
05745c4a 121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
e5b74c7d 122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
5a37a68d 123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
05745c4a 124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
e5b74c7d
SH		 125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
05745c4a 130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
e5b74c7d
SH		 131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
f1a0b6f5
SH		 134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
69161611 136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
5a37a68d 137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
cd28ab6a
SH		 138 { 0 }
139};
793b883e 140
cd28ab6a
SH		 141MODULE_DEVICE_TABLE(pci, sky2_id_table);
142
143/* Avoid conditionals by using array */
144static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
145static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 146static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 147
92f965e8
SH		 148/* This driver supports yukon2 chipset only */
149static const char *yukon2_name[] = {
150 "XL", /* 0xb3 */
151 "EC Ultra", /* 0xb4 */
93745494 152 "Extreme", /* 0xb5 */
92f965e8
SH		 153 "EC", /* 0xb6 */
154 "FE", /* 0xb7 */
05745c4a 155 "FE+", /* 0xb8 */
793b883e
SH		 156};
157
d1b139c0
SH		 158static void sky2_set_multicast(struct net_device *dev);
159
af043aa5 160/* Access to PHY via serial interconnect */
ef743d33 161static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 162{
163 int i;
164
165 gma_write16(hw, port, GM_SMI_DATA, val);
166 gma_write16(hw, port, GM_SMI_CTRL,
167 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
168
169 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 170 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
171 if (ctrl == 0xffff)
172 goto io_error;
173
174 if (!(ctrl & GM_SMI_CT_BUSY))
ef743d33 175 return 0;
af043aa5
SH		 176
177 udelay(10);
cd28ab6a 178 }
ef743d33 179
af043aa5 180 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 181 return -ETIMEDOUT;
af043aa5
SH		 182
183io_error:
184 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
185 return -EIO;
cd28ab6a
SH		 186}
187
ef743d33 188static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 189{
190 int i;
191
793b883e 192 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 193 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
194
195 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 196 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
197 if (ctrl == 0xffff)
198 goto io_error;
199
200 if (ctrl & GM_SMI_CT_RD_VAL) {
ef743d33
SH		 201 *val = gma_read16(hw, port, GM_SMI_DATA);
202 return 0;
203 }
204
af043aa5 205 udelay(10);
cd28ab6a
SH		 206 }
207
af043aa5 208 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
ef743d33 209 return -ETIMEDOUT;
af043aa5
SH		 210io_error:
211 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
212 return -EIO;
ef743d33
SH		 213}
214
af043aa5 215static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
ef743d33
SH		 216{
217 u16 v;
af043aa5 218 __gm_phy_read(hw, port, reg, &v);
ef743d33 219 return v;
cd28ab6a
SH		 220}
221
5afa0a9c 222
ae306cca
SH		 223static void sky2_power_on(struct sky2_hw *hw)
224{
225 /* switch power to VCC (WA for VAUX problem) */
226 sky2_write8(hw, B0_POWER_CTRL,
227 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
5afa0a9c 228
ae306cca
SH		 229 /* disable Core Clock Division, */
230 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
d3bcfbeb 231
ae306cca
SH		 232 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
233 /* enable bits are inverted */
234 sky2_write8(hw, B2_Y2_CLK_GATE,
235 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
236 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
237 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
238 else
239 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
977bdf06 240
ea76e635 241 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
fc99fe06 242 u32 reg;
5afa0a9c 243
b32f40c4 244 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
b2345773 245
b32f40c4 246 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
fc99fe06
SH		 247 /* set all bits to 0 except bits 15..12 and 8 */
248 reg &= P_ASPM_CONTROL_MSK;
b32f40c4 249 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
fc99fe06 250
b32f40c4 251 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
fc99fe06
SH		 252 /* set all bits to 0 except bits 28 & 27 */
253 reg &= P_CTL_TIM_VMAIN_AV_MSK;
b32f40c4 254 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
fc99fe06 255
b32f40c4 256 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
8f70920f
SH		 257
258 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
259 reg = sky2_read32(hw, B2_GP_IO);
260 reg |= GLB_GPIO_STAT_RACE_DIS;
261 sky2_write32(hw, B2_GP_IO, reg);
b2345773
SH		 262
263 sky2_read32(hw, B2_GP_IO);
5afa0a9c 264 }
ae306cca 265}
5afa0a9c 266
ae306cca
SH		 267static void sky2_power_aux(struct sky2_hw *hw)
268{
269 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
270 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
271 else
272 /* enable bits are inverted */
273 sky2_write8(hw, B2_Y2_CLK_GATE,
274 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
275 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
276 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
277
278 /* switch power to VAUX */
279 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
280 sky2_write8(hw, B0_POWER_CTRL,
281 (PC_VAUX_ENA | PC_VCC_ENA |
282 PC_VAUX_ON | PC_VCC_OFF));
5afa0a9c
SH		 283}
284
d3bcfbeb 285static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 286{
287 u16 reg;
288
289 /* disable all GMAC IRQ's */
290 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
793b883e 291
cd28ab6a
SH		 292 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
293 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
294 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
295 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
296
297 reg = gma_read16(hw, port, GM_RX_CTRL);
298 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
299 gma_write16(hw, port, GM_RX_CTRL, reg);
300}
301
16ad91e1
SH		 302/* flow control to advertise bits */
303static const u16 copper_fc_adv[] = {
304 [FC_NONE] = 0,
305 [FC_TX] = PHY_M_AN_ASP,
306 [FC_RX] = PHY_M_AN_PC,
307 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
308};
309
310/* flow control to advertise bits when using 1000BaseX */
311static const u16 fiber_fc_adv[] = {
df3fe1f3 312 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
16ad91e1
SH		 313 [FC_TX] = PHY_M_P_ASYM_MD_X,
314 [FC_RX] = PHY_M_P_SYM_MD_X,
df3fe1f3 315 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
16ad91e1
SH		 316};
317
318/* flow control to GMA disable bits */
319static const u16 gm_fc_disable[] = {
320 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
321 [FC_TX] = GM_GPCR_FC_RX_DIS,
322 [FC_RX] = GM_GPCR_FC_TX_DIS,
323 [FC_BOTH] = 0,
324};
325
326
cd28ab6a
SH		 327static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
328{
329 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 330 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 331
ea76e635
SH		 332 if (sky2->autoneg == AUTONEG_ENABLE &&
333 !(hw->flags & SKY2_HW_NEWER_PHY)) {
cd28ab6a
SH		 334 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
335
336 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 337 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 338 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
339
53419c68 340 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
cd28ab6a 341 if (hw->chip_id == CHIP_ID_YUKON_EC)
53419c68 342 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 343 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
344 else
53419c68
SH		 345 /* set master & slave downshift counter to 1x */
346 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
cd28ab6a
SH		 347
348 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
349 }
350
351 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 352 if (sky2_is_copper(hw)) {
05745c4a 353 if (!(hw->flags & SKY2_HW_GIGABIT)) {
cd28ab6a
SH		 354 /* enable automatic crossover */
355 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
6d3105d5
SH		 356
357 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
358 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
359 u16 spec;
360
361 /* Enable Class A driver for FE+ A0 */
362 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
363 spec |= PHY_M_FESC_SEL_CL_A;
364 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
365 }
cd28ab6a
SH		 366 } else {
367 /* disable energy detect */
368 ctrl &= ~PHY_M_PC_EN_DET_MSK;
369
370 /* enable automatic crossover */
371 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
372
53419c68 373 /* downshift on PHY 88E1112 and 88E1149 is changed */
93745494 374 if (sky2->autoneg == AUTONEG_ENABLE
ea76e635 375 && (hw->flags & SKY2_HW_NEWER_PHY)) {
53419c68 376 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 377 ctrl &= ~PHY_M_PC_DSC_MSK;
378 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
379 }
380 }
cd28ab6a
SH		 381 } else {
382 /* workaround for deviation #4.88 (CRC errors) */
383 /* disable Automatic Crossover */
384
385 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 386 }
cd28ab6a 387
b89165f2
SH		 388 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
389
390 /* special setup for PHY 88E1112 Fiber */
ea76e635 391 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
b89165f2 392 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 393
b89165f2
SH		 394 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
395 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
396 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
397 ctrl &= ~PHY_M_MAC_MD_MSK;
398 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
399 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
400
401 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 402 /* select page 1 to access Fiber registers */
403 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 404
405 /* for SFP-module set SIGDET polarity to low */
406 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
407 ctrl |= PHY_M_FIB_SIGD_POL;
34dd962b 408 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
cd28ab6a 409 }
b89165f2
SH		 410
411 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 412 }
413
7800fddc 414 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 415 ct1000 = 0;
416 adv = PHY_AN_CSMA;
2eaba1a2 417 reg = 0;
cd28ab6a
SH		 418
419 if (sky2->autoneg == AUTONEG_ENABLE) {
b89165f2 420 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 421 if (sky2->advertising & ADVERTISED_1000baseT_Full)
422 ct1000 |= PHY_M_1000C_AFD;
423 if (sky2->advertising & ADVERTISED_1000baseT_Half)
424 ct1000 |= PHY_M_1000C_AHD;
425 if (sky2->advertising & ADVERTISED_100baseT_Full)
426 adv |= PHY_M_AN_100_FD;
427 if (sky2->advertising & ADVERTISED_100baseT_Half)
428 adv |= PHY_M_AN_100_HD;
429 if (sky2->advertising & ADVERTISED_10baseT_Full)
430 adv |= PHY_M_AN_10_FD;
431 if (sky2->advertising & ADVERTISED_10baseT_Half)
432 adv |= PHY_M_AN_10_HD;
709c6e7b 433
16ad91e1 434 adv |= copper_fc_adv[sky2->flow_mode];
b89165f2
SH		 435 } else { /* special defines for FIBER (88E1040S only) */
436 if (sky2->advertising & ADVERTISED_1000baseT_Full)
437 adv |= PHY_M_AN_1000X_AFD;
438 if (sky2->advertising & ADVERTISED_1000baseT_Half)
439 adv |= PHY_M_AN_1000X_AHD;
cd28ab6a 440
16ad91e1 441 adv |= fiber_fc_adv[sky2->flow_mode];
709c6e7b 442 }
cd28ab6a
SH		 443
444 /* Restart Auto-negotiation */
445 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
446 } else {
447 /* forced speed/duplex settings */
448 ct1000 = PHY_M_1000C_MSE;
449
2eaba1a2
SH		 450 /* Disable auto update for duplex flow control and speed */
451 reg |= GM_GPCR_AU_ALL_DIS;
cd28ab6a
SH		 452
453 switch (sky2->speed) {
454 case SPEED_1000:
455 ctrl |= PHY_CT_SP1000;
2eaba1a2 456 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 457 break;
458 case SPEED_100:
459 ctrl |= PHY_CT_SP100;
2eaba1a2 460 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 461 break;
462 }
463
2eaba1a2
SH		 464 if (sky2->duplex == DUPLEX_FULL) {
465 reg |= GM_GPCR_DUP_FULL;
466 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 467 } else if (sky2->speed < SPEED_1000)
468 sky2->flow_mode = FC_NONE;
2eaba1a2 469
2eaba1a2 470
16ad91e1 471 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 472
473 /* Forward pause packets to GMAC? */
16ad91e1 474 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 475 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
476 else
477 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 478 }
479
2eaba1a2
SH		 480 gma_write16(hw, port, GM_GP_CTRL, reg);
481
05745c4a 482 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a
SH		 483 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
484
485 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
486 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
487
488 /* Setup Phy LED's */
489 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
490 ledover = 0;
491
492 switch (hw->chip_id) {
493 case CHIP_ID_YUKON_FE:
494 /* on 88E3082 these bits are at 11..9 (shifted left) */
495 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
496
497 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
498
499 /* delete ACT LED control bits */
500 ctrl &= ~PHY_M_FELP_LED1_MSK;
501 /* change ACT LED control to blink mode */
502 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
503 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
504 break;
505
05745c4a
SH		 506 case CHIP_ID_YUKON_FE_P:
507 /* Enable Link Partner Next Page */
508 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
509 ctrl |= PHY_M_PC_ENA_LIP_NP;
510
511 /* disable Energy Detect and enable scrambler */
512 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
513 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
514
515 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
516 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
517 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
518 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
519
520 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
521 break;
522
cd28ab6a 523 case CHIP_ID_YUKON_XL:
793b883e 524 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 525
526 /* select page 3 to access LED control register */
527 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
528
529 /* set LED Function Control register */
ed6d32c7
SH		 530 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
531 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
532 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
533 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
534 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 535
536 /* set Polarity Control register */
537 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 538 (PHY_M_POLC_LS1_P_MIX(4) |
539 PHY_M_POLC_IS0_P_MIX(4) |
540 PHY_M_POLC_LOS_CTRL(2) |
541 PHY_M_POLC_INIT_CTRL(2) |
542 PHY_M_POLC_STA1_CTRL(2) |
543 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 544
545 /* restore page register */
793b883e 546 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 547 break;
93745494 548
ed6d32c7 549 case CHIP_ID_YUKON_EC_U:
93745494 550 case CHIP_ID_YUKON_EX:
ed6d32c7
SH		 551 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
552
553 /* select page 3 to access LED control register */
554 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
555
556 /* set LED Function Control register */
557 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
558 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
559 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
560 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
561 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
562
563 /* set Blink Rate in LED Timer Control Register */
564 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
565 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
566 /* restore page register */
567 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
568 break;
cd28ab6a
SH		 569
570 default:
571 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
572 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
573 /* turn off the Rx LED (LED_RX) */
0efdf262 574 ledover &= ~PHY_M_LED_MO_RX;
cd28ab6a
SH		 575 }
576
9467a8fc
SH		 577 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
578 hw->chip_rev == CHIP_REV_YU_EC_U_A1) {
977bdf06 579 /* apply fixes in PHY AFE */
ed6d32c7
SH		 580 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
581
977bdf06 582 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 583 gm_phy_write(hw, port, 0x18, 0xaa99);
584 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 585
977bdf06 586 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
ed6d32c7
SH		 587 gm_phy_write(hw, port, 0x18, 0xa204);
588 gm_phy_write(hw, port, 0x17, 0x2002);
977bdf06
SH		 589
590 /* set page register to 0 */
9467a8fc 591 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
05745c4a
SH		 592 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
593 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
594 /* apply workaround for integrated resistors calibration */
595 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
596 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
93745494 597 } else if (hw->chip_id != CHIP_ID_YUKON_EX) {
05745c4a 598 /* no effect on Yukon-XL */
977bdf06 599 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 600
977bdf06
SH		 601 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
602 /* turn on 100 Mbps LED (LED_LINK100) */
0efdf262 603 ledover |= PHY_M_LED_MO_100;
977bdf06 604 }
cd28ab6a 605
977bdf06
SH		 606 if (ledover)
607 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
608
609 }
2eaba1a2 610
d571b694 611 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 612 if (sky2->autoneg == AUTONEG_ENABLE)
613 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
614 else
615 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
616}
617
d3bcfbeb
SH		 618static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
619{
620 u32 reg1;
ff35164e
SH		 621 static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
622 static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
d3bcfbeb 623
b32f40c4 624 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
ff35164e 625 /* Turn on/off phy power saving */
d3bcfbeb 626 if (onoff)
d3bcfbeb
SH		 627 reg1 &= ~phy_power[port];
628 else
629 reg1 |= phy_power[port];
630
ff35164e
SH		 631 if (onoff && hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
632 reg1 |= coma_mode[port];
633
b32f40c4
SH		 634 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
635 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
167f53d0 636
d3bcfbeb
SH		 637 udelay(100);
638}
639
1b537565
SH		 640/* Force a renegotiation */
641static void sky2_phy_reinit(struct sky2_port *sky2)
642{
e07b1aa8 643 spin_lock_bh(&sky2->phy_lock);
1b537565 644 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 645 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 646}
647
e3173832
SH		 648/* Put device in state to listen for Wake On Lan */
649static void sky2_wol_init(struct sky2_port *sky2)
650{
651 struct sky2_hw *hw = sky2->hw;
652 unsigned port = sky2->port;
653 enum flow_control save_mode;
654 u16 ctrl;
655 u32 reg1;
656
657 /* Bring hardware out of reset */
658 sky2_write16(hw, B0_CTST, CS_RST_CLR);
659 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
660
661 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
662 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
663
664 /* Force to 10/100
665 * sky2_reset will re-enable on resume
666 */
667 save_mode = sky2->flow_mode;
668 ctrl = sky2->advertising;
669
670 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
671 sky2->flow_mode = FC_NONE;
672 sky2_phy_power(hw, port, 1);
673 sky2_phy_reinit(sky2);
674
675 sky2->flow_mode = save_mode;
676 sky2->advertising = ctrl;
677
678 /* Set GMAC to no flow control and auto update for speed/duplex */
679 gma_write16(hw, port, GM_GP_CTRL,
680 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
681 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
682
683 /* Set WOL address */
684 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
685 sky2->netdev->dev_addr, ETH_ALEN);
686
687 /* Turn on appropriate WOL control bits */
688 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
689 ctrl = 0;
690 if (sky2->wol & WAKE_PHY)
691 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
692 else
693 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
694
695 if (sky2->wol & WAKE_MAGIC)
696 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
697 else
698 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
699
700 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
701 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
702
703 /* Turn on legacy PCI-Express PME mode */
b32f40c4 704 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
e3173832 705 reg1 |= PCI_Y2_PME_LEGACY;
b32f40c4 706 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
e3173832
SH		 707
708 /* block receiver */
709 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
710
711}
712
69161611
SH		 713static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
714{
05745c4a
SH		 715 struct net_device *dev = hw->dev[port];
716
717 if (dev->mtu <= ETH_DATA_LEN)
69161611 718 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
05745c4a
SH		 719 TX_JUMBO_DIS | TX_STFW_ENA);
720
721 else if (hw->chip_id != CHIP_ID_YUKON_EC_U)
722 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
723 TX_STFW_ENA | TX_JUMBO_ENA);
724 else {
725 /* set Tx GMAC FIFO Almost Empty Threshold */
726 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
727 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
69161611 728
05745c4a
SH		 729 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
730 TX_JUMBO_ENA | TX_STFW_DIS);
69161611 731
05745c4a
SH		 732 /* Can't do offload because of lack of store/forward */
733 dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM);
69161611
SH		 734 }
735}
736
cd28ab6a
SH		 737static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
738{
739 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
740 u16 reg;
25cccecc 741 u32 rx_reg;
cd28ab6a
SH		 742 int i;
743 const u8 *addr = hw->dev[port]->dev_addr;
744
f350339c
SH		 745 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
746 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
cd28ab6a
SH		 747
748 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
749
793b883e 750 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 751 /* WA DEV_472 -- looks like crossed wires on port 2 */
752 /* clear GMAC 1 Control reset */
753 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
754 do {
755 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
756 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
757 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
758 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
759 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
760 }
761
793b883e 762 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 763
2eaba1a2
SH		 764 /* Enable Transmit FIFO Underrun */
765 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
766
e07b1aa8 767 spin_lock_bh(&sky2->phy_lock);
cd28ab6a 768 sky2_phy_init(hw, port);
e07b1aa8 769 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 770
771 /* MIB clear */
772 reg = gma_read16(hw, port, GM_PHY_ADDR);
773 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
774
43f2f104
SH		 775 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
776 gma_read16(hw, port, i);
cd28ab6a
SH		 777 gma_write16(hw, port, GM_PHY_ADDR, reg);
778
779 /* transmit control */
780 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
781
782 /* receive control reg: unicast + multicast + no FCS */
783 gma_write16(hw, port, GM_RX_CTRL,
793b883e 784 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 785
786 /* transmit flow control */
787 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
788
789 /* transmit parameter */
790 gma_write16(hw, port, GM_TX_PARAM,
791 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
792 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
793 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
794 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
795
796 /* serial mode register */
797 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 798 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 799
6b1a3aef 800 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 801 reg |= GM_SMOD_JUMBO_ENA;
802
803 gma_write16(hw, port, GM_SERIAL_MODE, reg);
804
cd28ab6a
SH		 805 /* virtual address for data */
806 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
807
793b883e
SH		 808 /* physical address: used for pause frames */
809 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
810
811 /* ignore counter overflows */
cd28ab6a
SH		 812 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
813 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
814 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
815
816 /* Configure Rx MAC FIFO */
817 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
25cccecc 818 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
05745c4a
SH		 819 if (hw->chip_id == CHIP_ID_YUKON_EX ||
820 hw->chip_id == CHIP_ID_YUKON_FE_P)
25cccecc 821 rx_reg |= GMF_RX_OVER_ON;
69161611 822
25cccecc 823 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
cd28ab6a 824
d571b694 825 /* Flush Rx MAC FIFO on any flow control or error */
42eeea01 826 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
cd28ab6a 827
8df9a876 828 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
05745c4a
SH		 829 reg = RX_GMF_FL_THR_DEF + 1;
830 /* Another magic mystery workaround from sk98lin */
831 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
832 hw->chip_rev == CHIP_REV_YU_FE2_A0)
833 reg = 0x178;
834 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
cd28ab6a
SH		 835
836 /* Configure Tx MAC FIFO */
837 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
838 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 839
e0c28116
SH		 840 /* On chips without ram buffer, pause is controled by MAC level */
841 if (sky2_read8(hw, B2_E_0) == 0) {
8df9a876 842 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
5a5b1ea0 843 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
b628ed98 844
69161611 845 sky2_set_tx_stfwd(hw, port);
5a5b1ea0
SH		 846 }
847
cd28ab6a
SH		 848}
849
67712901
SH		 850/* Assign Ram Buffer allocation to queue */
851static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 852{
67712901
SH		 853 u32 end;
854
855 /* convert from K bytes to qwords used for hw register */
856 start *= 1024/8;
857 space *= 1024/8;
858 end = start + space - 1;
793b883e 859
cd28ab6a
SH		 860 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
861 sky2_write32(hw, RB_ADDR(q, RB_START), start);
862 sky2_write32(hw, RB_ADDR(q, RB_END), end);
863 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
864 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
865
866 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 867 u32 tp = space - space/4;
793b883e 868
1c28f6ba
SH		 869 /* On receive queue's set the thresholds
870 * give receiver priority when > 3/4 full
871 * send pause when down to 2K
872 */
873 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
874 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 875
1c28f6ba
SH		 876 tp = space - 2048/8;
877 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
878 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 879 } else {
880 /* Enable store & forward on Tx queue's because
881 * Tx FIFO is only 1K on Yukon
882 */
883 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
884 }
885
886 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 887 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 888}
889
cd28ab6a 890/* Setup Bus Memory Interface */
af4ed7e6 891static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 892{
893 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
894 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
895 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 896 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 897}
898
cd28ab6a
SH		 899/* Setup prefetch unit registers. This is the interface between
900 * hardware and driver list elements
901 */
8cc048e3 902static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 903 u64 addr, u32 last)
904{
cd28ab6a
SH		 905 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
906 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
907 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
908 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
909 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
910 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 911
912 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 913}
914
793b883e
SH		 915static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
916{
917 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
918
cb5d9547 919 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
291ea614 920 le->ctrl = 0;
793b883e
SH		 921 return le;
922}
cd28ab6a 923
88f5f0ca
SH		 924static void tx_init(struct sky2_port *sky2)
925{
926 struct sky2_tx_le *le;
927
928 sky2->tx_prod = sky2->tx_cons = 0;
929 sky2->tx_tcpsum = 0;
930 sky2->tx_last_mss = 0;
931
932 le = get_tx_le(sky2);
933 le->addr = 0;
934 le->opcode = OP_ADDR64 | HW_OWNER;
935 sky2->tx_addr64 = 0;
936}
937
291ea614
SH		 938static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
939 struct sky2_tx_le *le)
940{
941 return sky2->tx_ring + (le - sky2->tx_le);
942}
943
290d4de5
SH		 944/* Update chip's next pointer */
945static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 946{
50432cb5 947 /* Make sure write' to descriptors are complete before we tell hardware */
762c2de2 948 wmb();
50432cb5
SH		 949 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
950
951 /* Synchronize I/O on since next processor may write to tail */
952 mmiowb();
cd28ab6a
SH		 953}
954
793b883e 955
cd28ab6a
SH		 956static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
957{
958 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 959 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 960 le->ctrl = 0;
cd28ab6a
SH		 961 return le;
962}
963
14d0263f
SH		 964/* Build description to hardware for one receive segment */
965static void sky2_rx_add(struct sky2_port *sky2, u8 op,
966 dma_addr_t map, unsigned len)
cd28ab6a
SH		 967{
968 struct sky2_rx_le *le;
36eb0c71 969 u32 hi = upper_32_bits(map);
cd28ab6a 970
793b883e 971 if (sky2->rx_addr64 != hi) {
cd28ab6a 972 le = sky2_next_rx(sky2);
793b883e 973 le->addr = cpu_to_le32(hi);
cd28ab6a 974 le->opcode = OP_ADDR64 | HW_OWNER;
36eb0c71 975 sky2->rx_addr64 = upper_32_bits(map + len);
cd28ab6a 976 }
793b883e 977
cd28ab6a 978 le = sky2_next_rx(sky2);
734d1868
SH		 979 le->addr = cpu_to_le32((u32) map);
980 le->length = cpu_to_le16(len);
14d0263f 981 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 982}
983
14d0263f
SH		 984/* Build description to hardware for one possibly fragmented skb */
985static void sky2_rx_submit(struct sky2_port *sky2,
986 const struct rx_ring_info *re)
987{
988 int i;
989
990 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
991
992 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
993 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
994}
995
996
997static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
998 unsigned size)
999{
1000 struct sk_buff *skb = re->skb;
1001 int i;
1002
1003 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
1004 pci_unmap_len_set(re, data_size, size);
1005
1006 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1007 re->frag_addr[i] = pci_map_page(pdev,
1008 skb_shinfo(skb)->frags[i].page,
1009 skb_shinfo(skb)->frags[i].page_offset,
1010 skb_shinfo(skb)->frags[i].size,
1011 PCI_DMA_FROMDEVICE);
1012}
1013
1014static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1015{
1016 struct sk_buff *skb = re->skb;
1017 int i;
1018
1019 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1020 PCI_DMA_FROMDEVICE);
1021
1022 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1023 pci_unmap_page(pdev, re->frag_addr[i],
1024 skb_shinfo(skb)->frags[i].size,
1025 PCI_DMA_FROMDEVICE);
1026}
793b883e 1027
cd28ab6a
SH		 1028/* Tell chip where to start receive checksum.
1029 * Actually has two checksums, but set both same to avoid possible byte
1030 * order problems.
1031 */
793b883e 1032static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a 1033{
ea76e635 1034 struct sky2_rx_le *le = sky2_next_rx(sky2);
793b883e 1035
ea76e635
SH		 1036 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1037 le->ctrl = 0;
1038 le->opcode = OP_TCPSTART | HW_OWNER;
cd28ab6a 1039
ea76e635
SH		 1040 sky2_write32(sky2->hw,
1041 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1042 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 1043}
1044
6b1a3aef
SH		 1045/*
1046 * The RX Stop command will not work for Yukon-2 if the BMU does not
1047 * reach the end of packet and since we can't make sure that we have
1048 * incoming data, we must reset the BMU while it is not doing a DMA
1049 * transfer. Since it is possible that the RX path is still active,
1050 * the RX RAM buffer will be stopped first, so any possible incoming
1051 * data will not trigger a DMA. After the RAM buffer is stopped, the
1052 * BMU is polled until any DMA in progress is ended and only then it
1053 * will be reset.
1054 */
1055static void sky2_rx_stop(struct sky2_port *sky2)
1056{
1057 struct sky2_hw *hw = sky2->hw;
1058 unsigned rxq = rxqaddr[sky2->port];
1059 int i;
1060
1061 /* disable the RAM Buffer receive queue */
1062 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1063
1064 for (i = 0; i < 0xffff; i++)
1065 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1066 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1067 goto stopped;
1068
1069 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1070 sky2->netdev->name);
1071stopped:
1072 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1073
1074 /* reset the Rx prefetch unit */
1075 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
50432cb5 1076 mmiowb();
6b1a3aef 1077}
793b883e 1078
d571b694 1079/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 1080static void sky2_rx_clean(struct sky2_port *sky2)
1081{
1082 unsigned i;
1083
1084 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 1085 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 1086 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 1087
1088 if (re->skb) {
14d0263f 1089 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 1090 kfree_skb(re->skb);
1091 re->skb = NULL;
1092 }
1093 }
1094}
1095
ef743d33
SH		 1096/* Basic MII support */
1097static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1098{
1099 struct mii_ioctl_data *data = if_mii(ifr);
1100 struct sky2_port *sky2 = netdev_priv(dev);
1101 struct sky2_hw *hw = sky2->hw;
1102 int err = -EOPNOTSUPP;
1103
1104 if (!netif_running(dev))
1105 return -ENODEV; /* Phy still in reset */
1106
d89e1343 1107 switch (cmd) {
ef743d33
SH		 1108 case SIOCGMIIPHY:
1109 data->phy_id = PHY_ADDR_MARV;
1110
1111 /* fallthru */
1112 case SIOCGMIIREG: {
1113 u16 val = 0;
91c86df5 1114
e07b1aa8 1115 spin_lock_bh(&sky2->phy_lock);
ef743d33 1116 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 1117 spin_unlock_bh(&sky2->phy_lock);
91c86df5 1118
ef743d33
SH		 1119 data->val_out = val;
1120 break;
1121 }
1122
1123 case SIOCSMIIREG:
1124 if (!capable(CAP_NET_ADMIN))
1125 return -EPERM;
1126
e07b1aa8 1127 spin_lock_bh(&sky2->phy_lock);
ef743d33
SH		 1128 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1129 data->val_in);
e07b1aa8 1130 spin_unlock_bh(&sky2->phy_lock);
ef743d33
SH		 1131 break;
1132 }
1133 return err;
1134}
1135
d1f13708
SH		 1136#ifdef SKY2_VLAN_TAG_USED
1137static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1138{
1139 struct sky2_port *sky2 = netdev_priv(dev);
1140 struct sky2_hw *hw = sky2->hw;
1141 u16 port = sky2->port;
d1f13708 1142
2bb8c262 1143 netif_tx_lock_bh(dev);
bea3348e 1144 napi_disable(&hw->napi);
d1f13708 1145
d1f13708 1146 sky2->vlgrp = grp;
3d4e66f5
SH		 1147 if (grp) {
1148 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1149 RX_VLAN_STRIP_ON);
1150 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1151 TX_VLAN_TAG_ON);
1152 } else {
1153 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1154 RX_VLAN_STRIP_OFF);
1155 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1156 TX_VLAN_TAG_OFF);
1157 }
d1f13708 1158
bea3348e 1159 napi_enable(&hw->napi);
2bb8c262 1160 netif_tx_unlock_bh(dev);
d1f13708
SH		 1161}
1162#endif
1163
82788c7a 1164/*
14d0263f
SH		 1165 * Allocate an skb for receiving. If the MTU is large enough
1166 * make the skb non-linear with a fragment list of pages.
1167 *
82788c7a
SH		 1168 * It appears the hardware has a bug in the FIFO logic that
1169 * cause it to hang if the FIFO gets overrun and the receive buffer
497d7c86
SH		 1170 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1171 * aligned except if slab debugging is enabled.
82788c7a 1172 */
14d0263f 1173static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1174{
1175 struct sk_buff *skb;
14d0263f
SH		 1176 unsigned long p;
1177 int i;
82788c7a 1178
14d0263f
SH		 1179 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + RX_SKB_ALIGN);
1180 if (!skb)
1181 goto nomem;
1182
1183 p = (unsigned long) skb->data;
1184 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
1185
1186 for (i = 0; i < sky2->rx_nfrags; i++) {
1187 struct page *page = alloc_page(GFP_ATOMIC);
1188
1189 if (!page)
1190 goto free_partial;
1191 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1192 }
1193
1194 return skb;
14d0263f
SH		 1195free_partial:
1196 kfree_skb(skb);
1197nomem:
1198 return NULL;
82788c7a
SH		 1199}
1200
55c9dd35
SH		 1201static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1202{
1203 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1204}
1205
cd28ab6a
SH		 1206/*
1207 * Allocate and setup receiver buffer pool.
14d0263f
SH		 1208 * Normal case this ends up creating one list element for skb
1209 * in the receive ring. Worst case if using large MTU and each
1210 * allocation falls on a different 64 bit region, that results
1211 * in 6 list elements per ring entry.
1212 * One element is used for checksum enable/disable, and one
1213 * extra to avoid wrap.
cd28ab6a 1214 */
6b1a3aef 1215static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1216{
6b1a3aef 1217 struct sky2_hw *hw = sky2->hw;
14d0263f 1218 struct rx_ring_info *re;
6b1a3aef 1219 unsigned rxq = rxqaddr[sky2->port];
14d0263f 1220 unsigned i, size, space, thresh;
cd28ab6a 1221
6b1a3aef 1222 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1223 sky2_qset(hw, rxq);
977bdf06 1224
c3905bc4
SH		 1225 /* On PCI express lowering the watermark gives better performance */
1226 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1227 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1228
1229 /* These chips have no ram buffer?
1230 * MAC Rx RAM Read is controlled by hardware */
8df9a876 1231 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
c3905bc4
SH		 1232 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1233 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
f449c7c1 1234 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
977bdf06 1235
6b1a3aef
SH		 1236 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1237
ea76e635
SH		 1238 if (!(hw->flags & SKY2_HW_NEW_LE))
1239 rx_set_checksum(sky2);
14d0263f
SH		 1240
1241 /* Space needed for frame data + headers rounded up */
f957da2a 1242 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
14d0263f
SH		 1243
1244 /* Stopping point for hardware truncation */
1245 thresh = (size - 8) / sizeof(u32);
1246
1247 /* Account for overhead of skb - to avoid order > 0 allocation */
1248 space = SKB_DATA_ALIGN(size) + NET_SKB_PAD
1249 + sizeof(struct skb_shared_info);
1250
1251 sky2->rx_nfrags = space >> PAGE_SHIFT;
1252 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1253
1254 if (sky2->rx_nfrags != 0) {
1255 /* Compute residue after pages */
1256 space = sky2->rx_nfrags << PAGE_SHIFT;
1257
1258 if (space < size)
1259 size -= space;
1260 else
1261 size = 0;
1262
1263 /* Optimize to handle small packets and headers */
1264 if (size < copybreak)
1265 size = copybreak;
1266 if (size < ETH_HLEN)
1267 size = ETH_HLEN;
1268 }
1269 sky2->rx_data_size = size;
1270
1271 /* Fill Rx ring */
793b883e 1272 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1273 re = sky2->rx_ring + i;
cd28ab6a 1274
14d0263f 1275 re->skb = sky2_rx_alloc(sky2);
cd28ab6a
SH		 1276 if (!re->skb)
1277 goto nomem;
1278
14d0263f
SH		 1279 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1280 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1281 }
1282
a1433ac4
SH		 1283 /*
1284 * The receiver hangs if it receives frames larger than the
1285 * packet buffer. As a workaround, truncate oversize frames, but
1286 * the register is limited to 9 bits, so if you do frames > 2052
1287 * you better get the MTU right!
1288 */
a1433ac4
SH		 1289 if (thresh > 0x1ff)
1290 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1291 else {
1292 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1293 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1294 }
1295
6b1a3aef 1296 /* Tell chip about available buffers */
55c9dd35 1297 sky2_rx_update(sky2, rxq);
cd28ab6a
SH		 1298 return 0;
1299nomem:
1300 sky2_rx_clean(sky2);
1301 return -ENOMEM;
1302}
1303
1304/* Bring up network interface. */
1305static int sky2_up(struct net_device *dev)
1306{
1307 struct sky2_port *sky2 = netdev_priv(dev);
1308 struct sky2_hw *hw = sky2->hw;
1309 unsigned port = sky2->port;
e0c28116 1310 u32 imask, ramsize;
ee7abb04 1311 int cap, err = -ENOMEM;
843a46f4 1312 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1313
ee7abb04
SH		 1314 /*
1315 * On dual port PCI-X card, there is an problem where status
1316 * can be received out of order due to split transactions
843a46f4 1317 */
ee7abb04
SH		 1318 if (otherdev && netif_running(otherdev) &&
1319 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
ee7abb04
SH		 1320 u16 cmd;
1321
b32f40c4 1322 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
ee7abb04 1323 cmd &= ~PCI_X_CMD_MAX_SPLIT;
b32f40c4
SH		 1324 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1325
ee7abb04 1326 }
843a46f4 1327
cd28ab6a
SH		 1328 if (netif_msg_ifup(sky2))
1329 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1330
55d7b4e6
SH		 1331 netif_carrier_off(dev);
1332
cd28ab6a
SH		 1333 /* must be power of 2 */
1334 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 1335 TX_RING_SIZE *
1336 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 1337 &sky2->tx_le_map);
1338 if (!sky2->tx_le)
1339 goto err_out;
1340
6cdbbdf3 1341 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 1342 GFP_KERNEL);
1343 if (!sky2->tx_ring)
1344 goto err_out;
88f5f0ca
SH		 1345
1346 tx_init(sky2);
cd28ab6a
SH		 1347
1348 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1349 &sky2->rx_le_map);
1350 if (!sky2->rx_le)
1351 goto err_out;
1352 memset(sky2->rx_le, 0, RX_LE_BYTES);
1353
291ea614 1354 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
cd28ab6a
SH		 1355 GFP_KERNEL);
1356 if (!sky2->rx_ring)
1357 goto err_out;
1358
d3bcfbeb
SH		 1359 sky2_phy_power(hw, port, 1);
1360
cd28ab6a
SH		 1361 sky2_mac_init(hw, port);
1362
e0c28116
SH		 1363 /* Register is number of 4K blocks on internal RAM buffer. */
1364 ramsize = sky2_read8(hw, B2_E_0) * 4;
1365 if (ramsize > 0) {
67712901 1366 u32 rxspace;
cd28ab6a 1367
e0c28116 1368 pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
67712901
SH		 1369 if (ramsize < 16)
1370 rxspace = ramsize / 2;
1371 else
1372 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1373
67712901
SH		 1374 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1375 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1376
1377 /* Make sure SyncQ is disabled */
1378 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1379 RB_RST_SET);
1380 }
793b883e 1381
af4ed7e6 1382 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1383
69161611
SH		 1384 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1385 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1386 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1387
977bdf06 1388 /* Set almost empty threshold */
c2716fb4
SH		 1389 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1390 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
b628ed98 1391 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
5a5b1ea0 1392
6b1a3aef
SH		 1393 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1394 TX_RING_SIZE - 1);
cd28ab6a 1395
6b1a3aef 1396 err = sky2_rx_start(sky2);
6de16237 1397 if (err)
cd28ab6a
SH		 1398 goto err_out;
1399
cd28ab6a 1400 /* Enable interrupts from phy/mac for port */
e07b1aa8 1401 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1402 imask |= portirq_msk[port];
e07b1aa8
SH		 1403 sky2_write32(hw, B0_IMSK, imask);
1404
cd28ab6a
SH		 1405 return 0;
1406
1407err_out:
1b537565 1408 if (sky2->rx_le) {
cd28ab6a
SH		 1409 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1410 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1411 sky2->rx_le = NULL;
1412 }
1413 if (sky2->tx_le) {
cd28ab6a
SH		 1414 pci_free_consistent(hw->pdev,
1415 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1416 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1417 sky2->tx_le = NULL;
1418 }
1419 kfree(sky2->tx_ring);
1420 kfree(sky2->rx_ring);
cd28ab6a 1421
1b537565
SH		 1422 sky2->tx_ring = NULL;
1423 sky2->rx_ring = NULL;
cd28ab6a
SH		 1424 return err;
1425}
1426
793b883e
SH		 1427/* Modular subtraction in ring */
1428static inline int tx_dist(unsigned tail, unsigned head)
1429{
cb5d9547 1430 return (head - tail) & (TX_RING_SIZE - 1);
793b883e 1431}
cd28ab6a 1432
793b883e
SH		 1433/* Number of list elements available for next tx */
1434static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1435{
793b883e 1436 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1437}
1438
793b883e 1439/* Estimate of number of transmit list elements required */
28bd181a 1440static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1441{
793b883e
SH		 1442 unsigned count;
1443
1444 count = sizeof(dma_addr_t) / sizeof(u32);
1445 count += skb_shinfo(skb)->nr_frags * count;
1446
89114afd 1447 if (skb_is_gso(skb))
793b883e
SH		 1448 ++count;
1449
84fa7933 1450 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1451 ++count;
1452
1453 return count;
cd28ab6a
SH		 1454}
1455
793b883e
SH		 1456/*
1457 * Put one packet in ring for transmit.
1458 * A single packet can generate multiple list elements, and
1459 * the number of ring elements will probably be less than the number
1460 * of list elements used.
1461 */
cd28ab6a
SH		 1462static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1463{
1464 struct sky2_port *sky2 = netdev_priv(dev);
1465 struct sky2_hw *hw = sky2->hw;
d1f13708 1466 struct sky2_tx_le *le = NULL;
6cdbbdf3 1467 struct tx_ring_info *re;
cd28ab6a
SH		 1468 unsigned i, len;
1469 dma_addr_t mapping;
1470 u32 addr64;
1471 u16 mss;
1472 u8 ctrl;
1473
2bb8c262
SH		 1474 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1475 return NETDEV_TX_BUSY;
cd28ab6a 1476
793b883e 1477 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 1478 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1479 dev->name, sky2->tx_prod, skb->len);
1480
cd28ab6a
SH		 1481 len = skb_headlen(skb);
1482 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
36eb0c71 1483 addr64 = upper_32_bits(mapping);
793b883e 1484
a018e330 1485 /* Send high bits if changed or crosses boundary */
36eb0c71
SH		 1486 if (addr64 != sky2->tx_addr64 ||
1487 upper_32_bits(mapping + len) != sky2->tx_addr64) {
793b883e 1488 le = get_tx_le(sky2);
f65b138c 1489 le->addr = cpu_to_le32(addr64);
793b883e 1490 le->opcode = OP_ADDR64 | HW_OWNER;
36eb0c71 1491 sky2->tx_addr64 = upper_32_bits(mapping + len);
793b883e 1492 }
cd28ab6a
SH		 1493
1494 /* Check for TCP Segmentation Offload */
7967168c 1495 mss = skb_shinfo(skb)->gso_size;
793b883e 1496 if (mss != 0) {
ea76e635
SH		 1497
1498 if (!(hw->flags & SKY2_HW_NEW_LE))
69161611
SH		 1499 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1500
1501 if (mss != sky2->tx_last_mss) {
1502 le = get_tx_le(sky2);
1503 le->addr = cpu_to_le32(mss);
ea76e635
SH		 1504
1505 if (hw->flags & SKY2_HW_NEW_LE)
69161611
SH		 1506 le->opcode = OP_MSS | HW_OWNER;
1507 else
1508 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd
SH		 1509 sky2->tx_last_mss = mss;
1510 }
cd28ab6a
SH		 1511 }
1512
cd28ab6a 1513 ctrl = 0;
d1f13708
SH		 1514#ifdef SKY2_VLAN_TAG_USED
1515 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1516 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1517 if (!le) {
1518 le = get_tx_le(sky2);
f65b138c 1519 le->addr = 0;
d1f13708 1520 le->opcode = OP_VLAN|HW_OWNER;
d1f13708
SH		 1521 } else
1522 le->opcode |= OP_VLAN;
1523 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1524 ctrl |= INS_VLAN;
1525 }
1526#endif
1527
1528 /* Handle TCP checksum offload */
84fa7933 1529 if (skb->ip_summed == CHECKSUM_PARTIAL) {
69161611 1530 /* On Yukon EX (some versions) encoding change. */
ea76e635 1531 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
69161611
SH		 1532 ctrl |= CALSUM; /* auto checksum */
1533 else {
1534 const unsigned offset = skb_transport_offset(skb);
1535 u32 tcpsum;
1536
1537 tcpsum = offset << 16; /* sum start */
1538 tcpsum |= offset + skb->csum_offset; /* sum write */
1539
1540 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1541 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1542 ctrl |= UDPTCP;
1543
1544 if (tcpsum != sky2->tx_tcpsum) {
1545 sky2->tx_tcpsum = tcpsum;
1546
1547 le = get_tx_le(sky2);
1548 le->addr = cpu_to_le32(tcpsum);
1549 le->length = 0; /* initial checksum value */
1550 le->ctrl = 1; /* one packet */
1551 le->opcode = OP_TCPLISW | HW_OWNER;
1552 }
1d179332 1553 }
cd28ab6a
SH		 1554 }
1555
1556 le = get_tx_le(sky2);
f65b138c 1557 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1558 le->length = cpu_to_le16(len);
1559 le->ctrl = ctrl;
793b883e 1560 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1561
291ea614 1562 re = tx_le_re(sky2, le);
cd28ab6a 1563 re->skb = skb;
6cdbbdf3 1564 pci_unmap_addr_set(re, mapaddr, mapping);
291ea614 1565 pci_unmap_len_set(re, maplen, len);
cd28ab6a
SH		 1566
1567 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1568 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1569
1570 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1571 frag->size, PCI_DMA_TODEVICE);
36eb0c71 1572 addr64 = upper_32_bits(mapping);
793b883e
SH		 1573 if (addr64 != sky2->tx_addr64) {
1574 le = get_tx_le(sky2);
f65b138c 1575 le->addr = cpu_to_le32(addr64);
793b883e
SH		 1576 le->ctrl = 0;
1577 le->opcode = OP_ADDR64 | HW_OWNER;
1578 sky2->tx_addr64 = addr64;
cd28ab6a
SH		 1579 }
1580
1581 le = get_tx_le(sky2);
f65b138c 1582 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1583 le->length = cpu_to_le16(frag->size);
1584 le->ctrl = ctrl;
793b883e 1585 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1586
291ea614
SH		 1587 re = tx_le_re(sky2, le);
1588 re->skb = skb;
1589 pci_unmap_addr_set(re, mapaddr, mapping);
1590 pci_unmap_len_set(re, maplen, frag->size);
cd28ab6a 1591 }
6cdbbdf3 1592
cd28ab6a
SH		 1593 le->ctrl |= EOP;
1594
97bda706
SH		 1595 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1596 netif_stop_queue(dev);
b19666d9 1597
290d4de5 1598 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1599
cd28ab6a
SH		 1600 dev->trans_start = jiffies;
1601 return NETDEV_TX_OK;
1602}
1603
cd28ab6a 1604/*
793b883e
SH		 1605 * Free ring elements from starting at tx_cons until "done"
1606 *
1607 * NB: the hardware will tell us about partial completion of multi-part
291ea614 1608 * buffers so make sure not to free skb to early.
cd28ab6a 1609 */
d11c13e7 1610static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1611{
d11c13e7 1612 struct net_device *dev = sky2->netdev;
af2a58ac 1613 struct pci_dev *pdev = sky2->hw->pdev;
291ea614 1614 unsigned idx;
cd28ab6a 1615
0e3ff6aa 1616 BUG_ON(done >= TX_RING_SIZE);
2224795d 1617
291ea614
SH		 1618 for (idx = sky2->tx_cons; idx != done;
1619 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1620 struct sky2_tx_le *le = sky2->tx_le + idx;
1621 struct tx_ring_info *re = sky2->tx_ring + idx;
1622
1623 switch(le->opcode & ~HW_OWNER) {
1624 case OP_LARGESEND:
1625 case OP_PACKET:
1626 pci_unmap_single(pdev,
1627 pci_unmap_addr(re, mapaddr),
1628 pci_unmap_len(re, maplen),
1629 PCI_DMA_TODEVICE);
af2a58ac 1630 break;
291ea614
SH		 1631 case OP_BUFFER:
1632 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1633 pci_unmap_len(re, maplen),
734d1868 1634 PCI_DMA_TODEVICE);
291ea614
SH		 1635 break;
1636 }
1637
1638 if (le->ctrl & EOP) {
1639 if (unlikely(netif_msg_tx_done(sky2)))
1640 printk(KERN_DEBUG "%s: tx done %u\n",
1641 dev->name, idx);
3cf26753 1642
7138a0f5
SH		 1643 dev->stats.tx_packets++;
1644 dev->stats.tx_bytes += re->skb->len;
2bf56fe2 1645
794b2bd2 1646 dev_kfree_skb_any(re->skb);
3cf26753 1647 sky2->tx_next = RING_NEXT(idx, TX_RING_SIZE);
cd28ab6a 1648 }
793b883e 1649 }
793b883e 1650
291ea614 1651 sky2->tx_cons = idx;
50432cb5
SH		 1652 smp_mb();
1653
22e11703 1654 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
cd28ab6a 1655 netif_wake_queue(dev);
cd28ab6a
SH		 1656}
1657
1658/* Cleanup all untransmitted buffers, assume transmitter not running */
2bb8c262 1659static void sky2_tx_clean(struct net_device *dev)
cd28ab6a 1660{
2bb8c262
SH		 1661 struct sky2_port *sky2 = netdev_priv(dev);
1662
1663 netif_tx_lock_bh(dev);
d11c13e7 1664 sky2_tx_complete(sky2, sky2->tx_prod);
2bb8c262 1665 netif_tx_unlock_bh(dev);
cd28ab6a
SH		 1666}
1667
1668/* Network shutdown */
1669static int sky2_down(struct net_device *dev)
1670{
1671 struct sky2_port *sky2 = netdev_priv(dev);
1672 struct sky2_hw *hw = sky2->hw;
1673 unsigned port = sky2->port;
1674 u16 ctrl;
e07b1aa8 1675 u32 imask;
cd28ab6a 1676
1b537565
SH		 1677 /* Never really got started! */
1678 if (!sky2->tx_le)
1679 return 0;
1680
cd28ab6a
SH		 1681 if (netif_msg_ifdown(sky2))
1682 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1683
018d1c66 1684 /* Stop more packets from being queued */
cd28ab6a
SH		 1685 netif_stop_queue(dev);
1686
ebc646f6
SH		 1687 /* Disable port IRQ */
1688 imask = sky2_read32(hw, B0_IMSK);
1689 imask &= ~portirq_msk[port];
1690 sky2_write32(hw, B0_IMSK, imask);
1691
6de16237
SH		 1692 synchronize_irq(hw->pdev->irq);
1693
d3bcfbeb 1694 sky2_gmac_reset(hw, port);
793b883e 1695
cd28ab6a
SH		 1696 /* Stop transmitter */
1697 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1698 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1699
1700 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1701 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1702
1703 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1704 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1705 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1706
6de16237
SH		 1707 /* Make sure no packets are pending */
1708 napi_synchronize(&hw->napi);
1709
cd28ab6a
SH		 1710 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1711
1712 /* Workaround shared GMAC reset */
793b883e
SH		 1713 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1714 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1715 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1716
1717 /* Disable Force Sync bit and Enable Alloc bit */
1718 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1719 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1720
1721 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1722 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1723 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1724
1725 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1726 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1727 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1728
1729 /* Reset the Tx prefetch units */
1730 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1731 PREF_UNIT_RST_SET);
1732
1733 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1734
6b1a3aef 1735 sky2_rx_stop(sky2);
cd28ab6a
SH		 1736
1737 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1738 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1739
d3bcfbeb
SH		 1740 sky2_phy_power(hw, port, 0);
1741
55d7b4e6
SH		 1742 netif_carrier_off(dev);
1743
d571b694 1744 /* turn off LED's */
cd28ab6a
SH		 1745 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1746
2bb8c262 1747 sky2_tx_clean(dev);
cd28ab6a
SH		 1748 sky2_rx_clean(sky2);
1749
1750 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1751 sky2->rx_le, sky2->rx_le_map);
1752 kfree(sky2->rx_ring);
1753
1754 pci_free_consistent(hw->pdev,
1755 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1756 sky2->tx_le, sky2->tx_le_map);
1757 kfree(sky2->tx_ring);
1758
1b537565
SH		 1759 sky2->tx_le = NULL;
1760 sky2->rx_le = NULL;
1761
1762 sky2->rx_ring = NULL;
1763 sky2->tx_ring = NULL;
1764
cd28ab6a
SH		 1765 return 0;
1766}
1767
1768static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1769{
ea76e635 1770 if (hw->flags & SKY2_HW_FIBRE_PHY)
793b883e
SH		 1771 return SPEED_1000;
1772
05745c4a
SH		 1773 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1774 if (aux & PHY_M_PS_SPEED_100)
1775 return SPEED_100;
1776 else
1777 return SPEED_10;
1778 }
cd28ab6a
SH		 1779
1780 switch (aux & PHY_M_PS_SPEED_MSK) {
1781 case PHY_M_PS_SPEED_1000:
1782 return SPEED_1000;
1783 case PHY_M_PS_SPEED_100:
1784 return SPEED_100;
1785 default:
1786 return SPEED_10;
1787 }
1788}
1789
1790static void sky2_link_up(struct sky2_port *sky2)
1791{
1792 struct sky2_hw *hw = sky2->hw;
1793 unsigned port = sky2->port;
1794 u16 reg;
16ad91e1
SH		 1795 static const char *fc_name[] = {
1796 [FC_NONE] = "none",
1797 [FC_TX] = "tx",
1798 [FC_RX] = "rx",
1799 [FC_BOTH] = "both",
1800 };
cd28ab6a 1801
cd28ab6a 1802 /* enable Rx/Tx */
2eaba1a2 1803 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 1804 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1805 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 1806
1807 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1808
1809 netif_carrier_on(sky2->netdev);
cd28ab6a 1810
75e80683 1811 mod_timer(&hw->watchdog_timer, jiffies + 1);
32c2c300 1812
cd28ab6a 1813 /* Turn on link LED */
793b883e 1814 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1815 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1816
1817 if (netif_msg_link(sky2))
1818 printk(KERN_INFO PFX
d571b694 1819 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1820 sky2->netdev->name, sky2->speed,
1821 sky2->duplex == DUPLEX_FULL ? "full" : "half",
16ad91e1 1822 fc_name[sky2->flow_status]);
cd28ab6a
SH		 1823}
1824
1825static void sky2_link_down(struct sky2_port *sky2)
1826{
1827 struct sky2_hw *hw = sky2->hw;
1828 unsigned port = sky2->port;
1829 u16 reg;
1830
1831 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1832
1833 reg = gma_read16(hw, port, GM_GP_CTRL);
1834 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1835 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 1836
cd28ab6a 1837 netif_carrier_off(sky2->netdev);
cd28ab6a
SH		 1838
1839 /* Turn on link LED */
1840 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1841
1842 if (netif_msg_link(sky2))
1843 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2eaba1a2 1844
cd28ab6a
SH		 1845 sky2_phy_init(hw, port);
1846}
1847
16ad91e1
SH		 1848static enum flow_control sky2_flow(int rx, int tx)
1849{
1850 if (rx)
1851 return tx ? FC_BOTH : FC_RX;
1852 else
1853 return tx ? FC_TX : FC_NONE;
1854}
1855
793b883e
SH		 1856static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1857{
1858 struct sky2_hw *hw = sky2->hw;
1859 unsigned port = sky2->port;
da4c1ff4 1860 u16 advert, lpa;
793b883e 1861
da4c1ff4 1862 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
793b883e 1863 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
793b883e
SH		 1864 if (lpa & PHY_M_AN_RF) {
1865 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1866 return -1;
1867 }
1868
793b883e
SH		 1869 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1870 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1871 sky2->netdev->name);
1872 return -1;
1873 }
1874
793b883e 1875 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 1876 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e 1877
da4c1ff4
SH		 1878 /* Since the pause result bits seem to in different positions on
1879 * different chips. look at registers.
1880 */
ea76e635 1881 if (hw->flags & SKY2_HW_FIBRE_PHY) {
da4c1ff4
SH		 1882 /* Shift for bits in fiber PHY */
1883 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
1884 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
1885
1886 if (advert & ADVERTISE_1000XPAUSE)
1887 advert |= ADVERTISE_PAUSE_CAP;
1888 if (advert & ADVERTISE_1000XPSE_ASYM)
1889 advert |= ADVERTISE_PAUSE_ASYM;
1890 if (lpa & LPA_1000XPAUSE)
1891 lpa |= LPA_PAUSE_CAP;
1892 if (lpa & LPA_1000XPAUSE_ASYM)
1893 lpa |= LPA_PAUSE_ASYM;
1894 }
793b883e 1895
da4c1ff4
SH		 1896 sky2->flow_status = FC_NONE;
1897 if (advert & ADVERTISE_PAUSE_CAP) {
1898 if (lpa & LPA_PAUSE_CAP)
1899 sky2->flow_status = FC_BOTH;
1900 else if (advert & ADVERTISE_PAUSE_ASYM)
1901 sky2->flow_status = FC_RX;
1902 } else if (advert & ADVERTISE_PAUSE_ASYM) {
1903 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
1904 sky2->flow_status = FC_TX;
1905 }
793b883e 1906
16ad91e1 1907 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
93745494 1908 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
16ad91e1 1909 sky2->flow_status = FC_NONE;
2eaba1a2 1910
da4c1ff4 1911 if (sky2->flow_status & FC_TX)
793b883e
SH		 1912 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1913 else
1914 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1915
1916 return 0;
1917}
cd28ab6a 1918
e07b1aa8
SH		 1919/* Interrupt from PHY */
1920static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 1921{
e07b1aa8
SH		 1922 struct net_device *dev = hw->dev[port];
1923 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 1924 u16 istatus, phystat;
1925
ebc646f6
SH		 1926 if (!netif_running(dev))
1927 return;
1928
e07b1aa8
SH		 1929 spin_lock(&sky2->phy_lock);
1930 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1931 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1932
cd28ab6a
SH		 1933 if (netif_msg_intr(sky2))
1934 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1935 sky2->netdev->name, istatus, phystat);
1936
2eaba1a2 1937 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
793b883e
SH		 1938 if (sky2_autoneg_done(sky2, phystat) == 0)
1939 sky2_link_up(sky2);
1940 goto out;
1941 }
cd28ab6a 1942
793b883e
SH		 1943 if (istatus & PHY_M_IS_LSP_CHANGE)
1944 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 1945
793b883e
SH		 1946 if (istatus & PHY_M_IS_DUP_CHANGE)
1947 sky2->duplex =
1948 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 1949
793b883e
SH		 1950 if (istatus & PHY_M_IS_LST_CHANGE) {
1951 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 1952 sky2_link_up(sky2);
793b883e
SH		 1953 else
1954 sky2_link_down(sky2);
cd28ab6a 1955 }
793b883e 1956out:
e07b1aa8 1957 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 1958}
1959
62335ab0 1960/* Transmit timeout is only called if we are running, carrier is up
302d1252
SH		 1961 * and tx queue is full (stopped).
1962 */
cd28ab6a
SH		 1963static void sky2_tx_timeout(struct net_device *dev)
1964{
1965 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3 1966 struct sky2_hw *hw = sky2->hw;
cd28ab6a
SH		 1967
1968 if (netif_msg_timer(sky2))
1969 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1970
8f24664d 1971 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
62335ab0
SH		 1972 dev->name, sky2->tx_cons, sky2->tx_prod,
1973 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
1974 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
8f24664d 1975
81906791
SH		 1976 /* can't restart safely under softirq */
1977 schedule_work(&hw->restart_work);
cd28ab6a
SH		 1978}
1979
1980static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1981{
6b1a3aef
SH		 1982 struct sky2_port *sky2 = netdev_priv(dev);
1983 struct sky2_hw *hw = sky2->hw;
b628ed98 1984 unsigned port = sky2->port;
6b1a3aef
SH		 1985 int err;
1986 u16 ctl, mode;
e07b1aa8 1987 u32 imask;
cd28ab6a
SH		 1988
1989 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1990 return -EINVAL;
1991
05745c4a
SH		 1992 if (new_mtu > ETH_DATA_LEN &&
1993 (hw->chip_id == CHIP_ID_YUKON_FE ||
1994 hw->chip_id == CHIP_ID_YUKON_FE_P))
d2adf4f6
SH		 1995 return -EINVAL;
1996
6b1a3aef
SH		 1997 if (!netif_running(dev)) {
1998 dev->mtu = new_mtu;
1999 return 0;
2000 }
2001
e07b1aa8 2002 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef
SH		 2003 sky2_write32(hw, B0_IMSK, 0);
2004
018d1c66
SH		 2005 dev->trans_start = jiffies; /* prevent tx timeout */
2006 netif_stop_queue(dev);
bea3348e 2007 napi_disable(&hw->napi);
018d1c66 2008
e07b1aa8
SH		 2009 synchronize_irq(hw->pdev->irq);
2010
e0c28116 2011 if (sky2_read8(hw, B2_E_0) == 0)
69161611 2012 sky2_set_tx_stfwd(hw, port);
b628ed98
SH		 2013
2014 ctl = gma_read16(hw, port, GM_GP_CTRL);
2015 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
6b1a3aef
SH		 2016 sky2_rx_stop(sky2);
2017 sky2_rx_clean(sky2);
cd28ab6a
SH		 2018
2019 dev->mtu = new_mtu;
14d0263f 2020
6b1a3aef
SH		 2021 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2022 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2023
2024 if (dev->mtu > ETH_DATA_LEN)
2025 mode |= GM_SMOD_JUMBO_ENA;
2026
b628ed98 2027 gma_write16(hw, port, GM_SERIAL_MODE, mode);
cd28ab6a 2028
b628ed98 2029 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 2030
6b1a3aef 2031 err = sky2_rx_start(sky2);
e07b1aa8 2032 sky2_write32(hw, B0_IMSK, imask);
018d1c66 2033
bea3348e
SH		 2034 napi_enable(&hw->napi);
2035
1b537565
SH		 2036 if (err)
2037 dev_close(dev);
2038 else {
b628ed98 2039 gma_write16(hw, port, GM_GP_CTRL, ctl);
1b537565 2040
1b537565
SH		 2041 netif_wake_queue(dev);
2042 }
2043
cd28ab6a
SH		 2044 return err;
2045}
2046
14d0263f
SH		 2047/* For small just reuse existing skb for next receive */
2048static struct sk_buff *receive_copy(struct sky2_port *sky2,
2049 const struct rx_ring_info *re,
2050 unsigned length)
2051{
2052 struct sk_buff *skb;
2053
2054 skb = netdev_alloc_skb(sky2->netdev, length + 2);
2055 if (likely(skb)) {
2056 skb_reserve(skb, 2);
2057 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2058 length, PCI_DMA_FROMDEVICE);
d626f62b 2059 skb_copy_from_linear_data(re->skb, skb->data, length);
14d0263f
SH		 2060 skb->ip_summed = re->skb->ip_summed;
2061 skb->csum = re->skb->csum;
2062 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2063 length, PCI_DMA_FROMDEVICE);
2064 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 2065 skb_put(skb, length);
14d0263f
SH		 2066 }
2067 return skb;
2068}
2069
2070/* Adjust length of skb with fragments to match received data */
2071static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2072 unsigned int length)
2073{
2074 int i, num_frags;
2075 unsigned int size;
2076
2077 /* put header into skb */
2078 size = min(length, hdr_space);
2079 skb->tail += size;
2080 skb->len += size;
2081 length -= size;
2082
2083 num_frags = skb_shinfo(skb)->nr_frags;
2084 for (i = 0; i < num_frags; i++) {
2085 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2086
2087 if (length == 0) {
2088 /* don't need this page */
2089 __free_page(frag->page);
2090 --skb_shinfo(skb)->nr_frags;
2091 } else {
2092 size = min(length, (unsigned) PAGE_SIZE);
2093
2094 frag->size = size;
2095 skb->data_len += size;
2096 skb->truesize += size;
2097 skb->len += size;
2098 length -= size;
2099 }
2100 }
2101}
2102
2103/* Normal packet - take skb from ring element and put in a new one */
2104static struct sk_buff *receive_new(struct sky2_port *sky2,
2105 struct rx_ring_info *re,
2106 unsigned int length)
2107{
2108 struct sk_buff *skb, *nskb;
2109 unsigned hdr_space = sky2->rx_data_size;
2110
14d0263f
SH		 2111 /* Don't be tricky about reusing pages (yet) */
2112 nskb = sky2_rx_alloc(sky2);
2113 if (unlikely(!nskb))
2114 return NULL;
2115
2116 skb = re->skb;
2117 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2118
2119 prefetch(skb->data);
2120 re->skb = nskb;
2121 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
2122
2123 if (skb_shinfo(skb)->nr_frags)
2124 skb_put_frags(skb, hdr_space, length);
2125 else
489b10c1 2126 skb_put(skb, length);
14d0263f
SH		 2127 return skb;
2128}
2129
cd28ab6a
SH		 2130/*
2131 * Receive one packet.
d571b694 2132 * For larger packets, get new buffer.
cd28ab6a 2133 */
497d7c86 2134static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 2135 u16 length, u32 status)
2136{
497d7c86 2137 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 2138 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 2139 struct sk_buff *skb = NULL;
d6532232
SH		 2140 u16 count = (status & GMR_FS_LEN) >> 16;
2141
2142#ifdef SKY2_VLAN_TAG_USED
2143 /* Account for vlan tag */
2144 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2145 count -= VLAN_HLEN;
2146#endif
cd28ab6a
SH		 2147
2148 if (unlikely(netif_msg_rx_status(sky2)))
2149 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
497d7c86 2150 dev->name, sky2->rx_next, status, length);
cd28ab6a 2151
793b883e 2152 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 2153 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 2154
3b12e014
SH		 2155 /* This chip has hardware problems that generates bogus status.
2156 * So do only marginal checking and expect higher level protocols
2157 * to handle crap frames.
2158 */
2159 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2160 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2161 length != count)
2162 goto okay;
2163
42eeea01 2164 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 2165 goto error;
2166
42eeea01
SH		 2167 if (!(status & GMR_FS_RX_OK))
2168 goto resubmit;
2169
d6532232
SH		 2170 /* if length reported by DMA does not match PHY, packet was truncated */
2171 if (length != count)
3b12e014 2172 goto len_error;
71749531 2173
3b12e014 2174okay:
14d0263f
SH		 2175 if (length < copybreak)
2176 skb = receive_copy(sky2, re, length);
2177 else
2178 skb = receive_new(sky2, re, length);
793b883e 2179resubmit:
14d0263f 2180 sky2_rx_submit(sky2, re);
79e57d32 2181
cd28ab6a
SH		 2182 return skb;
2183
3b12e014 2184len_error:
71749531
SH		 2185 /* Truncation of overlength packets
2186 causes PHY length to not match MAC length */
7138a0f5 2187 ++dev->stats.rx_length_errors;
d6532232 2188 if (netif_msg_rx_err(sky2) && net_ratelimit())
3b12e014
SH		 2189 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2190 dev->name, status, length);
d6532232 2191 goto resubmit;
71749531 2192
cd28ab6a 2193error:
7138a0f5 2194 ++dev->stats.rx_errors;
b6d77734 2195 if (status & GMR_FS_RX_FF_OV) {
7138a0f5 2196 dev->stats.rx_over_errors++;
b6d77734
SH		 2197 goto resubmit;
2198 }
6e15b712 2199
3be92a70 2200 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a 2201 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
497d7c86 2202 dev->name, status, length);
793b883e
SH		 2203
2204 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
7138a0f5 2205 dev->stats.rx_length_errors++;
cd28ab6a 2206 if (status & GMR_FS_FRAGMENT)
7138a0f5 2207 dev->stats.rx_frame_errors++;
cd28ab6a 2208 if (status & GMR_FS_CRC_ERR)
7138a0f5 2209 dev->stats.rx_crc_errors++;
79e57d32 2210
793b883e 2211 goto resubmit;
cd28ab6a
SH		 2212}
2213
e07b1aa8
SH		 2214/* Transmit complete */
2215static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2216{
e07b1aa8 2217 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2218
e07b1aa8 2219 if (netif_running(dev)) {
2bb8c262 2220 netif_tx_lock(dev);
e07b1aa8 2221 sky2_tx_complete(sky2, last);
2bb8c262 2222 netif_tx_unlock(dev);
2224795d 2223 }
cd28ab6a
SH		 2224}
2225
e07b1aa8 2226/* Process status response ring */
26691830 2227static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
cd28ab6a 2228{
e07b1aa8 2229 int work_done = 0;
55c9dd35 2230 unsigned rx[2] = { 0, 0 };
a8fd6266 2231
af2a58ac 2232 rmb();
26691830 2233 do {
55c9dd35 2234 struct sky2_port *sky2;
13210ce5 2235 struct sky2_status_le *le = hw->st_le + hw->st_idx;
ab5adecb 2236 unsigned port;
13210ce5 2237 struct net_device *dev;
cd28ab6a 2238 struct sk_buff *skb;
cd28ab6a
SH		 2239 u32 status;
2240 u16 length;
ab5adecb
SH		 2241 u8 opcode = le->opcode;
2242
2243 if (!(opcode & HW_OWNER))
2244 break;
cd28ab6a 2245
cb5d9547 2246 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 2247
ab5adecb 2248 port = le->css & CSS_LINK_BIT;
69161611 2249 dev = hw->dev[port];
13210ce5 2250 sky2 = netdev_priv(dev);
f65b138c
SH		 2251 length = le16_to_cpu(le->length);
2252 status = le32_to_cpu(le->status);
cd28ab6a 2253
ab5adecb
SH		 2254 le->opcode = 0;
2255 switch (opcode & ~HW_OWNER) {
cd28ab6a 2256 case OP_RXSTAT:
55c9dd35 2257 ++rx[port];
497d7c86 2258 skb = sky2_receive(dev, length, status);
3225b919 2259 if (unlikely(!skb)) {
7138a0f5 2260 dev->stats.rx_dropped++;
55c9dd35 2261 break;
3225b919 2262 }
13210ce5 2263
69161611 2264 /* This chip reports checksum status differently */
05745c4a 2265 if (hw->flags & SKY2_HW_NEW_LE) {
69161611
SH		 2266 if (sky2->rx_csum &&
2267 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2268 (le->css & CSS_TCPUDPCSOK))
2269 skb->ip_summed = CHECKSUM_UNNECESSARY;
2270 else
2271 skb->ip_summed = CHECKSUM_NONE;
2272 }
2273
13210ce5 2274 skb->protocol = eth_type_trans(skb, dev);
7138a0f5
SH		 2275 dev->stats.rx_packets++;
2276 dev->stats.rx_bytes += skb->len;
13210ce5
SH		 2277 dev->last_rx = jiffies;
2278
d1f13708
SH		 2279#ifdef SKY2_VLAN_TAG_USED
2280 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2281 vlan_hwaccel_receive_skb(skb,
2282 sky2->vlgrp,
2283 be16_to_cpu(sky2->rx_tag));
2284 } else
2285#endif
cd28ab6a 2286 netif_receive_skb(skb);
13210ce5 2287
22e11703 2288 /* Stop after net poll weight */
13210ce5
SH		 2289 if (++work_done >= to_do)
2290 goto exit_loop;
cd28ab6a
SH		 2291 break;
2292
d1f13708
SH		 2293#ifdef SKY2_VLAN_TAG_USED
2294 case OP_RXVLAN:
2295 sky2->rx_tag = length;
2296 break;
2297
2298 case OP_RXCHKSVLAN:
2299 sky2->rx_tag = length;
2300 /* fall through */
2301#endif
cd28ab6a 2302 case OP_RXCHKS:
87418307
SH		 2303 if (!sky2->rx_csum)
2304 break;
2305
05745c4a
SH		 2306 /* If this happens then driver assuming wrong format */
2307 if (unlikely(hw->flags & SKY2_HW_NEW_LE)) {
2308 if (net_ratelimit())
2309 printk(KERN_NOTICE "%s: unexpected"
2310 " checksum status\n",
2311 dev->name);
69161611 2312 break;
05745c4a 2313 }
69161611 2314
87418307
SH		 2315 /* Both checksum counters are programmed to start at
2316 * the same offset, so unless there is a problem they
2317 * should match. This failure is an early indication that
2318 * hardware receive checksumming won't work.
2319 */
2320 if (likely(status >> 16 == (status & 0xffff))) {
2321 skb = sky2->rx_ring[sky2->rx_next].skb;
2322 skb->ip_summed = CHECKSUM_COMPLETE;
2323 skb->csum = status & 0xffff;
2324 } else {
2325 printk(KERN_NOTICE PFX "%s: hardware receive "
2326 "checksum problem (status = %#x)\n",
2327 dev->name, status);
2328 sky2->rx_csum = 0;
2329 sky2_write32(sky2->hw,
69161611 2330 Q_ADDR(rxqaddr[port], Q_CSR),
87418307
SH		 2331 BMU_DIS_RX_CHKSUM);
2332 }
cd28ab6a
SH		 2333 break;
2334
2335 case OP_TXINDEXLE:
13b97b74 2336 /* TX index reports status for both ports */
f55925d7
SH		 2337 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2338 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2339 if (hw->dev[1])
2340 sky2_tx_done(hw->dev[1],
2341 ((status >> 24) & 0xff)
2342 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2343 break;
2344
cd28ab6a
SH		 2345 default:
2346 if (net_ratelimit())
793b883e 2347 printk(KERN_WARNING PFX
ab5adecb 2348 "unknown status opcode 0x%x\n", opcode);
cd28ab6a 2349 }
26691830 2350 } while (hw->st_idx != idx);
cd28ab6a 2351
fe2a24df
SH		 2352 /* Fully processed status ring so clear irq */
2353 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2354
13210ce5 2355exit_loop:
55c9dd35
SH		 2356 if (rx[0])
2357 sky2_rx_update(netdev_priv(hw->dev[0]), Q_R1);
22e11703 2358
55c9dd35
SH		 2359 if (rx[1])
2360 sky2_rx_update(netdev_priv(hw->dev[1]), Q_R2);
22e11703 2361
e07b1aa8 2362 return work_done;
cd28ab6a
SH		 2363}
2364
2365static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2366{
2367 struct net_device *dev = hw->dev[port];
2368
3be92a70
SH		 2369 if (net_ratelimit())
2370 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2371 dev->name, status);
cd28ab6a
SH		 2372
2373 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2374 if (net_ratelimit())
2375 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2376 dev->name);
cd28ab6a
SH		 2377 /* Clear IRQ */
2378 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2379 }
2380
2381 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2382 if (net_ratelimit())
2383 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2384 dev->name);
cd28ab6a
SH		 2385
2386 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2387 }
2388
2389 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2390 if (net_ratelimit())
2391 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2392 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2393 }
2394
2395 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2396 if (net_ratelimit())
2397 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2398 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2399 }
2400
2401 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2402 if (net_ratelimit())
2403 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2404 dev->name);
cd28ab6a
SH		 2405 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2406 }
2407}
2408
2409static void sky2_hw_intr(struct sky2_hw *hw)
2410{
555382cb 2411 struct pci_dev *pdev = hw->pdev;
cd28ab6a 2412 u32 status = sky2_read32(hw, B0_HWE_ISRC);
555382cb
SH		 2413 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2414
2415 status &= hwmsk;
cd28ab6a 2416
793b883e 2417 if (status & Y2_IS_TIST_OV)
cd28ab6a 2418 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2419
2420 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2421 u16 pci_err;
2422
b32f40c4 2423 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70 2424 if (net_ratelimit())
555382cb 2425 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
b02a9258 2426 pci_err);
cd28ab6a 2427
b32f40c4 2428 sky2_pci_write16(hw, PCI_STATUS,
167f53d0 2429 pci_err | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 2430 }
2431
2432 if (status & Y2_IS_PCI_EXP) {
d571b694 2433 /* PCI-Express uncorrectable Error occurred */
555382cb 2434 u32 err;
cd28ab6a 2435
7782c8c4
SH		 2436 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2437 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2438 0xfffffffful);
3be92a70 2439 if (net_ratelimit())
555382cb 2440 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
cf06ffb4 2441
7782c8c4 2442 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
cd28ab6a
SH		 2443 }
2444
2445 if (status & Y2_HWE_L1_MASK)
2446 sky2_hw_error(hw, 0, status);
2447 status >>= 8;
2448 if (status & Y2_HWE_L1_MASK)
2449 sky2_hw_error(hw, 1, status);
2450}
2451
2452static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2453{
2454 struct net_device *dev = hw->dev[port];
2455 struct sky2_port *sky2 = netdev_priv(dev);
2456 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2457
2458 if (netif_msg_intr(sky2))
2459 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2460 dev->name, status);
2461
a3caeada
SH		 2462 if (status & GM_IS_RX_CO_OV)
2463 gma_read16(hw, port, GM_RX_IRQ_SRC);
2464
2465 if (status & GM_IS_TX_CO_OV)
2466 gma_read16(hw, port, GM_TX_IRQ_SRC);
2467
cd28ab6a 2468 if (status & GM_IS_RX_FF_OR) {
7138a0f5 2469 ++dev->stats.rx_fifo_errors;
cd28ab6a
SH		 2470 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2471 }
2472
2473 if (status & GM_IS_TX_FF_UR) {
7138a0f5 2474 ++dev->stats.tx_fifo_errors;
cd28ab6a
SH		 2475 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2476 }
cd28ab6a
SH		 2477}
2478
40b01727
SH		 2479/* This should never happen it is a bug. */
2480static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2481 u16 q, unsigned ring_size)
d257924e
SH		 2482{
2483 struct net_device *dev = hw->dev[port];
2484 struct sky2_port *sky2 = netdev_priv(dev);
40b01727
SH		 2485 unsigned idx;
2486 const u64 *le = (q == Q_R1 || q == Q_R2)
2487 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
d257924e 2488
40b01727
SH		 2489 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2490 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2491 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2492 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
d257924e 2493
40b01727 2494 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
d257924e 2495}
cd28ab6a 2496
75e80683
SH		 2497static int sky2_rx_hung(struct net_device *dev)
2498{
2499 struct sky2_port *sky2 = netdev_priv(dev);
2500 struct sky2_hw *hw = sky2->hw;
2501 unsigned port = sky2->port;
2502 unsigned rxq = rxqaddr[port];
2503 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2504 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2505 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2506 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2507
2508 /* If idle and MAC or PCI is stuck */
2509 if (sky2->check.last == dev->last_rx &&
2510 ((mac_rp == sky2->check.mac_rp &&
2511 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2512 /* Check if the PCI RX hang */
2513 (fifo_rp == sky2->check.fifo_rp &&
2514 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2515 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2516 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2517 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2518 return 1;
2519 } else {
2520 sky2->check.last = dev->last_rx;
2521 sky2->check.mac_rp = mac_rp;
2522 sky2->check.mac_lev = mac_lev;
2523 sky2->check.fifo_rp = fifo_rp;
2524 sky2->check.fifo_lev = fifo_lev;
2525 return 0;
2526 }
2527}
2528
32c2c300 2529static void sky2_watchdog(unsigned long arg)
d27ed387 2530{
01bd7564 2531 struct sky2_hw *hw = (struct sky2_hw *) arg;
d27ed387 2532
75e80683 2533 /* Check for lost IRQ once a second */
32c2c300 2534 if (sky2_read32(hw, B0_ISRC)) {
bea3348e 2535 napi_schedule(&hw->napi);
75e80683
SH		 2536 } else {
2537 int i, active = 0;
2538
2539 for (i = 0; i < hw->ports; i++) {
bea3348e 2540 struct net_device *dev = hw->dev[i];
75e80683
SH		 2541 if (!netif_running(dev))
2542 continue;
2543 ++active;
2544
2545 /* For chips with Rx FIFO, check if stuck */
e0c28116 2546 if ((hw->flags & SKY2_HW_FIFO_HANG_CHECK) &&
75e80683
SH		 2547 sky2_rx_hung(dev)) {
2548 pr_info(PFX "%s: receiver hang detected\n",
2549 dev->name);
2550 schedule_work(&hw->restart_work);
2551 return;
2552 }
2553 }
2554
2555 if (active == 0)
2556 return;
32c2c300 2557 }
01bd7564 2558
75e80683 2559 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
d27ed387
SH		 2560}
2561
40b01727
SH		 2562/* Hardware/software error handling */
2563static void sky2_err_intr(struct sky2_hw *hw, u32 status)
cd28ab6a 2564{
40b01727
SH		 2565 if (net_ratelimit())
2566 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
cd28ab6a 2567
1e5f1283
SH		 2568 if (status & Y2_IS_HW_ERR)
2569 sky2_hw_intr(hw);
d257924e 2570
1e5f1283
SH		 2571 if (status & Y2_IS_IRQ_MAC1)
2572 sky2_mac_intr(hw, 0);
cd28ab6a 2573
1e5f1283
SH		 2574 if (status & Y2_IS_IRQ_MAC2)
2575 sky2_mac_intr(hw, 1);
cd28ab6a 2576
1e5f1283 2577 if (status & Y2_IS_CHK_RX1)
40b01727 2578 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
d257924e 2579
1e5f1283 2580 if (status & Y2_IS_CHK_RX2)
40b01727 2581 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
d257924e 2582
1e5f1283 2583 if (status & Y2_IS_CHK_TXA1)
40b01727 2584 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
d257924e 2585
1e5f1283 2586 if (status & Y2_IS_CHK_TXA2)
40b01727
SH		 2587 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2588}
2589
bea3348e 2590static int sky2_poll(struct napi_struct *napi, int work_limit)
40b01727 2591{
bea3348e 2592 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
40b01727 2593 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
6f535763 2594 int work_done = 0;
26691830 2595 u16 idx;
40b01727
SH		 2596
2597 if (unlikely(status & Y2_IS_ERROR))
2598 sky2_err_intr(hw, status);
2599
2600 if (status & Y2_IS_IRQ_PHY1)
2601 sky2_phy_intr(hw, 0);
2602
2603 if (status & Y2_IS_IRQ_PHY2)
2604 sky2_phy_intr(hw, 1);
cd28ab6a 2605
26691830
SH		 2606 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2607 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
6f535763
DM		 2608
2609 if (work_done >= work_limit)
26691830
SH		 2610 goto done;
2611 }
6f535763 2612
26691830
SH		 2613 /* Bug/Errata workaround?
2614 * Need to kick the TX irq moderation timer.
2615 */
2616 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_START) {
2617 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2618 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
fe2a24df 2619 }
26691830
SH		 2620 napi_complete(napi);
2621 sky2_read32(hw, B0_Y2_SP_LISR);
2622done:
6f535763 2623
bea3348e 2624 return work_done;
e07b1aa8
SH		 2625}
2626
7d12e780 2627static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2628{
2629 struct sky2_hw *hw = dev_id;
e07b1aa8
SH		 2630 u32 status;
2631
2632 /* Reading this mask interrupts as side effect */
2633 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2634 if (status == 0 || status == ~0)
2635 return IRQ_NONE;
793b883e 2636
e07b1aa8 2637 prefetch(&hw->st_le[hw->st_idx]);
bea3348e
SH		 2638
2639 napi_schedule(&hw->napi);
793b883e 2640
cd28ab6a
SH		 2641 return IRQ_HANDLED;
2642}
2643
2644#ifdef CONFIG_NET_POLL_CONTROLLER
2645static void sky2_netpoll(struct net_device *dev)
2646{
2647 struct sky2_port *sky2 = netdev_priv(dev);
2648
bea3348e 2649 napi_schedule(&sky2->hw->napi);
cd28ab6a
SH		 2650}
2651#endif
2652
2653/* Chip internal frequency for clock calculations */
05745c4a 2654static u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2655{
793b883e 2656 switch (hw->chip_id) {
cd28ab6a 2657 case CHIP_ID_YUKON_EC:
5a5b1ea0 2658 case CHIP_ID_YUKON_EC_U:
93745494 2659 case CHIP_ID_YUKON_EX:
05745c4a
SH		 2660 return 125;
2661
cd28ab6a 2662 case CHIP_ID_YUKON_FE:
05745c4a
SH		 2663 return 100;
2664
2665 case CHIP_ID_YUKON_FE_P:
2666 return 50;
2667
2668 case CHIP_ID_YUKON_XL:
2669 return 156;
2670
2671 default:
2672 BUG();
cd28ab6a
SH		 2673 }
2674}
2675
fb17358f 2676static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2677{
fb17358f 2678 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2679}
2680
fb17358f 2681static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2682{
fb17358f 2683 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2684}
2685
fb17358f 2686
e3173832 2687static int __devinit sky2_init(struct sky2_hw *hw)
cd28ab6a 2688{
b89165f2 2689 u8 t8;
cd28ab6a 2690
167f53d0 2691 /* Enable all clocks and check for bad PCI access */
b32f40c4 2692 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
451af335 2693
cd28ab6a 2694 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2695
cd28ab6a 2696 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
ea76e635
SH		 2697 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2698
2699 switch(hw->chip_id) {
2700 case CHIP_ID_YUKON_XL:
2701 hw->flags = SKY2_HW_GIGABIT
e0c28116
SH		 2702 | SKY2_HW_NEWER_PHY;
2703 if (hw->chip_rev < 3)
2704 hw->flags |= SKY2_HW_FIFO_HANG_CHECK;
2705
ea76e635
SH		 2706 break;
2707
2708 case CHIP_ID_YUKON_EC_U:
2709 hw->flags = SKY2_HW_GIGABIT
2710 | SKY2_HW_NEWER_PHY
2711 | SKY2_HW_ADV_POWER_CTL;
2712 break;
2713
2714 case CHIP_ID_YUKON_EX:
2715 hw->flags = SKY2_HW_GIGABIT
2716 | SKY2_HW_NEWER_PHY
2717 | SKY2_HW_NEW_LE
2718 | SKY2_HW_ADV_POWER_CTL;
2719
2720 /* New transmit checksum */
2721 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2722 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2723 break;
2724
2725 case CHIP_ID_YUKON_EC:
2726 /* This rev is really old, and requires untested workarounds */
2727 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2728 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2729 return -EOPNOTSUPP;
2730 }
e0c28116 2731 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_FIFO_HANG_CHECK;
ea76e635
SH		 2732 break;
2733
2734 case CHIP_ID_YUKON_FE:
ea76e635
SH		 2735 break;
2736
05745c4a
SH		 2737 case CHIP_ID_YUKON_FE_P:
2738 hw->flags = SKY2_HW_NEWER_PHY
2739 | SKY2_HW_NEW_LE
2740 | SKY2_HW_AUTO_TX_SUM
2741 | SKY2_HW_ADV_POWER_CTL;
2742 break;
ea76e635 2743 default:
b02a9258
SH		 2744 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2745 hw->chip_id);
cd28ab6a
SH		 2746 return -EOPNOTSUPP;
2747 }
2748
ea76e635
SH		 2749 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2750 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
2751 hw->flags |= SKY2_HW_FIBRE_PHY;
290d4de5 2752
290d4de5 2753
e3173832
SH		 2754 hw->ports = 1;
2755 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2756 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2757 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2758 ++hw->ports;
2759 }
2760
2761 return 0;
2762}
2763
2764static void sky2_reset(struct sky2_hw *hw)
2765{
555382cb 2766 struct pci_dev *pdev = hw->pdev;
e3173832 2767 u16 status;
555382cb
SH		 2768 int i, cap;
2769 u32 hwe_mask = Y2_HWE_ALL_MASK;
e3173832 2770
cd28ab6a 2771 /* disable ASF */
4f44d8ba
SH		 2772 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2773 status = sky2_read16(hw, HCU_CCSR);
2774 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2775 HCU_CCSR_UC_STATE_MSK);
2776 sky2_write16(hw, HCU_CCSR, status);
2777 } else
2778 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2779 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
cd28ab6a
SH		 2780
2781 /* do a SW reset */
2782 sky2_write8(hw, B0_CTST, CS_RST_SET);
2783 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2784
ac93a394
SH		 2785 /* allow writes to PCI config */
2786 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2787
cd28ab6a 2788 /* clear PCI errors, if any */
b32f40c4 2789 status = sky2_pci_read16(hw, PCI_STATUS);
167f53d0 2790 status |= PCI_STATUS_ERROR_BITS;
b32f40c4 2791 sky2_pci_write16(hw, PCI_STATUS, status);
cd28ab6a
SH		 2792
2793 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2794
555382cb
SH		 2795 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2796 if (cap) {
7782c8c4
SH		 2797 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2798 0xfffffffful);
555382cb
SH		 2799
2800 /* If error bit is stuck on ignore it */
2801 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
2802 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
7782c8c4 2803 else
555382cb
SH		 2804 hwe_mask |= Y2_IS_PCI_EXP;
2805 }
cd28ab6a 2806
ae306cca 2807 sky2_power_on(hw);
cd28ab6a
SH		 2808
2809 for (i = 0; i < hw->ports; i++) {
2810 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2811 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
69161611
SH		 2812
2813 if (hw->chip_id == CHIP_ID_YUKON_EX)
2814 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
2815 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
2816 | GMC_BYP_RETR_ON);
cd28ab6a
SH		 2817 }
2818
793b883e
SH		 2819 /* Clear I2C IRQ noise */
2820 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2821
2822 /* turn off hardware timer (unused) */
2823 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2824 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2825
cd28ab6a
SH		 2826 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2827
69634ee7
SH		 2828 /* Turn off descriptor polling */
2829 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2830
2831 /* Turn off receive timestamp */
2832 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2833 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2834
2835 /* enable the Tx Arbiters */
2836 for (i = 0; i < hw->ports; i++)
2837 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2838
2839 /* Initialize ram interface */
2840 for (i = 0; i < hw->ports; i++) {
793b883e 2841 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2842
2843 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2844 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2845 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2846 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2847 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2848 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2849 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2850 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2851 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2852 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2853 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2854 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2855 }
2856
555382cb 2857 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
cd28ab6a 2858
cd28ab6a 2859 for (i = 0; i < hw->ports; i++)
d3bcfbeb 2860 sky2_gmac_reset(hw, i);
cd28ab6a 2861
cd28ab6a
SH		 2862 memset(hw->st_le, 0, STATUS_LE_BYTES);
2863 hw->st_idx = 0;
2864
2865 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2866 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2867
2868 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 2869 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 2870
2871 /* Set the list last index */
793b883e 2872 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 2873
290d4de5
SH		 2874 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2875 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 2876
290d4de5
SH		 2877 /* set Status-FIFO ISR watermark */
2878 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2879 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2880 else
2881 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 2882
290d4de5 2883 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 2884 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2885 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 2886
793b883e 2887 /* enable status unit */
cd28ab6a
SH		 2888 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2889
2890 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2891 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2892 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
e3173832
SH		 2893}
2894
81906791
SH		 2895static void sky2_restart(struct work_struct *work)
2896{
2897 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
2898 struct net_device *dev;
2899 int i, err;
2900
81906791
SH		 2901 rtnl_lock();
2902 sky2_write32(hw, B0_IMSK, 0);
2903 sky2_read32(hw, B0_IMSK);
6de16237 2904 napi_disable(&hw->napi);
81906791 2905
81906791
SH		 2906 for (i = 0; i < hw->ports; i++) {
2907 dev = hw->dev[i];
2908 if (netif_running(dev))
2909 sky2_down(dev);
2910 }
2911
2912 sky2_reset(hw);
2913 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 2914 napi_enable(&hw->napi);
81906791
SH		 2915
2916 for (i = 0; i < hw->ports; i++) {
2917 dev = hw->dev[i];
2918 if (netif_running(dev)) {
2919 err = sky2_up(dev);
2920 if (err) {
2921 printk(KERN_INFO PFX "%s: could not restart %d\n",
2922 dev->name, err);
2923 dev_close(dev);
2924 }
2925 }
2926 }
2927
81906791
SH		 2928 rtnl_unlock();
2929}
2930
e3173832
SH		 2931static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
2932{
2933 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
2934}
2935
2936static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2937{
2938 const struct sky2_port *sky2 = netdev_priv(dev);
2939
2940 wol->supported = sky2_wol_supported(sky2->hw);
2941 wol->wolopts = sky2->wol;
2942}
2943
2944static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2945{
2946 struct sky2_port *sky2 = netdev_priv(dev);
2947 struct sky2_hw *hw = sky2->hw;
cd28ab6a 2948
e3173832
SH		 2949 if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
2950 return -EOPNOTSUPP;
2951
2952 sky2->wol = wol->wolopts;
2953
05745c4a
SH		 2954 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
2955 hw->chip_id == CHIP_ID_YUKON_EX ||
2956 hw->chip_id == CHIP_ID_YUKON_FE_P)
e3173832
SH		 2957 sky2_write32(hw, B0_CTST, sky2->wol
2958 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
2959
2960 if (!netif_running(dev))
2961 sky2_wol_init(sky2);
cd28ab6a
SH		 2962 return 0;
2963}
2964
28bd181a 2965static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 2966{
b89165f2
SH		 2967 if (sky2_is_copper(hw)) {
2968 u32 modes = SUPPORTED_10baseT_Half
2969 | SUPPORTED_10baseT_Full
2970 | SUPPORTED_100baseT_Half
2971 | SUPPORTED_100baseT_Full
2972 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 2973
ea76e635 2974 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a 2975 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 2976 | SUPPORTED_1000baseT_Full;
2977 return modes;
cd28ab6a 2978 } else
b89165f2
SH		 2979 return SUPPORTED_1000baseT_Half
2980 | SUPPORTED_1000baseT_Full
2981 | SUPPORTED_Autoneg
2982 | SUPPORTED_FIBRE;
cd28ab6a
SH		 2983}
2984
793b883e 2985static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 2986{
2987 struct sky2_port *sky2 = netdev_priv(dev);
2988 struct sky2_hw *hw = sky2->hw;
2989
2990 ecmd->transceiver = XCVR_INTERNAL;
2991 ecmd->supported = sky2_supported_modes(hw);
2992 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 2993 if (sky2_is_copper(hw)) {
cd28ab6a 2994 ecmd->port = PORT_TP;
b89165f2
SH		 2995 ecmd->speed = sky2->speed;
2996 } else {
2997 ecmd->speed = SPEED_1000;
cd28ab6a 2998 ecmd->port = PORT_FIBRE;
b89165f2 2999 }
cd28ab6a
SH		 3000
3001 ecmd->advertising = sky2->advertising;
3002 ecmd->autoneg = sky2->autoneg;
cd28ab6a
SH		 3003 ecmd->duplex = sky2->duplex;
3004 return 0;
3005}
3006
3007static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3008{
3009 struct sky2_port *sky2 = netdev_priv(dev);
3010 const struct sky2_hw *hw = sky2->hw;
3011 u32 supported = sky2_supported_modes(hw);
3012
3013 if (ecmd->autoneg == AUTONEG_ENABLE) {
3014 ecmd->advertising = supported;
3015 sky2->duplex = -1;
3016 sky2->speed = -1;
3017 } else {
3018 u32 setting;
3019
793b883e 3020 switch (ecmd->speed) {
cd28ab6a
SH		 3021 case SPEED_1000:
3022 if (ecmd->duplex == DUPLEX_FULL)
3023 setting = SUPPORTED_1000baseT_Full;
3024 else if (ecmd->duplex == DUPLEX_HALF)
3025 setting = SUPPORTED_1000baseT_Half;
3026 else
3027 return -EINVAL;
3028 break;
3029 case SPEED_100:
3030 if (ecmd->duplex == DUPLEX_FULL)
3031 setting = SUPPORTED_100baseT_Full;
3032 else if (ecmd->duplex == DUPLEX_HALF)
3033 setting = SUPPORTED_100baseT_Half;
3034 else
3035 return -EINVAL;
3036 break;
3037
3038 case SPEED_10:
3039 if (ecmd->duplex == DUPLEX_FULL)
3040 setting = SUPPORTED_10baseT_Full;
3041 else if (ecmd->duplex == DUPLEX_HALF)
3042 setting = SUPPORTED_10baseT_Half;
3043 else
3044 return -EINVAL;
3045 break;
3046 default:
3047 return -EINVAL;
3048 }
3049
3050 if ((setting & supported) == 0)
3051 return -EINVAL;
3052
3053 sky2->speed = ecmd->speed;
3054 sky2->duplex = ecmd->duplex;
3055 }
3056
3057 sky2->autoneg = ecmd->autoneg;
3058 sky2->advertising = ecmd->advertising;
3059
d1b139c0 3060 if (netif_running(dev)) {
1b537565 3061 sky2_phy_reinit(sky2);
d1b139c0
SH		 3062 sky2_set_multicast(dev);
3063 }
cd28ab6a
SH		 3064
3065 return 0;
3066}
3067
3068static void sky2_get_drvinfo(struct net_device *dev,
3069 struct ethtool_drvinfo *info)
3070{
3071 struct sky2_port *sky2 = netdev_priv(dev);
3072
3073 strcpy(info->driver, DRV_NAME);
3074 strcpy(info->version, DRV_VERSION);
3075 strcpy(info->fw_version, "N/A");
3076 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3077}
3078
3079static const struct sky2_stat {
793b883e
SH		 3080 char name[ETH_GSTRING_LEN];
3081 u16 offset;
cd28ab6a
SH		 3082} sky2_stats[] = {
3083 { "tx_bytes", GM_TXO_OK_HI },
3084 { "rx_bytes", GM_RXO_OK_HI },
3085 { "tx_broadcast", GM_TXF_BC_OK },
3086 { "rx_broadcast", GM_RXF_BC_OK },
3087 { "tx_multicast", GM_TXF_MC_OK },
3088 { "rx_multicast", GM_RXF_MC_OK },
3089 { "tx_unicast", GM_TXF_UC_OK },
3090 { "rx_unicast", GM_RXF_UC_OK },
3091 { "tx_mac_pause", GM_TXF_MPAUSE },
3092 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 3093 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 3094 { "late_collision",GM_TXF_LAT_COL },
3095 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 3096 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 3097 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 3098
d2604540 3099 { "rx_short", GM_RXF_SHT },
cd28ab6a 3100 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 3101 { "rx_64_byte_packets", GM_RXF_64B },
3102 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3103 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3104 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3105 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3106 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3107 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 3108 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 3109 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3110 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 3111 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 3112
3113 { "tx_64_byte_packets", GM_TXF_64B },
3114 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3115 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3116 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3117 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3118 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3119 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3120 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 3121};
3122
cd28ab6a
SH		 3123static u32 sky2_get_rx_csum(struct net_device *dev)
3124{
3125 struct sky2_port *sky2 = netdev_priv(dev);
3126
3127 return sky2->rx_csum;
3128}
3129
3130static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3131{
3132 struct sky2_port *sky2 = netdev_priv(dev);
3133
3134 sky2->rx_csum = data;
793b883e 3135
cd28ab6a
SH		 3136 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3137 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3138
3139 return 0;
3140}
3141
3142static u32 sky2_get_msglevel(struct net_device *netdev)
3143{
3144 struct sky2_port *sky2 = netdev_priv(netdev);
3145 return sky2->msg_enable;
3146}
3147
9a7ae0a9
SH		 3148static int sky2_nway_reset(struct net_device *dev)
3149{
3150 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 3151
16ad91e1 3152 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
9a7ae0a9
SH		 3153 return -EINVAL;
3154
1b537565 3155 sky2_phy_reinit(sky2);
d1b139c0 3156 sky2_set_multicast(dev);
9a7ae0a9
SH		 3157
3158 return 0;
3159}
3160
793b883e 3161static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 3162{
3163 struct sky2_hw *hw = sky2->hw;
3164 unsigned port = sky2->port;
3165 int i;
3166
3167 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 3168 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 3169 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 3170 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 3171
793b883e 3172 for (i = 2; i < count; i++)
cd28ab6a
SH		 3173 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3174}
3175
cd28ab6a
SH		 3176static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3177{
3178 struct sky2_port *sky2 = netdev_priv(netdev);
3179 sky2->msg_enable = value;
3180}
3181
b9f2c044 3182static int sky2_get_sset_count(struct net_device *dev, int sset)
cd28ab6a 3183{
b9f2c044
JG		 3184 switch (sset) {
3185 case ETH_SS_STATS:
3186 return ARRAY_SIZE(sky2_stats);
3187 default:
3188 return -EOPNOTSUPP;
3189 }
cd28ab6a
SH		 3190}
3191
3192static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 3193 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 3194{
3195 struct sky2_port *sky2 = netdev_priv(dev);
3196
793b883e 3197 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 3198}
3199
793b883e 3200static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 3201{
3202 int i;
3203
3204 switch (stringset) {
3205 case ETH_SS_STATS:
3206 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3207 memcpy(data + i * ETH_GSTRING_LEN,
3208 sky2_stats[i].name, ETH_GSTRING_LEN);
3209 break;
3210 }
3211}
3212
cd28ab6a
SH		 3213static int sky2_set_mac_address(struct net_device *dev, void *p)
3214{
3215 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 3216 struct sky2_hw *hw = sky2->hw;
3217 unsigned port = sky2->port;
3218 const struct sockaddr *addr = p;
cd28ab6a
SH		 3219
3220 if (!is_valid_ether_addr(addr->sa_data))
3221 return -EADDRNOTAVAIL;
3222
cd28ab6a 3223 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 3224 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 3225 dev->dev_addr, ETH_ALEN);
a8ab1ec0 3226 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 3227 dev->dev_addr, ETH_ALEN);
1b537565 3228
a8ab1ec0
SH		 3229 /* virtual address for data */
3230 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3231
3232 /* physical address: used for pause frames */
3233 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 3234
3235 return 0;
cd28ab6a
SH		 3236}
3237
a052b52f
SH		 3238static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3239{
3240 u32 bit;
3241
3242 bit = ether_crc(ETH_ALEN, addr) & 63;
3243 filter[bit >> 3] |= 1 << (bit & 7);
3244}
3245
cd28ab6a
SH		 3246static void sky2_set_multicast(struct net_device *dev)
3247{
3248 struct sky2_port *sky2 = netdev_priv(dev);
3249 struct sky2_hw *hw = sky2->hw;
3250 unsigned port = sky2->port;
3251 struct dev_mc_list *list = dev->mc_list;
3252 u16 reg;
3253 u8 filter[8];
a052b52f
SH		 3254 int rx_pause;
3255 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 3256
a052b52f 3257 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 3258 memset(filter, 0, sizeof(filter));
3259
3260 reg = gma_read16(hw, port, GM_RX_CTRL);
3261 reg |= GM_RXCR_UCF_ENA;
3262
d571b694 3263 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 3264 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 3265 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 3266 memset(filter, 0xff, sizeof(filter));
a052b52f 3267 else if (dev->mc_count == 0 && !rx_pause)
cd28ab6a
SH		 3268 reg &= ~GM_RXCR_MCF_ENA;
3269 else {
3270 int i;
3271 reg |= GM_RXCR_MCF_ENA;
3272
a052b52f
SH		 3273 if (rx_pause)
3274 sky2_add_filter(filter, pause_mc_addr);
3275
3276 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3277 sky2_add_filter(filter, list->dmi_addr);
cd28ab6a
SH		 3278 }
3279
cd28ab6a 3280 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 3281 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 3282 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 3283 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 3284 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 3285 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 3286 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 3287 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 3288
3289 gma_write16(hw, port, GM_RX_CTRL, reg);
3290}
3291
3292/* Can have one global because blinking is controlled by
3293 * ethtool and that is always under RTNL mutex
3294 */
91c86df5 3295static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
cd28ab6a 3296{
793b883e
SH		 3297 u16 pg;
3298
793b883e
SH		 3299 switch (hw->chip_id) {
3300 case CHIP_ID_YUKON_XL:
3301 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3302 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3303 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3304 on ? (PHY_M_LEDC_LOS_CTRL(1) |
3305 PHY_M_LEDC_INIT_CTRL(7) |
3306 PHY_M_LEDC_STA1_CTRL(7) |
3307 PHY_M_LEDC_STA0_CTRL(7))
3308 : 0);
3309
3310 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3311 break;
3312
3313 default:
3314 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
0efdf262
SH		 3315 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3316 on ? PHY_M_LED_ALL : 0);
793b883e 3317 }
cd28ab6a
SH		 3318}
3319
3320/* blink LED's for finding board */
3321static int sky2_phys_id(struct net_device *dev, u32 data)
3322{
3323 struct sky2_port *sky2 = netdev_priv(dev);
3324 struct sky2_hw *hw = sky2->hw;
3325 unsigned port = sky2->port;
793b883e 3326 u16 ledctrl, ledover = 0;
cd28ab6a 3327 long ms;
91c86df5 3328 int interrupted;
cd28ab6a
SH		 3329 int onoff = 1;
3330
793b883e 3331 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
cd28ab6a
SH		 3332 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
3333 else
3334 ms = data * 1000;
3335
3336 /* save initial values */
e07b1aa8 3337 spin_lock_bh(&sky2->phy_lock);
793b883e
SH		 3338 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3339 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3340 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3341 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
3342 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3343 } else {
3344 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
3345 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
3346 }
cd28ab6a 3347
91c86df5
SH		 3348 interrupted = 0;
3349 while (!interrupted && ms > 0) {
cd28ab6a
SH		 3350 sky2_led(hw, port, onoff);
3351 onoff = !onoff;
3352
e07b1aa8 3353 spin_unlock_bh(&sky2->phy_lock);
91c86df5 3354 interrupted = msleep_interruptible(250);
e07b1aa8 3355 spin_lock_bh(&sky2->phy_lock);
91c86df5 3356
cd28ab6a
SH		 3357 ms -= 250;
3358 }
3359
3360 /* resume regularly scheduled programming */
793b883e
SH		 3361 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3362 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3363 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3364 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
3365 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3366 } else {
3367 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
3368 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
3369 }
e07b1aa8 3370 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 3371
3372 return 0;
3373}
3374
3375static void sky2_get_pauseparam(struct net_device *dev,
3376 struct ethtool_pauseparam *ecmd)
3377{
3378 struct sky2_port *sky2 = netdev_priv(dev);
3379
16ad91e1
SH		 3380 switch (sky2->flow_mode) {
3381 case FC_NONE:
3382 ecmd->tx_pause = ecmd->rx_pause = 0;
3383 break;
3384 case FC_TX:
3385 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3386 break;
3387 case FC_RX:
3388 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3389 break;
3390 case FC_BOTH:
3391 ecmd->tx_pause = ecmd->rx_pause = 1;
3392 }
3393
cd28ab6a
SH		 3394 ecmd->autoneg = sky2->autoneg;
3395}
3396
3397static int sky2_set_pauseparam(struct net_device *dev,
3398 struct ethtool_pauseparam *ecmd)
3399{
3400 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 3401
3402 sky2->autoneg = ecmd->autoneg;
16ad91e1 3403 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3404
16ad91e1
SH		 3405 if (netif_running(dev))
3406 sky2_phy_reinit(sky2);
cd28ab6a 3407
2eaba1a2 3408 return 0;
cd28ab6a
SH		 3409}
3410
fb17358f
SH		 3411static int sky2_get_coalesce(struct net_device *dev,
3412 struct ethtool_coalesce *ecmd)
3413{
3414 struct sky2_port *sky2 = netdev_priv(dev);
3415 struct sky2_hw *hw = sky2->hw;
3416
3417 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3418 ecmd->tx_coalesce_usecs = 0;
3419 else {
3420 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3421 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3422 }
3423 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3424
3425 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3426 ecmd->rx_coalesce_usecs = 0;
3427 else {
3428 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3429 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3430 }
3431 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3432
3433 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3434 ecmd->rx_coalesce_usecs_irq = 0;
3435 else {
3436 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3437 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3438 }
3439
3440 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3441
3442 return 0;
3443}
3444
3445/* Note: this affect both ports */
3446static int sky2_set_coalesce(struct net_device *dev,
3447 struct ethtool_coalesce *ecmd)
3448{
3449 struct sky2_port *sky2 = netdev_priv(dev);
3450 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3451 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3452
77b3d6a2
SH		 3453 if (ecmd->tx_coalesce_usecs > tmax ||
3454 ecmd->rx_coalesce_usecs > tmax ||
3455 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3456 return -EINVAL;
3457
ff81fbbe 3458 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
fb17358f 3459 return -EINVAL;
ff81fbbe 3460 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3461 return -EINVAL;
ff81fbbe 3462 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 3463 return -EINVAL;
3464
3465 if (ecmd->tx_coalesce_usecs == 0)
3466 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3467 else {
3468 sky2_write32(hw, STAT_TX_TIMER_INI,
3469 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3470 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3471 }
3472 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3473
3474 if (ecmd->rx_coalesce_usecs == 0)
3475 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3476 else {
3477 sky2_write32(hw, STAT_LEV_TIMER_INI,
3478 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3479 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3480 }
3481 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3482
3483 if (ecmd->rx_coalesce_usecs_irq == 0)
3484 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3485 else {
d28d4870 3486 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3487 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3488 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3489 }
3490 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3491 return 0;
3492}
3493
793b883e
SH		 3494static void sky2_get_ringparam(struct net_device *dev,
3495 struct ethtool_ringparam *ering)
3496{
3497 struct sky2_port *sky2 = netdev_priv(dev);
3498
3499 ering->rx_max_pending = RX_MAX_PENDING;
3500 ering->rx_mini_max_pending = 0;
3501 ering->rx_jumbo_max_pending = 0;
3502 ering->tx_max_pending = TX_RING_SIZE - 1;
3503
3504 ering->rx_pending = sky2->rx_pending;
3505 ering->rx_mini_pending = 0;
3506 ering->rx_jumbo_pending = 0;
3507 ering->tx_pending = sky2->tx_pending;
3508}
3509
3510static int sky2_set_ringparam(struct net_device *dev,
3511 struct ethtool_ringparam *ering)
3512{
3513 struct sky2_port *sky2 = netdev_priv(dev);
3514 int err = 0;
3515
3516 if (ering->rx_pending > RX_MAX_PENDING ||
3517 ering->rx_pending < 8 ||
3518 ering->tx_pending < MAX_SKB_TX_LE ||
3519 ering->tx_pending > TX_RING_SIZE - 1)
3520 return -EINVAL;
3521
3522 if (netif_running(dev))
3523 sky2_down(dev);
3524
3525 sky2->rx_pending = ering->rx_pending;
3526 sky2->tx_pending = ering->tx_pending;
3527
1b537565 3528 if (netif_running(dev)) {
793b883e 3529 err = sky2_up(dev);
1b537565
SH		 3530 if (err)
3531 dev_close(dev);
6ed995bb
SH		 3532 else
3533 sky2_set_multicast(dev);
1b537565 3534 }
793b883e
SH		 3535
3536 return err;
3537}
3538
793b883e
SH		 3539static int sky2_get_regs_len(struct net_device *dev)
3540{
6e4cbb34 3541 return 0x4000;
793b883e
SH		 3542}
3543
3544/*
3545 * Returns copy of control register region
3ead5db7 3546 * Note: ethtool_get_regs always provides full size (16k) buffer
793b883e
SH		 3547 */
3548static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3549 void *p)
3550{
3551 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3552 const void __iomem *io = sky2->hw->regs;
295b54c4 3553 unsigned int b;
793b883e
SH		 3554
3555 regs->version = 1;
793b883e 3556
295b54c4
SH		 3557 for (b = 0; b < 128; b++) {
3558 /* This complicated switch statement is to make sure and
3559 * only access regions that are unreserved.
3560 * Some blocks are only valid on dual port cards.
3561 * and block 3 has some special diagnostic registers that
3562 * are poison.
3563 */
3564 switch (b) {
3565 case 3:
3566 /* skip diagnostic ram region */
3567 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
3568 break;
3ead5db7 3569
295b54c4
SH		 3570 /* dual port cards only */
3571 case 5: /* Tx Arbiter 2 */
3572 case 9: /* RX2 */
3573 case 14 ... 15: /* TX2 */
3574 case 17: case 19: /* Ram Buffer 2 */
3575 case 22 ... 23: /* Tx Ram Buffer 2 */
3576 case 25: /* Rx MAC Fifo 1 */
3577 case 27: /* Tx MAC Fifo 2 */
3578 case 31: /* GPHY 2 */
3579 case 40 ... 47: /* Pattern Ram 2 */
3580 case 52: case 54: /* TCP Segmentation 2 */
3581 case 112 ... 116: /* GMAC 2 */
3582 if (sky2->hw->ports == 1)
3583 goto reserved;
3584 /* fall through */
3585 case 0: /* Control */
3586 case 2: /* Mac address */
3587 case 4: /* Tx Arbiter 1 */
3588 case 7: /* PCI express reg */
3589 case 8: /* RX1 */
3590 case 12 ... 13: /* TX1 */
3591 case 16: case 18:/* Rx Ram Buffer 1 */
3592 case 20 ... 21: /* Tx Ram Buffer 1 */
3593 case 24: /* Rx MAC Fifo 1 */
3594 case 26: /* Tx MAC Fifo 1 */
3595 case 28 ... 29: /* Descriptor and status unit */
3596 case 30: /* GPHY 1*/
3597 case 32 ... 39: /* Pattern Ram 1 */
3598 case 48: case 50: /* TCP Segmentation 1 */
3599 case 56 ... 60: /* PCI space */
3600 case 80 ... 84: /* GMAC 1 */
3601 memcpy_fromio(p, io, 128);
3602 break;
3603 default:
3604reserved:
3605 memset(p, 0, 128);
3606 }
3ead5db7 3607
295b54c4
SH		 3608 p += 128;
3609 io += 128;
3610 }
793b883e 3611}
cd28ab6a 3612
b628ed98
SH		 3613/* In order to do Jumbo packets on these chips, need to turn off the
3614 * transmit store/forward. Therefore checksum offload won't work.
3615 */
3616static int no_tx_offload(struct net_device *dev)
3617{
3618 const struct sky2_port *sky2 = netdev_priv(dev);
3619 const struct sky2_hw *hw = sky2->hw;
3620
69161611 3621 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
b628ed98
SH		 3622}
3623
3624static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3625{
3626 if (data && no_tx_offload(dev))
3627 return -EINVAL;
3628
3629 return ethtool_op_set_tx_csum(dev, data);
3630}
3631
3632
3633static int sky2_set_tso(struct net_device *dev, u32 data)
3634{
3635 if (data && no_tx_offload(dev))
3636 return -EINVAL;
3637
3638 return ethtool_op_set_tso(dev, data);
3639}
3640
f4331a6d
SH		 3641static int sky2_get_eeprom_len(struct net_device *dev)
3642{
3643 struct sky2_port *sky2 = netdev_priv(dev);
b32f40c4 3644 struct sky2_hw *hw = sky2->hw;
f4331a6d
SH		 3645 u16 reg2;
3646
b32f40c4 3647 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
f4331a6d
SH		 3648 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3649}
3650
b32f40c4 3651static u32 sky2_vpd_read(struct sky2_hw *hw, int cap, u16 offset)
f4331a6d 3652{
167f53d0 3653 u32 val;
f4331a6d 3654
b32f40c4 3655 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
167f53d0
SH		 3656
3657 do {
b32f40c4 3658 offset = sky2_pci_read16(hw, cap + PCI_VPD_ADDR);
167f53d0
SH		 3659 } while (!(offset & PCI_VPD_ADDR_F));
3660
b32f40c4 3661 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
167f53d0 3662 return val;
f4331a6d
SH		 3663}
3664
b32f40c4 3665static void sky2_vpd_write(struct sky2_hw *hw, int cap, u16 offset, u32 val)
f4331a6d 3666{
b32f40c4
SH		 3667 sky2_pci_write16(hw, cap + PCI_VPD_DATA, val);
3668 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
f4331a6d 3669 do {
b32f40c4 3670 offset = sky2_pci_read16(hw, cap + PCI_VPD_ADDR);
167f53d0 3671 } while (offset & PCI_VPD_ADDR_F);
f4331a6d
SH		 3672}
3673
3674static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3675 u8 *data)
3676{
3677 struct sky2_port *sky2 = netdev_priv(dev);
3678 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3679 int length = eeprom->len;
3680 u16 offset = eeprom->offset;
3681
3682 if (!cap)
3683 return -EINVAL;
3684
3685 eeprom->magic = SKY2_EEPROM_MAGIC;
3686
3687 while (length > 0) {
b32f40c4 3688 u32 val = sky2_vpd_read(sky2->hw, cap, offset);
f4331a6d
SH		 3689 int n = min_t(int, length, sizeof(val));
3690
3691 memcpy(data, &val, n);
3692 length -= n;
3693 data += n;
3694 offset += n;
3695 }
3696 return 0;
3697}
3698
3699static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3700 u8 *data)
3701{
3702 struct sky2_port *sky2 = netdev_priv(dev);
3703 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3704 int length = eeprom->len;
3705 u16 offset = eeprom->offset;
3706
3707 if (!cap)
3708 return -EINVAL;
3709
3710 if (eeprom->magic != SKY2_EEPROM_MAGIC)
3711 return -EINVAL;
3712
3713 while (length > 0) {
3714 u32 val;
3715 int n = min_t(int, length, sizeof(val));
3716
3717 if (n < sizeof(val))
b32f40c4 3718 val = sky2_vpd_read(sky2->hw, cap, offset);
f4331a6d
SH		 3719 memcpy(&val, data, n);
3720
b32f40c4 3721 sky2_vpd_write(sky2->hw, cap, offset, val);
f4331a6d
SH		 3722
3723 length -= n;
3724 data += n;
3725 offset += n;
3726 }
3727 return 0;
3728}
3729
3730
7282d491 3731static const struct ethtool_ops sky2_ethtool_ops = {
f4331a6d
SH		 3732 .get_settings = sky2_get_settings,
3733 .set_settings = sky2_set_settings,
3734 .get_drvinfo = sky2_get_drvinfo,
3735 .get_wol = sky2_get_wol,
3736 .set_wol = sky2_set_wol,
3737 .get_msglevel = sky2_get_msglevel,
3738 .set_msglevel = sky2_set_msglevel,
3739 .nway_reset = sky2_nway_reset,
3740 .get_regs_len = sky2_get_regs_len,
3741 .get_regs = sky2_get_regs,
3742 .get_link = ethtool_op_get_link,
3743 .get_eeprom_len = sky2_get_eeprom_len,
3744 .get_eeprom = sky2_get_eeprom,
3745 .set_eeprom = sky2_set_eeprom,
f4331a6d 3746 .set_sg = ethtool_op_set_sg,
f4331a6d 3747 .set_tx_csum = sky2_set_tx_csum,
f4331a6d
SH		 3748 .set_tso = sky2_set_tso,
3749 .get_rx_csum = sky2_get_rx_csum,
3750 .set_rx_csum = sky2_set_rx_csum,
3751 .get_strings = sky2_get_strings,
3752 .get_coalesce = sky2_get_coalesce,
3753 .set_coalesce = sky2_set_coalesce,
3754 .get_ringparam = sky2_get_ringparam,
3755 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 3756 .get_pauseparam = sky2_get_pauseparam,
3757 .set_pauseparam = sky2_set_pauseparam,
f4331a6d 3758 .phys_id = sky2_phys_id,
b9f2c044 3759 .get_sset_count = sky2_get_sset_count,
cd28ab6a
SH		 3760 .get_ethtool_stats = sky2_get_ethtool_stats,
3761};
3762
3cf26753
SH		 3763#ifdef CONFIG_SKY2_DEBUG
3764
3765static struct dentry *sky2_debug;
3766
3767static int sky2_debug_show(struct seq_file *seq, void *v)
3768{
3769 struct net_device *dev = seq->private;
3770 const struct sky2_port *sky2 = netdev_priv(dev);
bea3348e 3771 struct sky2_hw *hw = sky2->hw;
3cf26753
SH		 3772 unsigned port = sky2->port;
3773 unsigned idx, last;
3774 int sop;
3775
3776 if (!netif_running(dev))
3777 return -ENETDOWN;
3778
3779 seq_printf(seq, "IRQ src=%x mask=%x control=%x\n",
3780 sky2_read32(hw, B0_ISRC),
3781 sky2_read32(hw, B0_IMSK),
3782 sky2_read32(hw, B0_Y2_SP_ICR));
3783
bea3348e 3784 napi_disable(&hw->napi);
3cf26753
SH		 3785 last = sky2_read16(hw, STAT_PUT_IDX);
3786
3787 if (hw->st_idx == last)
3788 seq_puts(seq, "Status ring (empty)\n");
3789 else {
3790 seq_puts(seq, "Status ring\n");
3791 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
3792 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
3793 const struct sky2_status_le *le = hw->st_le + idx;
3794 seq_printf(seq, "[%d] %#x %d %#x\n",
3795 idx, le->opcode, le->length, le->status);
3796 }
3797 seq_puts(seq, "\n");
3798 }
3799
3800 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
3801 sky2->tx_cons, sky2->tx_prod,
3802 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
3803 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
3804
3805 /* Dump contents of tx ring */
3806 sop = 1;
3807 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < TX_RING_SIZE;
3808 idx = RING_NEXT(idx, TX_RING_SIZE)) {
3809 const struct sky2_tx_le *le = sky2->tx_le + idx;
3810 u32 a = le32_to_cpu(le->addr);
3811
3812 if (sop)
3813 seq_printf(seq, "%u:", idx);
3814 sop = 0;
3815
3816 switch(le->opcode & ~HW_OWNER) {
3817 case OP_ADDR64:
3818 seq_printf(seq, " %#x:", a);
3819 break;
3820 case OP_LRGLEN:
3821 seq_printf(seq, " mtu=%d", a);
3822 break;
3823 case OP_VLAN:
3824 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
3825 break;
3826 case OP_TCPLISW:
3827 seq_printf(seq, " csum=%#x", a);
3828 break;
3829 case OP_LARGESEND:
3830 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
3831 break;
3832 case OP_PACKET:
3833 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
3834 break;
3835 case OP_BUFFER:
3836 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
3837 break;
3838 default:
3839 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
3840 a, le16_to_cpu(le->length));
3841 }
3842
3843 if (le->ctrl & EOP) {
3844 seq_putc(seq, '\n');
3845 sop = 1;
3846 }
3847 }
3848
3849 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
3850 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
3851 last = sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
3852 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
3853
bea3348e 3854 napi_enable(&hw->napi);
3cf26753
SH		 3855 return 0;
3856}
3857
3858static int sky2_debug_open(struct inode *inode, struct file *file)
3859{
3860 return single_open(file, sky2_debug_show, inode->i_private);
3861}
3862
3863static const struct file_operations sky2_debug_fops = {
3864 .owner = THIS_MODULE,
3865 .open = sky2_debug_open,
3866 .read = seq_read,
3867 .llseek = seq_lseek,
3868 .release = single_release,
3869};
3870
3871/*
3872 * Use network device events to create/remove/rename
3873 * debugfs file entries
3874 */
3875static int sky2_device_event(struct notifier_block *unused,
3876 unsigned long event, void *ptr)
3877{
3878 struct net_device *dev = ptr;
5b296bc9 3879 struct sky2_port *sky2 = netdev_priv(dev);
3cf26753 3880
5b296bc9
SH		 3881 if (dev->open != sky2_up || !sky2_debug)
3882 return NOTIFY_DONE;
3cf26753 3883
5b296bc9
SH		 3884 switch(event) {
3885 case NETDEV_CHANGENAME:
3886 if (sky2->debugfs) {
3887 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
3888 sky2_debug, dev->name);
3889 }
3890 break;
3cf26753 3891
5b296bc9
SH		 3892 case NETDEV_GOING_DOWN:
3893 if (sky2->debugfs) {
3894 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
3895 dev->name);
3896 debugfs_remove(sky2->debugfs);
3897 sky2->debugfs = NULL;
3cf26753 3898 }
5b296bc9
SH		 3899 break;
3900
3901 case NETDEV_UP:
3902 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
3903 sky2_debug, dev,
3904 &sky2_debug_fops);
3905 if (IS_ERR(sky2->debugfs))
3906 sky2->debugfs = NULL;
3cf26753
SH		 3907 }
3908
3909 return NOTIFY_DONE;
3910}
3911
3912static struct notifier_block sky2_notifier = {
3913 .notifier_call = sky2_device_event,
3914};
3915
3916
3917static __init void sky2_debug_init(void)
3918{
3919 struct dentry *ent;
3920
3921 ent = debugfs_create_dir("sky2", NULL);
3922 if (!ent || IS_ERR(ent))
3923 return;
3924
3925 sky2_debug = ent;
3926 register_netdevice_notifier(&sky2_notifier);
3927}
3928
3929static __exit void sky2_debug_cleanup(void)
3930{
3931 if (sky2_debug) {
3932 unregister_netdevice_notifier(&sky2_notifier);
3933 debugfs_remove(sky2_debug);
3934 sky2_debug = NULL;
3935 }
3936}
3937
3938#else
3939#define sky2_debug_init()
3940#define sky2_debug_cleanup()
3941#endif
3942
3943
cd28ab6a
SH		 3944/* Initialize network device */
3945static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
e3173832
SH		 3946 unsigned port,
3947 int highmem, int wol)
cd28ab6a
SH		 3948{
3949 struct sky2_port *sky2;
3950 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3951
3952 if (!dev) {
898eb71c 3953 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
cd28ab6a
SH		 3954 return NULL;
3955 }
3956
cd28ab6a 3957 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 3958 dev->irq = hw->pdev->irq;
cd28ab6a
SH		 3959 dev->open = sky2_up;
3960 dev->stop = sky2_down;
ef743d33 3961 dev->do_ioctl = sky2_ioctl;
cd28ab6a 3962 dev->hard_start_xmit = sky2_xmit_frame;
cd28ab6a
SH		 3963 dev->set_multicast_list = sky2_set_multicast;
3964 dev->set_mac_address = sky2_set_mac_address;
3965 dev->change_mtu = sky2_change_mtu;
3966 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3967 dev->tx_timeout = sky2_tx_timeout;
3968 dev->watchdog_timeo = TX_WATCHDOG;
cd28ab6a 3969#ifdef CONFIG_NET_POLL_CONTROLLER
a5e68c02
SH		 3970 if (port == 0)
3971 dev->poll_controller = sky2_netpoll;
cd28ab6a 3972#endif
cd28ab6a
SH		 3973
3974 sky2 = netdev_priv(dev);
3975 sky2->netdev = dev;
3976 sky2->hw = hw;
3977 sky2->msg_enable = netif_msg_init(debug, default_msg);
3978
cd28ab6a
SH		 3979 /* Auto speed and flow control */
3980 sky2->autoneg = AUTONEG_ENABLE;
16ad91e1
SH		 3981 sky2->flow_mode = FC_BOTH;
3982
cd28ab6a
SH		 3983 sky2->duplex = -1;
3984 sky2->speed = -1;
3985 sky2->advertising = sky2_supported_modes(hw);
8b31cfbc 3986 sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);
e3173832 3987 sky2->wol = wol;
75d070c5 3988
e07b1aa8 3989 spin_lock_init(&sky2->phy_lock);
793b883e 3990 sky2->tx_pending = TX_DEF_PENDING;
290d4de5 3991 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 3992
3993 hw->dev[port] = dev;
3994
3995 sky2->port = port;
3996
4a50a876 3997 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a
SH		 3998 if (highmem)
3999 dev->features |= NETIF_F_HIGHDMA;
cd28ab6a 4000
d1f13708 4001#ifdef SKY2_VLAN_TAG_USED
d6c9bc1e
SH		 4002 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4003 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4004 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4005 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4006 dev->vlan_rx_register = sky2_vlan_rx_register;
4007 }
d1f13708
SH		 4008#endif
4009
cd28ab6a 4010 /* read the mac address */
793b883e 4011 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 4012 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a 4013
cd28ab6a
SH		 4014 return dev;
4015}
4016
28bd181a 4017static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 4018{
4019 const struct sky2_port *sky2 = netdev_priv(dev);
0795af57 4020 DECLARE_MAC_BUF(mac);
cd28ab6a
SH		 4021
4022 if (netif_msg_probe(sky2))
0795af57
JP		 4023 printk(KERN_INFO PFX "%s: addr %s\n",
4024 dev->name, print_mac(mac, dev->dev_addr));
cd28ab6a
SH		 4025}
4026
fb2690a9 4027/* Handle software interrupt used during MSI test */
7d12e780 4028static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 4029{
4030 struct sky2_hw *hw = dev_id;
4031 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4032
4033 if (status == 0)
4034 return IRQ_NONE;
4035
4036 if (status & Y2_IS_IRQ_SW) {
ea76e635 4037 hw->flags |= SKY2_HW_USE_MSI;
fb2690a9
SH		 4038 wake_up(&hw->msi_wait);
4039 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4040 }
4041 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4042
4043 return IRQ_HANDLED;
4044}
4045
4046/* Test interrupt path by forcing a a software IRQ */
4047static int __devinit sky2_test_msi(struct sky2_hw *hw)
4048{
4049 struct pci_dev *pdev = hw->pdev;
4050 int err;
4051
bb507fe1
SH		 4052 init_waitqueue_head (&hw->msi_wait);
4053
fb2690a9
SH		 4054 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4055
b0a20ded 4056 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9 4057 if (err) {
b02a9258 4058 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
fb2690a9
SH		 4059 return err;
4060 }
4061
fb2690a9 4062 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 4063 sky2_read8(hw, B0_CTST);
fb2690a9 4064
ea76e635 4065 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
fb2690a9 4066
ea76e635 4067 if (!(hw->flags & SKY2_HW_USE_MSI)) {
fb2690a9 4068 /* MSI test failed, go back to INTx mode */
b02a9258
SH		 4069 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4070 "switching to INTx mode.\n");
fb2690a9
SH		 4071
4072 err = -EOPNOTSUPP;
4073 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4074 }
4075
4076 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 4077 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 4078
4079 free_irq(pdev->irq, hw);
4080
4081 return err;
4082}
4083
e3173832
SH		 4084static int __devinit pci_wake_enabled(struct pci_dev *dev)
4085{
4086 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
4087 u16 value;
4088
4089 if (!pm)
4090 return 0;
4091 if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
4092 return 0;
4093 return value & PCI_PM_CTRL_PME_ENABLE;
4094}
4095
cd28ab6a
SH		 4096static int __devinit sky2_probe(struct pci_dev *pdev,
4097 const struct pci_device_id *ent)
4098{
7f60c64b 4099 struct net_device *dev;
cd28ab6a 4100 struct sky2_hw *hw;
e3173832 4101 int err, using_dac = 0, wol_default;
cd28ab6a 4102
793b883e
SH		 4103 err = pci_enable_device(pdev);
4104 if (err) {
b02a9258 4105 dev_err(&pdev->dev, "cannot enable PCI device\n");
cd28ab6a
SH		 4106 goto err_out;
4107 }
4108
793b883e
SH		 4109 err = pci_request_regions(pdev, DRV_NAME);
4110 if (err) {
b02a9258 4111 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
44a1d2e5 4112 goto err_out_disable;
cd28ab6a
SH		 4113 }
4114
4115 pci_set_master(pdev);
4116
d1f3d4dd
SH		 4117 if (sizeof(dma_addr_t) > sizeof(u32) &&
4118 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
4119 using_dac = 1;
4120 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
4121 if (err < 0) {
b02a9258
SH		 4122 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4123 "for consistent allocations\n");
d1f3d4dd
SH		 4124 goto err_out_free_regions;
4125 }
d1f3d4dd 4126 } else {
cd28ab6a
SH		 4127 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
4128 if (err) {
b02a9258 4129 dev_err(&pdev->dev, "no usable DMA configuration\n");
cd28ab6a
SH		 4130 goto err_out_free_regions;
4131 }
4132 }
d1f3d4dd 4133
e3173832
SH		 4134 wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
4135
cd28ab6a 4136 err = -ENOMEM;
6aad85d6 4137 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a 4138 if (!hw) {
b02a9258 4139 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
cd28ab6a
SH		 4140 goto err_out_free_regions;
4141 }
4142
cd28ab6a 4143 hw->pdev = pdev;
cd28ab6a
SH		 4144
4145 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4146 if (!hw->regs) {
b02a9258 4147 dev_err(&pdev->dev, "cannot map device registers\n");
cd28ab6a
SH		 4148 goto err_out_free_hw;
4149 }
4150
56a645cc 4151#ifdef __BIG_ENDIAN
f65b138c
SH		 4152 /* The sk98lin vendor driver uses hardware byte swapping but
4153 * this driver uses software swapping.
4154 */
56a645cc
SH		 4155 {
4156 u32 reg;
b32f40c4 4157 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
f65b138c 4158 reg &= ~PCI_REV_DESC;
b32f40c4 4159 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
56a645cc
SH		 4160 }
4161#endif
4162
08c06d8a 4163 /* ring for status responses */
167f53d0 4164 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
08c06d8a
SH		 4165 if (!hw->st_le)
4166 goto err_out_iounmap;
4167
e3173832 4168 err = sky2_init(hw);
cd28ab6a 4169 if (err)
793b883e 4170 goto err_out_iounmap;
cd28ab6a 4171
b02a9258 4172 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
7c7459d1
GKH		 4173 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
4174 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
793b883e 4175 hw->chip_id, hw->chip_rev);
cd28ab6a 4176
e3173832
SH		 4177 sky2_reset(hw);
4178
4179 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
7f60c64b 4180 if (!dev) {
4181 err = -ENOMEM;
cd28ab6a 4182 goto err_out_free_pci;
7f60c64b 4183 }
cd28ab6a 4184
9fa1b1f3
SH		 4185 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4186 err = sky2_test_msi(hw);
4187 if (err == -EOPNOTSUPP)
4188 pci_disable_msi(pdev);
4189 else if (err)
4190 goto err_out_free_netdev;
4191 }
4192
793b883e
SH		 4193 err = register_netdev(dev);
4194 if (err) {
b02a9258 4195 dev_err(&pdev->dev, "cannot register net device\n");
cd28ab6a
SH		 4196 goto err_out_free_netdev;
4197 }
4198
6de16237
SH		 4199 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4200
ea76e635
SH		 4201 err = request_irq(pdev->irq, sky2_intr,
4202 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
b0a20ded 4203 dev->name, hw);
9fa1b1f3 4204 if (err) {
b02a9258 4205 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
9fa1b1f3
SH		 4206 goto err_out_unregister;
4207 }
4208 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4209 napi_enable(&hw->napi);
9fa1b1f3 4210
cd28ab6a
SH		 4211 sky2_show_addr(dev);
4212
7f60c64b 4213 if (hw->ports > 1) {
4214 struct net_device *dev1;
4215
e3173832 4216 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
b02a9258
SH		 4217 if (!dev1)
4218 dev_warn(&pdev->dev, "allocation for second device failed\n");
4219 else if ((err = register_netdev(dev1))) {
4220 dev_warn(&pdev->dev,
4221 "register of second port failed (%d)\n", err);
cd28ab6a
SH		 4222 hw->dev[1] = NULL;
4223 free_netdev(dev1);
b02a9258
SH		 4224 } else
4225 sky2_show_addr(dev1);
cd28ab6a
SH		 4226 }
4227
32c2c300 4228 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
81906791
SH		 4229 INIT_WORK(&hw->restart_work, sky2_restart);
4230
793b883e
SH		 4231 pci_set_drvdata(pdev, hw);
4232
cd28ab6a
SH		 4233 return 0;
4234
793b883e 4235err_out_unregister:
ea76e635 4236 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4237 pci_disable_msi(pdev);
793b883e 4238 unregister_netdev(dev);
cd28ab6a
SH		 4239err_out_free_netdev:
4240 free_netdev(dev);
cd28ab6a 4241err_out_free_pci:
793b883e 4242 sky2_write8(hw, B0_CTST, CS_RST_SET);
167f53d0 4243 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4244err_out_iounmap:
4245 iounmap(hw->regs);
4246err_out_free_hw:
4247 kfree(hw);
4248err_out_free_regions:
4249 pci_release_regions(pdev);
44a1d2e5 4250err_out_disable:
cd28ab6a 4251 pci_disable_device(pdev);
cd28ab6a 4252err_out:
549a68c3 4253 pci_set_drvdata(pdev, NULL);
cd28ab6a
SH		 4254 return err;
4255}
4256
4257static void __devexit sky2_remove(struct pci_dev *pdev)
4258{
793b883e 4259 struct sky2_hw *hw = pci_get_drvdata(pdev);
6de16237 4260 int i;
cd28ab6a 4261
793b883e 4262 if (!hw)
cd28ab6a
SH		 4263 return;
4264
32c2c300 4265 del_timer_sync(&hw->watchdog_timer);
6de16237 4266 cancel_work_sync(&hw->restart_work);
d27ed387 4267
b877fe28 4268 for (i = hw->ports-1; i >= 0; --i)
6de16237 4269 unregister_netdev(hw->dev[i]);
81906791 4270
d27ed387 4271 sky2_write32(hw, B0_IMSK, 0);
cd28ab6a 4272
ae306cca
SH		 4273 sky2_power_aux(hw);
4274
cd28ab6a 4275 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 4276 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 4277 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 4278
4279 free_irq(pdev->irq, hw);
ea76e635 4280 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4281 pci_disable_msi(pdev);
793b883e 4282 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4283 pci_release_regions(pdev);
4284 pci_disable_device(pdev);
793b883e 4285
b877fe28 4286 for (i = hw->ports-1; i >= 0; --i)
6de16237
SH		 4287 free_netdev(hw->dev[i]);
4288
cd28ab6a
SH		 4289 iounmap(hw->regs);
4290 kfree(hw);
5afa0a9c 4291
cd28ab6a
SH		 4292 pci_set_drvdata(pdev, NULL);
4293}
4294
4295#ifdef CONFIG_PM
4296static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4297{
793b883e 4298 struct sky2_hw *hw = pci_get_drvdata(pdev);
e3173832 4299 int i, wol = 0;
cd28ab6a 4300
549a68c3
SH		 4301 if (!hw)
4302 return 0;
4303
f05267e7 4304 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4305 struct net_device *dev = hw->dev[i];
e3173832 4306 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 4307
e3173832 4308 if (netif_running(dev))
5afa0a9c 4309 sky2_down(dev);
e3173832
SH		 4310
4311 if (sky2->wol)
4312 sky2_wol_init(sky2);
4313
4314 wol |= sky2->wol;
cd28ab6a
SH		 4315 }
4316
8ab8fca2 4317 sky2_write32(hw, B0_IMSK, 0);
6de16237 4318 napi_disable(&hw->napi);
ae306cca 4319 sky2_power_aux(hw);
e3173832 4320
d374c1c1 4321 pci_save_state(pdev);
e3173832 4322 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
ae306cca
SH		 4323 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4324
2ccc99b7 4325 return 0;
cd28ab6a
SH		 4326}
4327
4328static int sky2_resume(struct pci_dev *pdev)
4329{
793b883e 4330 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 4331 int i, err;
cd28ab6a 4332
549a68c3
SH		 4333 if (!hw)
4334 return 0;
4335
ae306cca
SH		 4336 err = pci_set_power_state(pdev, PCI_D0);
4337 if (err)
4338 goto out;
4339
4340 err = pci_restore_state(pdev);
4341 if (err)
4342 goto out;
4343
cd28ab6a 4344 pci_enable_wake(pdev, PCI_D0, 0);
1ad5b4a5
SH		 4345
4346 /* Re-enable all clocks */
05745c4a
SH		 4347 if (hw->chip_id == CHIP_ID_YUKON_EX ||
4348 hw->chip_id == CHIP_ID_YUKON_EC_U ||
4349 hw->chip_id == CHIP_ID_YUKON_FE_P)
b32f40c4 4350 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
1ad5b4a5 4351
e3173832 4352 sky2_reset(hw);
8ab8fca2 4353 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4354 napi_enable(&hw->napi);
8ab8fca2 4355
f05267e7 4356 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4357 struct net_device *dev = hw->dev[i];
6a5706b9 4358 if (netif_running(dev)) {
08c06d8a
SH		 4359 err = sky2_up(dev);
4360 if (err) {
4361 printk(KERN_ERR PFX "%s: could not up: %d\n",
4362 dev->name, err);
4363 dev_close(dev);
eb35cf60 4364 goto out;
5afa0a9c 4365 }
d1b139c0
SH		 4366
4367 sky2_set_multicast(dev);
cd28ab6a
SH		 4368 }
4369 }
eb35cf60 4370
ae306cca 4371 return 0;
08c06d8a 4372out:
b02a9258 4373 dev_err(&pdev->dev, "resume failed (%d)\n", err);
ae306cca 4374 pci_disable_device(pdev);
08c06d8a 4375 return err;
cd28ab6a
SH		 4376}
4377#endif
4378
e3173832
SH		 4379static void sky2_shutdown(struct pci_dev *pdev)
4380{
4381 struct sky2_hw *hw = pci_get_drvdata(pdev);
4382 int i, wol = 0;
4383
549a68c3
SH		 4384 if (!hw)
4385 return;
4386
5c0d6b34 4387 del_timer_sync(&hw->watchdog_timer);
e3173832
SH		 4388
4389 for (i = 0; i < hw->ports; i++) {
4390 struct net_device *dev = hw->dev[i];
4391 struct sky2_port *sky2 = netdev_priv(dev);
4392
4393 if (sky2->wol) {
4394 wol = 1;
4395 sky2_wol_init(sky2);
4396 }
4397 }
4398
4399 if (wol)
4400 sky2_power_aux(hw);
4401
4402 pci_enable_wake(pdev, PCI_D3hot, wol);
4403 pci_enable_wake(pdev, PCI_D3cold, wol);
4404
4405 pci_disable_device(pdev);
4406 pci_set_power_state(pdev, PCI_D3hot);
4407
4408}
4409
cd28ab6a 4410static struct pci_driver sky2_driver = {
793b883e
SH		 4411 .name = DRV_NAME,
4412 .id_table = sky2_id_table,
4413 .probe = sky2_probe,
4414 .remove = __devexit_p(sky2_remove),
cd28ab6a 4415#ifdef CONFIG_PM
793b883e
SH		 4416 .suspend = sky2_suspend,
4417 .resume = sky2_resume,
cd28ab6a 4418#endif
e3173832 4419 .shutdown = sky2_shutdown,
cd28ab6a
SH		 4420};
4421
4422static int __init sky2_init_module(void)
4423{
3cf26753 4424 sky2_debug_init();
50241c4c 4425 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 4426}
4427
4428static void __exit sky2_cleanup_module(void)
4429{
4430 pci_unregister_driver(&sky2_driver);
3cf26753 4431 sky2_debug_cleanup();
cd28ab6a
SH		 4432}
4433
4434module_init(sky2_init_module);
4435module_exit(sky2_cleanup_module);
4436
4437MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
65ebe634 4438MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
cd28ab6a 4439MODULE_LICENSE("GPL");
5f4f9dc1 4440MODULE_VERSION(DRV_VERSION);
kernel source for telekom puls (alcatel/mediatek)