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KVM: x86: Call vcpu_load and vcpu_put in cpuid_update
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 *
9 * Authors:
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
85f455f7 18#include "irq.h"
1d737c8a 19#include "mmu.h"
e495606d 20
edf88417 21#include <linux/kvm_host.h>
6aa8b732 22#include <linux/module.h>
9d8f549d 23#include <linux/kernel.h>
6aa8b732
AK		 24#include <linux/mm.h>
25#include <linux/highmem.h>
e8edc6e0 26#include <linux/sched.h>
c7addb90 27#include <linux/moduleparam.h>
229456fc 28#include <linux/ftrace_event.h>
5a0e3ad6 29#include <linux/slab.h>
5fdbf976 30#include "kvm_cache_regs.h"
35920a35 31#include "x86.h"
e495606d 32
6aa8b732 33#include <asm/io.h>
3b3be0d1 34#include <asm/desc.h>
13673a90 35#include <asm/vmx.h>
6210e37b 36#include <asm/virtext.h>
a0861c02 37#include <asm/mce.h>
6aa8b732 38
229456fc
MT		 39#include "trace.h"
40
4ecac3fd
AK		 41#define __ex(x) __kvm_handle_fault_on_reboot(x)
42
6aa8b732
AK		 43MODULE_AUTHOR("Qumranet");
44MODULE_LICENSE("GPL");
45
4462d21a 46static int __read_mostly bypass_guest_pf = 1;
c1f8bc04 47module_param(bypass_guest_pf, bool, S_IRUGO);
c7addb90 48
4462d21a 49static int __read_mostly enable_vpid = 1;
736caefe 50module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 51
4462d21a 52static int __read_mostly flexpriority_enabled = 1;
736caefe 53module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 54
4462d21a 55static int __read_mostly enable_ept = 1;
736caefe 56module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 57
3a624e29
NK		 58static int __read_mostly enable_unrestricted_guest = 1;
59module_param_named(unrestricted_guest,
60 enable_unrestricted_guest, bool, S_IRUGO);
61
4462d21a 62static int __read_mostly emulate_invalid_guest_state = 0;
c1f8bc04 63module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 64
cdc0e244
AK		 65#define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
66 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
67#define KVM_GUEST_CR0_MASK \
68 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
69#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
81231c69 70 (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 71#define KVM_VM_CR0_ALWAYS_ON \
72 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 73#define KVM_CR4_GUEST_OWNED_BITS \
74 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
75 | X86_CR4_OSXMMEXCPT)
76
cdc0e244
AK		 77#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
78#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
79
78ac8b47
AK		 80#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
81
4b8d54f9
ZE		 82/*
83 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
84 * ple_gap: upper bound on the amount of time between two successive
85 * executions of PAUSE in a loop. Also indicate if ple enabled.
86 * According to test, this time is usually small than 41 cycles.
87 * ple_window: upper bound on the amount of time a guest is allowed to execute
88 * in a PAUSE loop. Tests indicate that most spinlocks are held for
89 * less than 2^12 cycles
90 * Time is measured based on a counter that runs at the same rate as the TSC,
91 * refer SDM volume 3b section 21.6.13 & 22.1.3.
92 */
93#define KVM_VMX_DEFAULT_PLE_GAP 41
94#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
95static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
96module_param(ple_gap, int, S_IRUGO);
97
98static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
99module_param(ple_window, int, S_IRUGO);
100
a2fa3e9f
GH		 101struct vmcs {
102 u32 revision_id;
103 u32 abort;
104 char data[0];
105};
106
26bb0981
AK		 107struct shared_msr_entry {
108 unsigned index;
109 u64 data;
d5696725 110 u64 mask;
26bb0981
AK		 111};
112
a2fa3e9f 113struct vcpu_vmx {
fb3f0f51 114 struct kvm_vcpu vcpu;
543e4243 115 struct list_head local_vcpus_link;
313dbd49 116 unsigned long host_rsp;
a2fa3e9f 117 int launched;
29bd8a78 118 u8 fail;
1155f76a 119 u32 idt_vectoring_info;
26bb0981 120 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 121 int nmsrs;
122 int save_nmsrs;
a2fa3e9f 123#ifdef CONFIG_X86_64
44ea2b17
AK		 124 u64 msr_host_kernel_gs_base;
125 u64 msr_guest_kernel_gs_base;
a2fa3e9f
GH		 126#endif
127 struct vmcs *vmcs;
128 struct {
129 int loaded;
130 u16 fs_sel, gs_sel, ldt_sel;
152d3f2f
LV		 131 int gs_ldt_reload_needed;
132 int fs_reload_needed;
d77c26fc 133 } host_state;
9c8cba37 134 struct {
7ffd92c5 135 int vm86_active;
78ac8b47 136 ulong save_rflags;
7ffd92c5
AK		 137 struct kvm_save_segment {
138 u16 selector;
139 unsigned long base;
140 u32 limit;
141 u32 ar;
142 } tr, es, ds, fs, gs;
9c8cba37
AK		 143 struct {
144 bool pending;
145 u8 vector;
146 unsigned rip;
147 } irq;
148 } rmode;
2384d2b3 149 int vpid;
04fa4d32 150 bool emulation_required;
3b86cd99
JK		 151
152 /* Support for vnmi-less CPUs */
153 int soft_vnmi_blocked;
154 ktime_t entry_time;
155 s64 vnmi_blocked_time;
a0861c02 156 u32 exit_reason;
4e47c7a6
SY		 157
158 bool rdtscp_enabled;
a2fa3e9f
GH		 159};
160
161static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
162{
fb3f0f51 163 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 164}
165
b7ebfb05 166static int init_rmode(struct kvm *kvm);
4e1096d2 167static u64 construct_eptp(unsigned long root_hpa);
75880a01 168
6aa8b732
AK		 169static DEFINE_PER_CPU(struct vmcs *, vmxarea);
170static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
543e4243 171static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
6aa8b732 172
3e7c73e9
AK		 173static unsigned long *vmx_io_bitmap_a;
174static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 175static unsigned long *vmx_msr_bitmap_legacy;
176static unsigned long *vmx_msr_bitmap_longmode;
fdef3ad1 177
2384d2b3
SY		 178static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
179static DEFINE_SPINLOCK(vmx_vpid_lock);
180
1c3d14fe 181static struct vmcs_config {
6aa8b732
AK		 182 int size;
183 int order;
184 u32 revision_id;
1c3d14fe
YS		 185 u32 pin_based_exec_ctrl;
186 u32 cpu_based_exec_ctrl;
f78e0e2e 187 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 188 u32 vmexit_ctrl;
189 u32 vmentry_ctrl;
190} vmcs_config;
6aa8b732 191
efff9e53 192static struct vmx_capability {
d56f546d
SY		 193 u32 ept;
194 u32 vpid;
195} vmx_capability;
196
6aa8b732
AK		 197#define VMX_SEGMENT_FIELD(seg) \
198 [VCPU_SREG_##seg] = { \
199 .selector = GUEST_##seg##_SELECTOR, \
200 .base = GUEST_##seg##_BASE, \
201 .limit = GUEST_##seg##_LIMIT, \
202 .ar_bytes = GUEST_##seg##_AR_BYTES, \
203 }
204
205static struct kvm_vmx_segment_field {
206 unsigned selector;
207 unsigned base;
208 unsigned limit;
209 unsigned ar_bytes;
210} kvm_vmx_segment_fields[] = {
211 VMX_SEGMENT_FIELD(CS),
212 VMX_SEGMENT_FIELD(DS),
213 VMX_SEGMENT_FIELD(ES),
214 VMX_SEGMENT_FIELD(FS),
215 VMX_SEGMENT_FIELD(GS),
216 VMX_SEGMENT_FIELD(SS),
217 VMX_SEGMENT_FIELD(TR),
218 VMX_SEGMENT_FIELD(LDTR),
219};
220
26bb0981
AK		 221static u64 host_efer;
222
6de4f3ad
AK		 223static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
224
4d56c8a7
AK		 225/*
226 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
227 * away by decrementing the array size.
228 */
6aa8b732 229static const u32 vmx_msr_index[] = {
05b3e0c2 230#ifdef CONFIG_X86_64
44ea2b17 231 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 232#endif
4e47c7a6 233 MSR_EFER, MSR_TSC_AUX, MSR_K6_STAR,
6aa8b732 234};
9d8f549d 235#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 236
6aa8b732
AK		 237static inline int is_page_fault(u32 intr_info)
238{
239 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
240 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 241 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 242}
243
2ab455cc
AL		 244static inline int is_no_device(u32 intr_info)
245{
246 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
247 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 248 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 249}
250
7aa81cc0
AL		 251static inline int is_invalid_opcode(u32 intr_info)
252{
253 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
254 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 255 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 256}
257
6aa8b732
AK		 258static inline int is_external_interrupt(u32 intr_info)
259{
260 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
261 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
262}
263
a0861c02
AK		 264static inline int is_machine_check(u32 intr_info)
265{
266 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
267 INTR_INFO_VALID_MASK)) ==
268 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
269}
270
25c5f225
SY		 271static inline int cpu_has_vmx_msr_bitmap(void)
272{
04547156 273 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 274}
275
6e5d865c
YS		 276static inline int cpu_has_vmx_tpr_shadow(void)
277{
04547156 278 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 279}
280
281static inline int vm_need_tpr_shadow(struct kvm *kvm)
282{
04547156 283 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 284}
285
f78e0e2e
SY		 286static inline int cpu_has_secondary_exec_ctrls(void)
287{
04547156
SY		 288 return vmcs_config.cpu_based_exec_ctrl &
289 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 290}
291
774ead3a 292static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 293{
04547156
SY		 294 return vmcs_config.cpu_based_2nd_exec_ctrl &
295 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
296}
297
298static inline bool cpu_has_vmx_flexpriority(void)
299{
300 return cpu_has_vmx_tpr_shadow() &&
301 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 302}
303
e799794e
MT		 304static inline bool cpu_has_vmx_ept_execute_only(void)
305{
306 return !!(vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT);
307}
308
309static inline bool cpu_has_vmx_eptp_uncacheable(void)
310{
311 return !!(vmx_capability.ept & VMX_EPTP_UC_BIT);
312}
313
314static inline bool cpu_has_vmx_eptp_writeback(void)
315{
316 return !!(vmx_capability.ept & VMX_EPTP_WB_BIT);
317}
318
319static inline bool cpu_has_vmx_ept_2m_page(void)
320{
321 return !!(vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT);
322}
323
878403b7
SY		 324static inline bool cpu_has_vmx_ept_1g_page(void)
325{
326 return !!(vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT);
327}
328
d56f546d
SY		 329static inline int cpu_has_vmx_invept_individual_addr(void)
330{
04547156 331 return !!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT);
d56f546d
SY		 332}
333
334static inline int cpu_has_vmx_invept_context(void)
335{
04547156 336 return !!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT);
d56f546d
SY		 337}
338
339static inline int cpu_has_vmx_invept_global(void)
340{
04547156 341 return !!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT);
d56f546d
SY		 342}
343
344static inline int cpu_has_vmx_ept(void)
345{
04547156
SY		 346 return vmcs_config.cpu_based_2nd_exec_ctrl &
347 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 348}
349
3a624e29
NK		 350static inline int cpu_has_vmx_unrestricted_guest(void)
351{
352 return vmcs_config.cpu_based_2nd_exec_ctrl &
353 SECONDARY_EXEC_UNRESTRICTED_GUEST;
354}
355
4b8d54f9
ZE		 356static inline int cpu_has_vmx_ple(void)
357{
358 return vmcs_config.cpu_based_2nd_exec_ctrl &
359 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
360}
361
f78e0e2e
SY		 362static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
363{
6d3e435e 364 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 365}
366
2384d2b3
SY		 367static inline int cpu_has_vmx_vpid(void)
368{
04547156
SY		 369 return vmcs_config.cpu_based_2nd_exec_ctrl &
370 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 371}
372
4e47c7a6
SY		 373static inline int cpu_has_vmx_rdtscp(void)
374{
375 return vmcs_config.cpu_based_2nd_exec_ctrl &
376 SECONDARY_EXEC_RDTSCP;
377}
378
f08864b4
SY		 379static inline int cpu_has_virtual_nmis(void)
380{
381 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
382}
383
04547156
SY		 384static inline bool report_flexpriority(void)
385{
386 return flexpriority_enabled;
387}
388
8b9cf98c 389static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 390{
391 int i;
392
a2fa3e9f 393 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 394 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 395 return i;
396 return -1;
397}
398
2384d2b3
SY		 399static inline void __invvpid(int ext, u16 vpid, gva_t gva)
400{
401 struct {
402 u64 vpid : 16;
403 u64 rsvd : 48;
404 u64 gva;
405 } operand = { vpid, 0, gva };
406
4ecac3fd 407 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 408 /* CF==1 or ZF==1 --> rc = -1 */
409 "; ja 1f ; ud2 ; 1:"
410 : : "a"(&operand), "c"(ext) : "cc", "memory");
411}
412
1439442c
SY		 413static inline void __invept(int ext, u64 eptp, gpa_t gpa)
414{
415 struct {
416 u64 eptp, gpa;
417 } operand = {eptp, gpa};
418
4ecac3fd 419 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 420 /* CF==1 or ZF==1 --> rc = -1 */
421 "; ja 1f ; ud2 ; 1:\n"
422 : : "a" (&operand), "c" (ext) : "cc", "memory");
423}
424
26bb0981 425static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 426{
427 int i;
428
8b9cf98c 429 i = __find_msr_index(vmx, msr);
a75beee6 430 if (i >= 0)
a2fa3e9f 431 return &vmx->guest_msrs[i];
8b6d44c7 432 return NULL;
7725f0ba
AK		 433}
434
6aa8b732
AK		 435static void vmcs_clear(struct vmcs *vmcs)
436{
437 u64 phys_addr = __pa(vmcs);
438 u8 error;
439
4ecac3fd 440 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
6aa8b732
AK		 441 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
442 : "cc", "memory");
443 if (error)
444 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
445 vmcs, phys_addr);
446}
447
448static void __vcpu_clear(void *arg)
449{
8b9cf98c 450 struct vcpu_vmx *vmx = arg;
d3b2c338 451 int cpu = raw_smp_processor_id();
6aa8b732 452
8b9cf98c 453 if (vmx->vcpu.cpu == cpu)
a2fa3e9f
GH		 454 vmcs_clear(vmx->vmcs);
455 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
6aa8b732 456 per_cpu(current_vmcs, cpu) = NULL;
ad312c7c 457 rdtscll(vmx->vcpu.arch.host_tsc);
543e4243
AK		 458 list_del(&vmx->local_vcpus_link);
459 vmx->vcpu.cpu = -1;
460 vmx->launched = 0;
6aa8b732
AK		 461}
462
8b9cf98c 463static void vcpu_clear(struct vcpu_vmx *vmx)
8d0be2b3 464{
eae5ecb5
AK		 465 if (vmx->vcpu.cpu == -1)
466 return;
8691e5a8 467 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
8d0be2b3
AK		 468}
469
2384d2b3
SY		 470static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
471{
472 if (vmx->vpid == 0)
473 return;
474
475 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
476}
477
1439442c
SY		 478static inline void ept_sync_global(void)
479{
480 if (cpu_has_vmx_invept_global())
481 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
482}
483
484static inline void ept_sync_context(u64 eptp)
485{
089d034e 486 if (enable_ept) {
1439442c
SY		 487 if (cpu_has_vmx_invept_context())
488 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
489 else
490 ept_sync_global();
491 }
492}
493
494static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
495{
089d034e 496 if (enable_ept) {
1439442c
SY		 497 if (cpu_has_vmx_invept_individual_addr())
498 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
499 eptp, gpa);
500 else
501 ept_sync_context(eptp);
502 }
503}
504
6aa8b732
AK		 505static unsigned long vmcs_readl(unsigned long field)
506{
507 unsigned long value;
508
4ecac3fd 509 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
6aa8b732
AK		 510 : "=a"(value) : "d"(field) : "cc");
511 return value;
512}
513
514static u16 vmcs_read16(unsigned long field)
515{
516 return vmcs_readl(field);
517}
518
519static u32 vmcs_read32(unsigned long field)
520{
521 return vmcs_readl(field);
522}
523
524static u64 vmcs_read64(unsigned long field)
525{
05b3e0c2 526#ifdef CONFIG_X86_64
6aa8b732
AK		 527 return vmcs_readl(field);
528#else
529 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
530#endif
531}
532
e52de1b8
AK		 533static noinline void vmwrite_error(unsigned long field, unsigned long value)
534{
535 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
536 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
537 dump_stack();
538}
539
6aa8b732
AK		 540static void vmcs_writel(unsigned long field, unsigned long value)
541{
542 u8 error;
543
4ecac3fd 544 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 545 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 546 if (unlikely(error))
547 vmwrite_error(field, value);
6aa8b732
AK		 548}
549
550static void vmcs_write16(unsigned long field, u16 value)
551{
552 vmcs_writel(field, value);
553}
554
555static void vmcs_write32(unsigned long field, u32 value)
556{
557 vmcs_writel(field, value);
558}
559
560static void vmcs_write64(unsigned long field, u64 value)
561{
6aa8b732 562 vmcs_writel(field, value);
7682f2d0 563#ifndef CONFIG_X86_64
6aa8b732
AK		 564 asm volatile ("");
565 vmcs_writel(field+1, value >> 32);
566#endif
567}
568
2ab455cc
AL		 569static void vmcs_clear_bits(unsigned long field, u32 mask)
570{
571 vmcs_writel(field, vmcs_readl(field) & ~mask);
572}
573
574static void vmcs_set_bits(unsigned long field, u32 mask)
575{
576 vmcs_writel(field, vmcs_readl(field) | mask);
577}
578
abd3f2d6
AK		 579static void update_exception_bitmap(struct kvm_vcpu *vcpu)
580{
581 u32 eb;
582
fd7373cc
JK		 583 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
584 (1u << NM_VECTOR) | (1u << DB_VECTOR);
585 if ((vcpu->guest_debug &
586 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
587 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
588 eb |= 1u << BP_VECTOR;
7ffd92c5 589 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 590 eb = ~0;
089d034e 591 if (enable_ept)
1439442c 592 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 593 if (vcpu->fpu_active)
594 eb &= ~(1u << NM_VECTOR);
abd3f2d6
AK		 595 vmcs_write32(EXCEPTION_BITMAP, eb);
596}
597
33ed6329
AK		 598static void reload_tss(void)
599{
33ed6329
AK		 600 /*
601 * VT restores TR but not its size. Useless.
602 */
603 struct descriptor_table gdt;
a5f61300 604 struct desc_struct *descs;
33ed6329 605
d6e88aec 606 kvm_get_gdt(&gdt);
33ed6329
AK		 607 descs = (void *)gdt.base;
608 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
609 load_TR_desc();
33ed6329
AK		 610}
611
92c0d900 612static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 613{
3a34a881 614 u64 guest_efer;
51c6cf66
AK		 615 u64 ignore_bits;
616
f6801dff 617 guest_efer = vmx->vcpu.arch.efer;
3a34a881 618
51c6cf66
AK		 619 /*
620 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
621 * outside long mode
622 */
623 ignore_bits = EFER_NX | EFER_SCE;
624#ifdef CONFIG_X86_64
625 ignore_bits |= EFER_LMA | EFER_LME;
626 /* SCE is meaningful only in long mode on Intel */
627 if (guest_efer & EFER_LMA)
628 ignore_bits &= ~(u64)EFER_SCE;
629#endif
51c6cf66
AK		 630 guest_efer &= ~ignore_bits;
631 guest_efer |= host_efer & ignore_bits;
26bb0981 632 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 633 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
26bb0981 634 return true;
51c6cf66
AK		 635}
636
04d2cc77 637static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 638{
04d2cc77 639 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 640 int i;
04d2cc77 641
a2fa3e9f 642 if (vmx->host_state.loaded)
33ed6329
AK		 643 return;
644
a2fa3e9f 645 vmx->host_state.loaded = 1;
33ed6329
AK		 646 /*
647 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
648 * allow segment selectors with cpl > 0 or ti == 1.
649 */
d6e88aec 650 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 651 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
d6e88aec 652 vmx->host_state.fs_sel = kvm_read_fs();
152d3f2f 653 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 654 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 655 vmx->host_state.fs_reload_needed = 0;
656 } else {
33ed6329 657 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 658 vmx->host_state.fs_reload_needed = 1;
33ed6329 659 }
d6e88aec 660 vmx->host_state.gs_sel = kvm_read_gs();
a2fa3e9f
GH		 661 if (!(vmx->host_state.gs_sel & 7))
662 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 663 else {
664 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 665 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 666 }
667
668#ifdef CONFIG_X86_64
669 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
670 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
671#else
a2fa3e9f
GH		 672 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
673 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 674#endif
707c0874
AK		 675
676#ifdef CONFIG_X86_64
44ea2b17
AK		 677 if (is_long_mode(&vmx->vcpu)) {
678 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
679 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
680 }
707c0874 681#endif
26bb0981
AK		 682 for (i = 0; i < vmx->save_nmsrs; ++i)
683 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 684 vmx->guest_msrs[i].data,
685 vmx->guest_msrs[i].mask);
33ed6329
AK		 686}
687
a9b21b62 688static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 689{
15ad7146 690 unsigned long flags;
33ed6329 691
a2fa3e9f 692 if (!vmx->host_state.loaded)
33ed6329
AK		 693 return;
694
e1beb1d3 695 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 696 vmx->host_state.loaded = 0;
152d3f2f 697 if (vmx->host_state.fs_reload_needed)
d6e88aec 698 kvm_load_fs(vmx->host_state.fs_sel);
152d3f2f 699 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 700 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329
AK		 701 /*
702 * If we have to reload gs, we must take care to
703 * preserve our gs base.
704 */
15ad7146 705 local_irq_save(flags);
d6e88aec 706 kvm_load_gs(vmx->host_state.gs_sel);
33ed6329
AK		 707#ifdef CONFIG_X86_64
708 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
709#endif
15ad7146 710 local_irq_restore(flags);
33ed6329 711 }
152d3f2f 712 reload_tss();
44ea2b17
AK		 713#ifdef CONFIG_X86_64
714 if (is_long_mode(&vmx->vcpu)) {
715 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
716 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
717 }
718#endif
33ed6329
AK		 719}
720
a9b21b62
AK		 721static void vmx_load_host_state(struct vcpu_vmx *vmx)
722{
723 preempt_disable();
724 __vmx_load_host_state(vmx);
725 preempt_enable();
726}
727
6aa8b732
AK		 728/*
729 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
730 * vcpu mutex is already taken.
731 */
15ad7146 732static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 733{
a2fa3e9f
GH		 734 struct vcpu_vmx *vmx = to_vmx(vcpu);
735 u64 phys_addr = __pa(vmx->vmcs);
019960ae 736 u64 tsc_this, delta, new_offset;
6aa8b732 737
a3d7f85f 738 if (vcpu->cpu != cpu) {
8b9cf98c 739 vcpu_clear(vmx);
2f599714 740 kvm_migrate_timers(vcpu);
eb5109e3 741 set_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests);
543e4243
AK		 742 local_irq_disable();
743 list_add(&vmx->local_vcpus_link,
744 &per_cpu(vcpus_on_cpu, cpu));
745 local_irq_enable();
a3d7f85f 746 }
6aa8b732 747
a2fa3e9f 748 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
6aa8b732
AK		 749 u8 error;
750
a2fa3e9f 751 per_cpu(current_vmcs, cpu) = vmx->vmcs;
4ecac3fd 752 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
6aa8b732
AK		 753 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
754 : "cc");
755 if (error)
756 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
a2fa3e9f 757 vmx->vmcs, phys_addr);
6aa8b732
AK		 758 }
759
760 if (vcpu->cpu != cpu) {
761 struct descriptor_table dt;
762 unsigned long sysenter_esp;
763
764 vcpu->cpu = cpu;
765 /*
766 * Linux uses per-cpu TSS and GDT, so set these when switching
767 * processors.
768 */
d6e88aec
AK		 769 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
770 kvm_get_gdt(&dt);
6aa8b732
AK		 771 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
772
773 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
774 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
7700270e
AK		 775
776 /*
777 * Make sure the time stamp counter is monotonous.
778 */
779 rdtscll(tsc_this);
019960ae
AK		 780 if (tsc_this < vcpu->arch.host_tsc) {
781 delta = vcpu->arch.host_tsc - tsc_this;
782 new_offset = vmcs_read64(TSC_OFFSET) + delta;
783 vmcs_write64(TSC_OFFSET, new_offset);
784 }
6aa8b732 785 }
6aa8b732
AK		 786}
787
788static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
789{
a9b21b62 790 __vmx_load_host_state(to_vmx(vcpu));
6aa8b732
AK		 791}
792
5fd86fcf
AK		 793static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
794{
81231c69
AK		 795 ulong cr0;
796
5fd86fcf
AK		 797 if (vcpu->fpu_active)
798 return;
799 vcpu->fpu_active = 1;
81231c69
AK		 800 cr0 = vmcs_readl(GUEST_CR0);
801 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
802 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
803 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 804 update_exception_bitmap(vcpu);
edcafe3c
AK		 805 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
806 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 807}
808
edcafe3c
AK		 809static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
810
5fd86fcf
AK		 811static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
812{
edcafe3c 813 vmx_decache_cr0_guest_bits(vcpu);
81231c69 814 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 815 update_exception_bitmap(vcpu);
edcafe3c
AK		 816 vcpu->arch.cr0_guest_owned_bits = 0;
817 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
818 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 819}
820
6aa8b732
AK		 821static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
822{
78ac8b47 823 unsigned long rflags, save_rflags;
345dcaa8
AK		 824
825 rflags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 826 if (to_vmx(vcpu)->rmode.vm86_active) {
827 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
828 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
829 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
830 }
345dcaa8 831 return rflags;
6aa8b732
AK		 832}
833
834static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
835{
78ac8b47
AK		 836 if (to_vmx(vcpu)->rmode.vm86_active) {
837 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 838 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 839 }
6aa8b732
AK		 840 vmcs_writel(GUEST_RFLAGS, rflags);
841}
842
2809f5d2
GC		 843static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
844{
845 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
846 int ret = 0;
847
848 if (interruptibility & GUEST_INTR_STATE_STI)
849 ret |= X86_SHADOW_INT_STI;
850 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
851 ret |= X86_SHADOW_INT_MOV_SS;
852
853 return ret & mask;
854}
855
856static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
857{
858 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
859 u32 interruptibility = interruptibility_old;
860
861 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
862
863 if (mask & X86_SHADOW_INT_MOV_SS)
864 interruptibility |= GUEST_INTR_STATE_MOV_SS;
865 if (mask & X86_SHADOW_INT_STI)
866 interruptibility |= GUEST_INTR_STATE_STI;
867
868 if ((interruptibility != interruptibility_old))
869 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
870}
871
6aa8b732
AK		 872static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
873{
874 unsigned long rip;
6aa8b732 875
5fdbf976 876 rip = kvm_rip_read(vcpu);
6aa8b732 877 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 878 kvm_rip_write(vcpu, rip);
6aa8b732 879
2809f5d2
GC		 880 /* skipping an emulated instruction also counts */
881 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 882}
883
298101da
AK		 884static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
885 bool has_error_code, u32 error_code)
886{
77ab6db0 887 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 888 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 889
8ab2d2e2 890 if (has_error_code) {
77ab6db0 891 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 892 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
893 }
77ab6db0 894
7ffd92c5 895 if (vmx->rmode.vm86_active) {
77ab6db0
JK		 896 vmx->rmode.irq.pending = true;
897 vmx->rmode.irq.vector = nr;
898 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
ae0bb3e0
GN		 899 if (kvm_exception_is_soft(nr))
900 vmx->rmode.irq.rip +=
901 vmx->vcpu.arch.event_exit_inst_len;
8ab2d2e2
JK		 902 intr_info |= INTR_TYPE_SOFT_INTR;
903 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
77ab6db0
JK		 904 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
905 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
906 return;
907 }
908
66fd3f7f
GN		 909 if (kvm_exception_is_soft(nr)) {
910 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
911 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 912 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
913 } else
914 intr_info |= INTR_TYPE_HARD_EXCEPTION;
915
916 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 917}
918
4e47c7a6
SY		 919static bool vmx_rdtscp_supported(void)
920{
921 return cpu_has_vmx_rdtscp();
922}
923
a75beee6
ED		 924/*
925 * Swap MSR entry in host/guest MSR entry array.
926 */
8b9cf98c 927static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 928{
26bb0981 929 struct shared_msr_entry tmp;
a2fa3e9f
GH		 930
931 tmp = vmx->guest_msrs[to];
932 vmx->guest_msrs[to] = vmx->guest_msrs[from];
933 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 934}
935
e38aea3e
AK		 936/*
937 * Set up the vmcs to automatically save and restore system
938 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
939 * mode, as fiddling with msrs is very expensive.
940 */
8b9cf98c 941static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 942{
26bb0981 943 int save_nmsrs, index;
5897297b 944 unsigned long *msr_bitmap;
e38aea3e 945
33f9c505 946 vmx_load_host_state(vmx);
a75beee6
ED		 947 save_nmsrs = 0;
948#ifdef CONFIG_X86_64
8b9cf98c 949 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 950 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 951 if (index >= 0)
8b9cf98c
RR		 952 move_msr_up(vmx, index, save_nmsrs++);
953 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 954 if (index >= 0)
8b9cf98c
RR		 955 move_msr_up(vmx, index, save_nmsrs++);
956 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 957 if (index >= 0)
8b9cf98c 958 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 959 index = __find_msr_index(vmx, MSR_TSC_AUX);
960 if (index >= 0 && vmx->rdtscp_enabled)
961 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 962 /*
963 * MSR_K6_STAR is only needed on long mode guests, and only
964 * if efer.sce is enabled.
965 */
8b9cf98c 966 index = __find_msr_index(vmx, MSR_K6_STAR);
f6801dff 967 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 968 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 969 }
970#endif
92c0d900
AK		 971 index = __find_msr_index(vmx, MSR_EFER);
972 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 973 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 974
26bb0981 975 vmx->save_nmsrs = save_nmsrs;
5897297b
AK		 976
977 if (cpu_has_vmx_msr_bitmap()) {
978 if (is_long_mode(&vmx->vcpu))
979 msr_bitmap = vmx_msr_bitmap_longmode;
980 else
981 msr_bitmap = vmx_msr_bitmap_legacy;
982
983 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
984 }
e38aea3e
AK		 985}
986
6aa8b732
AK		 987/*
988 * reads and returns guest's timestamp counter "register"
989 * guest_tsc = host_tsc + tsc_offset -- 21.3
990 */
991static u64 guest_read_tsc(void)
992{
993 u64 host_tsc, tsc_offset;
994
995 rdtscll(host_tsc);
996 tsc_offset = vmcs_read64(TSC_OFFSET);
997 return host_tsc + tsc_offset;
998}
999
1000/*
1001 * writes 'guest_tsc' into guest's timestamp counter "register"
1002 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
1003 */
53f658b3 1004static void guest_write_tsc(u64 guest_tsc, u64 host_tsc)
6aa8b732 1005{
6aa8b732
AK		 1006 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
1007}
1008
6aa8b732
AK		 1009/*
1010 * Reads an msr value (of 'msr_index') into 'pdata'.
1011 * Returns 0 on success, non-0 otherwise.
1012 * Assumes vcpu_load() was already called.
1013 */
1014static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1015{
1016 u64 data;
26bb0981 1017 struct shared_msr_entry *msr;
6aa8b732
AK		 1018
1019 if (!pdata) {
1020 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1021 return -EINVAL;
1022 }
1023
1024 switch (msr_index) {
05b3e0c2 1025#ifdef CONFIG_X86_64
6aa8b732
AK		 1026 case MSR_FS_BASE:
1027 data = vmcs_readl(GUEST_FS_BASE);
1028 break;
1029 case MSR_GS_BASE:
1030 data = vmcs_readl(GUEST_GS_BASE);
1031 break;
44ea2b17
AK		 1032 case MSR_KERNEL_GS_BASE:
1033 vmx_load_host_state(to_vmx(vcpu));
1034 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1035 break;
26bb0981 1036#endif
6aa8b732 1037 case MSR_EFER:
3bab1f5d 1038 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 1039 case MSR_IA32_TSC:
6aa8b732
AK		 1040 data = guest_read_tsc();
1041 break;
1042 case MSR_IA32_SYSENTER_CS:
1043 data = vmcs_read32(GUEST_SYSENTER_CS);
1044 break;
1045 case MSR_IA32_SYSENTER_EIP:
f5b42c33 1046 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 1047 break;
1048 case MSR_IA32_SYSENTER_ESP:
f5b42c33 1049 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 1050 break;
4e47c7a6
SY		 1051 case MSR_TSC_AUX:
1052 if (!to_vmx(vcpu)->rdtscp_enabled)
1053 return 1;
1054 /* Otherwise falls through */
6aa8b732 1055 default:
26bb0981 1056 vmx_load_host_state(to_vmx(vcpu));
8b9cf98c 1057 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d 1058 if (msr) {
542423b0 1059 vmx_load_host_state(to_vmx(vcpu));
3bab1f5d
AK		 1060 data = msr->data;
1061 break;
6aa8b732 1062 }
3bab1f5d 1063 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 1064 }
1065
1066 *pdata = data;
1067 return 0;
1068}
1069
1070/*
1071 * Writes msr value into into the appropriate "register".
1072 * Returns 0 on success, non-0 otherwise.
1073 * Assumes vcpu_load() was already called.
1074 */
1075static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1076{
a2fa3e9f 1077 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1078 struct shared_msr_entry *msr;
53f658b3 1079 u64 host_tsc;
2cc51560
ED		 1080 int ret = 0;
1081
6aa8b732 1082 switch (msr_index) {
3bab1f5d 1083 case MSR_EFER:
a9b21b62 1084 vmx_load_host_state(vmx);
2cc51560 1085 ret = kvm_set_msr_common(vcpu, msr_index, data);
2cc51560 1086 break;
16175a79 1087#ifdef CONFIG_X86_64
6aa8b732
AK		 1088 case MSR_FS_BASE:
1089 vmcs_writel(GUEST_FS_BASE, data);
1090 break;
1091 case MSR_GS_BASE:
1092 vmcs_writel(GUEST_GS_BASE, data);
1093 break;
44ea2b17
AK		 1094 case MSR_KERNEL_GS_BASE:
1095 vmx_load_host_state(vmx);
1096 vmx->msr_guest_kernel_gs_base = data;
1097 break;
6aa8b732
AK		 1098#endif
1099 case MSR_IA32_SYSENTER_CS:
1100 vmcs_write32(GUEST_SYSENTER_CS, data);
1101 break;
1102 case MSR_IA32_SYSENTER_EIP:
f5b42c33 1103 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 1104 break;
1105 case MSR_IA32_SYSENTER_ESP:
f5b42c33 1106 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 1107 break;
af24a4e4 1108 case MSR_IA32_TSC:
53f658b3
MT		 1109 rdtscll(host_tsc);
1110 guest_write_tsc(data, host_tsc);
6aa8b732 1111 break;
468d472f
SY		 1112 case MSR_IA32_CR_PAT:
1113 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1114 vmcs_write64(GUEST_IA32_PAT, data);
1115 vcpu->arch.pat = data;
1116 break;
1117 }
4e47c7a6
SY		 1118 ret = kvm_set_msr_common(vcpu, msr_index, data);
1119 break;
1120 case MSR_TSC_AUX:
1121 if (!vmx->rdtscp_enabled)
1122 return 1;
1123 /* Check reserved bit, higher 32 bits should be zero */
1124 if ((data >> 32) != 0)
1125 return 1;
1126 /* Otherwise falls through */
6aa8b732 1127 default:
8b9cf98c 1128 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 1129 if (msr) {
542423b0 1130 vmx_load_host_state(vmx);
3bab1f5d
AK		 1131 msr->data = data;
1132 break;
6aa8b732 1133 }
2cc51560 1134 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 1135 }
1136
2cc51560 1137 return ret;
6aa8b732
AK		 1138}
1139
5fdbf976 1140static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 1141{
5fdbf976
MT		 1142 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1143 switch (reg) {
1144 case VCPU_REGS_RSP:
1145 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1146 break;
1147 case VCPU_REGS_RIP:
1148 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1149 break;
6de4f3ad
AK		 1150 case VCPU_EXREG_PDPTR:
1151 if (enable_ept)
1152 ept_save_pdptrs(vcpu);
1153 break;
5fdbf976
MT		 1154 default:
1155 break;
1156 }
6aa8b732
AK		 1157}
1158
355be0b9 1159static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
6aa8b732 1160{
ae675ef0
JK		 1161 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1162 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1163 else
1164 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1165
abd3f2d6 1166 update_exception_bitmap(vcpu);
6aa8b732
AK		 1167}
1168
1169static __init int cpu_has_kvm_support(void)
1170{
6210e37b 1171 return cpu_has_vmx();
6aa8b732
AK		 1172}
1173
1174static __init int vmx_disabled_by_bios(void)
1175{
1176 u64 msr;
1177
1178 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
9ea542fa
SY		 1179 return (msr & (FEATURE_CONTROL_LOCKED |
1180 FEATURE_CONTROL_VMXON_ENABLED))
1181 == FEATURE_CONTROL_LOCKED;
62b3ffb8 1182 /* locked but not enabled */
6aa8b732
AK		 1183}
1184
10474ae8 1185static int hardware_enable(void *garbage)
6aa8b732
AK		 1186{
1187 int cpu = raw_smp_processor_id();
1188 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1189 u64 old;
1190
10474ae8
AG		 1191 if (read_cr4() & X86_CR4_VMXE)
1192 return -EBUSY;
1193
543e4243 1194 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
6aa8b732 1195 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
9ea542fa
SY		 1196 if ((old & (FEATURE_CONTROL_LOCKED |
1197 FEATURE_CONTROL_VMXON_ENABLED))
1198 != (FEATURE_CONTROL_LOCKED |
1199 FEATURE_CONTROL_VMXON_ENABLED))
6aa8b732 1200 /* enable and lock */
62b3ffb8 1201 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
9ea542fa
SY		 1202 FEATURE_CONTROL_LOCKED |
1203 FEATURE_CONTROL_VMXON_ENABLED);
66aee91a 1204 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
4ecac3fd
AK		 1205 asm volatile (ASM_VMX_VMXON_RAX
1206 : : "a"(&phys_addr), "m"(phys_addr)
6aa8b732 1207 : "memory", "cc");
10474ae8
AG		 1208
1209 ept_sync_global();
1210
1211 return 0;
6aa8b732
AK		 1212}
1213
543e4243
AK		 1214static void vmclear_local_vcpus(void)
1215{
1216 int cpu = raw_smp_processor_id();
1217 struct vcpu_vmx *vmx, *n;
1218
1219 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1220 local_vcpus_link)
1221 __vcpu_clear(vmx);
1222}
1223
710ff4a8
EH		 1224
1225/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1226 * tricks.
1227 */
1228static void kvm_cpu_vmxoff(void)
6aa8b732 1229{
4ecac3fd 1230 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
e693d71b 1231 write_cr4(read_cr4() & ~X86_CR4_VMXE);
6aa8b732
AK		 1232}
1233
710ff4a8
EH		 1234static void hardware_disable(void *garbage)
1235{
1236 vmclear_local_vcpus();
1237 kvm_cpu_vmxoff();
1238}
1239
1c3d14fe 1240static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 1241 u32 msr, u32 *result)
1c3d14fe
YS		 1242{
1243 u32 vmx_msr_low, vmx_msr_high;
1244 u32 ctl = ctl_min | ctl_opt;
1245
1246 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1247
1248 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1249 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1250
1251 /* Ensure minimum (required) set of control bits are supported. */
1252 if (ctl_min & ~ctl)
002c7f7c 1253 return -EIO;
1c3d14fe
YS		 1254
1255 *result = ctl;
1256 return 0;
1257}
1258
002c7f7c 1259static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 1260{
1261 u32 vmx_msr_low, vmx_msr_high;
d56f546d 1262 u32 min, opt, min2, opt2;
1c3d14fe
YS		 1263 u32 _pin_based_exec_control = 0;
1264 u32 _cpu_based_exec_control = 0;
f78e0e2e 1265 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 1266 u32 _vmexit_control = 0;
1267 u32 _vmentry_control = 0;
1268
1269 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
f08864b4 1270 opt = PIN_BASED_VIRTUAL_NMIS;
1c3d14fe
YS		 1271 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1272 &_pin_based_exec_control) < 0)
002c7f7c 1273 return -EIO;
1c3d14fe
YS		 1274
1275 min = CPU_BASED_HLT_EXITING |
1276#ifdef CONFIG_X86_64
1277 CPU_BASED_CR8_LOAD_EXITING |
1278 CPU_BASED_CR8_STORE_EXITING |
1279#endif
d56f546d
SY		 1280 CPU_BASED_CR3_LOAD_EXITING |
1281 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 1282 CPU_BASED_USE_IO_BITMAPS |
1283 CPU_BASED_MOV_DR_EXITING |
a7052897 1284 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 1285 CPU_BASED_MWAIT_EXITING |
1286 CPU_BASED_MONITOR_EXITING |
a7052897 1287 CPU_BASED_INVLPG_EXITING;
f78e0e2e 1288 opt = CPU_BASED_TPR_SHADOW |
25c5f225 1289 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 1290 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 1291 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1292 &_cpu_based_exec_control) < 0)
002c7f7c 1293 return -EIO;
6e5d865c
YS		 1294#ifdef CONFIG_X86_64
1295 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1296 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1297 ~CPU_BASED_CR8_STORE_EXITING;
1298#endif
f78e0e2e 1299 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 1300 min2 = 0;
1301 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2384d2b3 1302 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 1303 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 1304 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 1305 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6
SY		 1306 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
1307 SECONDARY_EXEC_RDTSCP;
d56f546d
SY		 1308 if (adjust_vmx_controls(min2, opt2,
1309 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 1310 &_cpu_based_2nd_exec_control) < 0)
1311 return -EIO;
1312 }
1313#ifndef CONFIG_X86_64
1314 if (!(_cpu_based_2nd_exec_control &
1315 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1316 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1317#endif
d56f546d 1318 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 1319 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1320 enabled */
5fff7d27
GN		 1321 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1322 CPU_BASED_CR3_STORE_EXITING |
1323 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 1324 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1325 vmx_capability.ept, vmx_capability.vpid);
1326 }
1c3d14fe
YS		 1327
1328 min = 0;
1329#ifdef CONFIG_X86_64
1330 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1331#endif
468d472f 1332 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1c3d14fe
YS		 1333 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1334 &_vmexit_control) < 0)
002c7f7c 1335 return -EIO;
1c3d14fe 1336
468d472f
SY		 1337 min = 0;
1338 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 1339 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1340 &_vmentry_control) < 0)
002c7f7c 1341 return -EIO;
6aa8b732 1342
c68876fd 1343 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 1344
1345 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1346 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 1347 return -EIO;
1c3d14fe
YS		 1348
1349#ifdef CONFIG_X86_64
1350 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1351 if (vmx_msr_high & (1u<<16))
002c7f7c 1352 return -EIO;
1c3d14fe
YS		 1353#endif
1354
1355 /* Require Write-Back (WB) memory type for VMCS accesses. */
1356 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 1357 return -EIO;
1c3d14fe 1358
002c7f7c
YS		 1359 vmcs_conf->size = vmx_msr_high & 0x1fff;
1360 vmcs_conf->order = get_order(vmcs_config.size);
1361 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 1362
002c7f7c
YS		 1363 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1364 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 1365 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 1366 vmcs_conf->vmexit_ctrl = _vmexit_control;
1367 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe
YS		 1368
1369 return 0;
c68876fd 1370}
6aa8b732
AK		 1371
1372static struct vmcs *alloc_vmcs_cpu(int cpu)
1373{
1374 int node = cpu_to_node(cpu);
1375 struct page *pages;
1376 struct vmcs *vmcs;
1377
6484eb3e 1378 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 1379 if (!pages)
1380 return NULL;
1381 vmcs = page_address(pages);
1c3d14fe
YS		 1382 memset(vmcs, 0, vmcs_config.size);
1383 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 1384 return vmcs;
1385}
1386
1387static struct vmcs *alloc_vmcs(void)
1388{
d3b2c338 1389 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 1390}
1391
1392static void free_vmcs(struct vmcs *vmcs)
1393{
1c3d14fe 1394 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 1395}
1396
39959588 1397static void free_kvm_area(void)
6aa8b732
AK		 1398{
1399 int cpu;
1400
3230bb47 1401 for_each_possible_cpu(cpu) {
6aa8b732 1402 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 1403 per_cpu(vmxarea, cpu) = NULL;
1404 }
6aa8b732
AK		 1405}
1406
6aa8b732
AK		 1407static __init int alloc_kvm_area(void)
1408{
1409 int cpu;
1410
3230bb47 1411 for_each_possible_cpu(cpu) {
6aa8b732
AK		 1412 struct vmcs *vmcs;
1413
1414 vmcs = alloc_vmcs_cpu(cpu);
1415 if (!vmcs) {
1416 free_kvm_area();
1417 return -ENOMEM;
1418 }
1419
1420 per_cpu(vmxarea, cpu) = vmcs;
1421 }
1422 return 0;
1423}
1424
1425static __init int hardware_setup(void)
1426{
002c7f7c
YS		 1427 if (setup_vmcs_config(&vmcs_config) < 0)
1428 return -EIO;
50a37eb4
JR		 1429
1430 if (boot_cpu_has(X86_FEATURE_NX))
1431 kvm_enable_efer_bits(EFER_NX);
1432
93ba03c2
SY		 1433 if (!cpu_has_vmx_vpid())
1434 enable_vpid = 0;
1435
3a624e29 1436 if (!cpu_has_vmx_ept()) {
93ba03c2 1437 enable_ept = 0;
3a624e29
NK		 1438 enable_unrestricted_guest = 0;
1439 }
1440
1441 if (!cpu_has_vmx_unrestricted_guest())
1442 enable_unrestricted_guest = 0;
93ba03c2
SY		 1443
1444 if (!cpu_has_vmx_flexpriority())
1445 flexpriority_enabled = 0;
1446
95ba8273
GN		 1447 if (!cpu_has_vmx_tpr_shadow())
1448 kvm_x86_ops->update_cr8_intercept = NULL;
1449
54dee993
MT		 1450 if (enable_ept && !cpu_has_vmx_ept_2m_page())
1451 kvm_disable_largepages();
1452
4b8d54f9
ZE		 1453 if (!cpu_has_vmx_ple())
1454 ple_gap = 0;
1455
6aa8b732
AK		 1456 return alloc_kvm_area();
1457}
1458
1459static __exit void hardware_unsetup(void)
1460{
1461 free_kvm_area();
1462}
1463
6aa8b732
AK		 1464static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1465{
1466 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1467
6af11b9e 1468 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 1469 vmcs_write16(sf->selector, save->selector);
1470 vmcs_writel(sf->base, save->base);
1471 vmcs_write32(sf->limit, save->limit);
1472 vmcs_write32(sf->ar_bytes, save->ar);
1473 } else {
1474 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1475 << AR_DPL_SHIFT;
1476 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1477 }
1478}
1479
1480static void enter_pmode(struct kvm_vcpu *vcpu)
1481{
1482 unsigned long flags;
a89a8fb9 1483 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1484
a89a8fb9 1485 vmx->emulation_required = 1;
7ffd92c5 1486 vmx->rmode.vm86_active = 0;
6aa8b732 1487
7ffd92c5
AK		 1488 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1489 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1490 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
6aa8b732
AK		 1491
1492 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 1493 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1494 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 1495 vmcs_writel(GUEST_RFLAGS, flags);
1496
66aee91a
RR		 1497 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1498 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 1499
1500 update_exception_bitmap(vcpu);
1501
a89a8fb9
MG		 1502 if (emulate_invalid_guest_state)
1503 return;
1504
7ffd92c5
AK		 1505 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1506 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1507 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1508 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
6aa8b732
AK		 1509
1510 vmcs_write16(GUEST_SS_SELECTOR, 0);
1511 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1512
1513 vmcs_write16(GUEST_CS_SELECTOR,
1514 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1515 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1516}
1517
d77c26fc 1518static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 1519{
bfc6d222 1520 if (!kvm->arch.tss_addr) {
bc6678a3
MT		 1521 struct kvm_memslots *slots;
1522 gfn_t base_gfn;
1523
1524 slots = rcu_dereference(kvm->memslots);
1525 base_gfn = kvm->memslots->memslots[0].base_gfn +
46a26bf5 1526 kvm->memslots->memslots[0].npages - 3;
cbc94022
IE		 1527 return base_gfn << PAGE_SHIFT;
1528 }
bfc6d222 1529 return kvm->arch.tss_addr;
6aa8b732
AK		 1530}
1531
1532static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1533{
1534 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1535
1536 save->selector = vmcs_read16(sf->selector);
1537 save->base = vmcs_readl(sf->base);
1538 save->limit = vmcs_read32(sf->limit);
1539 save->ar = vmcs_read32(sf->ar_bytes);
15b00f32
JK		 1540 vmcs_write16(sf->selector, save->base >> 4);
1541 vmcs_write32(sf->base, save->base & 0xfffff);
6aa8b732
AK		 1542 vmcs_write32(sf->limit, 0xffff);
1543 vmcs_write32(sf->ar_bytes, 0xf3);
1544}
1545
1546static void enter_rmode(struct kvm_vcpu *vcpu)
1547{
1548 unsigned long flags;
a89a8fb9 1549 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1550
3a624e29
NK		 1551 if (enable_unrestricted_guest)
1552 return;
1553
a89a8fb9 1554 vmx->emulation_required = 1;
7ffd92c5 1555 vmx->rmode.vm86_active = 1;
6aa8b732 1556
7ffd92c5 1557 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
6aa8b732
AK		 1558 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1559
7ffd92c5 1560 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
6aa8b732
AK		 1561 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1562
7ffd92c5 1563 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
6aa8b732
AK		 1564 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1565
1566 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 1567 vmx->rmode.save_rflags = flags;
6aa8b732 1568
053de044 1569 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 1570
1571 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 1572 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 1573 update_exception_bitmap(vcpu);
1574
a89a8fb9
MG		 1575 if (emulate_invalid_guest_state)
1576 goto continue_rmode;
1577
6aa8b732
AK		 1578 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1579 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1580 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1581
1582 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 1583 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
8cb5b033
AK		 1584 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1585 vmcs_writel(GUEST_CS_BASE, 0xf0000);
6aa8b732
AK		 1586 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1587
7ffd92c5
AK		 1588 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1589 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1590 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1591 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
75880a01 1592
a89a8fb9 1593continue_rmode:
8668a3c4 1594 kvm_mmu_reset_context(vcpu);
b7ebfb05 1595 init_rmode(vcpu->kvm);
6aa8b732
AK		 1596}
1597
401d10de
AS		 1598static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1599{
1600 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 1601 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1602
1603 if (!msr)
1604 return;
401d10de 1605
44ea2b17
AK		 1606 /*
1607 * Force kernel_gs_base reloading before EFER changes, as control
1608 * of this msr depends on is_long_mode().
1609 */
1610 vmx_load_host_state(to_vmx(vcpu));
f6801dff 1611 vcpu->arch.efer = efer;
401d10de
AS		 1612 if (efer & EFER_LMA) {
1613 vmcs_write32(VM_ENTRY_CONTROLS,
1614 vmcs_read32(VM_ENTRY_CONTROLS) |
1615 VM_ENTRY_IA32E_MODE);
1616 msr->data = efer;
1617 } else {
1618 vmcs_write32(VM_ENTRY_CONTROLS,
1619 vmcs_read32(VM_ENTRY_CONTROLS) &
1620 ~VM_ENTRY_IA32E_MODE);
1621
1622 msr->data = efer & ~EFER_LME;
1623 }
1624 setup_msrs(vmx);
1625}
1626
05b3e0c2 1627#ifdef CONFIG_X86_64
6aa8b732
AK		 1628
1629static void enter_lmode(struct kvm_vcpu *vcpu)
1630{
1631 u32 guest_tr_ar;
1632
1633 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1634 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1635 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
b8688d51 1636 __func__);
6aa8b732
AK		 1637 vmcs_write32(GUEST_TR_AR_BYTES,
1638 (guest_tr_ar & ~AR_TYPE_MASK)
1639 | AR_TYPE_BUSY_64_TSS);
1640 }
f6801dff
AK		 1641 vcpu->arch.efer |= EFER_LMA;
1642 vmx_set_efer(vcpu, vcpu->arch.efer);
6aa8b732
AK		 1643}
1644
1645static void exit_lmode(struct kvm_vcpu *vcpu)
1646{
f6801dff 1647 vcpu->arch.efer &= ~EFER_LMA;
6aa8b732
AK		 1648
1649 vmcs_write32(VM_ENTRY_CONTROLS,
1650 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 1651 & ~VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1652}
1653
1654#endif
1655
2384d2b3
SY		 1656static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1657{
1658 vpid_sync_vcpu_all(to_vmx(vcpu));
089d034e 1659 if (enable_ept)
4e1096d2 1660 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
2384d2b3
SY		 1661}
1662
e8467fda
AK		 1663static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1664{
1665 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
1666
1667 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
1668 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
1669}
1670
25c4c276 1671static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 1672{
fc78f519
AK		 1673 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
1674
1675 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
1676 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 1677}
1678
1439442c
SY		 1679static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1680{
6de4f3ad
AK		 1681 if (!test_bit(VCPU_EXREG_PDPTR,
1682 (unsigned long *)&vcpu->arch.regs_dirty))
1683 return;
1684
1439442c 1685 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1439442c
SY		 1686 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1687 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1688 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1689 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1690 }
1691}
1692
8f5d549f
AK		 1693static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1694{
1695 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1696 vcpu->arch.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1697 vcpu->arch.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1698 vcpu->arch.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1699 vcpu->arch.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
1700 }
6de4f3ad
AK		 1701
1702 __set_bit(VCPU_EXREG_PDPTR,
1703 (unsigned long *)&vcpu->arch.regs_avail);
1704 __set_bit(VCPU_EXREG_PDPTR,
1705 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 1706}
1707
1439442c
SY		 1708static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1709
1710static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1711 unsigned long cr0,
1712 struct kvm_vcpu *vcpu)
1713{
1714 if (!(cr0 & X86_CR0_PG)) {
1715 /* From paging/starting to nonpaging */
1716 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1717 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 1718 (CPU_BASED_CR3_LOAD_EXITING |
1719 CPU_BASED_CR3_STORE_EXITING));
1720 vcpu->arch.cr0 = cr0;
fc78f519 1721 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 1722 } else if (!is_paging(vcpu)) {
1723 /* From nonpaging to paging */
1724 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1725 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 1726 ~(CPU_BASED_CR3_LOAD_EXITING |
1727 CPU_BASED_CR3_STORE_EXITING));
1728 vcpu->arch.cr0 = cr0;
fc78f519 1729 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 1730 }
95eb84a7
SY		 1731
1732 if (!(cr0 & X86_CR0_WP))
1733 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 1734}
1735
6aa8b732
AK		 1736static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1737{
7ffd92c5 1738 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 1739 unsigned long hw_cr0;
1740
1741 if (enable_unrestricted_guest)
1742 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1743 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1744 else
1745 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1439442c 1746
7ffd92c5 1747 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 1748 enter_pmode(vcpu);
1749
7ffd92c5 1750 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 1751 enter_rmode(vcpu);
1752
05b3e0c2 1753#ifdef CONFIG_X86_64
f6801dff 1754 if (vcpu->arch.efer & EFER_LME) {
707d92fa 1755 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 1756 enter_lmode(vcpu);
707d92fa 1757 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 1758 exit_lmode(vcpu);
1759 }
1760#endif
1761
089d034e 1762 if (enable_ept)
1439442c
SY		 1763 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1764
02daab21 1765 if (!vcpu->fpu_active)
81231c69 1766 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 1767
6aa8b732 1768 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 1769 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 1770 vcpu->arch.cr0 = cr0;
6aa8b732
AK		 1771}
1772
1439442c
SY		 1773static u64 construct_eptp(unsigned long root_hpa)
1774{
1775 u64 eptp;
1776
1777 /* TODO write the value reading from MSR */
1778 eptp = VMX_EPT_DEFAULT_MT |
1779 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1780 eptp |= (root_hpa & PAGE_MASK);
1781
1782 return eptp;
1783}
1784
6aa8b732
AK		 1785static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1786{
1439442c
SY		 1787 unsigned long guest_cr3;
1788 u64 eptp;
1789
1790 guest_cr3 = cr3;
089d034e 1791 if (enable_ept) {
1439442c
SY		 1792 eptp = construct_eptp(cr3);
1793 vmcs_write64(EPT_POINTER, eptp);
1439442c 1794 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
b927a3ce 1795 vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 1796 ept_load_pdptrs(vcpu);
1439442c
SY		 1797 }
1798
2384d2b3 1799 vmx_flush_tlb(vcpu);
1439442c 1800 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 1801}
1802
1803static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1804{
7ffd92c5 1805 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 1806 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1807
ad312c7c 1808 vcpu->arch.cr4 = cr4;
bc23008b
AK		 1809 if (enable_ept) {
1810 if (!is_paging(vcpu)) {
1811 hw_cr4 &= ~X86_CR4_PAE;
1812 hw_cr4 |= X86_CR4_PSE;
1813 } else if (!(cr4 & X86_CR4_PAE)) {
1814 hw_cr4 &= ~X86_CR4_PAE;
1815 }
1816 }
1439442c
SY		 1817
1818 vmcs_writel(CR4_READ_SHADOW, cr4);
1819 vmcs_writel(GUEST_CR4, hw_cr4);
6aa8b732
AK		 1820}
1821
6aa8b732
AK		 1822static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1823{
1824 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1825
1826 return vmcs_readl(sf->base);
1827}
1828
1829static void vmx_get_segment(struct kvm_vcpu *vcpu,
1830 struct kvm_segment *var, int seg)
1831{
1832 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1833 u32 ar;
1834
1835 var->base = vmcs_readl(sf->base);
1836 var->limit = vmcs_read32(sf->limit);
1837 var->selector = vmcs_read16(sf->selector);
1838 ar = vmcs_read32(sf->ar_bytes);
9fd4a3b7 1839 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
6aa8b732
AK		 1840 ar = 0;
1841 var->type = ar & 15;
1842 var->s = (ar >> 4) & 1;
1843 var->dpl = (ar >> 5) & 3;
1844 var->present = (ar >> 7) & 1;
1845 var->avl = (ar >> 12) & 1;
1846 var->l = (ar >> 13) & 1;
1847 var->db = (ar >> 14) & 1;
1848 var->g = (ar >> 15) & 1;
1849 var->unusable = (ar >> 16) & 1;
1850}
1851
2e4d2653
IE		 1852static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1853{
3eeb3288 1854 if (!is_protmode(vcpu))
2e4d2653
IE		 1855 return 0;
1856
1857 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1858 return 3;
1859
eab4b8aa 1860 return vmcs_read16(GUEST_CS_SELECTOR) & 3;
2e4d2653
IE		 1861}
1862
653e3108 1863static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 1864{
6aa8b732
AK		 1865 u32 ar;
1866
653e3108 1867 if (var->unusable)
6aa8b732
AK		 1868 ar = 1 << 16;
1869 else {
1870 ar = var->type & 15;
1871 ar |= (var->s & 1) << 4;
1872 ar |= (var->dpl & 3) << 5;
1873 ar |= (var->present & 1) << 7;
1874 ar |= (var->avl & 1) << 12;
1875 ar |= (var->l & 1) << 13;
1876 ar |= (var->db & 1) << 14;
1877 ar |= (var->g & 1) << 15;
1878 }
f7fbf1fd
UL		 1879 if (ar == 0) /* a 0 value means unusable */
1880 ar = AR_UNUSABLE_MASK;
653e3108
AK		 1881
1882 return ar;
1883}
1884
1885static void vmx_set_segment(struct kvm_vcpu *vcpu,
1886 struct kvm_segment *var, int seg)
1887{
7ffd92c5 1888 struct vcpu_vmx *vmx = to_vmx(vcpu);
653e3108
AK		 1889 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1890 u32 ar;
1891
7ffd92c5
AK		 1892 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
1893 vmx->rmode.tr.selector = var->selector;
1894 vmx->rmode.tr.base = var->base;
1895 vmx->rmode.tr.limit = var->limit;
1896 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
653e3108
AK		 1897 return;
1898 }
1899 vmcs_writel(sf->base, var->base);
1900 vmcs_write32(sf->limit, var->limit);
1901 vmcs_write16(sf->selector, var->selector);
7ffd92c5 1902 if (vmx->rmode.vm86_active && var->s) {
653e3108
AK		 1903 /*
1904 * Hack real-mode segments into vm86 compatibility.
1905 */
1906 if (var->base == 0xffff0000 && var->selector == 0xf000)
1907 vmcs_writel(sf->base, 0xf0000);
1908 ar = 0xf3;
1909 } else
1910 ar = vmx_segment_access_rights(var);
3a624e29
NK		 1911
1912 /*
1913 * Fix the "Accessed" bit in AR field of segment registers for older
1914 * qemu binaries.
1915 * IA32 arch specifies that at the time of processor reset the
1916 * "Accessed" bit in the AR field of segment registers is 1. And qemu
1917 * is setting it to 0 in the usedland code. This causes invalid guest
1918 * state vmexit when "unrestricted guest" mode is turned on.
1919 * Fix for this setup issue in cpu_reset is being pushed in the qemu
1920 * tree. Newer qemu binaries with that qemu fix would not need this
1921 * kvm hack.
1922 */
1923 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
1924 ar |= 0x1; /* Accessed */
1925
6aa8b732
AK		 1926 vmcs_write32(sf->ar_bytes, ar);
1927}
1928
6aa8b732
AK		 1929static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1930{
1931 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1932
1933 *db = (ar >> 14) & 1;
1934 *l = (ar >> 13) & 1;
1935}
1936
1937static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1938{
1939 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1940 dt->base = vmcs_readl(GUEST_IDTR_BASE);
1941}
1942
1943static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1944{
1945 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1946 vmcs_writel(GUEST_IDTR_BASE, dt->base);
1947}
1948
1949static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1950{
1951 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1952 dt->base = vmcs_readl(GUEST_GDTR_BASE);
1953}
1954
1955static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1956{
1957 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1958 vmcs_writel(GUEST_GDTR_BASE, dt->base);
1959}
1960
648dfaa7
MG		 1961static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
1962{
1963 struct kvm_segment var;
1964 u32 ar;
1965
1966 vmx_get_segment(vcpu, &var, seg);
1967 ar = vmx_segment_access_rights(&var);
1968
1969 if (var.base != (var.selector << 4))
1970 return false;
1971 if (var.limit != 0xffff)
1972 return false;
1973 if (ar != 0xf3)
1974 return false;
1975
1976 return true;
1977}
1978
1979static bool code_segment_valid(struct kvm_vcpu *vcpu)
1980{
1981 struct kvm_segment cs;
1982 unsigned int cs_rpl;
1983
1984 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1985 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
1986
1872a3f4
AK		 1987 if (cs.unusable)
1988 return false;
648dfaa7
MG		 1989 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
1990 return false;
1991 if (!cs.s)
1992 return false;
1872a3f4 1993 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 1994 if (cs.dpl > cs_rpl)
1995 return false;
1872a3f4 1996 } else {
648dfaa7
MG		 1997 if (cs.dpl != cs_rpl)
1998 return false;
1999 }
2000 if (!cs.present)
2001 return false;
2002
2003 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
2004 return true;
2005}
2006
2007static bool stack_segment_valid(struct kvm_vcpu *vcpu)
2008{
2009 struct kvm_segment ss;
2010 unsigned int ss_rpl;
2011
2012 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2013 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
2014
1872a3f4
AK		 2015 if (ss.unusable)
2016 return true;
2017 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 2018 return false;
2019 if (!ss.s)
2020 return false;
2021 if (ss.dpl != ss_rpl) /* DPL != RPL */
2022 return false;
2023 if (!ss.present)
2024 return false;
2025
2026 return true;
2027}
2028
2029static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
2030{
2031 struct kvm_segment var;
2032 unsigned int rpl;
2033
2034 vmx_get_segment(vcpu, &var, seg);
2035 rpl = var.selector & SELECTOR_RPL_MASK;
2036
1872a3f4
AK		 2037 if (var.unusable)
2038 return true;
648dfaa7
MG		 2039 if (!var.s)
2040 return false;
2041 if (!var.present)
2042 return false;
2043 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
2044 if (var.dpl < rpl) /* DPL < RPL */
2045 return false;
2046 }
2047
2048 /* TODO: Add other members to kvm_segment_field to allow checking for other access
2049 * rights flags
2050 */
2051 return true;
2052}
2053
2054static bool tr_valid(struct kvm_vcpu *vcpu)
2055{
2056 struct kvm_segment tr;
2057
2058 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
2059
1872a3f4
AK		 2060 if (tr.unusable)
2061 return false;
648dfaa7
MG		 2062 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2063 return false;
1872a3f4 2064 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 2065 return false;
2066 if (!tr.present)
2067 return false;
2068
2069 return true;
2070}
2071
2072static bool ldtr_valid(struct kvm_vcpu *vcpu)
2073{
2074 struct kvm_segment ldtr;
2075
2076 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2077
1872a3f4
AK		 2078 if (ldtr.unusable)
2079 return true;
648dfaa7
MG		 2080 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2081 return false;
2082 if (ldtr.type != 2)
2083 return false;
2084 if (!ldtr.present)
2085 return false;
2086
2087 return true;
2088}
2089
2090static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2091{
2092 struct kvm_segment cs, ss;
2093
2094 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2095 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2096
2097 return ((cs.selector & SELECTOR_RPL_MASK) ==
2098 (ss.selector & SELECTOR_RPL_MASK));
2099}
2100
2101/*
2102 * Check if guest state is valid. Returns true if valid, false if
2103 * not.
2104 * We assume that registers are always usable
2105 */
2106static bool guest_state_valid(struct kvm_vcpu *vcpu)
2107{
2108 /* real mode guest state checks */
3eeb3288 2109 if (!is_protmode(vcpu)) {
648dfaa7
MG		 2110 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2111 return false;
2112 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2113 return false;
2114 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2115 return false;
2116 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2117 return false;
2118 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2119 return false;
2120 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2121 return false;
2122 } else {
2123 /* protected mode guest state checks */
2124 if (!cs_ss_rpl_check(vcpu))
2125 return false;
2126 if (!code_segment_valid(vcpu))
2127 return false;
2128 if (!stack_segment_valid(vcpu))
2129 return false;
2130 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2131 return false;
2132 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2133 return false;
2134 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2135 return false;
2136 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2137 return false;
2138 if (!tr_valid(vcpu))
2139 return false;
2140 if (!ldtr_valid(vcpu))
2141 return false;
2142 }
2143 /* TODO:
2144 * - Add checks on RIP
2145 * - Add checks on RFLAGS
2146 */
2147
2148 return true;
2149}
2150
d77c26fc 2151static int init_rmode_tss(struct kvm *kvm)
6aa8b732 2152{
6aa8b732 2153 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde 2154 u16 data = 0;
10589a46 2155 int ret = 0;
195aefde 2156 int r;
6aa8b732 2157
195aefde
IE		 2158 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2159 if (r < 0)
10589a46 2160 goto out;
195aefde 2161 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 2162 r = kvm_write_guest_page(kvm, fn++, &data,
2163 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 2164 if (r < 0)
10589a46 2165 goto out;
195aefde
IE		 2166 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2167 if (r < 0)
10589a46 2168 goto out;
195aefde
IE		 2169 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2170 if (r < 0)
10589a46 2171 goto out;
195aefde 2172 data = ~0;
10589a46
MT		 2173 r = kvm_write_guest_page(kvm, fn, &data,
2174 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2175 sizeof(u8));
195aefde 2176 if (r < 0)
10589a46
MT		 2177 goto out;
2178
2179 ret = 1;
2180out:
10589a46 2181 return ret;
6aa8b732
AK		 2182}
2183
b7ebfb05
SY		 2184static int init_rmode_identity_map(struct kvm *kvm)
2185{
2186 int i, r, ret;
2187 pfn_t identity_map_pfn;
2188 u32 tmp;
2189
089d034e 2190 if (!enable_ept)
b7ebfb05
SY		 2191 return 1;
2192 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2193 printk(KERN_ERR "EPT: identity-mapping pagetable "
2194 "haven't been allocated!\n");
2195 return 0;
2196 }
2197 if (likely(kvm->arch.ept_identity_pagetable_done))
2198 return 1;
2199 ret = 0;
b927a3ce 2200 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
b7ebfb05
SY		 2201 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2202 if (r < 0)
2203 goto out;
2204 /* Set up identity-mapping pagetable for EPT in real mode */
2205 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2206 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2207 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2208 r = kvm_write_guest_page(kvm, identity_map_pfn,
2209 &tmp, i * sizeof(tmp), sizeof(tmp));
2210 if (r < 0)
2211 goto out;
2212 }
2213 kvm->arch.ept_identity_pagetable_done = true;
2214 ret = 1;
2215out:
2216 return ret;
2217}
2218
6aa8b732
AK		 2219static void seg_setup(int seg)
2220{
2221 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 2222 unsigned int ar;
6aa8b732
AK		 2223
2224 vmcs_write16(sf->selector, 0);
2225 vmcs_writel(sf->base, 0);
2226 vmcs_write32(sf->limit, 0xffff);
3a624e29
NK		 2227 if (enable_unrestricted_guest) {
2228 ar = 0x93;
2229 if (seg == VCPU_SREG_CS)
2230 ar |= 0x08; /* code segment */
2231 } else
2232 ar = 0xf3;
2233
2234 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 2235}
2236
f78e0e2e
SY		 2237static int alloc_apic_access_page(struct kvm *kvm)
2238{
2239 struct kvm_userspace_memory_region kvm_userspace_mem;
2240 int r = 0;
2241
79fac95e 2242 mutex_lock(&kvm->slots_lock);
bfc6d222 2243 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 2244 goto out;
2245 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2246 kvm_userspace_mem.flags = 0;
2247 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2248 kvm_userspace_mem.memory_size = PAGE_SIZE;
2249 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2250 if (r)
2251 goto out;
72dc67a6 2252
bfc6d222 2253 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
f78e0e2e 2254out:
79fac95e 2255 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 2256 return r;
2257}
2258
b7ebfb05
SY		 2259static int alloc_identity_pagetable(struct kvm *kvm)
2260{
2261 struct kvm_userspace_memory_region kvm_userspace_mem;
2262 int r = 0;
2263
79fac95e 2264 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 2265 if (kvm->arch.ept_identity_pagetable)
2266 goto out;
2267 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2268 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 2269 kvm_userspace_mem.guest_phys_addr =
2270 kvm->arch.ept_identity_map_addr;
b7ebfb05
SY		 2271 kvm_userspace_mem.memory_size = PAGE_SIZE;
2272 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2273 if (r)
2274 goto out;
2275
b7ebfb05 2276 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
b927a3ce 2277 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
b7ebfb05 2278out:
79fac95e 2279 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 2280 return r;
2281}
2282
2384d2b3
SY		 2283static void allocate_vpid(struct vcpu_vmx *vmx)
2284{
2285 int vpid;
2286
2287 vmx->vpid = 0;
919818ab 2288 if (!enable_vpid)
2384d2b3
SY		 2289 return;
2290 spin_lock(&vmx_vpid_lock);
2291 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2292 if (vpid < VMX_NR_VPIDS) {
2293 vmx->vpid = vpid;
2294 __set_bit(vpid, vmx_vpid_bitmap);
2295 }
2296 spin_unlock(&vmx_vpid_lock);
2297}
2298
5897297b 2299static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
25c5f225 2300{
3e7c73e9 2301 int f = sizeof(unsigned long);
25c5f225
SY		 2302
2303 if (!cpu_has_vmx_msr_bitmap())
2304 return;
2305
2306 /*
2307 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2308 * have the write-low and read-high bitmap offsets the wrong way round.
2309 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2310 */
25c5f225 2311 if (msr <= 0x1fff) {
3e7c73e9
AK		 2312 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2313 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
25c5f225
SY		 2314 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2315 msr &= 0x1fff;
3e7c73e9
AK		 2316 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2317 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
25c5f225 2318 }
25c5f225
SY		 2319}
2320
5897297b
AK		 2321static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2322{
2323 if (!longmode_only)
2324 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2325 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2326}
2327
6aa8b732
AK		 2328/*
2329 * Sets up the vmcs for emulated real mode.
2330 */
8b9cf98c 2331static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 2332{
468d472f 2333 u32 host_sysenter_cs, msr_low, msr_high;
6aa8b732 2334 u32 junk;
53f658b3 2335 u64 host_pat, tsc_this, tsc_base;
6aa8b732
AK		 2336 unsigned long a;
2337 struct descriptor_table dt;
2338 int i;
cd2276a7 2339 unsigned long kvm_vmx_return;
6e5d865c 2340 u32 exec_control;
6aa8b732 2341
6aa8b732 2342 /* I/O */
3e7c73e9
AK		 2343 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2344 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 2345
25c5f225 2346 if (cpu_has_vmx_msr_bitmap())
5897297b 2347 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 2348
6aa8b732
AK		 2349 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2350
6aa8b732 2351 /* Control */
1c3d14fe
YS		 2352 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2353 vmcs_config.pin_based_exec_ctrl);
6e5d865c
YS		 2354
2355 exec_control = vmcs_config.cpu_based_exec_ctrl;
2356 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2357 exec_control &= ~CPU_BASED_TPR_SHADOW;
2358#ifdef CONFIG_X86_64
2359 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2360 CPU_BASED_CR8_LOAD_EXITING;
2361#endif
2362 }
089d034e 2363 if (!enable_ept)
d56f546d 2364 exec_control |= CPU_BASED_CR3_STORE_EXITING |
83dbc83a
MT		 2365 CPU_BASED_CR3_LOAD_EXITING |
2366 CPU_BASED_INVLPG_EXITING;
6e5d865c 2367 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6aa8b732 2368
83ff3b9d
SY		 2369 if (cpu_has_secondary_exec_ctrls()) {
2370 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2371 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2372 exec_control &=
2373 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2384d2b3
SY		 2374 if (vmx->vpid == 0)
2375 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
046d8710 2376 if (!enable_ept) {
d56f546d 2377 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
046d8710
SY		 2378 enable_unrestricted_guest = 0;
2379 }
3a624e29
NK		 2380 if (!enable_unrestricted_guest)
2381 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4b8d54f9
ZE		 2382 if (!ple_gap)
2383 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
83ff3b9d
SY		 2384 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2385 }
f78e0e2e 2386
4b8d54f9
ZE		 2387 if (ple_gap) {
2388 vmcs_write32(PLE_GAP, ple_gap);
2389 vmcs_write32(PLE_WINDOW, ple_window);
2390 }
2391
c7addb90
AK		 2392 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2393 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
6aa8b732
AK		 2394 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2395
2396 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
2397 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2398 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2399
2400 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2401 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2402 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
d6e88aec
AK		 2403 vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs()); /* 22.2.4 */
2404 vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs()); /* 22.2.4 */
6aa8b732 2405 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
05b3e0c2 2406#ifdef CONFIG_X86_64
6aa8b732
AK		 2407 rdmsrl(MSR_FS_BASE, a);
2408 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2409 rdmsrl(MSR_GS_BASE, a);
2410 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2411#else
2412 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2413 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2414#endif
2415
2416 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2417
d6e88aec 2418 kvm_get_idt(&dt);
6aa8b732
AK		 2419 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
2420
d77c26fc 2421 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
cd2276a7 2422 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2cc51560
ED		 2423 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2424 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2425 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
6aa8b732
AK		 2426
2427 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2428 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2429 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2430 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2431 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2432 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2433
468d472f
SY		 2434 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2435 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2436 host_pat = msr_low | ((u64) msr_high << 32);
2437 vmcs_write64(HOST_IA32_PAT, host_pat);
2438 }
2439 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2440 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2441 host_pat = msr_low | ((u64) msr_high << 32);
2442 /* Write the default value follow host pat */
2443 vmcs_write64(GUEST_IA32_PAT, host_pat);
2444 /* Keep arch.pat sync with GUEST_IA32_PAT */
2445 vmx->vcpu.arch.pat = host_pat;
2446 }
2447
6aa8b732
AK		 2448 for (i = 0; i < NR_VMX_MSR; ++i) {
2449 u32 index = vmx_msr_index[i];
2450 u32 data_low, data_high;
a2fa3e9f 2451 int j = vmx->nmsrs;
6aa8b732
AK		 2452
2453 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2454 continue;
432bd6cb
AK		 2455 if (wrmsr_safe(index, data_low, data_high) < 0)
2456 continue;
26bb0981
AK		 2457 vmx->guest_msrs[j].index = i;
2458 vmx->guest_msrs[j].data = 0;
d5696725 2459 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 2460 ++vmx->nmsrs;
6aa8b732 2461 }
6aa8b732 2462
1c3d14fe 2463 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 2464
2465 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 2466 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2467
e00c8cf2 2468 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4c38609a 2469 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
ce03e4f2
AK		 2470 if (enable_ept)
2471 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4c38609a 2472 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
e00c8cf2 2473
53f658b3
MT		 2474 tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc;
2475 rdtscll(tsc_this);
2476 if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc)
2477 tsc_base = tsc_this;
2478
2479 guest_write_tsc(0, tsc_base);
f78e0e2e 2480
e00c8cf2
AK		 2481 return 0;
2482}
2483
b7ebfb05
SY		 2484static int init_rmode(struct kvm *kvm)
2485{
2486 if (!init_rmode_tss(kvm))
2487 return 0;
2488 if (!init_rmode_identity_map(kvm))
2489 return 0;
2490 return 1;
2491}
2492
e00c8cf2
AK		 2493static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2494{
2495 struct vcpu_vmx *vmx = to_vmx(vcpu);
2496 u64 msr;
f656ce01 2497 int ret, idx;
e00c8cf2 2498
5fdbf976 2499 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
f656ce01 2500 idx = srcu_read_lock(&vcpu->kvm->srcu);
b7ebfb05 2501 if (!init_rmode(vmx->vcpu.kvm)) {
e00c8cf2
AK		 2502 ret = -ENOMEM;
2503 goto out;
2504 }
2505
7ffd92c5 2506 vmx->rmode.vm86_active = 0;
e00c8cf2 2507
3b86cd99
JK		 2508 vmx->soft_vnmi_blocked = 0;
2509
ad312c7c 2510 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 2511 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 2512 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 2513 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 2514 msr |= MSR_IA32_APICBASE_BSP;
2515 kvm_set_apic_base(&vmx->vcpu, msr);
2516
2517 fx_init(&vmx->vcpu);
2518
5706be0d 2519 seg_setup(VCPU_SREG_CS);
e00c8cf2
AK		 2520 /*
2521 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2522 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2523 */
c5af89b6 2524 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
e00c8cf2
AK		 2525 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2526 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2527 } else {
ad312c7c
ZX		 2528 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2529 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2 2530 }
e00c8cf2
AK		 2531
2532 seg_setup(VCPU_SREG_DS);
2533 seg_setup(VCPU_SREG_ES);
2534 seg_setup(VCPU_SREG_FS);
2535 seg_setup(VCPU_SREG_GS);
2536 seg_setup(VCPU_SREG_SS);
2537
2538 vmcs_write16(GUEST_TR_SELECTOR, 0);
2539 vmcs_writel(GUEST_TR_BASE, 0);
2540 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2541 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2542
2543 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2544 vmcs_writel(GUEST_LDTR_BASE, 0);
2545 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2546 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2547
2548 vmcs_write32(GUEST_SYSENTER_CS, 0);
2549 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2550 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2551
2552 vmcs_writel(GUEST_RFLAGS, 0x02);
c5af89b6 2553 if (kvm_vcpu_is_bsp(&vmx->vcpu))
5fdbf976 2554 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 2555 else
5fdbf976
MT		 2556 kvm_rip_write(vcpu, 0);
2557 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
e00c8cf2 2558
e00c8cf2
AK		 2559 vmcs_writel(GUEST_DR7, 0x400);
2560
2561 vmcs_writel(GUEST_GDTR_BASE, 0);
2562 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2563
2564 vmcs_writel(GUEST_IDTR_BASE, 0);
2565 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2566
2567 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2568 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2569 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2570
e00c8cf2
AK		 2571 /* Special registers */
2572 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2573
2574 setup_msrs(vmx);
2575
6aa8b732
AK		 2576 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2577
f78e0e2e
SY		 2578 if (cpu_has_vmx_tpr_shadow()) {
2579 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2580 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2581 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
ad312c7c 2582 page_to_phys(vmx->vcpu.arch.apic->regs_page));
f78e0e2e
SY		 2583 vmcs_write32(TPR_THRESHOLD, 0);
2584 }
2585
2586 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2587 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 2588 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 2589
2384d2b3
SY		 2590 if (vmx->vpid != 0)
2591 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2592
fa40052c 2593 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 2594 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 2595 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 2596 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 2597 vmx_fpu_activate(&vmx->vcpu);
2598 update_exception_bitmap(&vmx->vcpu);
6aa8b732 2599
2384d2b3
SY		 2600 vpid_sync_vcpu_all(vmx);
2601
3200f405 2602 ret = 0;
6aa8b732 2603
a89a8fb9
MG		 2604 /* HACK: Don't enable emulation on guest boot/reset */
2605 vmx->emulation_required = 0;
2606
6aa8b732 2607out:
f656ce01 2608 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6aa8b732
AK		 2609 return ret;
2610}
2611
3b86cd99
JK		 2612static void enable_irq_window(struct kvm_vcpu *vcpu)
2613{
2614 u32 cpu_based_vm_exec_control;
2615
2616 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2617 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2618 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2619}
2620
2621static void enable_nmi_window(struct kvm_vcpu *vcpu)
2622{
2623 u32 cpu_based_vm_exec_control;
2624
2625 if (!cpu_has_virtual_nmis()) {
2626 enable_irq_window(vcpu);
2627 return;
2628 }
2629
2630 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2631 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2632 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2633}
2634
66fd3f7f 2635static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 2636{
9c8cba37 2637 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 2638 uint32_t intr;
2639 int irq = vcpu->arch.interrupt.nr;
9c8cba37 2640
229456fc 2641 trace_kvm_inj_virq(irq);
2714d1d3 2642
fa89a817 2643 ++vcpu->stat.irq_injections;
7ffd92c5 2644 if (vmx->rmode.vm86_active) {
9c8cba37
AK		 2645 vmx->rmode.irq.pending = true;
2646 vmx->rmode.irq.vector = irq;
5fdbf976 2647 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
ae0bb3e0
GN		 2648 if (vcpu->arch.interrupt.soft)
2649 vmx->rmode.irq.rip +=
2650 vmx->vcpu.arch.event_exit_inst_len;
9c5623e3
AK		 2651 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2652 irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2653 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
5fdbf976 2654 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
85f455f7
ED		 2655 return;
2656 }
66fd3f7f
GN		 2657 intr = irq | INTR_INFO_VALID_MASK;
2658 if (vcpu->arch.interrupt.soft) {
2659 intr |= INTR_TYPE_SOFT_INTR;
2660 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2661 vmx->vcpu.arch.event_exit_inst_len);
2662 } else
2663 intr |= INTR_TYPE_EXT_INTR;
2664 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 2665}
2666
f08864b4
SY		 2667static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2668{
66a5a347
JK		 2669 struct vcpu_vmx *vmx = to_vmx(vcpu);
2670
3b86cd99
JK		 2671 if (!cpu_has_virtual_nmis()) {
2672 /*
2673 * Tracking the NMI-blocked state in software is built upon
2674 * finding the next open IRQ window. This, in turn, depends on
2675 * well-behaving guests: They have to keep IRQs disabled at
2676 * least as long as the NMI handler runs. Otherwise we may
2677 * cause NMI nesting, maybe breaking the guest. But as this is
2678 * highly unlikely, we can live with the residual risk.
2679 */
2680 vmx->soft_vnmi_blocked = 1;
2681 vmx->vnmi_blocked_time = 0;
2682 }
2683
487b391d 2684 ++vcpu->stat.nmi_injections;
7ffd92c5 2685 if (vmx->rmode.vm86_active) {
66a5a347
JK		 2686 vmx->rmode.irq.pending = true;
2687 vmx->rmode.irq.vector = NMI_VECTOR;
2688 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2689 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2690 NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2691 INTR_INFO_VALID_MASK);
2692 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2693 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2694 return;
2695 }
f08864b4
SY		 2696 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2697 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 2698}
2699
c4282df9 2700static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
33f089ca 2701{
3b86cd99 2702 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
c4282df9 2703 return 0;
33f089ca 2704
c4282df9
GN		 2705 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2706 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS |
2707 GUEST_INTR_STATE_NMI));
33f089ca
JK		 2708}
2709
3cfc3092
JK		 2710static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
2711{
2712 if (!cpu_has_virtual_nmis())
2713 return to_vmx(vcpu)->soft_vnmi_blocked;
2714 else
2715 return !!(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2716 GUEST_INTR_STATE_NMI);
2717}
2718
2719static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2720{
2721 struct vcpu_vmx *vmx = to_vmx(vcpu);
2722
2723 if (!cpu_has_virtual_nmis()) {
2724 if (vmx->soft_vnmi_blocked != masked) {
2725 vmx->soft_vnmi_blocked = masked;
2726 vmx->vnmi_blocked_time = 0;
2727 }
2728 } else {
2729 if (masked)
2730 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
2731 GUEST_INTR_STATE_NMI);
2732 else
2733 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2734 GUEST_INTR_STATE_NMI);
2735 }
2736}
2737
78646121
GN		 2738static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2739{
c4282df9
GN		 2740 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2741 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2742 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 2743}
2744
cbc94022
IE		 2745static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2746{
2747 int ret;
2748 struct kvm_userspace_memory_region tss_mem = {
6fe63979 2749 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 2750 .guest_phys_addr = addr,
2751 .memory_size = PAGE_SIZE * 3,
2752 .flags = 0,
2753 };
2754
2755 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2756 if (ret)
2757 return ret;
bfc6d222 2758 kvm->arch.tss_addr = addr;
cbc94022
IE		 2759 return 0;
2760}
2761
6aa8b732
AK		 2762static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2763 int vec, u32 err_code)
2764{
b3f37707
NK		 2765 /*
2766 * Instruction with address size override prefix opcode 0x67
2767 * Cause the #SS fault with 0 error code in VM86 mode.
2768 */
2769 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
851ba692 2770 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE)
6aa8b732 2771 return 1;
77ab6db0
JK		 2772 /*
2773 * Forward all other exceptions that are valid in real mode.
2774 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2775 * the required debugging infrastructure rework.
2776 */
2777 switch (vec) {
77ab6db0 2778 case DB_VECTOR:
d0bfb940
JK		 2779 if (vcpu->guest_debug &
2780 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2781 return 0;
2782 kvm_queue_exception(vcpu, vec);
2783 return 1;
77ab6db0 2784 case BP_VECTOR:
c573cd22
JK		 2785 /*
2786 * Update instruction length as we may reinject the exception
2787 * from user space while in guest debugging mode.
2788 */
2789 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
2790 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940
JK		 2791 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2792 return 0;
2793 /* fall through */
2794 case DE_VECTOR:
77ab6db0
JK		 2795 case OF_VECTOR:
2796 case BR_VECTOR:
2797 case UD_VECTOR:
2798 case DF_VECTOR:
2799 case SS_VECTOR:
2800 case GP_VECTOR:
2801 case MF_VECTOR:
2802 kvm_queue_exception(vcpu, vec);
2803 return 1;
2804 }
6aa8b732
AK		 2805 return 0;
2806}
2807
a0861c02
AK		 2808/*
2809 * Trigger machine check on the host. We assume all the MSRs are already set up
2810 * by the CPU and that we still run on the same CPU as the MCE occurred on.
2811 * We pass a fake environment to the machine check handler because we want
2812 * the guest to be always treated like user space, no matter what context
2813 * it used internally.
2814 */
2815static void kvm_machine_check(void)
2816{
2817#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
2818 struct pt_regs regs = {
2819 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
2820 .flags = X86_EFLAGS_IF,
2821 };
2822
2823 do_machine_check(&regs, 0);
2824#endif
2825}
2826
851ba692 2827static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 2828{
2829 /* already handled by vcpu_run */
2830 return 1;
2831}
2832
851ba692 2833static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 2834{
1155f76a 2835 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 2836 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 2837 u32 intr_info, ex_no, error_code;
42dbaa5a 2838 unsigned long cr2, rip, dr6;
6aa8b732
AK		 2839 u32 vect_info;
2840 enum emulation_result er;
2841
1155f76a 2842 vect_info = vmx->idt_vectoring_info;
6aa8b732
AK		 2843 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2844
a0861c02 2845 if (is_machine_check(intr_info))
851ba692 2846 return handle_machine_check(vcpu);
a0861c02 2847
6aa8b732 2848 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
65ac7264
AK		 2849 !is_page_fault(intr_info)) {
2850 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2851 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
2852 vcpu->run->internal.ndata = 2;
2853 vcpu->run->internal.data[0] = vect_info;
2854 vcpu->run->internal.data[1] = intr_info;
2855 return 0;
2856 }
6aa8b732 2857
e4a41889 2858 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 2859 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 2860
2861 if (is_no_device(intr_info)) {
5fd86fcf 2862 vmx_fpu_activate(vcpu);
2ab455cc
AL		 2863 return 1;
2864 }
2865
7aa81cc0 2866 if (is_invalid_opcode(intr_info)) {
851ba692 2867 er = emulate_instruction(vcpu, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 2868 if (er != EMULATE_DONE)
7ee5d940 2869 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 2870 return 1;
2871 }
2872
6aa8b732 2873 error_code = 0;
5fdbf976 2874 rip = kvm_rip_read(vcpu);
2e11384c 2875 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732
AK		 2876 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2877 if (is_page_fault(intr_info)) {
1439442c 2878 /* EPT won't cause page fault directly */
089d034e 2879 if (enable_ept)
1439442c 2880 BUG();
6aa8b732 2881 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 2882 trace_kvm_page_fault(cr2, error_code);
2883
3298b75c 2884 if (kvm_event_needs_reinjection(vcpu))
577bdc49 2885 kvm_mmu_unprotect_page_virt(vcpu, cr2);
3067714c 2886 return kvm_mmu_page_fault(vcpu, cr2, error_code);
6aa8b732
AK		 2887 }
2888
7ffd92c5 2889 if (vmx->rmode.vm86_active &&
6aa8b732 2890 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0 2891 error_code)) {
ad312c7c
ZX		 2892 if (vcpu->arch.halt_request) {
2893 vcpu->arch.halt_request = 0;
72d6e5a0
AK		 2894 return kvm_emulate_halt(vcpu);
2895 }
6aa8b732 2896 return 1;
72d6e5a0 2897 }
6aa8b732 2898
d0bfb940 2899 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
42dbaa5a
JK		 2900 switch (ex_no) {
2901 case DB_VECTOR:
2902 dr6 = vmcs_readl(EXIT_QUALIFICATION);
2903 if (!(vcpu->guest_debug &
2904 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
2905 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
2906 kvm_queue_exception(vcpu, DB_VECTOR);
2907 return 1;
2908 }
2909 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
2910 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
2911 /* fall through */
2912 case BP_VECTOR:
c573cd22
JK		 2913 /*
2914 * Update instruction length as we may reinject #BP from
2915 * user space while in guest debugging mode. Reading it for
2916 * #DB as well causes no harm, it is not used in that case.
2917 */
2918 vmx->vcpu.arch.event_exit_inst_len =
2919 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 2920 kvm_run->exit_reason = KVM_EXIT_DEBUG;
d0bfb940
JK		 2921 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
2922 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 2923 break;
2924 default:
d0bfb940
JK		 2925 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2926 kvm_run->ex.exception = ex_no;
2927 kvm_run->ex.error_code = error_code;
42dbaa5a 2928 break;
6aa8b732 2929 }
6aa8b732
AK		 2930 return 0;
2931}
2932
851ba692 2933static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 2934{
1165f5fe 2935 ++vcpu->stat.irq_exits;
6aa8b732
AK		 2936 return 1;
2937}
2938
851ba692 2939static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 2940{
851ba692 2941 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 2942 return 0;
2943}
6aa8b732 2944
851ba692 2945static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 2946{
bfdaab09 2947 unsigned long exit_qualification;
34c33d16 2948 int size, in, string;
039576c0 2949 unsigned port;
6aa8b732 2950
1165f5fe 2951 ++vcpu->stat.io_exits;
bfdaab09 2952 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 2953 string = (exit_qualification & 16) != 0;
e70669ab
LV		 2954
2955 if (string) {
851ba692 2956 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DO_MMIO)
e70669ab
LV		 2957 return 0;
2958 return 1;
2959 }
2960
2961 size = (exit_qualification & 7) + 1;
2962 in = (exit_qualification & 8) != 0;
039576c0 2963 port = exit_qualification >> 16;
e70669ab 2964
e93f36bc 2965 skip_emulated_instruction(vcpu);
851ba692 2966 return kvm_emulate_pio(vcpu, in, size, port);
6aa8b732
AK		 2967}
2968
102d8325
IM		 2969static void
2970vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2971{
2972 /*
2973 * Patch in the VMCALL instruction:
2974 */
2975 hypercall[0] = 0x0f;
2976 hypercall[1] = 0x01;
2977 hypercall[2] = 0xc1;
102d8325
IM		 2978}
2979
851ba692 2980static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 2981{
229456fc 2982 unsigned long exit_qualification, val;
6aa8b732
AK		 2983 int cr;
2984 int reg;
2985
bfdaab09 2986 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 2987 cr = exit_qualification & 15;
2988 reg = (exit_qualification >> 8) & 15;
2989 switch ((exit_qualification >> 4) & 3) {
2990 case 0: /* mov to cr */
229456fc
MT		 2991 val = kvm_register_read(vcpu, reg);
2992 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 2993 switch (cr) {
2994 case 0:
229456fc 2995 kvm_set_cr0(vcpu, val);
6aa8b732
AK		 2996 skip_emulated_instruction(vcpu);
2997 return 1;
2998 case 3:
229456fc 2999 kvm_set_cr3(vcpu, val);
6aa8b732
AK		 3000 skip_emulated_instruction(vcpu);
3001 return 1;
3002 case 4:
229456fc 3003 kvm_set_cr4(vcpu, val);
6aa8b732
AK		 3004 skip_emulated_instruction(vcpu);
3005 return 1;
0a5fff19
GN		 3006 case 8: {
3007 u8 cr8_prev = kvm_get_cr8(vcpu);
3008 u8 cr8 = kvm_register_read(vcpu, reg);
3009 kvm_set_cr8(vcpu, cr8);
3010 skip_emulated_instruction(vcpu);
3011 if (irqchip_in_kernel(vcpu->kvm))
3012 return 1;
3013 if (cr8_prev <= cr8)
3014 return 1;
851ba692 3015 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 3016 return 0;
3017 }
6aa8b732
AK		 3018 };
3019 break;
25c4c276 3020 case 2: /* clts */
edcafe3c 3021 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4d4ec087 3022 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 3023 skip_emulated_instruction(vcpu);
6b52d186 3024 vmx_fpu_activate(vcpu);
25c4c276 3025 return 1;
6aa8b732
AK		 3026 case 1: /*mov from cr*/
3027 switch (cr) {
3028 case 3:
5fdbf976 3029 kvm_register_write(vcpu, reg, vcpu->arch.cr3);
229456fc 3030 trace_kvm_cr_read(cr, vcpu->arch.cr3);
6aa8b732
AK		 3031 skip_emulated_instruction(vcpu);
3032 return 1;
3033 case 8:
229456fc
MT		 3034 val = kvm_get_cr8(vcpu);
3035 kvm_register_write(vcpu, reg, val);
3036 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 3037 skip_emulated_instruction(vcpu);
3038 return 1;
3039 }
3040 break;
3041 case 3: /* lmsw */
a1f83a74 3042 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 3043 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 3044 kvm_lmsw(vcpu, val);
6aa8b732
AK		 3045
3046 skip_emulated_instruction(vcpu);
3047 return 1;
3048 default:
3049 break;
3050 }
851ba692 3051 vcpu->run->exit_reason = 0;
f0242478 3052 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 3053 (int)(exit_qualification >> 4) & 3, cr);
3054 return 0;
3055}
3056
138ac8d8
JK		 3057static int check_dr_alias(struct kvm_vcpu *vcpu)
3058{
3059 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE)) {
3060 kvm_queue_exception(vcpu, UD_VECTOR);
3061 return -1;
3062 }
3063 return 0;
3064}
3065
851ba692 3066static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 3067{
bfdaab09 3068 unsigned long exit_qualification;
6aa8b732
AK		 3069 unsigned long val;
3070 int dr, reg;
3071
f2483415 3072 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 3073 if (!kvm_require_cpl(vcpu, 0))
3074 return 1;
42dbaa5a
JK		 3075 dr = vmcs_readl(GUEST_DR7);
3076 if (dr & DR7_GD) {
3077 /*
3078 * As the vm-exit takes precedence over the debug trap, we
3079 * need to emulate the latter, either for the host or the
3080 * guest debugging itself.
3081 */
3082 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 3083 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
3084 vcpu->run->debug.arch.dr7 = dr;
3085 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 3086 vmcs_readl(GUEST_CS_BASE) +
3087 vmcs_readl(GUEST_RIP);
851ba692
AK		 3088 vcpu->run->debug.arch.exception = DB_VECTOR;
3089 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 3090 return 0;
3091 } else {
3092 vcpu->arch.dr7 &= ~DR7_GD;
3093 vcpu->arch.dr6 |= DR6_BD;
3094 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3095 kvm_queue_exception(vcpu, DB_VECTOR);
3096 return 1;
3097 }
3098 }
3099
bfdaab09 3100 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 3101 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
3102 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
3103 if (exit_qualification & TYPE_MOV_FROM_DR) {
6aa8b732 3104 switch (dr) {
42dbaa5a
JK		 3105 case 0 ... 3:
3106 val = vcpu->arch.db[dr];
3107 break;
138ac8d8
JK		 3108 case 4:
3109 if (check_dr_alias(vcpu) < 0)
3110 return 1;
3111 /* fall through */
6aa8b732 3112 case 6:
42dbaa5a 3113 val = vcpu->arch.dr6;
6aa8b732 3114 break;
138ac8d8
JK		 3115 case 5:
3116 if (check_dr_alias(vcpu) < 0)
3117 return 1;
3118 /* fall through */
3119 default: /* 7 */
42dbaa5a 3120 val = vcpu->arch.dr7;
6aa8b732 3121 break;
6aa8b732 3122 }
5fdbf976 3123 kvm_register_write(vcpu, reg, val);
6aa8b732 3124 } else {
42dbaa5a
JK		 3125 val = vcpu->arch.regs[reg];
3126 switch (dr) {
3127 case 0 ... 3:
3128 vcpu->arch.db[dr] = val;
3129 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
3130 vcpu->arch.eff_db[dr] = val;
3131 break;
138ac8d8
JK		 3132 case 4:
3133 if (check_dr_alias(vcpu) < 0)
f2483415 3134 return 1;
138ac8d8 3135 /* fall through */
42dbaa5a
JK		 3136 case 6:
3137 if (val & 0xffffffff00000000ULL) {
f2483415
JK		 3138 kvm_inject_gp(vcpu, 0);
3139 return 1;
42dbaa5a
JK		 3140 }
3141 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
3142 break;
138ac8d8
JK		 3143 case 5:
3144 if (check_dr_alias(vcpu) < 0)
3145 return 1;
3146 /* fall through */
3147 default: /* 7 */
42dbaa5a 3148 if (val & 0xffffffff00000000ULL) {
f2483415
JK		 3149 kvm_inject_gp(vcpu, 0);
3150 return 1;
42dbaa5a
JK		 3151 }
3152 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
3153 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
3154 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3155 vcpu->arch.switch_db_regs =
3156 (val & DR7_BP_EN_MASK);
3157 }
3158 break;
3159 }
6aa8b732 3160 }
6aa8b732
AK		 3161 skip_emulated_instruction(vcpu);
3162 return 1;
3163}
3164
851ba692 3165static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 3166{
06465c5a
AK		 3167 kvm_emulate_cpuid(vcpu);
3168 return 1;
6aa8b732
AK		 3169}
3170
851ba692 3171static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 3172{
ad312c7c 3173 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 3174 u64 data;
3175
3176 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 3177 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 3178 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 3179 return 1;
3180 }
3181
229456fc 3182 trace_kvm_msr_read(ecx, data);
2714d1d3 3183
6aa8b732 3184 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 3185 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3186 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 3187 skip_emulated_instruction(vcpu);
3188 return 1;
3189}
3190
851ba692 3191static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 3192{
ad312c7c
ZX		 3193 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3194 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3195 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732
AK		 3196
3197 if (vmx_set_msr(vcpu, ecx, data) != 0) {
59200273 3198 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 3199 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 3200 return 1;
3201 }
3202
59200273 3203 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 3204 skip_emulated_instruction(vcpu);
3205 return 1;
3206}
3207
851ba692 3208static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c
YS		 3209{
3210 return 1;
3211}
3212
851ba692 3213static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 3214{
85f455f7
ED		 3215 u32 cpu_based_vm_exec_control;
3216
3217 /* clear pending irq */
3218 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3219 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3220 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 3221
a26bf12a 3222 ++vcpu->stat.irq_window_exits;
2714d1d3 3223
c1150d8c
DL		 3224 /*
3225 * If the user space waits to inject interrupts, exit as soon as
3226 * possible
3227 */
8061823a 3228 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 3229 vcpu->run->request_interrupt_window &&
8061823a 3230 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 3231 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 3232 return 0;
3233 }
6aa8b732
AK		 3234 return 1;
3235}
3236
851ba692 3237static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 3238{
3239 skip_emulated_instruction(vcpu);
d3bef15f 3240 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 3241}
3242
851ba692 3243static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 3244{
510043da 3245 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 3246 kvm_emulate_hypercall(vcpu);
3247 return 1;
c21415e8
IM		 3248}
3249
851ba692 3250static int handle_vmx_insn(struct kvm_vcpu *vcpu)
e3c7cb6a
AK		 3251{
3252 kvm_queue_exception(vcpu, UD_VECTOR);
3253 return 1;
3254}
3255
851ba692 3256static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 3257{
f9c617f6 3258 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 3259
3260 kvm_mmu_invlpg(vcpu, exit_qualification);
3261 skip_emulated_instruction(vcpu);
3262 return 1;
3263}
3264
851ba692 3265static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 3266{
3267 skip_emulated_instruction(vcpu);
3268 /* TODO: Add support for VT-d/pass-through device */
3269 return 1;
3270}
3271
851ba692 3272static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 3273{
f9c617f6 3274 unsigned long exit_qualification;
f78e0e2e
SY		 3275 enum emulation_result er;
3276 unsigned long offset;
3277
f9c617f6 3278 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
f78e0e2e
SY		 3279 offset = exit_qualification & 0xffful;
3280
851ba692 3281 er = emulate_instruction(vcpu, 0, 0, 0);
f78e0e2e
SY		 3282
3283 if (er != EMULATE_DONE) {
3284 printk(KERN_ERR
3285 "Fail to handle apic access vmexit! Offset is 0x%lx\n",
3286 offset);
7f582ab6 3287 return -ENOEXEC;
f78e0e2e
SY		 3288 }
3289 return 1;
3290}
3291
851ba692 3292static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 3293{
60637aac 3294 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29
IE		 3295 unsigned long exit_qualification;
3296 u16 tss_selector;
64a7ec06
GN		 3297 int reason, type, idt_v;
3298
3299 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3300 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 3301
3302 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3303
3304 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 3305 if (reason == TASK_SWITCH_GATE && idt_v) {
3306 switch (type) {
3307 case INTR_TYPE_NMI_INTR:
3308 vcpu->arch.nmi_injected = false;
3309 if (cpu_has_virtual_nmis())
3310 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3311 GUEST_INTR_STATE_NMI);
3312 break;
3313 case INTR_TYPE_EXT_INTR:
66fd3f7f 3314 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 3315 kvm_clear_interrupt_queue(vcpu);
3316 break;
3317 case INTR_TYPE_HARD_EXCEPTION:
3318 case INTR_TYPE_SOFT_EXCEPTION:
3319 kvm_clear_exception_queue(vcpu);
3320 break;
3321 default:
3322 break;
3323 }
60637aac 3324 }
37817f29
IE		 3325 tss_selector = exit_qualification;
3326
64a7ec06
GN		 3327 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3328 type != INTR_TYPE_EXT_INTR &&
3329 type != INTR_TYPE_NMI_INTR))
3330 skip_emulated_instruction(vcpu);
3331
42dbaa5a
JK		 3332 if (!kvm_task_switch(vcpu, tss_selector, reason))
3333 return 0;
3334
3335 /* clear all local breakpoint enable flags */
3336 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3337
3338 /*
3339 * TODO: What about debug traps on tss switch?
3340 * Are we supposed to inject them and update dr6?
3341 */
3342
3343 return 1;
37817f29
IE		 3344}
3345
851ba692 3346static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 3347{
f9c617f6 3348 unsigned long exit_qualification;
1439442c 3349 gpa_t gpa;
1439442c 3350 int gla_validity;
1439442c 3351
f9c617f6 3352 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c
SY		 3353
3354 if (exit_qualification & (1 << 6)) {
3355 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
7f582ab6 3356 return -EINVAL;
1439442c
SY		 3357 }
3358
3359 gla_validity = (exit_qualification >> 7) & 0x3;
3360 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3361 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3362 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3363 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 3364 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 3365 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3366 (long unsigned int)exit_qualification);
851ba692
AK		 3367 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3368 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 3369 return 0;
1439442c
SY		 3370 }
3371
3372 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 3373 trace_kvm_page_fault(gpa, exit_qualification);
49cd7d22 3374 return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
1439442c
SY		 3375}
3376
68f89400
MT		 3377static u64 ept_rsvd_mask(u64 spte, int level)
3378{
3379 int i;
3380 u64 mask = 0;
3381
3382 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3383 mask |= (1ULL << i);
3384
3385 if (level > 2)
3386 /* bits 7:3 reserved */
3387 mask |= 0xf8;
3388 else if (level == 2) {
3389 if (spte & (1ULL << 7))
3390 /* 2MB ref, bits 20:12 reserved */
3391 mask |= 0x1ff000;
3392 else
3393 /* bits 6:3 reserved */
3394 mask |= 0x78;
3395 }
3396
3397 return mask;
3398}
3399
3400static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3401 int level)
3402{
3403 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3404
3405 /* 010b (write-only) */
3406 WARN_ON((spte & 0x7) == 0x2);
3407
3408 /* 110b (write/execute) */
3409 WARN_ON((spte & 0x7) == 0x6);
3410
3411 /* 100b (execute-only) and value not supported by logical processor */
3412 if (!cpu_has_vmx_ept_execute_only())
3413 WARN_ON((spte & 0x7) == 0x4);
3414
3415 /* not 000b */
3416 if ((spte & 0x7)) {
3417 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3418
3419 if (rsvd_bits != 0) {
3420 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3421 __func__, rsvd_bits);
3422 WARN_ON(1);
3423 }
3424
3425 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3426 u64 ept_mem_type = (spte & 0x38) >> 3;
3427
3428 if (ept_mem_type == 2 || ept_mem_type == 3 ||
3429 ept_mem_type == 7) {
3430 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3431 __func__, ept_mem_type);
3432 WARN_ON(1);
3433 }
3434 }
3435 }
3436}
3437
851ba692 3438static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 3439{
3440 u64 sptes[4];
3441 int nr_sptes, i;
3442 gpa_t gpa;
3443
3444 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3445
3446 printk(KERN_ERR "EPT: Misconfiguration.\n");
3447 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3448
3449 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3450
3451 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3452 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3453
851ba692
AK		 3454 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3455 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 3456
3457 return 0;
3458}
3459
851ba692 3460static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 3461{
3462 u32 cpu_based_vm_exec_control;
3463
3464 /* clear pending NMI */
3465 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3466 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3467 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3468 ++vcpu->stat.nmi_window_exits;
3469
3470 return 1;
3471}
3472
80ced186 3473static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 3474{
8b3079a5
AK		 3475 struct vcpu_vmx *vmx = to_vmx(vcpu);
3476 enum emulation_result err = EMULATE_DONE;
80ced186 3477 int ret = 1;
ea953ef0
MG		 3478
3479 while (!guest_state_valid(vcpu)) {
851ba692 3480 err = emulate_instruction(vcpu, 0, 0, 0);
ea953ef0 3481
80ced186
MG		 3482 if (err == EMULATE_DO_MMIO) {
3483 ret = 0;
3484 goto out;
3485 }
1d5a4d9b
GT		 3486
3487 if (err != EMULATE_DONE) {
80ced186
MG		 3488 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3489 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
a9c7399d 3490 vcpu->run->internal.ndata = 0;
80ced186
MG		 3491 ret = 0;
3492 goto out;
ea953ef0
MG		 3493 }
3494
3495 if (signal_pending(current))
80ced186 3496 goto out;
ea953ef0
MG		 3497 if (need_resched())
3498 schedule();
3499 }
3500
80ced186
MG		 3501 vmx->emulation_required = 0;
3502out:
3503 return ret;
ea953ef0
MG		 3504}
3505
4b8d54f9
ZE		 3506/*
3507 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3508 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3509 */
9fb41ba8 3510static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 3511{
3512 skip_emulated_instruction(vcpu);
3513 kvm_vcpu_on_spin(vcpu);
3514
3515 return 1;
3516}
3517
59708670
SY		 3518static int handle_invalid_op(struct kvm_vcpu *vcpu)
3519{
3520 kvm_queue_exception(vcpu, UD_VECTOR);
3521 return 1;
3522}
3523
6aa8b732
AK		 3524/*
3525 * The exit handlers return 1 if the exit was handled fully and guest execution
3526 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3527 * to be done to userspace and return 0.
3528 */
851ba692 3529static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 3530 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3531 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 3532 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 3533 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 3534 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 3535 [EXIT_REASON_CR_ACCESS] = handle_cr,
3536 [EXIT_REASON_DR_ACCESS] = handle_dr,
3537 [EXIT_REASON_CPUID] = handle_cpuid,
3538 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3539 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3540 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3541 [EXIT_REASON_HLT] = handle_halt,
a7052897 3542 [EXIT_REASON_INVLPG] = handle_invlpg,
c21415e8 3543 [EXIT_REASON_VMCALL] = handle_vmcall,
e3c7cb6a
AK		 3544 [EXIT_REASON_VMCLEAR] = handle_vmx_insn,
3545 [EXIT_REASON_VMLAUNCH] = handle_vmx_insn,
3546 [EXIT_REASON_VMPTRLD] = handle_vmx_insn,
3547 [EXIT_REASON_VMPTRST] = handle_vmx_insn,
3548 [EXIT_REASON_VMREAD] = handle_vmx_insn,
3549 [EXIT_REASON_VMRESUME] = handle_vmx_insn,
3550 [EXIT_REASON_VMWRITE] = handle_vmx_insn,
3551 [EXIT_REASON_VMOFF] = handle_vmx_insn,
3552 [EXIT_REASON_VMON] = handle_vmx_insn,
f78e0e2e
SY		 3553 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3554 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 3555 [EXIT_REASON_WBINVD] = handle_wbinvd,
37817f29 3556 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 3557 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 3558 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
3559 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 3560 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 3561 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
3562 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
6aa8b732
AK		 3563};
3564
3565static const int kvm_vmx_max_exit_handlers =
50a3485c 3566 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732
AK		 3567
3568/*
3569 * The guest has exited. See if we can fix it or if we need userspace
3570 * assistance.
3571 */
851ba692 3572static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 3573{
29bd8a78 3574 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 3575 u32 exit_reason = vmx->exit_reason;
1155f76a 3576 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 3577
229456fc 3578 trace_kvm_exit(exit_reason, kvm_rip_read(vcpu));
2714d1d3 3579
80ced186
MG		 3580 /* If guest state is invalid, start emulating */
3581 if (vmx->emulation_required && emulate_invalid_guest_state)
3582 return handle_invalid_guest_state(vcpu);
1d5a4d9b 3583
1439442c
SY		 3584 /* Access CR3 don't cause VMExit in paging mode, so we need
3585 * to sync with guest real CR3. */
6de4f3ad 3586 if (enable_ept && is_paging(vcpu))
1439442c 3587 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
1439442c 3588
29bd8a78 3589 if (unlikely(vmx->fail)) {
851ba692
AK		 3590 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3591 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 3592 = vmcs_read32(VM_INSTRUCTION_ERROR);
3593 return 0;
3594 }
6aa8b732 3595
d77c26fc 3596 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 3597 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac
JK		 3598 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3599 exit_reason != EXIT_REASON_TASK_SWITCH))
3600 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3601 "(0x%x) and exit reason is 0x%x\n",
3602 __func__, vectoring_info, exit_reason);
3b86cd99
JK		 3603
3604 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
c4282df9 3605 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 3606 vmx->soft_vnmi_blocked = 0;
3b86cd99 3607 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 3608 vcpu->arch.nmi_pending) {
3b86cd99
JK		 3609 /*
3610 * This CPU don't support us in finding the end of an
3611 * NMI-blocked window if the guest runs with IRQs
3612 * disabled. So we pull the trigger after 1 s of
3613 * futile waiting, but inform the user about this.
3614 */
3615 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3616 "state on VCPU %d after 1 s timeout\n",
3617 __func__, vcpu->vcpu_id);
3618 vmx->soft_vnmi_blocked = 0;
3b86cd99 3619 }
3b86cd99
JK		 3620 }
3621
6aa8b732
AK		 3622 if (exit_reason < kvm_vmx_max_exit_handlers
3623 && kvm_vmx_exit_handlers[exit_reason])
851ba692 3624 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 3625 else {
851ba692
AK		 3626 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3627 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 3628 }
3629 return 0;
3630}
3631
95ba8273 3632static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 3633{
95ba8273 3634 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 3635 vmcs_write32(TPR_THRESHOLD, 0);
3636 return;
3637 }
3638
95ba8273 3639 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 3640}
3641
cf393f75
AK		 3642static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3643{
3644 u32 exit_intr_info;
7b4a25cb 3645 u32 idt_vectoring_info = vmx->idt_vectoring_info;
cf393f75
AK		 3646 bool unblock_nmi;
3647 u8 vector;
668f612f
AK		 3648 int type;
3649 bool idtv_info_valid;
cf393f75
AK		 3650
3651 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
20f65983 3652
a0861c02
AK		 3653 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
3654
3655 /* Handle machine checks before interrupts are enabled */
3656 if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3657 || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3658 && is_machine_check(exit_intr_info)))
3659 kvm_machine_check();
3660
20f65983
GN		 3661 /* We need to handle NMIs before interrupts are enabled */
3662 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
229456fc 3663 (exit_intr_info & INTR_INFO_VALID_MASK))
20f65983 3664 asm("int $2");
20f65983
GN		 3665
3666 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3667
cf393f75
AK		 3668 if (cpu_has_virtual_nmis()) {
3669 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3670 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3671 /*
7b4a25cb 3672 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 3673 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3674 * a guest IRET fault.
7b4a25cb
GN		 3675 * SDM 3: 23.2.2 (September 2008)
3676 * Bit 12 is undefined in any of the following cases:
3677 * If the VM exit sets the valid bit in the IDT-vectoring
3678 * information field.
3679 * If the VM exit is due to a double fault.
cf393f75 3680 */
7b4a25cb
GN		 3681 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3682 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 3683 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3684 GUEST_INTR_STATE_NMI);
3b86cd99
JK		 3685 } else if (unlikely(vmx->soft_vnmi_blocked))
3686 vmx->vnmi_blocked_time +=
3687 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
668f612f 3688
37b96e98
GN		 3689 vmx->vcpu.arch.nmi_injected = false;
3690 kvm_clear_exception_queue(&vmx->vcpu);
3691 kvm_clear_interrupt_queue(&vmx->vcpu);
3692
3693 if (!idtv_info_valid)
3694 return;
3695
668f612f
AK		 3696 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3697 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 3698
64a7ec06 3699 switch (type) {
37b96e98
GN		 3700 case INTR_TYPE_NMI_INTR:
3701 vmx->vcpu.arch.nmi_injected = true;
668f612f 3702 /*
7b4a25cb 3703 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 3704 * Clear bit "block by NMI" before VM entry if a NMI
3705 * delivery faulted.
668f612f 3706 */
37b96e98
GN		 3707 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3708 GUEST_INTR_STATE_NMI);
3709 break;
37b96e98 3710 case INTR_TYPE_SOFT_EXCEPTION:
66fd3f7f
GN		 3711 vmx->vcpu.arch.event_exit_inst_len =
3712 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3713 /* fall through */
3714 case INTR_TYPE_HARD_EXCEPTION:
35920a35 3715 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
37b96e98
GN		 3716 u32 err = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3717 kvm_queue_exception_e(&vmx->vcpu, vector, err);
35920a35
AK		 3718 } else
3719 kvm_queue_exception(&vmx->vcpu, vector);
37b96e98 3720 break;
66fd3f7f
GN		 3721 case INTR_TYPE_SOFT_INTR:
3722 vmx->vcpu.arch.event_exit_inst_len =
3723 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3724 /* fall through */
37b96e98 3725 case INTR_TYPE_EXT_INTR:
66fd3f7f
GN		 3726 kvm_queue_interrupt(&vmx->vcpu, vector,
3727 type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 3728 break;
3729 default:
3730 break;
f7d9238f 3731 }
cf393f75
AK		 3732}
3733
9c8cba37
AK		 3734/*
3735 * Failure to inject an interrupt should give us the information
3736 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
3737 * when fetching the interrupt redirection bitmap in the real-mode
3738 * tss, this doesn't happen. So we do it ourselves.
3739 */
3740static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3741{
3742 vmx->rmode.irq.pending = 0;
5fdbf976 3743 if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
9c8cba37 3744 return;
5fdbf976 3745 kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
9c8cba37
AK		 3746 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3747 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3748 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3749 return;
3750 }
3751 vmx->idt_vectoring_info =
3752 VECTORING_INFO_VALID_MASK
3753 | INTR_TYPE_EXT_INTR
3754 | vmx->rmode.irq.vector;
3755}
3756
c801949d
AK		 3757#ifdef CONFIG_X86_64
3758#define R "r"
3759#define Q "q"
3760#else
3761#define R "e"
3762#define Q "l"
3763#endif
3764
851ba692 3765static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 3766{
a2fa3e9f 3767 struct vcpu_vmx *vmx = to_vmx(vcpu);
e6adf283 3768
3b86cd99
JK		 3769 /* Record the guest's net vcpu time for enforced NMI injections. */
3770 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3771 vmx->entry_time = ktime_get();
3772
80ced186
MG		 3773 /* Don't enter VMX if guest state is invalid, let the exit handler
3774 start emulation until we arrive back to a valid state */
3775 if (vmx->emulation_required && emulate_invalid_guest_state)
a89a8fb9 3776 return;
a89a8fb9 3777
5fdbf976
MT		 3778 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3779 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3780 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3781 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3782
787ff736
GN		 3783 /* When single-stepping over STI and MOV SS, we must clear the
3784 * corresponding interruptibility bits in the guest state. Otherwise
3785 * vmentry fails as it then expects bit 14 (BS) in pending debug
3786 * exceptions being set, but that's not correct for the guest debugging
3787 * case. */
3788 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3789 vmx_set_interrupt_shadow(vcpu, 0);
3790
e6adf283
AK		 3791 /*
3792 * Loading guest fpu may have cleared host cr0.ts
3793 */
3794 vmcs_writel(HOST_CR0, read_cr0());
3795
d77c26fc 3796 asm(
6aa8b732 3797 /* Store host registers */
c801949d
AK		 3798 "push %%"R"dx; push %%"R"bp;"
3799 "push %%"R"cx \n\t"
313dbd49
AK		 3800 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3801 "je 1f \n\t"
3802 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
4ecac3fd 3803 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 3804 "1: \n\t"
d3edefc0
AK		 3805 /* Reload cr2 if changed */
3806 "mov %c[cr2](%0), %%"R"ax \n\t"
3807 "mov %%cr2, %%"R"dx \n\t"
3808 "cmp %%"R"ax, %%"R"dx \n\t"
3809 "je 2f \n\t"
3810 "mov %%"R"ax, %%cr2 \n\t"
3811 "2: \n\t"
6aa8b732 3812 /* Check if vmlaunch of vmresume is needed */
e08aa78a 3813 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 3814 /* Load guest registers. Don't clobber flags. */
c801949d
AK		 3815 "mov %c[rax](%0), %%"R"ax \n\t"
3816 "mov %c[rbx](%0), %%"R"bx \n\t"
3817 "mov %c[rdx](%0), %%"R"dx \n\t"
3818 "mov %c[rsi](%0), %%"R"si \n\t"
3819 "mov %c[rdi](%0), %%"R"di \n\t"
3820 "mov %c[rbp](%0), %%"R"bp \n\t"
05b3e0c2 3821#ifdef CONFIG_X86_64
e08aa78a
AK		 3822 "mov %c[r8](%0), %%r8 \n\t"
3823 "mov %c[r9](%0), %%r9 \n\t"
3824 "mov %c[r10](%0), %%r10 \n\t"
3825 "mov %c[r11](%0), %%r11 \n\t"
3826 "mov %c[r12](%0), %%r12 \n\t"
3827 "mov %c[r13](%0), %%r13 \n\t"
3828 "mov %c[r14](%0), %%r14 \n\t"
3829 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 3830#endif
c801949d
AK		 3831 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3832
6aa8b732 3833 /* Enter guest mode */
cd2276a7 3834 "jne .Llaunched \n\t"
4ecac3fd 3835 __ex(ASM_VMX_VMLAUNCH) "\n\t"
cd2276a7 3836 "jmp .Lkvm_vmx_return \n\t"
4ecac3fd 3837 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
cd2276a7 3838 ".Lkvm_vmx_return: "
6aa8b732 3839 /* Save guest registers, load host registers, keep flags */
c801949d
AK		 3840 "xchg %0, (%%"R"sp) \n\t"
3841 "mov %%"R"ax, %c[rax](%0) \n\t"
3842 "mov %%"R"bx, %c[rbx](%0) \n\t"
3843 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3844 "mov %%"R"dx, %c[rdx](%0) \n\t"
3845 "mov %%"R"si, %c[rsi](%0) \n\t"
3846 "mov %%"R"di, %c[rdi](%0) \n\t"
3847 "mov %%"R"bp, %c[rbp](%0) \n\t"
05b3e0c2 3848#ifdef CONFIG_X86_64
e08aa78a
AK		 3849 "mov %%r8, %c[r8](%0) \n\t"
3850 "mov %%r9, %c[r9](%0) \n\t"
3851 "mov %%r10, %c[r10](%0) \n\t"
3852 "mov %%r11, %c[r11](%0) \n\t"
3853 "mov %%r12, %c[r12](%0) \n\t"
3854 "mov %%r13, %c[r13](%0) \n\t"
3855 "mov %%r14, %c[r14](%0) \n\t"
3856 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 3857#endif
c801949d
AK		 3858 "mov %%cr2, %%"R"ax \n\t"
3859 "mov %%"R"ax, %c[cr2](%0) \n\t"
3860
3861 "pop %%"R"bp; pop %%"R"bp; pop %%"R"dx \n\t"
e08aa78a
AK		 3862 "setbe %c[fail](%0) \n\t"
3863 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3864 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3865 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 3866 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 3867 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3868 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3869 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3870 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3871 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3872 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3873 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 3874#ifdef CONFIG_X86_64
ad312c7c
ZX		 3875 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3876 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3877 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3878 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3879 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3880 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3881 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3882 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 3883#endif
ad312c7c 3884 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
c2036300 3885 : "cc", "memory"
c801949d 3886 , R"bx", R"di", R"si"
c2036300 3887#ifdef CONFIG_X86_64
c2036300
LV		 3888 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3889#endif
3890 );
6aa8b732 3891
6de4f3ad
AK		 3892 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
3893 | (1 << VCPU_EXREG_PDPTR));
5fdbf976
MT		 3894 vcpu->arch.regs_dirty = 0;
3895
1155f76a 3896 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9c8cba37
AK		 3897 if (vmx->rmode.irq.pending)
3898 fixup_rmode_irq(vmx);
1155f76a 3899
d77c26fc 3900 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
15ad7146 3901 vmx->launched = 1;
1b6269db 3902
cf393f75 3903 vmx_complete_interrupts(vmx);
6aa8b732
AK		 3904}
3905
c801949d
AK		 3906#undef R
3907#undef Q
3908
6aa8b732
AK		 3909static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3910{
a2fa3e9f
GH		 3911 struct vcpu_vmx *vmx = to_vmx(vcpu);
3912
3913 if (vmx->vmcs) {
543e4243 3914 vcpu_clear(vmx);
a2fa3e9f
GH		 3915 free_vmcs(vmx->vmcs);
3916 vmx->vmcs = NULL;
6aa8b732
AK		 3917 }
3918}
3919
3920static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3921{
fb3f0f51
RR		 3922 struct vcpu_vmx *vmx = to_vmx(vcpu);
3923
2384d2b3
SY		 3924 spin_lock(&vmx_vpid_lock);
3925 if (vmx->vpid != 0)
3926 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3927 spin_unlock(&vmx_vpid_lock);
6aa8b732 3928 vmx_free_vmcs(vcpu);
fb3f0f51
RR		 3929 kfree(vmx->guest_msrs);
3930 kvm_vcpu_uninit(vcpu);
a4770347 3931 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 3932}
3933
fb3f0f51 3934static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 3935{
fb3f0f51 3936 int err;
c16f862d 3937 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 3938 int cpu;
6aa8b732 3939
a2fa3e9f 3940 if (!vmx)
fb3f0f51
RR		 3941 return ERR_PTR(-ENOMEM);
3942
2384d2b3
SY		 3943 allocate_vpid(vmx);
3944
fb3f0f51
RR		 3945 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3946 if (err)
3947 goto free_vcpu;
965b58a5 3948
a2fa3e9f 3949 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
fb3f0f51
RR		 3950 if (!vmx->guest_msrs) {
3951 err = -ENOMEM;
3952 goto uninit_vcpu;
3953 }
965b58a5 3954
a2fa3e9f
GH		 3955 vmx->vmcs = alloc_vmcs();
3956 if (!vmx->vmcs)
fb3f0f51 3957 goto free_msrs;
a2fa3e9f
GH		 3958
3959 vmcs_clear(vmx->vmcs);
3960
15ad7146
AK		 3961 cpu = get_cpu();
3962 vmx_vcpu_load(&vmx->vcpu, cpu);
8b9cf98c 3963 err = vmx_vcpu_setup(vmx);
fb3f0f51 3964 vmx_vcpu_put(&vmx->vcpu);
15ad7146 3965 put_cpu();
fb3f0f51
RR		 3966 if (err)
3967 goto free_vmcs;
5e4a0b3c
MT		 3968 if (vm_need_virtualize_apic_accesses(kvm))
3969 if (alloc_apic_access_page(kvm) != 0)
3970 goto free_vmcs;
fb3f0f51 3971
b927a3ce
SY		 3972 if (enable_ept) {
3973 if (!kvm->arch.ept_identity_map_addr)
3974 kvm->arch.ept_identity_map_addr =
3975 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
b7ebfb05
SY		 3976 if (alloc_identity_pagetable(kvm) != 0)
3977 goto free_vmcs;
b927a3ce 3978 }
b7ebfb05 3979
fb3f0f51
RR		 3980 return &vmx->vcpu;
3981
3982free_vmcs:
3983 free_vmcs(vmx->vmcs);
3984free_msrs:
fb3f0f51
RR		 3985 kfree(vmx->guest_msrs);
3986uninit_vcpu:
3987 kvm_vcpu_uninit(&vmx->vcpu);
3988free_vcpu:
a4770347 3989 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 3990 return ERR_PTR(err);
6aa8b732
AK		 3991}
3992
002c7f7c
YS		 3993static void __init vmx_check_processor_compat(void *rtn)
3994{
3995 struct vmcs_config vmcs_conf;
3996
3997 *(int *)rtn = 0;
3998 if (setup_vmcs_config(&vmcs_conf) < 0)
3999 *(int *)rtn = -EIO;
4000 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
4001 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
4002 smp_processor_id());
4003 *(int *)rtn = -EIO;
4004 }
4005}
4006
67253af5
SY		 4007static int get_ept_level(void)
4008{
4009 return VMX_EPT_DEFAULT_GAW + 1;
4010}
4011
4b12f0de 4012static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 4013{
4b12f0de
SY		 4014 u64 ret;
4015
522c68c4
SY		 4016 /* For VT-d and EPT combination
4017 * 1. MMIO: always map as UC
4018 * 2. EPT with VT-d:
4019 * a. VT-d without snooping control feature: can't guarantee the
4020 * result, try to trust guest.
4021 * b. VT-d with snooping control feature: snooping control feature of
4022 * VT-d engine can guarantee the cache correctness. Just set it
4023 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 4024 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 4025 * consistent with host MTRR
4026 */
4b12f0de
SY		 4027 if (is_mmio)
4028 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 4029 else if (vcpu->kvm->arch.iommu_domain &&
4030 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
4031 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
4032 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 4033 else
522c68c4 4034 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 4035 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 4036
4037 return ret;
64d4d521
SY		 4038}
4039
f4c9e87c
AK		 4040#define _ER(x) { EXIT_REASON_##x, #x }
4041
229456fc 4042static const struct trace_print_flags vmx_exit_reasons_str[] = {
f4c9e87c
AK		 4043 _ER(EXCEPTION_NMI),
4044 _ER(EXTERNAL_INTERRUPT),
4045 _ER(TRIPLE_FAULT),
4046 _ER(PENDING_INTERRUPT),
4047 _ER(NMI_WINDOW),
4048 _ER(TASK_SWITCH),
4049 _ER(CPUID),
4050 _ER(HLT),
4051 _ER(INVLPG),
4052 _ER(RDPMC),
4053 _ER(RDTSC),
4054 _ER(VMCALL),
4055 _ER(VMCLEAR),
4056 _ER(VMLAUNCH),
4057 _ER(VMPTRLD),
4058 _ER(VMPTRST),
4059 _ER(VMREAD),
4060 _ER(VMRESUME),
4061 _ER(VMWRITE),
4062 _ER(VMOFF),
4063 _ER(VMON),
4064 _ER(CR_ACCESS),
4065 _ER(DR_ACCESS),
4066 _ER(IO_INSTRUCTION),
4067 _ER(MSR_READ),
4068 _ER(MSR_WRITE),
4069 _ER(MWAIT_INSTRUCTION),
4070 _ER(MONITOR_INSTRUCTION),
4071 _ER(PAUSE_INSTRUCTION),
4072 _ER(MCE_DURING_VMENTRY),
4073 _ER(TPR_BELOW_THRESHOLD),
4074 _ER(APIC_ACCESS),
4075 _ER(EPT_VIOLATION),
4076 _ER(EPT_MISCONFIG),
4077 _ER(WBINVD),
229456fc
MT		 4078 { -1, NULL }
4079};
4080
f4c9e87c
AK		 4081#undef _ER
4082
17cc3935 4083static int vmx_get_lpage_level(void)
344f414f 4084{
878403b7
SY		 4085 if (enable_ept && !cpu_has_vmx_ept_1g_page())
4086 return PT_DIRECTORY_LEVEL;
4087 else
4088 /* For shadow and EPT supported 1GB page */
4089 return PT_PDPE_LEVEL;
344f414f
JR		 4090}
4091
4e47c7a6
SY		 4092static inline u32 bit(int bitno)
4093{
4094 return 1 << (bitno & 31);
4095}
4096
0e851880
SY		 4097static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
4098{
4e47c7a6
SY		 4099 struct kvm_cpuid_entry2 *best;
4100 struct vcpu_vmx *vmx = to_vmx(vcpu);
4101 u32 exec_control;
4102
4103 vmx->rdtscp_enabled = false;
4104 if (vmx_rdtscp_supported()) {
4105 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
4106 if (exec_control & SECONDARY_EXEC_RDTSCP) {
4107 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
4108 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
4109 vmx->rdtscp_enabled = true;
4110 else {
4111 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4112 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4113 exec_control);
4114 }
4115 }
4116 }
0e851880
SY		 4117}
4118
cbdd1bea 4119static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 4120 .cpu_has_kvm_support = cpu_has_kvm_support,
4121 .disabled_by_bios = vmx_disabled_by_bios,
4122 .hardware_setup = hardware_setup,
4123 .hardware_unsetup = hardware_unsetup,
002c7f7c 4124 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 4125 .hardware_enable = hardware_enable,
4126 .hardware_disable = hardware_disable,
04547156 4127 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 4128
4129 .vcpu_create = vmx_create_vcpu,
4130 .vcpu_free = vmx_free_vcpu,
04d2cc77 4131 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 4132
04d2cc77 4133 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 4134 .vcpu_load = vmx_vcpu_load,
4135 .vcpu_put = vmx_vcpu_put,
4136
4137 .set_guest_debug = set_guest_debug,
4138 .get_msr = vmx_get_msr,
4139 .set_msr = vmx_set_msr,
4140 .get_segment_base = vmx_get_segment_base,
4141 .get_segment = vmx_get_segment,
4142 .set_segment = vmx_set_segment,
2e4d2653 4143 .get_cpl = vmx_get_cpl,
6aa8b732 4144 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 4145 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
25c4c276 4146 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 4147 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 4148 .set_cr3 = vmx_set_cr3,
4149 .set_cr4 = vmx_set_cr4,
6aa8b732 4150 .set_efer = vmx_set_efer,
6aa8b732
AK		 4151 .get_idt = vmx_get_idt,
4152 .set_idt = vmx_set_idt,
4153 .get_gdt = vmx_get_gdt,
4154 .set_gdt = vmx_set_gdt,
5fdbf976 4155 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 4156 .get_rflags = vmx_get_rflags,
4157 .set_rflags = vmx_set_rflags,
ebcbab4c 4158 .fpu_activate = vmx_fpu_activate,
02daab21 4159 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 4160
4161 .tlb_flush = vmx_flush_tlb,
6aa8b732 4162
6aa8b732 4163 .run = vmx_vcpu_run,
6062d012 4164 .handle_exit = vmx_handle_exit,
6aa8b732 4165 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 4166 .set_interrupt_shadow = vmx_set_interrupt_shadow,
4167 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 4168 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 4169 .set_irq = vmx_inject_irq,
95ba8273 4170 .set_nmi = vmx_inject_nmi,
298101da 4171 .queue_exception = vmx_queue_exception,
78646121 4172 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 4173 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 4174 .get_nmi_mask = vmx_get_nmi_mask,
4175 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 4176 .enable_nmi_window = enable_nmi_window,
4177 .enable_irq_window = enable_irq_window,
4178 .update_cr8_intercept = update_cr8_intercept,
95ba8273 4179
cbc94022 4180 .set_tss_addr = vmx_set_tss_addr,
67253af5 4181 .get_tdp_level = get_ept_level,
4b12f0de 4182 .get_mt_mask = vmx_get_mt_mask,
229456fc
MT		 4183
4184 .exit_reasons_str = vmx_exit_reasons_str,
17cc3935 4185 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 4186
4187 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 4188
4189 .rdtscp_supported = vmx_rdtscp_supported,
6aa8b732
AK		 4190};
4191
4192static int __init vmx_init(void)
4193{
26bb0981
AK		 4194 int r, i;
4195
4196 rdmsrl_safe(MSR_EFER, &host_efer);
4197
4198 for (i = 0; i < NR_VMX_MSR; ++i)
4199 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 4200
3e7c73e9 4201 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 4202 if (!vmx_io_bitmap_a)
4203 return -ENOMEM;
4204
3e7c73e9 4205 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 4206 if (!vmx_io_bitmap_b) {
4207 r = -ENOMEM;
4208 goto out;
4209 }
4210
5897297b
AK		 4211 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4212 if (!vmx_msr_bitmap_legacy) {
25c5f225
SY		 4213 r = -ENOMEM;
4214 goto out1;
4215 }
4216
5897297b
AK		 4217 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4218 if (!vmx_msr_bitmap_longmode) {
4219 r = -ENOMEM;
4220 goto out2;
4221 }
4222
fdef3ad1
HQ		 4223 /*
4224 * Allow direct access to the PC debug port (it is often used for I/O
4225 * delays, but the vmexits simply slow things down).
4226 */
3e7c73e9
AK		 4227 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4228 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 4229
3e7c73e9 4230 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 4231
5897297b
AK		 4232 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4233 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 4234
2384d2b3
SY		 4235 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4236
cb498ea2 4237 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 4238 if (r)
5897297b 4239 goto out3;
25c5f225 4240
5897297b
AK		 4241 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4242 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4243 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4244 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4245 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4246 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
fdef3ad1 4247
089d034e 4248 if (enable_ept) {
1439442c 4249 bypass_guest_pf = 0;
5fdbcb9d 4250 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
2aaf69dc 4251 VMX_EPT_WRITABLE_MASK);
534e38b4 4252 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4b12f0de 4253 VMX_EPT_EXECUTABLE_MASK);
5fdbcb9d
SY		 4254 kvm_enable_tdp();
4255 } else
4256 kvm_disable_tdp();
1439442c 4257
c7addb90
AK		 4258 if (bypass_guest_pf)
4259 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4260
fdef3ad1
HQ		 4261 return 0;
4262
5897297b
AK		 4263out3:
4264 free_page((unsigned long)vmx_msr_bitmap_longmode);
25c5f225 4265out2:
5897297b 4266 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 4267out1:
3e7c73e9 4268 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 4269out:
3e7c73e9 4270 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 4271 return r;
6aa8b732
AK		 4272}
4273
4274static void __exit vmx_exit(void)
4275{
5897297b
AK		 4276 free_page((unsigned long)vmx_msr_bitmap_legacy);
4277 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 4278 free_page((unsigned long)vmx_io_bitmap_b);
4279 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 4280
cb498ea2 4281 kvm_exit();
6aa8b732
AK		 4282}
4283
4284module_init(vmx_init)
4285module_exit(vmx_exit)
kernel source for telekom puls (alcatel/mediatek)