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KVM: VMX: Allow the guest to own some cr0 bits
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 *
9 * Authors:
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
85f455f7 18#include "irq.h"
1d737c8a 19#include "mmu.h"
e495606d 20
edf88417 21#include <linux/kvm_host.h>
6aa8b732 22#include <linux/module.h>
9d8f549d 23#include <linux/kernel.h>
6aa8b732
AK		 24#include <linux/mm.h>
25#include <linux/highmem.h>
e8edc6e0 26#include <linux/sched.h>
c7addb90 27#include <linux/moduleparam.h>
229456fc 28#include <linux/ftrace_event.h>
5fdbf976 29#include "kvm_cache_regs.h"
35920a35 30#include "x86.h"
e495606d 31
6aa8b732 32#include <asm/io.h>
3b3be0d1 33#include <asm/desc.h>
13673a90 34#include <asm/vmx.h>
6210e37b 35#include <asm/virtext.h>
a0861c02 36#include <asm/mce.h>
6aa8b732 37
229456fc
MT		 38#include "trace.h"
39
4ecac3fd
AK		 40#define __ex(x) __kvm_handle_fault_on_reboot(x)
41
6aa8b732
AK		 42MODULE_AUTHOR("Qumranet");
43MODULE_LICENSE("GPL");
44
4462d21a 45static int __read_mostly bypass_guest_pf = 1;
c1f8bc04 46module_param(bypass_guest_pf, bool, S_IRUGO);
c7addb90 47
4462d21a 48static int __read_mostly enable_vpid = 1;
736caefe 49module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 50
4462d21a 51static int __read_mostly flexpriority_enabled = 1;
736caefe 52module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 53
4462d21a 54static int __read_mostly enable_ept = 1;
736caefe 55module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 56
3a624e29
NK		 57static int __read_mostly enable_unrestricted_guest = 1;
58module_param_named(unrestricted_guest,
59 enable_unrestricted_guest, bool, S_IRUGO);
60
4462d21a 61static int __read_mostly emulate_invalid_guest_state = 0;
c1f8bc04 62module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 63
cdc0e244
AK		 64#define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
65 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
66#define KVM_GUEST_CR0_MASK \
67 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
68#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
69 (X86_CR0_WP | X86_CR0_NE | X86_CR0_TS | X86_CR0_MP)
70#define KVM_VM_CR0_ALWAYS_ON \
71 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 72#define KVM_CR4_GUEST_OWNED_BITS \
73 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
74 | X86_CR4_OSXMMEXCPT)
75
cdc0e244
AK		 76#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
77#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
78
4b8d54f9
ZE		 79/*
80 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
81 * ple_gap: upper bound on the amount of time between two successive
82 * executions of PAUSE in a loop. Also indicate if ple enabled.
83 * According to test, this time is usually small than 41 cycles.
84 * ple_window: upper bound on the amount of time a guest is allowed to execute
85 * in a PAUSE loop. Tests indicate that most spinlocks are held for
86 * less than 2^12 cycles
87 * Time is measured based on a counter that runs at the same rate as the TSC,
88 * refer SDM volume 3b section 21.6.13 & 22.1.3.
89 */
90#define KVM_VMX_DEFAULT_PLE_GAP 41
91#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
92static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
93module_param(ple_gap, int, S_IRUGO);
94
95static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
96module_param(ple_window, int, S_IRUGO);
97
a2fa3e9f
GH		 98struct vmcs {
99 u32 revision_id;
100 u32 abort;
101 char data[0];
102};
103
26bb0981
AK		 104struct shared_msr_entry {
105 unsigned index;
106 u64 data;
d5696725 107 u64 mask;
26bb0981
AK		 108};
109
a2fa3e9f 110struct vcpu_vmx {
fb3f0f51 111 struct kvm_vcpu vcpu;
543e4243 112 struct list_head local_vcpus_link;
313dbd49 113 unsigned long host_rsp;
a2fa3e9f 114 int launched;
29bd8a78 115 u8 fail;
1155f76a 116 u32 idt_vectoring_info;
26bb0981 117 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 118 int nmsrs;
119 int save_nmsrs;
a2fa3e9f 120#ifdef CONFIG_X86_64
44ea2b17
AK		 121 u64 msr_host_kernel_gs_base;
122 u64 msr_guest_kernel_gs_base;
a2fa3e9f
GH		 123#endif
124 struct vmcs *vmcs;
125 struct {
126 int loaded;
127 u16 fs_sel, gs_sel, ldt_sel;
152d3f2f
LV		 128 int gs_ldt_reload_needed;
129 int fs_reload_needed;
d77c26fc 130 } host_state;
9c8cba37 131 struct {
7ffd92c5
AK		 132 int vm86_active;
133 u8 save_iopl;
134 struct kvm_save_segment {
135 u16 selector;
136 unsigned long base;
137 u32 limit;
138 u32 ar;
139 } tr, es, ds, fs, gs;
9c8cba37
AK		 140 struct {
141 bool pending;
142 u8 vector;
143 unsigned rip;
144 } irq;
145 } rmode;
2384d2b3 146 int vpid;
04fa4d32 147 bool emulation_required;
3b86cd99
JK		 148
149 /* Support for vnmi-less CPUs */
150 int soft_vnmi_blocked;
151 ktime_t entry_time;
152 s64 vnmi_blocked_time;
a0861c02 153 u32 exit_reason;
4e47c7a6
SY		 154
155 bool rdtscp_enabled;
a2fa3e9f
GH		 156};
157
158static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
159{
fb3f0f51 160 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 161}
162
b7ebfb05 163static int init_rmode(struct kvm *kvm);
4e1096d2 164static u64 construct_eptp(unsigned long root_hpa);
75880a01 165
6aa8b732
AK		 166static DEFINE_PER_CPU(struct vmcs *, vmxarea);
167static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
543e4243 168static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
6aa8b732 169
3e7c73e9
AK		 170static unsigned long *vmx_io_bitmap_a;
171static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 172static unsigned long *vmx_msr_bitmap_legacy;
173static unsigned long *vmx_msr_bitmap_longmode;
fdef3ad1 174
2384d2b3
SY		 175static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
176static DEFINE_SPINLOCK(vmx_vpid_lock);
177
1c3d14fe 178static struct vmcs_config {
6aa8b732
AK		 179 int size;
180 int order;
181 u32 revision_id;
1c3d14fe
YS		 182 u32 pin_based_exec_ctrl;
183 u32 cpu_based_exec_ctrl;
f78e0e2e 184 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 185 u32 vmexit_ctrl;
186 u32 vmentry_ctrl;
187} vmcs_config;
6aa8b732 188
efff9e53 189static struct vmx_capability {
d56f546d
SY		 190 u32 ept;
191 u32 vpid;
192} vmx_capability;
193
6aa8b732
AK		 194#define VMX_SEGMENT_FIELD(seg) \
195 [VCPU_SREG_##seg] = { \
196 .selector = GUEST_##seg##_SELECTOR, \
197 .base = GUEST_##seg##_BASE, \
198 .limit = GUEST_##seg##_LIMIT, \
199 .ar_bytes = GUEST_##seg##_AR_BYTES, \
200 }
201
202static struct kvm_vmx_segment_field {
203 unsigned selector;
204 unsigned base;
205 unsigned limit;
206 unsigned ar_bytes;
207} kvm_vmx_segment_fields[] = {
208 VMX_SEGMENT_FIELD(CS),
209 VMX_SEGMENT_FIELD(DS),
210 VMX_SEGMENT_FIELD(ES),
211 VMX_SEGMENT_FIELD(FS),
212 VMX_SEGMENT_FIELD(GS),
213 VMX_SEGMENT_FIELD(SS),
214 VMX_SEGMENT_FIELD(TR),
215 VMX_SEGMENT_FIELD(LDTR),
216};
217
26bb0981
AK		 218static u64 host_efer;
219
6de4f3ad
AK		 220static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
221
4d56c8a7
AK		 222/*
223 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
224 * away by decrementing the array size.
225 */
6aa8b732 226static const u32 vmx_msr_index[] = {
05b3e0c2 227#ifdef CONFIG_X86_64
44ea2b17 228 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 229#endif
4e47c7a6 230 MSR_EFER, MSR_TSC_AUX, MSR_K6_STAR,
6aa8b732 231};
9d8f549d 232#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 233
6aa8b732
AK		 234static inline int is_page_fault(u32 intr_info)
235{
236 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
237 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 238 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 239}
240
2ab455cc
AL		 241static inline int is_no_device(u32 intr_info)
242{
243 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
244 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 245 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 246}
247
7aa81cc0
AL		 248static inline int is_invalid_opcode(u32 intr_info)
249{
250 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
251 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 252 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 253}
254
6aa8b732
AK		 255static inline int is_external_interrupt(u32 intr_info)
256{
257 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
258 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
259}
260
a0861c02
AK		 261static inline int is_machine_check(u32 intr_info)
262{
263 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
264 INTR_INFO_VALID_MASK)) ==
265 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
266}
267
25c5f225
SY		 268static inline int cpu_has_vmx_msr_bitmap(void)
269{
04547156 270 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 271}
272
6e5d865c
YS		 273static inline int cpu_has_vmx_tpr_shadow(void)
274{
04547156 275 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 276}
277
278static inline int vm_need_tpr_shadow(struct kvm *kvm)
279{
04547156 280 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 281}
282
f78e0e2e
SY		 283static inline int cpu_has_secondary_exec_ctrls(void)
284{
04547156
SY		 285 return vmcs_config.cpu_based_exec_ctrl &
286 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 287}
288
774ead3a 289static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 290{
04547156
SY		 291 return vmcs_config.cpu_based_2nd_exec_ctrl &
292 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
293}
294
295static inline bool cpu_has_vmx_flexpriority(void)
296{
297 return cpu_has_vmx_tpr_shadow() &&
298 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 299}
300
e799794e
MT		 301static inline bool cpu_has_vmx_ept_execute_only(void)
302{
303 return !!(vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT);
304}
305
306static inline bool cpu_has_vmx_eptp_uncacheable(void)
307{
308 return !!(vmx_capability.ept & VMX_EPTP_UC_BIT);
309}
310
311static inline bool cpu_has_vmx_eptp_writeback(void)
312{
313 return !!(vmx_capability.ept & VMX_EPTP_WB_BIT);
314}
315
316static inline bool cpu_has_vmx_ept_2m_page(void)
317{
318 return !!(vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT);
319}
320
878403b7
SY		 321static inline bool cpu_has_vmx_ept_1g_page(void)
322{
323 return !!(vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT);
324}
325
d56f546d
SY		 326static inline int cpu_has_vmx_invept_individual_addr(void)
327{
04547156 328 return !!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT);
d56f546d
SY		 329}
330
331static inline int cpu_has_vmx_invept_context(void)
332{
04547156 333 return !!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT);
d56f546d
SY		 334}
335
336static inline int cpu_has_vmx_invept_global(void)
337{
04547156 338 return !!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT);
d56f546d
SY		 339}
340
341static inline int cpu_has_vmx_ept(void)
342{
04547156
SY		 343 return vmcs_config.cpu_based_2nd_exec_ctrl &
344 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 345}
346
3a624e29
NK		 347static inline int cpu_has_vmx_unrestricted_guest(void)
348{
349 return vmcs_config.cpu_based_2nd_exec_ctrl &
350 SECONDARY_EXEC_UNRESTRICTED_GUEST;
351}
352
4b8d54f9
ZE		 353static inline int cpu_has_vmx_ple(void)
354{
355 return vmcs_config.cpu_based_2nd_exec_ctrl &
356 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
357}
358
f78e0e2e
SY		 359static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
360{
04547156
SY		 361 return flexpriority_enabled &&
362 (cpu_has_vmx_virtualize_apic_accesses()) &&
363 (irqchip_in_kernel(kvm));
f78e0e2e
SY		 364}
365
2384d2b3
SY		 366static inline int cpu_has_vmx_vpid(void)
367{
04547156
SY		 368 return vmcs_config.cpu_based_2nd_exec_ctrl &
369 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 370}
371
4e47c7a6
SY		 372static inline int cpu_has_vmx_rdtscp(void)
373{
374 return vmcs_config.cpu_based_2nd_exec_ctrl &
375 SECONDARY_EXEC_RDTSCP;
376}
377
f08864b4
SY		 378static inline int cpu_has_virtual_nmis(void)
379{
380 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
381}
382
04547156
SY		 383static inline bool report_flexpriority(void)
384{
385 return flexpriority_enabled;
386}
387
8b9cf98c 388static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 389{
390 int i;
391
a2fa3e9f 392 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 393 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 394 return i;
395 return -1;
396}
397
2384d2b3
SY		 398static inline void __invvpid(int ext, u16 vpid, gva_t gva)
399{
400 struct {
401 u64 vpid : 16;
402 u64 rsvd : 48;
403 u64 gva;
404 } operand = { vpid, 0, gva };
405
4ecac3fd 406 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 407 /* CF==1 or ZF==1 --> rc = -1 */
408 "; ja 1f ; ud2 ; 1:"
409 : : "a"(&operand), "c"(ext) : "cc", "memory");
410}
411
1439442c
SY		 412static inline void __invept(int ext, u64 eptp, gpa_t gpa)
413{
414 struct {
415 u64 eptp, gpa;
416 } operand = {eptp, gpa};
417
4ecac3fd 418 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 419 /* CF==1 or ZF==1 --> rc = -1 */
420 "; ja 1f ; ud2 ; 1:\n"
421 : : "a" (&operand), "c" (ext) : "cc", "memory");
422}
423
26bb0981 424static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 425{
426 int i;
427
8b9cf98c 428 i = __find_msr_index(vmx, msr);
a75beee6 429 if (i >= 0)
a2fa3e9f 430 return &vmx->guest_msrs[i];
8b6d44c7 431 return NULL;
7725f0ba
AK		 432}
433
6aa8b732
AK		 434static void vmcs_clear(struct vmcs *vmcs)
435{
436 u64 phys_addr = __pa(vmcs);
437 u8 error;
438
4ecac3fd 439 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
6aa8b732
AK		 440 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
441 : "cc", "memory");
442 if (error)
443 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
444 vmcs, phys_addr);
445}
446
447static void __vcpu_clear(void *arg)
448{
8b9cf98c 449 struct vcpu_vmx *vmx = arg;
d3b2c338 450 int cpu = raw_smp_processor_id();
6aa8b732 451
8b9cf98c 452 if (vmx->vcpu.cpu == cpu)
a2fa3e9f
GH		 453 vmcs_clear(vmx->vmcs);
454 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
6aa8b732 455 per_cpu(current_vmcs, cpu) = NULL;
ad312c7c 456 rdtscll(vmx->vcpu.arch.host_tsc);
543e4243
AK		 457 list_del(&vmx->local_vcpus_link);
458 vmx->vcpu.cpu = -1;
459 vmx->launched = 0;
6aa8b732
AK		 460}
461
8b9cf98c 462static void vcpu_clear(struct vcpu_vmx *vmx)
8d0be2b3 463{
eae5ecb5
AK		 464 if (vmx->vcpu.cpu == -1)
465 return;
8691e5a8 466 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
8d0be2b3
AK		 467}
468
2384d2b3
SY		 469static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
470{
471 if (vmx->vpid == 0)
472 return;
473
474 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
475}
476
1439442c
SY		 477static inline void ept_sync_global(void)
478{
479 if (cpu_has_vmx_invept_global())
480 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
481}
482
483static inline void ept_sync_context(u64 eptp)
484{
089d034e 485 if (enable_ept) {
1439442c
SY		 486 if (cpu_has_vmx_invept_context())
487 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
488 else
489 ept_sync_global();
490 }
491}
492
493static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
494{
089d034e 495 if (enable_ept) {
1439442c
SY		 496 if (cpu_has_vmx_invept_individual_addr())
497 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
498 eptp, gpa);
499 else
500 ept_sync_context(eptp);
501 }
502}
503
6aa8b732
AK		 504static unsigned long vmcs_readl(unsigned long field)
505{
506 unsigned long value;
507
4ecac3fd 508 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
6aa8b732
AK		 509 : "=a"(value) : "d"(field) : "cc");
510 return value;
511}
512
513static u16 vmcs_read16(unsigned long field)
514{
515 return vmcs_readl(field);
516}
517
518static u32 vmcs_read32(unsigned long field)
519{
520 return vmcs_readl(field);
521}
522
523static u64 vmcs_read64(unsigned long field)
524{
05b3e0c2 525#ifdef CONFIG_X86_64
6aa8b732
AK		 526 return vmcs_readl(field);
527#else
528 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
529#endif
530}
531
e52de1b8
AK		 532static noinline void vmwrite_error(unsigned long field, unsigned long value)
533{
534 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
535 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
536 dump_stack();
537}
538
6aa8b732
AK		 539static void vmcs_writel(unsigned long field, unsigned long value)
540{
541 u8 error;
542
4ecac3fd 543 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 544 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 545 if (unlikely(error))
546 vmwrite_error(field, value);
6aa8b732
AK		 547}
548
549static void vmcs_write16(unsigned long field, u16 value)
550{
551 vmcs_writel(field, value);
552}
553
554static void vmcs_write32(unsigned long field, u32 value)
555{
556 vmcs_writel(field, value);
557}
558
559static void vmcs_write64(unsigned long field, u64 value)
560{
6aa8b732 561 vmcs_writel(field, value);
7682f2d0 562#ifndef CONFIG_X86_64
6aa8b732
AK		 563 asm volatile ("");
564 vmcs_writel(field+1, value >> 32);
565#endif
566}
567
2ab455cc
AL		 568static void vmcs_clear_bits(unsigned long field, u32 mask)
569{
570 vmcs_writel(field, vmcs_readl(field) & ~mask);
571}
572
573static void vmcs_set_bits(unsigned long field, u32 mask)
574{
575 vmcs_writel(field, vmcs_readl(field) | mask);
576}
577
abd3f2d6
AK		 578static void update_exception_bitmap(struct kvm_vcpu *vcpu)
579{
580 u32 eb;
581
a0861c02 582 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR);
abd3f2d6
AK		 583 if (!vcpu->fpu_active)
584 eb |= 1u << NM_VECTOR;
e8a48342
AK		 585 /*
586 * Unconditionally intercept #DB so we can maintain dr6 without
587 * reading it every exit.
588 */
589 eb |= 1u << DB_VECTOR;
d0bfb940 590 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
d0bfb940
JK		 591 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
592 eb |= 1u << BP_VECTOR;
593 }
7ffd92c5 594 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 595 eb = ~0;
089d034e 596 if (enable_ept)
1439442c 597 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
abd3f2d6
AK		 598 vmcs_write32(EXCEPTION_BITMAP, eb);
599}
600
33ed6329
AK		 601static void reload_tss(void)
602{
33ed6329
AK		 603 /*
604 * VT restores TR but not its size. Useless.
605 */
606 struct descriptor_table gdt;
a5f61300 607 struct desc_struct *descs;
33ed6329 608
d6e88aec 609 kvm_get_gdt(&gdt);
33ed6329
AK		 610 descs = (void *)gdt.base;
611 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
612 load_TR_desc();
33ed6329
AK		 613}
614
92c0d900 615static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 616{
3a34a881 617 u64 guest_efer;
51c6cf66
AK		 618 u64 ignore_bits;
619
26bb0981 620 guest_efer = vmx->vcpu.arch.shadow_efer;
3a34a881 621
51c6cf66
AK		 622 /*
623 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
624 * outside long mode
625 */
626 ignore_bits = EFER_NX | EFER_SCE;
627#ifdef CONFIG_X86_64
628 ignore_bits |= EFER_LMA | EFER_LME;
629 /* SCE is meaningful only in long mode on Intel */
630 if (guest_efer & EFER_LMA)
631 ignore_bits &= ~(u64)EFER_SCE;
632#endif
51c6cf66
AK		 633 guest_efer &= ~ignore_bits;
634 guest_efer |= host_efer & ignore_bits;
26bb0981 635 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 636 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
26bb0981 637 return true;
51c6cf66
AK		 638}
639
04d2cc77 640static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 641{
04d2cc77 642 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 643 int i;
04d2cc77 644
a2fa3e9f 645 if (vmx->host_state.loaded)
33ed6329
AK		 646 return;
647
a2fa3e9f 648 vmx->host_state.loaded = 1;
33ed6329
AK		 649 /*
650 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
651 * allow segment selectors with cpl > 0 or ti == 1.
652 */
d6e88aec 653 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 654 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
d6e88aec 655 vmx->host_state.fs_sel = kvm_read_fs();
152d3f2f 656 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 657 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 658 vmx->host_state.fs_reload_needed = 0;
659 } else {
33ed6329 660 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 661 vmx->host_state.fs_reload_needed = 1;
33ed6329 662 }
d6e88aec 663 vmx->host_state.gs_sel = kvm_read_gs();
a2fa3e9f
GH		 664 if (!(vmx->host_state.gs_sel & 7))
665 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 666 else {
667 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 668 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 669 }
670
671#ifdef CONFIG_X86_64
672 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
673 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
674#else
a2fa3e9f
GH		 675 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
676 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 677#endif
707c0874
AK		 678
679#ifdef CONFIG_X86_64
44ea2b17
AK		 680 if (is_long_mode(&vmx->vcpu)) {
681 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
682 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
683 }
707c0874 684#endif
26bb0981
AK		 685 for (i = 0; i < vmx->save_nmsrs; ++i)
686 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 687 vmx->guest_msrs[i].data,
688 vmx->guest_msrs[i].mask);
33ed6329
AK		 689}
690
a9b21b62 691static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 692{
15ad7146 693 unsigned long flags;
33ed6329 694
a2fa3e9f 695 if (!vmx->host_state.loaded)
33ed6329
AK		 696 return;
697
e1beb1d3 698 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 699 vmx->host_state.loaded = 0;
152d3f2f 700 if (vmx->host_state.fs_reload_needed)
d6e88aec 701 kvm_load_fs(vmx->host_state.fs_sel);
152d3f2f 702 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 703 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329
AK		 704 /*
705 * If we have to reload gs, we must take care to
706 * preserve our gs base.
707 */
15ad7146 708 local_irq_save(flags);
d6e88aec 709 kvm_load_gs(vmx->host_state.gs_sel);
33ed6329
AK		 710#ifdef CONFIG_X86_64
711 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
712#endif
15ad7146 713 local_irq_restore(flags);
33ed6329 714 }
152d3f2f 715 reload_tss();
44ea2b17
AK		 716#ifdef CONFIG_X86_64
717 if (is_long_mode(&vmx->vcpu)) {
718 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
719 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
720 }
721#endif
33ed6329
AK		 722}
723
a9b21b62
AK		 724static void vmx_load_host_state(struct vcpu_vmx *vmx)
725{
726 preempt_disable();
727 __vmx_load_host_state(vmx);
728 preempt_enable();
729}
730
6aa8b732
AK		 731/*
732 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
733 * vcpu mutex is already taken.
734 */
15ad7146 735static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 736{
a2fa3e9f
GH		 737 struct vcpu_vmx *vmx = to_vmx(vcpu);
738 u64 phys_addr = __pa(vmx->vmcs);
019960ae 739 u64 tsc_this, delta, new_offset;
6aa8b732 740
a3d7f85f 741 if (vcpu->cpu != cpu) {
8b9cf98c 742 vcpu_clear(vmx);
2f599714 743 kvm_migrate_timers(vcpu);
eb5109e3 744 set_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests);
543e4243
AK		 745 local_irq_disable();
746 list_add(&vmx->local_vcpus_link,
747 &per_cpu(vcpus_on_cpu, cpu));
748 local_irq_enable();
a3d7f85f 749 }
6aa8b732 750
a2fa3e9f 751 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
6aa8b732
AK		 752 u8 error;
753
a2fa3e9f 754 per_cpu(current_vmcs, cpu) = vmx->vmcs;
4ecac3fd 755 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
6aa8b732
AK		 756 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
757 : "cc");
758 if (error)
759 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
a2fa3e9f 760 vmx->vmcs, phys_addr);
6aa8b732
AK		 761 }
762
763 if (vcpu->cpu != cpu) {
764 struct descriptor_table dt;
765 unsigned long sysenter_esp;
766
767 vcpu->cpu = cpu;
768 /*
769 * Linux uses per-cpu TSS and GDT, so set these when switching
770 * processors.
771 */
d6e88aec
AK		 772 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
773 kvm_get_gdt(&dt);
6aa8b732
AK		 774 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
775
776 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
777 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
7700270e
AK		 778
779 /*
780 * Make sure the time stamp counter is monotonous.
781 */
782 rdtscll(tsc_this);
019960ae
AK		 783 if (tsc_this < vcpu->arch.host_tsc) {
784 delta = vcpu->arch.host_tsc - tsc_this;
785 new_offset = vmcs_read64(TSC_OFFSET) + delta;
786 vmcs_write64(TSC_OFFSET, new_offset);
787 }
6aa8b732 788 }
6aa8b732
AK		 789}
790
791static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
792{
a9b21b62 793 __vmx_load_host_state(to_vmx(vcpu));
6aa8b732
AK		 794}
795
5fd86fcf
AK		 796static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
797{
798 if (vcpu->fpu_active)
799 return;
800 vcpu->fpu_active = 1;
707d92fa 801 vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
4d4ec087 802 if (kvm_read_cr0_bits(vcpu, X86_CR0_TS))
707d92fa 803 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
5fd86fcf
AK		 804 update_exception_bitmap(vcpu);
805}
806
807static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
808{
809 if (!vcpu->fpu_active)
810 return;
811 vcpu->fpu_active = 0;
707d92fa 812 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
5fd86fcf
AK		 813 update_exception_bitmap(vcpu);
814}
815
6aa8b732
AK		 816static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
817{
345dcaa8
AK		 818 unsigned long rflags;
819
820 rflags = vmcs_readl(GUEST_RFLAGS);
821 if (to_vmx(vcpu)->rmode.vm86_active)
822 rflags &= ~(unsigned long)(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
823 return rflags;
6aa8b732
AK		 824}
825
826static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
827{
7ffd92c5 828 if (to_vmx(vcpu)->rmode.vm86_active)
053de044 829 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 830 vmcs_writel(GUEST_RFLAGS, rflags);
831}
832
2809f5d2
GC		 833static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
834{
835 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
836 int ret = 0;
837
838 if (interruptibility & GUEST_INTR_STATE_STI)
839 ret |= X86_SHADOW_INT_STI;
840 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
841 ret |= X86_SHADOW_INT_MOV_SS;
842
843 return ret & mask;
844}
845
846static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
847{
848 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
849 u32 interruptibility = interruptibility_old;
850
851 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
852
853 if (mask & X86_SHADOW_INT_MOV_SS)
854 interruptibility |= GUEST_INTR_STATE_MOV_SS;
855 if (mask & X86_SHADOW_INT_STI)
856 interruptibility |= GUEST_INTR_STATE_STI;
857
858 if ((interruptibility != interruptibility_old))
859 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
860}
861
6aa8b732
AK		 862static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
863{
864 unsigned long rip;
6aa8b732 865
5fdbf976 866 rip = kvm_rip_read(vcpu);
6aa8b732 867 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 868 kvm_rip_write(vcpu, rip);
6aa8b732 869
2809f5d2
GC		 870 /* skipping an emulated instruction also counts */
871 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 872}
873
298101da
AK		 874static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
875 bool has_error_code, u32 error_code)
876{
77ab6db0 877 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 878 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 879
8ab2d2e2 880 if (has_error_code) {
77ab6db0 881 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 882 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
883 }
77ab6db0 884
7ffd92c5 885 if (vmx->rmode.vm86_active) {
77ab6db0
JK		 886 vmx->rmode.irq.pending = true;
887 vmx->rmode.irq.vector = nr;
888 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
ae0bb3e0
GN		 889 if (kvm_exception_is_soft(nr))
890 vmx->rmode.irq.rip +=
891 vmx->vcpu.arch.event_exit_inst_len;
8ab2d2e2
JK		 892 intr_info |= INTR_TYPE_SOFT_INTR;
893 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
77ab6db0
JK		 894 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
895 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
896 return;
897 }
898
66fd3f7f
GN		 899 if (kvm_exception_is_soft(nr)) {
900 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
901 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 902 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
903 } else
904 intr_info |= INTR_TYPE_HARD_EXCEPTION;
905
906 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 907}
908
4e47c7a6
SY		 909static bool vmx_rdtscp_supported(void)
910{
911 return cpu_has_vmx_rdtscp();
912}
913
a75beee6
ED		 914/*
915 * Swap MSR entry in host/guest MSR entry array.
916 */
8b9cf98c 917static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 918{
26bb0981 919 struct shared_msr_entry tmp;
a2fa3e9f
GH		 920
921 tmp = vmx->guest_msrs[to];
922 vmx->guest_msrs[to] = vmx->guest_msrs[from];
923 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 924}
925
e38aea3e
AK		 926/*
927 * Set up the vmcs to automatically save and restore system
928 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
929 * mode, as fiddling with msrs is very expensive.
930 */
8b9cf98c 931static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 932{
26bb0981 933 int save_nmsrs, index;
5897297b 934 unsigned long *msr_bitmap;
e38aea3e 935
33f9c505 936 vmx_load_host_state(vmx);
a75beee6
ED		 937 save_nmsrs = 0;
938#ifdef CONFIG_X86_64
8b9cf98c 939 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 940 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 941 if (index >= 0)
8b9cf98c
RR		 942 move_msr_up(vmx, index, save_nmsrs++);
943 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 944 if (index >= 0)
8b9cf98c
RR		 945 move_msr_up(vmx, index, save_nmsrs++);
946 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 947 if (index >= 0)
8b9cf98c 948 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 949 index = __find_msr_index(vmx, MSR_TSC_AUX);
950 if (index >= 0 && vmx->rdtscp_enabled)
951 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 952 /*
953 * MSR_K6_STAR is only needed on long mode guests, and only
954 * if efer.sce is enabled.
955 */
8b9cf98c 956 index = __find_msr_index(vmx, MSR_K6_STAR);
ad312c7c 957 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
8b9cf98c 958 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 959 }
960#endif
92c0d900
AK		 961 index = __find_msr_index(vmx, MSR_EFER);
962 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 963 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 964
26bb0981 965 vmx->save_nmsrs = save_nmsrs;
5897297b
AK		 966
967 if (cpu_has_vmx_msr_bitmap()) {
968 if (is_long_mode(&vmx->vcpu))
969 msr_bitmap = vmx_msr_bitmap_longmode;
970 else
971 msr_bitmap = vmx_msr_bitmap_legacy;
972
973 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
974 }
e38aea3e
AK		 975}
976
6aa8b732
AK		 977/*
978 * reads and returns guest's timestamp counter "register"
979 * guest_tsc = host_tsc + tsc_offset -- 21.3
980 */
981static u64 guest_read_tsc(void)
982{
983 u64 host_tsc, tsc_offset;
984
985 rdtscll(host_tsc);
986 tsc_offset = vmcs_read64(TSC_OFFSET);
987 return host_tsc + tsc_offset;
988}
989
990/*
991 * writes 'guest_tsc' into guest's timestamp counter "register"
992 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
993 */
53f658b3 994static void guest_write_tsc(u64 guest_tsc, u64 host_tsc)
6aa8b732 995{
6aa8b732
AK		 996 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
997}
998
6aa8b732
AK		 999/*
1000 * Reads an msr value (of 'msr_index') into 'pdata'.
1001 * Returns 0 on success, non-0 otherwise.
1002 * Assumes vcpu_load() was already called.
1003 */
1004static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1005{
1006 u64 data;
26bb0981 1007 struct shared_msr_entry *msr;
6aa8b732
AK		 1008
1009 if (!pdata) {
1010 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1011 return -EINVAL;
1012 }
1013
1014 switch (msr_index) {
05b3e0c2 1015#ifdef CONFIG_X86_64
6aa8b732
AK		 1016 case MSR_FS_BASE:
1017 data = vmcs_readl(GUEST_FS_BASE);
1018 break;
1019 case MSR_GS_BASE:
1020 data = vmcs_readl(GUEST_GS_BASE);
1021 break;
44ea2b17
AK		 1022 case MSR_KERNEL_GS_BASE:
1023 vmx_load_host_state(to_vmx(vcpu));
1024 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1025 break;
26bb0981 1026#endif
6aa8b732 1027 case MSR_EFER:
3bab1f5d 1028 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 1029 case MSR_IA32_TSC:
6aa8b732
AK		 1030 data = guest_read_tsc();
1031 break;
1032 case MSR_IA32_SYSENTER_CS:
1033 data = vmcs_read32(GUEST_SYSENTER_CS);
1034 break;
1035 case MSR_IA32_SYSENTER_EIP:
f5b42c33 1036 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 1037 break;
1038 case MSR_IA32_SYSENTER_ESP:
f5b42c33 1039 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 1040 break;
4e47c7a6
SY		 1041 case MSR_TSC_AUX:
1042 if (!to_vmx(vcpu)->rdtscp_enabled)
1043 return 1;
1044 /* Otherwise falls through */
6aa8b732 1045 default:
26bb0981 1046 vmx_load_host_state(to_vmx(vcpu));
8b9cf98c 1047 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d 1048 if (msr) {
542423b0 1049 vmx_load_host_state(to_vmx(vcpu));
3bab1f5d
AK		 1050 data = msr->data;
1051 break;
6aa8b732 1052 }
3bab1f5d 1053 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 1054 }
1055
1056 *pdata = data;
1057 return 0;
1058}
1059
1060/*
1061 * Writes msr value into into the appropriate "register".
1062 * Returns 0 on success, non-0 otherwise.
1063 * Assumes vcpu_load() was already called.
1064 */
1065static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1066{
a2fa3e9f 1067 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1068 struct shared_msr_entry *msr;
53f658b3 1069 u64 host_tsc;
2cc51560
ED		 1070 int ret = 0;
1071
6aa8b732 1072 switch (msr_index) {
3bab1f5d 1073 case MSR_EFER:
a9b21b62 1074 vmx_load_host_state(vmx);
2cc51560 1075 ret = kvm_set_msr_common(vcpu, msr_index, data);
2cc51560 1076 break;
16175a79 1077#ifdef CONFIG_X86_64
6aa8b732
AK		 1078 case MSR_FS_BASE:
1079 vmcs_writel(GUEST_FS_BASE, data);
1080 break;
1081 case MSR_GS_BASE:
1082 vmcs_writel(GUEST_GS_BASE, data);
1083 break;
44ea2b17
AK		 1084 case MSR_KERNEL_GS_BASE:
1085 vmx_load_host_state(vmx);
1086 vmx->msr_guest_kernel_gs_base = data;
1087 break;
6aa8b732
AK		 1088#endif
1089 case MSR_IA32_SYSENTER_CS:
1090 vmcs_write32(GUEST_SYSENTER_CS, data);
1091 break;
1092 case MSR_IA32_SYSENTER_EIP:
f5b42c33 1093 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 1094 break;
1095 case MSR_IA32_SYSENTER_ESP:
f5b42c33 1096 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 1097 break;
af24a4e4 1098 case MSR_IA32_TSC:
53f658b3
MT		 1099 rdtscll(host_tsc);
1100 guest_write_tsc(data, host_tsc);
6aa8b732 1101 break;
468d472f
SY		 1102 case MSR_IA32_CR_PAT:
1103 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1104 vmcs_write64(GUEST_IA32_PAT, data);
1105 vcpu->arch.pat = data;
1106 break;
1107 }
4e47c7a6
SY		 1108 ret = kvm_set_msr_common(vcpu, msr_index, data);
1109 break;
1110 case MSR_TSC_AUX:
1111 if (!vmx->rdtscp_enabled)
1112 return 1;
1113 /* Check reserved bit, higher 32 bits should be zero */
1114 if ((data >> 32) != 0)
1115 return 1;
1116 /* Otherwise falls through */
6aa8b732 1117 default:
8b9cf98c 1118 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 1119 if (msr) {
542423b0 1120 vmx_load_host_state(vmx);
3bab1f5d
AK		 1121 msr->data = data;
1122 break;
6aa8b732 1123 }
2cc51560 1124 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 1125 }
1126
2cc51560 1127 return ret;
6aa8b732
AK		 1128}
1129
5fdbf976 1130static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 1131{
5fdbf976
MT		 1132 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1133 switch (reg) {
1134 case VCPU_REGS_RSP:
1135 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1136 break;
1137 case VCPU_REGS_RIP:
1138 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1139 break;
6de4f3ad
AK		 1140 case VCPU_EXREG_PDPTR:
1141 if (enable_ept)
1142 ept_save_pdptrs(vcpu);
1143 break;
5fdbf976
MT		 1144 default:
1145 break;
1146 }
6aa8b732
AK		 1147}
1148
355be0b9 1149static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
6aa8b732 1150{
ae675ef0
JK		 1151 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1152 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1153 else
1154 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1155
abd3f2d6 1156 update_exception_bitmap(vcpu);
6aa8b732
AK		 1157}
1158
1159static __init int cpu_has_kvm_support(void)
1160{
6210e37b 1161 return cpu_has_vmx();
6aa8b732
AK		 1162}
1163
1164static __init int vmx_disabled_by_bios(void)
1165{
1166 u64 msr;
1167
1168 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
9ea542fa
SY		 1169 return (msr & (FEATURE_CONTROL_LOCKED |
1170 FEATURE_CONTROL_VMXON_ENABLED))
1171 == FEATURE_CONTROL_LOCKED;
62b3ffb8 1172 /* locked but not enabled */
6aa8b732
AK		 1173}
1174
10474ae8 1175static int hardware_enable(void *garbage)
6aa8b732
AK		 1176{
1177 int cpu = raw_smp_processor_id();
1178 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1179 u64 old;
1180
10474ae8
AG		 1181 if (read_cr4() & X86_CR4_VMXE)
1182 return -EBUSY;
1183
543e4243 1184 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
6aa8b732 1185 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
9ea542fa
SY		 1186 if ((old & (FEATURE_CONTROL_LOCKED |
1187 FEATURE_CONTROL_VMXON_ENABLED))
1188 != (FEATURE_CONTROL_LOCKED |
1189 FEATURE_CONTROL_VMXON_ENABLED))
6aa8b732 1190 /* enable and lock */
62b3ffb8 1191 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
9ea542fa
SY		 1192 FEATURE_CONTROL_LOCKED |
1193 FEATURE_CONTROL_VMXON_ENABLED);
66aee91a 1194 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
4ecac3fd
AK		 1195 asm volatile (ASM_VMX_VMXON_RAX
1196 : : "a"(&phys_addr), "m"(phys_addr)
6aa8b732 1197 : "memory", "cc");
10474ae8
AG		 1198
1199 ept_sync_global();
1200
1201 return 0;
6aa8b732
AK		 1202}
1203
543e4243
AK		 1204static void vmclear_local_vcpus(void)
1205{
1206 int cpu = raw_smp_processor_id();
1207 struct vcpu_vmx *vmx, *n;
1208
1209 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1210 local_vcpus_link)
1211 __vcpu_clear(vmx);
1212}
1213
710ff4a8
EH		 1214
1215/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1216 * tricks.
1217 */
1218static void kvm_cpu_vmxoff(void)
6aa8b732 1219{
4ecac3fd 1220 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
e693d71b 1221 write_cr4(read_cr4() & ~X86_CR4_VMXE);
6aa8b732
AK		 1222}
1223
710ff4a8
EH		 1224static void hardware_disable(void *garbage)
1225{
1226 vmclear_local_vcpus();
1227 kvm_cpu_vmxoff();
1228}
1229
1c3d14fe 1230static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 1231 u32 msr, u32 *result)
1c3d14fe
YS		 1232{
1233 u32 vmx_msr_low, vmx_msr_high;
1234 u32 ctl = ctl_min | ctl_opt;
1235
1236 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1237
1238 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1239 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1240
1241 /* Ensure minimum (required) set of control bits are supported. */
1242 if (ctl_min & ~ctl)
002c7f7c 1243 return -EIO;
1c3d14fe
YS		 1244
1245 *result = ctl;
1246 return 0;
1247}
1248
002c7f7c 1249static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 1250{
1251 u32 vmx_msr_low, vmx_msr_high;
d56f546d 1252 u32 min, opt, min2, opt2;
1c3d14fe
YS		 1253 u32 _pin_based_exec_control = 0;
1254 u32 _cpu_based_exec_control = 0;
f78e0e2e 1255 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 1256 u32 _vmexit_control = 0;
1257 u32 _vmentry_control = 0;
1258
1259 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
f08864b4 1260 opt = PIN_BASED_VIRTUAL_NMIS;
1c3d14fe
YS		 1261 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1262 &_pin_based_exec_control) < 0)
002c7f7c 1263 return -EIO;
1c3d14fe
YS		 1264
1265 min = CPU_BASED_HLT_EXITING |
1266#ifdef CONFIG_X86_64
1267 CPU_BASED_CR8_LOAD_EXITING |
1268 CPU_BASED_CR8_STORE_EXITING |
1269#endif
d56f546d
SY		 1270 CPU_BASED_CR3_LOAD_EXITING |
1271 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 1272 CPU_BASED_USE_IO_BITMAPS |
1273 CPU_BASED_MOV_DR_EXITING |
a7052897 1274 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 1275 CPU_BASED_MWAIT_EXITING |
1276 CPU_BASED_MONITOR_EXITING |
a7052897 1277 CPU_BASED_INVLPG_EXITING;
f78e0e2e 1278 opt = CPU_BASED_TPR_SHADOW |
25c5f225 1279 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 1280 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 1281 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1282 &_cpu_based_exec_control) < 0)
002c7f7c 1283 return -EIO;
6e5d865c
YS		 1284#ifdef CONFIG_X86_64
1285 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1286 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1287 ~CPU_BASED_CR8_STORE_EXITING;
1288#endif
f78e0e2e 1289 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 1290 min2 = 0;
1291 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2384d2b3 1292 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 1293 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 1294 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 1295 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6
SY		 1296 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
1297 SECONDARY_EXEC_RDTSCP;
d56f546d
SY		 1298 if (adjust_vmx_controls(min2, opt2,
1299 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 1300 &_cpu_based_2nd_exec_control) < 0)
1301 return -EIO;
1302 }
1303#ifndef CONFIG_X86_64
1304 if (!(_cpu_based_2nd_exec_control &
1305 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1306 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1307#endif
d56f546d 1308 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 1309 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1310 enabled */
5fff7d27
GN		 1311 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1312 CPU_BASED_CR3_STORE_EXITING |
1313 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 1314 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1315 vmx_capability.ept, vmx_capability.vpid);
1316 }
1c3d14fe
YS		 1317
1318 min = 0;
1319#ifdef CONFIG_X86_64
1320 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1321#endif
468d472f 1322 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1c3d14fe
YS		 1323 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1324 &_vmexit_control) < 0)
002c7f7c 1325 return -EIO;
1c3d14fe 1326
468d472f
SY		 1327 min = 0;
1328 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 1329 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1330 &_vmentry_control) < 0)
002c7f7c 1331 return -EIO;
6aa8b732 1332
c68876fd 1333 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 1334
1335 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1336 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 1337 return -EIO;
1c3d14fe
YS		 1338
1339#ifdef CONFIG_X86_64
1340 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1341 if (vmx_msr_high & (1u<<16))
002c7f7c 1342 return -EIO;
1c3d14fe
YS		 1343#endif
1344
1345 /* Require Write-Back (WB) memory type for VMCS accesses. */
1346 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 1347 return -EIO;
1c3d14fe 1348
002c7f7c
YS		 1349 vmcs_conf->size = vmx_msr_high & 0x1fff;
1350 vmcs_conf->order = get_order(vmcs_config.size);
1351 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 1352
002c7f7c
YS		 1353 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1354 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 1355 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 1356 vmcs_conf->vmexit_ctrl = _vmexit_control;
1357 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe
YS		 1358
1359 return 0;
c68876fd 1360}
6aa8b732
AK		 1361
1362static struct vmcs *alloc_vmcs_cpu(int cpu)
1363{
1364 int node = cpu_to_node(cpu);
1365 struct page *pages;
1366 struct vmcs *vmcs;
1367
6484eb3e 1368 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 1369 if (!pages)
1370 return NULL;
1371 vmcs = page_address(pages);
1c3d14fe
YS		 1372 memset(vmcs, 0, vmcs_config.size);
1373 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 1374 return vmcs;
1375}
1376
1377static struct vmcs *alloc_vmcs(void)
1378{
d3b2c338 1379 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 1380}
1381
1382static void free_vmcs(struct vmcs *vmcs)
1383{
1c3d14fe 1384 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 1385}
1386
39959588 1387static void free_kvm_area(void)
6aa8b732
AK		 1388{
1389 int cpu;
1390
3230bb47 1391 for_each_possible_cpu(cpu) {
6aa8b732 1392 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 1393 per_cpu(vmxarea, cpu) = NULL;
1394 }
6aa8b732
AK		 1395}
1396
6aa8b732
AK		 1397static __init int alloc_kvm_area(void)
1398{
1399 int cpu;
1400
3230bb47 1401 for_each_possible_cpu(cpu) {
6aa8b732
AK		 1402 struct vmcs *vmcs;
1403
1404 vmcs = alloc_vmcs_cpu(cpu);
1405 if (!vmcs) {
1406 free_kvm_area();
1407 return -ENOMEM;
1408 }
1409
1410 per_cpu(vmxarea, cpu) = vmcs;
1411 }
1412 return 0;
1413}
1414
1415static __init int hardware_setup(void)
1416{
002c7f7c
YS		 1417 if (setup_vmcs_config(&vmcs_config) < 0)
1418 return -EIO;
50a37eb4
JR		 1419
1420 if (boot_cpu_has(X86_FEATURE_NX))
1421 kvm_enable_efer_bits(EFER_NX);
1422
93ba03c2
SY		 1423 if (!cpu_has_vmx_vpid())
1424 enable_vpid = 0;
1425
3a624e29 1426 if (!cpu_has_vmx_ept()) {
93ba03c2 1427 enable_ept = 0;
3a624e29
NK		 1428 enable_unrestricted_guest = 0;
1429 }
1430
1431 if (!cpu_has_vmx_unrestricted_guest())
1432 enable_unrestricted_guest = 0;
93ba03c2
SY		 1433
1434 if (!cpu_has_vmx_flexpriority())
1435 flexpriority_enabled = 0;
1436
95ba8273
GN		 1437 if (!cpu_has_vmx_tpr_shadow())
1438 kvm_x86_ops->update_cr8_intercept = NULL;
1439
54dee993
MT		 1440 if (enable_ept && !cpu_has_vmx_ept_2m_page())
1441 kvm_disable_largepages();
1442
4b8d54f9
ZE		 1443 if (!cpu_has_vmx_ple())
1444 ple_gap = 0;
1445
6aa8b732
AK		 1446 return alloc_kvm_area();
1447}
1448
1449static __exit void hardware_unsetup(void)
1450{
1451 free_kvm_area();
1452}
1453
6aa8b732
AK		 1454static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1455{
1456 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1457
6af11b9e 1458 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 1459 vmcs_write16(sf->selector, save->selector);
1460 vmcs_writel(sf->base, save->base);
1461 vmcs_write32(sf->limit, save->limit);
1462 vmcs_write32(sf->ar_bytes, save->ar);
1463 } else {
1464 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1465 << AR_DPL_SHIFT;
1466 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1467 }
1468}
1469
1470static void enter_pmode(struct kvm_vcpu *vcpu)
1471{
1472 unsigned long flags;
a89a8fb9 1473 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1474
a89a8fb9 1475 vmx->emulation_required = 1;
7ffd92c5 1476 vmx->rmode.vm86_active = 0;
6aa8b732 1477
7ffd92c5
AK		 1478 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1479 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1480 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
6aa8b732
AK		 1481
1482 flags = vmcs_readl(GUEST_RFLAGS);
053de044 1483 flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
7ffd92c5 1484 flags |= (vmx->rmode.save_iopl << IOPL_SHIFT);
6aa8b732
AK		 1485 vmcs_writel(GUEST_RFLAGS, flags);
1486
66aee91a
RR		 1487 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1488 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 1489
1490 update_exception_bitmap(vcpu);
1491
a89a8fb9
MG		 1492 if (emulate_invalid_guest_state)
1493 return;
1494
7ffd92c5
AK		 1495 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1496 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1497 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1498 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
6aa8b732
AK		 1499
1500 vmcs_write16(GUEST_SS_SELECTOR, 0);
1501 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1502
1503 vmcs_write16(GUEST_CS_SELECTOR,
1504 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1505 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1506}
1507
d77c26fc 1508static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 1509{
bfc6d222 1510 if (!kvm->arch.tss_addr) {
bc6678a3
MT		 1511 struct kvm_memslots *slots;
1512 gfn_t base_gfn;
1513
1514 slots = rcu_dereference(kvm->memslots);
1515 base_gfn = kvm->memslots->memslots[0].base_gfn +
46a26bf5 1516 kvm->memslots->memslots[0].npages - 3;
cbc94022
IE		 1517 return base_gfn << PAGE_SHIFT;
1518 }
bfc6d222 1519 return kvm->arch.tss_addr;
6aa8b732
AK		 1520}
1521
1522static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1523{
1524 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1525
1526 save->selector = vmcs_read16(sf->selector);
1527 save->base = vmcs_readl(sf->base);
1528 save->limit = vmcs_read32(sf->limit);
1529 save->ar = vmcs_read32(sf->ar_bytes);
15b00f32
JK		 1530 vmcs_write16(sf->selector, save->base >> 4);
1531 vmcs_write32(sf->base, save->base & 0xfffff);
6aa8b732
AK		 1532 vmcs_write32(sf->limit, 0xffff);
1533 vmcs_write32(sf->ar_bytes, 0xf3);
1534}
1535
1536static void enter_rmode(struct kvm_vcpu *vcpu)
1537{
1538 unsigned long flags;
a89a8fb9 1539 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1540
3a624e29
NK		 1541 if (enable_unrestricted_guest)
1542 return;
1543
a89a8fb9 1544 vmx->emulation_required = 1;
7ffd92c5 1545 vmx->rmode.vm86_active = 1;
6aa8b732 1546
7ffd92c5 1547 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
6aa8b732
AK		 1548 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1549
7ffd92c5 1550 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
6aa8b732
AK		 1551 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1552
7ffd92c5 1553 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
6aa8b732
AK		 1554 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1555
1556 flags = vmcs_readl(GUEST_RFLAGS);
7ffd92c5 1557 vmx->rmode.save_iopl
ad312c7c 1558 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
6aa8b732 1559
053de044 1560 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 1561
1562 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 1563 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 1564 update_exception_bitmap(vcpu);
1565
a89a8fb9
MG		 1566 if (emulate_invalid_guest_state)
1567 goto continue_rmode;
1568
6aa8b732
AK		 1569 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1570 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1571 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1572
1573 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 1574 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
8cb5b033
AK		 1575 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1576 vmcs_writel(GUEST_CS_BASE, 0xf0000);
6aa8b732
AK		 1577 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1578
7ffd92c5
AK		 1579 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1580 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1581 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1582 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
75880a01 1583
a89a8fb9 1584continue_rmode:
8668a3c4 1585 kvm_mmu_reset_context(vcpu);
b7ebfb05 1586 init_rmode(vcpu->kvm);
6aa8b732
AK		 1587}
1588
401d10de
AS		 1589static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1590{
1591 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 1592 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1593
1594 if (!msr)
1595 return;
401d10de 1596
44ea2b17
AK		 1597 /*
1598 * Force kernel_gs_base reloading before EFER changes, as control
1599 * of this msr depends on is_long_mode().
1600 */
1601 vmx_load_host_state(to_vmx(vcpu));
401d10de
AS		 1602 vcpu->arch.shadow_efer = efer;
1603 if (!msr)
1604 return;
1605 if (efer & EFER_LMA) {
1606 vmcs_write32(VM_ENTRY_CONTROLS,
1607 vmcs_read32(VM_ENTRY_CONTROLS) |
1608 VM_ENTRY_IA32E_MODE);
1609 msr->data = efer;
1610 } else {
1611 vmcs_write32(VM_ENTRY_CONTROLS,
1612 vmcs_read32(VM_ENTRY_CONTROLS) &
1613 ~VM_ENTRY_IA32E_MODE);
1614
1615 msr->data = efer & ~EFER_LME;
1616 }
1617 setup_msrs(vmx);
1618}
1619
05b3e0c2 1620#ifdef CONFIG_X86_64
6aa8b732
AK		 1621
1622static void enter_lmode(struct kvm_vcpu *vcpu)
1623{
1624 u32 guest_tr_ar;
1625
1626 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1627 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1628 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
b8688d51 1629 __func__);
6aa8b732
AK		 1630 vmcs_write32(GUEST_TR_AR_BYTES,
1631 (guest_tr_ar & ~AR_TYPE_MASK)
1632 | AR_TYPE_BUSY_64_TSS);
1633 }
ad312c7c 1634 vcpu->arch.shadow_efer |= EFER_LMA;
401d10de 1635 vmx_set_efer(vcpu, vcpu->arch.shadow_efer);
6aa8b732
AK		 1636}
1637
1638static void exit_lmode(struct kvm_vcpu *vcpu)
1639{
ad312c7c 1640 vcpu->arch.shadow_efer &= ~EFER_LMA;
6aa8b732
AK		 1641
1642 vmcs_write32(VM_ENTRY_CONTROLS,
1643 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 1644 & ~VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1645}
1646
1647#endif
1648
2384d2b3
SY		 1649static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1650{
1651 vpid_sync_vcpu_all(to_vmx(vcpu));
089d034e 1652 if (enable_ept)
4e1096d2 1653 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
2384d2b3
SY		 1654}
1655
e8467fda
AK		 1656static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1657{
1658 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
1659
1660 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
1661 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
1662}
1663
25c4c276 1664static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 1665{
fc78f519
AK		 1666 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
1667
1668 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
1669 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 1670}
1671
1439442c
SY		 1672static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1673{
6de4f3ad
AK		 1674 if (!test_bit(VCPU_EXREG_PDPTR,
1675 (unsigned long *)&vcpu->arch.regs_dirty))
1676 return;
1677
1439442c 1678 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1439442c
SY		 1679 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1680 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1681 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1682 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1683 }
1684}
1685
8f5d549f
AK		 1686static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1687{
1688 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1689 vcpu->arch.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1690 vcpu->arch.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1691 vcpu->arch.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1692 vcpu->arch.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
1693 }
6de4f3ad
AK		 1694
1695 __set_bit(VCPU_EXREG_PDPTR,
1696 (unsigned long *)&vcpu->arch.regs_avail);
1697 __set_bit(VCPU_EXREG_PDPTR,
1698 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 1699}
1700
1439442c
SY		 1701static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1702
1703static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1704 unsigned long cr0,
1705 struct kvm_vcpu *vcpu)
1706{
1707 if (!(cr0 & X86_CR0_PG)) {
1708 /* From paging/starting to nonpaging */
1709 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1710 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 1711 (CPU_BASED_CR3_LOAD_EXITING |
1712 CPU_BASED_CR3_STORE_EXITING));
1713 vcpu->arch.cr0 = cr0;
fc78f519 1714 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 1715 } else if (!is_paging(vcpu)) {
1716 /* From nonpaging to paging */
1717 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1718 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 1719 ~(CPU_BASED_CR3_LOAD_EXITING |
1720 CPU_BASED_CR3_STORE_EXITING));
1721 vcpu->arch.cr0 = cr0;
fc78f519 1722 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 1723 }
95eb84a7
SY		 1724
1725 if (!(cr0 & X86_CR0_WP))
1726 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 1727}
1728
6aa8b732
AK		 1729static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1730{
7ffd92c5 1731 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 1732 unsigned long hw_cr0;
1733
1734 if (enable_unrestricted_guest)
1735 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1736 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1737 else
1738 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1439442c 1739
5fd86fcf
AK		 1740 vmx_fpu_deactivate(vcpu);
1741
7ffd92c5 1742 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 1743 enter_pmode(vcpu);
1744
7ffd92c5 1745 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 1746 enter_rmode(vcpu);
1747
05b3e0c2 1748#ifdef CONFIG_X86_64
ad312c7c 1749 if (vcpu->arch.shadow_efer & EFER_LME) {
707d92fa 1750 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 1751 enter_lmode(vcpu);
707d92fa 1752 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 1753 exit_lmode(vcpu);
1754 }
1755#endif
1756
089d034e 1757 if (enable_ept)
1439442c
SY		 1758 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1759
6aa8b732 1760 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 1761 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 1762 vcpu->arch.cr0 = cr0;
5fd86fcf 1763
707d92fa 1764 if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
5fd86fcf 1765 vmx_fpu_activate(vcpu);
6aa8b732
AK		 1766}
1767
1439442c
SY		 1768static u64 construct_eptp(unsigned long root_hpa)
1769{
1770 u64 eptp;
1771
1772 /* TODO write the value reading from MSR */
1773 eptp = VMX_EPT_DEFAULT_MT |
1774 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1775 eptp |= (root_hpa & PAGE_MASK);
1776
1777 return eptp;
1778}
1779
6aa8b732
AK		 1780static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1781{
1439442c
SY		 1782 unsigned long guest_cr3;
1783 u64 eptp;
1784
1785 guest_cr3 = cr3;
089d034e 1786 if (enable_ept) {
1439442c
SY		 1787 eptp = construct_eptp(cr3);
1788 vmcs_write64(EPT_POINTER, eptp);
1439442c 1789 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
b927a3ce 1790 vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 1791 ept_load_pdptrs(vcpu);
1439442c
SY		 1792 }
1793
2384d2b3 1794 vmx_flush_tlb(vcpu);
1439442c 1795 vmcs_writel(GUEST_CR3, guest_cr3);
4d4ec087 1796 if (kvm_read_cr0_bits(vcpu, X86_CR0_PE))
5fd86fcf 1797 vmx_fpu_deactivate(vcpu);
6aa8b732
AK		 1798}
1799
1800static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1801{
7ffd92c5 1802 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 1803 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1804
ad312c7c 1805 vcpu->arch.cr4 = cr4;
bc23008b
AK		 1806 if (enable_ept) {
1807 if (!is_paging(vcpu)) {
1808 hw_cr4 &= ~X86_CR4_PAE;
1809 hw_cr4 |= X86_CR4_PSE;
1810 } else if (!(cr4 & X86_CR4_PAE)) {
1811 hw_cr4 &= ~X86_CR4_PAE;
1812 }
1813 }
1439442c
SY		 1814
1815 vmcs_writel(CR4_READ_SHADOW, cr4);
1816 vmcs_writel(GUEST_CR4, hw_cr4);
6aa8b732
AK		 1817}
1818
6aa8b732
AK		 1819static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1820{
1821 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1822
1823 return vmcs_readl(sf->base);
1824}
1825
1826static void vmx_get_segment(struct kvm_vcpu *vcpu,
1827 struct kvm_segment *var, int seg)
1828{
1829 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1830 u32 ar;
1831
1832 var->base = vmcs_readl(sf->base);
1833 var->limit = vmcs_read32(sf->limit);
1834 var->selector = vmcs_read16(sf->selector);
1835 ar = vmcs_read32(sf->ar_bytes);
9fd4a3b7 1836 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
6aa8b732
AK		 1837 ar = 0;
1838 var->type = ar & 15;
1839 var->s = (ar >> 4) & 1;
1840 var->dpl = (ar >> 5) & 3;
1841 var->present = (ar >> 7) & 1;
1842 var->avl = (ar >> 12) & 1;
1843 var->l = (ar >> 13) & 1;
1844 var->db = (ar >> 14) & 1;
1845 var->g = (ar >> 15) & 1;
1846 var->unusable = (ar >> 16) & 1;
1847}
1848
2e4d2653
IE		 1849static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1850{
4d4ec087 1851 if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) /* if real mode */
2e4d2653
IE		 1852 return 0;
1853
1854 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1855 return 3;
1856
eab4b8aa 1857 return vmcs_read16(GUEST_CS_SELECTOR) & 3;
2e4d2653
IE		 1858}
1859
653e3108 1860static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 1861{
6aa8b732
AK		 1862 u32 ar;
1863
653e3108 1864 if (var->unusable)
6aa8b732
AK		 1865 ar = 1 << 16;
1866 else {
1867 ar = var->type & 15;
1868 ar |= (var->s & 1) << 4;
1869 ar |= (var->dpl & 3) << 5;
1870 ar |= (var->present & 1) << 7;
1871 ar |= (var->avl & 1) << 12;
1872 ar |= (var->l & 1) << 13;
1873 ar |= (var->db & 1) << 14;
1874 ar |= (var->g & 1) << 15;
1875 }
f7fbf1fd
UL		 1876 if (ar == 0) /* a 0 value means unusable */
1877 ar = AR_UNUSABLE_MASK;
653e3108
AK		 1878
1879 return ar;
1880}
1881
1882static void vmx_set_segment(struct kvm_vcpu *vcpu,
1883 struct kvm_segment *var, int seg)
1884{
7ffd92c5 1885 struct vcpu_vmx *vmx = to_vmx(vcpu);
653e3108
AK		 1886 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1887 u32 ar;
1888
7ffd92c5
AK		 1889 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
1890 vmx->rmode.tr.selector = var->selector;
1891 vmx->rmode.tr.base = var->base;
1892 vmx->rmode.tr.limit = var->limit;
1893 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
653e3108
AK		 1894 return;
1895 }
1896 vmcs_writel(sf->base, var->base);
1897 vmcs_write32(sf->limit, var->limit);
1898 vmcs_write16(sf->selector, var->selector);
7ffd92c5 1899 if (vmx->rmode.vm86_active && var->s) {
653e3108
AK		 1900 /*
1901 * Hack real-mode segments into vm86 compatibility.
1902 */
1903 if (var->base == 0xffff0000 && var->selector == 0xf000)
1904 vmcs_writel(sf->base, 0xf0000);
1905 ar = 0xf3;
1906 } else
1907 ar = vmx_segment_access_rights(var);
3a624e29
NK		 1908
1909 /*
1910 * Fix the "Accessed" bit in AR field of segment registers for older
1911 * qemu binaries.
1912 * IA32 arch specifies that at the time of processor reset the
1913 * "Accessed" bit in the AR field of segment registers is 1. And qemu
1914 * is setting it to 0 in the usedland code. This causes invalid guest
1915 * state vmexit when "unrestricted guest" mode is turned on.
1916 * Fix for this setup issue in cpu_reset is being pushed in the qemu
1917 * tree. Newer qemu binaries with that qemu fix would not need this
1918 * kvm hack.
1919 */
1920 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
1921 ar |= 0x1; /* Accessed */
1922
6aa8b732
AK		 1923 vmcs_write32(sf->ar_bytes, ar);
1924}
1925
6aa8b732
AK		 1926static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1927{
1928 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1929
1930 *db = (ar >> 14) & 1;
1931 *l = (ar >> 13) & 1;
1932}
1933
1934static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1935{
1936 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1937 dt->base = vmcs_readl(GUEST_IDTR_BASE);
1938}
1939
1940static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1941{
1942 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1943 vmcs_writel(GUEST_IDTR_BASE, dt->base);
1944}
1945
1946static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1947{
1948 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1949 dt->base = vmcs_readl(GUEST_GDTR_BASE);
1950}
1951
1952static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1953{
1954 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1955 vmcs_writel(GUEST_GDTR_BASE, dt->base);
1956}
1957
648dfaa7
MG		 1958static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
1959{
1960 struct kvm_segment var;
1961 u32 ar;
1962
1963 vmx_get_segment(vcpu, &var, seg);
1964 ar = vmx_segment_access_rights(&var);
1965
1966 if (var.base != (var.selector << 4))
1967 return false;
1968 if (var.limit != 0xffff)
1969 return false;
1970 if (ar != 0xf3)
1971 return false;
1972
1973 return true;
1974}
1975
1976static bool code_segment_valid(struct kvm_vcpu *vcpu)
1977{
1978 struct kvm_segment cs;
1979 unsigned int cs_rpl;
1980
1981 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1982 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
1983
1872a3f4
AK		 1984 if (cs.unusable)
1985 return false;
648dfaa7
MG		 1986 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
1987 return false;
1988 if (!cs.s)
1989 return false;
1872a3f4 1990 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 1991 if (cs.dpl > cs_rpl)
1992 return false;
1872a3f4 1993 } else {
648dfaa7
MG		 1994 if (cs.dpl != cs_rpl)
1995 return false;
1996 }
1997 if (!cs.present)
1998 return false;
1999
2000 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
2001 return true;
2002}
2003
2004static bool stack_segment_valid(struct kvm_vcpu *vcpu)
2005{
2006 struct kvm_segment ss;
2007 unsigned int ss_rpl;
2008
2009 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2010 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
2011
1872a3f4
AK		 2012 if (ss.unusable)
2013 return true;
2014 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 2015 return false;
2016 if (!ss.s)
2017 return false;
2018 if (ss.dpl != ss_rpl) /* DPL != RPL */
2019 return false;
2020 if (!ss.present)
2021 return false;
2022
2023 return true;
2024}
2025
2026static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
2027{
2028 struct kvm_segment var;
2029 unsigned int rpl;
2030
2031 vmx_get_segment(vcpu, &var, seg);
2032 rpl = var.selector & SELECTOR_RPL_MASK;
2033
1872a3f4
AK		 2034 if (var.unusable)
2035 return true;
648dfaa7
MG		 2036 if (!var.s)
2037 return false;
2038 if (!var.present)
2039 return false;
2040 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
2041 if (var.dpl < rpl) /* DPL < RPL */
2042 return false;
2043 }
2044
2045 /* TODO: Add other members to kvm_segment_field to allow checking for other access
2046 * rights flags
2047 */
2048 return true;
2049}
2050
2051static bool tr_valid(struct kvm_vcpu *vcpu)
2052{
2053 struct kvm_segment tr;
2054
2055 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
2056
1872a3f4
AK		 2057 if (tr.unusable)
2058 return false;
648dfaa7
MG		 2059 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2060 return false;
1872a3f4 2061 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 2062 return false;
2063 if (!tr.present)
2064 return false;
2065
2066 return true;
2067}
2068
2069static bool ldtr_valid(struct kvm_vcpu *vcpu)
2070{
2071 struct kvm_segment ldtr;
2072
2073 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2074
1872a3f4
AK		 2075 if (ldtr.unusable)
2076 return true;
648dfaa7
MG		 2077 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2078 return false;
2079 if (ldtr.type != 2)
2080 return false;
2081 if (!ldtr.present)
2082 return false;
2083
2084 return true;
2085}
2086
2087static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2088{
2089 struct kvm_segment cs, ss;
2090
2091 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2092 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2093
2094 return ((cs.selector & SELECTOR_RPL_MASK) ==
2095 (ss.selector & SELECTOR_RPL_MASK));
2096}
2097
2098/*
2099 * Check if guest state is valid. Returns true if valid, false if
2100 * not.
2101 * We assume that registers are always usable
2102 */
2103static bool guest_state_valid(struct kvm_vcpu *vcpu)
2104{
2105 /* real mode guest state checks */
4d4ec087 2106 if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
648dfaa7
MG		 2107 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2108 return false;
2109 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2110 return false;
2111 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2112 return false;
2113 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2114 return false;
2115 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2116 return false;
2117 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2118 return false;
2119 } else {
2120 /* protected mode guest state checks */
2121 if (!cs_ss_rpl_check(vcpu))
2122 return false;
2123 if (!code_segment_valid(vcpu))
2124 return false;
2125 if (!stack_segment_valid(vcpu))
2126 return false;
2127 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2128 return false;
2129 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2130 return false;
2131 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2132 return false;
2133 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2134 return false;
2135 if (!tr_valid(vcpu))
2136 return false;
2137 if (!ldtr_valid(vcpu))
2138 return false;
2139 }
2140 /* TODO:
2141 * - Add checks on RIP
2142 * - Add checks on RFLAGS
2143 */
2144
2145 return true;
2146}
2147
d77c26fc 2148static int init_rmode_tss(struct kvm *kvm)
6aa8b732 2149{
6aa8b732 2150 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde 2151 u16 data = 0;
10589a46 2152 int ret = 0;
195aefde 2153 int r;
6aa8b732 2154
195aefde
IE		 2155 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2156 if (r < 0)
10589a46 2157 goto out;
195aefde 2158 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 2159 r = kvm_write_guest_page(kvm, fn++, &data,
2160 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 2161 if (r < 0)
10589a46 2162 goto out;
195aefde
IE		 2163 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2164 if (r < 0)
10589a46 2165 goto out;
195aefde
IE		 2166 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2167 if (r < 0)
10589a46 2168 goto out;
195aefde 2169 data = ~0;
10589a46
MT		 2170 r = kvm_write_guest_page(kvm, fn, &data,
2171 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2172 sizeof(u8));
195aefde 2173 if (r < 0)
10589a46
MT		 2174 goto out;
2175
2176 ret = 1;
2177out:
10589a46 2178 return ret;
6aa8b732
AK		 2179}
2180
b7ebfb05
SY		 2181static int init_rmode_identity_map(struct kvm *kvm)
2182{
2183 int i, r, ret;
2184 pfn_t identity_map_pfn;
2185 u32 tmp;
2186
089d034e 2187 if (!enable_ept)
b7ebfb05
SY		 2188 return 1;
2189 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2190 printk(KERN_ERR "EPT: identity-mapping pagetable "
2191 "haven't been allocated!\n");
2192 return 0;
2193 }
2194 if (likely(kvm->arch.ept_identity_pagetable_done))
2195 return 1;
2196 ret = 0;
b927a3ce 2197 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
b7ebfb05
SY		 2198 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2199 if (r < 0)
2200 goto out;
2201 /* Set up identity-mapping pagetable for EPT in real mode */
2202 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2203 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2204 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2205 r = kvm_write_guest_page(kvm, identity_map_pfn,
2206 &tmp, i * sizeof(tmp), sizeof(tmp));
2207 if (r < 0)
2208 goto out;
2209 }
2210 kvm->arch.ept_identity_pagetable_done = true;
2211 ret = 1;
2212out:
2213 return ret;
2214}
2215
6aa8b732
AK		 2216static void seg_setup(int seg)
2217{
2218 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 2219 unsigned int ar;
6aa8b732
AK		 2220
2221 vmcs_write16(sf->selector, 0);
2222 vmcs_writel(sf->base, 0);
2223 vmcs_write32(sf->limit, 0xffff);
3a624e29
NK		 2224 if (enable_unrestricted_guest) {
2225 ar = 0x93;
2226 if (seg == VCPU_SREG_CS)
2227 ar |= 0x08; /* code segment */
2228 } else
2229 ar = 0xf3;
2230
2231 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 2232}
2233
f78e0e2e
SY		 2234static int alloc_apic_access_page(struct kvm *kvm)
2235{
2236 struct kvm_userspace_memory_region kvm_userspace_mem;
2237 int r = 0;
2238
79fac95e 2239 mutex_lock(&kvm->slots_lock);
bfc6d222 2240 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 2241 goto out;
2242 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2243 kvm_userspace_mem.flags = 0;
2244 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2245 kvm_userspace_mem.memory_size = PAGE_SIZE;
2246 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2247 if (r)
2248 goto out;
72dc67a6 2249
bfc6d222 2250 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
f78e0e2e 2251out:
79fac95e 2252 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 2253 return r;
2254}
2255
b7ebfb05
SY		 2256static int alloc_identity_pagetable(struct kvm *kvm)
2257{
2258 struct kvm_userspace_memory_region kvm_userspace_mem;
2259 int r = 0;
2260
79fac95e 2261 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 2262 if (kvm->arch.ept_identity_pagetable)
2263 goto out;
2264 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2265 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 2266 kvm_userspace_mem.guest_phys_addr =
2267 kvm->arch.ept_identity_map_addr;
b7ebfb05
SY		 2268 kvm_userspace_mem.memory_size = PAGE_SIZE;
2269 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2270 if (r)
2271 goto out;
2272
b7ebfb05 2273 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
b927a3ce 2274 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
b7ebfb05 2275out:
79fac95e 2276 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 2277 return r;
2278}
2279
2384d2b3
SY		 2280static void allocate_vpid(struct vcpu_vmx *vmx)
2281{
2282 int vpid;
2283
2284 vmx->vpid = 0;
919818ab 2285 if (!enable_vpid)
2384d2b3
SY		 2286 return;
2287 spin_lock(&vmx_vpid_lock);
2288 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2289 if (vpid < VMX_NR_VPIDS) {
2290 vmx->vpid = vpid;
2291 __set_bit(vpid, vmx_vpid_bitmap);
2292 }
2293 spin_unlock(&vmx_vpid_lock);
2294}
2295
5897297b 2296static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
25c5f225 2297{
3e7c73e9 2298 int f = sizeof(unsigned long);
25c5f225
SY		 2299
2300 if (!cpu_has_vmx_msr_bitmap())
2301 return;
2302
2303 /*
2304 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2305 * have the write-low and read-high bitmap offsets the wrong way round.
2306 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2307 */
25c5f225 2308 if (msr <= 0x1fff) {
3e7c73e9
AK		 2309 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2310 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
25c5f225
SY		 2311 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2312 msr &= 0x1fff;
3e7c73e9
AK		 2313 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2314 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
25c5f225 2315 }
25c5f225
SY		 2316}
2317
5897297b
AK		 2318static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2319{
2320 if (!longmode_only)
2321 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2322 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2323}
2324
6aa8b732
AK		 2325/*
2326 * Sets up the vmcs for emulated real mode.
2327 */
8b9cf98c 2328static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 2329{
468d472f 2330 u32 host_sysenter_cs, msr_low, msr_high;
6aa8b732 2331 u32 junk;
53f658b3 2332 u64 host_pat, tsc_this, tsc_base;
6aa8b732
AK		 2333 unsigned long a;
2334 struct descriptor_table dt;
2335 int i;
cd2276a7 2336 unsigned long kvm_vmx_return;
6e5d865c 2337 u32 exec_control;
6aa8b732 2338
6aa8b732 2339 /* I/O */
3e7c73e9
AK		 2340 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2341 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 2342
25c5f225 2343 if (cpu_has_vmx_msr_bitmap())
5897297b 2344 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 2345
6aa8b732
AK		 2346 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2347
6aa8b732 2348 /* Control */
1c3d14fe
YS		 2349 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2350 vmcs_config.pin_based_exec_ctrl);
6e5d865c
YS		 2351
2352 exec_control = vmcs_config.cpu_based_exec_ctrl;
2353 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2354 exec_control &= ~CPU_BASED_TPR_SHADOW;
2355#ifdef CONFIG_X86_64
2356 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2357 CPU_BASED_CR8_LOAD_EXITING;
2358#endif
2359 }
089d034e 2360 if (!enable_ept)
d56f546d 2361 exec_control |= CPU_BASED_CR3_STORE_EXITING |
83dbc83a
MT		 2362 CPU_BASED_CR3_LOAD_EXITING |
2363 CPU_BASED_INVLPG_EXITING;
6e5d865c 2364 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6aa8b732 2365
83ff3b9d
SY		 2366 if (cpu_has_secondary_exec_ctrls()) {
2367 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2368 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2369 exec_control &=
2370 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2384d2b3
SY		 2371 if (vmx->vpid == 0)
2372 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
046d8710 2373 if (!enable_ept) {
d56f546d 2374 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
046d8710
SY		 2375 enable_unrestricted_guest = 0;
2376 }
3a624e29
NK		 2377 if (!enable_unrestricted_guest)
2378 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4b8d54f9
ZE		 2379 if (!ple_gap)
2380 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
83ff3b9d
SY		 2381 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2382 }
f78e0e2e 2383
4b8d54f9
ZE		 2384 if (ple_gap) {
2385 vmcs_write32(PLE_GAP, ple_gap);
2386 vmcs_write32(PLE_WINDOW, ple_window);
2387 }
2388
c7addb90
AK		 2389 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2390 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
6aa8b732
AK		 2391 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2392
2393 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
2394 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2395 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2396
2397 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2398 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2399 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
d6e88aec
AK		 2400 vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs()); /* 22.2.4 */
2401 vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs()); /* 22.2.4 */
6aa8b732 2402 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
05b3e0c2 2403#ifdef CONFIG_X86_64
6aa8b732
AK		 2404 rdmsrl(MSR_FS_BASE, a);
2405 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2406 rdmsrl(MSR_GS_BASE, a);
2407 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2408#else
2409 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2410 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2411#endif
2412
2413 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2414
d6e88aec 2415 kvm_get_idt(&dt);
6aa8b732
AK		 2416 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
2417
d77c26fc 2418 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
cd2276a7 2419 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2cc51560
ED		 2420 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2421 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2422 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
6aa8b732
AK		 2423
2424 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2425 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2426 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2427 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2428 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2429 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2430
468d472f
SY		 2431 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2432 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2433 host_pat = msr_low | ((u64) msr_high << 32);
2434 vmcs_write64(HOST_IA32_PAT, host_pat);
2435 }
2436 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2437 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2438 host_pat = msr_low | ((u64) msr_high << 32);
2439 /* Write the default value follow host pat */
2440 vmcs_write64(GUEST_IA32_PAT, host_pat);
2441 /* Keep arch.pat sync with GUEST_IA32_PAT */
2442 vmx->vcpu.arch.pat = host_pat;
2443 }
2444
6aa8b732
AK		 2445 for (i = 0; i < NR_VMX_MSR; ++i) {
2446 u32 index = vmx_msr_index[i];
2447 u32 data_low, data_high;
a2fa3e9f 2448 int j = vmx->nmsrs;
6aa8b732
AK		 2449
2450 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2451 continue;
432bd6cb
AK		 2452 if (wrmsr_safe(index, data_low, data_high) < 0)
2453 continue;
26bb0981
AK		 2454 vmx->guest_msrs[j].index = i;
2455 vmx->guest_msrs[j].data = 0;
d5696725 2456 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 2457 ++vmx->nmsrs;
6aa8b732 2458 }
6aa8b732 2459
1c3d14fe 2460 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 2461
2462 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 2463 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2464
e00c8cf2 2465 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4c38609a 2466 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
ce03e4f2
AK		 2467 if (enable_ept)
2468 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4c38609a 2469 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
e00c8cf2 2470
53f658b3
MT		 2471 tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc;
2472 rdtscll(tsc_this);
2473 if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc)
2474 tsc_base = tsc_this;
2475
2476 guest_write_tsc(0, tsc_base);
f78e0e2e 2477
e00c8cf2
AK		 2478 return 0;
2479}
2480
b7ebfb05
SY		 2481static int init_rmode(struct kvm *kvm)
2482{
2483 if (!init_rmode_tss(kvm))
2484 return 0;
2485 if (!init_rmode_identity_map(kvm))
2486 return 0;
2487 return 1;
2488}
2489
e00c8cf2
AK		 2490static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2491{
2492 struct vcpu_vmx *vmx = to_vmx(vcpu);
2493 u64 msr;
f656ce01 2494 int ret, idx;
e00c8cf2 2495
5fdbf976 2496 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
f656ce01 2497 idx = srcu_read_lock(&vcpu->kvm->srcu);
b7ebfb05 2498 if (!init_rmode(vmx->vcpu.kvm)) {
e00c8cf2
AK		 2499 ret = -ENOMEM;
2500 goto out;
2501 }
2502
7ffd92c5 2503 vmx->rmode.vm86_active = 0;
e00c8cf2 2504
3b86cd99
JK		 2505 vmx->soft_vnmi_blocked = 0;
2506
ad312c7c 2507 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 2508 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 2509 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 2510 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 2511 msr |= MSR_IA32_APICBASE_BSP;
2512 kvm_set_apic_base(&vmx->vcpu, msr);
2513
2514 fx_init(&vmx->vcpu);
2515
5706be0d 2516 seg_setup(VCPU_SREG_CS);
e00c8cf2
AK		 2517 /*
2518 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2519 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2520 */
c5af89b6 2521 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
e00c8cf2
AK		 2522 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2523 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2524 } else {
ad312c7c
ZX		 2525 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2526 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2 2527 }
e00c8cf2
AK		 2528
2529 seg_setup(VCPU_SREG_DS);
2530 seg_setup(VCPU_SREG_ES);
2531 seg_setup(VCPU_SREG_FS);
2532 seg_setup(VCPU_SREG_GS);
2533 seg_setup(VCPU_SREG_SS);
2534
2535 vmcs_write16(GUEST_TR_SELECTOR, 0);
2536 vmcs_writel(GUEST_TR_BASE, 0);
2537 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2538 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2539
2540 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2541 vmcs_writel(GUEST_LDTR_BASE, 0);
2542 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2543 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2544
2545 vmcs_write32(GUEST_SYSENTER_CS, 0);
2546 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2547 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2548
2549 vmcs_writel(GUEST_RFLAGS, 0x02);
c5af89b6 2550 if (kvm_vcpu_is_bsp(&vmx->vcpu))
5fdbf976 2551 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 2552 else
5fdbf976
MT		 2553 kvm_rip_write(vcpu, 0);
2554 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
e00c8cf2 2555
e00c8cf2
AK		 2556 vmcs_writel(GUEST_DR7, 0x400);
2557
2558 vmcs_writel(GUEST_GDTR_BASE, 0);
2559 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2560
2561 vmcs_writel(GUEST_IDTR_BASE, 0);
2562 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2563
2564 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2565 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2566 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2567
e00c8cf2
AK		 2568 /* Special registers */
2569 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2570
2571 setup_msrs(vmx);
2572
6aa8b732
AK		 2573 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2574
f78e0e2e
SY		 2575 if (cpu_has_vmx_tpr_shadow()) {
2576 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2577 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2578 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
ad312c7c 2579 page_to_phys(vmx->vcpu.arch.apic->regs_page));
f78e0e2e
SY		 2580 vmcs_write32(TPR_THRESHOLD, 0);
2581 }
2582
2583 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2584 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 2585 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 2586
2384d2b3
SY		 2587 if (vmx->vpid != 0)
2588 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2589
fa40052c 2590 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 2591 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 2592 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 2593 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 2594 vmx_fpu_activate(&vmx->vcpu);
2595 update_exception_bitmap(&vmx->vcpu);
6aa8b732 2596
2384d2b3
SY		 2597 vpid_sync_vcpu_all(vmx);
2598
3200f405 2599 ret = 0;
6aa8b732 2600
a89a8fb9
MG		 2601 /* HACK: Don't enable emulation on guest boot/reset */
2602 vmx->emulation_required = 0;
2603
6aa8b732 2604out:
f656ce01 2605 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6aa8b732
AK		 2606 return ret;
2607}
2608
3b86cd99
JK		 2609static void enable_irq_window(struct kvm_vcpu *vcpu)
2610{
2611 u32 cpu_based_vm_exec_control;
2612
2613 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2614 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2615 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2616}
2617
2618static void enable_nmi_window(struct kvm_vcpu *vcpu)
2619{
2620 u32 cpu_based_vm_exec_control;
2621
2622 if (!cpu_has_virtual_nmis()) {
2623 enable_irq_window(vcpu);
2624 return;
2625 }
2626
2627 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2628 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2629 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2630}
2631
66fd3f7f 2632static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 2633{
9c8cba37 2634 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 2635 uint32_t intr;
2636 int irq = vcpu->arch.interrupt.nr;
9c8cba37 2637
229456fc 2638 trace_kvm_inj_virq(irq);
2714d1d3 2639
fa89a817 2640 ++vcpu->stat.irq_injections;
7ffd92c5 2641 if (vmx->rmode.vm86_active) {
9c8cba37
AK		 2642 vmx->rmode.irq.pending = true;
2643 vmx->rmode.irq.vector = irq;
5fdbf976 2644 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
ae0bb3e0
GN		 2645 if (vcpu->arch.interrupt.soft)
2646 vmx->rmode.irq.rip +=
2647 vmx->vcpu.arch.event_exit_inst_len;
9c5623e3
AK		 2648 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2649 irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2650 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
5fdbf976 2651 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
85f455f7
ED		 2652 return;
2653 }
66fd3f7f
GN		 2654 intr = irq | INTR_INFO_VALID_MASK;
2655 if (vcpu->arch.interrupt.soft) {
2656 intr |= INTR_TYPE_SOFT_INTR;
2657 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2658 vmx->vcpu.arch.event_exit_inst_len);
2659 } else
2660 intr |= INTR_TYPE_EXT_INTR;
2661 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 2662}
2663
f08864b4
SY		 2664static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2665{
66a5a347
JK		 2666 struct vcpu_vmx *vmx = to_vmx(vcpu);
2667
3b86cd99
JK		 2668 if (!cpu_has_virtual_nmis()) {
2669 /*
2670 * Tracking the NMI-blocked state in software is built upon
2671 * finding the next open IRQ window. This, in turn, depends on
2672 * well-behaving guests: They have to keep IRQs disabled at
2673 * least as long as the NMI handler runs. Otherwise we may
2674 * cause NMI nesting, maybe breaking the guest. But as this is
2675 * highly unlikely, we can live with the residual risk.
2676 */
2677 vmx->soft_vnmi_blocked = 1;
2678 vmx->vnmi_blocked_time = 0;
2679 }
2680
487b391d 2681 ++vcpu->stat.nmi_injections;
7ffd92c5 2682 if (vmx->rmode.vm86_active) {
66a5a347
JK		 2683 vmx->rmode.irq.pending = true;
2684 vmx->rmode.irq.vector = NMI_VECTOR;
2685 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2686 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2687 NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2688 INTR_INFO_VALID_MASK);
2689 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2690 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2691 return;
2692 }
f08864b4
SY		 2693 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2694 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 2695}
2696
c4282df9 2697static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
33f089ca 2698{
3b86cd99 2699 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
c4282df9 2700 return 0;
33f089ca 2701
c4282df9
GN		 2702 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2703 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS |
2704 GUEST_INTR_STATE_NMI));
33f089ca
JK		 2705}
2706
3cfc3092
JK		 2707static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
2708{
2709 if (!cpu_has_virtual_nmis())
2710 return to_vmx(vcpu)->soft_vnmi_blocked;
2711 else
2712 return !!(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2713 GUEST_INTR_STATE_NMI);
2714}
2715
2716static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2717{
2718 struct vcpu_vmx *vmx = to_vmx(vcpu);
2719
2720 if (!cpu_has_virtual_nmis()) {
2721 if (vmx->soft_vnmi_blocked != masked) {
2722 vmx->soft_vnmi_blocked = masked;
2723 vmx->vnmi_blocked_time = 0;
2724 }
2725 } else {
2726 if (masked)
2727 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
2728 GUEST_INTR_STATE_NMI);
2729 else
2730 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2731 GUEST_INTR_STATE_NMI);
2732 }
2733}
2734
78646121
GN		 2735static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2736{
c4282df9
GN		 2737 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2738 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2739 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 2740}
2741
cbc94022
IE		 2742static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2743{
2744 int ret;
2745 struct kvm_userspace_memory_region tss_mem = {
6fe63979 2746 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 2747 .guest_phys_addr = addr,
2748 .memory_size = PAGE_SIZE * 3,
2749 .flags = 0,
2750 };
2751
2752 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2753 if (ret)
2754 return ret;
bfc6d222 2755 kvm->arch.tss_addr = addr;
cbc94022
IE		 2756 return 0;
2757}
2758
6aa8b732
AK		 2759static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2760 int vec, u32 err_code)
2761{
b3f37707
NK		 2762 /*
2763 * Instruction with address size override prefix opcode 0x67
2764 * Cause the #SS fault with 0 error code in VM86 mode.
2765 */
2766 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
851ba692 2767 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE)
6aa8b732 2768 return 1;
77ab6db0
JK		 2769 /*
2770 * Forward all other exceptions that are valid in real mode.
2771 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2772 * the required debugging infrastructure rework.
2773 */
2774 switch (vec) {
77ab6db0 2775 case DB_VECTOR:
d0bfb940
JK		 2776 if (vcpu->guest_debug &
2777 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2778 return 0;
2779 kvm_queue_exception(vcpu, vec);
2780 return 1;
77ab6db0 2781 case BP_VECTOR:
d0bfb940
JK		 2782 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2783 return 0;
2784 /* fall through */
2785 case DE_VECTOR:
77ab6db0
JK		 2786 case OF_VECTOR:
2787 case BR_VECTOR:
2788 case UD_VECTOR:
2789 case DF_VECTOR:
2790 case SS_VECTOR:
2791 case GP_VECTOR:
2792 case MF_VECTOR:
2793 kvm_queue_exception(vcpu, vec);
2794 return 1;
2795 }
6aa8b732
AK		 2796 return 0;
2797}
2798
a0861c02
AK		 2799/*
2800 * Trigger machine check on the host. We assume all the MSRs are already set up
2801 * by the CPU and that we still run on the same CPU as the MCE occurred on.
2802 * We pass a fake environment to the machine check handler because we want
2803 * the guest to be always treated like user space, no matter what context
2804 * it used internally.
2805 */
2806static void kvm_machine_check(void)
2807{
2808#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
2809 struct pt_regs regs = {
2810 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
2811 .flags = X86_EFLAGS_IF,
2812 };
2813
2814 do_machine_check(&regs, 0);
2815#endif
2816}
2817
851ba692 2818static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 2819{
2820 /* already handled by vcpu_run */
2821 return 1;
2822}
2823
851ba692 2824static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 2825{
1155f76a 2826 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 2827 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 2828 u32 intr_info, ex_no, error_code;
42dbaa5a 2829 unsigned long cr2, rip, dr6;
6aa8b732
AK		 2830 u32 vect_info;
2831 enum emulation_result er;
2832
1155f76a 2833 vect_info = vmx->idt_vectoring_info;
6aa8b732
AK		 2834 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2835
a0861c02 2836 if (is_machine_check(intr_info))
851ba692 2837 return handle_machine_check(vcpu);
a0861c02 2838
6aa8b732 2839 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
65ac7264
AK		 2840 !is_page_fault(intr_info)) {
2841 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2842 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
2843 vcpu->run->internal.ndata = 2;
2844 vcpu->run->internal.data[0] = vect_info;
2845 vcpu->run->internal.data[1] = intr_info;
2846 return 0;
2847 }
6aa8b732 2848
e4a41889 2849 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 2850 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 2851
2852 if (is_no_device(intr_info)) {
5fd86fcf 2853 vmx_fpu_activate(vcpu);
2ab455cc
AL		 2854 return 1;
2855 }
2856
7aa81cc0 2857 if (is_invalid_opcode(intr_info)) {
851ba692 2858 er = emulate_instruction(vcpu, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 2859 if (er != EMULATE_DONE)
7ee5d940 2860 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 2861 return 1;
2862 }
2863
6aa8b732 2864 error_code = 0;
5fdbf976 2865 rip = kvm_rip_read(vcpu);
2e11384c 2866 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732
AK		 2867 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2868 if (is_page_fault(intr_info)) {
1439442c 2869 /* EPT won't cause page fault directly */
089d034e 2870 if (enable_ept)
1439442c 2871 BUG();
6aa8b732 2872 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 2873 trace_kvm_page_fault(cr2, error_code);
2874
3298b75c 2875 if (kvm_event_needs_reinjection(vcpu))
577bdc49 2876 kvm_mmu_unprotect_page_virt(vcpu, cr2);
3067714c 2877 return kvm_mmu_page_fault(vcpu, cr2, error_code);
6aa8b732
AK		 2878 }
2879
7ffd92c5 2880 if (vmx->rmode.vm86_active &&
6aa8b732 2881 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0 2882 error_code)) {
ad312c7c
ZX		 2883 if (vcpu->arch.halt_request) {
2884 vcpu->arch.halt_request = 0;
72d6e5a0
AK		 2885 return kvm_emulate_halt(vcpu);
2886 }
6aa8b732 2887 return 1;
72d6e5a0 2888 }
6aa8b732 2889
d0bfb940 2890 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
42dbaa5a
JK		 2891 switch (ex_no) {
2892 case DB_VECTOR:
2893 dr6 = vmcs_readl(EXIT_QUALIFICATION);
2894 if (!(vcpu->guest_debug &
2895 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
2896 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
2897 kvm_queue_exception(vcpu, DB_VECTOR);
2898 return 1;
2899 }
2900 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
2901 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
2902 /* fall through */
2903 case BP_VECTOR:
6aa8b732 2904 kvm_run->exit_reason = KVM_EXIT_DEBUG;
d0bfb940
JK		 2905 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
2906 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 2907 break;
2908 default:
d0bfb940
JK		 2909 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2910 kvm_run->ex.exception = ex_no;
2911 kvm_run->ex.error_code = error_code;
42dbaa5a 2912 break;
6aa8b732 2913 }
6aa8b732
AK		 2914 return 0;
2915}
2916
851ba692 2917static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 2918{
1165f5fe 2919 ++vcpu->stat.irq_exits;
6aa8b732
AK		 2920 return 1;
2921}
2922
851ba692 2923static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 2924{
851ba692 2925 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 2926 return 0;
2927}
6aa8b732 2928
851ba692 2929static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 2930{
bfdaab09 2931 unsigned long exit_qualification;
34c33d16 2932 int size, in, string;
039576c0 2933 unsigned port;
6aa8b732 2934
1165f5fe 2935 ++vcpu->stat.io_exits;
bfdaab09 2936 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 2937 string = (exit_qualification & 16) != 0;
e70669ab
LV		 2938
2939 if (string) {
851ba692 2940 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DO_MMIO)
e70669ab
LV		 2941 return 0;
2942 return 1;
2943 }
2944
2945 size = (exit_qualification & 7) + 1;
2946 in = (exit_qualification & 8) != 0;
039576c0 2947 port = exit_qualification >> 16;
e70669ab 2948
e93f36bc 2949 skip_emulated_instruction(vcpu);
851ba692 2950 return kvm_emulate_pio(vcpu, in, size, port);
6aa8b732
AK		 2951}
2952
102d8325
IM		 2953static void
2954vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2955{
2956 /*
2957 * Patch in the VMCALL instruction:
2958 */
2959 hypercall[0] = 0x0f;
2960 hypercall[1] = 0x01;
2961 hypercall[2] = 0xc1;
102d8325
IM		 2962}
2963
851ba692 2964static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 2965{
229456fc 2966 unsigned long exit_qualification, val;
6aa8b732
AK		 2967 int cr;
2968 int reg;
2969
bfdaab09 2970 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 2971 cr = exit_qualification & 15;
2972 reg = (exit_qualification >> 8) & 15;
2973 switch ((exit_qualification >> 4) & 3) {
2974 case 0: /* mov to cr */
229456fc
MT		 2975 val = kvm_register_read(vcpu, reg);
2976 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 2977 switch (cr) {
2978 case 0:
229456fc 2979 kvm_set_cr0(vcpu, val);
6aa8b732
AK		 2980 skip_emulated_instruction(vcpu);
2981 return 1;
2982 case 3:
229456fc 2983 kvm_set_cr3(vcpu, val);
6aa8b732
AK		 2984 skip_emulated_instruction(vcpu);
2985 return 1;
2986 case 4:
229456fc 2987 kvm_set_cr4(vcpu, val);
6aa8b732
AK		 2988 skip_emulated_instruction(vcpu);
2989 return 1;
0a5fff19
GN		 2990 case 8: {
2991 u8 cr8_prev = kvm_get_cr8(vcpu);
2992 u8 cr8 = kvm_register_read(vcpu, reg);
2993 kvm_set_cr8(vcpu, cr8);
2994 skip_emulated_instruction(vcpu);
2995 if (irqchip_in_kernel(vcpu->kvm))
2996 return 1;
2997 if (cr8_prev <= cr8)
2998 return 1;
851ba692 2999 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 3000 return 0;
3001 }
6aa8b732
AK		 3002 };
3003 break;
25c4c276 3004 case 2: /* clts */
5fd86fcf 3005 vmx_fpu_deactivate(vcpu);
ad312c7c 3006 vcpu->arch.cr0 &= ~X86_CR0_TS;
4d4ec087
AK		 3007 vmcs_writel(CR0_READ_SHADOW, kvm_read_cr0(vcpu));
3008 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5fd86fcf 3009 vmx_fpu_activate(vcpu);
25c4c276
AL		 3010 skip_emulated_instruction(vcpu);
3011 return 1;
6aa8b732
AK		 3012 case 1: /*mov from cr*/
3013 switch (cr) {
3014 case 3:
5fdbf976 3015 kvm_register_write(vcpu, reg, vcpu->arch.cr3);
229456fc 3016 trace_kvm_cr_read(cr, vcpu->arch.cr3);
6aa8b732
AK		 3017 skip_emulated_instruction(vcpu);
3018 return 1;
3019 case 8:
229456fc
MT		 3020 val = kvm_get_cr8(vcpu);
3021 kvm_register_write(vcpu, reg, val);
3022 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 3023 skip_emulated_instruction(vcpu);
3024 return 1;
3025 }
3026 break;
3027 case 3: /* lmsw */
a1f83a74 3028 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 3029 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 3030 kvm_lmsw(vcpu, val);
6aa8b732
AK		 3031
3032 skip_emulated_instruction(vcpu);
3033 return 1;
3034 default:
3035 break;
3036 }
851ba692 3037 vcpu->run->exit_reason = 0;
f0242478 3038 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 3039 (int)(exit_qualification >> 4) & 3, cr);
3040 return 0;
3041}
3042
851ba692 3043static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 3044{
bfdaab09 3045 unsigned long exit_qualification;
6aa8b732
AK		 3046 unsigned long val;
3047 int dr, reg;
3048
0a79b009
AK		 3049 if (!kvm_require_cpl(vcpu, 0))
3050 return 1;
42dbaa5a
JK		 3051 dr = vmcs_readl(GUEST_DR7);
3052 if (dr & DR7_GD) {
3053 /*
3054 * As the vm-exit takes precedence over the debug trap, we
3055 * need to emulate the latter, either for the host or the
3056 * guest debugging itself.
3057 */
3058 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 3059 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
3060 vcpu->run->debug.arch.dr7 = dr;
3061 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 3062 vmcs_readl(GUEST_CS_BASE) +
3063 vmcs_readl(GUEST_RIP);
851ba692
AK		 3064 vcpu->run->debug.arch.exception = DB_VECTOR;
3065 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 3066 return 0;
3067 } else {
3068 vcpu->arch.dr7 &= ~DR7_GD;
3069 vcpu->arch.dr6 |= DR6_BD;
3070 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3071 kvm_queue_exception(vcpu, DB_VECTOR);
3072 return 1;
3073 }
3074 }
3075
bfdaab09 3076 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 3077 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
3078 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
3079 if (exit_qualification & TYPE_MOV_FROM_DR) {
6aa8b732 3080 switch (dr) {
42dbaa5a
JK		 3081 case 0 ... 3:
3082 val = vcpu->arch.db[dr];
3083 break;
6aa8b732 3084 case 6:
42dbaa5a 3085 val = vcpu->arch.dr6;
6aa8b732
AK		 3086 break;
3087 case 7:
42dbaa5a 3088 val = vcpu->arch.dr7;
6aa8b732
AK		 3089 break;
3090 default:
3091 val = 0;
3092 }
5fdbf976 3093 kvm_register_write(vcpu, reg, val);
6aa8b732 3094 } else {
42dbaa5a
JK		 3095 val = vcpu->arch.regs[reg];
3096 switch (dr) {
3097 case 0 ... 3:
3098 vcpu->arch.db[dr] = val;
3099 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
3100 vcpu->arch.eff_db[dr] = val;
3101 break;
3102 case 4 ... 5:
fc78f519 3103 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
42dbaa5a
JK		 3104 kvm_queue_exception(vcpu, UD_VECTOR);
3105 break;
3106 case 6:
3107 if (val & 0xffffffff00000000ULL) {
3108 kvm_queue_exception(vcpu, GP_VECTOR);
3109 break;
3110 }
3111 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
3112 break;
3113 case 7:
3114 if (val & 0xffffffff00000000ULL) {
3115 kvm_queue_exception(vcpu, GP_VECTOR);
3116 break;
3117 }
3118 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
3119 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
3120 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3121 vcpu->arch.switch_db_regs =
3122 (val & DR7_BP_EN_MASK);
3123 }
3124 break;
3125 }
6aa8b732 3126 }
6aa8b732
AK		 3127 skip_emulated_instruction(vcpu);
3128 return 1;
3129}
3130
851ba692 3131static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 3132{
06465c5a
AK		 3133 kvm_emulate_cpuid(vcpu);
3134 return 1;
6aa8b732
AK		 3135}
3136
851ba692 3137static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 3138{
ad312c7c 3139 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 3140 u64 data;
3141
3142 if (vmx_get_msr(vcpu, ecx, &data)) {
c1a5d4f9 3143 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 3144 return 1;
3145 }
3146
229456fc 3147 trace_kvm_msr_read(ecx, data);
2714d1d3 3148
6aa8b732 3149 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 3150 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3151 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 3152 skip_emulated_instruction(vcpu);
3153 return 1;
3154}
3155
851ba692 3156static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 3157{
ad312c7c
ZX		 3158 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3159 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3160 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 3161
229456fc 3162 trace_kvm_msr_write(ecx, data);
2714d1d3 3163
6aa8b732 3164 if (vmx_set_msr(vcpu, ecx, data) != 0) {
c1a5d4f9 3165 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 3166 return 1;
3167 }
3168
3169 skip_emulated_instruction(vcpu);
3170 return 1;
3171}
3172
851ba692 3173static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c
YS		 3174{
3175 return 1;
3176}
3177
851ba692 3178static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 3179{
85f455f7
ED		 3180 u32 cpu_based_vm_exec_control;
3181
3182 /* clear pending irq */
3183 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3184 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3185 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 3186
a26bf12a 3187 ++vcpu->stat.irq_window_exits;
2714d1d3 3188
c1150d8c
DL		 3189 /*
3190 * If the user space waits to inject interrupts, exit as soon as
3191 * possible
3192 */
8061823a 3193 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 3194 vcpu->run->request_interrupt_window &&
8061823a 3195 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 3196 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 3197 return 0;
3198 }
6aa8b732
AK		 3199 return 1;
3200}
3201
851ba692 3202static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 3203{
3204 skip_emulated_instruction(vcpu);
d3bef15f 3205 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 3206}
3207
851ba692 3208static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 3209{
510043da 3210 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 3211 kvm_emulate_hypercall(vcpu);
3212 return 1;
c21415e8
IM		 3213}
3214
851ba692 3215static int handle_vmx_insn(struct kvm_vcpu *vcpu)
e3c7cb6a
AK		 3216{
3217 kvm_queue_exception(vcpu, UD_VECTOR);
3218 return 1;
3219}
3220
851ba692 3221static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 3222{
f9c617f6 3223 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 3224
3225 kvm_mmu_invlpg(vcpu, exit_qualification);
3226 skip_emulated_instruction(vcpu);
3227 return 1;
3228}
3229
851ba692 3230static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 3231{
3232 skip_emulated_instruction(vcpu);
3233 /* TODO: Add support for VT-d/pass-through device */
3234 return 1;
3235}
3236
851ba692 3237static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 3238{
f9c617f6 3239 unsigned long exit_qualification;
f78e0e2e
SY		 3240 enum emulation_result er;
3241 unsigned long offset;
3242
f9c617f6 3243 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
f78e0e2e
SY		 3244 offset = exit_qualification & 0xffful;
3245
851ba692 3246 er = emulate_instruction(vcpu, 0, 0, 0);
f78e0e2e
SY		 3247
3248 if (er != EMULATE_DONE) {
3249 printk(KERN_ERR
3250 "Fail to handle apic access vmexit! Offset is 0x%lx\n",
3251 offset);
7f582ab6 3252 return -ENOEXEC;
f78e0e2e
SY		 3253 }
3254 return 1;
3255}
3256
851ba692 3257static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 3258{
60637aac 3259 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29
IE		 3260 unsigned long exit_qualification;
3261 u16 tss_selector;
64a7ec06
GN		 3262 int reason, type, idt_v;
3263
3264 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3265 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 3266
3267 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3268
3269 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 3270 if (reason == TASK_SWITCH_GATE && idt_v) {
3271 switch (type) {
3272 case INTR_TYPE_NMI_INTR:
3273 vcpu->arch.nmi_injected = false;
3274 if (cpu_has_virtual_nmis())
3275 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3276 GUEST_INTR_STATE_NMI);
3277 break;
3278 case INTR_TYPE_EXT_INTR:
66fd3f7f 3279 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 3280 kvm_clear_interrupt_queue(vcpu);
3281 break;
3282 case INTR_TYPE_HARD_EXCEPTION:
3283 case INTR_TYPE_SOFT_EXCEPTION:
3284 kvm_clear_exception_queue(vcpu);
3285 break;
3286 default:
3287 break;
3288 }
60637aac 3289 }
37817f29
IE		 3290 tss_selector = exit_qualification;
3291
64a7ec06
GN		 3292 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3293 type != INTR_TYPE_EXT_INTR &&
3294 type != INTR_TYPE_NMI_INTR))
3295 skip_emulated_instruction(vcpu);
3296
42dbaa5a
JK		 3297 if (!kvm_task_switch(vcpu, tss_selector, reason))
3298 return 0;
3299
3300 /* clear all local breakpoint enable flags */
3301 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3302
3303 /*
3304 * TODO: What about debug traps on tss switch?
3305 * Are we supposed to inject them and update dr6?
3306 */
3307
3308 return 1;
37817f29
IE		 3309}
3310
851ba692 3311static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 3312{
f9c617f6 3313 unsigned long exit_qualification;
1439442c 3314 gpa_t gpa;
1439442c 3315 int gla_validity;
1439442c 3316
f9c617f6 3317 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c
SY		 3318
3319 if (exit_qualification & (1 << 6)) {
3320 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
7f582ab6 3321 return -EINVAL;
1439442c
SY		 3322 }
3323
3324 gla_validity = (exit_qualification >> 7) & 0x3;
3325 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3326 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3327 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3328 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 3329 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 3330 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3331 (long unsigned int)exit_qualification);
851ba692
AK		 3332 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3333 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 3334 return 0;
1439442c
SY		 3335 }
3336
3337 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 3338 trace_kvm_page_fault(gpa, exit_qualification);
49cd7d22 3339 return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
1439442c
SY		 3340}
3341
68f89400
MT		 3342static u64 ept_rsvd_mask(u64 spte, int level)
3343{
3344 int i;
3345 u64 mask = 0;
3346
3347 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3348 mask |= (1ULL << i);
3349
3350 if (level > 2)
3351 /* bits 7:3 reserved */
3352 mask |= 0xf8;
3353 else if (level == 2) {
3354 if (spte & (1ULL << 7))
3355 /* 2MB ref, bits 20:12 reserved */
3356 mask |= 0x1ff000;
3357 else
3358 /* bits 6:3 reserved */
3359 mask |= 0x78;
3360 }
3361
3362 return mask;
3363}
3364
3365static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3366 int level)
3367{
3368 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3369
3370 /* 010b (write-only) */
3371 WARN_ON((spte & 0x7) == 0x2);
3372
3373 /* 110b (write/execute) */
3374 WARN_ON((spte & 0x7) == 0x6);
3375
3376 /* 100b (execute-only) and value not supported by logical processor */
3377 if (!cpu_has_vmx_ept_execute_only())
3378 WARN_ON((spte & 0x7) == 0x4);
3379
3380 /* not 000b */
3381 if ((spte & 0x7)) {
3382 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3383
3384 if (rsvd_bits != 0) {
3385 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3386 __func__, rsvd_bits);
3387 WARN_ON(1);
3388 }
3389
3390 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3391 u64 ept_mem_type = (spte & 0x38) >> 3;
3392
3393 if (ept_mem_type == 2 || ept_mem_type == 3 ||
3394 ept_mem_type == 7) {
3395 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3396 __func__, ept_mem_type);
3397 WARN_ON(1);
3398 }
3399 }
3400 }
3401}
3402
851ba692 3403static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 3404{
3405 u64 sptes[4];
3406 int nr_sptes, i;
3407 gpa_t gpa;
3408
3409 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3410
3411 printk(KERN_ERR "EPT: Misconfiguration.\n");
3412 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3413
3414 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3415
3416 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3417 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3418
851ba692
AK		 3419 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3420 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 3421
3422 return 0;
3423}
3424
851ba692 3425static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 3426{
3427 u32 cpu_based_vm_exec_control;
3428
3429 /* clear pending NMI */
3430 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3431 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3432 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3433 ++vcpu->stat.nmi_window_exits;
3434
3435 return 1;
3436}
3437
80ced186 3438static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 3439{
8b3079a5
AK		 3440 struct vcpu_vmx *vmx = to_vmx(vcpu);
3441 enum emulation_result err = EMULATE_DONE;
80ced186 3442 int ret = 1;
ea953ef0
MG		 3443
3444 while (!guest_state_valid(vcpu)) {
851ba692 3445 err = emulate_instruction(vcpu, 0, 0, 0);
ea953ef0 3446
80ced186
MG		 3447 if (err == EMULATE_DO_MMIO) {
3448 ret = 0;
3449 goto out;
3450 }
1d5a4d9b
GT		 3451
3452 if (err != EMULATE_DONE) {
3453 kvm_report_emulation_failure(vcpu, "emulation failure");
80ced186
MG		 3454 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3455 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
a9c7399d 3456 vcpu->run->internal.ndata = 0;
80ced186
MG		 3457 ret = 0;
3458 goto out;
ea953ef0
MG		 3459 }
3460
3461 if (signal_pending(current))
80ced186 3462 goto out;
ea953ef0
MG		 3463 if (need_resched())
3464 schedule();
3465 }
3466
80ced186
MG		 3467 vmx->emulation_required = 0;
3468out:
3469 return ret;
ea953ef0
MG		 3470}
3471
4b8d54f9
ZE		 3472/*
3473 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3474 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3475 */
9fb41ba8 3476static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 3477{
3478 skip_emulated_instruction(vcpu);
3479 kvm_vcpu_on_spin(vcpu);
3480
3481 return 1;
3482}
3483
59708670
SY		 3484static int handle_invalid_op(struct kvm_vcpu *vcpu)
3485{
3486 kvm_queue_exception(vcpu, UD_VECTOR);
3487 return 1;
3488}
3489
6aa8b732
AK		 3490/*
3491 * The exit handlers return 1 if the exit was handled fully and guest execution
3492 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3493 * to be done to userspace and return 0.
3494 */
851ba692 3495static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 3496 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3497 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 3498 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 3499 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 3500 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 3501 [EXIT_REASON_CR_ACCESS] = handle_cr,
3502 [EXIT_REASON_DR_ACCESS] = handle_dr,
3503 [EXIT_REASON_CPUID] = handle_cpuid,
3504 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3505 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3506 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3507 [EXIT_REASON_HLT] = handle_halt,
a7052897 3508 [EXIT_REASON_INVLPG] = handle_invlpg,
c21415e8 3509 [EXIT_REASON_VMCALL] = handle_vmcall,
e3c7cb6a
AK		 3510 [EXIT_REASON_VMCLEAR] = handle_vmx_insn,
3511 [EXIT_REASON_VMLAUNCH] = handle_vmx_insn,
3512 [EXIT_REASON_VMPTRLD] = handle_vmx_insn,
3513 [EXIT_REASON_VMPTRST] = handle_vmx_insn,
3514 [EXIT_REASON_VMREAD] = handle_vmx_insn,
3515 [EXIT_REASON_VMRESUME] = handle_vmx_insn,
3516 [EXIT_REASON_VMWRITE] = handle_vmx_insn,
3517 [EXIT_REASON_VMOFF] = handle_vmx_insn,
3518 [EXIT_REASON_VMON] = handle_vmx_insn,
f78e0e2e
SY		 3519 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3520 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 3521 [EXIT_REASON_WBINVD] = handle_wbinvd,
37817f29 3522 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 3523 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 3524 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
3525 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 3526 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 3527 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
3528 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
6aa8b732
AK		 3529};
3530
3531static const int kvm_vmx_max_exit_handlers =
50a3485c 3532 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732
AK		 3533
3534/*
3535 * The guest has exited. See if we can fix it or if we need userspace
3536 * assistance.
3537 */
851ba692 3538static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 3539{
29bd8a78 3540 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 3541 u32 exit_reason = vmx->exit_reason;
1155f76a 3542 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 3543
229456fc 3544 trace_kvm_exit(exit_reason, kvm_rip_read(vcpu));
2714d1d3 3545
80ced186
MG		 3546 /* If guest state is invalid, start emulating */
3547 if (vmx->emulation_required && emulate_invalid_guest_state)
3548 return handle_invalid_guest_state(vcpu);
1d5a4d9b 3549
1439442c
SY		 3550 /* Access CR3 don't cause VMExit in paging mode, so we need
3551 * to sync with guest real CR3. */
6de4f3ad 3552 if (enable_ept && is_paging(vcpu))
1439442c 3553 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
1439442c 3554
29bd8a78 3555 if (unlikely(vmx->fail)) {
851ba692
AK		 3556 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3557 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 3558 = vmcs_read32(VM_INSTRUCTION_ERROR);
3559 return 0;
3560 }
6aa8b732 3561
d77c26fc 3562 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 3563 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac
JK		 3564 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3565 exit_reason != EXIT_REASON_TASK_SWITCH))
3566 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3567 "(0x%x) and exit reason is 0x%x\n",
3568 __func__, vectoring_info, exit_reason);
3b86cd99
JK		 3569
3570 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
c4282df9 3571 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 3572 vmx->soft_vnmi_blocked = 0;
3b86cd99 3573 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 3574 vcpu->arch.nmi_pending) {
3b86cd99
JK		 3575 /*
3576 * This CPU don't support us in finding the end of an
3577 * NMI-blocked window if the guest runs with IRQs
3578 * disabled. So we pull the trigger after 1 s of
3579 * futile waiting, but inform the user about this.
3580 */
3581 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3582 "state on VCPU %d after 1 s timeout\n",
3583 __func__, vcpu->vcpu_id);
3584 vmx->soft_vnmi_blocked = 0;
3b86cd99 3585 }
3b86cd99
JK		 3586 }
3587
6aa8b732
AK		 3588 if (exit_reason < kvm_vmx_max_exit_handlers
3589 && kvm_vmx_exit_handlers[exit_reason])
851ba692 3590 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 3591 else {
851ba692
AK		 3592 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3593 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 3594 }
3595 return 0;
3596}
3597
95ba8273 3598static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 3599{
95ba8273 3600 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 3601 vmcs_write32(TPR_THRESHOLD, 0);
3602 return;
3603 }
3604
95ba8273 3605 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 3606}
3607
cf393f75
AK		 3608static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3609{
3610 u32 exit_intr_info;
7b4a25cb 3611 u32 idt_vectoring_info = vmx->idt_vectoring_info;
cf393f75
AK		 3612 bool unblock_nmi;
3613 u8 vector;
668f612f
AK		 3614 int type;
3615 bool idtv_info_valid;
cf393f75
AK		 3616
3617 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
20f65983 3618
a0861c02
AK		 3619 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
3620
3621 /* Handle machine checks before interrupts are enabled */
3622 if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3623 || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3624 && is_machine_check(exit_intr_info)))
3625 kvm_machine_check();
3626
20f65983
GN		 3627 /* We need to handle NMIs before interrupts are enabled */
3628 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
229456fc 3629 (exit_intr_info & INTR_INFO_VALID_MASK))
20f65983 3630 asm("int $2");
20f65983
GN		 3631
3632 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3633
cf393f75
AK		 3634 if (cpu_has_virtual_nmis()) {
3635 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3636 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3637 /*
7b4a25cb 3638 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 3639 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3640 * a guest IRET fault.
7b4a25cb
GN		 3641 * SDM 3: 23.2.2 (September 2008)
3642 * Bit 12 is undefined in any of the following cases:
3643 * If the VM exit sets the valid bit in the IDT-vectoring
3644 * information field.
3645 * If the VM exit is due to a double fault.
cf393f75 3646 */
7b4a25cb
GN		 3647 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3648 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 3649 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3650 GUEST_INTR_STATE_NMI);
3b86cd99
JK		 3651 } else if (unlikely(vmx->soft_vnmi_blocked))
3652 vmx->vnmi_blocked_time +=
3653 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
668f612f 3654
37b96e98
GN		 3655 vmx->vcpu.arch.nmi_injected = false;
3656 kvm_clear_exception_queue(&vmx->vcpu);
3657 kvm_clear_interrupt_queue(&vmx->vcpu);
3658
3659 if (!idtv_info_valid)
3660 return;
3661
668f612f
AK		 3662 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3663 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 3664
64a7ec06 3665 switch (type) {
37b96e98
GN		 3666 case INTR_TYPE_NMI_INTR:
3667 vmx->vcpu.arch.nmi_injected = true;
668f612f 3668 /*
7b4a25cb 3669 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 3670 * Clear bit "block by NMI" before VM entry if a NMI
3671 * delivery faulted.
668f612f 3672 */
37b96e98
GN		 3673 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3674 GUEST_INTR_STATE_NMI);
3675 break;
37b96e98 3676 case INTR_TYPE_SOFT_EXCEPTION:
66fd3f7f
GN		 3677 vmx->vcpu.arch.event_exit_inst_len =
3678 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3679 /* fall through */
3680 case INTR_TYPE_HARD_EXCEPTION:
35920a35 3681 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
37b96e98
GN		 3682 u32 err = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3683 kvm_queue_exception_e(&vmx->vcpu, vector, err);
35920a35
AK		 3684 } else
3685 kvm_queue_exception(&vmx->vcpu, vector);
37b96e98 3686 break;
66fd3f7f
GN		 3687 case INTR_TYPE_SOFT_INTR:
3688 vmx->vcpu.arch.event_exit_inst_len =
3689 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3690 /* fall through */
37b96e98 3691 case INTR_TYPE_EXT_INTR:
66fd3f7f
GN		 3692 kvm_queue_interrupt(&vmx->vcpu, vector,
3693 type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 3694 break;
3695 default:
3696 break;
f7d9238f 3697 }
cf393f75
AK		 3698}
3699
9c8cba37
AK		 3700/*
3701 * Failure to inject an interrupt should give us the information
3702 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
3703 * when fetching the interrupt redirection bitmap in the real-mode
3704 * tss, this doesn't happen. So we do it ourselves.
3705 */
3706static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3707{
3708 vmx->rmode.irq.pending = 0;
5fdbf976 3709 if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
9c8cba37 3710 return;
5fdbf976 3711 kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
9c8cba37
AK		 3712 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3713 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3714 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3715 return;
3716 }
3717 vmx->idt_vectoring_info =
3718 VECTORING_INFO_VALID_MASK
3719 | INTR_TYPE_EXT_INTR
3720 | vmx->rmode.irq.vector;
3721}
3722
c801949d
AK		 3723#ifdef CONFIG_X86_64
3724#define R "r"
3725#define Q "q"
3726#else
3727#define R "e"
3728#define Q "l"
3729#endif
3730
851ba692 3731static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 3732{
a2fa3e9f 3733 struct vcpu_vmx *vmx = to_vmx(vcpu);
e6adf283 3734
3b86cd99
JK		 3735 /* Record the guest's net vcpu time for enforced NMI injections. */
3736 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3737 vmx->entry_time = ktime_get();
3738
80ced186
MG		 3739 /* Don't enter VMX if guest state is invalid, let the exit handler
3740 start emulation until we arrive back to a valid state */
3741 if (vmx->emulation_required && emulate_invalid_guest_state)
a89a8fb9 3742 return;
a89a8fb9 3743
5fdbf976
MT		 3744 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3745 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3746 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3747 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3748
787ff736
GN		 3749 /* When single-stepping over STI and MOV SS, we must clear the
3750 * corresponding interruptibility bits in the guest state. Otherwise
3751 * vmentry fails as it then expects bit 14 (BS) in pending debug
3752 * exceptions being set, but that's not correct for the guest debugging
3753 * case. */
3754 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3755 vmx_set_interrupt_shadow(vcpu, 0);
3756
e6adf283
AK		 3757 /*
3758 * Loading guest fpu may have cleared host cr0.ts
3759 */
3760 vmcs_writel(HOST_CR0, read_cr0());
3761
e8a48342
AK		 3762 if (vcpu->arch.switch_db_regs)
3763 set_debugreg(vcpu->arch.dr6, 6);
42dbaa5a 3764
d77c26fc 3765 asm(
6aa8b732 3766 /* Store host registers */
c801949d
AK		 3767 "push %%"R"dx; push %%"R"bp;"
3768 "push %%"R"cx \n\t"
313dbd49
AK		 3769 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3770 "je 1f \n\t"
3771 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
4ecac3fd 3772 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 3773 "1: \n\t"
d3edefc0
AK		 3774 /* Reload cr2 if changed */
3775 "mov %c[cr2](%0), %%"R"ax \n\t"
3776 "mov %%cr2, %%"R"dx \n\t"
3777 "cmp %%"R"ax, %%"R"dx \n\t"
3778 "je 2f \n\t"
3779 "mov %%"R"ax, %%cr2 \n\t"
3780 "2: \n\t"
6aa8b732 3781 /* Check if vmlaunch of vmresume is needed */
e08aa78a 3782 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 3783 /* Load guest registers. Don't clobber flags. */
c801949d
AK		 3784 "mov %c[rax](%0), %%"R"ax \n\t"
3785 "mov %c[rbx](%0), %%"R"bx \n\t"
3786 "mov %c[rdx](%0), %%"R"dx \n\t"
3787 "mov %c[rsi](%0), %%"R"si \n\t"
3788 "mov %c[rdi](%0), %%"R"di \n\t"
3789 "mov %c[rbp](%0), %%"R"bp \n\t"
05b3e0c2 3790#ifdef CONFIG_X86_64
e08aa78a
AK		 3791 "mov %c[r8](%0), %%r8 \n\t"
3792 "mov %c[r9](%0), %%r9 \n\t"
3793 "mov %c[r10](%0), %%r10 \n\t"
3794 "mov %c[r11](%0), %%r11 \n\t"
3795 "mov %c[r12](%0), %%r12 \n\t"
3796 "mov %c[r13](%0), %%r13 \n\t"
3797 "mov %c[r14](%0), %%r14 \n\t"
3798 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 3799#endif
c801949d
AK		 3800 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3801
6aa8b732 3802 /* Enter guest mode */
cd2276a7 3803 "jne .Llaunched \n\t"
4ecac3fd 3804 __ex(ASM_VMX_VMLAUNCH) "\n\t"
cd2276a7 3805 "jmp .Lkvm_vmx_return \n\t"
4ecac3fd 3806 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
cd2276a7 3807 ".Lkvm_vmx_return: "
6aa8b732 3808 /* Save guest registers, load host registers, keep flags */
c801949d
AK		 3809 "xchg %0, (%%"R"sp) \n\t"
3810 "mov %%"R"ax, %c[rax](%0) \n\t"
3811 "mov %%"R"bx, %c[rbx](%0) \n\t"
3812 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3813 "mov %%"R"dx, %c[rdx](%0) \n\t"
3814 "mov %%"R"si, %c[rsi](%0) \n\t"
3815 "mov %%"R"di, %c[rdi](%0) \n\t"
3816 "mov %%"R"bp, %c[rbp](%0) \n\t"
05b3e0c2 3817#ifdef CONFIG_X86_64
e08aa78a
AK		 3818 "mov %%r8, %c[r8](%0) \n\t"
3819 "mov %%r9, %c[r9](%0) \n\t"
3820 "mov %%r10, %c[r10](%0) \n\t"
3821 "mov %%r11, %c[r11](%0) \n\t"
3822 "mov %%r12, %c[r12](%0) \n\t"
3823 "mov %%r13, %c[r13](%0) \n\t"
3824 "mov %%r14, %c[r14](%0) \n\t"
3825 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 3826#endif
c801949d
AK		 3827 "mov %%cr2, %%"R"ax \n\t"
3828 "mov %%"R"ax, %c[cr2](%0) \n\t"
3829
3830 "pop %%"R"bp; pop %%"R"bp; pop %%"R"dx \n\t"
e08aa78a
AK		 3831 "setbe %c[fail](%0) \n\t"
3832 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3833 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3834 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 3835 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 3836 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3837 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3838 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3839 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3840 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3841 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3842 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 3843#ifdef CONFIG_X86_64
ad312c7c
ZX		 3844 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3845 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3846 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3847 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3848 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3849 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3850 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3851 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 3852#endif
ad312c7c 3853 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
c2036300 3854 : "cc", "memory"
c801949d 3855 , R"bx", R"di", R"si"
c2036300 3856#ifdef CONFIG_X86_64
c2036300
LV		 3857 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3858#endif
3859 );
6aa8b732 3860
6de4f3ad
AK		 3861 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
3862 | (1 << VCPU_EXREG_PDPTR));
5fdbf976
MT		 3863 vcpu->arch.regs_dirty = 0;
3864
e8a48342
AK		 3865 if (vcpu->arch.switch_db_regs)
3866 get_debugreg(vcpu->arch.dr6, 6);
42dbaa5a 3867
1155f76a 3868 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9c8cba37
AK		 3869 if (vmx->rmode.irq.pending)
3870 fixup_rmode_irq(vmx);
1155f76a 3871
d77c26fc 3872 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
15ad7146 3873 vmx->launched = 1;
1b6269db 3874
cf393f75 3875 vmx_complete_interrupts(vmx);
6aa8b732
AK		 3876}
3877
c801949d
AK		 3878#undef R
3879#undef Q
3880
6aa8b732
AK		 3881static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3882{
a2fa3e9f
GH		 3883 struct vcpu_vmx *vmx = to_vmx(vcpu);
3884
3885 if (vmx->vmcs) {
543e4243 3886 vcpu_clear(vmx);
a2fa3e9f
GH		 3887 free_vmcs(vmx->vmcs);
3888 vmx->vmcs = NULL;
6aa8b732
AK		 3889 }
3890}
3891
3892static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3893{
fb3f0f51
RR		 3894 struct vcpu_vmx *vmx = to_vmx(vcpu);
3895
2384d2b3
SY		 3896 spin_lock(&vmx_vpid_lock);
3897 if (vmx->vpid != 0)
3898 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3899 spin_unlock(&vmx_vpid_lock);
6aa8b732 3900 vmx_free_vmcs(vcpu);
fb3f0f51
RR		 3901 kfree(vmx->guest_msrs);
3902 kvm_vcpu_uninit(vcpu);
a4770347 3903 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 3904}
3905
fb3f0f51 3906static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 3907{
fb3f0f51 3908 int err;
c16f862d 3909 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 3910 int cpu;
6aa8b732 3911
a2fa3e9f 3912 if (!vmx)
fb3f0f51
RR		 3913 return ERR_PTR(-ENOMEM);
3914
2384d2b3
SY		 3915 allocate_vpid(vmx);
3916
fb3f0f51
RR		 3917 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3918 if (err)
3919 goto free_vcpu;
965b58a5 3920
a2fa3e9f 3921 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
fb3f0f51
RR		 3922 if (!vmx->guest_msrs) {
3923 err = -ENOMEM;
3924 goto uninit_vcpu;
3925 }
965b58a5 3926
a2fa3e9f
GH		 3927 vmx->vmcs = alloc_vmcs();
3928 if (!vmx->vmcs)
fb3f0f51 3929 goto free_msrs;
a2fa3e9f
GH		 3930
3931 vmcs_clear(vmx->vmcs);
3932
15ad7146
AK		 3933 cpu = get_cpu();
3934 vmx_vcpu_load(&vmx->vcpu, cpu);
8b9cf98c 3935 err = vmx_vcpu_setup(vmx);
fb3f0f51 3936 vmx_vcpu_put(&vmx->vcpu);
15ad7146 3937 put_cpu();
fb3f0f51
RR		 3938 if (err)
3939 goto free_vmcs;
5e4a0b3c
MT		 3940 if (vm_need_virtualize_apic_accesses(kvm))
3941 if (alloc_apic_access_page(kvm) != 0)
3942 goto free_vmcs;
fb3f0f51 3943
b927a3ce
SY		 3944 if (enable_ept) {
3945 if (!kvm->arch.ept_identity_map_addr)
3946 kvm->arch.ept_identity_map_addr =
3947 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
b7ebfb05
SY		 3948 if (alloc_identity_pagetable(kvm) != 0)
3949 goto free_vmcs;
b927a3ce 3950 }
b7ebfb05 3951
fb3f0f51
RR		 3952 return &vmx->vcpu;
3953
3954free_vmcs:
3955 free_vmcs(vmx->vmcs);
3956free_msrs:
fb3f0f51
RR		 3957 kfree(vmx->guest_msrs);
3958uninit_vcpu:
3959 kvm_vcpu_uninit(&vmx->vcpu);
3960free_vcpu:
a4770347 3961 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 3962 return ERR_PTR(err);
6aa8b732
AK		 3963}
3964
002c7f7c
YS		 3965static void __init vmx_check_processor_compat(void *rtn)
3966{
3967 struct vmcs_config vmcs_conf;
3968
3969 *(int *)rtn = 0;
3970 if (setup_vmcs_config(&vmcs_conf) < 0)
3971 *(int *)rtn = -EIO;
3972 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
3973 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
3974 smp_processor_id());
3975 *(int *)rtn = -EIO;
3976 }
3977}
3978
67253af5
SY		 3979static int get_ept_level(void)
3980{
3981 return VMX_EPT_DEFAULT_GAW + 1;
3982}
3983
4b12f0de 3984static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 3985{
4b12f0de
SY		 3986 u64 ret;
3987
522c68c4
SY		 3988 /* For VT-d and EPT combination
3989 * 1. MMIO: always map as UC
3990 * 2. EPT with VT-d:
3991 * a. VT-d without snooping control feature: can't guarantee the
3992 * result, try to trust guest.
3993 * b. VT-d with snooping control feature: snooping control feature of
3994 * VT-d engine can guarantee the cache correctness. Just set it
3995 * to WB to keep consistent with host. So the same as item 3.
3996 * 3. EPT without VT-d: always map as WB and set IGMT=1 to keep
3997 * consistent with host MTRR
3998 */
4b12f0de
SY		 3999 if (is_mmio)
4000 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 4001 else if (vcpu->kvm->arch.iommu_domain &&
4002 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
4003 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
4004 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 4005 else
522c68c4
SY		 4006 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
4007 | VMX_EPT_IGMT_BIT;
4b12f0de
SY		 4008
4009 return ret;
64d4d521
SY		 4010}
4011
f4c9e87c
AK		 4012#define _ER(x) { EXIT_REASON_##x, #x }
4013
229456fc 4014static const struct trace_print_flags vmx_exit_reasons_str[] = {
f4c9e87c
AK		 4015 _ER(EXCEPTION_NMI),
4016 _ER(EXTERNAL_INTERRUPT),
4017 _ER(TRIPLE_FAULT),
4018 _ER(PENDING_INTERRUPT),
4019 _ER(NMI_WINDOW),
4020 _ER(TASK_SWITCH),
4021 _ER(CPUID),
4022 _ER(HLT),
4023 _ER(INVLPG),
4024 _ER(RDPMC),
4025 _ER(RDTSC),
4026 _ER(VMCALL),
4027 _ER(VMCLEAR),
4028 _ER(VMLAUNCH),
4029 _ER(VMPTRLD),
4030 _ER(VMPTRST),
4031 _ER(VMREAD),
4032 _ER(VMRESUME),
4033 _ER(VMWRITE),
4034 _ER(VMOFF),
4035 _ER(VMON),
4036 _ER(CR_ACCESS),
4037 _ER(DR_ACCESS),
4038 _ER(IO_INSTRUCTION),
4039 _ER(MSR_READ),
4040 _ER(MSR_WRITE),
4041 _ER(MWAIT_INSTRUCTION),
4042 _ER(MONITOR_INSTRUCTION),
4043 _ER(PAUSE_INSTRUCTION),
4044 _ER(MCE_DURING_VMENTRY),
4045 _ER(TPR_BELOW_THRESHOLD),
4046 _ER(APIC_ACCESS),
4047 _ER(EPT_VIOLATION),
4048 _ER(EPT_MISCONFIG),
4049 _ER(WBINVD),
229456fc
MT		 4050 { -1, NULL }
4051};
4052
f4c9e87c
AK		 4053#undef _ER
4054
17cc3935 4055static int vmx_get_lpage_level(void)
344f414f 4056{
878403b7
SY		 4057 if (enable_ept && !cpu_has_vmx_ept_1g_page())
4058 return PT_DIRECTORY_LEVEL;
4059 else
4060 /* For shadow and EPT supported 1GB page */
4061 return PT_PDPE_LEVEL;
344f414f
JR		 4062}
4063
4e47c7a6
SY		 4064static inline u32 bit(int bitno)
4065{
4066 return 1 << (bitno & 31);
4067}
4068
0e851880
SY		 4069static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
4070{
4e47c7a6
SY		 4071 struct kvm_cpuid_entry2 *best;
4072 struct vcpu_vmx *vmx = to_vmx(vcpu);
4073 u32 exec_control;
4074
4075 vmx->rdtscp_enabled = false;
4076 if (vmx_rdtscp_supported()) {
4077 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
4078 if (exec_control & SECONDARY_EXEC_RDTSCP) {
4079 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
4080 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
4081 vmx->rdtscp_enabled = true;
4082 else {
4083 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4084 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4085 exec_control);
4086 }
4087 }
4088 }
0e851880
SY		 4089}
4090
cbdd1bea 4091static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 4092 .cpu_has_kvm_support = cpu_has_kvm_support,
4093 .disabled_by_bios = vmx_disabled_by_bios,
4094 .hardware_setup = hardware_setup,
4095 .hardware_unsetup = hardware_unsetup,
002c7f7c 4096 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 4097 .hardware_enable = hardware_enable,
4098 .hardware_disable = hardware_disable,
04547156 4099 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 4100
4101 .vcpu_create = vmx_create_vcpu,
4102 .vcpu_free = vmx_free_vcpu,
04d2cc77 4103 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 4104
04d2cc77 4105 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 4106 .vcpu_load = vmx_vcpu_load,
4107 .vcpu_put = vmx_vcpu_put,
4108
4109 .set_guest_debug = set_guest_debug,
4110 .get_msr = vmx_get_msr,
4111 .set_msr = vmx_set_msr,
4112 .get_segment_base = vmx_get_segment_base,
4113 .get_segment = vmx_get_segment,
4114 .set_segment = vmx_set_segment,
2e4d2653 4115 .get_cpl = vmx_get_cpl,
6aa8b732 4116 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 4117 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
25c4c276 4118 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 4119 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 4120 .set_cr3 = vmx_set_cr3,
4121 .set_cr4 = vmx_set_cr4,
6aa8b732 4122 .set_efer = vmx_set_efer,
6aa8b732
AK		 4123 .get_idt = vmx_get_idt,
4124 .set_idt = vmx_set_idt,
4125 .get_gdt = vmx_get_gdt,
4126 .set_gdt = vmx_set_gdt,
5fdbf976 4127 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 4128 .get_rflags = vmx_get_rflags,
4129 .set_rflags = vmx_set_rflags,
4130
4131 .tlb_flush = vmx_flush_tlb,
6aa8b732 4132
6aa8b732 4133 .run = vmx_vcpu_run,
6062d012 4134 .handle_exit = vmx_handle_exit,
6aa8b732 4135 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 4136 .set_interrupt_shadow = vmx_set_interrupt_shadow,
4137 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 4138 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 4139 .set_irq = vmx_inject_irq,
95ba8273 4140 .set_nmi = vmx_inject_nmi,
298101da 4141 .queue_exception = vmx_queue_exception,
78646121 4142 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 4143 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 4144 .get_nmi_mask = vmx_get_nmi_mask,
4145 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 4146 .enable_nmi_window = enable_nmi_window,
4147 .enable_irq_window = enable_irq_window,
4148 .update_cr8_intercept = update_cr8_intercept,
95ba8273 4149
cbc94022 4150 .set_tss_addr = vmx_set_tss_addr,
67253af5 4151 .get_tdp_level = get_ept_level,
4b12f0de 4152 .get_mt_mask = vmx_get_mt_mask,
229456fc
MT		 4153
4154 .exit_reasons_str = vmx_exit_reasons_str,
17cc3935 4155 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 4156
4157 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 4158
4159 .rdtscp_supported = vmx_rdtscp_supported,
6aa8b732
AK		 4160};
4161
4162static int __init vmx_init(void)
4163{
26bb0981
AK		 4164 int r, i;
4165
4166 rdmsrl_safe(MSR_EFER, &host_efer);
4167
4168 for (i = 0; i < NR_VMX_MSR; ++i)
4169 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 4170
3e7c73e9 4171 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 4172 if (!vmx_io_bitmap_a)
4173 return -ENOMEM;
4174
3e7c73e9 4175 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 4176 if (!vmx_io_bitmap_b) {
4177 r = -ENOMEM;
4178 goto out;
4179 }
4180
5897297b
AK		 4181 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4182 if (!vmx_msr_bitmap_legacy) {
25c5f225
SY		 4183 r = -ENOMEM;
4184 goto out1;
4185 }
4186
5897297b
AK		 4187 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4188 if (!vmx_msr_bitmap_longmode) {
4189 r = -ENOMEM;
4190 goto out2;
4191 }
4192
fdef3ad1
HQ		 4193 /*
4194 * Allow direct access to the PC debug port (it is often used for I/O
4195 * delays, but the vmexits simply slow things down).
4196 */
3e7c73e9
AK		 4197 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4198 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 4199
3e7c73e9 4200 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 4201
5897297b
AK		 4202 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4203 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 4204
2384d2b3
SY		 4205 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4206
cb498ea2 4207 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 4208 if (r)
5897297b 4209 goto out3;
25c5f225 4210
5897297b
AK		 4211 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4212 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4213 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4214 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4215 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4216 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
fdef3ad1 4217
089d034e 4218 if (enable_ept) {
1439442c 4219 bypass_guest_pf = 0;
5fdbcb9d 4220 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
2aaf69dc 4221 VMX_EPT_WRITABLE_MASK);
534e38b4 4222 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4b12f0de 4223 VMX_EPT_EXECUTABLE_MASK);
5fdbcb9d
SY		 4224 kvm_enable_tdp();
4225 } else
4226 kvm_disable_tdp();
1439442c 4227
c7addb90
AK		 4228 if (bypass_guest_pf)
4229 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4230
fdef3ad1
HQ		 4231 return 0;
4232
5897297b
AK		 4233out3:
4234 free_page((unsigned long)vmx_msr_bitmap_longmode);
25c5f225 4235out2:
5897297b 4236 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 4237out1:
3e7c73e9 4238 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 4239out:
3e7c73e9 4240 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 4241 return r;
6aa8b732
AK		 4242}
4243
4244static void __exit vmx_exit(void)
4245{
5897297b
AK		 4246 free_page((unsigned long)vmx_msr_bitmap_legacy);
4247 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 4248 free_page((unsigned long)vmx_io_bitmap_b);
4249 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 4250
cb498ea2 4251 kvm_exit();
6aa8b732
AK		 4252}
4253
4254module_init(vmx_init)
4255module_exit(vmx_exit)
kernel source for telekom puls (alcatel/mediatek)