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KVM: VMX: Make guest cr4 mask more conservative
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 *
9 * Authors:
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
85f455f7 18#include "irq.h"
1d737c8a 19#include "mmu.h"
e495606d 20
edf88417 21#include <linux/kvm_host.h>
6aa8b732 22#include <linux/module.h>
9d8f549d 23#include <linux/kernel.h>
6aa8b732
AK		 24#include <linux/mm.h>
25#include <linux/highmem.h>
e8edc6e0 26#include <linux/sched.h>
c7addb90 27#include <linux/moduleparam.h>
229456fc 28#include <linux/ftrace_event.h>
5fdbf976 29#include "kvm_cache_regs.h"
35920a35 30#include "x86.h"
e495606d 31
6aa8b732 32#include <asm/io.h>
3b3be0d1 33#include <asm/desc.h>
13673a90 34#include <asm/vmx.h>
6210e37b 35#include <asm/virtext.h>
a0861c02 36#include <asm/mce.h>
6aa8b732 37
229456fc
MT		 38#include "trace.h"
39
4ecac3fd
AK		 40#define __ex(x) __kvm_handle_fault_on_reboot(x)
41
6aa8b732
AK		 42MODULE_AUTHOR("Qumranet");
43MODULE_LICENSE("GPL");
44
4462d21a 45static int __read_mostly bypass_guest_pf = 1;
c1f8bc04 46module_param(bypass_guest_pf, bool, S_IRUGO);
c7addb90 47
4462d21a 48static int __read_mostly enable_vpid = 1;
736caefe 49module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 50
4462d21a 51static int __read_mostly flexpriority_enabled = 1;
736caefe 52module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 53
4462d21a 54static int __read_mostly enable_ept = 1;
736caefe 55module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 56
3a624e29
NK		 57static int __read_mostly enable_unrestricted_guest = 1;
58module_param_named(unrestricted_guest,
59 enable_unrestricted_guest, bool, S_IRUGO);
60
4462d21a 61static int __read_mostly emulate_invalid_guest_state = 0;
c1f8bc04 62module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 63
cdc0e244
AK		 64#define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
65 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
66#define KVM_GUEST_CR0_MASK \
67 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
68#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
69 (X86_CR0_WP | X86_CR0_NE | X86_CR0_TS | X86_CR0_MP)
70#define KVM_VM_CR0_ALWAYS_ON \
71 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 72#define KVM_CR4_GUEST_OWNED_BITS \
73 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
74 | X86_CR4_OSXMMEXCPT)
75
cdc0e244
AK		 76#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
77#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
78
4b8d54f9
ZE		 79/*
80 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
81 * ple_gap: upper bound on the amount of time between two successive
82 * executions of PAUSE in a loop. Also indicate if ple enabled.
83 * According to test, this time is usually small than 41 cycles.
84 * ple_window: upper bound on the amount of time a guest is allowed to execute
85 * in a PAUSE loop. Tests indicate that most spinlocks are held for
86 * less than 2^12 cycles
87 * Time is measured based on a counter that runs at the same rate as the TSC,
88 * refer SDM volume 3b section 21.6.13 & 22.1.3.
89 */
90#define KVM_VMX_DEFAULT_PLE_GAP 41
91#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
92static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
93module_param(ple_gap, int, S_IRUGO);
94
95static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
96module_param(ple_window, int, S_IRUGO);
97
a2fa3e9f
GH		 98struct vmcs {
99 u32 revision_id;
100 u32 abort;
101 char data[0];
102};
103
26bb0981
AK		 104struct shared_msr_entry {
105 unsigned index;
106 u64 data;
d5696725 107 u64 mask;
26bb0981
AK		 108};
109
a2fa3e9f 110struct vcpu_vmx {
fb3f0f51 111 struct kvm_vcpu vcpu;
543e4243 112 struct list_head local_vcpus_link;
313dbd49 113 unsigned long host_rsp;
a2fa3e9f 114 int launched;
29bd8a78 115 u8 fail;
1155f76a 116 u32 idt_vectoring_info;
26bb0981 117 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 118 int nmsrs;
119 int save_nmsrs;
a2fa3e9f 120#ifdef CONFIG_X86_64
44ea2b17
AK		 121 u64 msr_host_kernel_gs_base;
122 u64 msr_guest_kernel_gs_base;
a2fa3e9f
GH		 123#endif
124 struct vmcs *vmcs;
125 struct {
126 int loaded;
127 u16 fs_sel, gs_sel, ldt_sel;
152d3f2f
LV		 128 int gs_ldt_reload_needed;
129 int fs_reload_needed;
d77c26fc 130 } host_state;
9c8cba37 131 struct {
7ffd92c5
AK		 132 int vm86_active;
133 u8 save_iopl;
134 struct kvm_save_segment {
135 u16 selector;
136 unsigned long base;
137 u32 limit;
138 u32 ar;
139 } tr, es, ds, fs, gs;
9c8cba37
AK		 140 struct {
141 bool pending;
142 u8 vector;
143 unsigned rip;
144 } irq;
145 } rmode;
2384d2b3 146 int vpid;
04fa4d32 147 bool emulation_required;
3b86cd99
JK		 148
149 /* Support for vnmi-less CPUs */
150 int soft_vnmi_blocked;
151 ktime_t entry_time;
152 s64 vnmi_blocked_time;
a0861c02 153 u32 exit_reason;
a2fa3e9f
GH		 154};
155
156static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
157{
fb3f0f51 158 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 159}
160
b7ebfb05 161static int init_rmode(struct kvm *kvm);
4e1096d2 162static u64 construct_eptp(unsigned long root_hpa);
75880a01 163
6aa8b732
AK		 164static DEFINE_PER_CPU(struct vmcs *, vmxarea);
165static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
543e4243 166static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
6aa8b732 167
3e7c73e9
AK		 168static unsigned long *vmx_io_bitmap_a;
169static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 170static unsigned long *vmx_msr_bitmap_legacy;
171static unsigned long *vmx_msr_bitmap_longmode;
fdef3ad1 172
2384d2b3
SY		 173static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
174static DEFINE_SPINLOCK(vmx_vpid_lock);
175
1c3d14fe 176static struct vmcs_config {
6aa8b732
AK		 177 int size;
178 int order;
179 u32 revision_id;
1c3d14fe
YS		 180 u32 pin_based_exec_ctrl;
181 u32 cpu_based_exec_ctrl;
f78e0e2e 182 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 183 u32 vmexit_ctrl;
184 u32 vmentry_ctrl;
185} vmcs_config;
6aa8b732 186
efff9e53 187static struct vmx_capability {
d56f546d
SY		 188 u32 ept;
189 u32 vpid;
190} vmx_capability;
191
6aa8b732
AK		 192#define VMX_SEGMENT_FIELD(seg) \
193 [VCPU_SREG_##seg] = { \
194 .selector = GUEST_##seg##_SELECTOR, \
195 .base = GUEST_##seg##_BASE, \
196 .limit = GUEST_##seg##_LIMIT, \
197 .ar_bytes = GUEST_##seg##_AR_BYTES, \
198 }
199
200static struct kvm_vmx_segment_field {
201 unsigned selector;
202 unsigned base;
203 unsigned limit;
204 unsigned ar_bytes;
205} kvm_vmx_segment_fields[] = {
206 VMX_SEGMENT_FIELD(CS),
207 VMX_SEGMENT_FIELD(DS),
208 VMX_SEGMENT_FIELD(ES),
209 VMX_SEGMENT_FIELD(FS),
210 VMX_SEGMENT_FIELD(GS),
211 VMX_SEGMENT_FIELD(SS),
212 VMX_SEGMENT_FIELD(TR),
213 VMX_SEGMENT_FIELD(LDTR),
214};
215
26bb0981
AK		 216static u64 host_efer;
217
6de4f3ad
AK		 218static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
219
4d56c8a7
AK		 220/*
221 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
222 * away by decrementing the array size.
223 */
6aa8b732 224static const u32 vmx_msr_index[] = {
05b3e0c2 225#ifdef CONFIG_X86_64
44ea2b17 226 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732
AK		 227#endif
228 MSR_EFER, MSR_K6_STAR,
229};
9d8f549d 230#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 231
6aa8b732
AK		 232static inline int is_page_fault(u32 intr_info)
233{
234 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
235 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 236 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 237}
238
2ab455cc
AL		 239static inline int is_no_device(u32 intr_info)
240{
241 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
242 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 243 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 244}
245
7aa81cc0
AL		 246static inline int is_invalid_opcode(u32 intr_info)
247{
248 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
249 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 250 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 251}
252
6aa8b732
AK		 253static inline int is_external_interrupt(u32 intr_info)
254{
255 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
256 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
257}
258
a0861c02
AK		 259static inline int is_machine_check(u32 intr_info)
260{
261 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
262 INTR_INFO_VALID_MASK)) ==
263 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
264}
265
25c5f225
SY		 266static inline int cpu_has_vmx_msr_bitmap(void)
267{
04547156 268 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 269}
270
6e5d865c
YS		 271static inline int cpu_has_vmx_tpr_shadow(void)
272{
04547156 273 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 274}
275
276static inline int vm_need_tpr_shadow(struct kvm *kvm)
277{
04547156 278 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 279}
280
f78e0e2e
SY		 281static inline int cpu_has_secondary_exec_ctrls(void)
282{
04547156
SY		 283 return vmcs_config.cpu_based_exec_ctrl &
284 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 285}
286
774ead3a 287static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 288{
04547156
SY		 289 return vmcs_config.cpu_based_2nd_exec_ctrl &
290 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
291}
292
293static inline bool cpu_has_vmx_flexpriority(void)
294{
295 return cpu_has_vmx_tpr_shadow() &&
296 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 297}
298
e799794e
MT		 299static inline bool cpu_has_vmx_ept_execute_only(void)
300{
301 return !!(vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT);
302}
303
304static inline bool cpu_has_vmx_eptp_uncacheable(void)
305{
306 return !!(vmx_capability.ept & VMX_EPTP_UC_BIT);
307}
308
309static inline bool cpu_has_vmx_eptp_writeback(void)
310{
311 return !!(vmx_capability.ept & VMX_EPTP_WB_BIT);
312}
313
314static inline bool cpu_has_vmx_ept_2m_page(void)
315{
316 return !!(vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT);
317}
318
d56f546d
SY		 319static inline int cpu_has_vmx_invept_individual_addr(void)
320{
04547156 321 return !!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT);
d56f546d
SY		 322}
323
324static inline int cpu_has_vmx_invept_context(void)
325{
04547156 326 return !!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT);
d56f546d
SY		 327}
328
329static inline int cpu_has_vmx_invept_global(void)
330{
04547156 331 return !!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT);
d56f546d
SY		 332}
333
334static inline int cpu_has_vmx_ept(void)
335{
04547156
SY		 336 return vmcs_config.cpu_based_2nd_exec_ctrl &
337 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 338}
339
3a624e29
NK		 340static inline int cpu_has_vmx_unrestricted_guest(void)
341{
342 return vmcs_config.cpu_based_2nd_exec_ctrl &
343 SECONDARY_EXEC_UNRESTRICTED_GUEST;
344}
345
4b8d54f9
ZE		 346static inline int cpu_has_vmx_ple(void)
347{
348 return vmcs_config.cpu_based_2nd_exec_ctrl &
349 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
350}
351
f78e0e2e
SY		 352static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
353{
04547156
SY		 354 return flexpriority_enabled &&
355 (cpu_has_vmx_virtualize_apic_accesses()) &&
356 (irqchip_in_kernel(kvm));
f78e0e2e
SY		 357}
358
2384d2b3
SY		 359static inline int cpu_has_vmx_vpid(void)
360{
04547156
SY		 361 return vmcs_config.cpu_based_2nd_exec_ctrl &
362 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 363}
364
f08864b4
SY		 365static inline int cpu_has_virtual_nmis(void)
366{
367 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
368}
369
04547156
SY		 370static inline bool report_flexpriority(void)
371{
372 return flexpriority_enabled;
373}
374
8b9cf98c 375static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 376{
377 int i;
378
a2fa3e9f 379 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 380 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 381 return i;
382 return -1;
383}
384
2384d2b3
SY		 385static inline void __invvpid(int ext, u16 vpid, gva_t gva)
386{
387 struct {
388 u64 vpid : 16;
389 u64 rsvd : 48;
390 u64 gva;
391 } operand = { vpid, 0, gva };
392
4ecac3fd 393 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 394 /* CF==1 or ZF==1 --> rc = -1 */
395 "; ja 1f ; ud2 ; 1:"
396 : : "a"(&operand), "c"(ext) : "cc", "memory");
397}
398
1439442c
SY		 399static inline void __invept(int ext, u64 eptp, gpa_t gpa)
400{
401 struct {
402 u64 eptp, gpa;
403 } operand = {eptp, gpa};
404
4ecac3fd 405 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 406 /* CF==1 or ZF==1 --> rc = -1 */
407 "; ja 1f ; ud2 ; 1:\n"
408 : : "a" (&operand), "c" (ext) : "cc", "memory");
409}
410
26bb0981 411static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 412{
413 int i;
414
8b9cf98c 415 i = __find_msr_index(vmx, msr);
a75beee6 416 if (i >= 0)
a2fa3e9f 417 return &vmx->guest_msrs[i];
8b6d44c7 418 return NULL;
7725f0ba
AK		 419}
420
6aa8b732
AK		 421static void vmcs_clear(struct vmcs *vmcs)
422{
423 u64 phys_addr = __pa(vmcs);
424 u8 error;
425
4ecac3fd 426 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
6aa8b732
AK		 427 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
428 : "cc", "memory");
429 if (error)
430 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
431 vmcs, phys_addr);
432}
433
434static void __vcpu_clear(void *arg)
435{
8b9cf98c 436 struct vcpu_vmx *vmx = arg;
d3b2c338 437 int cpu = raw_smp_processor_id();
6aa8b732 438
8b9cf98c 439 if (vmx->vcpu.cpu == cpu)
a2fa3e9f
GH		 440 vmcs_clear(vmx->vmcs);
441 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
6aa8b732 442 per_cpu(current_vmcs, cpu) = NULL;
ad312c7c 443 rdtscll(vmx->vcpu.arch.host_tsc);
543e4243
AK		 444 list_del(&vmx->local_vcpus_link);
445 vmx->vcpu.cpu = -1;
446 vmx->launched = 0;
6aa8b732
AK		 447}
448
8b9cf98c 449static void vcpu_clear(struct vcpu_vmx *vmx)
8d0be2b3 450{
eae5ecb5
AK		 451 if (vmx->vcpu.cpu == -1)
452 return;
8691e5a8 453 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
8d0be2b3
AK		 454}
455
2384d2b3
SY		 456static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
457{
458 if (vmx->vpid == 0)
459 return;
460
461 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
462}
463
1439442c
SY		 464static inline void ept_sync_global(void)
465{
466 if (cpu_has_vmx_invept_global())
467 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
468}
469
470static inline void ept_sync_context(u64 eptp)
471{
089d034e 472 if (enable_ept) {
1439442c
SY		 473 if (cpu_has_vmx_invept_context())
474 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
475 else
476 ept_sync_global();
477 }
478}
479
480static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
481{
089d034e 482 if (enable_ept) {
1439442c
SY		 483 if (cpu_has_vmx_invept_individual_addr())
484 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
485 eptp, gpa);
486 else
487 ept_sync_context(eptp);
488 }
489}
490
6aa8b732
AK		 491static unsigned long vmcs_readl(unsigned long field)
492{
493 unsigned long value;
494
4ecac3fd 495 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
6aa8b732
AK		 496 : "=a"(value) : "d"(field) : "cc");
497 return value;
498}
499
500static u16 vmcs_read16(unsigned long field)
501{
502 return vmcs_readl(field);
503}
504
505static u32 vmcs_read32(unsigned long field)
506{
507 return vmcs_readl(field);
508}
509
510static u64 vmcs_read64(unsigned long field)
511{
05b3e0c2 512#ifdef CONFIG_X86_64
6aa8b732
AK		 513 return vmcs_readl(field);
514#else
515 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
516#endif
517}
518
e52de1b8
AK		 519static noinline void vmwrite_error(unsigned long field, unsigned long value)
520{
521 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
522 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
523 dump_stack();
524}
525
6aa8b732
AK		 526static void vmcs_writel(unsigned long field, unsigned long value)
527{
528 u8 error;
529
4ecac3fd 530 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 531 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 532 if (unlikely(error))
533 vmwrite_error(field, value);
6aa8b732
AK		 534}
535
536static void vmcs_write16(unsigned long field, u16 value)
537{
538 vmcs_writel(field, value);
539}
540
541static void vmcs_write32(unsigned long field, u32 value)
542{
543 vmcs_writel(field, value);
544}
545
546static void vmcs_write64(unsigned long field, u64 value)
547{
6aa8b732 548 vmcs_writel(field, value);
7682f2d0 549#ifndef CONFIG_X86_64
6aa8b732
AK		 550 asm volatile ("");
551 vmcs_writel(field+1, value >> 32);
552#endif
553}
554
2ab455cc
AL		 555static void vmcs_clear_bits(unsigned long field, u32 mask)
556{
557 vmcs_writel(field, vmcs_readl(field) & ~mask);
558}
559
560static void vmcs_set_bits(unsigned long field, u32 mask)
561{
562 vmcs_writel(field, vmcs_readl(field) | mask);
563}
564
abd3f2d6
AK		 565static void update_exception_bitmap(struct kvm_vcpu *vcpu)
566{
567 u32 eb;
568
a0861c02 569 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR);
abd3f2d6
AK		 570 if (!vcpu->fpu_active)
571 eb |= 1u << NM_VECTOR;
e8a48342
AK		 572 /*
573 * Unconditionally intercept #DB so we can maintain dr6 without
574 * reading it every exit.
575 */
576 eb |= 1u << DB_VECTOR;
d0bfb940 577 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
d0bfb940
JK		 578 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
579 eb |= 1u << BP_VECTOR;
580 }
7ffd92c5 581 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 582 eb = ~0;
089d034e 583 if (enable_ept)
1439442c 584 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
abd3f2d6
AK		 585 vmcs_write32(EXCEPTION_BITMAP, eb);
586}
587
33ed6329
AK		 588static void reload_tss(void)
589{
33ed6329
AK		 590 /*
591 * VT restores TR but not its size. Useless.
592 */
593 struct descriptor_table gdt;
a5f61300 594 struct desc_struct *descs;
33ed6329 595
d6e88aec 596 kvm_get_gdt(&gdt);
33ed6329
AK		 597 descs = (void *)gdt.base;
598 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
599 load_TR_desc();
33ed6329
AK		 600}
601
92c0d900 602static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 603{
3a34a881 604 u64 guest_efer;
51c6cf66
AK		 605 u64 ignore_bits;
606
26bb0981 607 guest_efer = vmx->vcpu.arch.shadow_efer;
3a34a881 608
51c6cf66
AK		 609 /*
610 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
611 * outside long mode
612 */
613 ignore_bits = EFER_NX | EFER_SCE;
614#ifdef CONFIG_X86_64
615 ignore_bits |= EFER_LMA | EFER_LME;
616 /* SCE is meaningful only in long mode on Intel */
617 if (guest_efer & EFER_LMA)
618 ignore_bits &= ~(u64)EFER_SCE;
619#endif
51c6cf66
AK		 620 guest_efer &= ~ignore_bits;
621 guest_efer |= host_efer & ignore_bits;
26bb0981 622 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 623 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
26bb0981 624 return true;
51c6cf66
AK		 625}
626
04d2cc77 627static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 628{
04d2cc77 629 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 630 int i;
04d2cc77 631
a2fa3e9f 632 if (vmx->host_state.loaded)
33ed6329
AK		 633 return;
634
a2fa3e9f 635 vmx->host_state.loaded = 1;
33ed6329
AK		 636 /*
637 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
638 * allow segment selectors with cpl > 0 or ti == 1.
639 */
d6e88aec 640 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 641 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
d6e88aec 642 vmx->host_state.fs_sel = kvm_read_fs();
152d3f2f 643 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 644 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 645 vmx->host_state.fs_reload_needed = 0;
646 } else {
33ed6329 647 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 648 vmx->host_state.fs_reload_needed = 1;
33ed6329 649 }
d6e88aec 650 vmx->host_state.gs_sel = kvm_read_gs();
a2fa3e9f
GH		 651 if (!(vmx->host_state.gs_sel & 7))
652 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 653 else {
654 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 655 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 656 }
657
658#ifdef CONFIG_X86_64
659 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
660 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
661#else
a2fa3e9f
GH		 662 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
663 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 664#endif
707c0874
AK		 665
666#ifdef CONFIG_X86_64
44ea2b17
AK		 667 if (is_long_mode(&vmx->vcpu)) {
668 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
669 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
670 }
707c0874 671#endif
26bb0981
AK		 672 for (i = 0; i < vmx->save_nmsrs; ++i)
673 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 674 vmx->guest_msrs[i].data,
675 vmx->guest_msrs[i].mask);
33ed6329
AK		 676}
677
a9b21b62 678static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 679{
15ad7146 680 unsigned long flags;
33ed6329 681
a2fa3e9f 682 if (!vmx->host_state.loaded)
33ed6329
AK		 683 return;
684
e1beb1d3 685 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 686 vmx->host_state.loaded = 0;
152d3f2f 687 if (vmx->host_state.fs_reload_needed)
d6e88aec 688 kvm_load_fs(vmx->host_state.fs_sel);
152d3f2f 689 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 690 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329
AK		 691 /*
692 * If we have to reload gs, we must take care to
693 * preserve our gs base.
694 */
15ad7146 695 local_irq_save(flags);
d6e88aec 696 kvm_load_gs(vmx->host_state.gs_sel);
33ed6329
AK		 697#ifdef CONFIG_X86_64
698 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
699#endif
15ad7146 700 local_irq_restore(flags);
33ed6329 701 }
152d3f2f 702 reload_tss();
44ea2b17
AK		 703#ifdef CONFIG_X86_64
704 if (is_long_mode(&vmx->vcpu)) {
705 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
706 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
707 }
708#endif
33ed6329
AK		 709}
710
a9b21b62
AK		 711static void vmx_load_host_state(struct vcpu_vmx *vmx)
712{
713 preempt_disable();
714 __vmx_load_host_state(vmx);
715 preempt_enable();
716}
717
6aa8b732
AK		 718/*
719 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
720 * vcpu mutex is already taken.
721 */
15ad7146 722static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 723{
a2fa3e9f
GH		 724 struct vcpu_vmx *vmx = to_vmx(vcpu);
725 u64 phys_addr = __pa(vmx->vmcs);
019960ae 726 u64 tsc_this, delta, new_offset;
6aa8b732 727
a3d7f85f 728 if (vcpu->cpu != cpu) {
8b9cf98c 729 vcpu_clear(vmx);
2f599714 730 kvm_migrate_timers(vcpu);
eb5109e3 731 set_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests);
543e4243
AK		 732 local_irq_disable();
733 list_add(&vmx->local_vcpus_link,
734 &per_cpu(vcpus_on_cpu, cpu));
735 local_irq_enable();
a3d7f85f 736 }
6aa8b732 737
a2fa3e9f 738 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
6aa8b732
AK		 739 u8 error;
740
a2fa3e9f 741 per_cpu(current_vmcs, cpu) = vmx->vmcs;
4ecac3fd 742 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
6aa8b732
AK		 743 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
744 : "cc");
745 if (error)
746 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
a2fa3e9f 747 vmx->vmcs, phys_addr);
6aa8b732
AK		 748 }
749
750 if (vcpu->cpu != cpu) {
751 struct descriptor_table dt;
752 unsigned long sysenter_esp;
753
754 vcpu->cpu = cpu;
755 /*
756 * Linux uses per-cpu TSS and GDT, so set these when switching
757 * processors.
758 */
d6e88aec
AK		 759 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
760 kvm_get_gdt(&dt);
6aa8b732
AK		 761 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
762
763 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
764 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
7700270e
AK		 765
766 /*
767 * Make sure the time stamp counter is monotonous.
768 */
769 rdtscll(tsc_this);
019960ae
AK		 770 if (tsc_this < vcpu->arch.host_tsc) {
771 delta = vcpu->arch.host_tsc - tsc_this;
772 new_offset = vmcs_read64(TSC_OFFSET) + delta;
773 vmcs_write64(TSC_OFFSET, new_offset);
774 }
6aa8b732 775 }
6aa8b732
AK		 776}
777
778static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
779{
a9b21b62 780 __vmx_load_host_state(to_vmx(vcpu));
6aa8b732
AK		 781}
782
5fd86fcf
AK		 783static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
784{
785 if (vcpu->fpu_active)
786 return;
787 vcpu->fpu_active = 1;
707d92fa 788 vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
ad312c7c 789 if (vcpu->arch.cr0 & X86_CR0_TS)
707d92fa 790 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
5fd86fcf
AK		 791 update_exception_bitmap(vcpu);
792}
793
794static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
795{
796 if (!vcpu->fpu_active)
797 return;
798 vcpu->fpu_active = 0;
707d92fa 799 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
5fd86fcf
AK		 800 update_exception_bitmap(vcpu);
801}
802
6aa8b732
AK		 803static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
804{
345dcaa8
AK		 805 unsigned long rflags;
806
807 rflags = vmcs_readl(GUEST_RFLAGS);
808 if (to_vmx(vcpu)->rmode.vm86_active)
809 rflags &= ~(unsigned long)(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
810 return rflags;
6aa8b732
AK		 811}
812
813static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
814{
7ffd92c5 815 if (to_vmx(vcpu)->rmode.vm86_active)
053de044 816 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 817 vmcs_writel(GUEST_RFLAGS, rflags);
818}
819
2809f5d2
GC		 820static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
821{
822 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
823 int ret = 0;
824
825 if (interruptibility & GUEST_INTR_STATE_STI)
826 ret |= X86_SHADOW_INT_STI;
827 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
828 ret |= X86_SHADOW_INT_MOV_SS;
829
830 return ret & mask;
831}
832
833static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
834{
835 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
836 u32 interruptibility = interruptibility_old;
837
838 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
839
840 if (mask & X86_SHADOW_INT_MOV_SS)
841 interruptibility |= GUEST_INTR_STATE_MOV_SS;
842 if (mask & X86_SHADOW_INT_STI)
843 interruptibility |= GUEST_INTR_STATE_STI;
844
845 if ((interruptibility != interruptibility_old))
846 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
847}
848
6aa8b732
AK		 849static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
850{
851 unsigned long rip;
6aa8b732 852
5fdbf976 853 rip = kvm_rip_read(vcpu);
6aa8b732 854 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 855 kvm_rip_write(vcpu, rip);
6aa8b732 856
2809f5d2
GC		 857 /* skipping an emulated instruction also counts */
858 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 859}
860
298101da
AK		 861static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
862 bool has_error_code, u32 error_code)
863{
77ab6db0 864 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 865 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 866
8ab2d2e2 867 if (has_error_code) {
77ab6db0 868 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 869 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
870 }
77ab6db0 871
7ffd92c5 872 if (vmx->rmode.vm86_active) {
77ab6db0
JK		 873 vmx->rmode.irq.pending = true;
874 vmx->rmode.irq.vector = nr;
875 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
ae0bb3e0
GN		 876 if (kvm_exception_is_soft(nr))
877 vmx->rmode.irq.rip +=
878 vmx->vcpu.arch.event_exit_inst_len;
8ab2d2e2
JK		 879 intr_info |= INTR_TYPE_SOFT_INTR;
880 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
77ab6db0
JK		 881 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
882 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
883 return;
884 }
885
66fd3f7f
GN		 886 if (kvm_exception_is_soft(nr)) {
887 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
888 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 889 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
890 } else
891 intr_info |= INTR_TYPE_HARD_EXCEPTION;
892
893 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 894}
895
a75beee6
ED		 896/*
897 * Swap MSR entry in host/guest MSR entry array.
898 */
8b9cf98c 899static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 900{
26bb0981 901 struct shared_msr_entry tmp;
a2fa3e9f
GH		 902
903 tmp = vmx->guest_msrs[to];
904 vmx->guest_msrs[to] = vmx->guest_msrs[from];
905 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 906}
907
e38aea3e
AK		 908/*
909 * Set up the vmcs to automatically save and restore system
910 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
911 * mode, as fiddling with msrs is very expensive.
912 */
8b9cf98c 913static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 914{
26bb0981 915 int save_nmsrs, index;
5897297b 916 unsigned long *msr_bitmap;
e38aea3e 917
33f9c505 918 vmx_load_host_state(vmx);
a75beee6
ED		 919 save_nmsrs = 0;
920#ifdef CONFIG_X86_64
8b9cf98c 921 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 922 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 923 if (index >= 0)
8b9cf98c
RR		 924 move_msr_up(vmx, index, save_nmsrs++);
925 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 926 if (index >= 0)
8b9cf98c
RR		 927 move_msr_up(vmx, index, save_nmsrs++);
928 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 929 if (index >= 0)
8b9cf98c 930 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 931 /*
932 * MSR_K6_STAR is only needed on long mode guests, and only
933 * if efer.sce is enabled.
934 */
8b9cf98c 935 index = __find_msr_index(vmx, MSR_K6_STAR);
ad312c7c 936 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
8b9cf98c 937 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 938 }
939#endif
92c0d900
AK		 940 index = __find_msr_index(vmx, MSR_EFER);
941 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 942 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 943
26bb0981 944 vmx->save_nmsrs = save_nmsrs;
5897297b
AK		 945
946 if (cpu_has_vmx_msr_bitmap()) {
947 if (is_long_mode(&vmx->vcpu))
948 msr_bitmap = vmx_msr_bitmap_longmode;
949 else
950 msr_bitmap = vmx_msr_bitmap_legacy;
951
952 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
953 }
e38aea3e
AK		 954}
955
6aa8b732
AK		 956/*
957 * reads and returns guest's timestamp counter "register"
958 * guest_tsc = host_tsc + tsc_offset -- 21.3
959 */
960static u64 guest_read_tsc(void)
961{
962 u64 host_tsc, tsc_offset;
963
964 rdtscll(host_tsc);
965 tsc_offset = vmcs_read64(TSC_OFFSET);
966 return host_tsc + tsc_offset;
967}
968
969/*
970 * writes 'guest_tsc' into guest's timestamp counter "register"
971 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
972 */
53f658b3 973static void guest_write_tsc(u64 guest_tsc, u64 host_tsc)
6aa8b732 974{
6aa8b732
AK		 975 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
976}
977
6aa8b732
AK		 978/*
979 * Reads an msr value (of 'msr_index') into 'pdata'.
980 * Returns 0 on success, non-0 otherwise.
981 * Assumes vcpu_load() was already called.
982 */
983static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
984{
985 u64 data;
26bb0981 986 struct shared_msr_entry *msr;
6aa8b732
AK		 987
988 if (!pdata) {
989 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
990 return -EINVAL;
991 }
992
993 switch (msr_index) {
05b3e0c2 994#ifdef CONFIG_X86_64
6aa8b732
AK		 995 case MSR_FS_BASE:
996 data = vmcs_readl(GUEST_FS_BASE);
997 break;
998 case MSR_GS_BASE:
999 data = vmcs_readl(GUEST_GS_BASE);
1000 break;
44ea2b17
AK		 1001 case MSR_KERNEL_GS_BASE:
1002 vmx_load_host_state(to_vmx(vcpu));
1003 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1004 break;
26bb0981 1005#endif
6aa8b732 1006 case MSR_EFER:
3bab1f5d 1007 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 1008 case MSR_IA32_TSC:
6aa8b732
AK		 1009 data = guest_read_tsc();
1010 break;
1011 case MSR_IA32_SYSENTER_CS:
1012 data = vmcs_read32(GUEST_SYSENTER_CS);
1013 break;
1014 case MSR_IA32_SYSENTER_EIP:
f5b42c33 1015 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 1016 break;
1017 case MSR_IA32_SYSENTER_ESP:
f5b42c33 1018 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 1019 break;
6aa8b732 1020 default:
26bb0981 1021 vmx_load_host_state(to_vmx(vcpu));
8b9cf98c 1022 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d 1023 if (msr) {
542423b0 1024 vmx_load_host_state(to_vmx(vcpu));
3bab1f5d
AK		 1025 data = msr->data;
1026 break;
6aa8b732 1027 }
3bab1f5d 1028 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 1029 }
1030
1031 *pdata = data;
1032 return 0;
1033}
1034
1035/*
1036 * Writes msr value into into the appropriate "register".
1037 * Returns 0 on success, non-0 otherwise.
1038 * Assumes vcpu_load() was already called.
1039 */
1040static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1041{
a2fa3e9f 1042 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1043 struct shared_msr_entry *msr;
53f658b3 1044 u64 host_tsc;
2cc51560
ED		 1045 int ret = 0;
1046
6aa8b732 1047 switch (msr_index) {
3bab1f5d 1048 case MSR_EFER:
a9b21b62 1049 vmx_load_host_state(vmx);
2cc51560 1050 ret = kvm_set_msr_common(vcpu, msr_index, data);
2cc51560 1051 break;
16175a79 1052#ifdef CONFIG_X86_64
6aa8b732
AK		 1053 case MSR_FS_BASE:
1054 vmcs_writel(GUEST_FS_BASE, data);
1055 break;
1056 case MSR_GS_BASE:
1057 vmcs_writel(GUEST_GS_BASE, data);
1058 break;
44ea2b17
AK		 1059 case MSR_KERNEL_GS_BASE:
1060 vmx_load_host_state(vmx);
1061 vmx->msr_guest_kernel_gs_base = data;
1062 break;
6aa8b732
AK		 1063#endif
1064 case MSR_IA32_SYSENTER_CS:
1065 vmcs_write32(GUEST_SYSENTER_CS, data);
1066 break;
1067 case MSR_IA32_SYSENTER_EIP:
f5b42c33 1068 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 1069 break;
1070 case MSR_IA32_SYSENTER_ESP:
f5b42c33 1071 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 1072 break;
af24a4e4 1073 case MSR_IA32_TSC:
53f658b3
MT		 1074 rdtscll(host_tsc);
1075 guest_write_tsc(data, host_tsc);
6aa8b732 1076 break;
468d472f
SY		 1077 case MSR_IA32_CR_PAT:
1078 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1079 vmcs_write64(GUEST_IA32_PAT, data);
1080 vcpu->arch.pat = data;
1081 break;
1082 }
1083 /* Otherwise falls through to kvm_set_msr_common */
6aa8b732 1084 default:
8b9cf98c 1085 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 1086 if (msr) {
542423b0 1087 vmx_load_host_state(vmx);
3bab1f5d
AK		 1088 msr->data = data;
1089 break;
6aa8b732 1090 }
2cc51560 1091 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 1092 }
1093
2cc51560 1094 return ret;
6aa8b732
AK		 1095}
1096
5fdbf976 1097static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 1098{
5fdbf976
MT		 1099 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1100 switch (reg) {
1101 case VCPU_REGS_RSP:
1102 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1103 break;
1104 case VCPU_REGS_RIP:
1105 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1106 break;
6de4f3ad
AK		 1107 case VCPU_EXREG_PDPTR:
1108 if (enable_ept)
1109 ept_save_pdptrs(vcpu);
1110 break;
5fdbf976
MT		 1111 default:
1112 break;
1113 }
6aa8b732
AK		 1114}
1115
355be0b9 1116static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
6aa8b732 1117{
ae675ef0
JK		 1118 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1119 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1120 else
1121 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1122
abd3f2d6 1123 update_exception_bitmap(vcpu);
6aa8b732
AK		 1124}
1125
1126static __init int cpu_has_kvm_support(void)
1127{
6210e37b 1128 return cpu_has_vmx();
6aa8b732
AK		 1129}
1130
1131static __init int vmx_disabled_by_bios(void)
1132{
1133 u64 msr;
1134
1135 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
9ea542fa
SY		 1136 return (msr & (FEATURE_CONTROL_LOCKED |
1137 FEATURE_CONTROL_VMXON_ENABLED))
1138 == FEATURE_CONTROL_LOCKED;
62b3ffb8 1139 /* locked but not enabled */
6aa8b732
AK		 1140}
1141
10474ae8 1142static int hardware_enable(void *garbage)
6aa8b732
AK		 1143{
1144 int cpu = raw_smp_processor_id();
1145 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1146 u64 old;
1147
10474ae8
AG		 1148 if (read_cr4() & X86_CR4_VMXE)
1149 return -EBUSY;
1150
543e4243 1151 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
6aa8b732 1152 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
9ea542fa
SY		 1153 if ((old & (FEATURE_CONTROL_LOCKED |
1154 FEATURE_CONTROL_VMXON_ENABLED))
1155 != (FEATURE_CONTROL_LOCKED |
1156 FEATURE_CONTROL_VMXON_ENABLED))
6aa8b732 1157 /* enable and lock */
62b3ffb8 1158 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
9ea542fa
SY		 1159 FEATURE_CONTROL_LOCKED |
1160 FEATURE_CONTROL_VMXON_ENABLED);
66aee91a 1161 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
4ecac3fd
AK		 1162 asm volatile (ASM_VMX_VMXON_RAX
1163 : : "a"(&phys_addr), "m"(phys_addr)
6aa8b732 1164 : "memory", "cc");
10474ae8
AG		 1165
1166 ept_sync_global();
1167
1168 return 0;
6aa8b732
AK		 1169}
1170
543e4243
AK		 1171static void vmclear_local_vcpus(void)
1172{
1173 int cpu = raw_smp_processor_id();
1174 struct vcpu_vmx *vmx, *n;
1175
1176 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1177 local_vcpus_link)
1178 __vcpu_clear(vmx);
1179}
1180
710ff4a8
EH		 1181
1182/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1183 * tricks.
1184 */
1185static void kvm_cpu_vmxoff(void)
6aa8b732 1186{
4ecac3fd 1187 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
e693d71b 1188 write_cr4(read_cr4() & ~X86_CR4_VMXE);
6aa8b732
AK		 1189}
1190
710ff4a8
EH		 1191static void hardware_disable(void *garbage)
1192{
1193 vmclear_local_vcpus();
1194 kvm_cpu_vmxoff();
1195}
1196
1c3d14fe 1197static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 1198 u32 msr, u32 *result)
1c3d14fe
YS		 1199{
1200 u32 vmx_msr_low, vmx_msr_high;
1201 u32 ctl = ctl_min | ctl_opt;
1202
1203 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1204
1205 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1206 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1207
1208 /* Ensure minimum (required) set of control bits are supported. */
1209 if (ctl_min & ~ctl)
002c7f7c 1210 return -EIO;
1c3d14fe
YS		 1211
1212 *result = ctl;
1213 return 0;
1214}
1215
002c7f7c 1216static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 1217{
1218 u32 vmx_msr_low, vmx_msr_high;
d56f546d 1219 u32 min, opt, min2, opt2;
1c3d14fe
YS		 1220 u32 _pin_based_exec_control = 0;
1221 u32 _cpu_based_exec_control = 0;
f78e0e2e 1222 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 1223 u32 _vmexit_control = 0;
1224 u32 _vmentry_control = 0;
1225
1226 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
f08864b4 1227 opt = PIN_BASED_VIRTUAL_NMIS;
1c3d14fe
YS		 1228 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1229 &_pin_based_exec_control) < 0)
002c7f7c 1230 return -EIO;
1c3d14fe
YS		 1231
1232 min = CPU_BASED_HLT_EXITING |
1233#ifdef CONFIG_X86_64
1234 CPU_BASED_CR8_LOAD_EXITING |
1235 CPU_BASED_CR8_STORE_EXITING |
1236#endif
d56f546d
SY		 1237 CPU_BASED_CR3_LOAD_EXITING |
1238 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 1239 CPU_BASED_USE_IO_BITMAPS |
1240 CPU_BASED_MOV_DR_EXITING |
a7052897 1241 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 1242 CPU_BASED_MWAIT_EXITING |
1243 CPU_BASED_MONITOR_EXITING |
a7052897 1244 CPU_BASED_INVLPG_EXITING;
f78e0e2e 1245 opt = CPU_BASED_TPR_SHADOW |
25c5f225 1246 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 1247 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 1248 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1249 &_cpu_based_exec_control) < 0)
002c7f7c 1250 return -EIO;
6e5d865c
YS		 1251#ifdef CONFIG_X86_64
1252 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1253 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1254 ~CPU_BASED_CR8_STORE_EXITING;
1255#endif
f78e0e2e 1256 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 1257 min2 = 0;
1258 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2384d2b3 1259 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 1260 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 1261 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9
ZE		 1262 SECONDARY_EXEC_UNRESTRICTED_GUEST |
1263 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
d56f546d
SY		 1264 if (adjust_vmx_controls(min2, opt2,
1265 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 1266 &_cpu_based_2nd_exec_control) < 0)
1267 return -EIO;
1268 }
1269#ifndef CONFIG_X86_64
1270 if (!(_cpu_based_2nd_exec_control &
1271 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1272 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1273#endif
d56f546d 1274 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 1275 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1276 enabled */
5fff7d27
GN		 1277 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1278 CPU_BASED_CR3_STORE_EXITING |
1279 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 1280 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1281 vmx_capability.ept, vmx_capability.vpid);
1282 }
1c3d14fe
YS		 1283
1284 min = 0;
1285#ifdef CONFIG_X86_64
1286 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1287#endif
468d472f 1288 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1c3d14fe
YS		 1289 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1290 &_vmexit_control) < 0)
002c7f7c 1291 return -EIO;
1c3d14fe 1292
468d472f
SY		 1293 min = 0;
1294 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 1295 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1296 &_vmentry_control) < 0)
002c7f7c 1297 return -EIO;
6aa8b732 1298
c68876fd 1299 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 1300
1301 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1302 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 1303 return -EIO;
1c3d14fe
YS		 1304
1305#ifdef CONFIG_X86_64
1306 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1307 if (vmx_msr_high & (1u<<16))
002c7f7c 1308 return -EIO;
1c3d14fe
YS		 1309#endif
1310
1311 /* Require Write-Back (WB) memory type for VMCS accesses. */
1312 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 1313 return -EIO;
1c3d14fe 1314
002c7f7c
YS		 1315 vmcs_conf->size = vmx_msr_high & 0x1fff;
1316 vmcs_conf->order = get_order(vmcs_config.size);
1317 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 1318
002c7f7c
YS		 1319 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1320 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 1321 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 1322 vmcs_conf->vmexit_ctrl = _vmexit_control;
1323 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe
YS		 1324
1325 return 0;
c68876fd 1326}
6aa8b732
AK		 1327
1328static struct vmcs *alloc_vmcs_cpu(int cpu)
1329{
1330 int node = cpu_to_node(cpu);
1331 struct page *pages;
1332 struct vmcs *vmcs;
1333
6484eb3e 1334 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 1335 if (!pages)
1336 return NULL;
1337 vmcs = page_address(pages);
1c3d14fe
YS		 1338 memset(vmcs, 0, vmcs_config.size);
1339 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 1340 return vmcs;
1341}
1342
1343static struct vmcs *alloc_vmcs(void)
1344{
d3b2c338 1345 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 1346}
1347
1348static void free_vmcs(struct vmcs *vmcs)
1349{
1c3d14fe 1350 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 1351}
1352
39959588 1353static void free_kvm_area(void)
6aa8b732
AK		 1354{
1355 int cpu;
1356
3230bb47 1357 for_each_possible_cpu(cpu) {
6aa8b732 1358 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 1359 per_cpu(vmxarea, cpu) = NULL;
1360 }
6aa8b732
AK		 1361}
1362
6aa8b732
AK		 1363static __init int alloc_kvm_area(void)
1364{
1365 int cpu;
1366
3230bb47 1367 for_each_possible_cpu(cpu) {
6aa8b732
AK		 1368 struct vmcs *vmcs;
1369
1370 vmcs = alloc_vmcs_cpu(cpu);
1371 if (!vmcs) {
1372 free_kvm_area();
1373 return -ENOMEM;
1374 }
1375
1376 per_cpu(vmxarea, cpu) = vmcs;
1377 }
1378 return 0;
1379}
1380
1381static __init int hardware_setup(void)
1382{
002c7f7c
YS		 1383 if (setup_vmcs_config(&vmcs_config) < 0)
1384 return -EIO;
50a37eb4
JR		 1385
1386 if (boot_cpu_has(X86_FEATURE_NX))
1387 kvm_enable_efer_bits(EFER_NX);
1388
93ba03c2
SY		 1389 if (!cpu_has_vmx_vpid())
1390 enable_vpid = 0;
1391
3a624e29 1392 if (!cpu_has_vmx_ept()) {
93ba03c2 1393 enable_ept = 0;
3a624e29
NK		 1394 enable_unrestricted_guest = 0;
1395 }
1396
1397 if (!cpu_has_vmx_unrestricted_guest())
1398 enable_unrestricted_guest = 0;
93ba03c2
SY		 1399
1400 if (!cpu_has_vmx_flexpriority())
1401 flexpriority_enabled = 0;
1402
95ba8273
GN		 1403 if (!cpu_has_vmx_tpr_shadow())
1404 kvm_x86_ops->update_cr8_intercept = NULL;
1405
54dee993
MT		 1406 if (enable_ept && !cpu_has_vmx_ept_2m_page())
1407 kvm_disable_largepages();
1408
4b8d54f9
ZE		 1409 if (!cpu_has_vmx_ple())
1410 ple_gap = 0;
1411
6aa8b732
AK		 1412 return alloc_kvm_area();
1413}
1414
1415static __exit void hardware_unsetup(void)
1416{
1417 free_kvm_area();
1418}
1419
6aa8b732
AK		 1420static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1421{
1422 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1423
6af11b9e 1424 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 1425 vmcs_write16(sf->selector, save->selector);
1426 vmcs_writel(sf->base, save->base);
1427 vmcs_write32(sf->limit, save->limit);
1428 vmcs_write32(sf->ar_bytes, save->ar);
1429 } else {
1430 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1431 << AR_DPL_SHIFT;
1432 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1433 }
1434}
1435
1436static void enter_pmode(struct kvm_vcpu *vcpu)
1437{
1438 unsigned long flags;
a89a8fb9 1439 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1440
a89a8fb9 1441 vmx->emulation_required = 1;
7ffd92c5 1442 vmx->rmode.vm86_active = 0;
6aa8b732 1443
7ffd92c5
AK		 1444 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1445 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1446 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
6aa8b732
AK		 1447
1448 flags = vmcs_readl(GUEST_RFLAGS);
053de044 1449 flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
7ffd92c5 1450 flags |= (vmx->rmode.save_iopl << IOPL_SHIFT);
6aa8b732
AK		 1451 vmcs_writel(GUEST_RFLAGS, flags);
1452
66aee91a
RR		 1453 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1454 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 1455
1456 update_exception_bitmap(vcpu);
1457
a89a8fb9
MG		 1458 if (emulate_invalid_guest_state)
1459 return;
1460
7ffd92c5
AK		 1461 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1462 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1463 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1464 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
6aa8b732
AK		 1465
1466 vmcs_write16(GUEST_SS_SELECTOR, 0);
1467 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1468
1469 vmcs_write16(GUEST_CS_SELECTOR,
1470 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1471 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1472}
1473
d77c26fc 1474static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 1475{
bfc6d222 1476 if (!kvm->arch.tss_addr) {
cbc94022
IE		 1477 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1478 kvm->memslots[0].npages - 3;
1479 return base_gfn << PAGE_SHIFT;
1480 }
bfc6d222 1481 return kvm->arch.tss_addr;
6aa8b732
AK		 1482}
1483
1484static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1485{
1486 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1487
1488 save->selector = vmcs_read16(sf->selector);
1489 save->base = vmcs_readl(sf->base);
1490 save->limit = vmcs_read32(sf->limit);
1491 save->ar = vmcs_read32(sf->ar_bytes);
15b00f32
JK		 1492 vmcs_write16(sf->selector, save->base >> 4);
1493 vmcs_write32(sf->base, save->base & 0xfffff);
6aa8b732
AK		 1494 vmcs_write32(sf->limit, 0xffff);
1495 vmcs_write32(sf->ar_bytes, 0xf3);
1496}
1497
1498static void enter_rmode(struct kvm_vcpu *vcpu)
1499{
1500 unsigned long flags;
a89a8fb9 1501 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1502
3a624e29
NK		 1503 if (enable_unrestricted_guest)
1504 return;
1505
a89a8fb9 1506 vmx->emulation_required = 1;
7ffd92c5 1507 vmx->rmode.vm86_active = 1;
6aa8b732 1508
7ffd92c5 1509 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
6aa8b732
AK		 1510 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1511
7ffd92c5 1512 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
6aa8b732
AK		 1513 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1514
7ffd92c5 1515 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
6aa8b732
AK		 1516 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1517
1518 flags = vmcs_readl(GUEST_RFLAGS);
7ffd92c5 1519 vmx->rmode.save_iopl
ad312c7c 1520 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
6aa8b732 1521
053de044 1522 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 1523
1524 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 1525 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 1526 update_exception_bitmap(vcpu);
1527
a89a8fb9
MG		 1528 if (emulate_invalid_guest_state)
1529 goto continue_rmode;
1530
6aa8b732
AK		 1531 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1532 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1533 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1534
1535 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 1536 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
8cb5b033
AK		 1537 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1538 vmcs_writel(GUEST_CS_BASE, 0xf0000);
6aa8b732
AK		 1539 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1540
7ffd92c5
AK		 1541 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1542 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1543 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1544 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
75880a01 1545
a89a8fb9 1546continue_rmode:
8668a3c4 1547 kvm_mmu_reset_context(vcpu);
b7ebfb05 1548 init_rmode(vcpu->kvm);
6aa8b732
AK		 1549}
1550
401d10de
AS		 1551static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1552{
1553 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 1554 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1555
1556 if (!msr)
1557 return;
401d10de 1558
44ea2b17
AK		 1559 /*
1560 * Force kernel_gs_base reloading before EFER changes, as control
1561 * of this msr depends on is_long_mode().
1562 */
1563 vmx_load_host_state(to_vmx(vcpu));
401d10de
AS		 1564 vcpu->arch.shadow_efer = efer;
1565 if (!msr)
1566 return;
1567 if (efer & EFER_LMA) {
1568 vmcs_write32(VM_ENTRY_CONTROLS,
1569 vmcs_read32(VM_ENTRY_CONTROLS) |
1570 VM_ENTRY_IA32E_MODE);
1571 msr->data = efer;
1572 } else {
1573 vmcs_write32(VM_ENTRY_CONTROLS,
1574 vmcs_read32(VM_ENTRY_CONTROLS) &
1575 ~VM_ENTRY_IA32E_MODE);
1576
1577 msr->data = efer & ~EFER_LME;
1578 }
1579 setup_msrs(vmx);
1580}
1581
05b3e0c2 1582#ifdef CONFIG_X86_64
6aa8b732
AK		 1583
1584static void enter_lmode(struct kvm_vcpu *vcpu)
1585{
1586 u32 guest_tr_ar;
1587
1588 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1589 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1590 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
b8688d51 1591 __func__);
6aa8b732
AK		 1592 vmcs_write32(GUEST_TR_AR_BYTES,
1593 (guest_tr_ar & ~AR_TYPE_MASK)
1594 | AR_TYPE_BUSY_64_TSS);
1595 }
ad312c7c 1596 vcpu->arch.shadow_efer |= EFER_LMA;
401d10de 1597 vmx_set_efer(vcpu, vcpu->arch.shadow_efer);
6aa8b732
AK		 1598}
1599
1600static void exit_lmode(struct kvm_vcpu *vcpu)
1601{
ad312c7c 1602 vcpu->arch.shadow_efer &= ~EFER_LMA;
6aa8b732
AK		 1603
1604 vmcs_write32(VM_ENTRY_CONTROLS,
1605 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 1606 & ~VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1607}
1608
1609#endif
1610
2384d2b3
SY		 1611static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1612{
1613 vpid_sync_vcpu_all(to_vmx(vcpu));
089d034e 1614 if (enable_ept)
4e1096d2 1615 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
2384d2b3
SY		 1616}
1617
25c4c276 1618static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 1619{
fc78f519
AK		 1620 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
1621
1622 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
1623 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 1624}
1625
1439442c
SY		 1626static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1627{
6de4f3ad
AK		 1628 if (!test_bit(VCPU_EXREG_PDPTR,
1629 (unsigned long *)&vcpu->arch.regs_dirty))
1630 return;
1631
1439442c 1632 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1439442c
SY		 1633 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1634 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1635 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1636 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1637 }
1638}
1639
8f5d549f
AK		 1640static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1641{
1642 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1643 vcpu->arch.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1644 vcpu->arch.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1645 vcpu->arch.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1646 vcpu->arch.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
1647 }
6de4f3ad
AK		 1648
1649 __set_bit(VCPU_EXREG_PDPTR,
1650 (unsigned long *)&vcpu->arch.regs_avail);
1651 __set_bit(VCPU_EXREG_PDPTR,
1652 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 1653}
1654
1439442c
SY		 1655static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1656
1657static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1658 unsigned long cr0,
1659 struct kvm_vcpu *vcpu)
1660{
1661 if (!(cr0 & X86_CR0_PG)) {
1662 /* From paging/starting to nonpaging */
1663 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1664 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 1665 (CPU_BASED_CR3_LOAD_EXITING |
1666 CPU_BASED_CR3_STORE_EXITING));
1667 vcpu->arch.cr0 = cr0;
fc78f519 1668 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 1669 } else if (!is_paging(vcpu)) {
1670 /* From nonpaging to paging */
1671 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1672 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 1673 ~(CPU_BASED_CR3_LOAD_EXITING |
1674 CPU_BASED_CR3_STORE_EXITING));
1675 vcpu->arch.cr0 = cr0;
fc78f519 1676 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 1677 }
95eb84a7
SY		 1678
1679 if (!(cr0 & X86_CR0_WP))
1680 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 1681}
1682
1683static void ept_update_paging_mode_cr4(unsigned long *hw_cr4,
1684 struct kvm_vcpu *vcpu)
1685{
1686 if (!is_paging(vcpu)) {
1687 *hw_cr4 &= ~X86_CR4_PAE;
1688 *hw_cr4 |= X86_CR4_PSE;
1689 } else if (!(vcpu->arch.cr4 & X86_CR4_PAE))
1690 *hw_cr4 &= ~X86_CR4_PAE;
1691}
1692
6aa8b732
AK		 1693static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1694{
7ffd92c5 1695 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 1696 unsigned long hw_cr0;
1697
1698 if (enable_unrestricted_guest)
1699 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1700 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1701 else
1702 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1439442c 1703
5fd86fcf
AK		 1704 vmx_fpu_deactivate(vcpu);
1705
7ffd92c5 1706 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 1707 enter_pmode(vcpu);
1708
7ffd92c5 1709 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 1710 enter_rmode(vcpu);
1711
05b3e0c2 1712#ifdef CONFIG_X86_64
ad312c7c 1713 if (vcpu->arch.shadow_efer & EFER_LME) {
707d92fa 1714 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 1715 enter_lmode(vcpu);
707d92fa 1716 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 1717 exit_lmode(vcpu);
1718 }
1719#endif
1720
089d034e 1721 if (enable_ept)
1439442c
SY		 1722 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1723
6aa8b732 1724 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 1725 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 1726 vcpu->arch.cr0 = cr0;
5fd86fcf 1727
707d92fa 1728 if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
5fd86fcf 1729 vmx_fpu_activate(vcpu);
6aa8b732
AK		 1730}
1731
1439442c
SY		 1732static u64 construct_eptp(unsigned long root_hpa)
1733{
1734 u64 eptp;
1735
1736 /* TODO write the value reading from MSR */
1737 eptp = VMX_EPT_DEFAULT_MT |
1738 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1739 eptp |= (root_hpa & PAGE_MASK);
1740
1741 return eptp;
1742}
1743
6aa8b732
AK		 1744static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1745{
1439442c
SY		 1746 unsigned long guest_cr3;
1747 u64 eptp;
1748
1749 guest_cr3 = cr3;
089d034e 1750 if (enable_ept) {
1439442c
SY		 1751 eptp = construct_eptp(cr3);
1752 vmcs_write64(EPT_POINTER, eptp);
1439442c 1753 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
b927a3ce 1754 vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 1755 ept_load_pdptrs(vcpu);
1439442c
SY		 1756 }
1757
2384d2b3 1758 vmx_flush_tlb(vcpu);
1439442c 1759 vmcs_writel(GUEST_CR3, guest_cr3);
ad312c7c 1760 if (vcpu->arch.cr0 & X86_CR0_PE)
5fd86fcf 1761 vmx_fpu_deactivate(vcpu);
6aa8b732
AK		 1762}
1763
1764static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1765{
7ffd92c5 1766 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 1767 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1768
ad312c7c 1769 vcpu->arch.cr4 = cr4;
089d034e 1770 if (enable_ept)
1439442c
SY		 1771 ept_update_paging_mode_cr4(&hw_cr4, vcpu);
1772
1773 vmcs_writel(CR4_READ_SHADOW, cr4);
1774 vmcs_writel(GUEST_CR4, hw_cr4);
6aa8b732
AK		 1775}
1776
6aa8b732
AK		 1777static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1778{
1779 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1780
1781 return vmcs_readl(sf->base);
1782}
1783
1784static void vmx_get_segment(struct kvm_vcpu *vcpu,
1785 struct kvm_segment *var, int seg)
1786{
1787 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1788 u32 ar;
1789
1790 var->base = vmcs_readl(sf->base);
1791 var->limit = vmcs_read32(sf->limit);
1792 var->selector = vmcs_read16(sf->selector);
1793 ar = vmcs_read32(sf->ar_bytes);
9fd4a3b7 1794 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
6aa8b732
AK		 1795 ar = 0;
1796 var->type = ar & 15;
1797 var->s = (ar >> 4) & 1;
1798 var->dpl = (ar >> 5) & 3;
1799 var->present = (ar >> 7) & 1;
1800 var->avl = (ar >> 12) & 1;
1801 var->l = (ar >> 13) & 1;
1802 var->db = (ar >> 14) & 1;
1803 var->g = (ar >> 15) & 1;
1804 var->unusable = (ar >> 16) & 1;
1805}
1806
2e4d2653
IE		 1807static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1808{
2e4d2653
IE		 1809 if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */
1810 return 0;
1811
1812 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1813 return 3;
1814
eab4b8aa 1815 return vmcs_read16(GUEST_CS_SELECTOR) & 3;
2e4d2653
IE		 1816}
1817
653e3108 1818static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 1819{
6aa8b732
AK		 1820 u32 ar;
1821
653e3108 1822 if (var->unusable)
6aa8b732
AK		 1823 ar = 1 << 16;
1824 else {
1825 ar = var->type & 15;
1826 ar |= (var->s & 1) << 4;
1827 ar |= (var->dpl & 3) << 5;
1828 ar |= (var->present & 1) << 7;
1829 ar |= (var->avl & 1) << 12;
1830 ar |= (var->l & 1) << 13;
1831 ar |= (var->db & 1) << 14;
1832 ar |= (var->g & 1) << 15;
1833 }
f7fbf1fd
UL		 1834 if (ar == 0) /* a 0 value means unusable */
1835 ar = AR_UNUSABLE_MASK;
653e3108
AK		 1836
1837 return ar;
1838}
1839
1840static void vmx_set_segment(struct kvm_vcpu *vcpu,
1841 struct kvm_segment *var, int seg)
1842{
7ffd92c5 1843 struct vcpu_vmx *vmx = to_vmx(vcpu);
653e3108
AK		 1844 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1845 u32 ar;
1846
7ffd92c5
AK		 1847 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
1848 vmx->rmode.tr.selector = var->selector;
1849 vmx->rmode.tr.base = var->base;
1850 vmx->rmode.tr.limit = var->limit;
1851 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
653e3108
AK		 1852 return;
1853 }
1854 vmcs_writel(sf->base, var->base);
1855 vmcs_write32(sf->limit, var->limit);
1856 vmcs_write16(sf->selector, var->selector);
7ffd92c5 1857 if (vmx->rmode.vm86_active && var->s) {
653e3108
AK		 1858 /*
1859 * Hack real-mode segments into vm86 compatibility.
1860 */
1861 if (var->base == 0xffff0000 && var->selector == 0xf000)
1862 vmcs_writel(sf->base, 0xf0000);
1863 ar = 0xf3;
1864 } else
1865 ar = vmx_segment_access_rights(var);
3a624e29
NK		 1866
1867 /*
1868 * Fix the "Accessed" bit in AR field of segment registers for older
1869 * qemu binaries.
1870 * IA32 arch specifies that at the time of processor reset the
1871 * "Accessed" bit in the AR field of segment registers is 1. And qemu
1872 * is setting it to 0 in the usedland code. This causes invalid guest
1873 * state vmexit when "unrestricted guest" mode is turned on.
1874 * Fix for this setup issue in cpu_reset is being pushed in the qemu
1875 * tree. Newer qemu binaries with that qemu fix would not need this
1876 * kvm hack.
1877 */
1878 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
1879 ar |= 0x1; /* Accessed */
1880
6aa8b732
AK		 1881 vmcs_write32(sf->ar_bytes, ar);
1882}
1883
6aa8b732
AK		 1884static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1885{
1886 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1887
1888 *db = (ar >> 14) & 1;
1889 *l = (ar >> 13) & 1;
1890}
1891
1892static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1893{
1894 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1895 dt->base = vmcs_readl(GUEST_IDTR_BASE);
1896}
1897
1898static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1899{
1900 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1901 vmcs_writel(GUEST_IDTR_BASE, dt->base);
1902}
1903
1904static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1905{
1906 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1907 dt->base = vmcs_readl(GUEST_GDTR_BASE);
1908}
1909
1910static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1911{
1912 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1913 vmcs_writel(GUEST_GDTR_BASE, dt->base);
1914}
1915
648dfaa7
MG		 1916static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
1917{
1918 struct kvm_segment var;
1919 u32 ar;
1920
1921 vmx_get_segment(vcpu, &var, seg);
1922 ar = vmx_segment_access_rights(&var);
1923
1924 if (var.base != (var.selector << 4))
1925 return false;
1926 if (var.limit != 0xffff)
1927 return false;
1928 if (ar != 0xf3)
1929 return false;
1930
1931 return true;
1932}
1933
1934static bool code_segment_valid(struct kvm_vcpu *vcpu)
1935{
1936 struct kvm_segment cs;
1937 unsigned int cs_rpl;
1938
1939 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1940 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
1941
1872a3f4
AK		 1942 if (cs.unusable)
1943 return false;
648dfaa7
MG		 1944 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
1945 return false;
1946 if (!cs.s)
1947 return false;
1872a3f4 1948 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 1949 if (cs.dpl > cs_rpl)
1950 return false;
1872a3f4 1951 } else {
648dfaa7
MG		 1952 if (cs.dpl != cs_rpl)
1953 return false;
1954 }
1955 if (!cs.present)
1956 return false;
1957
1958 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
1959 return true;
1960}
1961
1962static bool stack_segment_valid(struct kvm_vcpu *vcpu)
1963{
1964 struct kvm_segment ss;
1965 unsigned int ss_rpl;
1966
1967 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1968 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
1969
1872a3f4
AK		 1970 if (ss.unusable)
1971 return true;
1972 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 1973 return false;
1974 if (!ss.s)
1975 return false;
1976 if (ss.dpl != ss_rpl) /* DPL != RPL */
1977 return false;
1978 if (!ss.present)
1979 return false;
1980
1981 return true;
1982}
1983
1984static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
1985{
1986 struct kvm_segment var;
1987 unsigned int rpl;
1988
1989 vmx_get_segment(vcpu, &var, seg);
1990 rpl = var.selector & SELECTOR_RPL_MASK;
1991
1872a3f4
AK		 1992 if (var.unusable)
1993 return true;
648dfaa7
MG		 1994 if (!var.s)
1995 return false;
1996 if (!var.present)
1997 return false;
1998 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
1999 if (var.dpl < rpl) /* DPL < RPL */
2000 return false;
2001 }
2002
2003 /* TODO: Add other members to kvm_segment_field to allow checking for other access
2004 * rights flags
2005 */
2006 return true;
2007}
2008
2009static bool tr_valid(struct kvm_vcpu *vcpu)
2010{
2011 struct kvm_segment tr;
2012
2013 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
2014
1872a3f4
AK		 2015 if (tr.unusable)
2016 return false;
648dfaa7
MG		 2017 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2018 return false;
1872a3f4 2019 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 2020 return false;
2021 if (!tr.present)
2022 return false;
2023
2024 return true;
2025}
2026
2027static bool ldtr_valid(struct kvm_vcpu *vcpu)
2028{
2029 struct kvm_segment ldtr;
2030
2031 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2032
1872a3f4
AK		 2033 if (ldtr.unusable)
2034 return true;
648dfaa7
MG		 2035 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2036 return false;
2037 if (ldtr.type != 2)
2038 return false;
2039 if (!ldtr.present)
2040 return false;
2041
2042 return true;
2043}
2044
2045static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2046{
2047 struct kvm_segment cs, ss;
2048
2049 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2050 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2051
2052 return ((cs.selector & SELECTOR_RPL_MASK) ==
2053 (ss.selector & SELECTOR_RPL_MASK));
2054}
2055
2056/*
2057 * Check if guest state is valid. Returns true if valid, false if
2058 * not.
2059 * We assume that registers are always usable
2060 */
2061static bool guest_state_valid(struct kvm_vcpu *vcpu)
2062{
2063 /* real mode guest state checks */
2064 if (!(vcpu->arch.cr0 & X86_CR0_PE)) {
2065 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2066 return false;
2067 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2068 return false;
2069 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2070 return false;
2071 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2072 return false;
2073 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2074 return false;
2075 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2076 return false;
2077 } else {
2078 /* protected mode guest state checks */
2079 if (!cs_ss_rpl_check(vcpu))
2080 return false;
2081 if (!code_segment_valid(vcpu))
2082 return false;
2083 if (!stack_segment_valid(vcpu))
2084 return false;
2085 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2086 return false;
2087 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2088 return false;
2089 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2090 return false;
2091 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2092 return false;
2093 if (!tr_valid(vcpu))
2094 return false;
2095 if (!ldtr_valid(vcpu))
2096 return false;
2097 }
2098 /* TODO:
2099 * - Add checks on RIP
2100 * - Add checks on RFLAGS
2101 */
2102
2103 return true;
2104}
2105
d77c26fc 2106static int init_rmode_tss(struct kvm *kvm)
6aa8b732 2107{
6aa8b732 2108 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde 2109 u16 data = 0;
10589a46 2110 int ret = 0;
195aefde 2111 int r;
6aa8b732 2112
195aefde
IE		 2113 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2114 if (r < 0)
10589a46 2115 goto out;
195aefde 2116 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 2117 r = kvm_write_guest_page(kvm, fn++, &data,
2118 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 2119 if (r < 0)
10589a46 2120 goto out;
195aefde
IE		 2121 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2122 if (r < 0)
10589a46 2123 goto out;
195aefde
IE		 2124 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2125 if (r < 0)
10589a46 2126 goto out;
195aefde 2127 data = ~0;
10589a46
MT		 2128 r = kvm_write_guest_page(kvm, fn, &data,
2129 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2130 sizeof(u8));
195aefde 2131 if (r < 0)
10589a46
MT		 2132 goto out;
2133
2134 ret = 1;
2135out:
10589a46 2136 return ret;
6aa8b732
AK		 2137}
2138
b7ebfb05
SY		 2139static int init_rmode_identity_map(struct kvm *kvm)
2140{
2141 int i, r, ret;
2142 pfn_t identity_map_pfn;
2143 u32 tmp;
2144
089d034e 2145 if (!enable_ept)
b7ebfb05
SY		 2146 return 1;
2147 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2148 printk(KERN_ERR "EPT: identity-mapping pagetable "
2149 "haven't been allocated!\n");
2150 return 0;
2151 }
2152 if (likely(kvm->arch.ept_identity_pagetable_done))
2153 return 1;
2154 ret = 0;
b927a3ce 2155 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
b7ebfb05
SY		 2156 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2157 if (r < 0)
2158 goto out;
2159 /* Set up identity-mapping pagetable for EPT in real mode */
2160 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2161 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2162 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2163 r = kvm_write_guest_page(kvm, identity_map_pfn,
2164 &tmp, i * sizeof(tmp), sizeof(tmp));
2165 if (r < 0)
2166 goto out;
2167 }
2168 kvm->arch.ept_identity_pagetable_done = true;
2169 ret = 1;
2170out:
2171 return ret;
2172}
2173
6aa8b732
AK		 2174static void seg_setup(int seg)
2175{
2176 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 2177 unsigned int ar;
6aa8b732
AK		 2178
2179 vmcs_write16(sf->selector, 0);
2180 vmcs_writel(sf->base, 0);
2181 vmcs_write32(sf->limit, 0xffff);
3a624e29
NK		 2182 if (enable_unrestricted_guest) {
2183 ar = 0x93;
2184 if (seg == VCPU_SREG_CS)
2185 ar |= 0x08; /* code segment */
2186 } else
2187 ar = 0xf3;
2188
2189 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 2190}
2191
f78e0e2e
SY		 2192static int alloc_apic_access_page(struct kvm *kvm)
2193{
2194 struct kvm_userspace_memory_region kvm_userspace_mem;
2195 int r = 0;
2196
72dc67a6 2197 down_write(&kvm->slots_lock);
bfc6d222 2198 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 2199 goto out;
2200 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2201 kvm_userspace_mem.flags = 0;
2202 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2203 kvm_userspace_mem.memory_size = PAGE_SIZE;
2204 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2205 if (r)
2206 goto out;
72dc67a6 2207
bfc6d222 2208 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
f78e0e2e 2209out:
72dc67a6 2210 up_write(&kvm->slots_lock);
f78e0e2e
SY		 2211 return r;
2212}
2213
b7ebfb05
SY		 2214static int alloc_identity_pagetable(struct kvm *kvm)
2215{
2216 struct kvm_userspace_memory_region kvm_userspace_mem;
2217 int r = 0;
2218
2219 down_write(&kvm->slots_lock);
2220 if (kvm->arch.ept_identity_pagetable)
2221 goto out;
2222 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2223 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 2224 kvm_userspace_mem.guest_phys_addr =
2225 kvm->arch.ept_identity_map_addr;
b7ebfb05
SY		 2226 kvm_userspace_mem.memory_size = PAGE_SIZE;
2227 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2228 if (r)
2229 goto out;
2230
b7ebfb05 2231 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
b927a3ce 2232 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
b7ebfb05
SY		 2233out:
2234 up_write(&kvm->slots_lock);
2235 return r;
2236}
2237
2384d2b3
SY		 2238static void allocate_vpid(struct vcpu_vmx *vmx)
2239{
2240 int vpid;
2241
2242 vmx->vpid = 0;
919818ab 2243 if (!enable_vpid)
2384d2b3
SY		 2244 return;
2245 spin_lock(&vmx_vpid_lock);
2246 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2247 if (vpid < VMX_NR_VPIDS) {
2248 vmx->vpid = vpid;
2249 __set_bit(vpid, vmx_vpid_bitmap);
2250 }
2251 spin_unlock(&vmx_vpid_lock);
2252}
2253
5897297b 2254static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
25c5f225 2255{
3e7c73e9 2256 int f = sizeof(unsigned long);
25c5f225
SY		 2257
2258 if (!cpu_has_vmx_msr_bitmap())
2259 return;
2260
2261 /*
2262 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2263 * have the write-low and read-high bitmap offsets the wrong way round.
2264 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2265 */
25c5f225 2266 if (msr <= 0x1fff) {
3e7c73e9
AK		 2267 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2268 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
25c5f225
SY		 2269 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2270 msr &= 0x1fff;
3e7c73e9
AK		 2271 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2272 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
25c5f225 2273 }
25c5f225
SY		 2274}
2275
5897297b
AK		 2276static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2277{
2278 if (!longmode_only)
2279 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2280 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2281}
2282
6aa8b732
AK		 2283/*
2284 * Sets up the vmcs for emulated real mode.
2285 */
8b9cf98c 2286static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 2287{
468d472f 2288 u32 host_sysenter_cs, msr_low, msr_high;
6aa8b732 2289 u32 junk;
53f658b3 2290 u64 host_pat, tsc_this, tsc_base;
6aa8b732
AK		 2291 unsigned long a;
2292 struct descriptor_table dt;
2293 int i;
cd2276a7 2294 unsigned long kvm_vmx_return;
6e5d865c 2295 u32 exec_control;
6aa8b732 2296
6aa8b732 2297 /* I/O */
3e7c73e9
AK		 2298 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2299 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 2300
25c5f225 2301 if (cpu_has_vmx_msr_bitmap())
5897297b 2302 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 2303
6aa8b732
AK		 2304 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2305
6aa8b732 2306 /* Control */
1c3d14fe
YS		 2307 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2308 vmcs_config.pin_based_exec_ctrl);
6e5d865c
YS		 2309
2310 exec_control = vmcs_config.cpu_based_exec_ctrl;
2311 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2312 exec_control &= ~CPU_BASED_TPR_SHADOW;
2313#ifdef CONFIG_X86_64
2314 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2315 CPU_BASED_CR8_LOAD_EXITING;
2316#endif
2317 }
089d034e 2318 if (!enable_ept)
d56f546d 2319 exec_control |= CPU_BASED_CR3_STORE_EXITING |
83dbc83a
MT		 2320 CPU_BASED_CR3_LOAD_EXITING |
2321 CPU_BASED_INVLPG_EXITING;
6e5d865c 2322 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6aa8b732 2323
83ff3b9d
SY		 2324 if (cpu_has_secondary_exec_ctrls()) {
2325 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2326 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2327 exec_control &=
2328 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2384d2b3
SY		 2329 if (vmx->vpid == 0)
2330 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
046d8710 2331 if (!enable_ept) {
d56f546d 2332 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
046d8710
SY		 2333 enable_unrestricted_guest = 0;
2334 }
3a624e29
NK		 2335 if (!enable_unrestricted_guest)
2336 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4b8d54f9
ZE		 2337 if (!ple_gap)
2338 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
83ff3b9d
SY		 2339 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2340 }
f78e0e2e 2341
4b8d54f9
ZE		 2342 if (ple_gap) {
2343 vmcs_write32(PLE_GAP, ple_gap);
2344 vmcs_write32(PLE_WINDOW, ple_window);
2345 }
2346
c7addb90
AK		 2347 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2348 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
6aa8b732
AK		 2349 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2350
2351 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
2352 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2353 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2354
2355 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2356 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2357 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
d6e88aec
AK		 2358 vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs()); /* 22.2.4 */
2359 vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs()); /* 22.2.4 */
6aa8b732 2360 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
05b3e0c2 2361#ifdef CONFIG_X86_64
6aa8b732
AK		 2362 rdmsrl(MSR_FS_BASE, a);
2363 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2364 rdmsrl(MSR_GS_BASE, a);
2365 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2366#else
2367 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2368 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2369#endif
2370
2371 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2372
d6e88aec 2373 kvm_get_idt(&dt);
6aa8b732
AK		 2374 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
2375
d77c26fc 2376 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
cd2276a7 2377 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2cc51560
ED		 2378 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2379 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2380 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
6aa8b732
AK		 2381
2382 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2383 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2384 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2385 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2386 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2387 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2388
468d472f
SY		 2389 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2390 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2391 host_pat = msr_low | ((u64) msr_high << 32);
2392 vmcs_write64(HOST_IA32_PAT, host_pat);
2393 }
2394 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2395 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2396 host_pat = msr_low | ((u64) msr_high << 32);
2397 /* Write the default value follow host pat */
2398 vmcs_write64(GUEST_IA32_PAT, host_pat);
2399 /* Keep arch.pat sync with GUEST_IA32_PAT */
2400 vmx->vcpu.arch.pat = host_pat;
2401 }
2402
6aa8b732
AK		 2403 for (i = 0; i < NR_VMX_MSR; ++i) {
2404 u32 index = vmx_msr_index[i];
2405 u32 data_low, data_high;
2406 u64 data;
a2fa3e9f 2407 int j = vmx->nmsrs;
6aa8b732
AK		 2408
2409 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2410 continue;
432bd6cb
AK		 2411 if (wrmsr_safe(index, data_low, data_high) < 0)
2412 continue;
6aa8b732 2413 data = data_low | ((u64)data_high << 32);
26bb0981
AK		 2414 vmx->guest_msrs[j].index = i;
2415 vmx->guest_msrs[j].data = 0;
d5696725 2416 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 2417 ++vmx->nmsrs;
6aa8b732 2418 }
6aa8b732 2419
1c3d14fe 2420 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 2421
2422 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 2423 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2424
e00c8cf2 2425 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4c38609a
AK		 2426 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
2427 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
e00c8cf2 2428
53f658b3
MT		 2429 tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc;
2430 rdtscll(tsc_this);
2431 if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc)
2432 tsc_base = tsc_this;
2433
2434 guest_write_tsc(0, tsc_base);
f78e0e2e 2435
e00c8cf2
AK		 2436 return 0;
2437}
2438
b7ebfb05
SY		 2439static int init_rmode(struct kvm *kvm)
2440{
2441 if (!init_rmode_tss(kvm))
2442 return 0;
2443 if (!init_rmode_identity_map(kvm))
2444 return 0;
2445 return 1;
2446}
2447
e00c8cf2
AK		 2448static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2449{
2450 struct vcpu_vmx *vmx = to_vmx(vcpu);
2451 u64 msr;
2452 int ret;
2453
5fdbf976 2454 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3200f405 2455 down_read(&vcpu->kvm->slots_lock);
b7ebfb05 2456 if (!init_rmode(vmx->vcpu.kvm)) {
e00c8cf2
AK		 2457 ret = -ENOMEM;
2458 goto out;
2459 }
2460
7ffd92c5 2461 vmx->rmode.vm86_active = 0;
e00c8cf2 2462
3b86cd99
JK		 2463 vmx->soft_vnmi_blocked = 0;
2464
ad312c7c 2465 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 2466 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 2467 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 2468 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 2469 msr |= MSR_IA32_APICBASE_BSP;
2470 kvm_set_apic_base(&vmx->vcpu, msr);
2471
2472 fx_init(&vmx->vcpu);
2473
5706be0d 2474 seg_setup(VCPU_SREG_CS);
e00c8cf2
AK		 2475 /*
2476 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2477 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2478 */
c5af89b6 2479 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
e00c8cf2
AK		 2480 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2481 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2482 } else {
ad312c7c
ZX		 2483 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2484 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2 2485 }
e00c8cf2
AK		 2486
2487 seg_setup(VCPU_SREG_DS);
2488 seg_setup(VCPU_SREG_ES);
2489 seg_setup(VCPU_SREG_FS);
2490 seg_setup(VCPU_SREG_GS);
2491 seg_setup(VCPU_SREG_SS);
2492
2493 vmcs_write16(GUEST_TR_SELECTOR, 0);
2494 vmcs_writel(GUEST_TR_BASE, 0);
2495 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2496 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2497
2498 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2499 vmcs_writel(GUEST_LDTR_BASE, 0);
2500 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2501 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2502
2503 vmcs_write32(GUEST_SYSENTER_CS, 0);
2504 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2505 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2506
2507 vmcs_writel(GUEST_RFLAGS, 0x02);
c5af89b6 2508 if (kvm_vcpu_is_bsp(&vmx->vcpu))
5fdbf976 2509 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 2510 else
5fdbf976
MT		 2511 kvm_rip_write(vcpu, 0);
2512 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
e00c8cf2 2513
e00c8cf2
AK		 2514 vmcs_writel(GUEST_DR7, 0x400);
2515
2516 vmcs_writel(GUEST_GDTR_BASE, 0);
2517 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2518
2519 vmcs_writel(GUEST_IDTR_BASE, 0);
2520 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2521
2522 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2523 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2524 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2525
e00c8cf2
AK		 2526 /* Special registers */
2527 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2528
2529 setup_msrs(vmx);
2530
6aa8b732
AK		 2531 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2532
f78e0e2e
SY		 2533 if (cpu_has_vmx_tpr_shadow()) {
2534 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2535 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2536 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
ad312c7c 2537 page_to_phys(vmx->vcpu.arch.apic->regs_page));
f78e0e2e
SY		 2538 vmcs_write32(TPR_THRESHOLD, 0);
2539 }
2540
2541 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2542 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 2543 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 2544
2384d2b3
SY		 2545 if (vmx->vpid != 0)
2546 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2547
fa40052c 2548 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
ad312c7c 2549 vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
8b9cf98c 2550 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 2551 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 2552 vmx_fpu_activate(&vmx->vcpu);
2553 update_exception_bitmap(&vmx->vcpu);
6aa8b732 2554
2384d2b3
SY		 2555 vpid_sync_vcpu_all(vmx);
2556
3200f405 2557 ret = 0;
6aa8b732 2558
a89a8fb9
MG		 2559 /* HACK: Don't enable emulation on guest boot/reset */
2560 vmx->emulation_required = 0;
2561
6aa8b732 2562out:
3200f405 2563 up_read(&vcpu->kvm->slots_lock);
6aa8b732
AK		 2564 return ret;
2565}
2566
3b86cd99
JK		 2567static void enable_irq_window(struct kvm_vcpu *vcpu)
2568{
2569 u32 cpu_based_vm_exec_control;
2570
2571 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2572 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2573 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2574}
2575
2576static void enable_nmi_window(struct kvm_vcpu *vcpu)
2577{
2578 u32 cpu_based_vm_exec_control;
2579
2580 if (!cpu_has_virtual_nmis()) {
2581 enable_irq_window(vcpu);
2582 return;
2583 }
2584
2585 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2586 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2587 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2588}
2589
66fd3f7f 2590static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 2591{
9c8cba37 2592 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 2593 uint32_t intr;
2594 int irq = vcpu->arch.interrupt.nr;
9c8cba37 2595
229456fc 2596 trace_kvm_inj_virq(irq);
2714d1d3 2597
fa89a817 2598 ++vcpu->stat.irq_injections;
7ffd92c5 2599 if (vmx->rmode.vm86_active) {
9c8cba37
AK		 2600 vmx->rmode.irq.pending = true;
2601 vmx->rmode.irq.vector = irq;
5fdbf976 2602 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
ae0bb3e0
GN		 2603 if (vcpu->arch.interrupt.soft)
2604 vmx->rmode.irq.rip +=
2605 vmx->vcpu.arch.event_exit_inst_len;
9c5623e3
AK		 2606 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2607 irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2608 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
5fdbf976 2609 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
85f455f7
ED		 2610 return;
2611 }
66fd3f7f
GN		 2612 intr = irq | INTR_INFO_VALID_MASK;
2613 if (vcpu->arch.interrupt.soft) {
2614 intr |= INTR_TYPE_SOFT_INTR;
2615 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2616 vmx->vcpu.arch.event_exit_inst_len);
2617 } else
2618 intr |= INTR_TYPE_EXT_INTR;
2619 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 2620}
2621
f08864b4
SY		 2622static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2623{
66a5a347
JK		 2624 struct vcpu_vmx *vmx = to_vmx(vcpu);
2625
3b86cd99
JK		 2626 if (!cpu_has_virtual_nmis()) {
2627 /*
2628 * Tracking the NMI-blocked state in software is built upon
2629 * finding the next open IRQ window. This, in turn, depends on
2630 * well-behaving guests: They have to keep IRQs disabled at
2631 * least as long as the NMI handler runs. Otherwise we may
2632 * cause NMI nesting, maybe breaking the guest. But as this is
2633 * highly unlikely, we can live with the residual risk.
2634 */
2635 vmx->soft_vnmi_blocked = 1;
2636 vmx->vnmi_blocked_time = 0;
2637 }
2638
487b391d 2639 ++vcpu->stat.nmi_injections;
7ffd92c5 2640 if (vmx->rmode.vm86_active) {
66a5a347
JK		 2641 vmx->rmode.irq.pending = true;
2642 vmx->rmode.irq.vector = NMI_VECTOR;
2643 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2644 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2645 NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2646 INTR_INFO_VALID_MASK);
2647 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2648 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2649 return;
2650 }
f08864b4
SY		 2651 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2652 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 2653}
2654
c4282df9 2655static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
33f089ca 2656{
3b86cd99 2657 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
c4282df9 2658 return 0;
33f089ca 2659
c4282df9
GN		 2660 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2661 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS |
2662 GUEST_INTR_STATE_NMI));
33f089ca
JK		 2663}
2664
3cfc3092
JK		 2665static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
2666{
2667 if (!cpu_has_virtual_nmis())
2668 return to_vmx(vcpu)->soft_vnmi_blocked;
2669 else
2670 return !!(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2671 GUEST_INTR_STATE_NMI);
2672}
2673
2674static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2675{
2676 struct vcpu_vmx *vmx = to_vmx(vcpu);
2677
2678 if (!cpu_has_virtual_nmis()) {
2679 if (vmx->soft_vnmi_blocked != masked) {
2680 vmx->soft_vnmi_blocked = masked;
2681 vmx->vnmi_blocked_time = 0;
2682 }
2683 } else {
2684 if (masked)
2685 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
2686 GUEST_INTR_STATE_NMI);
2687 else
2688 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2689 GUEST_INTR_STATE_NMI);
2690 }
2691}
2692
78646121
GN		 2693static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2694{
c4282df9
GN		 2695 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2696 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2697 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 2698}
2699
cbc94022
IE		 2700static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2701{
2702 int ret;
2703 struct kvm_userspace_memory_region tss_mem = {
6fe63979 2704 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 2705 .guest_phys_addr = addr,
2706 .memory_size = PAGE_SIZE * 3,
2707 .flags = 0,
2708 };
2709
2710 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2711 if (ret)
2712 return ret;
bfc6d222 2713 kvm->arch.tss_addr = addr;
cbc94022
IE		 2714 return 0;
2715}
2716
6aa8b732
AK		 2717static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2718 int vec, u32 err_code)
2719{
b3f37707
NK		 2720 /*
2721 * Instruction with address size override prefix opcode 0x67
2722 * Cause the #SS fault with 0 error code in VM86 mode.
2723 */
2724 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
851ba692 2725 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE)
6aa8b732 2726 return 1;
77ab6db0
JK		 2727 /*
2728 * Forward all other exceptions that are valid in real mode.
2729 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2730 * the required debugging infrastructure rework.
2731 */
2732 switch (vec) {
77ab6db0 2733 case DB_VECTOR:
d0bfb940
JK		 2734 if (vcpu->guest_debug &
2735 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2736 return 0;
2737 kvm_queue_exception(vcpu, vec);
2738 return 1;
77ab6db0 2739 case BP_VECTOR:
d0bfb940
JK		 2740 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2741 return 0;
2742 /* fall through */
2743 case DE_VECTOR:
77ab6db0
JK		 2744 case OF_VECTOR:
2745 case BR_VECTOR:
2746 case UD_VECTOR:
2747 case DF_VECTOR:
2748 case SS_VECTOR:
2749 case GP_VECTOR:
2750 case MF_VECTOR:
2751 kvm_queue_exception(vcpu, vec);
2752 return 1;
2753 }
6aa8b732
AK		 2754 return 0;
2755}
2756
a0861c02
AK		 2757/*
2758 * Trigger machine check on the host. We assume all the MSRs are already set up
2759 * by the CPU and that we still run on the same CPU as the MCE occurred on.
2760 * We pass a fake environment to the machine check handler because we want
2761 * the guest to be always treated like user space, no matter what context
2762 * it used internally.
2763 */
2764static void kvm_machine_check(void)
2765{
2766#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
2767 struct pt_regs regs = {
2768 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
2769 .flags = X86_EFLAGS_IF,
2770 };
2771
2772 do_machine_check(&regs, 0);
2773#endif
2774}
2775
851ba692 2776static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 2777{
2778 /* already handled by vcpu_run */
2779 return 1;
2780}
2781
851ba692 2782static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 2783{
1155f76a 2784 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 2785 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 2786 u32 intr_info, ex_no, error_code;
42dbaa5a 2787 unsigned long cr2, rip, dr6;
6aa8b732
AK		 2788 u32 vect_info;
2789 enum emulation_result er;
2790
1155f76a 2791 vect_info = vmx->idt_vectoring_info;
6aa8b732
AK		 2792 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2793
a0861c02 2794 if (is_machine_check(intr_info))
851ba692 2795 return handle_machine_check(vcpu);
a0861c02 2796
6aa8b732 2797 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
65ac7264
AK		 2798 !is_page_fault(intr_info)) {
2799 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2800 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
2801 vcpu->run->internal.ndata = 2;
2802 vcpu->run->internal.data[0] = vect_info;
2803 vcpu->run->internal.data[1] = intr_info;
2804 return 0;
2805 }
6aa8b732 2806
e4a41889 2807 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 2808 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 2809
2810 if (is_no_device(intr_info)) {
5fd86fcf 2811 vmx_fpu_activate(vcpu);
2ab455cc
AL		 2812 return 1;
2813 }
2814
7aa81cc0 2815 if (is_invalid_opcode(intr_info)) {
851ba692 2816 er = emulate_instruction(vcpu, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 2817 if (er != EMULATE_DONE)
7ee5d940 2818 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 2819 return 1;
2820 }
2821
6aa8b732 2822 error_code = 0;
5fdbf976 2823 rip = kvm_rip_read(vcpu);
2e11384c 2824 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732
AK		 2825 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2826 if (is_page_fault(intr_info)) {
1439442c 2827 /* EPT won't cause page fault directly */
089d034e 2828 if (enable_ept)
1439442c 2829 BUG();
6aa8b732 2830 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 2831 trace_kvm_page_fault(cr2, error_code);
2832
3298b75c 2833 if (kvm_event_needs_reinjection(vcpu))
577bdc49 2834 kvm_mmu_unprotect_page_virt(vcpu, cr2);
3067714c 2835 return kvm_mmu_page_fault(vcpu, cr2, error_code);
6aa8b732
AK		 2836 }
2837
7ffd92c5 2838 if (vmx->rmode.vm86_active &&
6aa8b732 2839 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0 2840 error_code)) {
ad312c7c
ZX		 2841 if (vcpu->arch.halt_request) {
2842 vcpu->arch.halt_request = 0;
72d6e5a0
AK		 2843 return kvm_emulate_halt(vcpu);
2844 }
6aa8b732 2845 return 1;
72d6e5a0 2846 }
6aa8b732 2847
d0bfb940 2848 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
42dbaa5a
JK		 2849 switch (ex_no) {
2850 case DB_VECTOR:
2851 dr6 = vmcs_readl(EXIT_QUALIFICATION);
2852 if (!(vcpu->guest_debug &
2853 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
2854 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
2855 kvm_queue_exception(vcpu, DB_VECTOR);
2856 return 1;
2857 }
2858 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
2859 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
2860 /* fall through */
2861 case BP_VECTOR:
6aa8b732 2862 kvm_run->exit_reason = KVM_EXIT_DEBUG;
d0bfb940
JK		 2863 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
2864 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 2865 break;
2866 default:
d0bfb940
JK		 2867 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2868 kvm_run->ex.exception = ex_no;
2869 kvm_run->ex.error_code = error_code;
42dbaa5a 2870 break;
6aa8b732 2871 }
6aa8b732
AK		 2872 return 0;
2873}
2874
851ba692 2875static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 2876{
1165f5fe 2877 ++vcpu->stat.irq_exits;
6aa8b732
AK		 2878 return 1;
2879}
2880
851ba692 2881static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 2882{
851ba692 2883 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 2884 return 0;
2885}
6aa8b732 2886
851ba692 2887static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 2888{
bfdaab09 2889 unsigned long exit_qualification;
34c33d16 2890 int size, in, string;
039576c0 2891 unsigned port;
6aa8b732 2892
1165f5fe 2893 ++vcpu->stat.io_exits;
bfdaab09 2894 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 2895 string = (exit_qualification & 16) != 0;
e70669ab
LV		 2896
2897 if (string) {
851ba692 2898 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DO_MMIO)
e70669ab
LV		 2899 return 0;
2900 return 1;
2901 }
2902
2903 size = (exit_qualification & 7) + 1;
2904 in = (exit_qualification & 8) != 0;
039576c0 2905 port = exit_qualification >> 16;
e70669ab 2906
e93f36bc 2907 skip_emulated_instruction(vcpu);
851ba692 2908 return kvm_emulate_pio(vcpu, in, size, port);
6aa8b732
AK		 2909}
2910
102d8325
IM		 2911static void
2912vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2913{
2914 /*
2915 * Patch in the VMCALL instruction:
2916 */
2917 hypercall[0] = 0x0f;
2918 hypercall[1] = 0x01;
2919 hypercall[2] = 0xc1;
102d8325
IM		 2920}
2921
851ba692 2922static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 2923{
229456fc 2924 unsigned long exit_qualification, val;
6aa8b732
AK		 2925 int cr;
2926 int reg;
2927
bfdaab09 2928 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 2929 cr = exit_qualification & 15;
2930 reg = (exit_qualification >> 8) & 15;
2931 switch ((exit_qualification >> 4) & 3) {
2932 case 0: /* mov to cr */
229456fc
MT		 2933 val = kvm_register_read(vcpu, reg);
2934 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 2935 switch (cr) {
2936 case 0:
229456fc 2937 kvm_set_cr0(vcpu, val);
6aa8b732
AK		 2938 skip_emulated_instruction(vcpu);
2939 return 1;
2940 case 3:
229456fc 2941 kvm_set_cr3(vcpu, val);
6aa8b732
AK		 2942 skip_emulated_instruction(vcpu);
2943 return 1;
2944 case 4:
229456fc 2945 kvm_set_cr4(vcpu, val);
6aa8b732
AK		 2946 skip_emulated_instruction(vcpu);
2947 return 1;
0a5fff19
GN		 2948 case 8: {
2949 u8 cr8_prev = kvm_get_cr8(vcpu);
2950 u8 cr8 = kvm_register_read(vcpu, reg);
2951 kvm_set_cr8(vcpu, cr8);
2952 skip_emulated_instruction(vcpu);
2953 if (irqchip_in_kernel(vcpu->kvm))
2954 return 1;
2955 if (cr8_prev <= cr8)
2956 return 1;
851ba692 2957 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 2958 return 0;
2959 }
6aa8b732
AK		 2960 };
2961 break;
25c4c276 2962 case 2: /* clts */
5fd86fcf 2963 vmx_fpu_deactivate(vcpu);
ad312c7c
ZX		 2964 vcpu->arch.cr0 &= ~X86_CR0_TS;
2965 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf 2966 vmx_fpu_activate(vcpu);
25c4c276
AL		 2967 skip_emulated_instruction(vcpu);
2968 return 1;
6aa8b732
AK		 2969 case 1: /*mov from cr*/
2970 switch (cr) {
2971 case 3:
5fdbf976 2972 kvm_register_write(vcpu, reg, vcpu->arch.cr3);
229456fc 2973 trace_kvm_cr_read(cr, vcpu->arch.cr3);
6aa8b732
AK		 2974 skip_emulated_instruction(vcpu);
2975 return 1;
2976 case 8:
229456fc
MT		 2977 val = kvm_get_cr8(vcpu);
2978 kvm_register_write(vcpu, reg, val);
2979 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 2980 skip_emulated_instruction(vcpu);
2981 return 1;
2982 }
2983 break;
2984 case 3: /* lmsw */
2d3ad1f4 2985 kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
6aa8b732
AK		 2986
2987 skip_emulated_instruction(vcpu);
2988 return 1;
2989 default:
2990 break;
2991 }
851ba692 2992 vcpu->run->exit_reason = 0;
f0242478 2993 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 2994 (int)(exit_qualification >> 4) & 3, cr);
2995 return 0;
2996}
2997
851ba692 2998static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 2999{
bfdaab09 3000 unsigned long exit_qualification;
6aa8b732
AK		 3001 unsigned long val;
3002 int dr, reg;
3003
0a79b009
AK		 3004 if (!kvm_require_cpl(vcpu, 0))
3005 return 1;
42dbaa5a
JK		 3006 dr = vmcs_readl(GUEST_DR7);
3007 if (dr & DR7_GD) {
3008 /*
3009 * As the vm-exit takes precedence over the debug trap, we
3010 * need to emulate the latter, either for the host or the
3011 * guest debugging itself.
3012 */
3013 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 3014 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
3015 vcpu->run->debug.arch.dr7 = dr;
3016 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 3017 vmcs_readl(GUEST_CS_BASE) +
3018 vmcs_readl(GUEST_RIP);
851ba692
AK		 3019 vcpu->run->debug.arch.exception = DB_VECTOR;
3020 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 3021 return 0;
3022 } else {
3023 vcpu->arch.dr7 &= ~DR7_GD;
3024 vcpu->arch.dr6 |= DR6_BD;
3025 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3026 kvm_queue_exception(vcpu, DB_VECTOR);
3027 return 1;
3028 }
3029 }
3030
bfdaab09 3031 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 3032 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
3033 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
3034 if (exit_qualification & TYPE_MOV_FROM_DR) {
6aa8b732 3035 switch (dr) {
42dbaa5a
JK		 3036 case 0 ... 3:
3037 val = vcpu->arch.db[dr];
3038 break;
6aa8b732 3039 case 6:
42dbaa5a 3040 val = vcpu->arch.dr6;
6aa8b732
AK		 3041 break;
3042 case 7:
42dbaa5a 3043 val = vcpu->arch.dr7;
6aa8b732
AK		 3044 break;
3045 default:
3046 val = 0;
3047 }
5fdbf976 3048 kvm_register_write(vcpu, reg, val);
6aa8b732 3049 } else {
42dbaa5a
JK		 3050 val = vcpu->arch.regs[reg];
3051 switch (dr) {
3052 case 0 ... 3:
3053 vcpu->arch.db[dr] = val;
3054 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
3055 vcpu->arch.eff_db[dr] = val;
3056 break;
3057 case 4 ... 5:
fc78f519 3058 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
42dbaa5a
JK		 3059 kvm_queue_exception(vcpu, UD_VECTOR);
3060 break;
3061 case 6:
3062 if (val & 0xffffffff00000000ULL) {
3063 kvm_queue_exception(vcpu, GP_VECTOR);
3064 break;
3065 }
3066 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
3067 break;
3068 case 7:
3069 if (val & 0xffffffff00000000ULL) {
3070 kvm_queue_exception(vcpu, GP_VECTOR);
3071 break;
3072 }
3073 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
3074 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
3075 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3076 vcpu->arch.switch_db_regs =
3077 (val & DR7_BP_EN_MASK);
3078 }
3079 break;
3080 }
6aa8b732 3081 }
6aa8b732
AK		 3082 skip_emulated_instruction(vcpu);
3083 return 1;
3084}
3085
851ba692 3086static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 3087{
06465c5a
AK		 3088 kvm_emulate_cpuid(vcpu);
3089 return 1;
6aa8b732
AK		 3090}
3091
851ba692 3092static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 3093{
ad312c7c 3094 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 3095 u64 data;
3096
3097 if (vmx_get_msr(vcpu, ecx, &data)) {
c1a5d4f9 3098 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 3099 return 1;
3100 }
3101
229456fc 3102 trace_kvm_msr_read(ecx, data);
2714d1d3 3103
6aa8b732 3104 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 3105 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3106 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 3107 skip_emulated_instruction(vcpu);
3108 return 1;
3109}
3110
851ba692 3111static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 3112{
ad312c7c
ZX		 3113 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3114 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3115 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 3116
229456fc 3117 trace_kvm_msr_write(ecx, data);
2714d1d3 3118
6aa8b732 3119 if (vmx_set_msr(vcpu, ecx, data) != 0) {
c1a5d4f9 3120 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 3121 return 1;
3122 }
3123
3124 skip_emulated_instruction(vcpu);
3125 return 1;
3126}
3127
851ba692 3128static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c
YS		 3129{
3130 return 1;
3131}
3132
851ba692 3133static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 3134{
85f455f7
ED		 3135 u32 cpu_based_vm_exec_control;
3136
3137 /* clear pending irq */
3138 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3139 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3140 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 3141
a26bf12a 3142 ++vcpu->stat.irq_window_exits;
2714d1d3 3143
c1150d8c
DL		 3144 /*
3145 * If the user space waits to inject interrupts, exit as soon as
3146 * possible
3147 */
8061823a 3148 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 3149 vcpu->run->request_interrupt_window &&
8061823a 3150 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 3151 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 3152 return 0;
3153 }
6aa8b732
AK		 3154 return 1;
3155}
3156
851ba692 3157static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 3158{
3159 skip_emulated_instruction(vcpu);
d3bef15f 3160 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 3161}
3162
851ba692 3163static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 3164{
510043da 3165 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 3166 kvm_emulate_hypercall(vcpu);
3167 return 1;
c21415e8
IM		 3168}
3169
851ba692 3170static int handle_vmx_insn(struct kvm_vcpu *vcpu)
e3c7cb6a
AK		 3171{
3172 kvm_queue_exception(vcpu, UD_VECTOR);
3173 return 1;
3174}
3175
851ba692 3176static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 3177{
f9c617f6 3178 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 3179
3180 kvm_mmu_invlpg(vcpu, exit_qualification);
3181 skip_emulated_instruction(vcpu);
3182 return 1;
3183}
3184
851ba692 3185static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 3186{
3187 skip_emulated_instruction(vcpu);
3188 /* TODO: Add support for VT-d/pass-through device */
3189 return 1;
3190}
3191
851ba692 3192static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 3193{
f9c617f6 3194 unsigned long exit_qualification;
f78e0e2e
SY		 3195 enum emulation_result er;
3196 unsigned long offset;
3197
f9c617f6 3198 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
f78e0e2e
SY		 3199 offset = exit_qualification & 0xffful;
3200
851ba692 3201 er = emulate_instruction(vcpu, 0, 0, 0);
f78e0e2e
SY		 3202
3203 if (er != EMULATE_DONE) {
3204 printk(KERN_ERR
3205 "Fail to handle apic access vmexit! Offset is 0x%lx\n",
3206 offset);
7f582ab6 3207 return -ENOEXEC;
f78e0e2e
SY		 3208 }
3209 return 1;
3210}
3211
851ba692 3212static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 3213{
60637aac 3214 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29
IE		 3215 unsigned long exit_qualification;
3216 u16 tss_selector;
64a7ec06
GN		 3217 int reason, type, idt_v;
3218
3219 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3220 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 3221
3222 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3223
3224 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 3225 if (reason == TASK_SWITCH_GATE && idt_v) {
3226 switch (type) {
3227 case INTR_TYPE_NMI_INTR:
3228 vcpu->arch.nmi_injected = false;
3229 if (cpu_has_virtual_nmis())
3230 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3231 GUEST_INTR_STATE_NMI);
3232 break;
3233 case INTR_TYPE_EXT_INTR:
66fd3f7f 3234 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 3235 kvm_clear_interrupt_queue(vcpu);
3236 break;
3237 case INTR_TYPE_HARD_EXCEPTION:
3238 case INTR_TYPE_SOFT_EXCEPTION:
3239 kvm_clear_exception_queue(vcpu);
3240 break;
3241 default:
3242 break;
3243 }
60637aac 3244 }
37817f29
IE		 3245 tss_selector = exit_qualification;
3246
64a7ec06
GN		 3247 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3248 type != INTR_TYPE_EXT_INTR &&
3249 type != INTR_TYPE_NMI_INTR))
3250 skip_emulated_instruction(vcpu);
3251
42dbaa5a
JK		 3252 if (!kvm_task_switch(vcpu, tss_selector, reason))
3253 return 0;
3254
3255 /* clear all local breakpoint enable flags */
3256 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3257
3258 /*
3259 * TODO: What about debug traps on tss switch?
3260 * Are we supposed to inject them and update dr6?
3261 */
3262
3263 return 1;
37817f29
IE		 3264}
3265
851ba692 3266static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 3267{
f9c617f6 3268 unsigned long exit_qualification;
1439442c 3269 gpa_t gpa;
1439442c 3270 int gla_validity;
1439442c 3271
f9c617f6 3272 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c
SY		 3273
3274 if (exit_qualification & (1 << 6)) {
3275 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
7f582ab6 3276 return -EINVAL;
1439442c
SY		 3277 }
3278
3279 gla_validity = (exit_qualification >> 7) & 0x3;
3280 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3281 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3282 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3283 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 3284 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 3285 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3286 (long unsigned int)exit_qualification);
851ba692
AK		 3287 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3288 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 3289 return 0;
1439442c
SY		 3290 }
3291
3292 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 3293 trace_kvm_page_fault(gpa, exit_qualification);
49cd7d22 3294 return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
1439442c
SY		 3295}
3296
68f89400
MT		 3297static u64 ept_rsvd_mask(u64 spte, int level)
3298{
3299 int i;
3300 u64 mask = 0;
3301
3302 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3303 mask |= (1ULL << i);
3304
3305 if (level > 2)
3306 /* bits 7:3 reserved */
3307 mask |= 0xf8;
3308 else if (level == 2) {
3309 if (spte & (1ULL << 7))
3310 /* 2MB ref, bits 20:12 reserved */
3311 mask |= 0x1ff000;
3312 else
3313 /* bits 6:3 reserved */
3314 mask |= 0x78;
3315 }
3316
3317 return mask;
3318}
3319
3320static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3321 int level)
3322{
3323 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3324
3325 /* 010b (write-only) */
3326 WARN_ON((spte & 0x7) == 0x2);
3327
3328 /* 110b (write/execute) */
3329 WARN_ON((spte & 0x7) == 0x6);
3330
3331 /* 100b (execute-only) and value not supported by logical processor */
3332 if (!cpu_has_vmx_ept_execute_only())
3333 WARN_ON((spte & 0x7) == 0x4);
3334
3335 /* not 000b */
3336 if ((spte & 0x7)) {
3337 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3338
3339 if (rsvd_bits != 0) {
3340 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3341 __func__, rsvd_bits);
3342 WARN_ON(1);
3343 }
3344
3345 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3346 u64 ept_mem_type = (spte & 0x38) >> 3;
3347
3348 if (ept_mem_type == 2 || ept_mem_type == 3 ||
3349 ept_mem_type == 7) {
3350 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3351 __func__, ept_mem_type);
3352 WARN_ON(1);
3353 }
3354 }
3355 }
3356}
3357
851ba692 3358static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 3359{
3360 u64 sptes[4];
3361 int nr_sptes, i;
3362 gpa_t gpa;
3363
3364 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3365
3366 printk(KERN_ERR "EPT: Misconfiguration.\n");
3367 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3368
3369 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3370
3371 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3372 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3373
851ba692
AK		 3374 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3375 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 3376
3377 return 0;
3378}
3379
851ba692 3380static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 3381{
3382 u32 cpu_based_vm_exec_control;
3383
3384 /* clear pending NMI */
3385 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3386 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3387 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3388 ++vcpu->stat.nmi_window_exits;
3389
3390 return 1;
3391}
3392
80ced186 3393static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 3394{
8b3079a5
AK		 3395 struct vcpu_vmx *vmx = to_vmx(vcpu);
3396 enum emulation_result err = EMULATE_DONE;
80ced186 3397 int ret = 1;
ea953ef0
MG		 3398
3399 while (!guest_state_valid(vcpu)) {
851ba692 3400 err = emulate_instruction(vcpu, 0, 0, 0);
ea953ef0 3401
80ced186
MG		 3402 if (err == EMULATE_DO_MMIO) {
3403 ret = 0;
3404 goto out;
3405 }
1d5a4d9b
GT		 3406
3407 if (err != EMULATE_DONE) {
3408 kvm_report_emulation_failure(vcpu, "emulation failure");
80ced186
MG		 3409 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3410 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
a9c7399d 3411 vcpu->run->internal.ndata = 0;
80ced186
MG		 3412 ret = 0;
3413 goto out;
ea953ef0
MG		 3414 }
3415
3416 if (signal_pending(current))
80ced186 3417 goto out;
ea953ef0
MG		 3418 if (need_resched())
3419 schedule();
3420 }
3421
80ced186
MG		 3422 vmx->emulation_required = 0;
3423out:
3424 return ret;
ea953ef0
MG		 3425}
3426
4b8d54f9
ZE		 3427/*
3428 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3429 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3430 */
9fb41ba8 3431static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 3432{
3433 skip_emulated_instruction(vcpu);
3434 kvm_vcpu_on_spin(vcpu);
3435
3436 return 1;
3437}
3438
59708670
SY		 3439static int handle_invalid_op(struct kvm_vcpu *vcpu)
3440{
3441 kvm_queue_exception(vcpu, UD_VECTOR);
3442 return 1;
3443}
3444
6aa8b732
AK		 3445/*
3446 * The exit handlers return 1 if the exit was handled fully and guest execution
3447 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3448 * to be done to userspace and return 0.
3449 */
851ba692 3450static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 3451 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3452 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 3453 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 3454 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 3455 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 3456 [EXIT_REASON_CR_ACCESS] = handle_cr,
3457 [EXIT_REASON_DR_ACCESS] = handle_dr,
3458 [EXIT_REASON_CPUID] = handle_cpuid,
3459 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3460 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3461 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3462 [EXIT_REASON_HLT] = handle_halt,
a7052897 3463 [EXIT_REASON_INVLPG] = handle_invlpg,
c21415e8 3464 [EXIT_REASON_VMCALL] = handle_vmcall,
e3c7cb6a
AK		 3465 [EXIT_REASON_VMCLEAR] = handle_vmx_insn,
3466 [EXIT_REASON_VMLAUNCH] = handle_vmx_insn,
3467 [EXIT_REASON_VMPTRLD] = handle_vmx_insn,
3468 [EXIT_REASON_VMPTRST] = handle_vmx_insn,
3469 [EXIT_REASON_VMREAD] = handle_vmx_insn,
3470 [EXIT_REASON_VMRESUME] = handle_vmx_insn,
3471 [EXIT_REASON_VMWRITE] = handle_vmx_insn,
3472 [EXIT_REASON_VMOFF] = handle_vmx_insn,
3473 [EXIT_REASON_VMON] = handle_vmx_insn,
f78e0e2e
SY		 3474 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3475 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 3476 [EXIT_REASON_WBINVD] = handle_wbinvd,
37817f29 3477 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 3478 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 3479 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
3480 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 3481 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 3482 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
3483 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
6aa8b732
AK		 3484};
3485
3486static const int kvm_vmx_max_exit_handlers =
50a3485c 3487 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732
AK		 3488
3489/*
3490 * The guest has exited. See if we can fix it or if we need userspace
3491 * assistance.
3492 */
851ba692 3493static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 3494{
29bd8a78 3495 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 3496 u32 exit_reason = vmx->exit_reason;
1155f76a 3497 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 3498
229456fc 3499 trace_kvm_exit(exit_reason, kvm_rip_read(vcpu));
2714d1d3 3500
80ced186
MG		 3501 /* If guest state is invalid, start emulating */
3502 if (vmx->emulation_required && emulate_invalid_guest_state)
3503 return handle_invalid_guest_state(vcpu);
1d5a4d9b 3504
1439442c
SY		 3505 /* Access CR3 don't cause VMExit in paging mode, so we need
3506 * to sync with guest real CR3. */
6de4f3ad 3507 if (enable_ept && is_paging(vcpu))
1439442c 3508 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
1439442c 3509
29bd8a78 3510 if (unlikely(vmx->fail)) {
851ba692
AK		 3511 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3512 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 3513 = vmcs_read32(VM_INSTRUCTION_ERROR);
3514 return 0;
3515 }
6aa8b732 3516
d77c26fc 3517 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 3518 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac
JK		 3519 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3520 exit_reason != EXIT_REASON_TASK_SWITCH))
3521 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3522 "(0x%x) and exit reason is 0x%x\n",
3523 __func__, vectoring_info, exit_reason);
3b86cd99
JK		 3524
3525 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
c4282df9 3526 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 3527 vmx->soft_vnmi_blocked = 0;
3b86cd99 3528 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 3529 vcpu->arch.nmi_pending) {
3b86cd99
JK		 3530 /*
3531 * This CPU don't support us in finding the end of an
3532 * NMI-blocked window if the guest runs with IRQs
3533 * disabled. So we pull the trigger after 1 s of
3534 * futile waiting, but inform the user about this.
3535 */
3536 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3537 "state on VCPU %d after 1 s timeout\n",
3538 __func__, vcpu->vcpu_id);
3539 vmx->soft_vnmi_blocked = 0;
3b86cd99 3540 }
3b86cd99
JK		 3541 }
3542
6aa8b732
AK		 3543 if (exit_reason < kvm_vmx_max_exit_handlers
3544 && kvm_vmx_exit_handlers[exit_reason])
851ba692 3545 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 3546 else {
851ba692
AK		 3547 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3548 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 3549 }
3550 return 0;
3551}
3552
95ba8273 3553static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 3554{
95ba8273 3555 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 3556 vmcs_write32(TPR_THRESHOLD, 0);
3557 return;
3558 }
3559
95ba8273 3560 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 3561}
3562
cf393f75
AK		 3563static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3564{
3565 u32 exit_intr_info;
7b4a25cb 3566 u32 idt_vectoring_info = vmx->idt_vectoring_info;
cf393f75
AK		 3567 bool unblock_nmi;
3568 u8 vector;
668f612f
AK		 3569 int type;
3570 bool idtv_info_valid;
cf393f75
AK		 3571
3572 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
20f65983 3573
a0861c02
AK		 3574 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
3575
3576 /* Handle machine checks before interrupts are enabled */
3577 if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3578 || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3579 && is_machine_check(exit_intr_info)))
3580 kvm_machine_check();
3581
20f65983
GN		 3582 /* We need to handle NMIs before interrupts are enabled */
3583 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
229456fc 3584 (exit_intr_info & INTR_INFO_VALID_MASK))
20f65983 3585 asm("int $2");
20f65983
GN		 3586
3587 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3588
cf393f75
AK		 3589 if (cpu_has_virtual_nmis()) {
3590 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3591 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3592 /*
7b4a25cb 3593 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 3594 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3595 * a guest IRET fault.
7b4a25cb
GN		 3596 * SDM 3: 23.2.2 (September 2008)
3597 * Bit 12 is undefined in any of the following cases:
3598 * If the VM exit sets the valid bit in the IDT-vectoring
3599 * information field.
3600 * If the VM exit is due to a double fault.
cf393f75 3601 */
7b4a25cb
GN		 3602 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3603 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 3604 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3605 GUEST_INTR_STATE_NMI);
3b86cd99
JK		 3606 } else if (unlikely(vmx->soft_vnmi_blocked))
3607 vmx->vnmi_blocked_time +=
3608 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
668f612f 3609
37b96e98
GN		 3610 vmx->vcpu.arch.nmi_injected = false;
3611 kvm_clear_exception_queue(&vmx->vcpu);
3612 kvm_clear_interrupt_queue(&vmx->vcpu);
3613
3614 if (!idtv_info_valid)
3615 return;
3616
668f612f
AK		 3617 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3618 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 3619
64a7ec06 3620 switch (type) {
37b96e98
GN		 3621 case INTR_TYPE_NMI_INTR:
3622 vmx->vcpu.arch.nmi_injected = true;
668f612f 3623 /*
7b4a25cb 3624 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 3625 * Clear bit "block by NMI" before VM entry if a NMI
3626 * delivery faulted.
668f612f 3627 */
37b96e98
GN		 3628 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3629 GUEST_INTR_STATE_NMI);
3630 break;
37b96e98 3631 case INTR_TYPE_SOFT_EXCEPTION:
66fd3f7f
GN		 3632 vmx->vcpu.arch.event_exit_inst_len =
3633 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3634 /* fall through */
3635 case INTR_TYPE_HARD_EXCEPTION:
35920a35 3636 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
37b96e98
GN		 3637 u32 err = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3638 kvm_queue_exception_e(&vmx->vcpu, vector, err);
35920a35
AK		 3639 } else
3640 kvm_queue_exception(&vmx->vcpu, vector);
37b96e98 3641 break;
66fd3f7f
GN		 3642 case INTR_TYPE_SOFT_INTR:
3643 vmx->vcpu.arch.event_exit_inst_len =
3644 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3645 /* fall through */
37b96e98 3646 case INTR_TYPE_EXT_INTR:
66fd3f7f
GN		 3647 kvm_queue_interrupt(&vmx->vcpu, vector,
3648 type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 3649 break;
3650 default:
3651 break;
f7d9238f 3652 }
cf393f75
AK		 3653}
3654
9c8cba37
AK		 3655/*
3656 * Failure to inject an interrupt should give us the information
3657 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
3658 * when fetching the interrupt redirection bitmap in the real-mode
3659 * tss, this doesn't happen. So we do it ourselves.
3660 */
3661static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3662{
3663 vmx->rmode.irq.pending = 0;
5fdbf976 3664 if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
9c8cba37 3665 return;
5fdbf976 3666 kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
9c8cba37
AK		 3667 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3668 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3669 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3670 return;
3671 }
3672 vmx->idt_vectoring_info =
3673 VECTORING_INFO_VALID_MASK
3674 | INTR_TYPE_EXT_INTR
3675 | vmx->rmode.irq.vector;
3676}
3677
c801949d
AK		 3678#ifdef CONFIG_X86_64
3679#define R "r"
3680#define Q "q"
3681#else
3682#define R "e"
3683#define Q "l"
3684#endif
3685
851ba692 3686static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 3687{
a2fa3e9f 3688 struct vcpu_vmx *vmx = to_vmx(vcpu);
e6adf283 3689
3b86cd99
JK		 3690 /* Record the guest's net vcpu time for enforced NMI injections. */
3691 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3692 vmx->entry_time = ktime_get();
3693
80ced186
MG		 3694 /* Don't enter VMX if guest state is invalid, let the exit handler
3695 start emulation until we arrive back to a valid state */
3696 if (vmx->emulation_required && emulate_invalid_guest_state)
a89a8fb9 3697 return;
a89a8fb9 3698
5fdbf976
MT		 3699 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3700 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3701 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3702 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3703
787ff736
GN		 3704 /* When single-stepping over STI and MOV SS, we must clear the
3705 * corresponding interruptibility bits in the guest state. Otherwise
3706 * vmentry fails as it then expects bit 14 (BS) in pending debug
3707 * exceptions being set, but that's not correct for the guest debugging
3708 * case. */
3709 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3710 vmx_set_interrupt_shadow(vcpu, 0);
3711
e6adf283
AK		 3712 /*
3713 * Loading guest fpu may have cleared host cr0.ts
3714 */
3715 vmcs_writel(HOST_CR0, read_cr0());
3716
e8a48342
AK		 3717 if (vcpu->arch.switch_db_regs)
3718 set_debugreg(vcpu->arch.dr6, 6);
42dbaa5a 3719
d77c26fc 3720 asm(
6aa8b732 3721 /* Store host registers */
c801949d
AK		 3722 "push %%"R"dx; push %%"R"bp;"
3723 "push %%"R"cx \n\t"
313dbd49
AK		 3724 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3725 "je 1f \n\t"
3726 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
4ecac3fd 3727 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 3728 "1: \n\t"
d3edefc0
AK		 3729 /* Reload cr2 if changed */
3730 "mov %c[cr2](%0), %%"R"ax \n\t"
3731 "mov %%cr2, %%"R"dx \n\t"
3732 "cmp %%"R"ax, %%"R"dx \n\t"
3733 "je 2f \n\t"
3734 "mov %%"R"ax, %%cr2 \n\t"
3735 "2: \n\t"
6aa8b732 3736 /* Check if vmlaunch of vmresume is needed */
e08aa78a 3737 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 3738 /* Load guest registers. Don't clobber flags. */
c801949d
AK		 3739 "mov %c[rax](%0), %%"R"ax \n\t"
3740 "mov %c[rbx](%0), %%"R"bx \n\t"
3741 "mov %c[rdx](%0), %%"R"dx \n\t"
3742 "mov %c[rsi](%0), %%"R"si \n\t"
3743 "mov %c[rdi](%0), %%"R"di \n\t"
3744 "mov %c[rbp](%0), %%"R"bp \n\t"
05b3e0c2 3745#ifdef CONFIG_X86_64
e08aa78a
AK		 3746 "mov %c[r8](%0), %%r8 \n\t"
3747 "mov %c[r9](%0), %%r9 \n\t"
3748 "mov %c[r10](%0), %%r10 \n\t"
3749 "mov %c[r11](%0), %%r11 \n\t"
3750 "mov %c[r12](%0), %%r12 \n\t"
3751 "mov %c[r13](%0), %%r13 \n\t"
3752 "mov %c[r14](%0), %%r14 \n\t"
3753 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 3754#endif
c801949d
AK		 3755 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3756
6aa8b732 3757 /* Enter guest mode */
cd2276a7 3758 "jne .Llaunched \n\t"
4ecac3fd 3759 __ex(ASM_VMX_VMLAUNCH) "\n\t"
cd2276a7 3760 "jmp .Lkvm_vmx_return \n\t"
4ecac3fd 3761 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
cd2276a7 3762 ".Lkvm_vmx_return: "
6aa8b732 3763 /* Save guest registers, load host registers, keep flags */
c801949d
AK		 3764 "xchg %0, (%%"R"sp) \n\t"
3765 "mov %%"R"ax, %c[rax](%0) \n\t"
3766 "mov %%"R"bx, %c[rbx](%0) \n\t"
3767 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3768 "mov %%"R"dx, %c[rdx](%0) \n\t"
3769 "mov %%"R"si, %c[rsi](%0) \n\t"
3770 "mov %%"R"di, %c[rdi](%0) \n\t"
3771 "mov %%"R"bp, %c[rbp](%0) \n\t"
05b3e0c2 3772#ifdef CONFIG_X86_64
e08aa78a
AK		 3773 "mov %%r8, %c[r8](%0) \n\t"
3774 "mov %%r9, %c[r9](%0) \n\t"
3775 "mov %%r10, %c[r10](%0) \n\t"
3776 "mov %%r11, %c[r11](%0) \n\t"
3777 "mov %%r12, %c[r12](%0) \n\t"
3778 "mov %%r13, %c[r13](%0) \n\t"
3779 "mov %%r14, %c[r14](%0) \n\t"
3780 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 3781#endif
c801949d
AK		 3782 "mov %%cr2, %%"R"ax \n\t"
3783 "mov %%"R"ax, %c[cr2](%0) \n\t"
3784
3785 "pop %%"R"bp; pop %%"R"bp; pop %%"R"dx \n\t"
e08aa78a
AK		 3786 "setbe %c[fail](%0) \n\t"
3787 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3788 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3789 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 3790 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 3791 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3792 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3793 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3794 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3795 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3796 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3797 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 3798#ifdef CONFIG_X86_64
ad312c7c
ZX		 3799 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3800 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3801 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3802 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3803 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3804 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3805 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3806 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 3807#endif
ad312c7c 3808 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
c2036300 3809 : "cc", "memory"
c801949d 3810 , R"bx", R"di", R"si"
c2036300 3811#ifdef CONFIG_X86_64
c2036300
LV		 3812 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3813#endif
3814 );
6aa8b732 3815
6de4f3ad
AK		 3816 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
3817 | (1 << VCPU_EXREG_PDPTR));
5fdbf976
MT		 3818 vcpu->arch.regs_dirty = 0;
3819
e8a48342
AK		 3820 if (vcpu->arch.switch_db_regs)
3821 get_debugreg(vcpu->arch.dr6, 6);
42dbaa5a 3822
1155f76a 3823 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9c8cba37
AK		 3824 if (vmx->rmode.irq.pending)
3825 fixup_rmode_irq(vmx);
1155f76a 3826
d77c26fc 3827 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
15ad7146 3828 vmx->launched = 1;
1b6269db 3829
cf393f75 3830 vmx_complete_interrupts(vmx);
6aa8b732
AK		 3831}
3832
c801949d
AK		 3833#undef R
3834#undef Q
3835
6aa8b732
AK		 3836static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3837{
a2fa3e9f
GH		 3838 struct vcpu_vmx *vmx = to_vmx(vcpu);
3839
3840 if (vmx->vmcs) {
543e4243 3841 vcpu_clear(vmx);
a2fa3e9f
GH		 3842 free_vmcs(vmx->vmcs);
3843 vmx->vmcs = NULL;
6aa8b732
AK		 3844 }
3845}
3846
3847static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3848{
fb3f0f51
RR		 3849 struct vcpu_vmx *vmx = to_vmx(vcpu);
3850
2384d2b3
SY		 3851 spin_lock(&vmx_vpid_lock);
3852 if (vmx->vpid != 0)
3853 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3854 spin_unlock(&vmx_vpid_lock);
6aa8b732 3855 vmx_free_vmcs(vcpu);
fb3f0f51
RR		 3856 kfree(vmx->guest_msrs);
3857 kvm_vcpu_uninit(vcpu);
a4770347 3858 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 3859}
3860
fb3f0f51 3861static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 3862{
fb3f0f51 3863 int err;
c16f862d 3864 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 3865 int cpu;
6aa8b732 3866
a2fa3e9f 3867 if (!vmx)
fb3f0f51
RR		 3868 return ERR_PTR(-ENOMEM);
3869
2384d2b3
SY		 3870 allocate_vpid(vmx);
3871
fb3f0f51
RR		 3872 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3873 if (err)
3874 goto free_vcpu;
965b58a5 3875
a2fa3e9f 3876 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
fb3f0f51
RR		 3877 if (!vmx->guest_msrs) {
3878 err = -ENOMEM;
3879 goto uninit_vcpu;
3880 }
965b58a5 3881
a2fa3e9f
GH		 3882 vmx->vmcs = alloc_vmcs();
3883 if (!vmx->vmcs)
fb3f0f51 3884 goto free_msrs;
a2fa3e9f
GH		 3885
3886 vmcs_clear(vmx->vmcs);
3887
15ad7146
AK		 3888 cpu = get_cpu();
3889 vmx_vcpu_load(&vmx->vcpu, cpu);
8b9cf98c 3890 err = vmx_vcpu_setup(vmx);
fb3f0f51 3891 vmx_vcpu_put(&vmx->vcpu);
15ad7146 3892 put_cpu();
fb3f0f51
RR		 3893 if (err)
3894 goto free_vmcs;
5e4a0b3c
MT		 3895 if (vm_need_virtualize_apic_accesses(kvm))
3896 if (alloc_apic_access_page(kvm) != 0)
3897 goto free_vmcs;
fb3f0f51 3898
b927a3ce
SY		 3899 if (enable_ept) {
3900 if (!kvm->arch.ept_identity_map_addr)
3901 kvm->arch.ept_identity_map_addr =
3902 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
b7ebfb05
SY		 3903 if (alloc_identity_pagetable(kvm) != 0)
3904 goto free_vmcs;
b927a3ce 3905 }
b7ebfb05 3906
fb3f0f51
RR		 3907 return &vmx->vcpu;
3908
3909free_vmcs:
3910 free_vmcs(vmx->vmcs);
3911free_msrs:
fb3f0f51
RR		 3912 kfree(vmx->guest_msrs);
3913uninit_vcpu:
3914 kvm_vcpu_uninit(&vmx->vcpu);
3915free_vcpu:
a4770347 3916 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 3917 return ERR_PTR(err);
6aa8b732
AK		 3918}
3919
002c7f7c
YS		 3920static void __init vmx_check_processor_compat(void *rtn)
3921{
3922 struct vmcs_config vmcs_conf;
3923
3924 *(int *)rtn = 0;
3925 if (setup_vmcs_config(&vmcs_conf) < 0)
3926 *(int *)rtn = -EIO;
3927 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
3928 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
3929 smp_processor_id());
3930 *(int *)rtn = -EIO;
3931 }
3932}
3933
67253af5
SY		 3934static int get_ept_level(void)
3935{
3936 return VMX_EPT_DEFAULT_GAW + 1;
3937}
3938
4b12f0de 3939static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 3940{
4b12f0de
SY		 3941 u64 ret;
3942
522c68c4
SY		 3943 /* For VT-d and EPT combination
3944 * 1. MMIO: always map as UC
3945 * 2. EPT with VT-d:
3946 * a. VT-d without snooping control feature: can't guarantee the
3947 * result, try to trust guest.
3948 * b. VT-d with snooping control feature: snooping control feature of
3949 * VT-d engine can guarantee the cache correctness. Just set it
3950 * to WB to keep consistent with host. So the same as item 3.
3951 * 3. EPT without VT-d: always map as WB and set IGMT=1 to keep
3952 * consistent with host MTRR
3953 */
4b12f0de
SY		 3954 if (is_mmio)
3955 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 3956 else if (vcpu->kvm->arch.iommu_domain &&
3957 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
3958 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
3959 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 3960 else
522c68c4
SY		 3961 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
3962 | VMX_EPT_IGMT_BIT;
4b12f0de
SY		 3963
3964 return ret;
64d4d521
SY		 3965}
3966
229456fc
MT		 3967static const struct trace_print_flags vmx_exit_reasons_str[] = {
3968 { EXIT_REASON_EXCEPTION_NMI, "exception" },
3969 { EXIT_REASON_EXTERNAL_INTERRUPT, "ext_irq" },
3970 { EXIT_REASON_TRIPLE_FAULT, "triple_fault" },
3971 { EXIT_REASON_NMI_WINDOW, "nmi_window" },
3972 { EXIT_REASON_IO_INSTRUCTION, "io_instruction" },
3973 { EXIT_REASON_CR_ACCESS, "cr_access" },
3974 { EXIT_REASON_DR_ACCESS, "dr_access" },
3975 { EXIT_REASON_CPUID, "cpuid" },
3976 { EXIT_REASON_MSR_READ, "rdmsr" },
3977 { EXIT_REASON_MSR_WRITE, "wrmsr" },
3978 { EXIT_REASON_PENDING_INTERRUPT, "interrupt_window" },
3979 { EXIT_REASON_HLT, "halt" },
3980 { EXIT_REASON_INVLPG, "invlpg" },
3981 { EXIT_REASON_VMCALL, "hypercall" },
3982 { EXIT_REASON_TPR_BELOW_THRESHOLD, "tpr_below_thres" },
3983 { EXIT_REASON_APIC_ACCESS, "apic_access" },
3984 { EXIT_REASON_WBINVD, "wbinvd" },
3985 { EXIT_REASON_TASK_SWITCH, "task_switch" },
3986 { EXIT_REASON_EPT_VIOLATION, "ept_violation" },
3987 { -1, NULL }
3988};
3989
344f414f
JR		 3990static bool vmx_gb_page_enable(void)
3991{
3992 return false;
3993}
3994
cbdd1bea 3995static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 3996 .cpu_has_kvm_support = cpu_has_kvm_support,
3997 .disabled_by_bios = vmx_disabled_by_bios,
3998 .hardware_setup = hardware_setup,
3999 .hardware_unsetup = hardware_unsetup,
002c7f7c 4000 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 4001 .hardware_enable = hardware_enable,
4002 .hardware_disable = hardware_disable,
04547156 4003 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 4004
4005 .vcpu_create = vmx_create_vcpu,
4006 .vcpu_free = vmx_free_vcpu,
04d2cc77 4007 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 4008
04d2cc77 4009 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 4010 .vcpu_load = vmx_vcpu_load,
4011 .vcpu_put = vmx_vcpu_put,
4012
4013 .set_guest_debug = set_guest_debug,
4014 .get_msr = vmx_get_msr,
4015 .set_msr = vmx_set_msr,
4016 .get_segment_base = vmx_get_segment_base,
4017 .get_segment = vmx_get_segment,
4018 .set_segment = vmx_set_segment,
2e4d2653 4019 .get_cpl = vmx_get_cpl,
6aa8b732 4020 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
25c4c276 4021 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 4022 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 4023 .set_cr3 = vmx_set_cr3,
4024 .set_cr4 = vmx_set_cr4,
6aa8b732 4025 .set_efer = vmx_set_efer,
6aa8b732
AK		 4026 .get_idt = vmx_get_idt,
4027 .set_idt = vmx_set_idt,
4028 .get_gdt = vmx_get_gdt,
4029 .set_gdt = vmx_set_gdt,
5fdbf976 4030 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 4031 .get_rflags = vmx_get_rflags,
4032 .set_rflags = vmx_set_rflags,
4033
4034 .tlb_flush = vmx_flush_tlb,
6aa8b732 4035
6aa8b732 4036 .run = vmx_vcpu_run,
6062d012 4037 .handle_exit = vmx_handle_exit,
6aa8b732 4038 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 4039 .set_interrupt_shadow = vmx_set_interrupt_shadow,
4040 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 4041 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 4042 .set_irq = vmx_inject_irq,
95ba8273 4043 .set_nmi = vmx_inject_nmi,
298101da 4044 .queue_exception = vmx_queue_exception,
78646121 4045 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 4046 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 4047 .get_nmi_mask = vmx_get_nmi_mask,
4048 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 4049 .enable_nmi_window = enable_nmi_window,
4050 .enable_irq_window = enable_irq_window,
4051 .update_cr8_intercept = update_cr8_intercept,
95ba8273 4052
cbc94022 4053 .set_tss_addr = vmx_set_tss_addr,
67253af5 4054 .get_tdp_level = get_ept_level,
4b12f0de 4055 .get_mt_mask = vmx_get_mt_mask,
229456fc
MT		 4056
4057 .exit_reasons_str = vmx_exit_reasons_str,
344f414f 4058 .gb_page_enable = vmx_gb_page_enable,
6aa8b732
AK		 4059};
4060
4061static int __init vmx_init(void)
4062{
26bb0981
AK		 4063 int r, i;
4064
4065 rdmsrl_safe(MSR_EFER, &host_efer);
4066
4067 for (i = 0; i < NR_VMX_MSR; ++i)
4068 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 4069
3e7c73e9 4070 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 4071 if (!vmx_io_bitmap_a)
4072 return -ENOMEM;
4073
3e7c73e9 4074 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 4075 if (!vmx_io_bitmap_b) {
4076 r = -ENOMEM;
4077 goto out;
4078 }
4079
5897297b
AK		 4080 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4081 if (!vmx_msr_bitmap_legacy) {
25c5f225
SY		 4082 r = -ENOMEM;
4083 goto out1;
4084 }
4085
5897297b
AK		 4086 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4087 if (!vmx_msr_bitmap_longmode) {
4088 r = -ENOMEM;
4089 goto out2;
4090 }
4091
fdef3ad1
HQ		 4092 /*
4093 * Allow direct access to the PC debug port (it is often used for I/O
4094 * delays, but the vmexits simply slow things down).
4095 */
3e7c73e9
AK		 4096 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4097 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 4098
3e7c73e9 4099 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 4100
5897297b
AK		 4101 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4102 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 4103
2384d2b3
SY		 4104 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4105
cb498ea2 4106 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 4107 if (r)
5897297b 4108 goto out3;
25c5f225 4109
5897297b
AK		 4110 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4111 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4112 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4113 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4114 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4115 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
fdef3ad1 4116
089d034e 4117 if (enable_ept) {
1439442c 4118 bypass_guest_pf = 0;
5fdbcb9d 4119 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
2aaf69dc 4120 VMX_EPT_WRITABLE_MASK);
534e38b4 4121 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4b12f0de 4122 VMX_EPT_EXECUTABLE_MASK);
5fdbcb9d
SY		 4123 kvm_enable_tdp();
4124 } else
4125 kvm_disable_tdp();
1439442c 4126
c7addb90
AK		 4127 if (bypass_guest_pf)
4128 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4129
fdef3ad1
HQ		 4130 return 0;
4131
5897297b
AK		 4132out3:
4133 free_page((unsigned long)vmx_msr_bitmap_longmode);
25c5f225 4134out2:
5897297b 4135 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 4136out1:
3e7c73e9 4137 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 4138out:
3e7c73e9 4139 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 4140 return r;
6aa8b732
AK		 4141}
4142
4143static void __exit vmx_exit(void)
4144{
5897297b
AK		 4145 free_page((unsigned long)vmx_msr_bitmap_legacy);
4146 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 4147 free_page((unsigned long)vmx_io_bitmap_b);
4148 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 4149
cb498ea2 4150 kvm_exit();
6aa8b732
AK		 4151}
4152
4153module_init(vmx_init)
4154module_exit(vmx_exit)
kernel source for telekom puls (alcatel/mediatek)