Commit | Line | Data |
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b6c02715 JR |
1 | /* |
2 | * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. | |
3 | * Author: Joerg Roedel <joerg.roedel@amd.com> | |
4 | * Leo Duran <leo.duran@amd.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | ||
20 | #include <linux/pci.h> | |
21 | #include <linux/gfp.h> | |
22 | #include <linux/bitops.h> | |
7f26508b | 23 | #include <linux/debugfs.h> |
b6c02715 | 24 | #include <linux/scatterlist.h> |
51491367 | 25 | #include <linux/dma-mapping.h> |
b6c02715 | 26 | #include <linux/iommu-helper.h> |
c156e347 | 27 | #include <linux/iommu.h> |
b6c02715 | 28 | #include <asm/proto.h> |
46a7fa27 | 29 | #include <asm/iommu.h> |
1d9b16d1 | 30 | #include <asm/gart.h> |
b6c02715 | 31 | #include <asm/amd_iommu_types.h> |
c6da992e | 32 | #include <asm/amd_iommu.h> |
b6c02715 JR |
33 | |
34 | #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28)) | |
35 | ||
136f78a1 JR |
36 | #define EXIT_LOOP_COUNT 10000000 |
37 | ||
b6c02715 JR |
38 | static DEFINE_RWLOCK(amd_iommu_devtable_lock); |
39 | ||
bd60b735 JR |
40 | /* A list of preallocated protection domains */ |
41 | static LIST_HEAD(iommu_pd_list); | |
42 | static DEFINE_SPINLOCK(iommu_pd_list_lock); | |
43 | ||
26961efe JR |
44 | #ifdef CONFIG_IOMMU_API |
45 | static struct iommu_ops amd_iommu_ops; | |
46 | #endif | |
47 | ||
431b2a20 JR |
48 | /* |
49 | * general struct to manage commands send to an IOMMU | |
50 | */ | |
d6449536 | 51 | struct iommu_cmd { |
b6c02715 JR |
52 | u32 data[4]; |
53 | }; | |
54 | ||
bd0e5211 JR |
55 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
56 | struct unity_map_entry *e); | |
e275a2a0 | 57 | static struct dma_ops_domain *find_protection_domain(u16 devid); |
8bda3092 JR |
58 | static u64* alloc_pte(struct protection_domain *dom, |
59 | unsigned long address, u64 | |
60 | **pte_page, gfp_t gfp); | |
00cd122a JR |
61 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, |
62 | unsigned long start_page, | |
63 | unsigned int pages); | |
bd0e5211 | 64 | |
c1eee67b CW |
65 | #ifndef BUS_NOTIFY_UNBOUND_DRIVER |
66 | #define BUS_NOTIFY_UNBOUND_DRIVER 0x0005 | |
67 | #endif | |
68 | ||
7f26508b JR |
69 | #ifdef CONFIG_AMD_IOMMU_STATS |
70 | ||
71 | /* | |
72 | * Initialization code for statistics collection | |
73 | */ | |
74 | ||
da49f6df | 75 | DECLARE_STATS_COUNTER(compl_wait); |
0f2a86f2 | 76 | DECLARE_STATS_COUNTER(cnt_map_single); |
146a6917 | 77 | DECLARE_STATS_COUNTER(cnt_unmap_single); |
d03f067a | 78 | DECLARE_STATS_COUNTER(cnt_map_sg); |
55877a6b | 79 | DECLARE_STATS_COUNTER(cnt_unmap_sg); |
c8f0fb36 | 80 | DECLARE_STATS_COUNTER(cnt_alloc_coherent); |
5d31ee7e | 81 | DECLARE_STATS_COUNTER(cnt_free_coherent); |
c1858976 | 82 | DECLARE_STATS_COUNTER(cross_page); |
f57d98ae | 83 | DECLARE_STATS_COUNTER(domain_flush_single); |
18811f55 | 84 | DECLARE_STATS_COUNTER(domain_flush_all); |
5774f7c5 | 85 | DECLARE_STATS_COUNTER(alloced_io_mem); |
8ecaf8f1 | 86 | DECLARE_STATS_COUNTER(total_map_requests); |
da49f6df | 87 | |
7f26508b JR |
88 | static struct dentry *stats_dir; |
89 | static struct dentry *de_isolate; | |
90 | static struct dentry *de_fflush; | |
91 | ||
92 | static void amd_iommu_stats_add(struct __iommu_counter *cnt) | |
93 | { | |
94 | if (stats_dir == NULL) | |
95 | return; | |
96 | ||
97 | cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir, | |
98 | &cnt->value); | |
99 | } | |
100 | ||
101 | static void amd_iommu_stats_init(void) | |
102 | { | |
103 | stats_dir = debugfs_create_dir("amd-iommu", NULL); | |
104 | if (stats_dir == NULL) | |
105 | return; | |
106 | ||
107 | de_isolate = debugfs_create_bool("isolation", 0444, stats_dir, | |
108 | (u32 *)&amd_iommu_isolate); | |
109 | ||
110 | de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir, | |
111 | (u32 *)&amd_iommu_unmap_flush); | |
da49f6df JR |
112 | |
113 | amd_iommu_stats_add(&compl_wait); | |
0f2a86f2 | 114 | amd_iommu_stats_add(&cnt_map_single); |
146a6917 | 115 | amd_iommu_stats_add(&cnt_unmap_single); |
d03f067a | 116 | amd_iommu_stats_add(&cnt_map_sg); |
55877a6b | 117 | amd_iommu_stats_add(&cnt_unmap_sg); |
c8f0fb36 | 118 | amd_iommu_stats_add(&cnt_alloc_coherent); |
5d31ee7e | 119 | amd_iommu_stats_add(&cnt_free_coherent); |
c1858976 | 120 | amd_iommu_stats_add(&cross_page); |
f57d98ae | 121 | amd_iommu_stats_add(&domain_flush_single); |
18811f55 | 122 | amd_iommu_stats_add(&domain_flush_all); |
5774f7c5 | 123 | amd_iommu_stats_add(&alloced_io_mem); |
8ecaf8f1 | 124 | amd_iommu_stats_add(&total_map_requests); |
7f26508b JR |
125 | } |
126 | ||
127 | #endif | |
128 | ||
431b2a20 | 129 | /* returns !0 if the IOMMU is caching non-present entries in its TLB */ |
4da70b9e JR |
130 | static int iommu_has_npcache(struct amd_iommu *iommu) |
131 | { | |
ae9b9403 | 132 | return iommu->cap & (1UL << IOMMU_CAP_NPCACHE); |
4da70b9e JR |
133 | } |
134 | ||
a80dc3e0 JR |
135 | /**************************************************************************** |
136 | * | |
137 | * Interrupt handling functions | |
138 | * | |
139 | ****************************************************************************/ | |
140 | ||
e3e59876 JR |
141 | static void dump_dte_entry(u16 devid) |
142 | { | |
143 | int i; | |
144 | ||
145 | for (i = 0; i < 8; ++i) | |
146 | pr_err("AMD-Vi: DTE[%d]: %08x\n", i, | |
147 | amd_iommu_dev_table[devid].data[i]); | |
148 | } | |
149 | ||
90008ee4 JR |
150 | static void iommu_print_event(void *__evt) |
151 | { | |
152 | u32 *event = __evt; | |
153 | int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK; | |
154 | int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK; | |
155 | int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK; | |
156 | int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK; | |
157 | u64 address = (u64)(((u64)event[3]) << 32) | event[2]; | |
158 | ||
159 | printk(KERN_ERR "AMD IOMMU: Event logged ["); | |
160 | ||
161 | switch (type) { | |
162 | case EVENT_TYPE_ILL_DEV: | |
163 | printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x " | |
164 | "address=0x%016llx flags=0x%04x]\n", | |
165 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
166 | address, flags); | |
e3e59876 | 167 | dump_dte_entry(devid); |
90008ee4 JR |
168 | break; |
169 | case EVENT_TYPE_IO_FAULT: | |
170 | printk("IO_PAGE_FAULT device=%02x:%02x.%x " | |
171 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
172 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
173 | domid, address, flags); | |
174 | break; | |
175 | case EVENT_TYPE_DEV_TAB_ERR: | |
176 | printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
177 | "address=0x%016llx flags=0x%04x]\n", | |
178 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
179 | address, flags); | |
180 | break; | |
181 | case EVENT_TYPE_PAGE_TAB_ERR: | |
182 | printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x " | |
183 | "domain=0x%04x address=0x%016llx flags=0x%04x]\n", | |
184 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
185 | domid, address, flags); | |
186 | break; | |
187 | case EVENT_TYPE_ILL_CMD: | |
188 | printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address); | |
189 | break; | |
190 | case EVENT_TYPE_CMD_HARD_ERR: | |
191 | printk("COMMAND_HARDWARE_ERROR address=0x%016llx " | |
192 | "flags=0x%04x]\n", address, flags); | |
193 | break; | |
194 | case EVENT_TYPE_IOTLB_INV_TO: | |
195 | printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x " | |
196 | "address=0x%016llx]\n", | |
197 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
198 | address); | |
199 | break; | |
200 | case EVENT_TYPE_INV_DEV_REQ: | |
201 | printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x " | |
202 | "address=0x%016llx flags=0x%04x]\n", | |
203 | PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid), | |
204 | address, flags); | |
205 | break; | |
206 | default: | |
207 | printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type); | |
208 | } | |
209 | } | |
210 | ||
211 | static void iommu_poll_events(struct amd_iommu *iommu) | |
212 | { | |
213 | u32 head, tail; | |
214 | unsigned long flags; | |
215 | ||
216 | spin_lock_irqsave(&iommu->lock, flags); | |
217 | ||
218 | head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
219 | tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); | |
220 | ||
221 | while (head != tail) { | |
222 | iommu_print_event(iommu->evt_buf + head); | |
223 | head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size; | |
224 | } | |
225 | ||
226 | writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); | |
227 | ||
228 | spin_unlock_irqrestore(&iommu->lock, flags); | |
229 | } | |
230 | ||
a80dc3e0 JR |
231 | irqreturn_t amd_iommu_int_handler(int irq, void *data) |
232 | { | |
90008ee4 JR |
233 | struct amd_iommu *iommu; |
234 | ||
3bd22172 | 235 | for_each_iommu(iommu) |
90008ee4 JR |
236 | iommu_poll_events(iommu); |
237 | ||
238 | return IRQ_HANDLED; | |
a80dc3e0 JR |
239 | } |
240 | ||
431b2a20 JR |
241 | /**************************************************************************** |
242 | * | |
243 | * IOMMU command queuing functions | |
244 | * | |
245 | ****************************************************************************/ | |
246 | ||
247 | /* | |
248 | * Writes the command to the IOMMUs command buffer and informs the | |
249 | * hardware about the new command. Must be called with iommu->lock held. | |
250 | */ | |
d6449536 | 251 | static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec JR |
252 | { |
253 | u32 tail, head; | |
254 | u8 *target; | |
255 | ||
256 | tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
8a7c5ef3 | 257 | target = iommu->cmd_buf + tail; |
a19ae1ec JR |
258 | memcpy_toio(target, cmd, sizeof(*cmd)); |
259 | tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size; | |
260 | head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); | |
261 | if (tail == head) | |
262 | return -ENOMEM; | |
263 | writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); | |
264 | ||
265 | return 0; | |
266 | } | |
267 | ||
431b2a20 JR |
268 | /* |
269 | * General queuing function for commands. Takes iommu->lock and calls | |
270 | * __iommu_queue_command(). | |
271 | */ | |
d6449536 | 272 | static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd) |
a19ae1ec JR |
273 | { |
274 | unsigned long flags; | |
275 | int ret; | |
276 | ||
277 | spin_lock_irqsave(&iommu->lock, flags); | |
278 | ret = __iommu_queue_command(iommu, cmd); | |
09ee17eb | 279 | if (!ret) |
0cfd7aa9 | 280 | iommu->need_sync = true; |
a19ae1ec JR |
281 | spin_unlock_irqrestore(&iommu->lock, flags); |
282 | ||
283 | return ret; | |
284 | } | |
285 | ||
8d201968 JR |
286 | /* |
287 | * This function waits until an IOMMU has completed a completion | |
288 | * wait command | |
289 | */ | |
290 | static void __iommu_wait_for_completion(struct amd_iommu *iommu) | |
291 | { | |
292 | int ready = 0; | |
293 | unsigned status = 0; | |
294 | unsigned long i = 0; | |
295 | ||
da49f6df JR |
296 | INC_STATS_COUNTER(compl_wait); |
297 | ||
8d201968 JR |
298 | while (!ready && (i < EXIT_LOOP_COUNT)) { |
299 | ++i; | |
300 | /* wait for the bit to become one */ | |
301 | status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); | |
302 | ready = status & MMIO_STATUS_COM_WAIT_INT_MASK; | |
303 | } | |
304 | ||
305 | /* set bit back to zero */ | |
306 | status &= ~MMIO_STATUS_COM_WAIT_INT_MASK; | |
307 | writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET); | |
308 | ||
309 | if (unlikely(i == EXIT_LOOP_COUNT)) | |
310 | panic("AMD IOMMU: Completion wait loop failed\n"); | |
311 | } | |
312 | ||
313 | /* | |
314 | * This function queues a completion wait command into the command | |
315 | * buffer of an IOMMU | |
316 | */ | |
317 | static int __iommu_completion_wait(struct amd_iommu *iommu) | |
318 | { | |
319 | struct iommu_cmd cmd; | |
320 | ||
321 | memset(&cmd, 0, sizeof(cmd)); | |
322 | cmd.data[0] = CMD_COMPL_WAIT_INT_MASK; | |
323 | CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT); | |
324 | ||
325 | return __iommu_queue_command(iommu, &cmd); | |
326 | } | |
327 | ||
431b2a20 JR |
328 | /* |
329 | * This function is called whenever we need to ensure that the IOMMU has | |
330 | * completed execution of all commands we sent. It sends a | |
331 | * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs | |
332 | * us about that by writing a value to a physical address we pass with | |
333 | * the command. | |
334 | */ | |
a19ae1ec JR |
335 | static int iommu_completion_wait(struct amd_iommu *iommu) |
336 | { | |
8d201968 JR |
337 | int ret = 0; |
338 | unsigned long flags; | |
a19ae1ec | 339 | |
7e4f88da JR |
340 | spin_lock_irqsave(&iommu->lock, flags); |
341 | ||
09ee17eb JR |
342 | if (!iommu->need_sync) |
343 | goto out; | |
344 | ||
8d201968 | 345 | ret = __iommu_completion_wait(iommu); |
09ee17eb | 346 | |
0cfd7aa9 | 347 | iommu->need_sync = false; |
a19ae1ec JR |
348 | |
349 | if (ret) | |
7e4f88da | 350 | goto out; |
a19ae1ec | 351 | |
8d201968 | 352 | __iommu_wait_for_completion(iommu); |
84df8175 | 353 | |
7e4f88da JR |
354 | out: |
355 | spin_unlock_irqrestore(&iommu->lock, flags); | |
a19ae1ec JR |
356 | |
357 | return 0; | |
358 | } | |
359 | ||
431b2a20 JR |
360 | /* |
361 | * Command send function for invalidating a device table entry | |
362 | */ | |
a19ae1ec JR |
363 | static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid) |
364 | { | |
d6449536 | 365 | struct iommu_cmd cmd; |
ee2fa743 | 366 | int ret; |
a19ae1ec JR |
367 | |
368 | BUG_ON(iommu == NULL); | |
369 | ||
370 | memset(&cmd, 0, sizeof(cmd)); | |
371 | CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY); | |
372 | cmd.data[0] = devid; | |
373 | ||
ee2fa743 JR |
374 | ret = iommu_queue_command(iommu, &cmd); |
375 | ||
ee2fa743 | 376 | return ret; |
a19ae1ec JR |
377 | } |
378 | ||
237b6f33 JR |
379 | static void __iommu_build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address, |
380 | u16 domid, int pde, int s) | |
381 | { | |
382 | memset(cmd, 0, sizeof(*cmd)); | |
383 | address &= PAGE_MASK; | |
384 | CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES); | |
385 | cmd->data[1] |= domid; | |
386 | cmd->data[2] = lower_32_bits(address); | |
387 | cmd->data[3] = upper_32_bits(address); | |
388 | if (s) /* size bit - we flush more than one 4kb page */ | |
389 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK; | |
390 | if (pde) /* PDE bit - we wan't flush everything not only the PTEs */ | |
391 | cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK; | |
392 | } | |
393 | ||
431b2a20 JR |
394 | /* |
395 | * Generic command send function for invalidaing TLB entries | |
396 | */ | |
a19ae1ec JR |
397 | static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu, |
398 | u64 address, u16 domid, int pde, int s) | |
399 | { | |
d6449536 | 400 | struct iommu_cmd cmd; |
ee2fa743 | 401 | int ret; |
a19ae1ec | 402 | |
237b6f33 | 403 | __iommu_build_inv_iommu_pages(&cmd, address, domid, pde, s); |
a19ae1ec | 404 | |
ee2fa743 JR |
405 | ret = iommu_queue_command(iommu, &cmd); |
406 | ||
ee2fa743 | 407 | return ret; |
a19ae1ec JR |
408 | } |
409 | ||
431b2a20 JR |
410 | /* |
411 | * TLB invalidation function which is called from the mapping functions. | |
412 | * It invalidates a single PTE if the range to flush is within a single | |
413 | * page. Otherwise it flushes the whole TLB of the IOMMU. | |
414 | */ | |
a19ae1ec JR |
415 | static int iommu_flush_pages(struct amd_iommu *iommu, u16 domid, |
416 | u64 address, size_t size) | |
417 | { | |
999ba417 | 418 | int s = 0; |
e3c449f5 | 419 | unsigned pages = iommu_num_pages(address, size, PAGE_SIZE); |
a19ae1ec JR |
420 | |
421 | address &= PAGE_MASK; | |
422 | ||
999ba417 JR |
423 | if (pages > 1) { |
424 | /* | |
425 | * If we have to flush more than one page, flush all | |
426 | * TLB entries for this domain | |
427 | */ | |
428 | address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
429 | s = 1; | |
a19ae1ec JR |
430 | } |
431 | ||
999ba417 JR |
432 | iommu_queue_inv_iommu_pages(iommu, address, domid, 0, s); |
433 | ||
a19ae1ec JR |
434 | return 0; |
435 | } | |
b6c02715 | 436 | |
1c655773 JR |
437 | /* Flush the whole IO/TLB for a given protection domain */ |
438 | static void iommu_flush_tlb(struct amd_iommu *iommu, u16 domid) | |
439 | { | |
440 | u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
441 | ||
f57d98ae JR |
442 | INC_STATS_COUNTER(domain_flush_single); |
443 | ||
1c655773 JR |
444 | iommu_queue_inv_iommu_pages(iommu, address, domid, 0, 1); |
445 | } | |
446 | ||
42a49f96 CW |
447 | /* Flush the whole IO/TLB for a given protection domain - including PDE */ |
448 | static void iommu_flush_tlb_pde(struct amd_iommu *iommu, u16 domid) | |
449 | { | |
450 | u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS; | |
451 | ||
452 | INC_STATS_COUNTER(domain_flush_single); | |
453 | ||
454 | iommu_queue_inv_iommu_pages(iommu, address, domid, 1, 1); | |
455 | } | |
456 | ||
43f49609 JR |
457 | /* |
458 | * This function is used to flush the IO/TLB for a given protection domain | |
459 | * on every IOMMU in the system | |
460 | */ | |
461 | static void iommu_flush_domain(u16 domid) | |
462 | { | |
463 | unsigned long flags; | |
464 | struct amd_iommu *iommu; | |
465 | struct iommu_cmd cmd; | |
466 | ||
18811f55 JR |
467 | INC_STATS_COUNTER(domain_flush_all); |
468 | ||
43f49609 JR |
469 | __iommu_build_inv_iommu_pages(&cmd, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, |
470 | domid, 1, 1); | |
471 | ||
3bd22172 | 472 | for_each_iommu(iommu) { |
43f49609 JR |
473 | spin_lock_irqsave(&iommu->lock, flags); |
474 | __iommu_queue_command(iommu, &cmd); | |
475 | __iommu_completion_wait(iommu); | |
476 | __iommu_wait_for_completion(iommu); | |
477 | spin_unlock_irqrestore(&iommu->lock, flags); | |
478 | } | |
479 | } | |
43f49609 | 480 | |
bfd1be18 JR |
481 | void amd_iommu_flush_all_domains(void) |
482 | { | |
483 | int i; | |
484 | ||
485 | for (i = 1; i < MAX_DOMAIN_ID; ++i) { | |
486 | if (!test_bit(i, amd_iommu_pd_alloc_bitmap)) | |
487 | continue; | |
488 | iommu_flush_domain(i); | |
489 | } | |
490 | } | |
491 | ||
7d7a110c JR |
492 | void amd_iommu_flush_all_devices(void) |
493 | { | |
494 | struct amd_iommu *iommu; | |
495 | int i; | |
496 | ||
497 | for (i = 0; i <= amd_iommu_last_bdf; ++i) { | |
498 | if (amd_iommu_pd_table[i] == NULL) | |
499 | continue; | |
500 | ||
501 | iommu = amd_iommu_rlookup_table[i]; | |
502 | if (!iommu) | |
503 | continue; | |
504 | ||
505 | iommu_queue_inv_dev_entry(iommu, i); | |
506 | iommu_completion_wait(iommu); | |
507 | } | |
508 | } | |
509 | ||
431b2a20 JR |
510 | /**************************************************************************** |
511 | * | |
512 | * The functions below are used the create the page table mappings for | |
513 | * unity mapped regions. | |
514 | * | |
515 | ****************************************************************************/ | |
516 | ||
517 | /* | |
518 | * Generic mapping functions. It maps a physical address into a DMA | |
519 | * address space. It allocates the page table pages if necessary. | |
520 | * In the future it can be extended to a generic mapping function | |
521 | * supporting all features of AMD IOMMU page tables like level skipping | |
522 | * and full 64 bit address spaces. | |
523 | */ | |
38e817fe JR |
524 | static int iommu_map_page(struct protection_domain *dom, |
525 | unsigned long bus_addr, | |
526 | unsigned long phys_addr, | |
527 | int prot) | |
bd0e5211 | 528 | { |
8bda3092 | 529 | u64 __pte, *pte; |
bd0e5211 JR |
530 | |
531 | bus_addr = PAGE_ALIGN(bus_addr); | |
bb9d4ff8 | 532 | phys_addr = PAGE_ALIGN(phys_addr); |
bd0e5211 JR |
533 | |
534 | /* only support 512GB address spaces for now */ | |
535 | if (bus_addr > IOMMU_MAP_SIZE_L3 || !(prot & IOMMU_PROT_MASK)) | |
536 | return -EINVAL; | |
537 | ||
8bda3092 | 538 | pte = alloc_pte(dom, bus_addr, NULL, GFP_KERNEL); |
bd0e5211 JR |
539 | |
540 | if (IOMMU_PTE_PRESENT(*pte)) | |
541 | return -EBUSY; | |
542 | ||
543 | __pte = phys_addr | IOMMU_PTE_P; | |
544 | if (prot & IOMMU_PROT_IR) | |
545 | __pte |= IOMMU_PTE_IR; | |
546 | if (prot & IOMMU_PROT_IW) | |
547 | __pte |= IOMMU_PTE_IW; | |
548 | ||
549 | *pte = __pte; | |
550 | ||
551 | return 0; | |
552 | } | |
553 | ||
eb74ff6c JR |
554 | static void iommu_unmap_page(struct protection_domain *dom, |
555 | unsigned long bus_addr) | |
556 | { | |
557 | u64 *pte; | |
558 | ||
559 | pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)]; | |
560 | ||
561 | if (!IOMMU_PTE_PRESENT(*pte)) | |
562 | return; | |
563 | ||
564 | pte = IOMMU_PTE_PAGE(*pte); | |
565 | pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)]; | |
566 | ||
567 | if (!IOMMU_PTE_PRESENT(*pte)) | |
568 | return; | |
569 | ||
570 | pte = IOMMU_PTE_PAGE(*pte); | |
571 | pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)]; | |
572 | ||
573 | *pte = 0; | |
574 | } | |
eb74ff6c | 575 | |
431b2a20 JR |
576 | /* |
577 | * This function checks if a specific unity mapping entry is needed for | |
578 | * this specific IOMMU. | |
579 | */ | |
bd0e5211 JR |
580 | static int iommu_for_unity_map(struct amd_iommu *iommu, |
581 | struct unity_map_entry *entry) | |
582 | { | |
583 | u16 bdf, i; | |
584 | ||
585 | for (i = entry->devid_start; i <= entry->devid_end; ++i) { | |
586 | bdf = amd_iommu_alias_table[i]; | |
587 | if (amd_iommu_rlookup_table[bdf] == iommu) | |
588 | return 1; | |
589 | } | |
590 | ||
591 | return 0; | |
592 | } | |
593 | ||
431b2a20 JR |
594 | /* |
595 | * Init the unity mappings for a specific IOMMU in the system | |
596 | * | |
597 | * Basically iterates over all unity mapping entries and applies them to | |
598 | * the default domain DMA of that IOMMU if necessary. | |
599 | */ | |
bd0e5211 JR |
600 | static int iommu_init_unity_mappings(struct amd_iommu *iommu) |
601 | { | |
602 | struct unity_map_entry *entry; | |
603 | int ret; | |
604 | ||
605 | list_for_each_entry(entry, &amd_iommu_unity_map, list) { | |
606 | if (!iommu_for_unity_map(iommu, entry)) | |
607 | continue; | |
608 | ret = dma_ops_unity_map(iommu->default_dom, entry); | |
609 | if (ret) | |
610 | return ret; | |
611 | } | |
612 | ||
613 | return 0; | |
614 | } | |
615 | ||
431b2a20 JR |
616 | /* |
617 | * This function actually applies the mapping to the page table of the | |
618 | * dma_ops domain. | |
619 | */ | |
bd0e5211 JR |
620 | static int dma_ops_unity_map(struct dma_ops_domain *dma_dom, |
621 | struct unity_map_entry *e) | |
622 | { | |
623 | u64 addr; | |
624 | int ret; | |
625 | ||
626 | for (addr = e->address_start; addr < e->address_end; | |
627 | addr += PAGE_SIZE) { | |
38e817fe | 628 | ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot); |
bd0e5211 JR |
629 | if (ret) |
630 | return ret; | |
631 | /* | |
632 | * if unity mapping is in aperture range mark the page | |
633 | * as allocated in the aperture | |
634 | */ | |
635 | if (addr < dma_dom->aperture_size) | |
c3239567 | 636 | __set_bit(addr >> PAGE_SHIFT, |
384de729 | 637 | dma_dom->aperture[0]->bitmap); |
bd0e5211 JR |
638 | } |
639 | ||
640 | return 0; | |
641 | } | |
642 | ||
431b2a20 JR |
643 | /* |
644 | * Inits the unity mappings required for a specific device | |
645 | */ | |
bd0e5211 JR |
646 | static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom, |
647 | u16 devid) | |
648 | { | |
649 | struct unity_map_entry *e; | |
650 | int ret; | |
651 | ||
652 | list_for_each_entry(e, &amd_iommu_unity_map, list) { | |
653 | if (!(devid >= e->devid_start && devid <= e->devid_end)) | |
654 | continue; | |
655 | ret = dma_ops_unity_map(dma_dom, e); | |
656 | if (ret) | |
657 | return ret; | |
658 | } | |
659 | ||
660 | return 0; | |
661 | } | |
662 | ||
431b2a20 JR |
663 | /**************************************************************************** |
664 | * | |
665 | * The next functions belong to the address allocator for the dma_ops | |
666 | * interface functions. They work like the allocators in the other IOMMU | |
667 | * drivers. Its basically a bitmap which marks the allocated pages in | |
668 | * the aperture. Maybe it could be enhanced in the future to a more | |
669 | * efficient allocator. | |
670 | * | |
671 | ****************************************************************************/ | |
d3086444 | 672 | |
431b2a20 | 673 | /* |
384de729 | 674 | * The address allocator core functions. |
431b2a20 JR |
675 | * |
676 | * called with domain->lock held | |
677 | */ | |
384de729 | 678 | |
00cd122a JR |
679 | /* |
680 | * This function checks if there is a PTE for a given dma address. If | |
681 | * there is one, it returns the pointer to it. | |
682 | */ | |
683 | static u64* fetch_pte(struct protection_domain *domain, | |
684 | unsigned long address) | |
685 | { | |
686 | u64 *pte; | |
687 | ||
688 | pte = &domain->pt_root[IOMMU_PTE_L2_INDEX(address)]; | |
689 | ||
690 | if (!IOMMU_PTE_PRESENT(*pte)) | |
691 | return NULL; | |
692 | ||
693 | pte = IOMMU_PTE_PAGE(*pte); | |
694 | pte = &pte[IOMMU_PTE_L1_INDEX(address)]; | |
695 | ||
696 | if (!IOMMU_PTE_PRESENT(*pte)) | |
697 | return NULL; | |
698 | ||
699 | pte = IOMMU_PTE_PAGE(*pte); | |
700 | pte = &pte[IOMMU_PTE_L0_INDEX(address)]; | |
701 | ||
702 | return pte; | |
703 | } | |
704 | ||
9cabe89b JR |
705 | /* |
706 | * This function is used to add a new aperture range to an existing | |
707 | * aperture in case of dma_ops domain allocation or address allocation | |
708 | * failure. | |
709 | */ | |
00cd122a JR |
710 | static int alloc_new_range(struct amd_iommu *iommu, |
711 | struct dma_ops_domain *dma_dom, | |
9cabe89b JR |
712 | bool populate, gfp_t gfp) |
713 | { | |
714 | int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT; | |
00cd122a | 715 | int i; |
9cabe89b | 716 | |
f5e9705c JR |
717 | #ifdef CONFIG_IOMMU_STRESS |
718 | populate = false; | |
719 | #endif | |
720 | ||
9cabe89b JR |
721 | if (index >= APERTURE_MAX_RANGES) |
722 | return -ENOMEM; | |
723 | ||
724 | dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp); | |
725 | if (!dma_dom->aperture[index]) | |
726 | return -ENOMEM; | |
727 | ||
728 | dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp); | |
729 | if (!dma_dom->aperture[index]->bitmap) | |
730 | goto out_free; | |
731 | ||
732 | dma_dom->aperture[index]->offset = dma_dom->aperture_size; | |
733 | ||
734 | if (populate) { | |
735 | unsigned long address = dma_dom->aperture_size; | |
736 | int i, num_ptes = APERTURE_RANGE_PAGES / 512; | |
737 | u64 *pte, *pte_page; | |
738 | ||
739 | for (i = 0; i < num_ptes; ++i) { | |
740 | pte = alloc_pte(&dma_dom->domain, address, | |
741 | &pte_page, gfp); | |
742 | if (!pte) | |
743 | goto out_free; | |
744 | ||
745 | dma_dom->aperture[index]->pte_pages[i] = pte_page; | |
746 | ||
747 | address += APERTURE_RANGE_SIZE / 64; | |
748 | } | |
749 | } | |
750 | ||
751 | dma_dom->aperture_size += APERTURE_RANGE_SIZE; | |
752 | ||
00cd122a JR |
753 | /* Intialize the exclusion range if necessary */ |
754 | if (iommu->exclusion_start && | |
755 | iommu->exclusion_start >= dma_dom->aperture[index]->offset && | |
756 | iommu->exclusion_start < dma_dom->aperture_size) { | |
757 | unsigned long startpage = iommu->exclusion_start >> PAGE_SHIFT; | |
758 | int pages = iommu_num_pages(iommu->exclusion_start, | |
759 | iommu->exclusion_length, | |
760 | PAGE_SIZE); | |
761 | dma_ops_reserve_addresses(dma_dom, startpage, pages); | |
762 | } | |
763 | ||
764 | /* | |
765 | * Check for areas already mapped as present in the new aperture | |
766 | * range and mark those pages as reserved in the allocator. Such | |
767 | * mappings may already exist as a result of requested unity | |
768 | * mappings for devices. | |
769 | */ | |
770 | for (i = dma_dom->aperture[index]->offset; | |
771 | i < dma_dom->aperture_size; | |
772 | i += PAGE_SIZE) { | |
773 | u64 *pte = fetch_pte(&dma_dom->domain, i); | |
774 | if (!pte || !IOMMU_PTE_PRESENT(*pte)) | |
775 | continue; | |
776 | ||
777 | dma_ops_reserve_addresses(dma_dom, i << PAGE_SHIFT, 1); | |
778 | } | |
779 | ||
9cabe89b JR |
780 | return 0; |
781 | ||
782 | out_free: | |
783 | free_page((unsigned long)dma_dom->aperture[index]->bitmap); | |
784 | ||
785 | kfree(dma_dom->aperture[index]); | |
786 | dma_dom->aperture[index] = NULL; | |
787 | ||
788 | return -ENOMEM; | |
789 | } | |
790 | ||
384de729 JR |
791 | static unsigned long dma_ops_area_alloc(struct device *dev, |
792 | struct dma_ops_domain *dom, | |
793 | unsigned int pages, | |
794 | unsigned long align_mask, | |
795 | u64 dma_mask, | |
796 | unsigned long start) | |
797 | { | |
803b8cb4 | 798 | unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE; |
384de729 JR |
799 | int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT; |
800 | int i = start >> APERTURE_RANGE_SHIFT; | |
801 | unsigned long boundary_size; | |
802 | unsigned long address = -1; | |
803 | unsigned long limit; | |
804 | ||
803b8cb4 JR |
805 | next_bit >>= PAGE_SHIFT; |
806 | ||
384de729 JR |
807 | boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, |
808 | PAGE_SIZE) >> PAGE_SHIFT; | |
809 | ||
810 | for (;i < max_index; ++i) { | |
811 | unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT; | |
812 | ||
813 | if (dom->aperture[i]->offset >= dma_mask) | |
814 | break; | |
815 | ||
816 | limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset, | |
817 | dma_mask >> PAGE_SHIFT); | |
818 | ||
819 | address = iommu_area_alloc(dom->aperture[i]->bitmap, | |
820 | limit, next_bit, pages, 0, | |
821 | boundary_size, align_mask); | |
822 | if (address != -1) { | |
823 | address = dom->aperture[i]->offset + | |
824 | (address << PAGE_SHIFT); | |
803b8cb4 | 825 | dom->next_address = address + (pages << PAGE_SHIFT); |
384de729 JR |
826 | break; |
827 | } | |
828 | ||
829 | next_bit = 0; | |
830 | } | |
831 | ||
832 | return address; | |
833 | } | |
834 | ||
d3086444 JR |
835 | static unsigned long dma_ops_alloc_addresses(struct device *dev, |
836 | struct dma_ops_domain *dom, | |
6d4f343f | 837 | unsigned int pages, |
832a90c3 JR |
838 | unsigned long align_mask, |
839 | u64 dma_mask) | |
d3086444 | 840 | { |
d3086444 | 841 | unsigned long address; |
d3086444 | 842 | |
fe16f088 JR |
843 | #ifdef CONFIG_IOMMU_STRESS |
844 | dom->next_address = 0; | |
845 | dom->need_flush = true; | |
846 | #endif | |
d3086444 | 847 | |
384de729 | 848 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
803b8cb4 | 849 | dma_mask, dom->next_address); |
d3086444 | 850 | |
1c655773 | 851 | if (address == -1) { |
803b8cb4 | 852 | dom->next_address = 0; |
384de729 JR |
853 | address = dma_ops_area_alloc(dev, dom, pages, align_mask, |
854 | dma_mask, 0); | |
1c655773 JR |
855 | dom->need_flush = true; |
856 | } | |
d3086444 | 857 | |
384de729 | 858 | if (unlikely(address == -1)) |
d3086444 JR |
859 | address = bad_dma_address; |
860 | ||
861 | WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size); | |
862 | ||
863 | return address; | |
864 | } | |
865 | ||
431b2a20 JR |
866 | /* |
867 | * The address free function. | |
868 | * | |
869 | * called with domain->lock held | |
870 | */ | |
d3086444 JR |
871 | static void dma_ops_free_addresses(struct dma_ops_domain *dom, |
872 | unsigned long address, | |
873 | unsigned int pages) | |
874 | { | |
384de729 JR |
875 | unsigned i = address >> APERTURE_RANGE_SHIFT; |
876 | struct aperture_range *range = dom->aperture[i]; | |
80be308d | 877 | |
384de729 JR |
878 | BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL); |
879 | ||
47bccd6b JR |
880 | #ifdef CONFIG_IOMMU_STRESS |
881 | if (i < 4) | |
882 | return; | |
883 | #endif | |
80be308d | 884 | |
803b8cb4 | 885 | if (address >= dom->next_address) |
80be308d | 886 | dom->need_flush = true; |
384de729 JR |
887 | |
888 | address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT; | |
803b8cb4 | 889 | |
384de729 JR |
890 | iommu_area_free(range->bitmap, address, pages); |
891 | ||
d3086444 JR |
892 | } |
893 | ||
431b2a20 JR |
894 | /**************************************************************************** |
895 | * | |
896 | * The next functions belong to the domain allocation. A domain is | |
897 | * allocated for every IOMMU as the default domain. If device isolation | |
898 | * is enabled, every device get its own domain. The most important thing | |
899 | * about domains is the page table mapping the DMA address space they | |
900 | * contain. | |
901 | * | |
902 | ****************************************************************************/ | |
903 | ||
ec487d1a JR |
904 | static u16 domain_id_alloc(void) |
905 | { | |
906 | unsigned long flags; | |
907 | int id; | |
908 | ||
909 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
910 | id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID); | |
911 | BUG_ON(id == 0); | |
912 | if (id > 0 && id < MAX_DOMAIN_ID) | |
913 | __set_bit(id, amd_iommu_pd_alloc_bitmap); | |
914 | else | |
915 | id = 0; | |
916 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
917 | ||
918 | return id; | |
919 | } | |
920 | ||
a2acfb75 JR |
921 | static void domain_id_free(int id) |
922 | { | |
923 | unsigned long flags; | |
924 | ||
925 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
926 | if (id > 0 && id < MAX_DOMAIN_ID) | |
927 | __clear_bit(id, amd_iommu_pd_alloc_bitmap); | |
928 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
929 | } | |
a2acfb75 | 930 | |
431b2a20 JR |
931 | /* |
932 | * Used to reserve address ranges in the aperture (e.g. for exclusion | |
933 | * ranges. | |
934 | */ | |
ec487d1a JR |
935 | static void dma_ops_reserve_addresses(struct dma_ops_domain *dom, |
936 | unsigned long start_page, | |
937 | unsigned int pages) | |
938 | { | |
384de729 | 939 | unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT; |
ec487d1a JR |
940 | |
941 | if (start_page + pages > last_page) | |
942 | pages = last_page - start_page; | |
943 | ||
384de729 JR |
944 | for (i = start_page; i < start_page + pages; ++i) { |
945 | int index = i / APERTURE_RANGE_PAGES; | |
946 | int page = i % APERTURE_RANGE_PAGES; | |
947 | __set_bit(page, dom->aperture[index]->bitmap); | |
948 | } | |
ec487d1a JR |
949 | } |
950 | ||
86db2e5d | 951 | static void free_pagetable(struct protection_domain *domain) |
ec487d1a JR |
952 | { |
953 | int i, j; | |
954 | u64 *p1, *p2, *p3; | |
955 | ||
86db2e5d | 956 | p1 = domain->pt_root; |
ec487d1a JR |
957 | |
958 | if (!p1) | |
959 | return; | |
960 | ||
961 | for (i = 0; i < 512; ++i) { | |
962 | if (!IOMMU_PTE_PRESENT(p1[i])) | |
963 | continue; | |
964 | ||
965 | p2 = IOMMU_PTE_PAGE(p1[i]); | |
3cc3d84b | 966 | for (j = 0; j < 512; ++j) { |
ec487d1a JR |
967 | if (!IOMMU_PTE_PRESENT(p2[j])) |
968 | continue; | |
969 | p3 = IOMMU_PTE_PAGE(p2[j]); | |
970 | free_page((unsigned long)p3); | |
971 | } | |
972 | ||
973 | free_page((unsigned long)p2); | |
974 | } | |
975 | ||
976 | free_page((unsigned long)p1); | |
86db2e5d JR |
977 | |
978 | domain->pt_root = NULL; | |
ec487d1a JR |
979 | } |
980 | ||
431b2a20 JR |
981 | /* |
982 | * Free a domain, only used if something went wrong in the | |
983 | * allocation path and we need to free an already allocated page table | |
984 | */ | |
ec487d1a JR |
985 | static void dma_ops_domain_free(struct dma_ops_domain *dom) |
986 | { | |
384de729 JR |
987 | int i; |
988 | ||
ec487d1a JR |
989 | if (!dom) |
990 | return; | |
991 | ||
86db2e5d | 992 | free_pagetable(&dom->domain); |
ec487d1a | 993 | |
384de729 JR |
994 | for (i = 0; i < APERTURE_MAX_RANGES; ++i) { |
995 | if (!dom->aperture[i]) | |
996 | continue; | |
997 | free_page((unsigned long)dom->aperture[i]->bitmap); | |
998 | kfree(dom->aperture[i]); | |
999 | } | |
ec487d1a JR |
1000 | |
1001 | kfree(dom); | |
1002 | } | |
1003 | ||
431b2a20 JR |
1004 | /* |
1005 | * Allocates a new protection domain usable for the dma_ops functions. | |
1006 | * It also intializes the page table and the address allocator data | |
1007 | * structures required for the dma_ops interface | |
1008 | */ | |
d9cfed92 | 1009 | static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu) |
ec487d1a JR |
1010 | { |
1011 | struct dma_ops_domain *dma_dom; | |
ec487d1a JR |
1012 | |
1013 | dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL); | |
1014 | if (!dma_dom) | |
1015 | return NULL; | |
1016 | ||
1017 | spin_lock_init(&dma_dom->domain.lock); | |
1018 | ||
1019 | dma_dom->domain.id = domain_id_alloc(); | |
1020 | if (dma_dom->domain.id == 0) | |
1021 | goto free_dma_dom; | |
1022 | dma_dom->domain.mode = PAGE_MODE_3_LEVEL; | |
1023 | dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); | |
9fdb19d6 | 1024 | dma_dom->domain.flags = PD_DMA_OPS_MASK; |
ec487d1a JR |
1025 | dma_dom->domain.priv = dma_dom; |
1026 | if (!dma_dom->domain.pt_root) | |
1027 | goto free_dma_dom; | |
ec487d1a | 1028 | |
1c655773 | 1029 | dma_dom->need_flush = false; |
bd60b735 | 1030 | dma_dom->target_dev = 0xffff; |
1c655773 | 1031 | |
00cd122a | 1032 | if (alloc_new_range(iommu, dma_dom, true, GFP_KERNEL)) |
ec487d1a | 1033 | goto free_dma_dom; |
ec487d1a | 1034 | |
431b2a20 | 1035 | /* |
ec487d1a JR |
1036 | * mark the first page as allocated so we never return 0 as |
1037 | * a valid dma-address. So we can use 0 as error value | |
431b2a20 | 1038 | */ |
384de729 | 1039 | dma_dom->aperture[0]->bitmap[0] = 1; |
803b8cb4 | 1040 | dma_dom->next_address = 0; |
ec487d1a | 1041 | |
ec487d1a JR |
1042 | |
1043 | return dma_dom; | |
1044 | ||
1045 | free_dma_dom: | |
1046 | dma_ops_domain_free(dma_dom); | |
1047 | ||
1048 | return NULL; | |
1049 | } | |
1050 | ||
5b28df6f JR |
1051 | /* |
1052 | * little helper function to check whether a given protection domain is a | |
1053 | * dma_ops domain | |
1054 | */ | |
1055 | static bool dma_ops_domain(struct protection_domain *domain) | |
1056 | { | |
1057 | return domain->flags & PD_DMA_OPS_MASK; | |
1058 | } | |
1059 | ||
431b2a20 JR |
1060 | /* |
1061 | * Find out the protection domain structure for a given PCI device. This | |
1062 | * will give us the pointer to the page table root for example. | |
1063 | */ | |
b20ac0d4 JR |
1064 | static struct protection_domain *domain_for_device(u16 devid) |
1065 | { | |
1066 | struct protection_domain *dom; | |
1067 | unsigned long flags; | |
1068 | ||
1069 | read_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1070 | dom = amd_iommu_pd_table[devid]; | |
1071 | read_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1072 | ||
1073 | return dom; | |
1074 | } | |
1075 | ||
431b2a20 JR |
1076 | /* |
1077 | * If a device is not yet associated with a domain, this function does | |
1078 | * assigns it visible for the hardware | |
1079 | */ | |
f1179dc0 JR |
1080 | static void attach_device(struct amd_iommu *iommu, |
1081 | struct protection_domain *domain, | |
1082 | u16 devid) | |
b20ac0d4 JR |
1083 | { |
1084 | unsigned long flags; | |
b20ac0d4 JR |
1085 | u64 pte_root = virt_to_phys(domain->pt_root); |
1086 | ||
863c74eb JR |
1087 | domain->dev_cnt += 1; |
1088 | ||
38ddf41b JR |
1089 | pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK) |
1090 | << DEV_ENTRY_MODE_SHIFT; | |
1091 | pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV; | |
b20ac0d4 JR |
1092 | |
1093 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
38ddf41b JR |
1094 | amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root); |
1095 | amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root); | |
b20ac0d4 JR |
1096 | amd_iommu_dev_table[devid].data[2] = domain->id; |
1097 | ||
1098 | amd_iommu_pd_table[devid] = domain; | |
1099 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1100 | ||
42a49f96 CW |
1101 | /* |
1102 | * We might boot into a crash-kernel here. The crashed kernel | |
1103 | * left the caches in the IOMMU dirty. So we have to flush | |
1104 | * here to evict all dirty stuff. | |
1105 | */ | |
b20ac0d4 | 1106 | iommu_queue_inv_dev_entry(iommu, devid); |
42a49f96 | 1107 | iommu_flush_tlb_pde(iommu, domain->id); |
b20ac0d4 JR |
1108 | } |
1109 | ||
355bf553 JR |
1110 | /* |
1111 | * Removes a device from a protection domain (unlocked) | |
1112 | */ | |
1113 | static void __detach_device(struct protection_domain *domain, u16 devid) | |
1114 | { | |
1115 | ||
1116 | /* lock domain */ | |
1117 | spin_lock(&domain->lock); | |
1118 | ||
1119 | /* remove domain from the lookup table */ | |
1120 | amd_iommu_pd_table[devid] = NULL; | |
1121 | ||
1122 | /* remove entry from the device table seen by the hardware */ | |
1123 | amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV; | |
1124 | amd_iommu_dev_table[devid].data[1] = 0; | |
1125 | amd_iommu_dev_table[devid].data[2] = 0; | |
1126 | ||
1127 | /* decrease reference counter */ | |
1128 | domain->dev_cnt -= 1; | |
1129 | ||
1130 | /* ready */ | |
1131 | spin_unlock(&domain->lock); | |
1132 | } | |
1133 | ||
1134 | /* | |
1135 | * Removes a device from a protection domain (with devtable_lock held) | |
1136 | */ | |
1137 | static void detach_device(struct protection_domain *domain, u16 devid) | |
1138 | { | |
1139 | unsigned long flags; | |
1140 | ||
1141 | /* lock device table */ | |
1142 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1143 | __detach_device(domain, devid); | |
1144 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1145 | } | |
e275a2a0 JR |
1146 | |
1147 | static int device_change_notifier(struct notifier_block *nb, | |
1148 | unsigned long action, void *data) | |
1149 | { | |
1150 | struct device *dev = data; | |
1151 | struct pci_dev *pdev = to_pci_dev(dev); | |
1152 | u16 devid = calc_devid(pdev->bus->number, pdev->devfn); | |
1153 | struct protection_domain *domain; | |
1154 | struct dma_ops_domain *dma_domain; | |
1155 | struct amd_iommu *iommu; | |
1ac4cbbc | 1156 | unsigned long flags; |
e275a2a0 JR |
1157 | |
1158 | if (devid > amd_iommu_last_bdf) | |
1159 | goto out; | |
1160 | ||
1161 | devid = amd_iommu_alias_table[devid]; | |
1162 | ||
1163 | iommu = amd_iommu_rlookup_table[devid]; | |
1164 | if (iommu == NULL) | |
1165 | goto out; | |
1166 | ||
1167 | domain = domain_for_device(devid); | |
1168 | ||
1169 | if (domain && !dma_ops_domain(domain)) | |
1170 | WARN_ONCE(1, "AMD IOMMU WARNING: device %s already bound " | |
1171 | "to a non-dma-ops domain\n", dev_name(dev)); | |
1172 | ||
1173 | switch (action) { | |
c1eee67b | 1174 | case BUS_NOTIFY_UNBOUND_DRIVER: |
e275a2a0 JR |
1175 | if (!domain) |
1176 | goto out; | |
1177 | detach_device(domain, devid); | |
1ac4cbbc JR |
1178 | break; |
1179 | case BUS_NOTIFY_ADD_DEVICE: | |
1180 | /* allocate a protection domain if a device is added */ | |
1181 | dma_domain = find_protection_domain(devid); | |
1182 | if (dma_domain) | |
1183 | goto out; | |
d9cfed92 | 1184 | dma_domain = dma_ops_domain_alloc(iommu); |
1ac4cbbc JR |
1185 | if (!dma_domain) |
1186 | goto out; | |
1187 | dma_domain->target_dev = devid; | |
1188 | ||
1189 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
1190 | list_add_tail(&dma_domain->list, &iommu_pd_list); | |
1191 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
1192 | ||
e275a2a0 JR |
1193 | break; |
1194 | default: | |
1195 | goto out; | |
1196 | } | |
1197 | ||
1198 | iommu_queue_inv_dev_entry(iommu, devid); | |
1199 | iommu_completion_wait(iommu); | |
1200 | ||
1201 | out: | |
1202 | return 0; | |
1203 | } | |
1204 | ||
b25ae679 | 1205 | static struct notifier_block device_nb = { |
e275a2a0 JR |
1206 | .notifier_call = device_change_notifier, |
1207 | }; | |
355bf553 | 1208 | |
431b2a20 JR |
1209 | /***************************************************************************** |
1210 | * | |
1211 | * The next functions belong to the dma_ops mapping/unmapping code. | |
1212 | * | |
1213 | *****************************************************************************/ | |
1214 | ||
dbcc112e JR |
1215 | /* |
1216 | * This function checks if the driver got a valid device from the caller to | |
1217 | * avoid dereferencing invalid pointers. | |
1218 | */ | |
1219 | static bool check_device(struct device *dev) | |
1220 | { | |
1221 | if (!dev || !dev->dma_mask) | |
1222 | return false; | |
1223 | ||
1224 | return true; | |
1225 | } | |
1226 | ||
bd60b735 JR |
1227 | /* |
1228 | * In this function the list of preallocated protection domains is traversed to | |
1229 | * find the domain for a specific device | |
1230 | */ | |
1231 | static struct dma_ops_domain *find_protection_domain(u16 devid) | |
1232 | { | |
1233 | struct dma_ops_domain *entry, *ret = NULL; | |
1234 | unsigned long flags; | |
1235 | ||
1236 | if (list_empty(&iommu_pd_list)) | |
1237 | return NULL; | |
1238 | ||
1239 | spin_lock_irqsave(&iommu_pd_list_lock, flags); | |
1240 | ||
1241 | list_for_each_entry(entry, &iommu_pd_list, list) { | |
1242 | if (entry->target_dev == devid) { | |
1243 | ret = entry; | |
bd60b735 JR |
1244 | break; |
1245 | } | |
1246 | } | |
1247 | ||
1248 | spin_unlock_irqrestore(&iommu_pd_list_lock, flags); | |
1249 | ||
1250 | return ret; | |
1251 | } | |
1252 | ||
431b2a20 JR |
1253 | /* |
1254 | * In the dma_ops path we only have the struct device. This function | |
1255 | * finds the corresponding IOMMU, the protection domain and the | |
1256 | * requestor id for a given device. | |
1257 | * If the device is not yet associated with a domain this is also done | |
1258 | * in this function. | |
1259 | */ | |
b20ac0d4 JR |
1260 | static int get_device_resources(struct device *dev, |
1261 | struct amd_iommu **iommu, | |
1262 | struct protection_domain **domain, | |
1263 | u16 *bdf) | |
1264 | { | |
1265 | struct dma_ops_domain *dma_dom; | |
1266 | struct pci_dev *pcidev; | |
1267 | u16 _bdf; | |
1268 | ||
dbcc112e JR |
1269 | *iommu = NULL; |
1270 | *domain = NULL; | |
1271 | *bdf = 0xffff; | |
1272 | ||
1273 | if (dev->bus != &pci_bus_type) | |
1274 | return 0; | |
b20ac0d4 JR |
1275 | |
1276 | pcidev = to_pci_dev(dev); | |
d591b0a3 | 1277 | _bdf = calc_devid(pcidev->bus->number, pcidev->devfn); |
b20ac0d4 | 1278 | |
431b2a20 | 1279 | /* device not translated by any IOMMU in the system? */ |
dbcc112e | 1280 | if (_bdf > amd_iommu_last_bdf) |
b20ac0d4 | 1281 | return 0; |
b20ac0d4 JR |
1282 | |
1283 | *bdf = amd_iommu_alias_table[_bdf]; | |
1284 | ||
1285 | *iommu = amd_iommu_rlookup_table[*bdf]; | |
1286 | if (*iommu == NULL) | |
1287 | return 0; | |
b20ac0d4 JR |
1288 | *domain = domain_for_device(*bdf); |
1289 | if (*domain == NULL) { | |
bd60b735 JR |
1290 | dma_dom = find_protection_domain(*bdf); |
1291 | if (!dma_dom) | |
1292 | dma_dom = (*iommu)->default_dom; | |
b20ac0d4 | 1293 | *domain = &dma_dom->domain; |
f1179dc0 | 1294 | attach_device(*iommu, *domain, *bdf); |
e9a22a13 JR |
1295 | DUMP_printk("Using protection domain %d for device %s\n", |
1296 | (*domain)->id, dev_name(dev)); | |
b20ac0d4 JR |
1297 | } |
1298 | ||
f91ba190 | 1299 | if (domain_for_device(_bdf) == NULL) |
f1179dc0 | 1300 | attach_device(*iommu, *domain, _bdf); |
f91ba190 | 1301 | |
b20ac0d4 JR |
1302 | return 1; |
1303 | } | |
1304 | ||
8bda3092 JR |
1305 | /* |
1306 | * If the pte_page is not yet allocated this function is called | |
1307 | */ | |
1308 | static u64* alloc_pte(struct protection_domain *dom, | |
1309 | unsigned long address, u64 **pte_page, gfp_t gfp) | |
1310 | { | |
1311 | u64 *pte, *page; | |
1312 | ||
1313 | pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(address)]; | |
1314 | ||
1315 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
1316 | page = (u64 *)get_zeroed_page(gfp); | |
1317 | if (!page) | |
1318 | return NULL; | |
1319 | *pte = IOMMU_L2_PDE(virt_to_phys(page)); | |
1320 | } | |
1321 | ||
1322 | pte = IOMMU_PTE_PAGE(*pte); | |
1323 | pte = &pte[IOMMU_PTE_L1_INDEX(address)]; | |
1324 | ||
1325 | if (!IOMMU_PTE_PRESENT(*pte)) { | |
1326 | page = (u64 *)get_zeroed_page(gfp); | |
1327 | if (!page) | |
1328 | return NULL; | |
1329 | *pte = IOMMU_L1_PDE(virt_to_phys(page)); | |
1330 | } | |
1331 | ||
1332 | pte = IOMMU_PTE_PAGE(*pte); | |
1333 | ||
1334 | if (pte_page) | |
1335 | *pte_page = pte; | |
1336 | ||
1337 | pte = &pte[IOMMU_PTE_L0_INDEX(address)]; | |
1338 | ||
1339 | return pte; | |
1340 | } | |
1341 | ||
1342 | /* | |
1343 | * This function fetches the PTE for a given address in the aperture | |
1344 | */ | |
1345 | static u64* dma_ops_get_pte(struct dma_ops_domain *dom, | |
1346 | unsigned long address) | |
1347 | { | |
384de729 | 1348 | struct aperture_range *aperture; |
8bda3092 JR |
1349 | u64 *pte, *pte_page; |
1350 | ||
384de729 JR |
1351 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
1352 | if (!aperture) | |
1353 | return NULL; | |
1354 | ||
1355 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
8bda3092 JR |
1356 | if (!pte) { |
1357 | pte = alloc_pte(&dom->domain, address, &pte_page, GFP_ATOMIC); | |
384de729 JR |
1358 | aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page; |
1359 | } else | |
1360 | pte += IOMMU_PTE_L0_INDEX(address); | |
8bda3092 JR |
1361 | |
1362 | return pte; | |
1363 | } | |
1364 | ||
431b2a20 JR |
1365 | /* |
1366 | * This is the generic map function. It maps one 4kb page at paddr to | |
1367 | * the given address in the DMA address space for the domain. | |
1368 | */ | |
cb76c322 JR |
1369 | static dma_addr_t dma_ops_domain_map(struct amd_iommu *iommu, |
1370 | struct dma_ops_domain *dom, | |
1371 | unsigned long address, | |
1372 | phys_addr_t paddr, | |
1373 | int direction) | |
1374 | { | |
1375 | u64 *pte, __pte; | |
1376 | ||
1377 | WARN_ON(address > dom->aperture_size); | |
1378 | ||
1379 | paddr &= PAGE_MASK; | |
1380 | ||
8bda3092 | 1381 | pte = dma_ops_get_pte(dom, address); |
53812c11 JR |
1382 | if (!pte) |
1383 | return bad_dma_address; | |
cb76c322 JR |
1384 | |
1385 | __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC; | |
1386 | ||
1387 | if (direction == DMA_TO_DEVICE) | |
1388 | __pte |= IOMMU_PTE_IR; | |
1389 | else if (direction == DMA_FROM_DEVICE) | |
1390 | __pte |= IOMMU_PTE_IW; | |
1391 | else if (direction == DMA_BIDIRECTIONAL) | |
1392 | __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW; | |
1393 | ||
1394 | WARN_ON(*pte); | |
1395 | ||
1396 | *pte = __pte; | |
1397 | ||
1398 | return (dma_addr_t)address; | |
1399 | } | |
1400 | ||
431b2a20 JR |
1401 | /* |
1402 | * The generic unmapping function for on page in the DMA address space. | |
1403 | */ | |
cb76c322 JR |
1404 | static void dma_ops_domain_unmap(struct amd_iommu *iommu, |
1405 | struct dma_ops_domain *dom, | |
1406 | unsigned long address) | |
1407 | { | |
384de729 | 1408 | struct aperture_range *aperture; |
cb76c322 JR |
1409 | u64 *pte; |
1410 | ||
1411 | if (address >= dom->aperture_size) | |
1412 | return; | |
1413 | ||
384de729 JR |
1414 | aperture = dom->aperture[APERTURE_RANGE_INDEX(address)]; |
1415 | if (!aperture) | |
1416 | return; | |
1417 | ||
1418 | pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)]; | |
1419 | if (!pte) | |
1420 | return; | |
cb76c322 | 1421 | |
cb76c322 JR |
1422 | pte += IOMMU_PTE_L0_INDEX(address); |
1423 | ||
1424 | WARN_ON(!*pte); | |
1425 | ||
1426 | *pte = 0ULL; | |
1427 | } | |
1428 | ||
431b2a20 JR |
1429 | /* |
1430 | * This function contains common code for mapping of a physically | |
24f81160 JR |
1431 | * contiguous memory region into DMA address space. It is used by all |
1432 | * mapping functions provided with this IOMMU driver. | |
431b2a20 JR |
1433 | * Must be called with the domain lock held. |
1434 | */ | |
cb76c322 JR |
1435 | static dma_addr_t __map_single(struct device *dev, |
1436 | struct amd_iommu *iommu, | |
1437 | struct dma_ops_domain *dma_dom, | |
1438 | phys_addr_t paddr, | |
1439 | size_t size, | |
6d4f343f | 1440 | int dir, |
832a90c3 JR |
1441 | bool align, |
1442 | u64 dma_mask) | |
cb76c322 JR |
1443 | { |
1444 | dma_addr_t offset = paddr & ~PAGE_MASK; | |
53812c11 | 1445 | dma_addr_t address, start, ret; |
cb76c322 | 1446 | unsigned int pages; |
6d4f343f | 1447 | unsigned long align_mask = 0; |
cb76c322 JR |
1448 | int i; |
1449 | ||
e3c449f5 | 1450 | pages = iommu_num_pages(paddr, size, PAGE_SIZE); |
cb76c322 JR |
1451 | paddr &= PAGE_MASK; |
1452 | ||
8ecaf8f1 JR |
1453 | INC_STATS_COUNTER(total_map_requests); |
1454 | ||
c1858976 JR |
1455 | if (pages > 1) |
1456 | INC_STATS_COUNTER(cross_page); | |
1457 | ||
6d4f343f JR |
1458 | if (align) |
1459 | align_mask = (1UL << get_order(size)) - 1; | |
1460 | ||
11b83888 | 1461 | retry: |
832a90c3 JR |
1462 | address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask, |
1463 | dma_mask); | |
11b83888 JR |
1464 | if (unlikely(address == bad_dma_address)) { |
1465 | /* | |
1466 | * setting next_address here will let the address | |
1467 | * allocator only scan the new allocated range in the | |
1468 | * first run. This is a small optimization. | |
1469 | */ | |
1470 | dma_dom->next_address = dma_dom->aperture_size; | |
1471 | ||
1472 | if (alloc_new_range(iommu, dma_dom, false, GFP_ATOMIC)) | |
1473 | goto out; | |
1474 | ||
1475 | /* | |
1476 | * aperture was sucessfully enlarged by 128 MB, try | |
1477 | * allocation again | |
1478 | */ | |
1479 | goto retry; | |
1480 | } | |
cb76c322 JR |
1481 | |
1482 | start = address; | |
1483 | for (i = 0; i < pages; ++i) { | |
53812c11 JR |
1484 | ret = dma_ops_domain_map(iommu, dma_dom, start, paddr, dir); |
1485 | if (ret == bad_dma_address) | |
1486 | goto out_unmap; | |
1487 | ||
cb76c322 JR |
1488 | paddr += PAGE_SIZE; |
1489 | start += PAGE_SIZE; | |
1490 | } | |
1491 | address += offset; | |
1492 | ||
5774f7c5 JR |
1493 | ADD_STATS_COUNTER(alloced_io_mem, size); |
1494 | ||
afa9fdc2 | 1495 | if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) { |
1c655773 JR |
1496 | iommu_flush_tlb(iommu, dma_dom->domain.id); |
1497 | dma_dom->need_flush = false; | |
1498 | } else if (unlikely(iommu_has_npcache(iommu))) | |
270cab24 JR |
1499 | iommu_flush_pages(iommu, dma_dom->domain.id, address, size); |
1500 | ||
cb76c322 JR |
1501 | out: |
1502 | return address; | |
53812c11 JR |
1503 | |
1504 | out_unmap: | |
1505 | ||
1506 | for (--i; i >= 0; --i) { | |
1507 | start -= PAGE_SIZE; | |
1508 | dma_ops_domain_unmap(iommu, dma_dom, start); | |
1509 | } | |
1510 | ||
1511 | dma_ops_free_addresses(dma_dom, address, pages); | |
1512 | ||
1513 | return bad_dma_address; | |
cb76c322 JR |
1514 | } |
1515 | ||
431b2a20 JR |
1516 | /* |
1517 | * Does the reverse of the __map_single function. Must be called with | |
1518 | * the domain lock held too | |
1519 | */ | |
cb76c322 JR |
1520 | static void __unmap_single(struct amd_iommu *iommu, |
1521 | struct dma_ops_domain *dma_dom, | |
1522 | dma_addr_t dma_addr, | |
1523 | size_t size, | |
1524 | int dir) | |
1525 | { | |
1526 | dma_addr_t i, start; | |
1527 | unsigned int pages; | |
1528 | ||
b8d9905d JR |
1529 | if ((dma_addr == bad_dma_address) || |
1530 | (dma_addr + size > dma_dom->aperture_size)) | |
cb76c322 JR |
1531 | return; |
1532 | ||
e3c449f5 | 1533 | pages = iommu_num_pages(dma_addr, size, PAGE_SIZE); |
cb76c322 JR |
1534 | dma_addr &= PAGE_MASK; |
1535 | start = dma_addr; | |
1536 | ||
1537 | for (i = 0; i < pages; ++i) { | |
1538 | dma_ops_domain_unmap(iommu, dma_dom, start); | |
1539 | start += PAGE_SIZE; | |
1540 | } | |
1541 | ||
5774f7c5 JR |
1542 | SUB_STATS_COUNTER(alloced_io_mem, size); |
1543 | ||
cb76c322 | 1544 | dma_ops_free_addresses(dma_dom, dma_addr, pages); |
270cab24 | 1545 | |
80be308d | 1546 | if (amd_iommu_unmap_flush || dma_dom->need_flush) { |
1c655773 | 1547 | iommu_flush_pages(iommu, dma_dom->domain.id, dma_addr, size); |
80be308d JR |
1548 | dma_dom->need_flush = false; |
1549 | } | |
cb76c322 JR |
1550 | } |
1551 | ||
431b2a20 JR |
1552 | /* |
1553 | * The exported map_single function for dma_ops. | |
1554 | */ | |
51491367 FT |
1555 | static dma_addr_t map_page(struct device *dev, struct page *page, |
1556 | unsigned long offset, size_t size, | |
1557 | enum dma_data_direction dir, | |
1558 | struct dma_attrs *attrs) | |
4da70b9e JR |
1559 | { |
1560 | unsigned long flags; | |
1561 | struct amd_iommu *iommu; | |
1562 | struct protection_domain *domain; | |
1563 | u16 devid; | |
1564 | dma_addr_t addr; | |
832a90c3 | 1565 | u64 dma_mask; |
51491367 | 1566 | phys_addr_t paddr = page_to_phys(page) + offset; |
4da70b9e | 1567 | |
0f2a86f2 JR |
1568 | INC_STATS_COUNTER(cnt_map_single); |
1569 | ||
dbcc112e JR |
1570 | if (!check_device(dev)) |
1571 | return bad_dma_address; | |
1572 | ||
832a90c3 | 1573 | dma_mask = *dev->dma_mask; |
4da70b9e JR |
1574 | |
1575 | get_device_resources(dev, &iommu, &domain, &devid); | |
1576 | ||
1577 | if (iommu == NULL || domain == NULL) | |
431b2a20 | 1578 | /* device not handled by any AMD IOMMU */ |
4da70b9e JR |
1579 | return (dma_addr_t)paddr; |
1580 | ||
5b28df6f JR |
1581 | if (!dma_ops_domain(domain)) |
1582 | return bad_dma_address; | |
1583 | ||
4da70b9e | 1584 | spin_lock_irqsave(&domain->lock, flags); |
832a90c3 JR |
1585 | addr = __map_single(dev, iommu, domain->priv, paddr, size, dir, false, |
1586 | dma_mask); | |
4da70b9e JR |
1587 | if (addr == bad_dma_address) |
1588 | goto out; | |
1589 | ||
09ee17eb | 1590 | iommu_completion_wait(iommu); |
4da70b9e JR |
1591 | |
1592 | out: | |
1593 | spin_unlock_irqrestore(&domain->lock, flags); | |
1594 | ||
1595 | return addr; | |
1596 | } | |
1597 | ||
431b2a20 JR |
1598 | /* |
1599 | * The exported unmap_single function for dma_ops. | |
1600 | */ | |
51491367 FT |
1601 | static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size, |
1602 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
4da70b9e JR |
1603 | { |
1604 | unsigned long flags; | |
1605 | struct amd_iommu *iommu; | |
1606 | struct protection_domain *domain; | |
1607 | u16 devid; | |
1608 | ||
146a6917 JR |
1609 | INC_STATS_COUNTER(cnt_unmap_single); |
1610 | ||
dbcc112e JR |
1611 | if (!check_device(dev) || |
1612 | !get_device_resources(dev, &iommu, &domain, &devid)) | |
431b2a20 | 1613 | /* device not handled by any AMD IOMMU */ |
4da70b9e JR |
1614 | return; |
1615 | ||
5b28df6f JR |
1616 | if (!dma_ops_domain(domain)) |
1617 | return; | |
1618 | ||
4da70b9e JR |
1619 | spin_lock_irqsave(&domain->lock, flags); |
1620 | ||
1621 | __unmap_single(iommu, domain->priv, dma_addr, size, dir); | |
1622 | ||
09ee17eb | 1623 | iommu_completion_wait(iommu); |
4da70b9e JR |
1624 | |
1625 | spin_unlock_irqrestore(&domain->lock, flags); | |
1626 | } | |
1627 | ||
431b2a20 JR |
1628 | /* |
1629 | * This is a special map_sg function which is used if we should map a | |
1630 | * device which is not handled by an AMD IOMMU in the system. | |
1631 | */ | |
65b050ad JR |
1632 | static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist, |
1633 | int nelems, int dir) | |
1634 | { | |
1635 | struct scatterlist *s; | |
1636 | int i; | |
1637 | ||
1638 | for_each_sg(sglist, s, nelems, i) { | |
1639 | s->dma_address = (dma_addr_t)sg_phys(s); | |
1640 | s->dma_length = s->length; | |
1641 | } | |
1642 | ||
1643 | return nelems; | |
1644 | } | |
1645 | ||
431b2a20 JR |
1646 | /* |
1647 | * The exported map_sg function for dma_ops (handles scatter-gather | |
1648 | * lists). | |
1649 | */ | |
65b050ad | 1650 | static int map_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
1651 | int nelems, enum dma_data_direction dir, |
1652 | struct dma_attrs *attrs) | |
65b050ad JR |
1653 | { |
1654 | unsigned long flags; | |
1655 | struct amd_iommu *iommu; | |
1656 | struct protection_domain *domain; | |
1657 | u16 devid; | |
1658 | int i; | |
1659 | struct scatterlist *s; | |
1660 | phys_addr_t paddr; | |
1661 | int mapped_elems = 0; | |
832a90c3 | 1662 | u64 dma_mask; |
65b050ad | 1663 | |
d03f067a JR |
1664 | INC_STATS_COUNTER(cnt_map_sg); |
1665 | ||
dbcc112e JR |
1666 | if (!check_device(dev)) |
1667 | return 0; | |
1668 | ||
832a90c3 | 1669 | dma_mask = *dev->dma_mask; |
65b050ad JR |
1670 | |
1671 | get_device_resources(dev, &iommu, &domain, &devid); | |
1672 | ||
1673 | if (!iommu || !domain) | |
1674 | return map_sg_no_iommu(dev, sglist, nelems, dir); | |
1675 | ||
5b28df6f JR |
1676 | if (!dma_ops_domain(domain)) |
1677 | return 0; | |
1678 | ||
65b050ad JR |
1679 | spin_lock_irqsave(&domain->lock, flags); |
1680 | ||
1681 | for_each_sg(sglist, s, nelems, i) { | |
1682 | paddr = sg_phys(s); | |
1683 | ||
1684 | s->dma_address = __map_single(dev, iommu, domain->priv, | |
832a90c3 JR |
1685 | paddr, s->length, dir, false, |
1686 | dma_mask); | |
65b050ad JR |
1687 | |
1688 | if (s->dma_address) { | |
1689 | s->dma_length = s->length; | |
1690 | mapped_elems++; | |
1691 | } else | |
1692 | goto unmap; | |
65b050ad JR |
1693 | } |
1694 | ||
09ee17eb | 1695 | iommu_completion_wait(iommu); |
65b050ad JR |
1696 | |
1697 | out: | |
1698 | spin_unlock_irqrestore(&domain->lock, flags); | |
1699 | ||
1700 | return mapped_elems; | |
1701 | unmap: | |
1702 | for_each_sg(sglist, s, mapped_elems, i) { | |
1703 | if (s->dma_address) | |
1704 | __unmap_single(iommu, domain->priv, s->dma_address, | |
1705 | s->dma_length, dir); | |
1706 | s->dma_address = s->dma_length = 0; | |
1707 | } | |
1708 | ||
1709 | mapped_elems = 0; | |
1710 | ||
1711 | goto out; | |
1712 | } | |
1713 | ||
431b2a20 JR |
1714 | /* |
1715 | * The exported map_sg function for dma_ops (handles scatter-gather | |
1716 | * lists). | |
1717 | */ | |
65b050ad | 1718 | static void unmap_sg(struct device *dev, struct scatterlist *sglist, |
160c1d8e FT |
1719 | int nelems, enum dma_data_direction dir, |
1720 | struct dma_attrs *attrs) | |
65b050ad JR |
1721 | { |
1722 | unsigned long flags; | |
1723 | struct amd_iommu *iommu; | |
1724 | struct protection_domain *domain; | |
1725 | struct scatterlist *s; | |
1726 | u16 devid; | |
1727 | int i; | |
1728 | ||
55877a6b JR |
1729 | INC_STATS_COUNTER(cnt_unmap_sg); |
1730 | ||
dbcc112e JR |
1731 | if (!check_device(dev) || |
1732 | !get_device_resources(dev, &iommu, &domain, &devid)) | |
65b050ad JR |
1733 | return; |
1734 | ||
5b28df6f JR |
1735 | if (!dma_ops_domain(domain)) |
1736 | return; | |
1737 | ||
65b050ad JR |
1738 | spin_lock_irqsave(&domain->lock, flags); |
1739 | ||
1740 | for_each_sg(sglist, s, nelems, i) { | |
1741 | __unmap_single(iommu, domain->priv, s->dma_address, | |
1742 | s->dma_length, dir); | |
65b050ad JR |
1743 | s->dma_address = s->dma_length = 0; |
1744 | } | |
1745 | ||
09ee17eb | 1746 | iommu_completion_wait(iommu); |
65b050ad JR |
1747 | |
1748 | spin_unlock_irqrestore(&domain->lock, flags); | |
1749 | } | |
1750 | ||
431b2a20 JR |
1751 | /* |
1752 | * The exported alloc_coherent function for dma_ops. | |
1753 | */ | |
5d8b53cf JR |
1754 | static void *alloc_coherent(struct device *dev, size_t size, |
1755 | dma_addr_t *dma_addr, gfp_t flag) | |
1756 | { | |
1757 | unsigned long flags; | |
1758 | void *virt_addr; | |
1759 | struct amd_iommu *iommu; | |
1760 | struct protection_domain *domain; | |
1761 | u16 devid; | |
1762 | phys_addr_t paddr; | |
832a90c3 | 1763 | u64 dma_mask = dev->coherent_dma_mask; |
5d8b53cf | 1764 | |
c8f0fb36 JR |
1765 | INC_STATS_COUNTER(cnt_alloc_coherent); |
1766 | ||
dbcc112e JR |
1767 | if (!check_device(dev)) |
1768 | return NULL; | |
5d8b53cf | 1769 | |
13d9fead FT |
1770 | if (!get_device_resources(dev, &iommu, &domain, &devid)) |
1771 | flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32); | |
5d8b53cf | 1772 | |
c97ac535 | 1773 | flag |= __GFP_ZERO; |
5d8b53cf JR |
1774 | virt_addr = (void *)__get_free_pages(flag, get_order(size)); |
1775 | if (!virt_addr) | |
b25ae679 | 1776 | return NULL; |
5d8b53cf | 1777 | |
5d8b53cf JR |
1778 | paddr = virt_to_phys(virt_addr); |
1779 | ||
5d8b53cf JR |
1780 | if (!iommu || !domain) { |
1781 | *dma_addr = (dma_addr_t)paddr; | |
1782 | return virt_addr; | |
1783 | } | |
1784 | ||
5b28df6f JR |
1785 | if (!dma_ops_domain(domain)) |
1786 | goto out_free; | |
1787 | ||
832a90c3 JR |
1788 | if (!dma_mask) |
1789 | dma_mask = *dev->dma_mask; | |
1790 | ||
5d8b53cf JR |
1791 | spin_lock_irqsave(&domain->lock, flags); |
1792 | ||
1793 | *dma_addr = __map_single(dev, iommu, domain->priv, paddr, | |
832a90c3 | 1794 | size, DMA_BIDIRECTIONAL, true, dma_mask); |
5d8b53cf | 1795 | |
367d04c4 JS |
1796 | if (*dma_addr == bad_dma_address) { |
1797 | spin_unlock_irqrestore(&domain->lock, flags); | |
5b28df6f | 1798 | goto out_free; |
367d04c4 | 1799 | } |
5d8b53cf | 1800 | |
09ee17eb | 1801 | iommu_completion_wait(iommu); |
5d8b53cf | 1802 | |
5d8b53cf JR |
1803 | spin_unlock_irqrestore(&domain->lock, flags); |
1804 | ||
1805 | return virt_addr; | |
5b28df6f JR |
1806 | |
1807 | out_free: | |
1808 | ||
1809 | free_pages((unsigned long)virt_addr, get_order(size)); | |
1810 | ||
1811 | return NULL; | |
5d8b53cf JR |
1812 | } |
1813 | ||
431b2a20 JR |
1814 | /* |
1815 | * The exported free_coherent function for dma_ops. | |
431b2a20 | 1816 | */ |
5d8b53cf JR |
1817 | static void free_coherent(struct device *dev, size_t size, |
1818 | void *virt_addr, dma_addr_t dma_addr) | |
1819 | { | |
1820 | unsigned long flags; | |
1821 | struct amd_iommu *iommu; | |
1822 | struct protection_domain *domain; | |
1823 | u16 devid; | |
1824 | ||
5d31ee7e JR |
1825 | INC_STATS_COUNTER(cnt_free_coherent); |
1826 | ||
dbcc112e JR |
1827 | if (!check_device(dev)) |
1828 | return; | |
1829 | ||
5d8b53cf JR |
1830 | get_device_resources(dev, &iommu, &domain, &devid); |
1831 | ||
1832 | if (!iommu || !domain) | |
1833 | goto free_mem; | |
1834 | ||
5b28df6f JR |
1835 | if (!dma_ops_domain(domain)) |
1836 | goto free_mem; | |
1837 | ||
5d8b53cf JR |
1838 | spin_lock_irqsave(&domain->lock, flags); |
1839 | ||
1840 | __unmap_single(iommu, domain->priv, dma_addr, size, DMA_BIDIRECTIONAL); | |
5d8b53cf | 1841 | |
09ee17eb | 1842 | iommu_completion_wait(iommu); |
5d8b53cf JR |
1843 | |
1844 | spin_unlock_irqrestore(&domain->lock, flags); | |
1845 | ||
1846 | free_mem: | |
1847 | free_pages((unsigned long)virt_addr, get_order(size)); | |
1848 | } | |
1849 | ||
b39ba6ad JR |
1850 | /* |
1851 | * This function is called by the DMA layer to find out if we can handle a | |
1852 | * particular device. It is part of the dma_ops. | |
1853 | */ | |
1854 | static int amd_iommu_dma_supported(struct device *dev, u64 mask) | |
1855 | { | |
1856 | u16 bdf; | |
1857 | struct pci_dev *pcidev; | |
1858 | ||
1859 | /* No device or no PCI device */ | |
1860 | if (!dev || dev->bus != &pci_bus_type) | |
1861 | return 0; | |
1862 | ||
1863 | pcidev = to_pci_dev(dev); | |
1864 | ||
1865 | bdf = calc_devid(pcidev->bus->number, pcidev->devfn); | |
1866 | ||
1867 | /* Out of our scope? */ | |
1868 | if (bdf > amd_iommu_last_bdf) | |
1869 | return 0; | |
1870 | ||
1871 | return 1; | |
1872 | } | |
1873 | ||
c432f3df | 1874 | /* |
431b2a20 JR |
1875 | * The function for pre-allocating protection domains. |
1876 | * | |
c432f3df JR |
1877 | * If the driver core informs the DMA layer if a driver grabs a device |
1878 | * we don't need to preallocate the protection domains anymore. | |
1879 | * For now we have to. | |
1880 | */ | |
0e93dd88 | 1881 | static void prealloc_protection_domains(void) |
c432f3df JR |
1882 | { |
1883 | struct pci_dev *dev = NULL; | |
1884 | struct dma_ops_domain *dma_dom; | |
1885 | struct amd_iommu *iommu; | |
c432f3df JR |
1886 | u16 devid; |
1887 | ||
1888 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { | |
edcb34da | 1889 | devid = calc_devid(dev->bus->number, dev->devfn); |
3a61ec38 | 1890 | if (devid > amd_iommu_last_bdf) |
c432f3df JR |
1891 | continue; |
1892 | devid = amd_iommu_alias_table[devid]; | |
1893 | if (domain_for_device(devid)) | |
1894 | continue; | |
1895 | iommu = amd_iommu_rlookup_table[devid]; | |
1896 | if (!iommu) | |
1897 | continue; | |
d9cfed92 | 1898 | dma_dom = dma_ops_domain_alloc(iommu); |
c432f3df JR |
1899 | if (!dma_dom) |
1900 | continue; | |
1901 | init_unity_mappings_for_device(dma_dom, devid); | |
bd60b735 JR |
1902 | dma_dom->target_dev = devid; |
1903 | ||
1904 | list_add_tail(&dma_dom->list, &iommu_pd_list); | |
c432f3df JR |
1905 | } |
1906 | } | |
1907 | ||
160c1d8e | 1908 | static struct dma_map_ops amd_iommu_dma_ops = { |
6631ee9d JR |
1909 | .alloc_coherent = alloc_coherent, |
1910 | .free_coherent = free_coherent, | |
51491367 FT |
1911 | .map_page = map_page, |
1912 | .unmap_page = unmap_page, | |
6631ee9d JR |
1913 | .map_sg = map_sg, |
1914 | .unmap_sg = unmap_sg, | |
b39ba6ad | 1915 | .dma_supported = amd_iommu_dma_supported, |
6631ee9d JR |
1916 | }; |
1917 | ||
431b2a20 JR |
1918 | /* |
1919 | * The function which clues the AMD IOMMU driver into dma_ops. | |
1920 | */ | |
6631ee9d JR |
1921 | int __init amd_iommu_init_dma_ops(void) |
1922 | { | |
1923 | struct amd_iommu *iommu; | |
6631ee9d JR |
1924 | int ret; |
1925 | ||
431b2a20 JR |
1926 | /* |
1927 | * first allocate a default protection domain for every IOMMU we | |
1928 | * found in the system. Devices not assigned to any other | |
1929 | * protection domain will be assigned to the default one. | |
1930 | */ | |
3bd22172 | 1931 | for_each_iommu(iommu) { |
d9cfed92 | 1932 | iommu->default_dom = dma_ops_domain_alloc(iommu); |
6631ee9d JR |
1933 | if (iommu->default_dom == NULL) |
1934 | return -ENOMEM; | |
e2dc14a2 | 1935 | iommu->default_dom->domain.flags |= PD_DEFAULT_MASK; |
6631ee9d JR |
1936 | ret = iommu_init_unity_mappings(iommu); |
1937 | if (ret) | |
1938 | goto free_domains; | |
1939 | } | |
1940 | ||
431b2a20 JR |
1941 | /* |
1942 | * If device isolation is enabled, pre-allocate the protection | |
1943 | * domains for each device. | |
1944 | */ | |
6631ee9d JR |
1945 | if (amd_iommu_isolate) |
1946 | prealloc_protection_domains(); | |
1947 | ||
1948 | iommu_detected = 1; | |
1949 | force_iommu = 1; | |
1950 | bad_dma_address = 0; | |
92af4e29 | 1951 | #ifdef CONFIG_GART_IOMMU |
6631ee9d JR |
1952 | gart_iommu_aperture_disabled = 1; |
1953 | gart_iommu_aperture = 0; | |
92af4e29 | 1954 | #endif |
6631ee9d | 1955 | |
431b2a20 | 1956 | /* Make the driver finally visible to the drivers */ |
6631ee9d JR |
1957 | dma_ops = &amd_iommu_dma_ops; |
1958 | ||
26961efe | 1959 | register_iommu(&amd_iommu_ops); |
26961efe | 1960 | |
e275a2a0 JR |
1961 | bus_register_notifier(&pci_bus_type, &device_nb); |
1962 | ||
7f26508b JR |
1963 | amd_iommu_stats_init(); |
1964 | ||
6631ee9d JR |
1965 | return 0; |
1966 | ||
1967 | free_domains: | |
1968 | ||
3bd22172 | 1969 | for_each_iommu(iommu) { |
6631ee9d JR |
1970 | if (iommu->default_dom) |
1971 | dma_ops_domain_free(iommu->default_dom); | |
1972 | } | |
1973 | ||
1974 | return ret; | |
1975 | } | |
6d98cd80 JR |
1976 | |
1977 | /***************************************************************************** | |
1978 | * | |
1979 | * The following functions belong to the exported interface of AMD IOMMU | |
1980 | * | |
1981 | * This interface allows access to lower level functions of the IOMMU | |
1982 | * like protection domain handling and assignement of devices to domains | |
1983 | * which is not possible with the dma_ops interface. | |
1984 | * | |
1985 | *****************************************************************************/ | |
1986 | ||
6d98cd80 JR |
1987 | static void cleanup_domain(struct protection_domain *domain) |
1988 | { | |
1989 | unsigned long flags; | |
1990 | u16 devid; | |
1991 | ||
1992 | write_lock_irqsave(&amd_iommu_devtable_lock, flags); | |
1993 | ||
1994 | for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) | |
1995 | if (amd_iommu_pd_table[devid] == domain) | |
1996 | __detach_device(domain, devid); | |
1997 | ||
1998 | write_unlock_irqrestore(&amd_iommu_devtable_lock, flags); | |
1999 | } | |
2000 | ||
c156e347 JR |
2001 | static int amd_iommu_domain_init(struct iommu_domain *dom) |
2002 | { | |
2003 | struct protection_domain *domain; | |
2004 | ||
2005 | domain = kzalloc(sizeof(*domain), GFP_KERNEL); | |
2006 | if (!domain) | |
2007 | return -ENOMEM; | |
2008 | ||
2009 | spin_lock_init(&domain->lock); | |
2010 | domain->mode = PAGE_MODE_3_LEVEL; | |
2011 | domain->id = domain_id_alloc(); | |
2012 | if (!domain->id) | |
2013 | goto out_free; | |
2014 | domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL); | |
2015 | if (!domain->pt_root) | |
2016 | goto out_free; | |
2017 | ||
2018 | dom->priv = domain; | |
2019 | ||
2020 | return 0; | |
2021 | ||
2022 | out_free: | |
2023 | kfree(domain); | |
2024 | ||
2025 | return -ENOMEM; | |
2026 | } | |
2027 | ||
98383fc3 JR |
2028 | static void amd_iommu_domain_destroy(struct iommu_domain *dom) |
2029 | { | |
2030 | struct protection_domain *domain = dom->priv; | |
2031 | ||
2032 | if (!domain) | |
2033 | return; | |
2034 | ||
2035 | if (domain->dev_cnt > 0) | |
2036 | cleanup_domain(domain); | |
2037 | ||
2038 | BUG_ON(domain->dev_cnt != 0); | |
2039 | ||
2040 | free_pagetable(domain); | |
2041 | ||
2042 | domain_id_free(domain->id); | |
2043 | ||
2044 | kfree(domain); | |
2045 | ||
2046 | dom->priv = NULL; | |
2047 | } | |
2048 | ||
684f2888 JR |
2049 | static void amd_iommu_detach_device(struct iommu_domain *dom, |
2050 | struct device *dev) | |
2051 | { | |
2052 | struct protection_domain *domain = dom->priv; | |
2053 | struct amd_iommu *iommu; | |
2054 | struct pci_dev *pdev; | |
2055 | u16 devid; | |
2056 | ||
2057 | if (dev->bus != &pci_bus_type) | |
2058 | return; | |
2059 | ||
2060 | pdev = to_pci_dev(dev); | |
2061 | ||
2062 | devid = calc_devid(pdev->bus->number, pdev->devfn); | |
2063 | ||
2064 | if (devid > 0) | |
2065 | detach_device(domain, devid); | |
2066 | ||
2067 | iommu = amd_iommu_rlookup_table[devid]; | |
2068 | if (!iommu) | |
2069 | return; | |
2070 | ||
2071 | iommu_queue_inv_dev_entry(iommu, devid); | |
2072 | iommu_completion_wait(iommu); | |
2073 | } | |
2074 | ||
01106066 JR |
2075 | static int amd_iommu_attach_device(struct iommu_domain *dom, |
2076 | struct device *dev) | |
2077 | { | |
2078 | struct protection_domain *domain = dom->priv; | |
2079 | struct protection_domain *old_domain; | |
2080 | struct amd_iommu *iommu; | |
2081 | struct pci_dev *pdev; | |
2082 | u16 devid; | |
2083 | ||
2084 | if (dev->bus != &pci_bus_type) | |
2085 | return -EINVAL; | |
2086 | ||
2087 | pdev = to_pci_dev(dev); | |
2088 | ||
2089 | devid = calc_devid(pdev->bus->number, pdev->devfn); | |
2090 | ||
2091 | if (devid >= amd_iommu_last_bdf || | |
2092 | devid != amd_iommu_alias_table[devid]) | |
2093 | return -EINVAL; | |
2094 | ||
2095 | iommu = amd_iommu_rlookup_table[devid]; | |
2096 | if (!iommu) | |
2097 | return -EINVAL; | |
2098 | ||
2099 | old_domain = domain_for_device(devid); | |
2100 | if (old_domain) | |
71ff3bca | 2101 | detach_device(old_domain, devid); |
01106066 JR |
2102 | |
2103 | attach_device(iommu, domain, devid); | |
2104 | ||
2105 | iommu_completion_wait(iommu); | |
2106 | ||
2107 | return 0; | |
2108 | } | |
2109 | ||
c6229ca6 JR |
2110 | static int amd_iommu_map_range(struct iommu_domain *dom, |
2111 | unsigned long iova, phys_addr_t paddr, | |
2112 | size_t size, int iommu_prot) | |
2113 | { | |
2114 | struct protection_domain *domain = dom->priv; | |
2115 | unsigned long i, npages = iommu_num_pages(paddr, size, PAGE_SIZE); | |
2116 | int prot = 0; | |
2117 | int ret; | |
2118 | ||
2119 | if (iommu_prot & IOMMU_READ) | |
2120 | prot |= IOMMU_PROT_IR; | |
2121 | if (iommu_prot & IOMMU_WRITE) | |
2122 | prot |= IOMMU_PROT_IW; | |
2123 | ||
2124 | iova &= PAGE_MASK; | |
2125 | paddr &= PAGE_MASK; | |
2126 | ||
2127 | for (i = 0; i < npages; ++i) { | |
2128 | ret = iommu_map_page(domain, iova, paddr, prot); | |
2129 | if (ret) | |
2130 | return ret; | |
2131 | ||
2132 | iova += PAGE_SIZE; | |
2133 | paddr += PAGE_SIZE; | |
2134 | } | |
2135 | ||
2136 | return 0; | |
2137 | } | |
2138 | ||
eb74ff6c JR |
2139 | static void amd_iommu_unmap_range(struct iommu_domain *dom, |
2140 | unsigned long iova, size_t size) | |
2141 | { | |
2142 | ||
2143 | struct protection_domain *domain = dom->priv; | |
2144 | unsigned long i, npages = iommu_num_pages(iova, size, PAGE_SIZE); | |
2145 | ||
2146 | iova &= PAGE_MASK; | |
2147 | ||
2148 | for (i = 0; i < npages; ++i) { | |
2149 | iommu_unmap_page(domain, iova); | |
2150 | iova += PAGE_SIZE; | |
2151 | } | |
2152 | ||
2153 | iommu_flush_domain(domain->id); | |
2154 | } | |
2155 | ||
645c4c8d JR |
2156 | static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, |
2157 | unsigned long iova) | |
2158 | { | |
2159 | struct protection_domain *domain = dom->priv; | |
2160 | unsigned long offset = iova & ~PAGE_MASK; | |
2161 | phys_addr_t paddr; | |
2162 | u64 *pte; | |
2163 | ||
2164 | pte = &domain->pt_root[IOMMU_PTE_L2_INDEX(iova)]; | |
2165 | ||
2166 | if (!IOMMU_PTE_PRESENT(*pte)) | |
2167 | return 0; | |
2168 | ||
2169 | pte = IOMMU_PTE_PAGE(*pte); | |
2170 | pte = &pte[IOMMU_PTE_L1_INDEX(iova)]; | |
2171 | ||
2172 | if (!IOMMU_PTE_PRESENT(*pte)) | |
2173 | return 0; | |
2174 | ||
2175 | pte = IOMMU_PTE_PAGE(*pte); | |
2176 | pte = &pte[IOMMU_PTE_L0_INDEX(iova)]; | |
2177 | ||
2178 | if (!IOMMU_PTE_PRESENT(*pte)) | |
2179 | return 0; | |
2180 | ||
2181 | paddr = *pte & IOMMU_PAGE_MASK; | |
2182 | paddr |= offset; | |
2183 | ||
2184 | return paddr; | |
2185 | } | |
2186 | ||
dbb9fd86 SY |
2187 | static int amd_iommu_domain_has_cap(struct iommu_domain *domain, |
2188 | unsigned long cap) | |
2189 | { | |
2190 | return 0; | |
2191 | } | |
2192 | ||
26961efe JR |
2193 | static struct iommu_ops amd_iommu_ops = { |
2194 | .domain_init = amd_iommu_domain_init, | |
2195 | .domain_destroy = amd_iommu_domain_destroy, | |
2196 | .attach_dev = amd_iommu_attach_device, | |
2197 | .detach_dev = amd_iommu_detach_device, | |
2198 | .map = amd_iommu_map_range, | |
2199 | .unmap = amd_iommu_unmap_range, | |
2200 | .iova_to_phys = amd_iommu_iova_to_phys, | |
dbb9fd86 | 2201 | .domain_has_cap = amd_iommu_domain_has_cap, |
26961efe JR |
2202 | }; |
2203 |