Commit | Line | Data |
---|---|---|
1b8873a0 JI |
1 | #undef DEBUG |
2 | ||
3 | /* | |
4 | * ARM performance counter support. | |
5 | * | |
6 | * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles | |
43eab878 | 7 | * Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com> |
796d1295 | 8 | * |
1b8873a0 JI |
9 | * This code is based on the sparc64 perf event code, which is in turn based |
10 | * on the x86 code. Callchain code is based on the ARM OProfile backtrace | |
11 | * code. | |
12 | */ | |
13 | #define pr_fmt(fmt) "hw perfevents: " fmt | |
14 | ||
1b8873a0 | 15 | #include <linux/kernel.h> |
49c006b9 | 16 | #include <linux/platform_device.h> |
7be2958e | 17 | #include <linux/pm_runtime.h> |
5505b206 | 18 | #include <linux/uaccess.h> |
1b8873a0 | 19 | |
1b8873a0 JI |
20 | #include <asm/irq_regs.h> |
21 | #include <asm/pmu.h> | |
22 | #include <asm/stacktrace.h> | |
23 | ||
1b8873a0 | 24 | static int |
e1f431b5 MR |
25 | armpmu_map_cache_event(const unsigned (*cache_map) |
26 | [PERF_COUNT_HW_CACHE_MAX] | |
27 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
28 | [PERF_COUNT_HW_CACHE_RESULT_MAX], | |
29 | u64 config) | |
1b8873a0 JI |
30 | { |
31 | unsigned int cache_type, cache_op, cache_result, ret; | |
32 | ||
33 | cache_type = (config >> 0) & 0xff; | |
34 | if (cache_type >= PERF_COUNT_HW_CACHE_MAX) | |
35 | return -EINVAL; | |
36 | ||
37 | cache_op = (config >> 8) & 0xff; | |
38 | if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) | |
39 | return -EINVAL; | |
40 | ||
41 | cache_result = (config >> 16) & 0xff; | |
42 | if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | |
43 | return -EINVAL; | |
44 | ||
e1f431b5 | 45 | ret = (int)(*cache_map)[cache_type][cache_op][cache_result]; |
1b8873a0 JI |
46 | |
47 | if (ret == CACHE_OP_UNSUPPORTED) | |
48 | return -ENOENT; | |
49 | ||
50 | return ret; | |
51 | } | |
52 | ||
84fee97a | 53 | static int |
6dbc0029 | 54 | armpmu_map_hw_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config) |
84fee97a | 55 | { |
e1f431b5 MR |
56 | int mapping = (*event_map)[config]; |
57 | return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping; | |
84fee97a WD |
58 | } |
59 | ||
60 | static int | |
e1f431b5 | 61 | armpmu_map_raw_event(u32 raw_event_mask, u64 config) |
84fee97a | 62 | { |
e1f431b5 MR |
63 | return (int)(config & raw_event_mask); |
64 | } | |
65 | ||
6dbc0029 WD |
66 | int |
67 | armpmu_map_event(struct perf_event *event, | |
68 | const unsigned (*event_map)[PERF_COUNT_HW_MAX], | |
69 | const unsigned (*cache_map) | |
70 | [PERF_COUNT_HW_CACHE_MAX] | |
71 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
72 | [PERF_COUNT_HW_CACHE_RESULT_MAX], | |
73 | u32 raw_event_mask) | |
e1f431b5 MR |
74 | { |
75 | u64 config = event->attr.config; | |
76 | ||
77 | switch (event->attr.type) { | |
78 | case PERF_TYPE_HARDWARE: | |
6dbc0029 | 79 | return armpmu_map_hw_event(event_map, config); |
e1f431b5 MR |
80 | case PERF_TYPE_HW_CACHE: |
81 | return armpmu_map_cache_event(cache_map, config); | |
82 | case PERF_TYPE_RAW: | |
83 | return armpmu_map_raw_event(raw_event_mask, config); | |
84 | } | |
85 | ||
86 | return -ENOENT; | |
84fee97a WD |
87 | } |
88 | ||
ed6f2a52 | 89 | int armpmu_event_set_period(struct perf_event *event) |
1b8873a0 | 90 | { |
8a16b34e | 91 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
ed6f2a52 | 92 | struct hw_perf_event *hwc = &event->hw; |
e7850595 | 93 | s64 left = local64_read(&hwc->period_left); |
1b8873a0 JI |
94 | s64 period = hwc->sample_period; |
95 | int ret = 0; | |
96 | ||
3581fe0e WD |
97 | /* The period may have been changed by PERF_EVENT_IOC_PERIOD */ |
98 | if (unlikely(period != hwc->last_period)) | |
99 | left = period - (hwc->last_period - left); | |
100 | ||
1b8873a0 JI |
101 | if (unlikely(left <= -period)) { |
102 | left = period; | |
e7850595 | 103 | local64_set(&hwc->period_left, left); |
1b8873a0 JI |
104 | hwc->last_period = period; |
105 | ret = 1; | |
106 | } | |
107 | ||
108 | if (unlikely(left <= 0)) { | |
109 | left += period; | |
e7850595 | 110 | local64_set(&hwc->period_left, left); |
1b8873a0 JI |
111 | hwc->last_period = period; |
112 | ret = 1; | |
113 | } | |
114 | ||
115 | if (left > (s64)armpmu->max_period) | |
116 | left = armpmu->max_period; | |
117 | ||
e7850595 | 118 | local64_set(&hwc->prev_count, (u64)-left); |
1b8873a0 | 119 | |
ed6f2a52 | 120 | armpmu->write_counter(event, (u64)(-left) & 0xffffffff); |
1b8873a0 JI |
121 | |
122 | perf_event_update_userpage(event); | |
123 | ||
124 | return ret; | |
125 | } | |
126 | ||
ed6f2a52 | 127 | u64 armpmu_event_update(struct perf_event *event) |
1b8873a0 | 128 | { |
8a16b34e | 129 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
ed6f2a52 | 130 | struct hw_perf_event *hwc = &event->hw; |
a737823d | 131 | u64 delta, prev_raw_count, new_raw_count; |
1b8873a0 JI |
132 | |
133 | again: | |
e7850595 | 134 | prev_raw_count = local64_read(&hwc->prev_count); |
ed6f2a52 | 135 | new_raw_count = armpmu->read_counter(event); |
1b8873a0 | 136 | |
e7850595 | 137 | if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, |
1b8873a0 JI |
138 | new_raw_count) != prev_raw_count) |
139 | goto again; | |
140 | ||
57273471 | 141 | delta = (new_raw_count - prev_raw_count) & armpmu->max_period; |
1b8873a0 | 142 | |
e7850595 PZ |
143 | local64_add(delta, &event->count); |
144 | local64_sub(delta, &hwc->period_left); | |
1b8873a0 JI |
145 | |
146 | return new_raw_count; | |
147 | } | |
148 | ||
149 | static void | |
a4eaf7f1 | 150 | armpmu_read(struct perf_event *event) |
1b8873a0 | 151 | { |
ed6f2a52 | 152 | armpmu_event_update(event); |
1b8873a0 JI |
153 | } |
154 | ||
155 | static void | |
a4eaf7f1 | 156 | armpmu_stop(struct perf_event *event, int flags) |
1b8873a0 | 157 | { |
8a16b34e | 158 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
1b8873a0 JI |
159 | struct hw_perf_event *hwc = &event->hw; |
160 | ||
a4eaf7f1 PZ |
161 | /* |
162 | * ARM pmu always has to update the counter, so ignore | |
163 | * PERF_EF_UPDATE, see comments in armpmu_start(). | |
164 | */ | |
165 | if (!(hwc->state & PERF_HES_STOPPED)) { | |
ed6f2a52 SK |
166 | armpmu->disable(event); |
167 | armpmu_event_update(event); | |
a4eaf7f1 PZ |
168 | hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; |
169 | } | |
1b8873a0 JI |
170 | } |
171 | ||
ed6f2a52 | 172 | static void armpmu_start(struct perf_event *event, int flags) |
1b8873a0 | 173 | { |
8a16b34e | 174 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
1b8873a0 JI |
175 | struct hw_perf_event *hwc = &event->hw; |
176 | ||
a4eaf7f1 PZ |
177 | /* |
178 | * ARM pmu always has to reprogram the period, so ignore | |
179 | * PERF_EF_RELOAD, see the comment below. | |
180 | */ | |
181 | if (flags & PERF_EF_RELOAD) | |
182 | WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE)); | |
183 | ||
184 | hwc->state = 0; | |
1b8873a0 JI |
185 | /* |
186 | * Set the period again. Some counters can't be stopped, so when we | |
a4eaf7f1 | 187 | * were stopped we simply disabled the IRQ source and the counter |
1b8873a0 JI |
188 | * may have been left counting. If we don't do this step then we may |
189 | * get an interrupt too soon or *way* too late if the overflow has | |
190 | * happened since disabling. | |
191 | */ | |
ed6f2a52 SK |
192 | armpmu_event_set_period(event); |
193 | armpmu->enable(event); | |
1b8873a0 JI |
194 | } |
195 | ||
a4eaf7f1 PZ |
196 | static void |
197 | armpmu_del(struct perf_event *event, int flags) | |
198 | { | |
8a16b34e | 199 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
8be3f9a2 | 200 | struct pmu_hw_events *hw_events = armpmu->get_hw_events(); |
a4eaf7f1 PZ |
201 | struct hw_perf_event *hwc = &event->hw; |
202 | int idx = hwc->idx; | |
203 | ||
a4eaf7f1 | 204 | armpmu_stop(event, PERF_EF_UPDATE); |
8be3f9a2 MR |
205 | hw_events->events[idx] = NULL; |
206 | clear_bit(idx, hw_events->used_mask); | |
a4eaf7f1 PZ |
207 | |
208 | perf_event_update_userpage(event); | |
209 | } | |
210 | ||
1b8873a0 | 211 | static int |
a4eaf7f1 | 212 | armpmu_add(struct perf_event *event, int flags) |
1b8873a0 | 213 | { |
8a16b34e | 214 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
8be3f9a2 | 215 | struct pmu_hw_events *hw_events = armpmu->get_hw_events(); |
1b8873a0 JI |
216 | struct hw_perf_event *hwc = &event->hw; |
217 | int idx; | |
218 | int err = 0; | |
219 | ||
33696fc0 | 220 | perf_pmu_disable(event->pmu); |
24cd7f54 | 221 | |
1b8873a0 | 222 | /* If we don't have a space for the counter then finish early. */ |
ed6f2a52 | 223 | idx = armpmu->get_event_idx(hw_events, event); |
1b8873a0 JI |
224 | if (idx < 0) { |
225 | err = idx; | |
226 | goto out; | |
227 | } | |
228 | ||
229 | /* | |
230 | * If there is an event in the counter we are going to use then make | |
231 | * sure it is disabled. | |
232 | */ | |
233 | event->hw.idx = idx; | |
ed6f2a52 | 234 | armpmu->disable(event); |
8be3f9a2 | 235 | hw_events->events[idx] = event; |
1b8873a0 | 236 | |
a4eaf7f1 PZ |
237 | hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE; |
238 | if (flags & PERF_EF_START) | |
239 | armpmu_start(event, PERF_EF_RELOAD); | |
1b8873a0 JI |
240 | |
241 | /* Propagate our changes to the userspace mapping. */ | |
242 | perf_event_update_userpage(event); | |
243 | ||
244 | out: | |
33696fc0 | 245 | perf_pmu_enable(event->pmu); |
1b8873a0 JI |
246 | return err; |
247 | } | |
248 | ||
1b8873a0 | 249 | static int |
8be3f9a2 | 250 | validate_event(struct pmu_hw_events *hw_events, |
1b8873a0 JI |
251 | struct perf_event *event) |
252 | { | |
8a16b34e | 253 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
7b9f72c6 | 254 | struct pmu *leader_pmu = event->group_leader->pmu; |
1b8873a0 | 255 | |
cb2d8b34 WD |
256 | if (event->pmu != leader_pmu || event->state < PERF_EVENT_STATE_OFF) |
257 | return 1; | |
258 | ||
259 | if (event->state == PERF_EVENT_STATE_OFF && !event->attr.enable_on_exec) | |
65b4711f | 260 | return 1; |
1b8873a0 | 261 | |
ed6f2a52 | 262 | return armpmu->get_event_idx(hw_events, event) >= 0; |
1b8873a0 JI |
263 | } |
264 | ||
265 | static int | |
266 | validate_group(struct perf_event *event) | |
267 | { | |
268 | struct perf_event *sibling, *leader = event->group_leader; | |
8be3f9a2 | 269 | struct pmu_hw_events fake_pmu; |
bce34d14 | 270 | DECLARE_BITMAP(fake_used_mask, ARMPMU_MAX_HWEVENTS); |
1b8873a0 | 271 | |
bce34d14 WD |
272 | /* |
273 | * Initialise the fake PMU. We only need to populate the | |
274 | * used_mask for the purposes of validation. | |
275 | */ | |
276 | memset(fake_used_mask, 0, sizeof(fake_used_mask)); | |
277 | fake_pmu.used_mask = fake_used_mask; | |
1b8873a0 JI |
278 | |
279 | if (!validate_event(&fake_pmu, leader)) | |
aa2bc1ad | 280 | return -EINVAL; |
1b8873a0 JI |
281 | |
282 | list_for_each_entry(sibling, &leader->sibling_list, group_entry) { | |
283 | if (!validate_event(&fake_pmu, sibling)) | |
aa2bc1ad | 284 | return -EINVAL; |
1b8873a0 JI |
285 | } |
286 | ||
287 | if (!validate_event(&fake_pmu, event)) | |
aa2bc1ad | 288 | return -EINVAL; |
1b8873a0 JI |
289 | |
290 | return 0; | |
291 | } | |
292 | ||
051f1b13 | 293 | static irqreturn_t armpmu_dispatch_irq(int irq, void *dev) |
0e25a5c9 | 294 | { |
8a16b34e | 295 | struct arm_pmu *armpmu = (struct arm_pmu *) dev; |
a9356a04 MR |
296 | struct platform_device *plat_device = armpmu->plat_device; |
297 | struct arm_pmu_platdata *plat = dev_get_platdata(&plat_device->dev); | |
0e25a5c9 | 298 | |
051f1b13 SK |
299 | if (plat && plat->handle_irq) |
300 | return plat->handle_irq(irq, dev, armpmu->handle_irq); | |
301 | else | |
302 | return armpmu->handle_irq(irq, dev); | |
0e25a5c9 RV |
303 | } |
304 | ||
0b390e21 | 305 | static void |
8a16b34e | 306 | armpmu_release_hardware(struct arm_pmu *armpmu) |
0b390e21 | 307 | { |
ed6f2a52 | 308 | armpmu->free_irq(armpmu); |
051f1b13 | 309 | pm_runtime_put_sync(&armpmu->plat_device->dev); |
0b390e21 WD |
310 | } |
311 | ||
1b8873a0 | 312 | static int |
8a16b34e | 313 | armpmu_reserve_hardware(struct arm_pmu *armpmu) |
1b8873a0 | 314 | { |
051f1b13 | 315 | int err; |
a9356a04 | 316 | struct platform_device *pmu_device = armpmu->plat_device; |
1b8873a0 | 317 | |
e5a21327 WD |
318 | if (!pmu_device) |
319 | return -ENODEV; | |
320 | ||
7be2958e | 321 | pm_runtime_get_sync(&pmu_device->dev); |
ed6f2a52 | 322 | err = armpmu->request_irq(armpmu, armpmu_dispatch_irq); |
051f1b13 SK |
323 | if (err) { |
324 | armpmu_release_hardware(armpmu); | |
325 | return err; | |
49c006b9 | 326 | } |
1b8873a0 | 327 | |
0b390e21 | 328 | return 0; |
1b8873a0 JI |
329 | } |
330 | ||
1b8873a0 JI |
331 | static void |
332 | hw_perf_event_destroy(struct perf_event *event) | |
333 | { | |
8a16b34e | 334 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
03b7898d MR |
335 | atomic_t *active_events = &armpmu->active_events; |
336 | struct mutex *pmu_reserve_mutex = &armpmu->reserve_mutex; | |
337 | ||
338 | if (atomic_dec_and_mutex_lock(active_events, pmu_reserve_mutex)) { | |
8a16b34e | 339 | armpmu_release_hardware(armpmu); |
03b7898d | 340 | mutex_unlock(pmu_reserve_mutex); |
1b8873a0 JI |
341 | } |
342 | } | |
343 | ||
05d22fde WD |
344 | static int |
345 | event_requires_mode_exclusion(struct perf_event_attr *attr) | |
346 | { | |
347 | return attr->exclude_idle || attr->exclude_user || | |
348 | attr->exclude_kernel || attr->exclude_hv; | |
349 | } | |
350 | ||
1b8873a0 JI |
351 | static int |
352 | __hw_perf_event_init(struct perf_event *event) | |
353 | { | |
8a16b34e | 354 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
1b8873a0 | 355 | struct hw_perf_event *hwc = &event->hw; |
9dcbf466 | 356 | int mapping; |
1b8873a0 | 357 | |
e1f431b5 | 358 | mapping = armpmu->map_event(event); |
1b8873a0 JI |
359 | |
360 | if (mapping < 0) { | |
361 | pr_debug("event %x:%llx not supported\n", event->attr.type, | |
362 | event->attr.config); | |
363 | return mapping; | |
364 | } | |
365 | ||
05d22fde WD |
366 | /* |
367 | * We don't assign an index until we actually place the event onto | |
368 | * hardware. Use -1 to signify that we haven't decided where to put it | |
369 | * yet. For SMP systems, each core has it's own PMU so we can't do any | |
370 | * clever allocation or constraints checking at this point. | |
371 | */ | |
372 | hwc->idx = -1; | |
373 | hwc->config_base = 0; | |
374 | hwc->config = 0; | |
375 | hwc->event_base = 0; | |
376 | ||
1b8873a0 JI |
377 | /* |
378 | * Check whether we need to exclude the counter from certain modes. | |
1b8873a0 | 379 | */ |
05d22fde WD |
380 | if ((!armpmu->set_event_filter || |
381 | armpmu->set_event_filter(hwc, &event->attr)) && | |
382 | event_requires_mode_exclusion(&event->attr)) { | |
1b8873a0 JI |
383 | pr_debug("ARM performance counters do not support " |
384 | "mode exclusion\n"); | |
fdeb8e35 | 385 | return -EOPNOTSUPP; |
1b8873a0 JI |
386 | } |
387 | ||
388 | /* | |
05d22fde | 389 | * Store the event encoding into the config_base field. |
1b8873a0 | 390 | */ |
05d22fde | 391 | hwc->config_base |= (unsigned long)mapping; |
1b8873a0 JI |
392 | |
393 | if (!hwc->sample_period) { | |
57273471 WD |
394 | /* |
395 | * For non-sampling runs, limit the sample_period to half | |
396 | * of the counter width. That way, the new counter value | |
397 | * is far less likely to overtake the previous one unless | |
398 | * you have some serious IRQ latency issues. | |
399 | */ | |
400 | hwc->sample_period = armpmu->max_period >> 1; | |
1b8873a0 | 401 | hwc->last_period = hwc->sample_period; |
e7850595 | 402 | local64_set(&hwc->period_left, hwc->sample_period); |
1b8873a0 JI |
403 | } |
404 | ||
1b8873a0 | 405 | if (event->group_leader != event) { |
e595ede6 | 406 | if (validate_group(event) != 0) |
1b8873a0 JI |
407 | return -EINVAL; |
408 | } | |
409 | ||
9dcbf466 | 410 | return 0; |
1b8873a0 JI |
411 | } |
412 | ||
b0a873eb | 413 | static int armpmu_event_init(struct perf_event *event) |
1b8873a0 | 414 | { |
8a16b34e | 415 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
1b8873a0 | 416 | int err = 0; |
03b7898d | 417 | atomic_t *active_events = &armpmu->active_events; |
1b8873a0 | 418 | |
2481c5fa SE |
419 | /* does not support taken branch sampling */ |
420 | if (has_branch_stack(event)) | |
421 | return -EOPNOTSUPP; | |
422 | ||
e1f431b5 | 423 | if (armpmu->map_event(event) == -ENOENT) |
b0a873eb | 424 | return -ENOENT; |
b0a873eb | 425 | |
1b8873a0 JI |
426 | event->destroy = hw_perf_event_destroy; |
427 | ||
03b7898d MR |
428 | if (!atomic_inc_not_zero(active_events)) { |
429 | mutex_lock(&armpmu->reserve_mutex); | |
430 | if (atomic_read(active_events) == 0) | |
8a16b34e | 431 | err = armpmu_reserve_hardware(armpmu); |
1b8873a0 JI |
432 | |
433 | if (!err) | |
03b7898d MR |
434 | atomic_inc(active_events); |
435 | mutex_unlock(&armpmu->reserve_mutex); | |
1b8873a0 JI |
436 | } |
437 | ||
438 | if (err) | |
b0a873eb | 439 | return err; |
1b8873a0 JI |
440 | |
441 | err = __hw_perf_event_init(event); | |
442 | if (err) | |
443 | hw_perf_event_destroy(event); | |
444 | ||
b0a873eb | 445 | return err; |
1b8873a0 JI |
446 | } |
447 | ||
a4eaf7f1 | 448 | static void armpmu_enable(struct pmu *pmu) |
1b8873a0 | 449 | { |
8be3f9a2 | 450 | struct arm_pmu *armpmu = to_arm_pmu(pmu); |
8be3f9a2 | 451 | struct pmu_hw_events *hw_events = armpmu->get_hw_events(); |
7325eaec | 452 | int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events); |
1b8873a0 | 453 | |
f4f38430 | 454 | if (enabled) |
ed6f2a52 | 455 | armpmu->start(armpmu); |
1b8873a0 JI |
456 | } |
457 | ||
a4eaf7f1 | 458 | static void armpmu_disable(struct pmu *pmu) |
1b8873a0 | 459 | { |
8a16b34e | 460 | struct arm_pmu *armpmu = to_arm_pmu(pmu); |
ed6f2a52 | 461 | armpmu->stop(armpmu); |
1b8873a0 JI |
462 | } |
463 | ||
7be2958e JH |
464 | #ifdef CONFIG_PM_RUNTIME |
465 | static int armpmu_runtime_resume(struct device *dev) | |
466 | { | |
467 | struct arm_pmu_platdata *plat = dev_get_platdata(dev); | |
468 | ||
469 | if (plat && plat->runtime_resume) | |
470 | return plat->runtime_resume(dev); | |
471 | ||
472 | return 0; | |
473 | } | |
474 | ||
475 | static int armpmu_runtime_suspend(struct device *dev) | |
476 | { | |
477 | struct arm_pmu_platdata *plat = dev_get_platdata(dev); | |
478 | ||
479 | if (plat && plat->runtime_suspend) | |
480 | return plat->runtime_suspend(dev); | |
481 | ||
482 | return 0; | |
483 | } | |
484 | #endif | |
485 | ||
6dbc0029 WD |
486 | const struct dev_pm_ops armpmu_dev_pm_ops = { |
487 | SET_RUNTIME_PM_OPS(armpmu_runtime_suspend, armpmu_runtime_resume, NULL) | |
488 | }; | |
489 | ||
44d6b1fc | 490 | static void armpmu_init(struct arm_pmu *armpmu) |
03b7898d MR |
491 | { |
492 | atomic_set(&armpmu->active_events, 0); | |
493 | mutex_init(&armpmu->reserve_mutex); | |
8a16b34e MR |
494 | |
495 | armpmu->pmu = (struct pmu) { | |
496 | .pmu_enable = armpmu_enable, | |
497 | .pmu_disable = armpmu_disable, | |
498 | .event_init = armpmu_event_init, | |
499 | .add = armpmu_add, | |
500 | .del = armpmu_del, | |
501 | .start = armpmu_start, | |
502 | .stop = armpmu_stop, | |
503 | .read = armpmu_read, | |
504 | }; | |
505 | } | |
506 | ||
0305230a | 507 | int armpmu_register(struct arm_pmu *armpmu, int type) |
8a16b34e MR |
508 | { |
509 | armpmu_init(armpmu); | |
2ac29a14 | 510 | pm_runtime_enable(&armpmu->plat_device->dev); |
04236f9f WD |
511 | pr_info("enabled with %s PMU driver, %d counters available\n", |
512 | armpmu->name, armpmu->num_events); | |
0305230a | 513 | return perf_pmu_register(&armpmu->pmu, armpmu->name, type); |
03b7898d MR |
514 | } |
515 | ||
1b8873a0 JI |
516 | /* |
517 | * Callchain handling code. | |
518 | */ | |
1b8873a0 JI |
519 | |
520 | /* | |
521 | * The registers we're interested in are at the end of the variable | |
522 | * length saved register structure. The fp points at the end of this | |
523 | * structure so the address of this struct is: | |
524 | * (struct frame_tail *)(xxx->fp)-1 | |
525 | * | |
526 | * This code has been adapted from the ARM OProfile support. | |
527 | */ | |
528 | struct frame_tail { | |
4d6b7a77 WD |
529 | struct frame_tail __user *fp; |
530 | unsigned long sp; | |
531 | unsigned long lr; | |
1b8873a0 JI |
532 | } __attribute__((packed)); |
533 | ||
534 | /* | |
535 | * Get the return address for a single stackframe and return a pointer to the | |
536 | * next frame tail. | |
537 | */ | |
4d6b7a77 WD |
538 | static struct frame_tail __user * |
539 | user_backtrace(struct frame_tail __user *tail, | |
1b8873a0 JI |
540 | struct perf_callchain_entry *entry) |
541 | { | |
542 | struct frame_tail buftail; | |
543 | ||
544 | /* Also check accessibility of one struct frame_tail beyond */ | |
545 | if (!access_ok(VERIFY_READ, tail, sizeof(buftail))) | |
546 | return NULL; | |
547 | if (__copy_from_user_inatomic(&buftail, tail, sizeof(buftail))) | |
548 | return NULL; | |
549 | ||
70791ce9 | 550 | perf_callchain_store(entry, buftail.lr); |
1b8873a0 JI |
551 | |
552 | /* | |
553 | * Frame pointers should strictly progress back up the stack | |
554 | * (towards higher addresses). | |
555 | */ | |
cb06199b | 556 | if (tail + 1 >= buftail.fp) |
1b8873a0 JI |
557 | return NULL; |
558 | ||
559 | return buftail.fp - 1; | |
560 | } | |
561 | ||
56962b44 FW |
562 | void |
563 | perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs) | |
1b8873a0 | 564 | { |
4d6b7a77 | 565 | struct frame_tail __user *tail; |
1b8873a0 | 566 | |
e50c5418 MZ |
567 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
568 | /* We don't support guest os callchain now */ | |
569 | return; | |
570 | } | |
1b8873a0 | 571 | |
4d6b7a77 | 572 | tail = (struct frame_tail __user *)regs->ARM_fp - 1; |
1b8873a0 | 573 | |
860ad782 SR |
574 | while ((entry->nr < PERF_MAX_STACK_DEPTH) && |
575 | tail && !((unsigned long)tail & 0x3)) | |
1b8873a0 JI |
576 | tail = user_backtrace(tail, entry); |
577 | } | |
578 | ||
579 | /* | |
580 | * Gets called by walk_stackframe() for every stackframe. This will be called | |
581 | * whist unwinding the stackframe and is like a subroutine return so we use | |
582 | * the PC. | |
583 | */ | |
584 | static int | |
585 | callchain_trace(struct stackframe *fr, | |
586 | void *data) | |
587 | { | |
588 | struct perf_callchain_entry *entry = data; | |
70791ce9 | 589 | perf_callchain_store(entry, fr->pc); |
1b8873a0 JI |
590 | return 0; |
591 | } | |
592 | ||
56962b44 FW |
593 | void |
594 | perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs) | |
1b8873a0 JI |
595 | { |
596 | struct stackframe fr; | |
597 | ||
e50c5418 MZ |
598 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
599 | /* We don't support guest os callchain now */ | |
600 | return; | |
601 | } | |
602 | ||
1b8873a0 JI |
603 | fr.fp = regs->ARM_fp; |
604 | fr.sp = regs->ARM_sp; | |
605 | fr.lr = regs->ARM_lr; | |
606 | fr.pc = regs->ARM_pc; | |
607 | walk_stackframe(&fr, callchain_trace, entry); | |
608 | } | |
e50c5418 MZ |
609 | |
610 | unsigned long perf_instruction_pointer(struct pt_regs *regs) | |
611 | { | |
612 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) | |
613 | return perf_guest_cbs->get_guest_ip(); | |
614 | ||
615 | return instruction_pointer(regs); | |
616 | } | |
617 | ||
618 | unsigned long perf_misc_flags(struct pt_regs *regs) | |
619 | { | |
620 | int misc = 0; | |
621 | ||
622 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { | |
623 | if (perf_guest_cbs->is_user_mode()) | |
624 | misc |= PERF_RECORD_MISC_GUEST_USER; | |
625 | else | |
626 | misc |= PERF_RECORD_MISC_GUEST_KERNEL; | |
627 | } else { | |
628 | if (user_mode(regs)) | |
629 | misc |= PERF_RECORD_MISC_USER; | |
630 | else | |
631 | misc |= PERF_RECORD_MISC_KERNEL; | |
632 | } | |
633 | ||
634 | return misc; | |
635 | } |