Commit | Line | Data |
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1b8873a0 JI |
1 | #undef DEBUG |
2 | ||
3 | /* | |
4 | * ARM performance counter support. | |
5 | * | |
6 | * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles | |
43eab878 | 7 | * Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com> |
796d1295 | 8 | * |
1b8873a0 JI |
9 | * This code is based on the sparc64 perf event code, which is in turn based |
10 | * on the x86 code. Callchain code is based on the ARM OProfile backtrace | |
11 | * code. | |
12 | */ | |
13 | #define pr_fmt(fmt) "hw perfevents: " fmt | |
14 | ||
15 | #include <linux/interrupt.h> | |
16 | #include <linux/kernel.h> | |
181193f3 | 17 | #include <linux/module.h> |
1b8873a0 | 18 | #include <linux/perf_event.h> |
49c006b9 | 19 | #include <linux/platform_device.h> |
1b8873a0 JI |
20 | #include <linux/spinlock.h> |
21 | #include <linux/uaccess.h> | |
22 | ||
23 | #include <asm/cputype.h> | |
24 | #include <asm/irq.h> | |
25 | #include <asm/irq_regs.h> | |
26 | #include <asm/pmu.h> | |
27 | #include <asm/stacktrace.h> | |
28 | ||
49c006b9 | 29 | static struct platform_device *pmu_device; |
1b8873a0 JI |
30 | |
31 | /* | |
32 | * Hardware lock to serialize accesses to PMU registers. Needed for the | |
33 | * read/modify/write sequences. | |
34 | */ | |
961ec6da | 35 | static DEFINE_RAW_SPINLOCK(pmu_lock); |
1b8873a0 JI |
36 | |
37 | /* | |
ecf5a893 | 38 | * ARMv6 supports a maximum of 3 events, starting from index 0. If we add |
1b8873a0 JI |
39 | * another platform that supports more, we need to increase this to be the |
40 | * largest of all platforms. | |
796d1295 JP |
41 | * |
42 | * ARMv7 supports up to 32 events: | |
43 | * cycle counter CCNT + 31 events counters CNT0..30. | |
44 | * Cortex-A8 has 1+4 counters, Cortex-A9 has 1+6 counters. | |
1b8873a0 | 45 | */ |
ecf5a893 | 46 | #define ARMPMU_MAX_HWEVENTS 32 |
1b8873a0 JI |
47 | |
48 | /* The events for a given CPU. */ | |
49 | struct cpu_hw_events { | |
50 | /* | |
ecf5a893 | 51 | * The events that are active on the CPU for the given index. |
1b8873a0 JI |
52 | */ |
53 | struct perf_event *events[ARMPMU_MAX_HWEVENTS]; | |
54 | ||
55 | /* | |
56 | * A 1 bit for an index indicates that the counter is being used for | |
57 | * an event. A 0 means that the counter can be used. | |
58 | */ | |
59 | unsigned long used_mask[BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)]; | |
1b8873a0 | 60 | }; |
4d6b7a77 | 61 | static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events); |
181193f3 | 62 | |
1b8873a0 | 63 | struct arm_pmu { |
181193f3 | 64 | enum arm_perf_pmu_ids id; |
0b390e21 | 65 | cpumask_t active_irqs; |
62994831 | 66 | const char *name; |
1b8873a0 JI |
67 | irqreturn_t (*handle_irq)(int irq_num, void *dev); |
68 | void (*enable)(struct hw_perf_event *evt, int idx); | |
69 | void (*disable)(struct hw_perf_event *evt, int idx); | |
1b8873a0 JI |
70 | int (*get_event_idx)(struct cpu_hw_events *cpuc, |
71 | struct hw_perf_event *hwc); | |
05d22fde WD |
72 | int (*set_event_filter)(struct hw_perf_event *evt, |
73 | struct perf_event_attr *attr); | |
1b8873a0 JI |
74 | u32 (*read_counter)(int idx); |
75 | void (*write_counter)(int idx, u32 val); | |
76 | void (*start)(void); | |
77 | void (*stop)(void); | |
574b69cb | 78 | void (*reset)(void *); |
84fee97a WD |
79 | const unsigned (*cache_map)[PERF_COUNT_HW_CACHE_MAX] |
80 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
81 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
82 | const unsigned (*event_map)[PERF_COUNT_HW_MAX]; | |
83 | u32 raw_event_mask; | |
1b8873a0 JI |
84 | int num_events; |
85 | u64 max_period; | |
86 | }; | |
87 | ||
88 | /* Set at runtime when we know what CPU type we are. */ | |
a6c93afe | 89 | static struct arm_pmu *armpmu; |
1b8873a0 | 90 | |
181193f3 WD |
91 | enum arm_perf_pmu_ids |
92 | armpmu_get_pmu_id(void) | |
93 | { | |
94 | int id = -ENODEV; | |
95 | ||
96 | if (armpmu != NULL) | |
97 | id = armpmu->id; | |
98 | ||
99 | return id; | |
100 | } | |
101 | EXPORT_SYMBOL_GPL(armpmu_get_pmu_id); | |
102 | ||
929f5199 WD |
103 | int |
104 | armpmu_get_max_events(void) | |
105 | { | |
106 | int max_events = 0; | |
107 | ||
108 | if (armpmu != NULL) | |
109 | max_events = armpmu->num_events; | |
110 | ||
111 | return max_events; | |
112 | } | |
113 | EXPORT_SYMBOL_GPL(armpmu_get_max_events); | |
114 | ||
3bf101ba MF |
115 | int perf_num_counters(void) |
116 | { | |
117 | return armpmu_get_max_events(); | |
118 | } | |
119 | EXPORT_SYMBOL_GPL(perf_num_counters); | |
120 | ||
1b8873a0 JI |
121 | #define HW_OP_UNSUPPORTED 0xFFFF |
122 | ||
123 | #define C(_x) \ | |
124 | PERF_COUNT_HW_CACHE_##_x | |
125 | ||
126 | #define CACHE_OP_UNSUPPORTED 0xFFFF | |
127 | ||
1b8873a0 JI |
128 | static int |
129 | armpmu_map_cache_event(u64 config) | |
130 | { | |
131 | unsigned int cache_type, cache_op, cache_result, ret; | |
132 | ||
133 | cache_type = (config >> 0) & 0xff; | |
134 | if (cache_type >= PERF_COUNT_HW_CACHE_MAX) | |
135 | return -EINVAL; | |
136 | ||
137 | cache_op = (config >> 8) & 0xff; | |
138 | if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) | |
139 | return -EINVAL; | |
140 | ||
141 | cache_result = (config >> 16) & 0xff; | |
142 | if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | |
143 | return -EINVAL; | |
144 | ||
84fee97a | 145 | ret = (int)(*armpmu->cache_map)[cache_type][cache_op][cache_result]; |
1b8873a0 JI |
146 | |
147 | if (ret == CACHE_OP_UNSUPPORTED) | |
148 | return -ENOENT; | |
149 | ||
150 | return ret; | |
151 | } | |
152 | ||
84fee97a WD |
153 | static int |
154 | armpmu_map_event(u64 config) | |
155 | { | |
156 | int mapping = (*armpmu->event_map)[config]; | |
157 | return mapping == HW_OP_UNSUPPORTED ? -EOPNOTSUPP : mapping; | |
158 | } | |
159 | ||
160 | static int | |
161 | armpmu_map_raw_event(u64 config) | |
162 | { | |
163 | return (int)(config & armpmu->raw_event_mask); | |
164 | } | |
165 | ||
1b8873a0 JI |
166 | static int |
167 | armpmu_event_set_period(struct perf_event *event, | |
168 | struct hw_perf_event *hwc, | |
169 | int idx) | |
170 | { | |
e7850595 | 171 | s64 left = local64_read(&hwc->period_left); |
1b8873a0 JI |
172 | s64 period = hwc->sample_period; |
173 | int ret = 0; | |
174 | ||
175 | if (unlikely(left <= -period)) { | |
176 | left = period; | |
e7850595 | 177 | local64_set(&hwc->period_left, left); |
1b8873a0 JI |
178 | hwc->last_period = period; |
179 | ret = 1; | |
180 | } | |
181 | ||
182 | if (unlikely(left <= 0)) { | |
183 | left += period; | |
e7850595 | 184 | local64_set(&hwc->period_left, left); |
1b8873a0 JI |
185 | hwc->last_period = period; |
186 | ret = 1; | |
187 | } | |
188 | ||
189 | if (left > (s64)armpmu->max_period) | |
190 | left = armpmu->max_period; | |
191 | ||
e7850595 | 192 | local64_set(&hwc->prev_count, (u64)-left); |
1b8873a0 JI |
193 | |
194 | armpmu->write_counter(idx, (u64)(-left) & 0xffffffff); | |
195 | ||
196 | perf_event_update_userpage(event); | |
197 | ||
198 | return ret; | |
199 | } | |
200 | ||
201 | static u64 | |
202 | armpmu_event_update(struct perf_event *event, | |
203 | struct hw_perf_event *hwc, | |
a737823d | 204 | int idx, int overflow) |
1b8873a0 | 205 | { |
a737823d | 206 | u64 delta, prev_raw_count, new_raw_count; |
1b8873a0 JI |
207 | |
208 | again: | |
e7850595 | 209 | prev_raw_count = local64_read(&hwc->prev_count); |
1b8873a0 JI |
210 | new_raw_count = armpmu->read_counter(idx); |
211 | ||
e7850595 | 212 | if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, |
1b8873a0 JI |
213 | new_raw_count) != prev_raw_count) |
214 | goto again; | |
215 | ||
a737823d WD |
216 | new_raw_count &= armpmu->max_period; |
217 | prev_raw_count &= armpmu->max_period; | |
218 | ||
219 | if (overflow) | |
6759788b | 220 | delta = armpmu->max_period - prev_raw_count + new_raw_count + 1; |
a737823d WD |
221 | else |
222 | delta = new_raw_count - prev_raw_count; | |
1b8873a0 | 223 | |
e7850595 PZ |
224 | local64_add(delta, &event->count); |
225 | local64_sub(delta, &hwc->period_left); | |
1b8873a0 JI |
226 | |
227 | return new_raw_count; | |
228 | } | |
229 | ||
230 | static void | |
a4eaf7f1 | 231 | armpmu_read(struct perf_event *event) |
1b8873a0 | 232 | { |
1b8873a0 | 233 | struct hw_perf_event *hwc = &event->hw; |
1b8873a0 | 234 | |
a4eaf7f1 PZ |
235 | /* Don't read disabled counters! */ |
236 | if (hwc->idx < 0) | |
237 | return; | |
1b8873a0 | 238 | |
a737823d | 239 | armpmu_event_update(event, hwc, hwc->idx, 0); |
1b8873a0 JI |
240 | } |
241 | ||
242 | static void | |
a4eaf7f1 | 243 | armpmu_stop(struct perf_event *event, int flags) |
1b8873a0 JI |
244 | { |
245 | struct hw_perf_event *hwc = &event->hw; | |
246 | ||
a4eaf7f1 PZ |
247 | /* |
248 | * ARM pmu always has to update the counter, so ignore | |
249 | * PERF_EF_UPDATE, see comments in armpmu_start(). | |
250 | */ | |
251 | if (!(hwc->state & PERF_HES_STOPPED)) { | |
252 | armpmu->disable(hwc, hwc->idx); | |
253 | barrier(); /* why? */ | |
a737823d | 254 | armpmu_event_update(event, hwc, hwc->idx, 0); |
a4eaf7f1 PZ |
255 | hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; |
256 | } | |
1b8873a0 JI |
257 | } |
258 | ||
259 | static void | |
a4eaf7f1 | 260 | armpmu_start(struct perf_event *event, int flags) |
1b8873a0 JI |
261 | { |
262 | struct hw_perf_event *hwc = &event->hw; | |
263 | ||
a4eaf7f1 PZ |
264 | /* |
265 | * ARM pmu always has to reprogram the period, so ignore | |
266 | * PERF_EF_RELOAD, see the comment below. | |
267 | */ | |
268 | if (flags & PERF_EF_RELOAD) | |
269 | WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE)); | |
270 | ||
271 | hwc->state = 0; | |
1b8873a0 JI |
272 | /* |
273 | * Set the period again. Some counters can't be stopped, so when we | |
a4eaf7f1 | 274 | * were stopped we simply disabled the IRQ source and the counter |
1b8873a0 JI |
275 | * may have been left counting. If we don't do this step then we may |
276 | * get an interrupt too soon or *way* too late if the overflow has | |
277 | * happened since disabling. | |
278 | */ | |
279 | armpmu_event_set_period(event, hwc, hwc->idx); | |
280 | armpmu->enable(hwc, hwc->idx); | |
281 | } | |
282 | ||
a4eaf7f1 PZ |
283 | static void |
284 | armpmu_del(struct perf_event *event, int flags) | |
285 | { | |
286 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
287 | struct hw_perf_event *hwc = &event->hw; | |
288 | int idx = hwc->idx; | |
289 | ||
290 | WARN_ON(idx < 0); | |
291 | ||
a4eaf7f1 PZ |
292 | armpmu_stop(event, PERF_EF_UPDATE); |
293 | cpuc->events[idx] = NULL; | |
294 | clear_bit(idx, cpuc->used_mask); | |
295 | ||
296 | perf_event_update_userpage(event); | |
297 | } | |
298 | ||
1b8873a0 | 299 | static int |
a4eaf7f1 | 300 | armpmu_add(struct perf_event *event, int flags) |
1b8873a0 JI |
301 | { |
302 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
303 | struct hw_perf_event *hwc = &event->hw; | |
304 | int idx; | |
305 | int err = 0; | |
306 | ||
33696fc0 | 307 | perf_pmu_disable(event->pmu); |
24cd7f54 | 308 | |
1b8873a0 JI |
309 | /* If we don't have a space for the counter then finish early. */ |
310 | idx = armpmu->get_event_idx(cpuc, hwc); | |
311 | if (idx < 0) { | |
312 | err = idx; | |
313 | goto out; | |
314 | } | |
315 | ||
316 | /* | |
317 | * If there is an event in the counter we are going to use then make | |
318 | * sure it is disabled. | |
319 | */ | |
320 | event->hw.idx = idx; | |
321 | armpmu->disable(hwc, idx); | |
322 | cpuc->events[idx] = event; | |
1b8873a0 | 323 | |
a4eaf7f1 PZ |
324 | hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE; |
325 | if (flags & PERF_EF_START) | |
326 | armpmu_start(event, PERF_EF_RELOAD); | |
1b8873a0 JI |
327 | |
328 | /* Propagate our changes to the userspace mapping. */ | |
329 | perf_event_update_userpage(event); | |
330 | ||
331 | out: | |
33696fc0 | 332 | perf_pmu_enable(event->pmu); |
1b8873a0 JI |
333 | return err; |
334 | } | |
335 | ||
b0a873eb | 336 | static struct pmu pmu; |
1b8873a0 JI |
337 | |
338 | static int | |
339 | validate_event(struct cpu_hw_events *cpuc, | |
340 | struct perf_event *event) | |
341 | { | |
342 | struct hw_perf_event fake_event = event->hw; | |
7b9f72c6 | 343 | struct pmu *leader_pmu = event->group_leader->pmu; |
1b8873a0 | 344 | |
7b9f72c6 | 345 | if (event->pmu != leader_pmu || event->state <= PERF_EVENT_STATE_OFF) |
65b4711f | 346 | return 1; |
1b8873a0 JI |
347 | |
348 | return armpmu->get_event_idx(cpuc, &fake_event) >= 0; | |
349 | } | |
350 | ||
351 | static int | |
352 | validate_group(struct perf_event *event) | |
353 | { | |
354 | struct perf_event *sibling, *leader = event->group_leader; | |
355 | struct cpu_hw_events fake_pmu; | |
356 | ||
357 | memset(&fake_pmu, 0, sizeof(fake_pmu)); | |
358 | ||
359 | if (!validate_event(&fake_pmu, leader)) | |
360 | return -ENOSPC; | |
361 | ||
362 | list_for_each_entry(sibling, &leader->sibling_list, group_entry) { | |
363 | if (!validate_event(&fake_pmu, sibling)) | |
364 | return -ENOSPC; | |
365 | } | |
366 | ||
367 | if (!validate_event(&fake_pmu, event)) | |
368 | return -ENOSPC; | |
369 | ||
370 | return 0; | |
371 | } | |
372 | ||
0e25a5c9 RV |
373 | static irqreturn_t armpmu_platform_irq(int irq, void *dev) |
374 | { | |
375 | struct arm_pmu_platdata *plat = dev_get_platdata(&pmu_device->dev); | |
376 | ||
377 | return plat->handle_irq(irq, dev, armpmu->handle_irq); | |
378 | } | |
379 | ||
0b390e21 WD |
380 | static void |
381 | armpmu_release_hardware(void) | |
382 | { | |
383 | int i, irq, irqs; | |
384 | ||
385 | irqs = min(pmu_device->num_resources, num_possible_cpus()); | |
386 | ||
387 | for (i = 0; i < irqs; ++i) { | |
388 | if (!cpumask_test_and_clear_cpu(i, &armpmu->active_irqs)) | |
389 | continue; | |
390 | irq = platform_get_irq(pmu_device, i); | |
391 | if (irq >= 0) | |
392 | free_irq(irq, NULL); | |
393 | } | |
394 | ||
395 | armpmu->stop(); | |
396 | release_pmu(ARM_PMU_DEVICE_CPU); | |
397 | } | |
398 | ||
1b8873a0 JI |
399 | static int |
400 | armpmu_reserve_hardware(void) | |
401 | { | |
0e25a5c9 RV |
402 | struct arm_pmu_platdata *plat; |
403 | irq_handler_t handle_irq; | |
b0e89590 | 404 | int i, err, irq, irqs; |
1b8873a0 | 405 | |
b0e89590 WD |
406 | err = reserve_pmu(ARM_PMU_DEVICE_CPU); |
407 | if (err) { | |
1b8873a0 | 408 | pr_warning("unable to reserve pmu\n"); |
b0e89590 | 409 | return err; |
1b8873a0 JI |
410 | } |
411 | ||
0e25a5c9 RV |
412 | plat = dev_get_platdata(&pmu_device->dev); |
413 | if (plat && plat->handle_irq) | |
414 | handle_irq = armpmu_platform_irq; | |
415 | else | |
416 | handle_irq = armpmu->handle_irq; | |
417 | ||
0b390e21 | 418 | irqs = min(pmu_device->num_resources, num_possible_cpus()); |
b0e89590 | 419 | if (irqs < 1) { |
1b8873a0 JI |
420 | pr_err("no irqs for PMUs defined\n"); |
421 | return -ENODEV; | |
422 | } | |
423 | ||
b0e89590 | 424 | for (i = 0; i < irqs; ++i) { |
0b390e21 | 425 | err = 0; |
49c006b9 WD |
426 | irq = platform_get_irq(pmu_device, i); |
427 | if (irq < 0) | |
428 | continue; | |
429 | ||
b0e89590 WD |
430 | /* |
431 | * If we have a single PMU interrupt that we can't shift, | |
432 | * assume that we're running on a uniprocessor machine and | |
0b390e21 | 433 | * continue. Otherwise, continue without this interrupt. |
b0e89590 | 434 | */ |
0b390e21 WD |
435 | if (irq_set_affinity(irq, cpumask_of(i)) && irqs > 1) { |
436 | pr_warning("unable to set irq affinity (irq=%d, cpu=%u)\n", | |
437 | irq, i); | |
438 | continue; | |
b0e89590 WD |
439 | } |
440 | ||
0e25a5c9 | 441 | err = request_irq(irq, handle_irq, |
ddee87f2 | 442 | IRQF_DISABLED | IRQF_NOBALANCING, |
b0e89590 | 443 | "arm-pmu", NULL); |
1b8873a0 | 444 | if (err) { |
b0e89590 WD |
445 | pr_err("unable to request IRQ%d for ARM PMU counters\n", |
446 | irq); | |
0b390e21 WD |
447 | armpmu_release_hardware(); |
448 | return err; | |
1b8873a0 | 449 | } |
1b8873a0 | 450 | |
0b390e21 | 451 | cpumask_set_cpu(i, &armpmu->active_irqs); |
49c006b9 | 452 | } |
1b8873a0 | 453 | |
0b390e21 | 454 | return 0; |
1b8873a0 JI |
455 | } |
456 | ||
457 | static atomic_t active_events = ATOMIC_INIT(0); | |
458 | static DEFINE_MUTEX(pmu_reserve_mutex); | |
459 | ||
460 | static void | |
461 | hw_perf_event_destroy(struct perf_event *event) | |
462 | { | |
463 | if (atomic_dec_and_mutex_lock(&active_events, &pmu_reserve_mutex)) { | |
464 | armpmu_release_hardware(); | |
465 | mutex_unlock(&pmu_reserve_mutex); | |
466 | } | |
467 | } | |
468 | ||
05d22fde WD |
469 | static int |
470 | event_requires_mode_exclusion(struct perf_event_attr *attr) | |
471 | { | |
472 | return attr->exclude_idle || attr->exclude_user || | |
473 | attr->exclude_kernel || attr->exclude_hv; | |
474 | } | |
475 | ||
1b8873a0 JI |
476 | static int |
477 | __hw_perf_event_init(struct perf_event *event) | |
478 | { | |
479 | struct hw_perf_event *hwc = &event->hw; | |
480 | int mapping, err; | |
481 | ||
482 | /* Decode the generic type into an ARM event identifier. */ | |
483 | if (PERF_TYPE_HARDWARE == event->attr.type) { | |
84fee97a | 484 | mapping = armpmu_map_event(event->attr.config); |
1b8873a0 JI |
485 | } else if (PERF_TYPE_HW_CACHE == event->attr.type) { |
486 | mapping = armpmu_map_cache_event(event->attr.config); | |
487 | } else if (PERF_TYPE_RAW == event->attr.type) { | |
84fee97a | 488 | mapping = armpmu_map_raw_event(event->attr.config); |
1b8873a0 JI |
489 | } else { |
490 | pr_debug("event type %x not supported\n", event->attr.type); | |
491 | return -EOPNOTSUPP; | |
492 | } | |
493 | ||
494 | if (mapping < 0) { | |
495 | pr_debug("event %x:%llx not supported\n", event->attr.type, | |
496 | event->attr.config); | |
497 | return mapping; | |
498 | } | |
499 | ||
05d22fde WD |
500 | /* |
501 | * We don't assign an index until we actually place the event onto | |
502 | * hardware. Use -1 to signify that we haven't decided where to put it | |
503 | * yet. For SMP systems, each core has it's own PMU so we can't do any | |
504 | * clever allocation or constraints checking at this point. | |
505 | */ | |
506 | hwc->idx = -1; | |
507 | hwc->config_base = 0; | |
508 | hwc->config = 0; | |
509 | hwc->event_base = 0; | |
510 | ||
1b8873a0 JI |
511 | /* |
512 | * Check whether we need to exclude the counter from certain modes. | |
1b8873a0 | 513 | */ |
05d22fde WD |
514 | if ((!armpmu->set_event_filter || |
515 | armpmu->set_event_filter(hwc, &event->attr)) && | |
516 | event_requires_mode_exclusion(&event->attr)) { | |
1b8873a0 JI |
517 | pr_debug("ARM performance counters do not support " |
518 | "mode exclusion\n"); | |
519 | return -EPERM; | |
520 | } | |
521 | ||
522 | /* | |
05d22fde | 523 | * Store the event encoding into the config_base field. |
1b8873a0 | 524 | */ |
05d22fde | 525 | hwc->config_base |= (unsigned long)mapping; |
1b8873a0 JI |
526 | |
527 | if (!hwc->sample_period) { | |
528 | hwc->sample_period = armpmu->max_period; | |
529 | hwc->last_period = hwc->sample_period; | |
e7850595 | 530 | local64_set(&hwc->period_left, hwc->sample_period); |
1b8873a0 JI |
531 | } |
532 | ||
533 | err = 0; | |
534 | if (event->group_leader != event) { | |
535 | err = validate_group(event); | |
536 | if (err) | |
537 | return -EINVAL; | |
538 | } | |
539 | ||
540 | return err; | |
541 | } | |
542 | ||
b0a873eb | 543 | static int armpmu_event_init(struct perf_event *event) |
1b8873a0 JI |
544 | { |
545 | int err = 0; | |
546 | ||
b0a873eb PZ |
547 | switch (event->attr.type) { |
548 | case PERF_TYPE_RAW: | |
549 | case PERF_TYPE_HARDWARE: | |
550 | case PERF_TYPE_HW_CACHE: | |
551 | break; | |
552 | ||
553 | default: | |
554 | return -ENOENT; | |
555 | } | |
556 | ||
1b8873a0 JI |
557 | event->destroy = hw_perf_event_destroy; |
558 | ||
559 | if (!atomic_inc_not_zero(&active_events)) { | |
1b8873a0 JI |
560 | mutex_lock(&pmu_reserve_mutex); |
561 | if (atomic_read(&active_events) == 0) { | |
562 | err = armpmu_reserve_hardware(); | |
563 | } | |
564 | ||
565 | if (!err) | |
566 | atomic_inc(&active_events); | |
567 | mutex_unlock(&pmu_reserve_mutex); | |
568 | } | |
569 | ||
570 | if (err) | |
b0a873eb | 571 | return err; |
1b8873a0 JI |
572 | |
573 | err = __hw_perf_event_init(event); | |
574 | if (err) | |
575 | hw_perf_event_destroy(event); | |
576 | ||
b0a873eb | 577 | return err; |
1b8873a0 JI |
578 | } |
579 | ||
a4eaf7f1 | 580 | static void armpmu_enable(struct pmu *pmu) |
1b8873a0 JI |
581 | { |
582 | /* Enable all of the perf events on hardware. */ | |
f4f38430 | 583 | int idx, enabled = 0; |
1b8873a0 JI |
584 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
585 | ||
ecf5a893 | 586 | for (idx = 0; idx < armpmu->num_events; ++idx) { |
1b8873a0 JI |
587 | struct perf_event *event = cpuc->events[idx]; |
588 | ||
589 | if (!event) | |
590 | continue; | |
591 | ||
592 | armpmu->enable(&event->hw, idx); | |
f4f38430 | 593 | enabled = 1; |
1b8873a0 JI |
594 | } |
595 | ||
f4f38430 WD |
596 | if (enabled) |
597 | armpmu->start(); | |
1b8873a0 JI |
598 | } |
599 | ||
a4eaf7f1 | 600 | static void armpmu_disable(struct pmu *pmu) |
1b8873a0 | 601 | { |
48957155 | 602 | armpmu->stop(); |
1b8873a0 JI |
603 | } |
604 | ||
33696fc0 | 605 | static struct pmu pmu = { |
a4eaf7f1 PZ |
606 | .pmu_enable = armpmu_enable, |
607 | .pmu_disable = armpmu_disable, | |
608 | .event_init = armpmu_event_init, | |
609 | .add = armpmu_add, | |
610 | .del = armpmu_del, | |
611 | .start = armpmu_start, | |
612 | .stop = armpmu_stop, | |
613 | .read = armpmu_read, | |
33696fc0 PZ |
614 | }; |
615 | ||
43eab878 WD |
616 | /* Include the PMU-specific implementations. */ |
617 | #include "perf_event_xscale.c" | |
618 | #include "perf_event_v6.c" | |
619 | #include "perf_event_v7.c" | |
49e6a32f | 620 | |
574b69cb WD |
621 | /* |
622 | * Ensure the PMU has sane values out of reset. | |
623 | * This requires SMP to be available, so exists as a separate initcall. | |
624 | */ | |
625 | static int __init | |
626 | armpmu_reset(void) | |
627 | { | |
628 | if (armpmu && armpmu->reset) | |
629 | return on_each_cpu(armpmu->reset, NULL, 1); | |
630 | return 0; | |
631 | } | |
632 | arch_initcall(armpmu_reset); | |
633 | ||
b0e89590 WD |
634 | /* |
635 | * PMU platform driver and devicetree bindings. | |
636 | */ | |
637 | static struct of_device_id armpmu_of_device_ids[] = { | |
638 | {.compatible = "arm,cortex-a9-pmu"}, | |
639 | {.compatible = "arm,cortex-a8-pmu"}, | |
640 | {.compatible = "arm,arm1136-pmu"}, | |
641 | {.compatible = "arm,arm1176-pmu"}, | |
642 | {}, | |
643 | }; | |
644 | ||
645 | static struct platform_device_id armpmu_plat_device_ids[] = { | |
646 | {.name = "arm-pmu"}, | |
647 | {}, | |
648 | }; | |
649 | ||
650 | static int __devinit armpmu_device_probe(struct platform_device *pdev) | |
651 | { | |
652 | pmu_device = pdev; | |
653 | return 0; | |
654 | } | |
655 | ||
656 | static struct platform_driver armpmu_driver = { | |
657 | .driver = { | |
658 | .name = "arm-pmu", | |
659 | .of_match_table = armpmu_of_device_ids, | |
660 | }, | |
661 | .probe = armpmu_device_probe, | |
662 | .id_table = armpmu_plat_device_ids, | |
663 | }; | |
664 | ||
665 | static int __init register_pmu_driver(void) | |
666 | { | |
667 | return platform_driver_register(&armpmu_driver); | |
668 | } | |
669 | device_initcall(register_pmu_driver); | |
670 | ||
671 | /* | |
672 | * CPU PMU identification and registration. | |
673 | */ | |
1b8873a0 JI |
674 | static int __init |
675 | init_hw_perf_events(void) | |
676 | { | |
677 | unsigned long cpuid = read_cpuid_id(); | |
678 | unsigned long implementor = (cpuid & 0xFF000000) >> 24; | |
679 | unsigned long part_number = (cpuid & 0xFFF0); | |
680 | ||
49e6a32f | 681 | /* ARM Ltd CPUs. */ |
1b8873a0 JI |
682 | if (0x41 == implementor) { |
683 | switch (part_number) { | |
684 | case 0xB360: /* ARM1136 */ | |
685 | case 0xB560: /* ARM1156 */ | |
686 | case 0xB760: /* ARM1176 */ | |
3cb314ba | 687 | armpmu = armv6pmu_init(); |
1b8873a0 JI |
688 | break; |
689 | case 0xB020: /* ARM11mpcore */ | |
3cb314ba | 690 | armpmu = armv6mpcore_pmu_init(); |
1b8873a0 | 691 | break; |
796d1295 | 692 | case 0xC080: /* Cortex-A8 */ |
3cb314ba | 693 | armpmu = armv7_a8_pmu_init(); |
796d1295 JP |
694 | break; |
695 | case 0xC090: /* Cortex-A9 */ | |
3cb314ba | 696 | armpmu = armv7_a9_pmu_init(); |
796d1295 | 697 | break; |
0c205cbe WD |
698 | case 0xC050: /* Cortex-A5 */ |
699 | armpmu = armv7_a5_pmu_init(); | |
700 | break; | |
14abd038 WD |
701 | case 0xC0F0: /* Cortex-A15 */ |
702 | armpmu = armv7_a15_pmu_init(); | |
703 | break; | |
49e6a32f WD |
704 | } |
705 | /* Intel CPUs [xscale]. */ | |
706 | } else if (0x69 == implementor) { | |
707 | part_number = (cpuid >> 13) & 0x7; | |
708 | switch (part_number) { | |
709 | case 1: | |
3cb314ba | 710 | armpmu = xscale1pmu_init(); |
49e6a32f WD |
711 | break; |
712 | case 2: | |
3cb314ba | 713 | armpmu = xscale2pmu_init(); |
49e6a32f | 714 | break; |
1b8873a0 JI |
715 | } |
716 | } | |
717 | ||
49e6a32f | 718 | if (armpmu) { |
796d1295 | 719 | pr_info("enabled with %s PMU driver, %d counters available\n", |
62994831 | 720 | armpmu->name, armpmu->num_events); |
48957155 | 721 | perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW); |
49e6a32f WD |
722 | } else { |
723 | pr_info("no hardware support available\n"); | |
49e6a32f | 724 | } |
1b8873a0 JI |
725 | |
726 | return 0; | |
727 | } | |
004417a6 | 728 | early_initcall(init_hw_perf_events); |
1b8873a0 JI |
729 | |
730 | /* | |
731 | * Callchain handling code. | |
732 | */ | |
1b8873a0 JI |
733 | |
734 | /* | |
735 | * The registers we're interested in are at the end of the variable | |
736 | * length saved register structure. The fp points at the end of this | |
737 | * structure so the address of this struct is: | |
738 | * (struct frame_tail *)(xxx->fp)-1 | |
739 | * | |
740 | * This code has been adapted from the ARM OProfile support. | |
741 | */ | |
742 | struct frame_tail { | |
4d6b7a77 WD |
743 | struct frame_tail __user *fp; |
744 | unsigned long sp; | |
745 | unsigned long lr; | |
1b8873a0 JI |
746 | } __attribute__((packed)); |
747 | ||
748 | /* | |
749 | * Get the return address for a single stackframe and return a pointer to the | |
750 | * next frame tail. | |
751 | */ | |
4d6b7a77 WD |
752 | static struct frame_tail __user * |
753 | user_backtrace(struct frame_tail __user *tail, | |
1b8873a0 JI |
754 | struct perf_callchain_entry *entry) |
755 | { | |
756 | struct frame_tail buftail; | |
757 | ||
758 | /* Also check accessibility of one struct frame_tail beyond */ | |
759 | if (!access_ok(VERIFY_READ, tail, sizeof(buftail))) | |
760 | return NULL; | |
761 | if (__copy_from_user_inatomic(&buftail, tail, sizeof(buftail))) | |
762 | return NULL; | |
763 | ||
70791ce9 | 764 | perf_callchain_store(entry, buftail.lr); |
1b8873a0 JI |
765 | |
766 | /* | |
767 | * Frame pointers should strictly progress back up the stack | |
768 | * (towards higher addresses). | |
769 | */ | |
cb06199b | 770 | if (tail + 1 >= buftail.fp) |
1b8873a0 JI |
771 | return NULL; |
772 | ||
773 | return buftail.fp - 1; | |
774 | } | |
775 | ||
56962b44 FW |
776 | void |
777 | perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs) | |
1b8873a0 | 778 | { |
4d6b7a77 | 779 | struct frame_tail __user *tail; |
1b8873a0 | 780 | |
1b8873a0 | 781 | |
4d6b7a77 | 782 | tail = (struct frame_tail __user *)regs->ARM_fp - 1; |
1b8873a0 | 783 | |
860ad782 SR |
784 | while ((entry->nr < PERF_MAX_STACK_DEPTH) && |
785 | tail && !((unsigned long)tail & 0x3)) | |
1b8873a0 JI |
786 | tail = user_backtrace(tail, entry); |
787 | } | |
788 | ||
789 | /* | |
790 | * Gets called by walk_stackframe() for every stackframe. This will be called | |
791 | * whist unwinding the stackframe and is like a subroutine return so we use | |
792 | * the PC. | |
793 | */ | |
794 | static int | |
795 | callchain_trace(struct stackframe *fr, | |
796 | void *data) | |
797 | { | |
798 | struct perf_callchain_entry *entry = data; | |
70791ce9 | 799 | perf_callchain_store(entry, fr->pc); |
1b8873a0 JI |
800 | return 0; |
801 | } | |
802 | ||
56962b44 FW |
803 | void |
804 | perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs) | |
1b8873a0 JI |
805 | { |
806 | struct stackframe fr; | |
807 | ||
1b8873a0 JI |
808 | fr.fp = regs->ARM_fp; |
809 | fr.sp = regs->ARM_sp; | |
810 | fr.lr = regs->ARM_lr; | |
811 | fr.pc = regs->ARM_pc; | |
812 | walk_stackframe(&fr, callchain_trace, entry); | |
813 | } |