Commit | Line | Data |
---|---|---|
1b8873a0 JI |
1 | #undef DEBUG |
2 | ||
3 | /* | |
4 | * ARM performance counter support. | |
5 | * | |
6 | * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles | |
43eab878 | 7 | * Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com> |
796d1295 | 8 | * |
1b8873a0 JI |
9 | * This code is based on the sparc64 perf event code, which is in turn based |
10 | * on the x86 code. Callchain code is based on the ARM OProfile backtrace | |
11 | * code. | |
12 | */ | |
13 | #define pr_fmt(fmt) "hw perfevents: " fmt | |
14 | ||
7325eaec | 15 | #include <linux/bitmap.h> |
1b8873a0 JI |
16 | #include <linux/interrupt.h> |
17 | #include <linux/kernel.h> | |
ecea4ab6 | 18 | #include <linux/export.h> |
1b8873a0 | 19 | #include <linux/perf_event.h> |
49c006b9 | 20 | #include <linux/platform_device.h> |
1b8873a0 JI |
21 | #include <linux/spinlock.h> |
22 | #include <linux/uaccess.h> | |
7be2958e | 23 | #include <linux/pm_runtime.h> |
1b8873a0 JI |
24 | |
25 | #include <asm/cputype.h> | |
26 | #include <asm/irq.h> | |
27 | #include <asm/irq_regs.h> | |
28 | #include <asm/pmu.h> | |
29 | #include <asm/stacktrace.h> | |
30 | ||
1b8873a0 | 31 | /* |
ecf5a893 | 32 | * ARMv6 supports a maximum of 3 events, starting from index 0. If we add |
1b8873a0 JI |
33 | * another platform that supports more, we need to increase this to be the |
34 | * largest of all platforms. | |
796d1295 JP |
35 | * |
36 | * ARMv7 supports up to 32 events: | |
37 | * cycle counter CCNT + 31 events counters CNT0..30. | |
38 | * Cortex-A8 has 1+4 counters, Cortex-A9 has 1+6 counters. | |
1b8873a0 | 39 | */ |
ecf5a893 | 40 | #define ARMPMU_MAX_HWEVENTS 32 |
1b8873a0 | 41 | |
3fc2c830 MR |
42 | static DEFINE_PER_CPU(struct perf_event * [ARMPMU_MAX_HWEVENTS], hw_events); |
43 | static DEFINE_PER_CPU(unsigned long [BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)], used_mask); | |
8be3f9a2 | 44 | static DEFINE_PER_CPU(struct pmu_hw_events, cpu_hw_events); |
181193f3 | 45 | |
8a16b34e MR |
46 | #define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu)) |
47 | ||
1b8873a0 | 48 | /* Set at runtime when we know what CPU type we are. */ |
8be3f9a2 | 49 | static struct arm_pmu *cpu_pmu; |
1b8873a0 | 50 | |
4295b898 | 51 | const char *perf_pmu_name(void) |
181193f3 | 52 | { |
4295b898 WD |
53 | if (!cpu_pmu) |
54 | return NULL; | |
181193f3 | 55 | |
4295b898 | 56 | return cpu_pmu->pmu.name; |
181193f3 | 57 | } |
4295b898 | 58 | EXPORT_SYMBOL_GPL(perf_pmu_name); |
181193f3 | 59 | |
feb45d06 | 60 | int perf_num_counters(void) |
929f5199 WD |
61 | { |
62 | int max_events = 0; | |
63 | ||
8be3f9a2 MR |
64 | if (cpu_pmu != NULL) |
65 | max_events = cpu_pmu->num_events; | |
929f5199 WD |
66 | |
67 | return max_events; | |
68 | } | |
3bf101ba MF |
69 | EXPORT_SYMBOL_GPL(perf_num_counters); |
70 | ||
1b8873a0 JI |
71 | #define HW_OP_UNSUPPORTED 0xFFFF |
72 | ||
73 | #define C(_x) \ | |
74 | PERF_COUNT_HW_CACHE_##_x | |
75 | ||
76 | #define CACHE_OP_UNSUPPORTED 0xFFFF | |
77 | ||
1b8873a0 | 78 | static int |
e1f431b5 MR |
79 | armpmu_map_cache_event(const unsigned (*cache_map) |
80 | [PERF_COUNT_HW_CACHE_MAX] | |
81 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
82 | [PERF_COUNT_HW_CACHE_RESULT_MAX], | |
83 | u64 config) | |
1b8873a0 JI |
84 | { |
85 | unsigned int cache_type, cache_op, cache_result, ret; | |
86 | ||
87 | cache_type = (config >> 0) & 0xff; | |
88 | if (cache_type >= PERF_COUNT_HW_CACHE_MAX) | |
89 | return -EINVAL; | |
90 | ||
91 | cache_op = (config >> 8) & 0xff; | |
92 | if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) | |
93 | return -EINVAL; | |
94 | ||
95 | cache_result = (config >> 16) & 0xff; | |
96 | if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | |
97 | return -EINVAL; | |
98 | ||
e1f431b5 | 99 | ret = (int)(*cache_map)[cache_type][cache_op][cache_result]; |
1b8873a0 JI |
100 | |
101 | if (ret == CACHE_OP_UNSUPPORTED) | |
102 | return -ENOENT; | |
103 | ||
104 | return ret; | |
105 | } | |
106 | ||
84fee97a | 107 | static int |
e1f431b5 | 108 | armpmu_map_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config) |
84fee97a | 109 | { |
e1f431b5 MR |
110 | int mapping = (*event_map)[config]; |
111 | return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping; | |
84fee97a WD |
112 | } |
113 | ||
114 | static int | |
e1f431b5 | 115 | armpmu_map_raw_event(u32 raw_event_mask, u64 config) |
84fee97a | 116 | { |
e1f431b5 MR |
117 | return (int)(config & raw_event_mask); |
118 | } | |
119 | ||
120 | static int map_cpu_event(struct perf_event *event, | |
121 | const unsigned (*event_map)[PERF_COUNT_HW_MAX], | |
122 | const unsigned (*cache_map) | |
123 | [PERF_COUNT_HW_CACHE_MAX] | |
124 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
125 | [PERF_COUNT_HW_CACHE_RESULT_MAX], | |
126 | u32 raw_event_mask) | |
127 | { | |
128 | u64 config = event->attr.config; | |
129 | ||
130 | switch (event->attr.type) { | |
131 | case PERF_TYPE_HARDWARE: | |
132 | return armpmu_map_event(event_map, config); | |
133 | case PERF_TYPE_HW_CACHE: | |
134 | return armpmu_map_cache_event(cache_map, config); | |
135 | case PERF_TYPE_RAW: | |
136 | return armpmu_map_raw_event(raw_event_mask, config); | |
137 | } | |
138 | ||
139 | return -ENOENT; | |
84fee97a WD |
140 | } |
141 | ||
0ce47080 | 142 | int |
1b8873a0 JI |
143 | armpmu_event_set_period(struct perf_event *event, |
144 | struct hw_perf_event *hwc, | |
145 | int idx) | |
146 | { | |
8a16b34e | 147 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
e7850595 | 148 | s64 left = local64_read(&hwc->period_left); |
1b8873a0 JI |
149 | s64 period = hwc->sample_period; |
150 | int ret = 0; | |
151 | ||
152 | if (unlikely(left <= -period)) { | |
153 | left = period; | |
e7850595 | 154 | local64_set(&hwc->period_left, left); |
1b8873a0 JI |
155 | hwc->last_period = period; |
156 | ret = 1; | |
157 | } | |
158 | ||
159 | if (unlikely(left <= 0)) { | |
160 | left += period; | |
e7850595 | 161 | local64_set(&hwc->period_left, left); |
1b8873a0 JI |
162 | hwc->last_period = period; |
163 | ret = 1; | |
164 | } | |
165 | ||
166 | if (left > (s64)armpmu->max_period) | |
167 | left = armpmu->max_period; | |
168 | ||
e7850595 | 169 | local64_set(&hwc->prev_count, (u64)-left); |
1b8873a0 JI |
170 | |
171 | armpmu->write_counter(idx, (u64)(-left) & 0xffffffff); | |
172 | ||
173 | perf_event_update_userpage(event); | |
174 | ||
175 | return ret; | |
176 | } | |
177 | ||
0ce47080 | 178 | u64 |
1b8873a0 JI |
179 | armpmu_event_update(struct perf_event *event, |
180 | struct hw_perf_event *hwc, | |
57273471 | 181 | int idx) |
1b8873a0 | 182 | { |
8a16b34e | 183 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
a737823d | 184 | u64 delta, prev_raw_count, new_raw_count; |
1b8873a0 JI |
185 | |
186 | again: | |
e7850595 | 187 | prev_raw_count = local64_read(&hwc->prev_count); |
1b8873a0 JI |
188 | new_raw_count = armpmu->read_counter(idx); |
189 | ||
e7850595 | 190 | if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, |
1b8873a0 JI |
191 | new_raw_count) != prev_raw_count) |
192 | goto again; | |
193 | ||
57273471 | 194 | delta = (new_raw_count - prev_raw_count) & armpmu->max_period; |
1b8873a0 | 195 | |
e7850595 PZ |
196 | local64_add(delta, &event->count); |
197 | local64_sub(delta, &hwc->period_left); | |
1b8873a0 JI |
198 | |
199 | return new_raw_count; | |
200 | } | |
201 | ||
202 | static void | |
a4eaf7f1 | 203 | armpmu_read(struct perf_event *event) |
1b8873a0 | 204 | { |
1b8873a0 | 205 | struct hw_perf_event *hwc = &event->hw; |
1b8873a0 | 206 | |
a4eaf7f1 PZ |
207 | /* Don't read disabled counters! */ |
208 | if (hwc->idx < 0) | |
209 | return; | |
1b8873a0 | 210 | |
57273471 | 211 | armpmu_event_update(event, hwc, hwc->idx); |
1b8873a0 JI |
212 | } |
213 | ||
214 | static void | |
a4eaf7f1 | 215 | armpmu_stop(struct perf_event *event, int flags) |
1b8873a0 | 216 | { |
8a16b34e | 217 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
1b8873a0 JI |
218 | struct hw_perf_event *hwc = &event->hw; |
219 | ||
a4eaf7f1 PZ |
220 | /* |
221 | * ARM pmu always has to update the counter, so ignore | |
222 | * PERF_EF_UPDATE, see comments in armpmu_start(). | |
223 | */ | |
224 | if (!(hwc->state & PERF_HES_STOPPED)) { | |
225 | armpmu->disable(hwc, hwc->idx); | |
57273471 | 226 | armpmu_event_update(event, hwc, hwc->idx); |
a4eaf7f1 PZ |
227 | hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; |
228 | } | |
1b8873a0 JI |
229 | } |
230 | ||
231 | static void | |
a4eaf7f1 | 232 | armpmu_start(struct perf_event *event, int flags) |
1b8873a0 | 233 | { |
8a16b34e | 234 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
1b8873a0 JI |
235 | struct hw_perf_event *hwc = &event->hw; |
236 | ||
a4eaf7f1 PZ |
237 | /* |
238 | * ARM pmu always has to reprogram the period, so ignore | |
239 | * PERF_EF_RELOAD, see the comment below. | |
240 | */ | |
241 | if (flags & PERF_EF_RELOAD) | |
242 | WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE)); | |
243 | ||
244 | hwc->state = 0; | |
1b8873a0 JI |
245 | /* |
246 | * Set the period again. Some counters can't be stopped, so when we | |
a4eaf7f1 | 247 | * were stopped we simply disabled the IRQ source and the counter |
1b8873a0 JI |
248 | * may have been left counting. If we don't do this step then we may |
249 | * get an interrupt too soon or *way* too late if the overflow has | |
250 | * happened since disabling. | |
251 | */ | |
252 | armpmu_event_set_period(event, hwc, hwc->idx); | |
253 | armpmu->enable(hwc, hwc->idx); | |
254 | } | |
255 | ||
a4eaf7f1 PZ |
256 | static void |
257 | armpmu_del(struct perf_event *event, int flags) | |
258 | { | |
8a16b34e | 259 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
8be3f9a2 | 260 | struct pmu_hw_events *hw_events = armpmu->get_hw_events(); |
a4eaf7f1 PZ |
261 | struct hw_perf_event *hwc = &event->hw; |
262 | int idx = hwc->idx; | |
263 | ||
264 | WARN_ON(idx < 0); | |
265 | ||
a4eaf7f1 | 266 | armpmu_stop(event, PERF_EF_UPDATE); |
8be3f9a2 MR |
267 | hw_events->events[idx] = NULL; |
268 | clear_bit(idx, hw_events->used_mask); | |
a4eaf7f1 PZ |
269 | |
270 | perf_event_update_userpage(event); | |
271 | } | |
272 | ||
1b8873a0 | 273 | static int |
a4eaf7f1 | 274 | armpmu_add(struct perf_event *event, int flags) |
1b8873a0 | 275 | { |
8a16b34e | 276 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
8be3f9a2 | 277 | struct pmu_hw_events *hw_events = armpmu->get_hw_events(); |
1b8873a0 JI |
278 | struct hw_perf_event *hwc = &event->hw; |
279 | int idx; | |
280 | int err = 0; | |
281 | ||
33696fc0 | 282 | perf_pmu_disable(event->pmu); |
24cd7f54 | 283 | |
1b8873a0 | 284 | /* If we don't have a space for the counter then finish early. */ |
8be3f9a2 | 285 | idx = armpmu->get_event_idx(hw_events, hwc); |
1b8873a0 JI |
286 | if (idx < 0) { |
287 | err = idx; | |
288 | goto out; | |
289 | } | |
290 | ||
291 | /* | |
292 | * If there is an event in the counter we are going to use then make | |
293 | * sure it is disabled. | |
294 | */ | |
295 | event->hw.idx = idx; | |
296 | armpmu->disable(hwc, idx); | |
8be3f9a2 | 297 | hw_events->events[idx] = event; |
1b8873a0 | 298 | |
a4eaf7f1 PZ |
299 | hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE; |
300 | if (flags & PERF_EF_START) | |
301 | armpmu_start(event, PERF_EF_RELOAD); | |
1b8873a0 JI |
302 | |
303 | /* Propagate our changes to the userspace mapping. */ | |
304 | perf_event_update_userpage(event); | |
305 | ||
306 | out: | |
33696fc0 | 307 | perf_pmu_enable(event->pmu); |
1b8873a0 JI |
308 | return err; |
309 | } | |
310 | ||
1b8873a0 | 311 | static int |
8be3f9a2 | 312 | validate_event(struct pmu_hw_events *hw_events, |
1b8873a0 JI |
313 | struct perf_event *event) |
314 | { | |
8a16b34e | 315 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
1b8873a0 | 316 | struct hw_perf_event fake_event = event->hw; |
7b9f72c6 | 317 | struct pmu *leader_pmu = event->group_leader->pmu; |
1b8873a0 | 318 | |
7b9f72c6 | 319 | if (event->pmu != leader_pmu || event->state <= PERF_EVENT_STATE_OFF) |
65b4711f | 320 | return 1; |
1b8873a0 | 321 | |
8be3f9a2 | 322 | return armpmu->get_event_idx(hw_events, &fake_event) >= 0; |
1b8873a0 JI |
323 | } |
324 | ||
325 | static int | |
326 | validate_group(struct perf_event *event) | |
327 | { | |
328 | struct perf_event *sibling, *leader = event->group_leader; | |
8be3f9a2 | 329 | struct pmu_hw_events fake_pmu; |
bce34d14 | 330 | DECLARE_BITMAP(fake_used_mask, ARMPMU_MAX_HWEVENTS); |
1b8873a0 | 331 | |
bce34d14 WD |
332 | /* |
333 | * Initialise the fake PMU. We only need to populate the | |
334 | * used_mask for the purposes of validation. | |
335 | */ | |
336 | memset(fake_used_mask, 0, sizeof(fake_used_mask)); | |
337 | fake_pmu.used_mask = fake_used_mask; | |
1b8873a0 JI |
338 | |
339 | if (!validate_event(&fake_pmu, leader)) | |
aa2bc1ad | 340 | return -EINVAL; |
1b8873a0 JI |
341 | |
342 | list_for_each_entry(sibling, &leader->sibling_list, group_entry) { | |
343 | if (!validate_event(&fake_pmu, sibling)) | |
aa2bc1ad | 344 | return -EINVAL; |
1b8873a0 JI |
345 | } |
346 | ||
347 | if (!validate_event(&fake_pmu, event)) | |
aa2bc1ad | 348 | return -EINVAL; |
1b8873a0 JI |
349 | |
350 | return 0; | |
351 | } | |
352 | ||
0e25a5c9 RV |
353 | static irqreturn_t armpmu_platform_irq(int irq, void *dev) |
354 | { | |
8a16b34e | 355 | struct arm_pmu *armpmu = (struct arm_pmu *) dev; |
a9356a04 MR |
356 | struct platform_device *plat_device = armpmu->plat_device; |
357 | struct arm_pmu_platdata *plat = dev_get_platdata(&plat_device->dev); | |
0e25a5c9 RV |
358 | |
359 | return plat->handle_irq(irq, dev, armpmu->handle_irq); | |
360 | } | |
361 | ||
0b390e21 | 362 | static void |
8a16b34e | 363 | armpmu_release_hardware(struct arm_pmu *armpmu) |
0b390e21 WD |
364 | { |
365 | int i, irq, irqs; | |
a9356a04 | 366 | struct platform_device *pmu_device = armpmu->plat_device; |
0b390e21 WD |
367 | |
368 | irqs = min(pmu_device->num_resources, num_possible_cpus()); | |
369 | ||
370 | for (i = 0; i < irqs; ++i) { | |
371 | if (!cpumask_test_and_clear_cpu(i, &armpmu->active_irqs)) | |
372 | continue; | |
373 | irq = platform_get_irq(pmu_device, i); | |
7be2958e | 374 | if (irq >= 0) |
8a16b34e | 375 | free_irq(irq, armpmu); |
0b390e21 WD |
376 | } |
377 | ||
7be2958e | 378 | pm_runtime_put_sync(&pmu_device->dev); |
0b390e21 WD |
379 | } |
380 | ||
1b8873a0 | 381 | static int |
8a16b34e | 382 | armpmu_reserve_hardware(struct arm_pmu *armpmu) |
1b8873a0 | 383 | { |
0e25a5c9 RV |
384 | struct arm_pmu_platdata *plat; |
385 | irq_handler_t handle_irq; | |
b0e89590 | 386 | int i, err, irq, irqs; |
a9356a04 | 387 | struct platform_device *pmu_device = armpmu->plat_device; |
1b8873a0 | 388 | |
e5a21327 WD |
389 | if (!pmu_device) |
390 | return -ENODEV; | |
391 | ||
0e25a5c9 RV |
392 | plat = dev_get_platdata(&pmu_device->dev); |
393 | if (plat && plat->handle_irq) | |
394 | handle_irq = armpmu_platform_irq; | |
395 | else | |
396 | handle_irq = armpmu->handle_irq; | |
397 | ||
0b390e21 | 398 | irqs = min(pmu_device->num_resources, num_possible_cpus()); |
b0e89590 | 399 | if (irqs < 1) { |
1b8873a0 JI |
400 | pr_err("no irqs for PMUs defined\n"); |
401 | return -ENODEV; | |
402 | } | |
403 | ||
7be2958e JH |
404 | pm_runtime_get_sync(&pmu_device->dev); |
405 | ||
b0e89590 | 406 | for (i = 0; i < irqs; ++i) { |
0b390e21 | 407 | err = 0; |
49c006b9 WD |
408 | irq = platform_get_irq(pmu_device, i); |
409 | if (irq < 0) | |
410 | continue; | |
411 | ||
b0e89590 WD |
412 | /* |
413 | * If we have a single PMU interrupt that we can't shift, | |
414 | * assume that we're running on a uniprocessor machine and | |
0b390e21 | 415 | * continue. Otherwise, continue without this interrupt. |
b0e89590 | 416 | */ |
0b390e21 WD |
417 | if (irq_set_affinity(irq, cpumask_of(i)) && irqs > 1) { |
418 | pr_warning("unable to set irq affinity (irq=%d, cpu=%u)\n", | |
419 | irq, i); | |
420 | continue; | |
b0e89590 WD |
421 | } |
422 | ||
0e25a5c9 | 423 | err = request_irq(irq, handle_irq, |
ddee87f2 | 424 | IRQF_DISABLED | IRQF_NOBALANCING, |
8a16b34e | 425 | "arm-pmu", armpmu); |
1b8873a0 | 426 | if (err) { |
b0e89590 WD |
427 | pr_err("unable to request IRQ%d for ARM PMU counters\n", |
428 | irq); | |
8a16b34e | 429 | armpmu_release_hardware(armpmu); |
0b390e21 | 430 | return err; |
7be2958e | 431 | } |
1b8873a0 | 432 | |
0b390e21 | 433 | cpumask_set_cpu(i, &armpmu->active_irqs); |
49c006b9 | 434 | } |
1b8873a0 | 435 | |
0b390e21 | 436 | return 0; |
1b8873a0 JI |
437 | } |
438 | ||
1b8873a0 JI |
439 | static void |
440 | hw_perf_event_destroy(struct perf_event *event) | |
441 | { | |
8a16b34e | 442 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
03b7898d MR |
443 | atomic_t *active_events = &armpmu->active_events; |
444 | struct mutex *pmu_reserve_mutex = &armpmu->reserve_mutex; | |
445 | ||
446 | if (atomic_dec_and_mutex_lock(active_events, pmu_reserve_mutex)) { | |
8a16b34e | 447 | armpmu_release_hardware(armpmu); |
03b7898d | 448 | mutex_unlock(pmu_reserve_mutex); |
1b8873a0 JI |
449 | } |
450 | } | |
451 | ||
05d22fde WD |
452 | static int |
453 | event_requires_mode_exclusion(struct perf_event_attr *attr) | |
454 | { | |
455 | return attr->exclude_idle || attr->exclude_user || | |
456 | attr->exclude_kernel || attr->exclude_hv; | |
457 | } | |
458 | ||
1b8873a0 JI |
459 | static int |
460 | __hw_perf_event_init(struct perf_event *event) | |
461 | { | |
8a16b34e | 462 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
1b8873a0 JI |
463 | struct hw_perf_event *hwc = &event->hw; |
464 | int mapping, err; | |
465 | ||
e1f431b5 | 466 | mapping = armpmu->map_event(event); |
1b8873a0 JI |
467 | |
468 | if (mapping < 0) { | |
469 | pr_debug("event %x:%llx not supported\n", event->attr.type, | |
470 | event->attr.config); | |
471 | return mapping; | |
472 | } | |
473 | ||
05d22fde WD |
474 | /* |
475 | * We don't assign an index until we actually place the event onto | |
476 | * hardware. Use -1 to signify that we haven't decided where to put it | |
477 | * yet. For SMP systems, each core has it's own PMU so we can't do any | |
478 | * clever allocation or constraints checking at this point. | |
479 | */ | |
480 | hwc->idx = -1; | |
481 | hwc->config_base = 0; | |
482 | hwc->config = 0; | |
483 | hwc->event_base = 0; | |
484 | ||
1b8873a0 JI |
485 | /* |
486 | * Check whether we need to exclude the counter from certain modes. | |
1b8873a0 | 487 | */ |
05d22fde WD |
488 | if ((!armpmu->set_event_filter || |
489 | armpmu->set_event_filter(hwc, &event->attr)) && | |
490 | event_requires_mode_exclusion(&event->attr)) { | |
1b8873a0 JI |
491 | pr_debug("ARM performance counters do not support " |
492 | "mode exclusion\n"); | |
fdeb8e35 | 493 | return -EOPNOTSUPP; |
1b8873a0 JI |
494 | } |
495 | ||
496 | /* | |
05d22fde | 497 | * Store the event encoding into the config_base field. |
1b8873a0 | 498 | */ |
05d22fde | 499 | hwc->config_base |= (unsigned long)mapping; |
1b8873a0 JI |
500 | |
501 | if (!hwc->sample_period) { | |
57273471 WD |
502 | /* |
503 | * For non-sampling runs, limit the sample_period to half | |
504 | * of the counter width. That way, the new counter value | |
505 | * is far less likely to overtake the previous one unless | |
506 | * you have some serious IRQ latency issues. | |
507 | */ | |
508 | hwc->sample_period = armpmu->max_period >> 1; | |
1b8873a0 | 509 | hwc->last_period = hwc->sample_period; |
e7850595 | 510 | local64_set(&hwc->period_left, hwc->sample_period); |
1b8873a0 JI |
511 | } |
512 | ||
513 | err = 0; | |
514 | if (event->group_leader != event) { | |
515 | err = validate_group(event); | |
516 | if (err) | |
517 | return -EINVAL; | |
518 | } | |
519 | ||
520 | return err; | |
521 | } | |
522 | ||
b0a873eb | 523 | static int armpmu_event_init(struct perf_event *event) |
1b8873a0 | 524 | { |
8a16b34e | 525 | struct arm_pmu *armpmu = to_arm_pmu(event->pmu); |
1b8873a0 | 526 | int err = 0; |
03b7898d | 527 | atomic_t *active_events = &armpmu->active_events; |
1b8873a0 | 528 | |
2481c5fa SE |
529 | /* does not support taken branch sampling */ |
530 | if (has_branch_stack(event)) | |
531 | return -EOPNOTSUPP; | |
532 | ||
e1f431b5 | 533 | if (armpmu->map_event(event) == -ENOENT) |
b0a873eb | 534 | return -ENOENT; |
b0a873eb | 535 | |
1b8873a0 JI |
536 | event->destroy = hw_perf_event_destroy; |
537 | ||
03b7898d MR |
538 | if (!atomic_inc_not_zero(active_events)) { |
539 | mutex_lock(&armpmu->reserve_mutex); | |
540 | if (atomic_read(active_events) == 0) | |
8a16b34e | 541 | err = armpmu_reserve_hardware(armpmu); |
1b8873a0 JI |
542 | |
543 | if (!err) | |
03b7898d MR |
544 | atomic_inc(active_events); |
545 | mutex_unlock(&armpmu->reserve_mutex); | |
1b8873a0 JI |
546 | } |
547 | ||
548 | if (err) | |
b0a873eb | 549 | return err; |
1b8873a0 JI |
550 | |
551 | err = __hw_perf_event_init(event); | |
552 | if (err) | |
553 | hw_perf_event_destroy(event); | |
554 | ||
b0a873eb | 555 | return err; |
1b8873a0 JI |
556 | } |
557 | ||
a4eaf7f1 | 558 | static void armpmu_enable(struct pmu *pmu) |
1b8873a0 | 559 | { |
8be3f9a2 | 560 | struct arm_pmu *armpmu = to_arm_pmu(pmu); |
8be3f9a2 | 561 | struct pmu_hw_events *hw_events = armpmu->get_hw_events(); |
7325eaec | 562 | int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events); |
1b8873a0 | 563 | |
f4f38430 WD |
564 | if (enabled) |
565 | armpmu->start(); | |
1b8873a0 JI |
566 | } |
567 | ||
a4eaf7f1 | 568 | static void armpmu_disable(struct pmu *pmu) |
1b8873a0 | 569 | { |
8a16b34e | 570 | struct arm_pmu *armpmu = to_arm_pmu(pmu); |
48957155 | 571 | armpmu->stop(); |
1b8873a0 JI |
572 | } |
573 | ||
7be2958e JH |
574 | #ifdef CONFIG_PM_RUNTIME |
575 | static int armpmu_runtime_resume(struct device *dev) | |
576 | { | |
577 | struct arm_pmu_platdata *plat = dev_get_platdata(dev); | |
578 | ||
579 | if (plat && plat->runtime_resume) | |
580 | return plat->runtime_resume(dev); | |
581 | ||
582 | return 0; | |
583 | } | |
584 | ||
585 | static int armpmu_runtime_suspend(struct device *dev) | |
586 | { | |
587 | struct arm_pmu_platdata *plat = dev_get_platdata(dev); | |
588 | ||
589 | if (plat && plat->runtime_suspend) | |
590 | return plat->runtime_suspend(dev); | |
591 | ||
592 | return 0; | |
593 | } | |
594 | #endif | |
595 | ||
03b7898d MR |
596 | static void __init armpmu_init(struct arm_pmu *armpmu) |
597 | { | |
598 | atomic_set(&armpmu->active_events, 0); | |
599 | mutex_init(&armpmu->reserve_mutex); | |
8a16b34e MR |
600 | |
601 | armpmu->pmu = (struct pmu) { | |
602 | .pmu_enable = armpmu_enable, | |
603 | .pmu_disable = armpmu_disable, | |
604 | .event_init = armpmu_event_init, | |
605 | .add = armpmu_add, | |
606 | .del = armpmu_del, | |
607 | .start = armpmu_start, | |
608 | .stop = armpmu_stop, | |
609 | .read = armpmu_read, | |
610 | }; | |
611 | } | |
612 | ||
0ce47080 | 613 | int __init armpmu_register(struct arm_pmu *armpmu, char *name, int type) |
8a16b34e MR |
614 | { |
615 | armpmu_init(armpmu); | |
616 | return perf_pmu_register(&armpmu->pmu, name, type); | |
03b7898d MR |
617 | } |
618 | ||
43eab878 WD |
619 | /* Include the PMU-specific implementations. */ |
620 | #include "perf_event_xscale.c" | |
621 | #include "perf_event_v6.c" | |
622 | #include "perf_event_v7.c" | |
49e6a32f | 623 | |
574b69cb WD |
624 | /* |
625 | * Ensure the PMU has sane values out of reset. | |
626 | * This requires SMP to be available, so exists as a separate initcall. | |
627 | */ | |
628 | static int __init | |
8be3f9a2 | 629 | cpu_pmu_reset(void) |
574b69cb | 630 | { |
8be3f9a2 MR |
631 | if (cpu_pmu && cpu_pmu->reset) |
632 | return on_each_cpu(cpu_pmu->reset, NULL, 1); | |
574b69cb WD |
633 | return 0; |
634 | } | |
8be3f9a2 | 635 | arch_initcall(cpu_pmu_reset); |
574b69cb | 636 | |
b0e89590 WD |
637 | /* |
638 | * PMU platform driver and devicetree bindings. | |
639 | */ | |
640 | static struct of_device_id armpmu_of_device_ids[] = { | |
50243efd | 641 | {.compatible = "arm,cortex-a15-pmu"}, |
b0e89590 WD |
642 | {.compatible = "arm,cortex-a9-pmu"}, |
643 | {.compatible = "arm,cortex-a8-pmu"}, | |
50243efd WD |
644 | {.compatible = "arm,cortex-a7-pmu"}, |
645 | {.compatible = "arm,cortex-a5-pmu"}, | |
646 | {.compatible = "arm,arm11mpcore-pmu"}, | |
b0e89590 | 647 | {.compatible = "arm,arm1176-pmu"}, |
50243efd | 648 | {.compatible = "arm,arm1136-pmu"}, |
b0e89590 WD |
649 | {}, |
650 | }; | |
651 | ||
652 | static struct platform_device_id armpmu_plat_device_ids[] = { | |
653 | {.name = "arm-pmu"}, | |
654 | {}, | |
655 | }; | |
656 | ||
657 | static int __devinit armpmu_device_probe(struct platform_device *pdev) | |
658 | { | |
6bd05409 WD |
659 | if (!cpu_pmu) |
660 | return -ENODEV; | |
661 | ||
8be3f9a2 | 662 | cpu_pmu->plat_device = pdev; |
b0e89590 WD |
663 | return 0; |
664 | } | |
665 | ||
7be2958e JH |
666 | static const struct dev_pm_ops armpmu_dev_pm_ops = { |
667 | SET_RUNTIME_PM_OPS(armpmu_runtime_suspend, armpmu_runtime_resume, NULL) | |
668 | }; | |
669 | ||
b0e89590 WD |
670 | static struct platform_driver armpmu_driver = { |
671 | .driver = { | |
672 | .name = "arm-pmu", | |
7be2958e | 673 | .pm = &armpmu_dev_pm_ops, |
b0e89590 WD |
674 | .of_match_table = armpmu_of_device_ids, |
675 | }, | |
676 | .probe = armpmu_device_probe, | |
677 | .id_table = armpmu_plat_device_ids, | |
678 | }; | |
679 | ||
680 | static int __init register_pmu_driver(void) | |
681 | { | |
682 | return platform_driver_register(&armpmu_driver); | |
683 | } | |
684 | device_initcall(register_pmu_driver); | |
685 | ||
8be3f9a2 | 686 | static struct pmu_hw_events *armpmu_get_cpu_events(void) |
92f701e1 MR |
687 | { |
688 | return &__get_cpu_var(cpu_hw_events); | |
689 | } | |
690 | ||
691 | static void __init cpu_pmu_init(struct arm_pmu *armpmu) | |
692 | { | |
0f78d2d5 MR |
693 | int cpu; |
694 | for_each_possible_cpu(cpu) { | |
8be3f9a2 | 695 | struct pmu_hw_events *events = &per_cpu(cpu_hw_events, cpu); |
3fc2c830 MR |
696 | events->events = per_cpu(hw_events, cpu); |
697 | events->used_mask = per_cpu(used_mask, cpu); | |
0f78d2d5 MR |
698 | raw_spin_lock_init(&events->pmu_lock); |
699 | } | |
92f701e1 MR |
700 | armpmu->get_hw_events = armpmu_get_cpu_events; |
701 | } | |
702 | ||
a0feb6db LP |
703 | /* |
704 | * PMU hardware loses all context when a CPU goes offline. | |
705 | * When a CPU is hotplugged back in, since some hardware registers are | |
706 | * UNKNOWN at reset, the PMU must be explicitly reset to avoid reading | |
707 | * junk values out of them. | |
708 | */ | |
709 | static int __cpuinit pmu_cpu_notify(struct notifier_block *b, | |
710 | unsigned long action, void *hcpu) | |
711 | { | |
712 | if ((action & ~CPU_TASKS_FROZEN) != CPU_STARTING) | |
713 | return NOTIFY_DONE; | |
714 | ||
715 | if (cpu_pmu && cpu_pmu->reset) | |
716 | cpu_pmu->reset(NULL); | |
717 | ||
718 | return NOTIFY_OK; | |
719 | } | |
720 | ||
721 | static struct notifier_block __cpuinitdata pmu_cpu_notifier = { | |
722 | .notifier_call = pmu_cpu_notify, | |
723 | }; | |
724 | ||
b0e89590 WD |
725 | /* |
726 | * CPU PMU identification and registration. | |
727 | */ | |
1b8873a0 JI |
728 | static int __init |
729 | init_hw_perf_events(void) | |
730 | { | |
731 | unsigned long cpuid = read_cpuid_id(); | |
732 | unsigned long implementor = (cpuid & 0xFF000000) >> 24; | |
733 | unsigned long part_number = (cpuid & 0xFFF0); | |
734 | ||
49e6a32f | 735 | /* ARM Ltd CPUs. */ |
1b8873a0 JI |
736 | if (0x41 == implementor) { |
737 | switch (part_number) { | |
738 | case 0xB360: /* ARM1136 */ | |
739 | case 0xB560: /* ARM1156 */ | |
740 | case 0xB760: /* ARM1176 */ | |
8be3f9a2 | 741 | cpu_pmu = armv6pmu_init(); |
1b8873a0 JI |
742 | break; |
743 | case 0xB020: /* ARM11mpcore */ | |
8be3f9a2 | 744 | cpu_pmu = armv6mpcore_pmu_init(); |
1b8873a0 | 745 | break; |
796d1295 | 746 | case 0xC080: /* Cortex-A8 */ |
8be3f9a2 | 747 | cpu_pmu = armv7_a8_pmu_init(); |
796d1295 JP |
748 | break; |
749 | case 0xC090: /* Cortex-A9 */ | |
8be3f9a2 | 750 | cpu_pmu = armv7_a9_pmu_init(); |
796d1295 | 751 | break; |
0c205cbe | 752 | case 0xC050: /* Cortex-A5 */ |
8be3f9a2 | 753 | cpu_pmu = armv7_a5_pmu_init(); |
0c205cbe | 754 | break; |
14abd038 | 755 | case 0xC0F0: /* Cortex-A15 */ |
8be3f9a2 | 756 | cpu_pmu = armv7_a15_pmu_init(); |
14abd038 | 757 | break; |
d33c88c6 WD |
758 | case 0xC070: /* Cortex-A7 */ |
759 | cpu_pmu = armv7_a7_pmu_init(); | |
760 | break; | |
49e6a32f WD |
761 | } |
762 | /* Intel CPUs [xscale]. */ | |
763 | } else if (0x69 == implementor) { | |
764 | part_number = (cpuid >> 13) & 0x7; | |
765 | switch (part_number) { | |
766 | case 1: | |
8be3f9a2 | 767 | cpu_pmu = xscale1pmu_init(); |
49e6a32f WD |
768 | break; |
769 | case 2: | |
8be3f9a2 | 770 | cpu_pmu = xscale2pmu_init(); |
49e6a32f | 771 | break; |
1b8873a0 JI |
772 | } |
773 | } | |
774 | ||
8be3f9a2 | 775 | if (cpu_pmu) { |
796d1295 | 776 | pr_info("enabled with %s PMU driver, %d counters available\n", |
8be3f9a2 MR |
777 | cpu_pmu->name, cpu_pmu->num_events); |
778 | cpu_pmu_init(cpu_pmu); | |
a0feb6db | 779 | register_cpu_notifier(&pmu_cpu_notifier); |
4295b898 | 780 | armpmu_register(cpu_pmu, cpu_pmu->name, PERF_TYPE_RAW); |
49e6a32f WD |
781 | } else { |
782 | pr_info("no hardware support available\n"); | |
49e6a32f | 783 | } |
1b8873a0 JI |
784 | |
785 | return 0; | |
786 | } | |
004417a6 | 787 | early_initcall(init_hw_perf_events); |
1b8873a0 JI |
788 | |
789 | /* | |
790 | * Callchain handling code. | |
791 | */ | |
1b8873a0 JI |
792 | |
793 | /* | |
794 | * The registers we're interested in are at the end of the variable | |
795 | * length saved register structure. The fp points at the end of this | |
796 | * structure so the address of this struct is: | |
797 | * (struct frame_tail *)(xxx->fp)-1 | |
798 | * | |
799 | * This code has been adapted from the ARM OProfile support. | |
800 | */ | |
801 | struct frame_tail { | |
4d6b7a77 WD |
802 | struct frame_tail __user *fp; |
803 | unsigned long sp; | |
804 | unsigned long lr; | |
1b8873a0 JI |
805 | } __attribute__((packed)); |
806 | ||
807 | /* | |
808 | * Get the return address for a single stackframe and return a pointer to the | |
809 | * next frame tail. | |
810 | */ | |
4d6b7a77 WD |
811 | static struct frame_tail __user * |
812 | user_backtrace(struct frame_tail __user *tail, | |
1b8873a0 JI |
813 | struct perf_callchain_entry *entry) |
814 | { | |
815 | struct frame_tail buftail; | |
816 | ||
817 | /* Also check accessibility of one struct frame_tail beyond */ | |
818 | if (!access_ok(VERIFY_READ, tail, sizeof(buftail))) | |
819 | return NULL; | |
820 | if (__copy_from_user_inatomic(&buftail, tail, sizeof(buftail))) | |
821 | return NULL; | |
822 | ||
70791ce9 | 823 | perf_callchain_store(entry, buftail.lr); |
1b8873a0 JI |
824 | |
825 | /* | |
826 | * Frame pointers should strictly progress back up the stack | |
827 | * (towards higher addresses). | |
828 | */ | |
cb06199b | 829 | if (tail + 1 >= buftail.fp) |
1b8873a0 JI |
830 | return NULL; |
831 | ||
832 | return buftail.fp - 1; | |
833 | } | |
834 | ||
56962b44 FW |
835 | void |
836 | perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs) | |
1b8873a0 | 837 | { |
4d6b7a77 | 838 | struct frame_tail __user *tail; |
1b8873a0 | 839 | |
1b8873a0 | 840 | |
4d6b7a77 | 841 | tail = (struct frame_tail __user *)regs->ARM_fp - 1; |
1b8873a0 | 842 | |
860ad782 SR |
843 | while ((entry->nr < PERF_MAX_STACK_DEPTH) && |
844 | tail && !((unsigned long)tail & 0x3)) | |
1b8873a0 JI |
845 | tail = user_backtrace(tail, entry); |
846 | } | |
847 | ||
848 | /* | |
849 | * Gets called by walk_stackframe() for every stackframe. This will be called | |
850 | * whist unwinding the stackframe and is like a subroutine return so we use | |
851 | * the PC. | |
852 | */ | |
853 | static int | |
854 | callchain_trace(struct stackframe *fr, | |
855 | void *data) | |
856 | { | |
857 | struct perf_callchain_entry *entry = data; | |
70791ce9 | 858 | perf_callchain_store(entry, fr->pc); |
1b8873a0 JI |
859 | return 0; |
860 | } | |
861 | ||
56962b44 FW |
862 | void |
863 | perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs) | |
1b8873a0 JI |
864 | { |
865 | struct stackframe fr; | |
866 | ||
1b8873a0 JI |
867 | fr.fp = regs->ARM_fp; |
868 | fr.sp = regs->ARM_sp; | |
869 | fr.lr = regs->ARM_lr; | |
870 | fr.pc = regs->ARM_pc; | |
871 | walk_stackframe(&fr, callchain_trace, entry); | |
872 | } |