Commit | Line | Data |
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1b8873a0 JI |
1 | #undef DEBUG |
2 | ||
3 | /* | |
4 | * ARM performance counter support. | |
5 | * | |
6 | * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles | |
43eab878 | 7 | * Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com> |
796d1295 | 8 | * |
1b8873a0 JI |
9 | * This code is based on the sparc64 perf event code, which is in turn based |
10 | * on the x86 code. Callchain code is based on the ARM OProfile backtrace | |
11 | * code. | |
12 | */ | |
13 | #define pr_fmt(fmt) "hw perfevents: " fmt | |
14 | ||
15 | #include <linux/interrupt.h> | |
16 | #include <linux/kernel.h> | |
181193f3 | 17 | #include <linux/module.h> |
1b8873a0 | 18 | #include <linux/perf_event.h> |
49c006b9 | 19 | #include <linux/platform_device.h> |
1b8873a0 JI |
20 | #include <linux/spinlock.h> |
21 | #include <linux/uaccess.h> | |
22 | ||
23 | #include <asm/cputype.h> | |
24 | #include <asm/irq.h> | |
25 | #include <asm/irq_regs.h> | |
26 | #include <asm/pmu.h> | |
27 | #include <asm/stacktrace.h> | |
28 | ||
49c006b9 | 29 | static struct platform_device *pmu_device; |
1b8873a0 JI |
30 | |
31 | /* | |
32 | * Hardware lock to serialize accesses to PMU registers. Needed for the | |
33 | * read/modify/write sequences. | |
34 | */ | |
961ec6da | 35 | static DEFINE_RAW_SPINLOCK(pmu_lock); |
1b8873a0 JI |
36 | |
37 | /* | |
ecf5a893 | 38 | * ARMv6 supports a maximum of 3 events, starting from index 0. If we add |
1b8873a0 JI |
39 | * another platform that supports more, we need to increase this to be the |
40 | * largest of all platforms. | |
796d1295 JP |
41 | * |
42 | * ARMv7 supports up to 32 events: | |
43 | * cycle counter CCNT + 31 events counters CNT0..30. | |
44 | * Cortex-A8 has 1+4 counters, Cortex-A9 has 1+6 counters. | |
1b8873a0 | 45 | */ |
ecf5a893 | 46 | #define ARMPMU_MAX_HWEVENTS 32 |
1b8873a0 JI |
47 | |
48 | /* The events for a given CPU. */ | |
49 | struct cpu_hw_events { | |
50 | /* | |
ecf5a893 | 51 | * The events that are active on the CPU for the given index. |
1b8873a0 JI |
52 | */ |
53 | struct perf_event *events[ARMPMU_MAX_HWEVENTS]; | |
54 | ||
55 | /* | |
56 | * A 1 bit for an index indicates that the counter is being used for | |
57 | * an event. A 0 means that the counter can be used. | |
58 | */ | |
59 | unsigned long used_mask[BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)]; | |
60 | ||
61 | /* | |
62 | * A 1 bit for an index indicates that the counter is actively being | |
63 | * used. | |
64 | */ | |
65 | unsigned long active_mask[BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)]; | |
66 | }; | |
4d6b7a77 | 67 | static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events); |
181193f3 | 68 | |
1b8873a0 | 69 | struct arm_pmu { |
181193f3 | 70 | enum arm_perf_pmu_ids id; |
0b390e21 | 71 | cpumask_t active_irqs; |
62994831 | 72 | const char *name; |
1b8873a0 JI |
73 | irqreturn_t (*handle_irq)(int irq_num, void *dev); |
74 | void (*enable)(struct hw_perf_event *evt, int idx); | |
75 | void (*disable)(struct hw_perf_event *evt, int idx); | |
1b8873a0 JI |
76 | int (*get_event_idx)(struct cpu_hw_events *cpuc, |
77 | struct hw_perf_event *hwc); | |
05d22fde WD |
78 | int (*set_event_filter)(struct hw_perf_event *evt, |
79 | struct perf_event_attr *attr); | |
1b8873a0 JI |
80 | u32 (*read_counter)(int idx); |
81 | void (*write_counter)(int idx, u32 val); | |
82 | void (*start)(void); | |
83 | void (*stop)(void); | |
574b69cb | 84 | void (*reset)(void *); |
84fee97a WD |
85 | const unsigned (*cache_map)[PERF_COUNT_HW_CACHE_MAX] |
86 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
87 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
88 | const unsigned (*event_map)[PERF_COUNT_HW_MAX]; | |
89 | u32 raw_event_mask; | |
1b8873a0 JI |
90 | int num_events; |
91 | u64 max_period; | |
92 | }; | |
93 | ||
94 | /* Set at runtime when we know what CPU type we are. */ | |
a6c93afe | 95 | static struct arm_pmu *armpmu; |
1b8873a0 | 96 | |
181193f3 WD |
97 | enum arm_perf_pmu_ids |
98 | armpmu_get_pmu_id(void) | |
99 | { | |
100 | int id = -ENODEV; | |
101 | ||
102 | if (armpmu != NULL) | |
103 | id = armpmu->id; | |
104 | ||
105 | return id; | |
106 | } | |
107 | EXPORT_SYMBOL_GPL(armpmu_get_pmu_id); | |
108 | ||
929f5199 WD |
109 | int |
110 | armpmu_get_max_events(void) | |
111 | { | |
112 | int max_events = 0; | |
113 | ||
114 | if (armpmu != NULL) | |
115 | max_events = armpmu->num_events; | |
116 | ||
117 | return max_events; | |
118 | } | |
119 | EXPORT_SYMBOL_GPL(armpmu_get_max_events); | |
120 | ||
3bf101ba MF |
121 | int perf_num_counters(void) |
122 | { | |
123 | return armpmu_get_max_events(); | |
124 | } | |
125 | EXPORT_SYMBOL_GPL(perf_num_counters); | |
126 | ||
1b8873a0 JI |
127 | #define HW_OP_UNSUPPORTED 0xFFFF |
128 | ||
129 | #define C(_x) \ | |
130 | PERF_COUNT_HW_CACHE_##_x | |
131 | ||
132 | #define CACHE_OP_UNSUPPORTED 0xFFFF | |
133 | ||
1b8873a0 JI |
134 | static int |
135 | armpmu_map_cache_event(u64 config) | |
136 | { | |
137 | unsigned int cache_type, cache_op, cache_result, ret; | |
138 | ||
139 | cache_type = (config >> 0) & 0xff; | |
140 | if (cache_type >= PERF_COUNT_HW_CACHE_MAX) | |
141 | return -EINVAL; | |
142 | ||
143 | cache_op = (config >> 8) & 0xff; | |
144 | if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) | |
145 | return -EINVAL; | |
146 | ||
147 | cache_result = (config >> 16) & 0xff; | |
148 | if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | |
149 | return -EINVAL; | |
150 | ||
84fee97a | 151 | ret = (int)(*armpmu->cache_map)[cache_type][cache_op][cache_result]; |
1b8873a0 JI |
152 | |
153 | if (ret == CACHE_OP_UNSUPPORTED) | |
154 | return -ENOENT; | |
155 | ||
156 | return ret; | |
157 | } | |
158 | ||
84fee97a WD |
159 | static int |
160 | armpmu_map_event(u64 config) | |
161 | { | |
162 | int mapping = (*armpmu->event_map)[config]; | |
163 | return mapping == HW_OP_UNSUPPORTED ? -EOPNOTSUPP : mapping; | |
164 | } | |
165 | ||
166 | static int | |
167 | armpmu_map_raw_event(u64 config) | |
168 | { | |
169 | return (int)(config & armpmu->raw_event_mask); | |
170 | } | |
171 | ||
1b8873a0 JI |
172 | static int |
173 | armpmu_event_set_period(struct perf_event *event, | |
174 | struct hw_perf_event *hwc, | |
175 | int idx) | |
176 | { | |
e7850595 | 177 | s64 left = local64_read(&hwc->period_left); |
1b8873a0 JI |
178 | s64 period = hwc->sample_period; |
179 | int ret = 0; | |
180 | ||
181 | if (unlikely(left <= -period)) { | |
182 | left = period; | |
e7850595 | 183 | local64_set(&hwc->period_left, left); |
1b8873a0 JI |
184 | hwc->last_period = period; |
185 | ret = 1; | |
186 | } | |
187 | ||
188 | if (unlikely(left <= 0)) { | |
189 | left += period; | |
e7850595 | 190 | local64_set(&hwc->period_left, left); |
1b8873a0 JI |
191 | hwc->last_period = period; |
192 | ret = 1; | |
193 | } | |
194 | ||
195 | if (left > (s64)armpmu->max_period) | |
196 | left = armpmu->max_period; | |
197 | ||
e7850595 | 198 | local64_set(&hwc->prev_count, (u64)-left); |
1b8873a0 JI |
199 | |
200 | armpmu->write_counter(idx, (u64)(-left) & 0xffffffff); | |
201 | ||
202 | perf_event_update_userpage(event); | |
203 | ||
204 | return ret; | |
205 | } | |
206 | ||
207 | static u64 | |
208 | armpmu_event_update(struct perf_event *event, | |
209 | struct hw_perf_event *hwc, | |
a737823d | 210 | int idx, int overflow) |
1b8873a0 | 211 | { |
a737823d | 212 | u64 delta, prev_raw_count, new_raw_count; |
1b8873a0 JI |
213 | |
214 | again: | |
e7850595 | 215 | prev_raw_count = local64_read(&hwc->prev_count); |
1b8873a0 JI |
216 | new_raw_count = armpmu->read_counter(idx); |
217 | ||
e7850595 | 218 | if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, |
1b8873a0 JI |
219 | new_raw_count) != prev_raw_count) |
220 | goto again; | |
221 | ||
a737823d WD |
222 | new_raw_count &= armpmu->max_period; |
223 | prev_raw_count &= armpmu->max_period; | |
224 | ||
225 | if (overflow) | |
6759788b | 226 | delta = armpmu->max_period - prev_raw_count + new_raw_count + 1; |
a737823d WD |
227 | else |
228 | delta = new_raw_count - prev_raw_count; | |
1b8873a0 | 229 | |
e7850595 PZ |
230 | local64_add(delta, &event->count); |
231 | local64_sub(delta, &hwc->period_left); | |
1b8873a0 JI |
232 | |
233 | return new_raw_count; | |
234 | } | |
235 | ||
236 | static void | |
a4eaf7f1 | 237 | armpmu_read(struct perf_event *event) |
1b8873a0 | 238 | { |
1b8873a0 | 239 | struct hw_perf_event *hwc = &event->hw; |
1b8873a0 | 240 | |
a4eaf7f1 PZ |
241 | /* Don't read disabled counters! */ |
242 | if (hwc->idx < 0) | |
243 | return; | |
1b8873a0 | 244 | |
a737823d | 245 | armpmu_event_update(event, hwc, hwc->idx, 0); |
1b8873a0 JI |
246 | } |
247 | ||
248 | static void | |
a4eaf7f1 | 249 | armpmu_stop(struct perf_event *event, int flags) |
1b8873a0 JI |
250 | { |
251 | struct hw_perf_event *hwc = &event->hw; | |
252 | ||
a4eaf7f1 PZ |
253 | /* |
254 | * ARM pmu always has to update the counter, so ignore | |
255 | * PERF_EF_UPDATE, see comments in armpmu_start(). | |
256 | */ | |
257 | if (!(hwc->state & PERF_HES_STOPPED)) { | |
258 | armpmu->disable(hwc, hwc->idx); | |
259 | barrier(); /* why? */ | |
a737823d | 260 | armpmu_event_update(event, hwc, hwc->idx, 0); |
a4eaf7f1 PZ |
261 | hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; |
262 | } | |
1b8873a0 JI |
263 | } |
264 | ||
265 | static void | |
a4eaf7f1 | 266 | armpmu_start(struct perf_event *event, int flags) |
1b8873a0 JI |
267 | { |
268 | struct hw_perf_event *hwc = &event->hw; | |
269 | ||
a4eaf7f1 PZ |
270 | /* |
271 | * ARM pmu always has to reprogram the period, so ignore | |
272 | * PERF_EF_RELOAD, see the comment below. | |
273 | */ | |
274 | if (flags & PERF_EF_RELOAD) | |
275 | WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE)); | |
276 | ||
277 | hwc->state = 0; | |
1b8873a0 JI |
278 | /* |
279 | * Set the period again. Some counters can't be stopped, so when we | |
a4eaf7f1 | 280 | * were stopped we simply disabled the IRQ source and the counter |
1b8873a0 JI |
281 | * may have been left counting. If we don't do this step then we may |
282 | * get an interrupt too soon or *way* too late if the overflow has | |
283 | * happened since disabling. | |
284 | */ | |
285 | armpmu_event_set_period(event, hwc, hwc->idx); | |
286 | armpmu->enable(hwc, hwc->idx); | |
287 | } | |
288 | ||
a4eaf7f1 PZ |
289 | static void |
290 | armpmu_del(struct perf_event *event, int flags) | |
291 | { | |
292 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
293 | struct hw_perf_event *hwc = &event->hw; | |
294 | int idx = hwc->idx; | |
295 | ||
296 | WARN_ON(idx < 0); | |
297 | ||
298 | clear_bit(idx, cpuc->active_mask); | |
299 | armpmu_stop(event, PERF_EF_UPDATE); | |
300 | cpuc->events[idx] = NULL; | |
301 | clear_bit(idx, cpuc->used_mask); | |
302 | ||
303 | perf_event_update_userpage(event); | |
304 | } | |
305 | ||
1b8873a0 | 306 | static int |
a4eaf7f1 | 307 | armpmu_add(struct perf_event *event, int flags) |
1b8873a0 JI |
308 | { |
309 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
310 | struct hw_perf_event *hwc = &event->hw; | |
311 | int idx; | |
312 | int err = 0; | |
313 | ||
33696fc0 | 314 | perf_pmu_disable(event->pmu); |
24cd7f54 | 315 | |
1b8873a0 JI |
316 | /* If we don't have a space for the counter then finish early. */ |
317 | idx = armpmu->get_event_idx(cpuc, hwc); | |
318 | if (idx < 0) { | |
319 | err = idx; | |
320 | goto out; | |
321 | } | |
322 | ||
323 | /* | |
324 | * If there is an event in the counter we are going to use then make | |
325 | * sure it is disabled. | |
326 | */ | |
327 | event->hw.idx = idx; | |
328 | armpmu->disable(hwc, idx); | |
329 | cpuc->events[idx] = event; | |
330 | set_bit(idx, cpuc->active_mask); | |
331 | ||
a4eaf7f1 PZ |
332 | hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE; |
333 | if (flags & PERF_EF_START) | |
334 | armpmu_start(event, PERF_EF_RELOAD); | |
1b8873a0 JI |
335 | |
336 | /* Propagate our changes to the userspace mapping. */ | |
337 | perf_event_update_userpage(event); | |
338 | ||
339 | out: | |
33696fc0 | 340 | perf_pmu_enable(event->pmu); |
1b8873a0 JI |
341 | return err; |
342 | } | |
343 | ||
b0a873eb | 344 | static struct pmu pmu; |
1b8873a0 JI |
345 | |
346 | static int | |
347 | validate_event(struct cpu_hw_events *cpuc, | |
348 | struct perf_event *event) | |
349 | { | |
350 | struct hw_perf_event fake_event = event->hw; | |
351 | ||
65b4711f WD |
352 | if (event->pmu != &pmu || event->state <= PERF_EVENT_STATE_OFF) |
353 | return 1; | |
1b8873a0 JI |
354 | |
355 | return armpmu->get_event_idx(cpuc, &fake_event) >= 0; | |
356 | } | |
357 | ||
358 | static int | |
359 | validate_group(struct perf_event *event) | |
360 | { | |
361 | struct perf_event *sibling, *leader = event->group_leader; | |
362 | struct cpu_hw_events fake_pmu; | |
363 | ||
364 | memset(&fake_pmu, 0, sizeof(fake_pmu)); | |
365 | ||
366 | if (!validate_event(&fake_pmu, leader)) | |
367 | return -ENOSPC; | |
368 | ||
369 | list_for_each_entry(sibling, &leader->sibling_list, group_entry) { | |
370 | if (!validate_event(&fake_pmu, sibling)) | |
371 | return -ENOSPC; | |
372 | } | |
373 | ||
374 | if (!validate_event(&fake_pmu, event)) | |
375 | return -ENOSPC; | |
376 | ||
377 | return 0; | |
378 | } | |
379 | ||
0e25a5c9 RV |
380 | static irqreturn_t armpmu_platform_irq(int irq, void *dev) |
381 | { | |
382 | struct arm_pmu_platdata *plat = dev_get_platdata(&pmu_device->dev); | |
383 | ||
384 | return plat->handle_irq(irq, dev, armpmu->handle_irq); | |
385 | } | |
386 | ||
0b390e21 WD |
387 | static void |
388 | armpmu_release_hardware(void) | |
389 | { | |
390 | int i, irq, irqs; | |
391 | ||
392 | irqs = min(pmu_device->num_resources, num_possible_cpus()); | |
393 | ||
394 | for (i = 0; i < irqs; ++i) { | |
395 | if (!cpumask_test_and_clear_cpu(i, &armpmu->active_irqs)) | |
396 | continue; | |
397 | irq = platform_get_irq(pmu_device, i); | |
398 | if (irq >= 0) | |
399 | free_irq(irq, NULL); | |
400 | } | |
401 | ||
402 | armpmu->stop(); | |
403 | release_pmu(ARM_PMU_DEVICE_CPU); | |
404 | } | |
405 | ||
1b8873a0 JI |
406 | static int |
407 | armpmu_reserve_hardware(void) | |
408 | { | |
0e25a5c9 RV |
409 | struct arm_pmu_platdata *plat; |
410 | irq_handler_t handle_irq; | |
b0e89590 | 411 | int i, err, irq, irqs; |
1b8873a0 | 412 | |
b0e89590 WD |
413 | err = reserve_pmu(ARM_PMU_DEVICE_CPU); |
414 | if (err) { | |
1b8873a0 | 415 | pr_warning("unable to reserve pmu\n"); |
b0e89590 | 416 | return err; |
1b8873a0 JI |
417 | } |
418 | ||
0e25a5c9 RV |
419 | plat = dev_get_platdata(&pmu_device->dev); |
420 | if (plat && plat->handle_irq) | |
421 | handle_irq = armpmu_platform_irq; | |
422 | else | |
423 | handle_irq = armpmu->handle_irq; | |
424 | ||
0b390e21 | 425 | irqs = min(pmu_device->num_resources, num_possible_cpus()); |
b0e89590 | 426 | if (irqs < 1) { |
1b8873a0 JI |
427 | pr_err("no irqs for PMUs defined\n"); |
428 | return -ENODEV; | |
429 | } | |
430 | ||
b0e89590 | 431 | for (i = 0; i < irqs; ++i) { |
0b390e21 | 432 | err = 0; |
49c006b9 WD |
433 | irq = platform_get_irq(pmu_device, i); |
434 | if (irq < 0) | |
435 | continue; | |
436 | ||
b0e89590 WD |
437 | /* |
438 | * If we have a single PMU interrupt that we can't shift, | |
439 | * assume that we're running on a uniprocessor machine and | |
0b390e21 | 440 | * continue. Otherwise, continue without this interrupt. |
b0e89590 | 441 | */ |
0b390e21 WD |
442 | if (irq_set_affinity(irq, cpumask_of(i)) && irqs > 1) { |
443 | pr_warning("unable to set irq affinity (irq=%d, cpu=%u)\n", | |
444 | irq, i); | |
445 | continue; | |
b0e89590 WD |
446 | } |
447 | ||
0e25a5c9 | 448 | err = request_irq(irq, handle_irq, |
ddee87f2 | 449 | IRQF_DISABLED | IRQF_NOBALANCING, |
b0e89590 | 450 | "arm-pmu", NULL); |
1b8873a0 | 451 | if (err) { |
b0e89590 WD |
452 | pr_err("unable to request IRQ%d for ARM PMU counters\n", |
453 | irq); | |
0b390e21 WD |
454 | armpmu_release_hardware(); |
455 | return err; | |
1b8873a0 | 456 | } |
1b8873a0 | 457 | |
0b390e21 | 458 | cpumask_set_cpu(i, &armpmu->active_irqs); |
49c006b9 | 459 | } |
1b8873a0 | 460 | |
0b390e21 | 461 | return 0; |
1b8873a0 JI |
462 | } |
463 | ||
464 | static atomic_t active_events = ATOMIC_INIT(0); | |
465 | static DEFINE_MUTEX(pmu_reserve_mutex); | |
466 | ||
467 | static void | |
468 | hw_perf_event_destroy(struct perf_event *event) | |
469 | { | |
470 | if (atomic_dec_and_mutex_lock(&active_events, &pmu_reserve_mutex)) { | |
471 | armpmu_release_hardware(); | |
472 | mutex_unlock(&pmu_reserve_mutex); | |
473 | } | |
474 | } | |
475 | ||
05d22fde WD |
476 | static int |
477 | event_requires_mode_exclusion(struct perf_event_attr *attr) | |
478 | { | |
479 | return attr->exclude_idle || attr->exclude_user || | |
480 | attr->exclude_kernel || attr->exclude_hv; | |
481 | } | |
482 | ||
1b8873a0 JI |
483 | static int |
484 | __hw_perf_event_init(struct perf_event *event) | |
485 | { | |
486 | struct hw_perf_event *hwc = &event->hw; | |
487 | int mapping, err; | |
488 | ||
489 | /* Decode the generic type into an ARM event identifier. */ | |
490 | if (PERF_TYPE_HARDWARE == event->attr.type) { | |
84fee97a | 491 | mapping = armpmu_map_event(event->attr.config); |
1b8873a0 JI |
492 | } else if (PERF_TYPE_HW_CACHE == event->attr.type) { |
493 | mapping = armpmu_map_cache_event(event->attr.config); | |
494 | } else if (PERF_TYPE_RAW == event->attr.type) { | |
84fee97a | 495 | mapping = armpmu_map_raw_event(event->attr.config); |
1b8873a0 JI |
496 | } else { |
497 | pr_debug("event type %x not supported\n", event->attr.type); | |
498 | return -EOPNOTSUPP; | |
499 | } | |
500 | ||
501 | if (mapping < 0) { | |
502 | pr_debug("event %x:%llx not supported\n", event->attr.type, | |
503 | event->attr.config); | |
504 | return mapping; | |
505 | } | |
506 | ||
05d22fde WD |
507 | /* |
508 | * We don't assign an index until we actually place the event onto | |
509 | * hardware. Use -1 to signify that we haven't decided where to put it | |
510 | * yet. For SMP systems, each core has it's own PMU so we can't do any | |
511 | * clever allocation or constraints checking at this point. | |
512 | */ | |
513 | hwc->idx = -1; | |
514 | hwc->config_base = 0; | |
515 | hwc->config = 0; | |
516 | hwc->event_base = 0; | |
517 | ||
1b8873a0 JI |
518 | /* |
519 | * Check whether we need to exclude the counter from certain modes. | |
1b8873a0 | 520 | */ |
05d22fde WD |
521 | if ((!armpmu->set_event_filter || |
522 | armpmu->set_event_filter(hwc, &event->attr)) && | |
523 | event_requires_mode_exclusion(&event->attr)) { | |
1b8873a0 JI |
524 | pr_debug("ARM performance counters do not support " |
525 | "mode exclusion\n"); | |
526 | return -EPERM; | |
527 | } | |
528 | ||
529 | /* | |
05d22fde | 530 | * Store the event encoding into the config_base field. |
1b8873a0 | 531 | */ |
05d22fde | 532 | hwc->config_base |= (unsigned long)mapping; |
1b8873a0 JI |
533 | |
534 | if (!hwc->sample_period) { | |
535 | hwc->sample_period = armpmu->max_period; | |
536 | hwc->last_period = hwc->sample_period; | |
e7850595 | 537 | local64_set(&hwc->period_left, hwc->sample_period); |
1b8873a0 JI |
538 | } |
539 | ||
540 | err = 0; | |
541 | if (event->group_leader != event) { | |
542 | err = validate_group(event); | |
543 | if (err) | |
544 | return -EINVAL; | |
545 | } | |
546 | ||
547 | return err; | |
548 | } | |
549 | ||
b0a873eb | 550 | static int armpmu_event_init(struct perf_event *event) |
1b8873a0 JI |
551 | { |
552 | int err = 0; | |
553 | ||
b0a873eb PZ |
554 | switch (event->attr.type) { |
555 | case PERF_TYPE_RAW: | |
556 | case PERF_TYPE_HARDWARE: | |
557 | case PERF_TYPE_HW_CACHE: | |
558 | break; | |
559 | ||
560 | default: | |
561 | return -ENOENT; | |
562 | } | |
563 | ||
1b8873a0 JI |
564 | event->destroy = hw_perf_event_destroy; |
565 | ||
566 | if (!atomic_inc_not_zero(&active_events)) { | |
1b8873a0 JI |
567 | mutex_lock(&pmu_reserve_mutex); |
568 | if (atomic_read(&active_events) == 0) { | |
569 | err = armpmu_reserve_hardware(); | |
570 | } | |
571 | ||
572 | if (!err) | |
573 | atomic_inc(&active_events); | |
574 | mutex_unlock(&pmu_reserve_mutex); | |
575 | } | |
576 | ||
577 | if (err) | |
b0a873eb | 578 | return err; |
1b8873a0 JI |
579 | |
580 | err = __hw_perf_event_init(event); | |
581 | if (err) | |
582 | hw_perf_event_destroy(event); | |
583 | ||
b0a873eb | 584 | return err; |
1b8873a0 JI |
585 | } |
586 | ||
a4eaf7f1 | 587 | static void armpmu_enable(struct pmu *pmu) |
1b8873a0 JI |
588 | { |
589 | /* Enable all of the perf events on hardware. */ | |
f4f38430 | 590 | int idx, enabled = 0; |
1b8873a0 JI |
591 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
592 | ||
ecf5a893 | 593 | for (idx = 0; idx < armpmu->num_events; ++idx) { |
1b8873a0 JI |
594 | struct perf_event *event = cpuc->events[idx]; |
595 | ||
596 | if (!event) | |
597 | continue; | |
598 | ||
599 | armpmu->enable(&event->hw, idx); | |
f4f38430 | 600 | enabled = 1; |
1b8873a0 JI |
601 | } |
602 | ||
f4f38430 WD |
603 | if (enabled) |
604 | armpmu->start(); | |
1b8873a0 JI |
605 | } |
606 | ||
a4eaf7f1 | 607 | static void armpmu_disable(struct pmu *pmu) |
1b8873a0 | 608 | { |
48957155 | 609 | armpmu->stop(); |
1b8873a0 JI |
610 | } |
611 | ||
33696fc0 | 612 | static struct pmu pmu = { |
a4eaf7f1 PZ |
613 | .pmu_enable = armpmu_enable, |
614 | .pmu_disable = armpmu_disable, | |
615 | .event_init = armpmu_event_init, | |
616 | .add = armpmu_add, | |
617 | .del = armpmu_del, | |
618 | .start = armpmu_start, | |
619 | .stop = armpmu_stop, | |
620 | .read = armpmu_read, | |
33696fc0 PZ |
621 | }; |
622 | ||
43eab878 WD |
623 | /* Include the PMU-specific implementations. */ |
624 | #include "perf_event_xscale.c" | |
625 | #include "perf_event_v6.c" | |
626 | #include "perf_event_v7.c" | |
49e6a32f | 627 | |
574b69cb WD |
628 | /* |
629 | * Ensure the PMU has sane values out of reset. | |
630 | * This requires SMP to be available, so exists as a separate initcall. | |
631 | */ | |
632 | static int __init | |
633 | armpmu_reset(void) | |
634 | { | |
635 | if (armpmu && armpmu->reset) | |
636 | return on_each_cpu(armpmu->reset, NULL, 1); | |
637 | return 0; | |
638 | } | |
639 | arch_initcall(armpmu_reset); | |
640 | ||
b0e89590 WD |
641 | /* |
642 | * PMU platform driver and devicetree bindings. | |
643 | */ | |
644 | static struct of_device_id armpmu_of_device_ids[] = { | |
645 | {.compatible = "arm,cortex-a9-pmu"}, | |
646 | {.compatible = "arm,cortex-a8-pmu"}, | |
647 | {.compatible = "arm,arm1136-pmu"}, | |
648 | {.compatible = "arm,arm1176-pmu"}, | |
649 | {}, | |
650 | }; | |
651 | ||
652 | static struct platform_device_id armpmu_plat_device_ids[] = { | |
653 | {.name = "arm-pmu"}, | |
654 | {}, | |
655 | }; | |
656 | ||
657 | static int __devinit armpmu_device_probe(struct platform_device *pdev) | |
658 | { | |
659 | pmu_device = pdev; | |
660 | return 0; | |
661 | } | |
662 | ||
663 | static struct platform_driver armpmu_driver = { | |
664 | .driver = { | |
665 | .name = "arm-pmu", | |
666 | .of_match_table = armpmu_of_device_ids, | |
667 | }, | |
668 | .probe = armpmu_device_probe, | |
669 | .id_table = armpmu_plat_device_ids, | |
670 | }; | |
671 | ||
672 | static int __init register_pmu_driver(void) | |
673 | { | |
674 | return platform_driver_register(&armpmu_driver); | |
675 | } | |
676 | device_initcall(register_pmu_driver); | |
677 | ||
678 | /* | |
679 | * CPU PMU identification and registration. | |
680 | */ | |
1b8873a0 JI |
681 | static int __init |
682 | init_hw_perf_events(void) | |
683 | { | |
684 | unsigned long cpuid = read_cpuid_id(); | |
685 | unsigned long implementor = (cpuid & 0xFF000000) >> 24; | |
686 | unsigned long part_number = (cpuid & 0xFFF0); | |
687 | ||
49e6a32f | 688 | /* ARM Ltd CPUs. */ |
1b8873a0 JI |
689 | if (0x41 == implementor) { |
690 | switch (part_number) { | |
691 | case 0xB360: /* ARM1136 */ | |
692 | case 0xB560: /* ARM1156 */ | |
693 | case 0xB760: /* ARM1176 */ | |
3cb314ba | 694 | armpmu = armv6pmu_init(); |
1b8873a0 JI |
695 | break; |
696 | case 0xB020: /* ARM11mpcore */ | |
3cb314ba | 697 | armpmu = armv6mpcore_pmu_init(); |
1b8873a0 | 698 | break; |
796d1295 | 699 | case 0xC080: /* Cortex-A8 */ |
3cb314ba | 700 | armpmu = armv7_a8_pmu_init(); |
796d1295 JP |
701 | break; |
702 | case 0xC090: /* Cortex-A9 */ | |
3cb314ba | 703 | armpmu = armv7_a9_pmu_init(); |
796d1295 | 704 | break; |
0c205cbe WD |
705 | case 0xC050: /* Cortex-A5 */ |
706 | armpmu = armv7_a5_pmu_init(); | |
707 | break; | |
14abd038 WD |
708 | case 0xC0F0: /* Cortex-A15 */ |
709 | armpmu = armv7_a15_pmu_init(); | |
710 | break; | |
49e6a32f WD |
711 | } |
712 | /* Intel CPUs [xscale]. */ | |
713 | } else if (0x69 == implementor) { | |
714 | part_number = (cpuid >> 13) & 0x7; | |
715 | switch (part_number) { | |
716 | case 1: | |
3cb314ba | 717 | armpmu = xscale1pmu_init(); |
49e6a32f WD |
718 | break; |
719 | case 2: | |
3cb314ba | 720 | armpmu = xscale2pmu_init(); |
49e6a32f | 721 | break; |
1b8873a0 JI |
722 | } |
723 | } | |
724 | ||
49e6a32f | 725 | if (armpmu) { |
796d1295 | 726 | pr_info("enabled with %s PMU driver, %d counters available\n", |
62994831 | 727 | armpmu->name, armpmu->num_events); |
48957155 | 728 | perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW); |
49e6a32f WD |
729 | } else { |
730 | pr_info("no hardware support available\n"); | |
49e6a32f | 731 | } |
1b8873a0 JI |
732 | |
733 | return 0; | |
734 | } | |
004417a6 | 735 | early_initcall(init_hw_perf_events); |
1b8873a0 JI |
736 | |
737 | /* | |
738 | * Callchain handling code. | |
739 | */ | |
1b8873a0 JI |
740 | |
741 | /* | |
742 | * The registers we're interested in are at the end of the variable | |
743 | * length saved register structure. The fp points at the end of this | |
744 | * structure so the address of this struct is: | |
745 | * (struct frame_tail *)(xxx->fp)-1 | |
746 | * | |
747 | * This code has been adapted from the ARM OProfile support. | |
748 | */ | |
749 | struct frame_tail { | |
4d6b7a77 WD |
750 | struct frame_tail __user *fp; |
751 | unsigned long sp; | |
752 | unsigned long lr; | |
1b8873a0 JI |
753 | } __attribute__((packed)); |
754 | ||
755 | /* | |
756 | * Get the return address for a single stackframe and return a pointer to the | |
757 | * next frame tail. | |
758 | */ | |
4d6b7a77 WD |
759 | static struct frame_tail __user * |
760 | user_backtrace(struct frame_tail __user *tail, | |
1b8873a0 JI |
761 | struct perf_callchain_entry *entry) |
762 | { | |
763 | struct frame_tail buftail; | |
764 | ||
765 | /* Also check accessibility of one struct frame_tail beyond */ | |
766 | if (!access_ok(VERIFY_READ, tail, sizeof(buftail))) | |
767 | return NULL; | |
768 | if (__copy_from_user_inatomic(&buftail, tail, sizeof(buftail))) | |
769 | return NULL; | |
770 | ||
70791ce9 | 771 | perf_callchain_store(entry, buftail.lr); |
1b8873a0 JI |
772 | |
773 | /* | |
774 | * Frame pointers should strictly progress back up the stack | |
775 | * (towards higher addresses). | |
776 | */ | |
cb06199b | 777 | if (tail + 1 >= buftail.fp) |
1b8873a0 JI |
778 | return NULL; |
779 | ||
780 | return buftail.fp - 1; | |
781 | } | |
782 | ||
56962b44 FW |
783 | void |
784 | perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs) | |
1b8873a0 | 785 | { |
4d6b7a77 | 786 | struct frame_tail __user *tail; |
1b8873a0 | 787 | |
1b8873a0 | 788 | |
4d6b7a77 | 789 | tail = (struct frame_tail __user *)regs->ARM_fp - 1; |
1b8873a0 | 790 | |
860ad782 SR |
791 | while ((entry->nr < PERF_MAX_STACK_DEPTH) && |
792 | tail && !((unsigned long)tail & 0x3)) | |
1b8873a0 JI |
793 | tail = user_backtrace(tail, entry); |
794 | } | |
795 | ||
796 | /* | |
797 | * Gets called by walk_stackframe() for every stackframe. This will be called | |
798 | * whist unwinding the stackframe and is like a subroutine return so we use | |
799 | * the PC. | |
800 | */ | |
801 | static int | |
802 | callchain_trace(struct stackframe *fr, | |
803 | void *data) | |
804 | { | |
805 | struct perf_callchain_entry *entry = data; | |
70791ce9 | 806 | perf_callchain_store(entry, fr->pc); |
1b8873a0 JI |
807 | return 0; |
808 | } | |
809 | ||
56962b44 FW |
810 | void |
811 | perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs) | |
1b8873a0 JI |
812 | { |
813 | struct stackframe fr; | |
814 | ||
1b8873a0 JI |
815 | fr.fp = regs->ARM_fp; |
816 | fr.sp = regs->ARM_sp; | |
817 | fr.lr = regs->ARM_lr; | |
818 | fr.pc = regs->ARM_pc; | |
819 | walk_stackframe(&fr, callchain_trace, entry); | |
820 | } |