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Merge tag 'v3.10.106' into update
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / usb / dwc3 / gadget.c
CommitLineData
72246da4
FB		 1/**
2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
72246da4
FB		 5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer,
14 * without modification.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. The names of the above-listed copyright holders may not be used
19 * to endorse or promote products derived from this software without
20 * specific prior written permission.
21 *
22 * ALTERNATIVELY, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2, as published by the Free
24 * Software Foundation.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 */
38
39#include <linux/kernel.h>
40#include <linux/delay.h>
41#include <linux/slab.h>
42#include <linux/spinlock.h>
43#include <linux/platform_device.h>
44#include <linux/pm_runtime.h>
45#include <linux/interrupt.h>
46#include <linux/io.h>
47#include <linux/list.h>
48#include <linux/dma-mapping.h>
49
50#include <linux/usb/ch9.h>
51#include <linux/usb/gadget.h>
52
53#include "core.h"
54#include "gadget.h"
55#include "io.h"
56
04a9bfcd
FB		 57/**
58 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
59 * @dwc: pointer to our context structure
60 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
61 *
62 * Caller should take care of locking. This function will
63 * return 0 on success or -EINVAL if wrong Test Selector
64 * is passed
65 */
66int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
67{
68 u32 reg;
69
70 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
71 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
72
73 switch (mode) {
74 case TEST_J:
75 case TEST_K:
76 case TEST_SE0_NAK:
77 case TEST_PACKET:
78 case TEST_FORCE_EN:
79 reg |= mode << 1;
80 break;
81 default:
82 return -EINVAL;
83 }
84
85 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
86
87 return 0;
88}
89
8598bde7
FB		 90/**
91 * dwc3_gadget_set_link_state - Sets USB Link to a particular State
92 * @dwc: pointer to our context structure
93 * @state: the state to put link into
94 *
95 * Caller should take care of locking. This function will
aee63e3c 96 * return 0 on success or -ETIMEDOUT.
8598bde7
FB		 97 */
98int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
99{
aee63e3c 100 int retries = 10000;
8598bde7
FB		 101 u32 reg;
102
802fde98
PZ		 103 /*
104 * Wait until device controller is ready. Only applies to 1.94a and
105 * later RTL.
106 */
107 if (dwc->revision >= DWC3_REVISION_194A) {
108 while (--retries) {
109 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
110 if (reg & DWC3_DSTS_DCNRD)
111 udelay(5);
112 else
113 break;
114 }
115
116 if (retries <= 0)
117 return -ETIMEDOUT;
118 }
119
8598bde7
FB		 120 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
121 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
122
123 /* set requested state */
124 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
125 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
126
802fde98
PZ		 127 /*
128 * The following code is racy when called from dwc3_gadget_wakeup,
129 * and is not needed, at least on newer versions
130 */
131 if (dwc->revision >= DWC3_REVISION_194A)
132 return 0;
133
8598bde7 134 /* wait for a change in DSTS */
aed430e5 135 retries = 10000;
8598bde7
FB		 136 while (--retries) {
137 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
138
8598bde7
FB		 139 if (DWC3_DSTS_USBLNKST(reg) == state)
140 return 0;
141
aee63e3c 142 udelay(5);
8598bde7
FB		 143 }
144
145 dev_vdbg(dwc->dev, "link state change request timed out\n");
146
147 return -ETIMEDOUT;
148}
149
457e84b6
FB		 150/**
151 * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
152 * @dwc: pointer to our context structure
153 *
154 * This function will a best effort FIFO allocation in order
155 * to improve FIFO usage and throughput, while still allowing
156 * us to enable as many endpoints as possible.
157 *
158 * Keep in mind that this operation will be highly dependent
159 * on the configured size for RAM1 - which contains TxFifo -,
160 * the amount of endpoints enabled on coreConsultant tool, and
161 * the width of the Master Bus.
162 *
163 * In the ideal world, we would always be able to satisfy the
164 * following equation:
165 *
166 * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \
167 * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes
168 *
169 * Unfortunately, due to many variables that's not always the case.
170 */
171int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc)
172{
173 int last_fifo_depth = 0;
174 int ram1_depth;
175 int fifo_size;
176 int mdwidth;
177 int num;
178
179 if (!dwc->needs_fifo_resize)
180 return 0;
181
182 ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
183 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
184
185 /* MDWIDTH is represented in bits, we need it in bytes */
186 mdwidth >>= 3;
187
188 /*
189 * FIXME For now we will only allocate 1 wMaxPacketSize space
190 * for each enabled endpoint, later patches will come to
191 * improve this algorithm so that we better use the internal
192 * FIFO space
193 */
194 for (num = 0; num < DWC3_ENDPOINTS_NUM; num++) {
195 struct dwc3_ep *dep = dwc->eps[num];
196 int fifo_number = dep->number >> 1;
2e81c36a 197 int mult = 1;
457e84b6
FB		 198 int tmp;
199
200 if (!(dep->number & 1))
201 continue;
202
203 if (!(dep->flags & DWC3_EP_ENABLED))
204 continue;
205
16e78db7
IS		 206 if (usb_endpoint_xfer_bulk(dep->endpoint.desc)
207 || usb_endpoint_xfer_isoc(dep->endpoint.desc))
2e81c36a
FB		 208 mult = 3;
209
210 /*
211 * REVISIT: the following assumes we will always have enough
212 * space available on the FIFO RAM for all possible use cases.
213 * Make sure that's true somehow and change FIFO allocation
214 * accordingly.
215 *
216 * If we have Bulk or Isochronous endpoints, we want
217 * them to be able to be very, very fast. So we're giving
218 * those endpoints a fifo_size which is enough for 3 full
219 * packets
220 */
221 tmp = mult * (dep->endpoint.maxpacket + mdwidth);
457e84b6
FB		 222 tmp += mdwidth;
223
224 fifo_size = DIV_ROUND_UP(tmp, mdwidth);
2e81c36a 225
457e84b6
FB		 226 fifo_size |= (last_fifo_depth << 16);
227
228 dev_vdbg(dwc->dev, "%s: Fifo Addr %04x Size %d\n",
229 dep->name, last_fifo_depth, fifo_size & 0xffff);
230
231 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(fifo_number),
232 fifo_size);
233
234 last_fifo_depth += (fifo_size & 0xffff);
235 }
236
237 return 0;
238}
239
72246da4
FB		 240void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
241 int status)
242{
243 struct dwc3 *dwc = dep->dwc;
e5ba5ec8 244 int i;
72246da4
FB		 245
246 if (req->queued) {
e5ba5ec8
PA		 247 i = 0;
248 do {
eeb720fb 249 dep->busy_slot++;
e5ba5ec8
PA		 250 /*
251 * Skip LINK TRB. We can't use req->trb and check for
252 * DWC3_TRBCTL_LINK_TRB because it points the TRB we
253 * just completed (not the LINK TRB).
254 */
255 if (((dep->busy_slot & DWC3_TRB_MASK) ==
256 DWC3_TRB_NUM- 1) &&
16e78db7 257 usb_endpoint_xfer_isoc(dep->endpoint.desc))
e5ba5ec8
PA		 258 dep->busy_slot++;
259 } while(++i < req->request.num_mapped_sgs);
c9fda7d6 260 req->queued = false;
72246da4
FB		 261 }
262 list_del(&req->list);
eeb720fb 263 req->trb = NULL;
72246da4
FB		 264
265 if (req->request.status == -EINPROGRESS)
266 req->request.status = status;
267
34c83571 268 if (dwc->ep0_bounced && dep->number <= 1)
0416e494 269 dwc->ep0_bounced = false;
34c83571
FB		 270
271 usb_gadget_unmap_request(&dwc->gadget, &req->request,
272 req->direction);
72246da4
FB		 273
274 dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n",
275 req, dep->name, req->request.actual,
276 req->request.length, status);
277
278 spin_unlock(&dwc->lock);
0fc9a1be 279 req->request.complete(&dep->endpoint, &req->request);
72246da4
FB		 280 spin_lock(&dwc->lock);
281}
282
283static const char *dwc3_gadget_ep_cmd_string(u8 cmd)
284{
285 switch (cmd) {
286 case DWC3_DEPCMD_DEPSTARTCFG:
287 return "Start New Configuration";
288 case DWC3_DEPCMD_ENDTRANSFER:
289 return "End Transfer";
290 case DWC3_DEPCMD_UPDATETRANSFER:
291 return "Update Transfer";
292 case DWC3_DEPCMD_STARTTRANSFER:
293 return "Start Transfer";
294 case DWC3_DEPCMD_CLEARSTALL:
295 return "Clear Stall";
296 case DWC3_DEPCMD_SETSTALL:
297 return "Set Stall";
802fde98
PZ		 298 case DWC3_DEPCMD_GETEPSTATE:
299 return "Get Endpoint State";
72246da4
FB		 300 case DWC3_DEPCMD_SETTRANSFRESOURCE:
301 return "Set Endpoint Transfer Resource";
302 case DWC3_DEPCMD_SETEPCONFIG:
303 return "Set Endpoint Configuration";
304 default:
305 return "UNKNOWN command";
306 }
307}
308
b09bb642
FB		 309int dwc3_send_gadget_generic_command(struct dwc3 *dwc, int cmd, u32 param)
310{
311 u32 timeout = 500;
312 u32 reg;
313
314 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
315 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
316
317 do {
318 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
319 if (!(reg & DWC3_DGCMD_CMDACT)) {
320 dev_vdbg(dwc->dev, "Command Complete --> %d\n",
321 DWC3_DGCMD_STATUS(reg));
265f7f39
SSB		 322 if (DWC3_DGCMD_STATUS(reg))
323 return -EINVAL;
b09bb642
FB		 324 return 0;
325 }
326
327 /*
328 * We can't sleep here, because it's also called from
329 * interrupt context.
330 */
331 timeout--;
332 if (!timeout)
333 return -ETIMEDOUT;
334 udelay(1);
335 } while (1);
336}
337
72246da4
FB		 338int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
339 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
340{
341 struct dwc3_ep *dep = dwc->eps[ep];
61d58242 342 u32 timeout = 500;
72246da4
FB		 343 u32 reg;
344
345 dev_vdbg(dwc->dev, "%s: cmd '%s' params %08x %08x %08x\n",
346 dep->name,
dc1c70a7
FB		 347 dwc3_gadget_ep_cmd_string(cmd), params->param0,
348 params->param1, params->param2);
72246da4 349
dc1c70a7
FB		 350 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
351 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
352 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
72246da4
FB		 353
354 dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
355 do {
356 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
357 if (!(reg & DWC3_DEPCMD_CMDACT)) {
164f6e14
FB		 358 dev_vdbg(dwc->dev, "Command Complete --> %d\n",
359 DWC3_DEPCMD_STATUS(reg));
de03d218
SSB		 360 if (DWC3_DEPCMD_STATUS(reg))
361 return -EINVAL;
72246da4
FB		 362 return 0;
363 }
364
365 /*
72246da4
FB		 366 * We can't sleep here, because it is also called from
367 * interrupt context.
368 */
369 timeout--;
370 if (!timeout)
371 return -ETIMEDOUT;
372
61d58242 373 udelay(1);
72246da4
FB		 374 } while (1);
375}
376
377static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
f6bafc6a 378 struct dwc3_trb *trb)
72246da4 379{
c439ef87 380 u32 offset = (char *) trb - (char *) dep->trb_pool;
72246da4
FB		 381
382 return dep->trb_pool_dma + offset;
383}
384
385static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
386{
387 struct dwc3 *dwc = dep->dwc;
388
389 if (dep->trb_pool)
390 return 0;
391
392 if (dep->number == 0 || dep->number == 1)
393 return 0;
394
395 dep->trb_pool = dma_alloc_coherent(dwc->dev,
396 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
397 &dep->trb_pool_dma, GFP_KERNEL);
398 if (!dep->trb_pool) {
399 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
400 dep->name);
401 return -ENOMEM;
402 }
403
404 return 0;
405}
406
407static void dwc3_free_trb_pool(struct dwc3_ep *dep)
408{
409 struct dwc3 *dwc = dep->dwc;
410
411 dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
412 dep->trb_pool, dep->trb_pool_dma);
413
414 dep->trb_pool = NULL;
415 dep->trb_pool_dma = 0;
416}
417
418static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
419{
420 struct dwc3_gadget_ep_cmd_params params;
421 u32 cmd;
422
423 memset(&params, 0x00, sizeof(params));
424
425 if (dep->number != 1) {
426 cmd = DWC3_DEPCMD_DEPSTARTCFG;
427 /* XferRscIdx == 0 for ep0 and 2 for the remaining */
b23c8439
PZ		 428 if (dep->number > 1) {
429 if (dwc->start_config_issued)
430 return 0;
431 dwc->start_config_issued = true;
72246da4 432 cmd |= DWC3_DEPCMD_PARAM(2);
b23c8439 433 }
72246da4
FB		 434
435 return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, &params);
436 }
437
438 return 0;
439}
440
441static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
c90bfaec 442 const struct usb_endpoint_descriptor *desc,
4b345c9a
FB		 443 const struct usb_ss_ep_comp_descriptor *comp_desc,
444 bool ignore)
72246da4
FB		 445{
446 struct dwc3_gadget_ep_cmd_params params;
447
448 memset(&params, 0x00, sizeof(params));
449
dc1c70a7 450 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
d2e9a13a
CP		 451 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
452
453 /* Burst size is only needed in SuperSpeed mode */
454 if (dwc->gadget.speed == USB_SPEED_SUPER) {
455 u32 burst = dep->endpoint.maxburst - 1;
456
457 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst);
458 }
72246da4 459
4b345c9a
FB		 460 if (ignore)
461 params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM;
462
dc1c70a7
FB		 463 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
464 | DWC3_DEPCFG_XFER_NOT_READY_EN;
72246da4 465
18b7ede5 466 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
dc1c70a7
FB		 467 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
468 | DWC3_DEPCFG_STREAM_EVENT_EN;
879631aa
FB		 469 dep->stream_capable = true;
470 }
471
72246da4 472 if (usb_endpoint_xfer_isoc(desc))
dc1c70a7 473 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
72246da4
FB		 474
475 /*
476 * We are doing 1:1 mapping for endpoints, meaning
477 * Physical Endpoints 2 maps to Logical Endpoint 2 and
478 * so on. We consider the direction bit as part of the physical
479 * endpoint number. So USB endpoint 0x81 is 0x03.
480 */
dc1c70a7 481 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
72246da4
FB		 482
483 /*
484 * We must use the lower 16 TX FIFOs even though
485 * HW might have more
486 */
487 if (dep->direction)
dc1c70a7 488 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
72246da4
FB		 489
490 if (desc->bInterval) {
dc1c70a7 491 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
72246da4
FB		 492 dep->interval = 1 << (desc->bInterval - 1);
493 }
494
495 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
496 DWC3_DEPCMD_SETEPCONFIG, &params);
497}
498
499static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
500{
501 struct dwc3_gadget_ep_cmd_params params;
502
503 memset(&params, 0x00, sizeof(params));
504
dc1c70a7 505 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
72246da4
FB		 506
507 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
508 DWC3_DEPCMD_SETTRANSFRESOURCE, &params);
509}
510
511/**
512 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
513 * @dep: endpoint to be initialized
514 * @desc: USB Endpoint Descriptor
515 *
516 * Caller should take care of locking
517 */
518static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
c90bfaec 519 const struct usb_endpoint_descriptor *desc,
4b345c9a
FB		 520 const struct usb_ss_ep_comp_descriptor *comp_desc,
521 bool ignore)
72246da4
FB		 522{
523 struct dwc3 *dwc = dep->dwc;
524 u32 reg;
525 int ret = -ENOMEM;
526
527 if (!(dep->flags & DWC3_EP_ENABLED)) {
528 ret = dwc3_gadget_start_config(dwc, dep);
529 if (ret)
530 return ret;
531 }
532
4b345c9a 533 ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore);
72246da4
FB		 534 if (ret)
535 return ret;
536
537 if (!(dep->flags & DWC3_EP_ENABLED)) {
f6bafc6a
FB		 538 struct dwc3_trb *trb_st_hw;
539 struct dwc3_trb *trb_link;
72246da4
FB		 540
541 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
542 if (ret)
543 return ret;
544
16e78db7 545 dep->endpoint.desc = desc;
c90bfaec 546 dep->comp_desc = comp_desc;
72246da4
FB		 547 dep->type = usb_endpoint_type(desc);
548 dep->flags |= DWC3_EP_ENABLED;
549
550 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
551 reg |= DWC3_DALEPENA_EP(dep->number);
552 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
553
554 if (!usb_endpoint_xfer_isoc(desc))
555 return 0;
556
1d046793 557 /* Link TRB for ISOC. The HWO bit is never reset */
72246da4
FB		 558 trb_st_hw = &dep->trb_pool[0];
559
f6bafc6a 560 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
6b93e366 561 memset(trb_link, 0, sizeof(*trb_link));
72246da4 562
f6bafc6a
FB		 563 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
564 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
565 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
566 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
72246da4
FB		 567 }
568
569 return 0;
570}
571
624407f9
SAS		 572static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum);
573static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
72246da4
FB		 574{
575 struct dwc3_request *req;
576
ea53b882 577 if (!list_empty(&dep->req_queued)) {
624407f9
SAS		 578 dwc3_stop_active_transfer(dwc, dep->number);
579
57911504 580 /* - giveback all requests to gadget driver */
1591633e
PA		 581 while (!list_empty(&dep->req_queued)) {
582 req = next_request(&dep->req_queued);
583
584 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
585 }
ea53b882
FB		 586 }
587
72246da4
FB		 588 while (!list_empty(&dep->request_list)) {
589 req = next_request(&dep->request_list);
590
624407f9 591 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
72246da4 592 }
72246da4
FB		 593}
594
595/**
596 * __dwc3_gadget_ep_disable - Disables a HW endpoint
597 * @dep: the endpoint to disable
598 *
624407f9
SAS		 599 * This function also removes requests which are currently processed ny the
600 * hardware and those which are not yet scheduled.
601 * Caller should take care of locking.
72246da4 602 */
72246da4
FB		 603static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
604{
605 struct dwc3 *dwc = dep->dwc;
606 u32 reg;
607
624407f9 608 dwc3_remove_requests(dwc, dep);
72246da4 609
c3ea18ca
FB		 610 /* make sure HW endpoint isn't stalled */
611 if (dep->flags & DWC3_EP_STALL)
7d513758 612 __dwc3_gadget_ep_set_halt(dep, 0, false);
c3ea18ca 613
72246da4
FB		 614 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
615 reg &= ~DWC3_DALEPENA_EP(dep->number);
616 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
617
879631aa 618 dep->stream_capable = false;
f9c56cdd 619 dep->endpoint.desc = NULL;
c90bfaec 620 dep->comp_desc = NULL;
72246da4 621 dep->type = 0;
879631aa 622 dep->flags = 0;
72246da4
FB		 623
624 return 0;
625}
626
627/* -------------------------------------------------------------------------- */
628
629static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
630 const struct usb_endpoint_descriptor *desc)
631{
632 return -EINVAL;
633}
634
635static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
636{
637 return -EINVAL;
638}
639
640/* -------------------------------------------------------------------------- */
641
642static int dwc3_gadget_ep_enable(struct usb_ep *ep,
643 const struct usb_endpoint_descriptor *desc)
644{
645 struct dwc3_ep *dep;
646 struct dwc3 *dwc;
647 unsigned long flags;
648 int ret;
649
650 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
651 pr_debug("dwc3: invalid parameters\n");
652 return -EINVAL;
653 }
654
655 if (!desc->wMaxPacketSize) {
656 pr_debug("dwc3: missing wMaxPacketSize\n");
657 return -EINVAL;
658 }
659
660 dep = to_dwc3_ep(ep);
661 dwc = dep->dwc;
662
c6f83f38
FB		 663 if (dep->flags & DWC3_EP_ENABLED) {
664 dev_WARN_ONCE(dwc->dev, true, "%s is already enabled\n",
665 dep->name);
666 return 0;
667 }
668
72246da4
FB		 669 switch (usb_endpoint_type(desc)) {
670 case USB_ENDPOINT_XFER_CONTROL:
27a78d6a 671 strlcat(dep->name, "-control", sizeof(dep->name));
72246da4
FB		 672 break;
673 case USB_ENDPOINT_XFER_ISOC:
27a78d6a 674 strlcat(dep->name, "-isoc", sizeof(dep->name));
72246da4
FB		 675 break;
676 case USB_ENDPOINT_XFER_BULK:
27a78d6a 677 strlcat(dep->name, "-bulk", sizeof(dep->name));
72246da4
FB		 678 break;
679 case USB_ENDPOINT_XFER_INT:
27a78d6a 680 strlcat(dep->name, "-int", sizeof(dep->name));
72246da4
FB		 681 break;
682 default:
683 dev_err(dwc->dev, "invalid endpoint transfer type\n");
684 }
685
72246da4
FB		 686 dev_vdbg(dwc->dev, "Enabling %s\n", dep->name);
687
688 spin_lock_irqsave(&dwc->lock, flags);
4b345c9a 689 ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false);
72246da4
FB		 690 spin_unlock_irqrestore(&dwc->lock, flags);
691
692 return ret;
693}
694
695static int dwc3_gadget_ep_disable(struct usb_ep *ep)
696{
697 struct dwc3_ep *dep;
698 struct dwc3 *dwc;
699 unsigned long flags;
700 int ret;
701
702 if (!ep) {
703 pr_debug("dwc3: invalid parameters\n");
704 return -EINVAL;
705 }
706
707 dep = to_dwc3_ep(ep);
708 dwc = dep->dwc;
709
710 if (!(dep->flags & DWC3_EP_ENABLED)) {
711 dev_WARN_ONCE(dwc->dev, true, "%s is already disabled\n",
712 dep->name);
713 return 0;
714 }
715
716 snprintf(dep->name, sizeof(dep->name), "ep%d%s",
717 dep->number >> 1,
718 (dep->number & 1) ? "in" : "out");
719
720 spin_lock_irqsave(&dwc->lock, flags);
721 ret = __dwc3_gadget_ep_disable(dep);
722 spin_unlock_irqrestore(&dwc->lock, flags);
723
724 return ret;
725}
726
727static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
728 gfp_t gfp_flags)
729{
730 struct dwc3_request *req;
731 struct dwc3_ep *dep = to_dwc3_ep(ep);
732 struct dwc3 *dwc = dep->dwc;
733
734 req = kzalloc(sizeof(*req), gfp_flags);
735 if (!req) {
736 dev_err(dwc->dev, "not enough memory\n");
737 return NULL;
738 }
739
740 req->epnum = dep->number;
741 req->dep = dep;
72246da4
FB		 742
743 return &req->request;
744}
745
746static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
747 struct usb_request *request)
748{
749 struct dwc3_request *req = to_dwc3_request(request);
750
751 kfree(req);
752}
753
c71fc37c
FB		 754/**
755 * dwc3_prepare_one_trb - setup one TRB from one request
756 * @dep: endpoint for which this request is prepared
757 * @req: dwc3_request pointer
758 */
68e823e2 759static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
eeb720fb 760 struct dwc3_request *req, dma_addr_t dma,
e5ba5ec8 761 unsigned length, unsigned last, unsigned chain, unsigned node)
c71fc37c 762{
eeb720fb 763 struct dwc3 *dwc = dep->dwc;
f6bafc6a 764 struct dwc3_trb *trb;
c71fc37c 765
eeb720fb
FB		 766 dev_vdbg(dwc->dev, "%s: req %p dma %08llx length %d%s%s\n",
767 dep->name, req, (unsigned long long) dma,
768 length, last ? " last" : "",
769 chain ? " chain" : "");
770
c71fc37c 771 /* Skip the LINK-TRB on ISOC */
915e202a 772 if (((dep->free_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
16e78db7 773 usb_endpoint_xfer_isoc(dep->endpoint.desc))
915e202a
PA		 774 dep->free_slot++;
775
776 trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
c71fc37c 777
eeb720fb
FB		 778 if (!req->trb) {
779 dwc3_gadget_move_request_queued(req);
f6bafc6a
FB		 780 req->trb = trb;
781 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
e5ba5ec8 782 req->start_slot = dep->free_slot & DWC3_TRB_MASK;
eeb720fb 783 }
c71fc37c 784
e5ba5ec8
PA		 785 dep->free_slot++;
786
f6bafc6a
FB		 787 trb->size = DWC3_TRB_SIZE_LENGTH(length);
788 trb->bpl = lower_32_bits(dma);
789 trb->bph = upper_32_bits(dma);
c71fc37c 790
16e78db7 791 switch (usb_endpoint_type(dep->endpoint.desc)) {
c71fc37c 792 case USB_ENDPOINT_XFER_CONTROL:
f6bafc6a 793 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
c71fc37c
FB		 794 break;
795
796 case USB_ENDPOINT_XFER_ISOC:
e5ba5ec8
PA		 797 if (!node)
798 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
799 else
800 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
c71fc37c 801
e5ba5ec8 802 if (!req->request.no_interrupt && !chain)
f6bafc6a 803 trb->ctrl |= DWC3_TRB_CTRL_IOC;
c71fc37c
FB		 804 break;
805
806 case USB_ENDPOINT_XFER_BULK:
807 case USB_ENDPOINT_XFER_INT:
f6bafc6a 808 trb->ctrl = DWC3_TRBCTL_NORMAL;
c71fc37c
FB		 809 break;
810 default:
811 /*
812 * This is only possible with faulty memory because we
813 * checked it already :)
814 */
815 BUG();
816 }
817
16e78db7 818 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
f6bafc6a
FB		 819 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
820 trb->ctrl |= DWC3_TRB_CTRL_CSP;
e5ba5ec8
PA		 821 } else if (last) {
822 trb->ctrl |= DWC3_TRB_CTRL_LST;
f6bafc6a 823 }
c71fc37c 824
e5ba5ec8
PA		 825 if (chain)
826 trb->ctrl |= DWC3_TRB_CTRL_CHN;
827
16e78db7 828 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
f6bafc6a 829 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
c71fc37c 830
f6bafc6a 831 trb->ctrl |= DWC3_TRB_CTRL_HWO;
c71fc37c
FB		 832}
833
72246da4
FB		 834/*
835 * dwc3_prepare_trbs - setup TRBs from requests
836 * @dep: endpoint for which requests are being prepared
837 * @starting: true if the endpoint is idle and no requests are queued.
838 *
1d046793
PZ		 839 * The function goes through the requests list and sets up TRBs for the
840 * transfers. The function returns once there are no more TRBs available or
841 * it runs out of requests.
72246da4 842 */
68e823e2 843static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
72246da4 844{
68e823e2 845 struct dwc3_request *req, *n;
72246da4 846 u32 trbs_left;
8d62cd65 847 u32 max;
c71fc37c 848 unsigned int last_one = 0;
72246da4
FB		 849
850 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
851
852 /* the first request must not be queued */
853 trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
c71fc37c 854
8d62cd65 855 /* Can't wrap around on a non-isoc EP since there's no link TRB */
16e78db7 856 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
8d62cd65
PZ		 857 max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK);
858 if (trbs_left > max)
859 trbs_left = max;
860 }
861
72246da4 862 /*
1d046793
PZ		 863 * If busy & slot are equal than it is either full or empty. If we are
864 * starting to process requests then we are empty. Otherwise we are
72246da4
FB		 865 * full and don't do anything
866 */
867 if (!trbs_left) {
868 if (!starting)
68e823e2 869 return;
72246da4
FB		 870 trbs_left = DWC3_TRB_NUM;
871 /*
872 * In case we start from scratch, we queue the ISOC requests
873 * starting from slot 1. This is done because we use ring
874 * buffer and have no LST bit to stop us. Instead, we place
1d046793 875 * IOC bit every TRB_NUM/4. We try to avoid having an interrupt
72246da4
FB		 876 * after the first request so we start at slot 1 and have
877 * 7 requests proceed before we hit the first IOC.
878 * Other transfer types don't use the ring buffer and are
879 * processed from the first TRB until the last one. Since we
880 * don't wrap around we have to start at the beginning.
881 */
16e78db7 882 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
72246da4
FB		 883 dep->busy_slot = 1;
884 dep->free_slot = 1;
885 } else {
886 dep->busy_slot = 0;
887 dep->free_slot = 0;
888 }
889 }
890
891 /* The last TRB is a link TRB, not used for xfer */
16e78db7 892 if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc))
68e823e2 893 return;
72246da4
FB		 894
895 list_for_each_entry_safe(req, n, &dep->request_list, list) {
eeb720fb
FB		 896 unsigned length;
897 dma_addr_t dma;
e5ba5ec8 898 last_one = false;
72246da4 899
eeb720fb
FB		 900 if (req->request.num_mapped_sgs > 0) {
901 struct usb_request *request = &req->request;
902 struct scatterlist *sg = request->sg;
903 struct scatterlist *s;
904 int i;
72246da4 905
eeb720fb
FB		 906 for_each_sg(sg, s, request->num_mapped_sgs, i) {
907 unsigned chain = true;
72246da4 908
eeb720fb
FB		 909 length = sg_dma_len(s);
910 dma = sg_dma_address(s);
72246da4 911
1d046793
PZ		 912 if (i == (request->num_mapped_sgs - 1) ||
913 sg_is_last(s)) {
94b762f0 914 if (list_empty(&dep->request_list))
e5ba5ec8 915 last_one = true;
eeb720fb
FB		 916 chain = false;
917 }
72246da4 918
eeb720fb
FB		 919 trbs_left--;
920 if (!trbs_left)
921 last_one = true;
72246da4 922
eeb720fb
FB		 923 if (last_one)
924 chain = false;
72246da4 925
eeb720fb 926 dwc3_prepare_one_trb(dep, req, dma, length,
e5ba5ec8 927 last_one, chain, i);
72246da4 928
eeb720fb
FB		 929 if (last_one)
930 break;
931 }
a3664806
AV		 932
933 if (last_one)
934 break;
72246da4 935 } else {
eeb720fb
FB		 936 dma = req->request.dma;
937 length = req->request.length;
938 trbs_left--;
72246da4 939
eeb720fb
FB		 940 if (!trbs_left)
941 last_one = 1;
879631aa 942
eeb720fb
FB		 943 /* Is this the last request? */
944 if (list_is_last(&req->list, &dep->request_list))
945 last_one = 1;
72246da4 946
eeb720fb 947 dwc3_prepare_one_trb(dep, req, dma, length,
e5ba5ec8 948 last_one, false, 0);
72246da4 949
eeb720fb
FB		 950 if (last_one)
951 break;
72246da4 952 }
72246da4 953 }
72246da4
FB		 954}
955
956static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
957 int start_new)
958{
959 struct dwc3_gadget_ep_cmd_params params;
960 struct dwc3_request *req;
961 struct dwc3 *dwc = dep->dwc;
962 int ret;
963 u32 cmd;
964
965 if (start_new && (dep->flags & DWC3_EP_BUSY)) {
966 dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name);
967 return -EBUSY;
968 }
969 dep->flags &= ~DWC3_EP_PENDING_REQUEST;
970
971 /*
972 * If we are getting here after a short-out-packet we don't enqueue any
973 * new requests as we try to set the IOC bit only on the last request.
974 */
975 if (start_new) {
976 if (list_empty(&dep->req_queued))
977 dwc3_prepare_trbs(dep, start_new);
978
979 /* req points to the first request which will be sent */
980 req = next_request(&dep->req_queued);
981 } else {
68e823e2
FB		 982 dwc3_prepare_trbs(dep, start_new);
983
72246da4 984 /*
1d046793 985 * req points to the first request where HWO changed from 0 to 1
72246da4 986 */
68e823e2 987 req = next_request(&dep->req_queued);
72246da4
FB		 988 }
989 if (!req) {
990 dep->flags |= DWC3_EP_PENDING_REQUEST;
991 return 0;
992 }
993
994 memset(&params, 0, sizeof(params));
72246da4 995
1877d6c9
PA		 996 if (start_new) {
997 params.param0 = upper_32_bits(req->trb_dma);
998 params.param1 = lower_32_bits(req->trb_dma);
72246da4 999 cmd = DWC3_DEPCMD_STARTTRANSFER;
1877d6c9 1000 } else {
72246da4 1001 cmd = DWC3_DEPCMD_UPDATETRANSFER;
1877d6c9 1002 }
72246da4
FB		 1003
1004 cmd |= DWC3_DEPCMD_PARAM(cmd_param);
1005 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
1006 if (ret < 0) {
1007 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
1008
1009 /*
1010 * FIXME we need to iterate over the list of requests
1011 * here and stop, unmap, free and del each of the linked
1d046793 1012 * requests instead of what we do now.
72246da4 1013 */
0fc9a1be
FB		 1014 usb_gadget_unmap_request(&dwc->gadget, &req->request,
1015 req->direction);
72246da4
FB		 1016 list_del(&req->list);
1017 return ret;
1018 }
1019
1020 dep->flags |= DWC3_EP_BUSY;
25b8ff68 1021
f898ae09 1022 if (start_new) {
b4996a86 1023 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
f898ae09 1024 dep->number);
b4996a86 1025 WARN_ON_ONCE(!dep->resource_index);
f898ae09 1026 }
25b8ff68 1027
72246da4
FB		 1028 return 0;
1029}
1030
d6d6ec7b
PA		 1031static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1032 struct dwc3_ep *dep, u32 cur_uf)
1033{
1034 u32 uf;
1035
1036 if (list_empty(&dep->request_list)) {
1037 dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n",
1038 dep->name);
f4a53c55 1039 dep->flags |= DWC3_EP_PENDING_REQUEST;
d6d6ec7b
PA		 1040 return;
1041 }
1042
1043 /* 4 micro frames in the future */
1044 uf = cur_uf + dep->interval * 4;
1045
1046 __dwc3_gadget_kick_transfer(dep, uf, 1);
1047}
1048
1049static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1050 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1051{
1052 u32 cur_uf, mask;
1053
1054 mask = ~(dep->interval - 1);
1055 cur_uf = event->parameters & mask;
1056
1057 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1058}
1059
72246da4
FB		 1060static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1061{
0fc9a1be
FB		 1062 struct dwc3 *dwc = dep->dwc;
1063 int ret;
1064
72246da4
FB		 1065 req->request.actual = 0;
1066 req->request.status = -EINPROGRESS;
1067 req->direction = dep->direction;
1068 req->epnum = dep->number;
1069
1070 /*
1071 * We only add to our list of requests now and
1072 * start consuming the list once we get XferNotReady
1073 * IRQ.
1074 *
1075 * That way, we avoid doing anything that we don't need
1076 * to do now and defer it until the point we receive a
1077 * particular token from the Host side.
1078 *
1079 * This will also avoid Host cancelling URBs due to too
1d046793 1080 * many NAKs.
72246da4 1081 */
0fc9a1be
FB		 1082 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1083 dep->direction);
1084 if (ret)
1085 return ret;
1086
72246da4
FB		 1087 list_add_tail(&req->list, &dep->request_list);
1088
1089 /*
b511e5e7 1090 * There are a few special cases:
72246da4 1091 *
f898ae09
PZ		 1092 * 1. XferNotReady with empty list of requests. We need to kick the
1093 * transfer here in that situation, otherwise we will be NAKing
1094 * forever. If we get XferNotReady before gadget driver has a
1095 * chance to queue a request, we will ACK the IRQ but won't be
1096 * able to receive the data until the next request is queued.
1097 * The following code is handling exactly that.
72246da4 1098 *
72246da4
FB		 1099 */
1100 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
f4a53c55
PA		 1101 /*
1102 * If xfernotready is already elapsed and it is a case
1103 * of isoc transfer, then issue END TRANSFER, so that
1104 * you can receive xfernotready again and can have
1105 * notion of current microframe.
1106 */
1107 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
cdc359dd
PA		 1108 if (list_empty(&dep->req_queued)) {
1109 dwc3_stop_active_transfer(dwc, dep->number);
1110 dep->flags = DWC3_EP_ENABLED;
1111 }
f4a53c55
PA		 1112 return 0;
1113 }
1114
b511e5e7 1115 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
348e026f 1116 if (ret && ret != -EBUSY)
b511e5e7
FB		 1117 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1118 dep->name);
15f86bde 1119 return ret;
b511e5e7 1120 }
72246da4 1121
b511e5e7
FB		 1122 /*
1123 * 2. XferInProgress on Isoc EP with an active transfer. We need to
1124 * kick the transfer here after queuing a request, otherwise the
1125 * core may not see the modified TRB(s).
1126 */
1127 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
79c9046e
PA		 1128 (dep->flags & DWC3_EP_BUSY) &&
1129 !(dep->flags & DWC3_EP_MISSED_ISOC)) {
b4996a86
FB		 1130 WARN_ON_ONCE(!dep->resource_index);
1131 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index,
b511e5e7 1132 false);
348e026f 1133 if (ret && ret != -EBUSY)
72246da4
FB		 1134 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1135 dep->name);
15f86bde 1136 return ret;
a0925324 1137 }
72246da4
FB		 1138
1139 return 0;
1140}
1141
1142static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1143 gfp_t gfp_flags)
1144{
1145 struct dwc3_request *req = to_dwc3_request(request);
1146 struct dwc3_ep *dep = to_dwc3_ep(ep);
1147 struct dwc3 *dwc = dep->dwc;
1148
1149 unsigned long flags;
1150
1151 int ret;
1152
16e78db7 1153 if (!dep->endpoint.desc) {
72246da4
FB		 1154 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
1155 request, ep->name);
1156 return -ESHUTDOWN;
1157 }
1158
1159 dev_vdbg(dwc->dev, "queing request %p to %s length %d\n",
1160 request, ep->name, request->length);
1161
1162 spin_lock_irqsave(&dwc->lock, flags);
1163 ret = __dwc3_gadget_ep_queue(dep, req);
1164 spin_unlock_irqrestore(&dwc->lock, flags);
1165
1166 return ret;
1167}
1168
1169static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1170 struct usb_request *request)
1171{
1172 struct dwc3_request *req = to_dwc3_request(request);
1173 struct dwc3_request *r = NULL;
1174
1175 struct dwc3_ep *dep = to_dwc3_ep(ep);
1176 struct dwc3 *dwc = dep->dwc;
1177
1178 unsigned long flags;
1179 int ret = 0;
1180
1181 spin_lock_irqsave(&dwc->lock, flags);
1182
1183 list_for_each_entry(r, &dep->request_list, list) {
1184 if (r == req)
1185 break;
1186 }
1187
1188 if (r != req) {
1189 list_for_each_entry(r, &dep->req_queued, list) {
1190 if (r == req)
1191 break;
1192 }
1193 if (r == req) {
1194 /* wait until it is processed */
1195 dwc3_stop_active_transfer(dwc, dep->number);
e8d4e8be 1196 goto out1;
72246da4
FB		 1197 }
1198 dev_err(dwc->dev, "request %p was not queued to %s\n",
1199 request, ep->name);
1200 ret = -EINVAL;
1201 goto out0;
1202 }
1203
e8d4e8be 1204out1:
72246da4
FB		 1205 /* giveback the request */
1206 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1207
1208out0:
1209 spin_unlock_irqrestore(&dwc->lock, flags);
1210
1211 return ret;
1212}
1213
7d513758 1214int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
72246da4
FB		 1215{
1216 struct dwc3_gadget_ep_cmd_params params;
1217 struct dwc3 *dwc = dep->dwc;
1218 int ret;
1219
1220 memset(&params, 0x00, sizeof(params));
1221
1222 if (value) {
7d513758
FB		 1223 if (!protocol && ((dep->direction && dep->flags & DWC3_EP_BUSY) ||
1224 (!list_empty(&dep->req_queued) ||
1225 !list_empty(&dep->request_list)))) {
1226 dev_dbg(dwc->dev, "%s: pending request, cannot halt\n",
1227 dep->name);
1228 return -EAGAIN;
1229 }
1230
72246da4
FB		 1231 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1232 DWC3_DEPCMD_SETSTALL, &params);
1233 if (ret)
1234 dev_err(dwc->dev, "failed to %s STALL on %s\n",
1235 value ? "set" : "clear",
1236 dep->name);
1237 else
1238 dep->flags |= DWC3_EP_STALL;
1239 } else {
1240 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1241 DWC3_DEPCMD_CLEARSTALL, &params);
1242 if (ret)
1243 dev_err(dwc->dev, "failed to %s STALL on %s\n",
1244 value ? "set" : "clear",
1245 dep->name);
1246 else
e6303463 1247 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
72246da4 1248 }
5275455a 1249
72246da4
FB		 1250 return ret;
1251}
1252
1253static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1254{
1255 struct dwc3_ep *dep = to_dwc3_ep(ep);
1256 struct dwc3 *dwc = dep->dwc;
1257
1258 unsigned long flags;
1259
1260 int ret;
1261
1262 spin_lock_irqsave(&dwc->lock, flags);
1263
16e78db7 1264 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
72246da4
FB		 1265 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1266 ret = -EINVAL;
1267 goto out;
1268 }
1269
7d513758 1270 ret = __dwc3_gadget_ep_set_halt(dep, value, false);
72246da4
FB		 1271out:
1272 spin_unlock_irqrestore(&dwc->lock, flags);
1273
1274 return ret;
1275}
1276
1277static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1278{
1279 struct dwc3_ep *dep = to_dwc3_ep(ep);
249a4569
PZ		 1280 struct dwc3 *dwc = dep->dwc;
1281 unsigned long flags;
72246da4 1282
249a4569 1283 spin_lock_irqsave(&dwc->lock, flags);
72246da4 1284 dep->flags |= DWC3_EP_WEDGE;
249a4569 1285 spin_unlock_irqrestore(&dwc->lock, flags);
72246da4 1286
08f0d966
PA		 1287 if (dep->number == 0 || dep->number == 1)
1288 return dwc3_gadget_ep0_set_halt(ep, 1);
1289 else
7d513758 1290 return __dwc3_gadget_ep_set_halt(dep, 1, false);
72246da4
FB		 1291}
1292
1293/* -------------------------------------------------------------------------- */
1294
1295static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1296 .bLength = USB_DT_ENDPOINT_SIZE,
1297 .bDescriptorType = USB_DT_ENDPOINT,
1298 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1299};
1300
1301static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1302 .enable = dwc3_gadget_ep0_enable,
1303 .disable = dwc3_gadget_ep0_disable,
1304 .alloc_request = dwc3_gadget_ep_alloc_request,
1305 .free_request = dwc3_gadget_ep_free_request,
1306 .queue = dwc3_gadget_ep0_queue,
1307 .dequeue = dwc3_gadget_ep_dequeue,
08f0d966 1308 .set_halt = dwc3_gadget_ep0_set_halt,
72246da4
FB		 1309 .set_wedge = dwc3_gadget_ep_set_wedge,
1310};
1311
1312static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1313 .enable = dwc3_gadget_ep_enable,
1314 .disable = dwc3_gadget_ep_disable,
1315 .alloc_request = dwc3_gadget_ep_alloc_request,
1316 .free_request = dwc3_gadget_ep_free_request,
1317 .queue = dwc3_gadget_ep_queue,
1318 .dequeue = dwc3_gadget_ep_dequeue,
1319 .set_halt = dwc3_gadget_ep_set_halt,
1320 .set_wedge = dwc3_gadget_ep_set_wedge,
1321};
1322
1323/* -------------------------------------------------------------------------- */
1324
1325static int dwc3_gadget_get_frame(struct usb_gadget *g)
1326{
1327 struct dwc3 *dwc = gadget_to_dwc(g);
1328 u32 reg;
1329
1330 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1331 return DWC3_DSTS_SOFFN(reg);
1332}
1333
1334static int dwc3_gadget_wakeup(struct usb_gadget *g)
1335{
1336 struct dwc3 *dwc = gadget_to_dwc(g);
1337
1338 unsigned long timeout;
1339 unsigned long flags;
1340
1341 u32 reg;
1342
1343 int ret = 0;
1344
1345 u8 link_state;
1346 u8 speed;
1347
1348 spin_lock_irqsave(&dwc->lock, flags);
1349
1350 /*
1351 * According to the Databook Remote wakeup request should
1352 * be issued only when the device is in early suspend state.
1353 *
1354 * We can check that via USB Link State bits in DSTS register.
1355 */
1356 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1357
1358 speed = reg & DWC3_DSTS_CONNECTSPD;
1359 if (speed == DWC3_DSTS_SUPERSPEED) {
1360 dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n");
1361 ret = -EINVAL;
1362 goto out;
1363 }
1364
1365 link_state = DWC3_DSTS_USBLNKST(reg);
1366
1367 switch (link_state) {
1368 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1369 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1370 break;
1371 default:
1372 dev_dbg(dwc->dev, "can't wakeup from link state %d\n",
1373 link_state);
1374 ret = -EINVAL;
1375 goto out;
1376 }
1377
8598bde7
FB		 1378 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1379 if (ret < 0) {
1380 dev_err(dwc->dev, "failed to put link in Recovery\n");
1381 goto out;
1382 }
72246da4 1383
802fde98
PZ		 1384 /* Recent versions do this automatically */
1385 if (dwc->revision < DWC3_REVISION_194A) {
1386 /* write zeroes to Link Change Request */
fcc023c7 1387 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
802fde98
PZ		 1388 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1389 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1390 }
72246da4 1391
1d046793 1392 /* poll until Link State changes to ON */
72246da4
FB		 1393 timeout = jiffies + msecs_to_jiffies(100);
1394
1d046793 1395 while (!time_after(jiffies, timeout)) {
72246da4
FB		 1396 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1397
1398 /* in HS, means ON */
1399 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1400 break;
1401 }
1402
1403 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1404 dev_err(dwc->dev, "failed to send remote wakeup\n");
1405 ret = -EINVAL;
1406 }
1407
1408out:
1409 spin_unlock_irqrestore(&dwc->lock, flags);
1410
1411 return ret;
1412}
1413
1414static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1415 int is_selfpowered)
1416{
1417 struct dwc3 *dwc = gadget_to_dwc(g);
249a4569 1418 unsigned long flags;
72246da4 1419
249a4569 1420 spin_lock_irqsave(&dwc->lock, flags);
72246da4 1421 dwc->is_selfpowered = !!is_selfpowered;
249a4569 1422 spin_unlock_irqrestore(&dwc->lock, flags);
72246da4
FB		 1423
1424 return 0;
1425}
1426
6f17f74b 1427static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on)
72246da4
FB		 1428{
1429 u32 reg;
61d58242 1430 u32 timeout = 500;
72246da4
FB		 1431
1432 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
8db7ed15 1433 if (is_on) {
802fde98
PZ		 1434 if (dwc->revision <= DWC3_REVISION_187A) {
1435 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1436 reg |= DWC3_DCTL_TRGTULST_RX_DET;
1437 }
1438
1439 if (dwc->revision >= DWC3_REVISION_194A)
1440 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1441 reg |= DWC3_DCTL_RUN_STOP;
9fcb3bd8 1442 dwc->pullups_connected = true;
8db7ed15 1443 } else {
72246da4 1444 reg &= ~DWC3_DCTL_RUN_STOP;
9fcb3bd8 1445 dwc->pullups_connected = false;
8db7ed15 1446 }
72246da4
FB		 1447
1448 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1449
1450 do {
1451 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1452 if (is_on) {
1453 if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1454 break;
1455 } else {
1456 if (reg & DWC3_DSTS_DEVCTRLHLT)
1457 break;
1458 }
72246da4
FB		 1459 timeout--;
1460 if (!timeout)
6f17f74b 1461 return -ETIMEDOUT;
61d58242 1462 udelay(1);
72246da4
FB		 1463 } while (1);
1464
1465 dev_vdbg(dwc->dev, "gadget %s data soft-%s\n",
1466 dwc->gadget_driver
1467 ? dwc->gadget_driver->function : "no-function",
1468 is_on ? "connect" : "disconnect");
6f17f74b
PA		 1469
1470 return 0;
72246da4
FB		 1471}
1472
1473static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1474{
1475 struct dwc3 *dwc = gadget_to_dwc(g);
1476 unsigned long flags;
6f17f74b 1477 int ret;
72246da4
FB		 1478
1479 is_on = !!is_on;
1480
1481 spin_lock_irqsave(&dwc->lock, flags);
6f17f74b 1482 ret = dwc3_gadget_run_stop(dwc, is_on);
72246da4
FB		 1483 spin_unlock_irqrestore(&dwc->lock, flags);
1484
6f17f74b 1485 return ret;
72246da4
FB		 1486}
1487
8698e2ac
FB		 1488static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1489{
1490 u32 reg;
1491
1492 /* Enable all but Start and End of Frame IRQs */
1493 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1494 DWC3_DEVTEN_EVNTOVERFLOWEN |
1495 DWC3_DEVTEN_CMDCMPLTEN |
1496 DWC3_DEVTEN_ERRTICERREN |
1497 DWC3_DEVTEN_WKUPEVTEN |
1498 DWC3_DEVTEN_ULSTCNGEN |
1499 DWC3_DEVTEN_CONNECTDONEEN |
1500 DWC3_DEVTEN_USBRSTEN |
1501 DWC3_DEVTEN_DISCONNEVTEN);
1502
1503 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1504}
1505
1506static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1507{
1508 /* mask all interrupts */
1509 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1510}
1511
1512static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
b15a762f 1513static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
8698e2ac 1514
72246da4
FB		 1515static int dwc3_gadget_start(struct usb_gadget *g,
1516 struct usb_gadget_driver *driver)
1517{
1518 struct dwc3 *dwc = gadget_to_dwc(g);
1519 struct dwc3_ep *dep;
1520 unsigned long flags;
1521 int ret = 0;
8698e2ac 1522 int irq;
72246da4
FB		 1523 u32 reg;
1524
734b2fe9
FB		 1525 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1526 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
1527 IRQF_SHARED | IRQF_ONESHOT, "dwc3", dwc);
1528 if (ret) {
1529 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1530 irq, ret);
1531 goto err0;
1532 }
1533
72246da4
FB		 1534 spin_lock_irqsave(&dwc->lock, flags);
1535
1536 if (dwc->gadget_driver) {
1537 dev_err(dwc->dev, "%s is already bound to %s\n",
1538 dwc->gadget.name,
1539 dwc->gadget_driver->driver.name);
1540 ret = -EBUSY;
734b2fe9 1541 goto err1;
72246da4
FB		 1542 }
1543
1544 dwc->gadget_driver = driver;
72246da4 1545
72246da4
FB		 1546 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1547 reg &= ~(DWC3_DCFG_SPEED_MASK);
07e7f47b
FB		 1548
1549 /**
1550 * WORKAROUND: DWC3 revision < 2.20a have an issue
1551 * which would cause metastability state on Run/Stop
1552 * bit if we try to force the IP to USB2-only mode.
1553 *
1554 * Because of that, we cannot configure the IP to any
1555 * speed other than the SuperSpeed
1556 *
1557 * Refers to:
1558 *
1559 * STAR#9000525659: Clock Domain Crossing on DCTL in
1560 * USB 2.0 Mode
1561 */
1562 if (dwc->revision < DWC3_REVISION_220A)
1563 reg |= DWC3_DCFG_SUPERSPEED;
1564 else
1565 reg |= dwc->maximum_speed;
72246da4
FB		 1566 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1567
b23c8439
PZ		 1568 dwc->start_config_issued = false;
1569
72246da4
FB		 1570 /* Start with SuperSpeed Default */
1571 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1572
1573 dep = dwc->eps[0];
4b345c9a 1574 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false);
72246da4
FB		 1575 if (ret) {
1576 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
734b2fe9 1577 goto err2;
72246da4
FB		 1578 }
1579
1580 dep = dwc->eps[1];
4b345c9a 1581 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false);
72246da4
FB		 1582 if (ret) {
1583 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
734b2fe9 1584 goto err3;
72246da4
FB		 1585 }
1586
1587 /* begin to receive SETUP packets */
c7fcdeb2 1588 dwc->ep0state = EP0_SETUP_PHASE;
72246da4
FB		 1589 dwc3_ep0_out_start(dwc);
1590
8698e2ac
FB		 1591 dwc3_gadget_enable_irq(dwc);
1592
72246da4
FB		 1593 spin_unlock_irqrestore(&dwc->lock, flags);
1594
1595 return 0;
1596
734b2fe9 1597err3:
72246da4
FB		 1598 __dwc3_gadget_ep_disable(dwc->eps[0]);
1599
734b2fe9 1600err2:
003dda8a 1601 dwc->gadget_driver = NULL;
734b2fe9
FB		 1602
1603err1:
72246da4
FB		 1604 spin_unlock_irqrestore(&dwc->lock, flags);
1605
734b2fe9
FB		 1606 free_irq(irq, dwc);
1607
1608err0:
72246da4
FB		 1609 return ret;
1610}
1611
1612static int dwc3_gadget_stop(struct usb_gadget *g,
1613 struct usb_gadget_driver *driver)
1614{
1615 struct dwc3 *dwc = gadget_to_dwc(g);
1616 unsigned long flags;
8698e2ac 1617 int irq;
72246da4
FB		 1618
1619 spin_lock_irqsave(&dwc->lock, flags);
1620
8698e2ac 1621 dwc3_gadget_disable_irq(dwc);
72246da4
FB		 1622 __dwc3_gadget_ep_disable(dwc->eps[0]);
1623 __dwc3_gadget_ep_disable(dwc->eps[1]);
1624
1625 dwc->gadget_driver = NULL;
72246da4
FB		 1626
1627 spin_unlock_irqrestore(&dwc->lock, flags);
1628
734b2fe9
FB		 1629 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1630 free_irq(irq, dwc);
1631
72246da4
FB		 1632 return 0;
1633}
802fde98 1634
72246da4
FB		 1635static const struct usb_gadget_ops dwc3_gadget_ops = {
1636 .get_frame = dwc3_gadget_get_frame,
1637 .wakeup = dwc3_gadget_wakeup,
1638 .set_selfpowered = dwc3_gadget_set_selfpowered,
1639 .pullup = dwc3_gadget_pullup,
1640 .udc_start = dwc3_gadget_start,
1641 .udc_stop = dwc3_gadget_stop,
1642};
1643
1644/* -------------------------------------------------------------------------- */
1645
6a1e3ef4
FB		 1646static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,
1647 u8 num, u32 direction)
72246da4
FB		 1648{
1649 struct dwc3_ep *dep;
6a1e3ef4 1650 u8 i;
72246da4 1651
6a1e3ef4
FB		 1652 for (i = 0; i < num; i++) {
1653 u8 epnum = (i << 1) | (!!direction);
72246da4 1654
72246da4
FB		 1655 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1656 if (!dep) {
1657 dev_err(dwc->dev, "can't allocate endpoint %d\n",
1658 epnum);
1659 return -ENOMEM;
1660 }
1661
1662 dep->dwc = dwc;
1663 dep->number = epnum;
1664 dwc->eps[epnum] = dep;
1665
1666 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1667 (epnum & 1) ? "in" : "out");
6a1e3ef4 1668
72246da4
FB		 1669 dep->endpoint.name = dep->name;
1670 dep->direction = (epnum & 1);
1671
1672 if (epnum == 0 || epnum == 1) {
1673 dep->endpoint.maxpacket = 512;
6048e4c6 1674 dep->endpoint.maxburst = 1;
72246da4
FB		 1675 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1676 if (!epnum)
1677 dwc->gadget.ep0 = &dep->endpoint;
1678 } else {
1679 int ret;
1680
1681 dep->endpoint.maxpacket = 1024;
12d36c16 1682 dep->endpoint.max_streams = 15;
72246da4
FB		 1683 dep->endpoint.ops = &dwc3_gadget_ep_ops;
1684 list_add_tail(&dep->endpoint.ep_list,
1685 &dwc->gadget.ep_list);
1686
1687 ret = dwc3_alloc_trb_pool(dep);
25b8ff68 1688 if (ret)
72246da4 1689 return ret;
72246da4 1690 }
25b8ff68 1691
72246da4
FB		 1692 INIT_LIST_HEAD(&dep->request_list);
1693 INIT_LIST_HEAD(&dep->req_queued);
1694 }
1695
1696 return 0;
1697}
1698
6a1e3ef4
FB		 1699static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1700{
1701 int ret;
1702
1703 INIT_LIST_HEAD(&dwc->gadget.ep_list);
1704
1705 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0);
1706 if (ret < 0) {
1707 dev_vdbg(dwc->dev, "failed to allocate OUT endpoints\n");
1708 return ret;
1709 }
1710
1711 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1);
1712 if (ret < 0) {
1713 dev_vdbg(dwc->dev, "failed to allocate IN endpoints\n");
1714 return ret;
1715 }
1716
1717 return 0;
1718}
1719
72246da4
FB		 1720static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1721{
1722 struct dwc3_ep *dep;
1723 u8 epnum;
1724
1725 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1726 dep = dwc->eps[epnum];
6a1e3ef4
FB		 1727 if (!dep)
1728 continue;
5bf8fae3
GC		 1729 /*
1730 * Physical endpoints 0 and 1 are special; they form the
1731 * bi-directional USB endpoint 0.
1732 *
1733 * For those two physical endpoints, we don't allocate a TRB
1734 * pool nor do we add them the endpoints list. Due to that, we
1735 * shouldn't do these two operations otherwise we would end up
1736 * with all sorts of bugs when removing dwc3.ko.
1737 */
1738 if (epnum != 0 && epnum != 1) {
1739 dwc3_free_trb_pool(dep);
72246da4 1740 list_del(&dep->endpoint.ep_list);
5bf8fae3 1741 }
72246da4
FB		 1742
1743 kfree(dep);
1744 }
1745}
1746
72246da4 1747/* -------------------------------------------------------------------------- */
e5caff68 1748
e5ba5ec8
PA		 1749static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
1750 struct dwc3_request *req, struct dwc3_trb *trb,
72246da4
FB		 1751 const struct dwc3_event_depevt *event, int status)
1752{
72246da4
FB		 1753 unsigned int count;
1754 unsigned int s_pkt = 0;
d6d6ec7b 1755 unsigned int trb_status;
72246da4 1756
e5ba5ec8
PA		 1757 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1758 /*
1759 * We continue despite the error. There is not much we
1760 * can do. If we don't clean it up we loop forever. If
1761 * we skip the TRB then it gets overwritten after a
1762 * while since we use them in a ring buffer. A BUG()
1763 * would help. Lets hope that if this occurs, someone
1764 * fixes the root cause instead of looking away :)
1765 */
1766 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1767 dep->name, trb);
1768 count = trb->size & DWC3_TRB_SIZE_MASK;
1769
1770 if (dep->direction) {
1771 if (count) {
1772 trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
1773 if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
1774 dev_dbg(dwc->dev, "incomplete IN transfer %s\n",
1775 dep->name);
1776 /*
1777 * If missed isoc occurred and there is
1778 * no request queued then issue END
1779 * TRANSFER, so that core generates
1780 * next xfernotready and we will issue
1781 * a fresh START TRANSFER.
1782 * If there are still queued request
1783 * then wait, do not issue either END
1784 * or UPDATE TRANSFER, just attach next
1785 * request in request_list during
1786 * giveback.If any future queued request
1787 * is successfully transferred then we
1788 * will issue UPDATE TRANSFER for all
1789 * request in the request_list.
1790 */
1791 dep->flags |= DWC3_EP_MISSED_ISOC;
1792 } else {
1793 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1794 dep->name);
1795 status = -ECONNRESET;
1796 }
1797 } else {
1798 dep->flags &= ~DWC3_EP_MISSED_ISOC;
1799 }
1800 } else {
1801 if (count && (event->status & DEPEVT_STATUS_SHORT))
1802 s_pkt = 1;
1803 }
1804
e5ba5ec8
PA		 1805 if (s_pkt)
1806 return 1;
1807 if ((event->status & DEPEVT_STATUS_LST) &&
1808 (trb->ctrl & (DWC3_TRB_CTRL_LST |
1809 DWC3_TRB_CTRL_HWO)))
1810 return 1;
1811 if ((event->status & DEPEVT_STATUS_IOC) &&
1812 (trb->ctrl & DWC3_TRB_CTRL_IOC))
1813 return 1;
1814 return 0;
1815}
1816
1817static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1818 const struct dwc3_event_depevt *event, int status)
1819{
1820 struct dwc3_request *req;
1821 struct dwc3_trb *trb;
1822 unsigned int slot;
1823 unsigned int i;
1cb7105d 1824 int count = 0;
e5ba5ec8
PA		 1825 int ret;
1826
72246da4
FB		 1827 do {
1828 req = next_request(&dep->req_queued);
d39ee7be
SAS		 1829 if (!req) {
1830 WARN_ON_ONCE(1);
1831 return 1;
1832 }
e5ba5ec8
PA		 1833 i = 0;
1834 do {
1835 slot = req->start_slot + i;
1836 if ((slot == DWC3_TRB_NUM - 1) &&
1837 usb_endpoint_xfer_isoc(dep->endpoint.desc))
1838 slot++;
1839 slot %= DWC3_TRB_NUM;
1840 trb = &dep->trb_pool[slot];
1cb7105d
FB		 1841 count += trb->size & DWC3_TRB_SIZE_MASK;
1842
72246da4 1843
e5ba5ec8
PA		 1844 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
1845 event, status);
1846 if (ret)
1847 break;
1848 }while (++i < req->request.num_mapped_sgs);
72246da4 1849
1cb7105d
FB		 1850 /*
1851 * We assume here we will always receive the entire data block
1852 * which we should receive. Meaning, if we program RX to
1853 * receive 4K but we receive only 2K, we assume that's all we
1854 * should receive and we simply bounce the request back to the
1855 * gadget driver for further processing.
1856 */
1857 req->request.actual += req->request.length - count;
72246da4 1858 dwc3_gadget_giveback(dep, req, status);
e5ba5ec8
PA		 1859
1860 if (ret)
72246da4
FB		 1861 break;
1862 } while (1);
1863
cdc359dd
PA		 1864 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1865 list_empty(&dep->req_queued)) {
1866 if (list_empty(&dep->request_list)) {
1867 /*
1868 * If there is no entry in request list then do
1869 * not issue END TRANSFER now. Just set PENDING
1870 * flag, so that END TRANSFER is issued when an
1871 * entry is added into request list.
1872 */
1873 dep->flags = DWC3_EP_PENDING_REQUEST;
1874 } else {
1875 dwc3_stop_active_transfer(dwc, dep->number);
1876 dep->flags = DWC3_EP_ENABLED;
1877 }
7efea86c
PA		 1878 return 1;
1879 }
1880
f6bafc6a
FB		 1881 if ((event->status & DEPEVT_STATUS_IOC) &&
1882 (trb->ctrl & DWC3_TRB_CTRL_IOC))
72246da4
FB		 1883 return 0;
1884 return 1;
1885}
1886
1887static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
1888 struct dwc3_ep *dep, const struct dwc3_event_depevt *event,
1889 int start_new)
1890{
1891 unsigned status = 0;
1892 int clean_busy;
1893
1894 if (event->status & DEPEVT_STATUS_BUSERR)
1895 status = -ECONNRESET;
1896
1d046793 1897 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
c2df85ca 1898 if (clean_busy)
72246da4 1899 dep->flags &= ~DWC3_EP_BUSY;
fae2b904
FB		 1900
1901 /*
1902 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
1903 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
1904 */
1905 if (dwc->revision < DWC3_REVISION_183A) {
1906 u32 reg;
1907 int i;
1908
1909 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
348e026f 1910 dep = dwc->eps[i];
fae2b904
FB		 1911
1912 if (!(dep->flags & DWC3_EP_ENABLED))
1913 continue;
1914
1915 if (!list_empty(&dep->req_queued))
1916 return;
1917 }
1918
1919 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1920 reg |= dwc->u1u2;
1921 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1922
1923 dwc->u1u2 = 0;
1924 }
72246da4
FB		 1925}
1926
72246da4
FB		 1927static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
1928 const struct dwc3_event_depevt *event)
1929{
1930 struct dwc3_ep *dep;
1931 u8 epnum = event->endpoint_number;
1932
1933 dep = dwc->eps[epnum];
1934
3336abb5
FB		 1935 if (!(dep->flags & DWC3_EP_ENABLED))
1936 return;
1937
72246da4
FB		 1938 dev_vdbg(dwc->dev, "%s: %s\n", dep->name,
1939 dwc3_ep_event_string(event->endpoint_event));
1940
1941 if (epnum == 0 || epnum == 1) {
1942 dwc3_ep0_interrupt(dwc, event);
1943 return;
1944 }
1945
1946 switch (event->endpoint_event) {
1947 case DWC3_DEPEVT_XFERCOMPLETE:
b4996a86 1948 dep->resource_index = 0;
c2df85ca 1949
16e78db7 1950 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
72246da4
FB		 1951 dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n",
1952 dep->name);
1953 return;
1954 }
1955
1956 dwc3_endpoint_transfer_complete(dwc, dep, event, 1);
1957 break;
1958 case DWC3_DEPEVT_XFERINPROGRESS:
16e78db7 1959 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
72246da4
FB		 1960 dev_dbg(dwc->dev, "%s is not an Isochronous endpoint\n",
1961 dep->name);
1962 return;
1963 }
1964
1965 dwc3_endpoint_transfer_complete(dwc, dep, event, 0);
1966 break;
1967 case DWC3_DEPEVT_XFERNOTREADY:
16e78db7 1968 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
72246da4
FB		 1969 dwc3_gadget_start_isoc(dwc, dep, event);
1970 } else {
1971 int ret;
1972
1973 dev_vdbg(dwc->dev, "%s: reason %s\n",
40aa41fb
FB		 1974 dep->name, event->status &
1975 DEPEVT_STATUS_TRANSFER_ACTIVE
72246da4
FB		 1976 ? "Transfer Active"
1977 : "Transfer Not Active");
1978
1979 ret = __dwc3_gadget_kick_transfer(dep, 0, 1);
1980 if (!ret || ret == -EBUSY)
1981 return;
1982
1983 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1984 dep->name);
1985 }
1986
879631aa
FB		 1987 break;
1988 case DWC3_DEPEVT_STREAMEVT:
16e78db7 1989 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
879631aa
FB		 1990 dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
1991 dep->name);
1992 return;
1993 }
1994
1995 switch (event->status) {
1996 case DEPEVT_STREAMEVT_FOUND:
1997 dev_vdbg(dwc->dev, "Stream %d found and started\n",
1998 event->parameters);
1999
2000 break;
2001 case DEPEVT_STREAMEVT_NOTFOUND:
2002 /* FALLTHROUGH */
2003 default:
2004 dev_dbg(dwc->dev, "Couldn't find suitable stream\n");
2005 }
72246da4
FB		 2006 break;
2007 case DWC3_DEPEVT_RXTXFIFOEVT:
2008 dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name);
2009 break;
72246da4 2010 case DWC3_DEPEVT_EPCMDCMPLT:
ea53b882 2011 dev_vdbg(dwc->dev, "Endpoint Command Complete\n");
72246da4
FB		 2012 break;
2013 }
2014}
2015
2016static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2017{
2018 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2019 spin_unlock(&dwc->lock);
2020 dwc->gadget_driver->disconnect(&dwc->gadget);
2021 spin_lock(&dwc->lock);
2022 }
2023}
2024
2025static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum)
2026{
2027 struct dwc3_ep *dep;
2028 struct dwc3_gadget_ep_cmd_params params;
2029 u32 cmd;
2030 int ret;
2031
2032 dep = dwc->eps[epnum];
2033
b4996a86 2034 if (!dep->resource_index)
3daf74d7
PA		 2035 return;
2036
57911504
PA		 2037 /*
2038 * NOTICE: We are violating what the Databook says about the
2039 * EndTransfer command. Ideally we would _always_ wait for the
2040 * EndTransfer Command Completion IRQ, but that's causing too
2041 * much trouble synchronizing between us and gadget driver.
2042 *
2043 * We have discussed this with the IP Provider and it was
2044 * suggested to giveback all requests here, but give HW some
2045 * extra time to synchronize with the interconnect. We're using
2046 * an arbitraty 100us delay for that.
2047 *
2048 * Note also that a similar handling was tested by Synopsys
2049 * (thanks a lot Paul) and nothing bad has come out of it.
2050 * In short, what we're doing is:
2051 *
2052 * - Issue EndTransfer WITH CMDIOC bit set
2053 * - Wait 100us
2054 */
2055
3daf74d7
PA		 2056 cmd = DWC3_DEPCMD_ENDTRANSFER;
2057 cmd |= DWC3_DEPCMD_HIPRI_FORCERM | DWC3_DEPCMD_CMDIOC;
b4996a86 2058 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
3daf74d7
PA		 2059 memset(&params, 0, sizeof(params));
2060 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
2061 WARN_ON_ONCE(ret);
b4996a86 2062 dep->resource_index = 0;
041d81f4 2063 dep->flags &= ~DWC3_EP_BUSY;
57911504 2064 udelay(100);
72246da4
FB		 2065}
2066
2067static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2068{
2069 u32 epnum;
2070
2071 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2072 struct dwc3_ep *dep;
2073
2074 dep = dwc->eps[epnum];
6a1e3ef4
FB		 2075 if (!dep)
2076 continue;
2077
72246da4
FB		 2078 if (!(dep->flags & DWC3_EP_ENABLED))
2079 continue;
2080
624407f9 2081 dwc3_remove_requests(dwc, dep);
72246da4
FB		 2082 }
2083}
2084
2085static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2086{
2087 u32 epnum;
2088
2089 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2090 struct dwc3_ep *dep;
2091 struct dwc3_gadget_ep_cmd_params params;
2092 int ret;
2093
2094 dep = dwc->eps[epnum];
6a1e3ef4
FB		 2095 if (!dep)
2096 continue;
72246da4
FB		 2097
2098 if (!(dep->flags & DWC3_EP_STALL))
2099 continue;
2100
2101 dep->flags &= ~DWC3_EP_STALL;
2102
2103 memset(&params, 0, sizeof(params));
2104 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
2105 DWC3_DEPCMD_CLEARSTALL, &params);
2106 WARN_ON_ONCE(ret);
2107 }
2108}
2109
2110static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2111{
c4430a26
FB		 2112 int reg;
2113
72246da4 2114 dev_vdbg(dwc->dev, "%s\n", __func__);
72246da4
FB		 2115
2116 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2117 reg &= ~DWC3_DCTL_INITU1ENA;
2118 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2119
2120 reg &= ~DWC3_DCTL_INITU2ENA;
2121 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
72246da4 2122
72246da4 2123 dwc3_disconnect_gadget(dwc);
b23c8439 2124 dwc->start_config_issued = false;
72246da4
FB		 2125
2126 dwc->gadget.speed = USB_SPEED_UNKNOWN;
df62df56 2127 dwc->setup_packet_pending = false;
72246da4
FB		 2128}
2129
d7a46a8d 2130static void dwc3_gadget_usb3_phy_suspend(struct dwc3 *dwc, int suspend)
72246da4
FB		 2131{
2132 u32 reg;
2133
2134 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
2135
d7a46a8d 2136 if (suspend)
72246da4 2137 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
d7a46a8d
PZ		 2138 else
2139 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
72246da4
FB		 2140
2141 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
2142}
2143
d7a46a8d 2144static void dwc3_gadget_usb2_phy_suspend(struct dwc3 *dwc, int suspend)
72246da4
FB		 2145{
2146 u32 reg;
2147
2148 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
2149
d7a46a8d 2150 if (suspend)
72246da4 2151 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
d7a46a8d
PZ		 2152 else
2153 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
72246da4
FB		 2154
2155 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
2156}
2157
2158static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2159{
2160 u32 reg;
2161
2162 dev_vdbg(dwc->dev, "%s\n", __func__);
2163
df62df56
FB		 2164 /*
2165 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2166 * would cause a missing Disconnect Event if there's a
2167 * pending Setup Packet in the FIFO.
2168 *
2169 * There's no suggested workaround on the official Bug
2170 * report, which states that "unless the driver/application
2171 * is doing any special handling of a disconnect event,
2172 * there is no functional issue".
2173 *
2174 * Unfortunately, it turns out that we _do_ some special
2175 * handling of a disconnect event, namely complete all
2176 * pending transfers, notify gadget driver of the
2177 * disconnection, and so on.
2178 *
2179 * Our suggested workaround is to follow the Disconnect
2180 * Event steps here, instead, based on a setup_packet_pending
2181 * flag. Such flag gets set whenever we have a XferNotReady
2182 * event on EP0 and gets cleared on XferComplete for the
2183 * same endpoint.
2184 *
2185 * Refers to:
2186 *
2187 * STAR#9000466709: RTL: Device : Disconnect event not
2188 * generated if setup packet pending in FIFO
2189 */
2190 if (dwc->revision < DWC3_REVISION_188A) {
2191 if (dwc->setup_packet_pending)
2192 dwc3_gadget_disconnect_interrupt(dwc);
2193 }
2194
961906ed 2195 /* after reset -> Default State */
14cd592f 2196 usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT);
961906ed 2197
802fde98
PZ		 2198 /* Recent versions support automatic phy suspend and don't need this */
2199 if (dwc->revision < DWC3_REVISION_194A) {
2200 /* Resume PHYs */
2201 dwc3_gadget_usb2_phy_suspend(dwc, false);
2202 dwc3_gadget_usb3_phy_suspend(dwc, false);
2203 }
72246da4
FB		 2204
2205 if (dwc->gadget.speed != USB_SPEED_UNKNOWN)
2206 dwc3_disconnect_gadget(dwc);
2207
2208 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2209 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2210 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
3b637367 2211 dwc->test_mode = false;
72246da4
FB		 2212
2213 dwc3_stop_active_transfers(dwc);
2214 dwc3_clear_stall_all_ep(dwc);
b23c8439 2215 dwc->start_config_issued = false;
72246da4
FB		 2216
2217 /* Reset device address to zero */
2218 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2219 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2220 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
72246da4
FB		 2221}
2222
2223static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
2224{
2225 u32 reg;
2226 u32 usb30_clock = DWC3_GCTL_CLK_BUS;
2227
2228 /*
2229 * We change the clock only at SS but I dunno why I would want to do
2230 * this. Maybe it becomes part of the power saving plan.
2231 */
2232
2233 if (speed != DWC3_DSTS_SUPERSPEED)
2234 return;
2235
2236 /*
2237 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2238 * each time on Connect Done.
2239 */
2240 if (!usb30_clock)
2241 return;
2242
2243 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2244 reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2245 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2246}
2247
d7a46a8d 2248static void dwc3_gadget_phy_suspend(struct dwc3 *dwc, u8 speed)
72246da4
FB		 2249{
2250 switch (speed) {
2251 case USB_SPEED_SUPER:
d7a46a8d 2252 dwc3_gadget_usb2_phy_suspend(dwc, true);
72246da4
FB		 2253 break;
2254 case USB_SPEED_HIGH:
2255 case USB_SPEED_FULL:
2256 case USB_SPEED_LOW:
d7a46a8d 2257 dwc3_gadget_usb3_phy_suspend(dwc, true);
72246da4
FB		 2258 break;
2259 }
2260}
2261
2262static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2263{
72246da4
FB		 2264 struct dwc3_ep *dep;
2265 int ret;
2266 u32 reg;
2267 u8 speed;
2268
2269 dev_vdbg(dwc->dev, "%s\n", __func__);
2270
72246da4
FB		 2271 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2272 speed = reg & DWC3_DSTS_CONNECTSPD;
2273 dwc->speed = speed;
2274
2275 dwc3_update_ram_clk_sel(dwc, speed);
2276
2277 switch (speed) {
2278 case DWC3_DCFG_SUPERSPEED:
05870c5b
FB		 2279 /*
2280 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2281 * would cause a missing USB3 Reset event.
2282 *
2283 * In such situations, we should force a USB3 Reset
2284 * event by calling our dwc3_gadget_reset_interrupt()
2285 * routine.
2286 *
2287 * Refers to:
2288 *
2289 * STAR#9000483510: RTL: SS : USB3 reset event may
2290 * not be generated always when the link enters poll
2291 */
2292 if (dwc->revision < DWC3_REVISION_190A)
2293 dwc3_gadget_reset_interrupt(dwc);
2294
72246da4
FB		 2295 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2296 dwc->gadget.ep0->maxpacket = 512;
2297 dwc->gadget.speed = USB_SPEED_SUPER;
2298 break;
2299 case DWC3_DCFG_HIGHSPEED:
2300 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2301 dwc->gadget.ep0->maxpacket = 64;
2302 dwc->gadget.speed = USB_SPEED_HIGH;
2303 break;
2304 case DWC3_DCFG_FULLSPEED2:
2305 case DWC3_DCFG_FULLSPEED1:
2306 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2307 dwc->gadget.ep0->maxpacket = 64;
2308 dwc->gadget.speed = USB_SPEED_FULL;
2309 break;
2310 case DWC3_DCFG_LOWSPEED:
2311 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2312 dwc->gadget.ep0->maxpacket = 8;
2313 dwc->gadget.speed = USB_SPEED_LOW;
2314 break;
2315 }
2316
2b758350
PA		 2317 /* Enable USB2 LPM Capability */
2318
2319 if ((dwc->revision > DWC3_REVISION_194A)
2320 && (speed != DWC3_DCFG_SUPERSPEED)) {
2321 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2322 reg |= DWC3_DCFG_LPM_CAP;
2323 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2324
2325 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2326 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2327
1a947746
FB		 2328 /*
2329 * TODO: This should be configurable. For now using
2330 * maximum allowed HIRD threshold value of 0b1100
2331 */
2332 reg |= DWC3_DCTL_HIRD_THRES(12);
2b758350
PA		 2333
2334 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2335 }
2336
802fde98
PZ		 2337 /* Recent versions support automatic phy suspend and don't need this */
2338 if (dwc->revision < DWC3_REVISION_194A) {
2339 /* Suspend unneeded PHY */
2340 dwc3_gadget_phy_suspend(dwc, dwc->gadget.speed);
2341 }
72246da4
FB		 2342
2343 dep = dwc->eps[0];
4b345c9a 2344 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true);
72246da4
FB		 2345 if (ret) {
2346 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2347 return;
2348 }
2349
2350 dep = dwc->eps[1];
4b345c9a 2351 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true);
72246da4
FB		 2352 if (ret) {
2353 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2354 return;
2355 }
2356
2357 /*
2358 * Configure PHY via GUSB3PIPECTLn if required.
2359 *
2360 * Update GTXFIFOSIZn
2361 *
2362 * In both cases reset values should be sufficient.
2363 */
2364}
2365
2366static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2367{
2368 dev_vdbg(dwc->dev, "%s\n", __func__);
2369
2370 /*
2371 * TODO take core out of low power mode when that's
2372 * implemented.
2373 */
2374
2375 dwc->gadget_driver->resume(&dwc->gadget);
2376}
2377
2378static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2379 unsigned int evtinfo)
2380{
fae2b904 2381 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
0b0cc1cd
FB		 2382 unsigned int pwropt;
2383
2384 /*
2385 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2386 * Hibernation mode enabled which would show up when device detects
2387 * host-initiated U3 exit.
2388 *
2389 * In that case, device will generate a Link State Change Interrupt
2390 * from U3 to RESUME which is only necessary if Hibernation is
2391 * configured in.
2392 *
2393 * There are no functional changes due to such spurious event and we
2394 * just need to ignore it.
2395 *
2396 * Refers to:
2397 *
2398 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2399 * operational mode
2400 */
2401 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2402 if ((dwc->revision < DWC3_REVISION_250A) &&
2403 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2404 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2405 (next == DWC3_LINK_STATE_RESUME)) {
2406 dev_vdbg(dwc->dev, "ignoring transition U3 -> Resume\n");
2407 return;
2408 }
2409 }
fae2b904
FB		 2410
2411 /*
2412 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2413 * on the link partner, the USB session might do multiple entry/exit
2414 * of low power states before a transfer takes place.
2415 *
2416 * Due to this problem, we might experience lower throughput. The
2417 * suggested workaround is to disable DCTL[12:9] bits if we're
2418 * transitioning from U1/U2 to U0 and enable those bits again
2419 * after a transfer completes and there are no pending transfers
2420 * on any of the enabled endpoints.
2421 *
2422 * This is the first half of that workaround.
2423 *
2424 * Refers to:
2425 *
2426 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2427 * core send LGO_Ux entering U0
2428 */
2429 if (dwc->revision < DWC3_REVISION_183A) {
2430 if (next == DWC3_LINK_STATE_U0) {
2431 u32 u1u2;
2432 u32 reg;
2433
2434 switch (dwc->link_state) {
2435 case DWC3_LINK_STATE_U1:
2436 case DWC3_LINK_STATE_U2:
2437 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2438 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2439 | DWC3_DCTL_ACCEPTU2ENA
2440 | DWC3_DCTL_INITU1ENA
2441 | DWC3_DCTL_ACCEPTU1ENA);
2442
2443 if (!dwc->u1u2)
2444 dwc->u1u2 = reg & u1u2;
2445
2446 reg &= ~u1u2;
2447
2448 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2449 break;
2450 default:
2451 /* do nothing */
2452 break;
2453 }
2454 }
2455 }
2456
2457 dwc->link_state = next;
019ac832
FB		 2458
2459 dev_vdbg(dwc->dev, "%s link %d\n", __func__, dwc->link_state);
72246da4
FB		 2460}
2461
2462static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2463 const struct dwc3_event_devt *event)
2464{
2465 switch (event->type) {
2466 case DWC3_DEVICE_EVENT_DISCONNECT:
2467 dwc3_gadget_disconnect_interrupt(dwc);
2468 break;
2469 case DWC3_DEVICE_EVENT_RESET:
2470 dwc3_gadget_reset_interrupt(dwc);
2471 break;
2472 case DWC3_DEVICE_EVENT_CONNECT_DONE:
2473 dwc3_gadget_conndone_interrupt(dwc);
2474 break;
2475 case DWC3_DEVICE_EVENT_WAKEUP:
2476 dwc3_gadget_wakeup_interrupt(dwc);
2477 break;
2478 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2479 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2480 break;
2481 case DWC3_DEVICE_EVENT_EOPF:
2482 dev_vdbg(dwc->dev, "End of Periodic Frame\n");
2483 break;
2484 case DWC3_DEVICE_EVENT_SOF:
2485 dev_vdbg(dwc->dev, "Start of Periodic Frame\n");
2486 break;
2487 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2488 dev_vdbg(dwc->dev, "Erratic Error\n");
2489 break;
2490 case DWC3_DEVICE_EVENT_CMD_CMPL:
2491 dev_vdbg(dwc->dev, "Command Complete\n");
2492 break;
2493 case DWC3_DEVICE_EVENT_OVERFLOW:
2494 dev_vdbg(dwc->dev, "Overflow\n");
2495 break;
2496 default:
2497 dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2498 }
2499}
2500
2501static void dwc3_process_event_entry(struct dwc3 *dwc,
2502 const union dwc3_event *event)
2503{
2504 /* Endpoint IRQ, handle it and return early */
2505 if (event->type.is_devspec == 0) {
2506 /* depevt */
2507 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2508 }
2509
2510 switch (event->type.type) {
2511 case DWC3_EVENT_TYPE_DEV:
2512 dwc3_gadget_interrupt(dwc, &event->devt);
2513 break;
2514 /* REVISIT what to do with Carkit and I2C events ? */
2515 default:
2516 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2517 }
2518}
2519
b15a762f
FB		 2520static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc)
2521{
2522 struct dwc3 *dwc = _dwc;
2523 unsigned long flags;
2524 irqreturn_t ret = IRQ_NONE;
2525 int i;
2526
2527 spin_lock_irqsave(&dwc->lock, flags);
2528
2529 for (i = 0; i < dwc->num_event_buffers; i++) {
2530 struct dwc3_event_buffer *evt;
2531 int left;
2532
2533 evt = dwc->ev_buffs[i];
2534 left = evt->count;
2535
2536 if (!(evt->flags & DWC3_EVENT_PENDING))
2537 continue;
2538
2539 while (left > 0) {
2540 union dwc3_event event;
2541
2542 event.raw = *(u32 *) (evt->buf + evt->lpos);
2543
2544 dwc3_process_event_entry(dwc, &event);
2545
2546 /*
2547 * FIXME we wrap around correctly to the next entry as
2548 * almost all entries are 4 bytes in size. There is one
2549 * entry which has 12 bytes which is a regular entry
2550 * followed by 8 bytes data. ATM I don't know how
2551 * things are organized if we get next to the a
2552 * boundary so I worry about that once we try to handle
2553 * that.
2554 */
2555 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2556 left -= 4;
2557
2558 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(i), 4);
2559 }
2560
2561 evt->count = 0;
2562 evt->flags &= ~DWC3_EVENT_PENDING;
2563 ret = IRQ_HANDLED;
2564 }
2565
2566 spin_unlock_irqrestore(&dwc->lock, flags);
2567
2568 return ret;
2569}
2570
72246da4
FB		 2571static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
2572{
2573 struct dwc3_event_buffer *evt;
72246da4
FB		 2574 u32 count;
2575
b15a762f
FB		 2576 evt = dwc->ev_buffs[buf];
2577
72246da4
FB		 2578 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf));
2579 count &= DWC3_GEVNTCOUNT_MASK;
2580 if (!count)
2581 return IRQ_NONE;
2582
b15a762f
FB		 2583 evt->count = count;
2584 evt->flags |= DWC3_EVENT_PENDING;
72246da4 2585
b15a762f 2586 return IRQ_WAKE_THREAD;
72246da4
FB		 2587}
2588
2589static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
2590{
2591 struct dwc3 *dwc = _dwc;
2592 int i;
2593 irqreturn_t ret = IRQ_NONE;
2594
2595 spin_lock(&dwc->lock);
2596
9f622b2a 2597 for (i = 0; i < dwc->num_event_buffers; i++) {
72246da4
FB		 2598 irqreturn_t status;
2599
2600 status = dwc3_process_event_buf(dwc, i);
b15a762f 2601 if (status == IRQ_WAKE_THREAD)
72246da4
FB		 2602 ret = status;
2603 }
2604
2605 spin_unlock(&dwc->lock);
2606
2607 return ret;
2608}
2609
2610/**
2611 * dwc3_gadget_init - Initializes gadget related registers
1d046793 2612 * @dwc: pointer to our controller context structure
72246da4
FB		 2613 *
2614 * Returns 0 on success otherwise negative errno.
2615 */
41ac7b3a 2616int dwc3_gadget_init(struct dwc3 *dwc)
72246da4
FB		 2617{
2618 u32 reg;
2619 int ret;
72246da4
FB		 2620
2621 dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2622 &dwc->ctrl_req_addr, GFP_KERNEL);
2623 if (!dwc->ctrl_req) {
2624 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2625 ret = -ENOMEM;
2626 goto err0;
2627 }
2628
2629 dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2630 &dwc->ep0_trb_addr, GFP_KERNEL);
2631 if (!dwc->ep0_trb) {
2632 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2633 ret = -ENOMEM;
2634 goto err1;
2635 }
2636
3ef35faf 2637 dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
72246da4
FB		 2638 if (!dwc->setup_buf) {
2639 dev_err(dwc->dev, "failed to allocate setup buffer\n");
2640 ret = -ENOMEM;
2641 goto err2;
2642 }
2643
5812b1c2 2644 dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
3ef35faf
FB		 2645 DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr,
2646 GFP_KERNEL);
5812b1c2
FB		 2647 if (!dwc->ep0_bounce) {
2648 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2649 ret = -ENOMEM;
2650 goto err3;
2651 }
2652
72246da4 2653 dwc->gadget.ops = &dwc3_gadget_ops;
d327ab5b 2654 dwc->gadget.max_speed = USB_SPEED_SUPER;
72246da4 2655 dwc->gadget.speed = USB_SPEED_UNKNOWN;
eeb720fb 2656 dwc->gadget.sg_supported = true;
72246da4
FB		 2657 dwc->gadget.name = "dwc3-gadget";
2658
2659 /*
2660 * REVISIT: Here we should clear all pending IRQs to be
2661 * sure we're starting from a well known location.
2662 */
2663
2664 ret = dwc3_gadget_init_endpoints(dwc);
2665 if (ret)
5812b1c2 2666 goto err4;
72246da4 2667
e6a3b5e2
SAS		 2668 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2669 reg |= DWC3_DCFG_LPM_CAP;
2670 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2671
8698e2ac 2672 /* Enable USB2 LPM and automatic phy suspend only on recent versions */
802fde98 2673 if (dwc->revision >= DWC3_REVISION_194A) {
dcae3573
PA		 2674 dwc3_gadget_usb2_phy_suspend(dwc, false);
2675 dwc3_gadget_usb3_phy_suspend(dwc, false);
802fde98
PZ		 2676 }
2677
72246da4
FB		 2678 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2679 if (ret) {
2680 dev_err(dwc->dev, "failed to register udc\n");
8698e2ac 2681 goto err5;
72246da4
FB		 2682 }
2683
2684 return 0;
2685
5812b1c2 2686err5:
72246da4
FB		 2687 dwc3_gadget_free_endpoints(dwc);
2688
5812b1c2 2689err4:
3ef35faf
FB		 2690 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2691 dwc->ep0_bounce, dwc->ep0_bounce_addr);
5812b1c2 2692
72246da4 2693err3:
0fc9a1be 2694 kfree(dwc->setup_buf);
72246da4
FB		 2695
2696err2:
2697 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2698 dwc->ep0_trb, dwc->ep0_trb_addr);
2699
2700err1:
2701 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2702 dwc->ctrl_req, dwc->ctrl_req_addr);
2703
2704err0:
2705 return ret;
2706}
2707
7415f17c
FB		 2708/* -------------------------------------------------------------------------- */
2709
72246da4
FB		 2710void dwc3_gadget_exit(struct dwc3 *dwc)
2711{
72246da4 2712 usb_del_gadget_udc(&dwc->gadget);
72246da4 2713
72246da4
FB		 2714 dwc3_gadget_free_endpoints(dwc);
2715
3ef35faf
FB		 2716 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2717 dwc->ep0_bounce, dwc->ep0_bounce_addr);
5812b1c2 2718
0fc9a1be 2719 kfree(dwc->setup_buf);
72246da4
FB		 2720
2721 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2722 dwc->ep0_trb, dwc->ep0_trb_addr);
2723
2724 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2725 dwc->ctrl_req, dwc->ctrl_req_addr);
72246da4 2726}
7415f17c
FB		 2727
2728int dwc3_gadget_prepare(struct dwc3 *dwc)
2729{
2730 if (dwc->pullups_connected)
2731 dwc3_gadget_disable_irq(dwc);
2732
2733 return 0;
2734}
2735
2736void dwc3_gadget_complete(struct dwc3 *dwc)
2737{
2738 if (dwc->pullups_connected) {
2739 dwc3_gadget_enable_irq(dwc);
2740 dwc3_gadget_run_stop(dwc, true);
2741 }
2742}
2743
2744int dwc3_gadget_suspend(struct dwc3 *dwc)
2745{
2746 __dwc3_gadget_ep_disable(dwc->eps[0]);
2747 __dwc3_gadget_ep_disable(dwc->eps[1]);
2748
2749 dwc->dcfg = dwc3_readl(dwc->regs, DWC3_DCFG);
2750
2751 return 0;
2752}
2753
2754int dwc3_gadget_resume(struct dwc3 *dwc)
2755{
2756 struct dwc3_ep *dep;
2757 int ret;
2758
2759 /* Start with SuperSpeed Default */
2760 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2761
2762 dep = dwc->eps[0];
2763 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false);
2764 if (ret)
2765 goto err0;
2766
2767 dep = dwc->eps[1];
2768 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false);
2769 if (ret)
2770 goto err1;
2771
2772 /* begin to receive SETUP packets */
2773 dwc->ep0state = EP0_SETUP_PHASE;
2774 dwc3_ep0_out_start(dwc);
2775
2776 dwc3_writel(dwc->regs, DWC3_DCFG, dwc->dcfg);
2777
2778 return 0;
2779
2780err1:
2781 __dwc3_gadget_ep_disable(dwc->eps[0]);
2782
2783err0:
2784 return ret;
2785}
kernel source for telekom puls (alcatel/mediatek)