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usb: dwc3: gadget: allow testmodes changes via debugfs
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / usb / dwc3 / gadget.c
CommitLineData
72246da4
FB		 1/**
2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
72246da4
FB		 5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer,
14 * without modification.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. The names of the above-listed copyright holders may not be used
19 * to endorse or promote products derived from this software without
20 * specific prior written permission.
21 *
22 * ALTERNATIVELY, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2, as published by the Free
24 * Software Foundation.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 */
38
39#include <linux/kernel.h>
40#include <linux/delay.h>
41#include <linux/slab.h>
42#include <linux/spinlock.h>
43#include <linux/platform_device.h>
44#include <linux/pm_runtime.h>
45#include <linux/interrupt.h>
46#include <linux/io.h>
47#include <linux/list.h>
48#include <linux/dma-mapping.h>
49
50#include <linux/usb/ch9.h>
51#include <linux/usb/gadget.h>
52
53#include "core.h"
54#include "gadget.h"
55#include "io.h"
56
57#define DMA_ADDR_INVALID (~(dma_addr_t)0)
58
04a9bfcd
FB		 59/**
60 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
61 * @dwc: pointer to our context structure
62 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
63 *
64 * Caller should take care of locking. This function will
65 * return 0 on success or -EINVAL if wrong Test Selector
66 * is passed
67 */
68int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
69{
70 u32 reg;
71
72 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
73 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
74
75 switch (mode) {
76 case TEST_J:
77 case TEST_K:
78 case TEST_SE0_NAK:
79 case TEST_PACKET:
80 case TEST_FORCE_EN:
81 reg |= mode << 1;
82 break;
83 default:
84 return -EINVAL;
85 }
86
87 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
88
89 return 0;
90}
91
72246da4
FB		 92void dwc3_map_buffer_to_dma(struct dwc3_request *req)
93{
94 struct dwc3 *dwc = req->dep->dwc;
95
78c58a53
SAS		 96 if (req->request.length == 0) {
97 /* req->request.dma = dwc->setup_buf_addr; */
98 return;
99 }
100
eeb720fb
FB		 101 if (req->request.num_sgs) {
102 int mapped;
103
104 mapped = dma_map_sg(dwc->dev, req->request.sg,
105 req->request.num_sgs,
106 req->direction ? DMA_TO_DEVICE
107 : DMA_FROM_DEVICE);
108 if (mapped < 0) {
109 dev_err(dwc->dev, "failed to map SGs\n");
110 return;
111 }
112
113 req->request.num_mapped_sgs = mapped;
114 return;
115 }
116
72246da4
FB		 117 if (req->request.dma == DMA_ADDR_INVALID) {
118 req->request.dma = dma_map_single(dwc->dev, req->request.buf,
119 req->request.length, req->direction
120 ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
121 req->mapped = true;
72246da4
FB		 122 }
123}
124
125void dwc3_unmap_buffer_from_dma(struct dwc3_request *req)
126{
127 struct dwc3 *dwc = req->dep->dwc;
128
78c58a53
SAS		 129 if (req->request.length == 0) {
130 req->request.dma = DMA_ADDR_INVALID;
131 return;
132 }
133
eeb720fb
FB		 134 if (req->request.num_mapped_sgs) {
135 req->request.dma = DMA_ADDR_INVALID;
136 dma_unmap_sg(dwc->dev, req->request.sg,
c09d6b51 137 req->request.num_mapped_sgs,
eeb720fb
FB		 138 req->direction ? DMA_TO_DEVICE
139 : DMA_FROM_DEVICE);
140
141 req->request.num_mapped_sgs = 0;
142 return;
143 }
144
72246da4
FB		 145 if (req->mapped) {
146 dma_unmap_single(dwc->dev, req->request.dma,
147 req->request.length, req->direction
148 ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
149 req->mapped = 0;
f198ead2 150 req->request.dma = DMA_ADDR_INVALID;
72246da4
FB		 151 }
152}
153
154void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
155 int status)
156{
157 struct dwc3 *dwc = dep->dwc;
158
159 if (req->queued) {
eeb720fb
FB		 160 if (req->request.num_mapped_sgs)
161 dep->busy_slot += req->request.num_mapped_sgs;
162 else
163 dep->busy_slot++;
164
72246da4
FB		 165 /*
166 * Skip LINK TRB. We can't use req->trb and check for
167 * DWC3_TRBCTL_LINK_TRB because it points the TRB we just
168 * completed (not the LINK TRB).
169 */
170 if (((dep->busy_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
171 usb_endpoint_xfer_isoc(dep->desc))
172 dep->busy_slot++;
173 }
174 list_del(&req->list);
eeb720fb 175 req->trb = NULL;
72246da4
FB		 176
177 if (req->request.status == -EINPROGRESS)
178 req->request.status = status;
179
180 dwc3_unmap_buffer_from_dma(req);
181
182 dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n",
183 req, dep->name, req->request.actual,
184 req->request.length, status);
185
186 spin_unlock(&dwc->lock);
187 req->request.complete(&req->dep->endpoint, &req->request);
188 spin_lock(&dwc->lock);
189}
190
191static const char *dwc3_gadget_ep_cmd_string(u8 cmd)
192{
193 switch (cmd) {
194 case DWC3_DEPCMD_DEPSTARTCFG:
195 return "Start New Configuration";
196 case DWC3_DEPCMD_ENDTRANSFER:
197 return "End Transfer";
198 case DWC3_DEPCMD_UPDATETRANSFER:
199 return "Update Transfer";
200 case DWC3_DEPCMD_STARTTRANSFER:
201 return "Start Transfer";
202 case DWC3_DEPCMD_CLEARSTALL:
203 return "Clear Stall";
204 case DWC3_DEPCMD_SETSTALL:
205 return "Set Stall";
206 case DWC3_DEPCMD_GETSEQNUMBER:
207 return "Get Data Sequence Number";
208 case DWC3_DEPCMD_SETTRANSFRESOURCE:
209 return "Set Endpoint Transfer Resource";
210 case DWC3_DEPCMD_SETEPCONFIG:
211 return "Set Endpoint Configuration";
212 default:
213 return "UNKNOWN command";
214 }
215}
216
217int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
218 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
219{
220 struct dwc3_ep *dep = dwc->eps[ep];
61d58242 221 u32 timeout = 500;
72246da4
FB		 222 u32 reg;
223
224 dev_vdbg(dwc->dev, "%s: cmd '%s' params %08x %08x %08x\n",
225 dep->name,
dc1c70a7
FB		 226 dwc3_gadget_ep_cmd_string(cmd), params->param0,
227 params->param1, params->param2);
72246da4 228
dc1c70a7
FB		 229 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
230 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
231 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
72246da4
FB		 232
233 dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
234 do {
235 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
236 if (!(reg & DWC3_DEPCMD_CMDACT)) {
164f6e14
FB		 237 dev_vdbg(dwc->dev, "Command Complete --> %d\n",
238 DWC3_DEPCMD_STATUS(reg));
72246da4
FB		 239 return 0;
240 }
241
242 /*
72246da4
FB		 243 * We can't sleep here, because it is also called from
244 * interrupt context.
245 */
246 timeout--;
247 if (!timeout)
248 return -ETIMEDOUT;
249
61d58242 250 udelay(1);
72246da4
FB		 251 } while (1);
252}
253
254static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
255 struct dwc3_trb_hw *trb)
256{
c439ef87 257 u32 offset = (char *) trb - (char *) dep->trb_pool;
72246da4
FB		 258
259 return dep->trb_pool_dma + offset;
260}
261
262static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
263{
264 struct dwc3 *dwc = dep->dwc;
265
266 if (dep->trb_pool)
267 return 0;
268
269 if (dep->number == 0 || dep->number == 1)
270 return 0;
271
272 dep->trb_pool = dma_alloc_coherent(dwc->dev,
273 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
274 &dep->trb_pool_dma, GFP_KERNEL);
275 if (!dep->trb_pool) {
276 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
277 dep->name);
278 return -ENOMEM;
279 }
280
281 return 0;
282}
283
284static void dwc3_free_trb_pool(struct dwc3_ep *dep)
285{
286 struct dwc3 *dwc = dep->dwc;
287
288 dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
289 dep->trb_pool, dep->trb_pool_dma);
290
291 dep->trb_pool = NULL;
292 dep->trb_pool_dma = 0;
293}
294
295static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
296{
297 struct dwc3_gadget_ep_cmd_params params;
298 u32 cmd;
299
300 memset(&params, 0x00, sizeof(params));
301
302 if (dep->number != 1) {
303 cmd = DWC3_DEPCMD_DEPSTARTCFG;
304 /* XferRscIdx == 0 for ep0 and 2 for the remaining */
b23c8439
PZ		 305 if (dep->number > 1) {
306 if (dwc->start_config_issued)
307 return 0;
308 dwc->start_config_issued = true;
72246da4 309 cmd |= DWC3_DEPCMD_PARAM(2);
b23c8439 310 }
72246da4
FB		 311
312 return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, &params);
313 }
314
315 return 0;
316}
317
318static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
c90bfaec
FB		 319 const struct usb_endpoint_descriptor *desc,
320 const struct usb_ss_ep_comp_descriptor *comp_desc)
72246da4
FB		 321{
322 struct dwc3_gadget_ep_cmd_params params;
323
324 memset(&params, 0x00, sizeof(params));
325
dc1c70a7
FB		 326 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
327 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc))
328 | DWC3_DEPCFG_BURST_SIZE(dep->endpoint.maxburst);
72246da4 329
dc1c70a7
FB		 330 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
331 | DWC3_DEPCFG_XFER_NOT_READY_EN;
72246da4 332
18b7ede5 333 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
dc1c70a7
FB		 334 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
335 | DWC3_DEPCFG_STREAM_EVENT_EN;
879631aa
FB		 336 dep->stream_capable = true;
337 }
338
72246da4 339 if (usb_endpoint_xfer_isoc(desc))
dc1c70a7 340 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
72246da4
FB		 341
342 /*
343 * We are doing 1:1 mapping for endpoints, meaning
344 * Physical Endpoints 2 maps to Logical Endpoint 2 and
345 * so on. We consider the direction bit as part of the physical
346 * endpoint number. So USB endpoint 0x81 is 0x03.
347 */
dc1c70a7 348 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
72246da4
FB		 349
350 /*
351 * We must use the lower 16 TX FIFOs even though
352 * HW might have more
353 */
354 if (dep->direction)
dc1c70a7 355 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
72246da4
FB		 356
357 if (desc->bInterval) {
dc1c70a7 358 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
72246da4
FB		 359 dep->interval = 1 << (desc->bInterval - 1);
360 }
361
362 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
363 DWC3_DEPCMD_SETEPCONFIG, &params);
364}
365
366static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
367{
368 struct dwc3_gadget_ep_cmd_params params;
369
370 memset(&params, 0x00, sizeof(params));
371
dc1c70a7 372 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
72246da4
FB		 373
374 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
375 DWC3_DEPCMD_SETTRANSFRESOURCE, &params);
376}
377
378/**
379 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
380 * @dep: endpoint to be initialized
381 * @desc: USB Endpoint Descriptor
382 *
383 * Caller should take care of locking
384 */
385static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
c90bfaec
FB		 386 const struct usb_endpoint_descriptor *desc,
387 const struct usb_ss_ep_comp_descriptor *comp_desc)
72246da4
FB		 388{
389 struct dwc3 *dwc = dep->dwc;
390 u32 reg;
391 int ret = -ENOMEM;
392
393 if (!(dep->flags & DWC3_EP_ENABLED)) {
394 ret = dwc3_gadget_start_config(dwc, dep);
395 if (ret)
396 return ret;
397 }
398
c90bfaec 399 ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc);
72246da4
FB		 400 if (ret)
401 return ret;
402
403 if (!(dep->flags & DWC3_EP_ENABLED)) {
404 struct dwc3_trb_hw *trb_st_hw;
405 struct dwc3_trb_hw *trb_link_hw;
406 struct dwc3_trb trb_link;
407
408 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
409 if (ret)
410 return ret;
411
412 dep->desc = desc;
c90bfaec 413 dep->comp_desc = comp_desc;
72246da4
FB		 414 dep->type = usb_endpoint_type(desc);
415 dep->flags |= DWC3_EP_ENABLED;
416
417 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
418 reg |= DWC3_DALEPENA_EP(dep->number);
419 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
420
421 if (!usb_endpoint_xfer_isoc(desc))
422 return 0;
423
424 memset(&trb_link, 0, sizeof(trb_link));
425
426 /* Link TRB for ISOC. The HWO but is never reset */
427 trb_st_hw = &dep->trb_pool[0];
428
429 trb_link.bplh = dwc3_trb_dma_offset(dep, trb_st_hw);
430 trb_link.trbctl = DWC3_TRBCTL_LINK_TRB;
431 trb_link.hwo = true;
432
433 trb_link_hw = &dep->trb_pool[DWC3_TRB_NUM - 1];
434 dwc3_trb_to_hw(&trb_link, trb_link_hw);
435 }
436
437 return 0;
438}
439
624407f9
SAS		 440static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum);
441static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
72246da4
FB		 442{
443 struct dwc3_request *req;
444
624407f9
SAS		 445 if (!list_empty(&dep->req_queued))
446 dwc3_stop_active_transfer(dwc, dep->number);
447
72246da4
FB		 448 while (!list_empty(&dep->request_list)) {
449 req = next_request(&dep->request_list);
450
624407f9 451 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
72246da4 452 }
72246da4
FB		 453}
454
455/**
456 * __dwc3_gadget_ep_disable - Disables a HW endpoint
457 * @dep: the endpoint to disable
458 *
624407f9
SAS		 459 * This function also removes requests which are currently processed ny the
460 * hardware and those which are not yet scheduled.
461 * Caller should take care of locking.
72246da4 462 */
72246da4
FB		 463static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
464{
465 struct dwc3 *dwc = dep->dwc;
466 u32 reg;
467
624407f9 468 dwc3_remove_requests(dwc, dep);
72246da4
FB		 469
470 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
471 reg &= ~DWC3_DALEPENA_EP(dep->number);
472 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
473
879631aa 474 dep->stream_capable = false;
72246da4 475 dep->desc = NULL;
c90bfaec 476 dep->comp_desc = NULL;
72246da4 477 dep->type = 0;
879631aa 478 dep->flags = 0;
72246da4
FB		 479
480 return 0;
481}
482
483/* -------------------------------------------------------------------------- */
484
485static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
486 const struct usb_endpoint_descriptor *desc)
487{
488 return -EINVAL;
489}
490
491static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
492{
493 return -EINVAL;
494}
495
496/* -------------------------------------------------------------------------- */
497
498static int dwc3_gadget_ep_enable(struct usb_ep *ep,
499 const struct usb_endpoint_descriptor *desc)
500{
501 struct dwc3_ep *dep;
502 struct dwc3 *dwc;
503 unsigned long flags;
504 int ret;
505
506 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
507 pr_debug("dwc3: invalid parameters\n");
508 return -EINVAL;
509 }
510
511 if (!desc->wMaxPacketSize) {
512 pr_debug("dwc3: missing wMaxPacketSize\n");
513 return -EINVAL;
514 }
515
516 dep = to_dwc3_ep(ep);
517 dwc = dep->dwc;
518
519 switch (usb_endpoint_type(desc)) {
520 case USB_ENDPOINT_XFER_CONTROL:
521 strncat(dep->name, "-control", sizeof(dep->name));
522 break;
523 case USB_ENDPOINT_XFER_ISOC:
524 strncat(dep->name, "-isoc", sizeof(dep->name));
525 break;
526 case USB_ENDPOINT_XFER_BULK:
527 strncat(dep->name, "-bulk", sizeof(dep->name));
528 break;
529 case USB_ENDPOINT_XFER_INT:
530 strncat(dep->name, "-int", sizeof(dep->name));
531 break;
532 default:
533 dev_err(dwc->dev, "invalid endpoint transfer type\n");
534 }
535
536 if (dep->flags & DWC3_EP_ENABLED) {
537 dev_WARN_ONCE(dwc->dev, true, "%s is already enabled\n",
538 dep->name);
539 return 0;
540 }
541
542 dev_vdbg(dwc->dev, "Enabling %s\n", dep->name);
543
544 spin_lock_irqsave(&dwc->lock, flags);
c90bfaec 545 ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc);
72246da4
FB		 546 spin_unlock_irqrestore(&dwc->lock, flags);
547
548 return ret;
549}
550
551static int dwc3_gadget_ep_disable(struct usb_ep *ep)
552{
553 struct dwc3_ep *dep;
554 struct dwc3 *dwc;
555 unsigned long flags;
556 int ret;
557
558 if (!ep) {
559 pr_debug("dwc3: invalid parameters\n");
560 return -EINVAL;
561 }
562
563 dep = to_dwc3_ep(ep);
564 dwc = dep->dwc;
565
566 if (!(dep->flags & DWC3_EP_ENABLED)) {
567 dev_WARN_ONCE(dwc->dev, true, "%s is already disabled\n",
568 dep->name);
569 return 0;
570 }
571
572 snprintf(dep->name, sizeof(dep->name), "ep%d%s",
573 dep->number >> 1,
574 (dep->number & 1) ? "in" : "out");
575
576 spin_lock_irqsave(&dwc->lock, flags);
577 ret = __dwc3_gadget_ep_disable(dep);
578 spin_unlock_irqrestore(&dwc->lock, flags);
579
580 return ret;
581}
582
583static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
584 gfp_t gfp_flags)
585{
586 struct dwc3_request *req;
587 struct dwc3_ep *dep = to_dwc3_ep(ep);
588 struct dwc3 *dwc = dep->dwc;
589
590 req = kzalloc(sizeof(*req), gfp_flags);
591 if (!req) {
592 dev_err(dwc->dev, "not enough memory\n");
593 return NULL;
594 }
595
596 req->epnum = dep->number;
597 req->dep = dep;
598 req->request.dma = DMA_ADDR_INVALID;
599
600 return &req->request;
601}
602
603static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
604 struct usb_request *request)
605{
606 struct dwc3_request *req = to_dwc3_request(request);
607
608 kfree(req);
609}
610
c71fc37c
FB		 611/**
612 * dwc3_prepare_one_trb - setup one TRB from one request
613 * @dep: endpoint for which this request is prepared
614 * @req: dwc3_request pointer
615 */
68e823e2 616static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
eeb720fb
FB		 617 struct dwc3_request *req, dma_addr_t dma,
618 unsigned length, unsigned last, unsigned chain)
c71fc37c 619{
eeb720fb 620 struct dwc3 *dwc = dep->dwc;
c71fc37c
FB		 621 struct dwc3_trb_hw *trb_hw;
622 struct dwc3_trb trb;
623
624 unsigned int cur_slot;
625
eeb720fb
FB		 626 dev_vdbg(dwc->dev, "%s: req %p dma %08llx length %d%s%s\n",
627 dep->name, req, (unsigned long long) dma,
628 length, last ? " last" : "",
629 chain ? " chain" : "");
630
c71fc37c
FB		 631 trb_hw = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
632 cur_slot = dep->free_slot;
633 dep->free_slot++;
634
635 /* Skip the LINK-TRB on ISOC */
636 if (((cur_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
637 usb_endpoint_xfer_isoc(dep->desc))
68e823e2 638 return;
c71fc37c 639
c71fc37c 640 memset(&trb, 0, sizeof(trb));
eeb720fb
FB		 641 if (!req->trb) {
642 dwc3_gadget_move_request_queued(req);
643 req->trb = trb_hw;
644 req->trb_dma = dwc3_trb_dma_offset(dep, trb_hw);
645 }
c71fc37c
FB		 646
647 if (usb_endpoint_xfer_isoc(dep->desc)) {
648 trb.isp_imi = true;
649 trb.csp = true;
650 } else {
eeb720fb 651 trb.chn = chain;
c71fc37c
FB		 652 trb.lst = last;
653 }
654
655 if (usb_endpoint_xfer_bulk(dep->desc) && dep->stream_capable)
656 trb.sid_sofn = req->request.stream_id;
657
658 switch (usb_endpoint_type(dep->desc)) {
659 case USB_ENDPOINT_XFER_CONTROL:
660 trb.trbctl = DWC3_TRBCTL_CONTROL_SETUP;
661 break;
662
663 case USB_ENDPOINT_XFER_ISOC:
664 trb.trbctl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
665
666 /* IOC every DWC3_TRB_NUM / 4 so we can refill */
667 if (!(cur_slot % (DWC3_TRB_NUM / 4)))
668 trb.ioc = last;
669 break;
670
671 case USB_ENDPOINT_XFER_BULK:
672 case USB_ENDPOINT_XFER_INT:
673 trb.trbctl = DWC3_TRBCTL_NORMAL;
674 break;
675 default:
676 /*
677 * This is only possible with faulty memory because we
678 * checked it already :)
679 */
680 BUG();
681 }
682
eeb720fb
FB		 683 trb.length = length;
684 trb.bplh = dma;
c71fc37c
FB		 685 trb.hwo = true;
686
687 dwc3_trb_to_hw(&trb, trb_hw);
c71fc37c
FB		 688}
689
72246da4
FB		 690/*
691 * dwc3_prepare_trbs - setup TRBs from requests
692 * @dep: endpoint for which requests are being prepared
693 * @starting: true if the endpoint is idle and no requests are queued.
694 *
695 * The functions goes through the requests list and setups TRBs for the
696 * transfers. The functions returns once there are not more TRBs available or
697 * it run out of requests.
698 */
68e823e2 699static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
72246da4 700{
68e823e2 701 struct dwc3_request *req, *n;
72246da4 702 u32 trbs_left;
c71fc37c 703 unsigned int last_one = 0;
72246da4
FB		 704
705 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
706
707 /* the first request must not be queued */
708 trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
c71fc37c 709
72246da4
FB		 710 /*
711 * if busy & slot are equal than it is either full or empty. If we are
712 * starting to proceed requests then we are empty. Otherwise we ar
713 * full and don't do anything
714 */
715 if (!trbs_left) {
716 if (!starting)
68e823e2 717 return;
72246da4
FB		 718 trbs_left = DWC3_TRB_NUM;
719 /*
720 * In case we start from scratch, we queue the ISOC requests
721 * starting from slot 1. This is done because we use ring
722 * buffer and have no LST bit to stop us. Instead, we place
723 * IOC bit TRB_NUM/4. We try to avoid to having an interrupt
724 * after the first request so we start at slot 1 and have
725 * 7 requests proceed before we hit the first IOC.
726 * Other transfer types don't use the ring buffer and are
727 * processed from the first TRB until the last one. Since we
728 * don't wrap around we have to start at the beginning.
729 */
730 if (usb_endpoint_xfer_isoc(dep->desc)) {
731 dep->busy_slot = 1;
732 dep->free_slot = 1;
733 } else {
734 dep->busy_slot = 0;
735 dep->free_slot = 0;
736 }
737 }
738
739 /* The last TRB is a link TRB, not used for xfer */
740 if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->desc))
68e823e2 741 return;
72246da4
FB		 742
743 list_for_each_entry_safe(req, n, &dep->request_list, list) {
eeb720fb
FB		 744 unsigned length;
745 dma_addr_t dma;
72246da4 746
eeb720fb
FB		 747 if (req->request.num_mapped_sgs > 0) {
748 struct usb_request *request = &req->request;
749 struct scatterlist *sg = request->sg;
750 struct scatterlist *s;
751 int i;
72246da4 752
eeb720fb
FB		 753 for_each_sg(sg, s, request->num_mapped_sgs, i) {
754 unsigned chain = true;
72246da4 755
eeb720fb
FB		 756 length = sg_dma_len(s);
757 dma = sg_dma_address(s);
72246da4 758
eeb720fb
FB		 759 if (i == (request->num_mapped_sgs - 1)
760 || sg_is_last(s)) {
761 last_one = true;
762 chain = false;
763 }
72246da4 764
eeb720fb
FB		 765 trbs_left--;
766 if (!trbs_left)
767 last_one = true;
72246da4 768
eeb720fb
FB		 769 if (last_one)
770 chain = false;
72246da4 771
eeb720fb
FB		 772 dwc3_prepare_one_trb(dep, req, dma, length,
773 last_one, chain);
72246da4 774
eeb720fb
FB		 775 if (last_one)
776 break;
777 }
72246da4 778 } else {
eeb720fb
FB		 779 dma = req->request.dma;
780 length = req->request.length;
781 trbs_left--;
72246da4 782
eeb720fb
FB		 783 if (!trbs_left)
784 last_one = 1;
879631aa 785
eeb720fb
FB		 786 /* Is this the last request? */
787 if (list_is_last(&req->list, &dep->request_list))
788 last_one = 1;
72246da4 789
eeb720fb
FB		 790 dwc3_prepare_one_trb(dep, req, dma, length,
791 last_one, false);
72246da4 792
eeb720fb
FB		 793 if (last_one)
794 break;
72246da4 795 }
72246da4 796 }
72246da4
FB		 797}
798
799static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
800 int start_new)
801{
802 struct dwc3_gadget_ep_cmd_params params;
803 struct dwc3_request *req;
804 struct dwc3 *dwc = dep->dwc;
805 int ret;
806 u32 cmd;
807
808 if (start_new && (dep->flags & DWC3_EP_BUSY)) {
809 dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name);
810 return -EBUSY;
811 }
812 dep->flags &= ~DWC3_EP_PENDING_REQUEST;
813
814 /*
815 * If we are getting here after a short-out-packet we don't enqueue any
816 * new requests as we try to set the IOC bit only on the last request.
817 */
818 if (start_new) {
819 if (list_empty(&dep->req_queued))
820 dwc3_prepare_trbs(dep, start_new);
821
822 /* req points to the first request which will be sent */
823 req = next_request(&dep->req_queued);
824 } else {
68e823e2
FB		 825 dwc3_prepare_trbs(dep, start_new);
826
72246da4
FB		 827 /*
828 * req points to the first request where HWO changed
829 * from 0 to 1
830 */
68e823e2 831 req = next_request(&dep->req_queued);
72246da4
FB		 832 }
833 if (!req) {
834 dep->flags |= DWC3_EP_PENDING_REQUEST;
835 return 0;
836 }
837
838 memset(&params, 0, sizeof(params));
dc1c70a7
FB		 839 params.param0 = upper_32_bits(req->trb_dma);
840 params.param1 = lower_32_bits(req->trb_dma);
72246da4
FB		 841
842 if (start_new)
843 cmd = DWC3_DEPCMD_STARTTRANSFER;
844 else
845 cmd = DWC3_DEPCMD_UPDATETRANSFER;
846
847 cmd |= DWC3_DEPCMD_PARAM(cmd_param);
848 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
849 if (ret < 0) {
850 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
851
852 /*
853 * FIXME we need to iterate over the list of requests
854 * here and stop, unmap, free and del each of the linked
855 * requests instead of we do now.
856 */
857 dwc3_unmap_buffer_from_dma(req);
858 list_del(&req->list);
859 return ret;
860 }
861
862 dep->flags |= DWC3_EP_BUSY;
863 dep->res_trans_idx = dwc3_gadget_ep_get_transfer_index(dwc,
864 dep->number);
25b8ff68
FB		 865
866 WARN_ON_ONCE(!dep->res_trans_idx);
867
72246da4
FB		 868 return 0;
869}
870
871static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
872{
873 req->request.actual = 0;
874 req->request.status = -EINPROGRESS;
875 req->direction = dep->direction;
876 req->epnum = dep->number;
877
878 /*
879 * We only add to our list of requests now and
880 * start consuming the list once we get XferNotReady
881 * IRQ.
882 *
883 * That way, we avoid doing anything that we don't need
884 * to do now and defer it until the point we receive a
885 * particular token from the Host side.
886 *
887 * This will also avoid Host cancelling URBs due to too
888 * many NACKs.
889 */
890 dwc3_map_buffer_to_dma(req);
891 list_add_tail(&req->list, &dep->request_list);
892
893 /*
894 * There is one special case: XferNotReady with
895 * empty list of requests. We need to kick the
896 * transfer here in that situation, otherwise
897 * we will be NAKing forever.
898 *
899 * If we get XferNotReady before gadget driver
900 * has a chance to queue a request, we will ACK
901 * the IRQ but won't be able to receive the data
902 * until the next request is queued. The following
903 * code is handling exactly that.
904 */
905 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
906 int ret;
907 int start_trans;
908
909 start_trans = 1;
910 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
911 dep->flags & DWC3_EP_BUSY)
912 start_trans = 0;
913
914 ret = __dwc3_gadget_kick_transfer(dep, 0, start_trans);
915 if (ret && ret != -EBUSY) {
916 struct dwc3 *dwc = dep->dwc;
917
918 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
919 dep->name);
920 }
921 };
922
923 return 0;
924}
925
926static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
927 gfp_t gfp_flags)
928{
929 struct dwc3_request *req = to_dwc3_request(request);
930 struct dwc3_ep *dep = to_dwc3_ep(ep);
931 struct dwc3 *dwc = dep->dwc;
932
933 unsigned long flags;
934
935 int ret;
936
937 if (!dep->desc) {
938 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
939 request, ep->name);
940 return -ESHUTDOWN;
941 }
942
943 dev_vdbg(dwc->dev, "queing request %p to %s length %d\n",
944 request, ep->name, request->length);
945
946 spin_lock_irqsave(&dwc->lock, flags);
947 ret = __dwc3_gadget_ep_queue(dep, req);
948 spin_unlock_irqrestore(&dwc->lock, flags);
949
950 return ret;
951}
952
953static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
954 struct usb_request *request)
955{
956 struct dwc3_request *req = to_dwc3_request(request);
957 struct dwc3_request *r = NULL;
958
959 struct dwc3_ep *dep = to_dwc3_ep(ep);
960 struct dwc3 *dwc = dep->dwc;
961
962 unsigned long flags;
963 int ret = 0;
964
965 spin_lock_irqsave(&dwc->lock, flags);
966
967 list_for_each_entry(r, &dep->request_list, list) {
968 if (r == req)
969 break;
970 }
971
972 if (r != req) {
973 list_for_each_entry(r, &dep->req_queued, list) {
974 if (r == req)
975 break;
976 }
977 if (r == req) {
978 /* wait until it is processed */
979 dwc3_stop_active_transfer(dwc, dep->number);
980 goto out0;
981 }
982 dev_err(dwc->dev, "request %p was not queued to %s\n",
983 request, ep->name);
984 ret = -EINVAL;
985 goto out0;
986 }
987
988 /* giveback the request */
989 dwc3_gadget_giveback(dep, req, -ECONNRESET);
990
991out0:
992 spin_unlock_irqrestore(&dwc->lock, flags);
993
994 return ret;
995}
996
997int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value)
998{
999 struct dwc3_gadget_ep_cmd_params params;
1000 struct dwc3 *dwc = dep->dwc;
1001 int ret;
1002
1003 memset(&params, 0x00, sizeof(params));
1004
1005 if (value) {
0b7836a9
FB		 1006 if (dep->number == 0 || dep->number == 1) {
1007 /*
1008 * Whenever EP0 is stalled, we will restart
1009 * the state machine, thus moving back to
1010 * Setup Phase
1011 */
1012 dwc->ep0state = EP0_SETUP_PHASE;
1013 }
72246da4
FB		 1014
1015 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1016 DWC3_DEPCMD_SETSTALL, &params);
1017 if (ret)
1018 dev_err(dwc->dev, "failed to %s STALL on %s\n",
1019 value ? "set" : "clear",
1020 dep->name);
1021 else
1022 dep->flags |= DWC3_EP_STALL;
1023 } else {
5275455a
PZ		 1024 if (dep->flags & DWC3_EP_WEDGE)
1025 return 0;
1026
72246da4
FB		 1027 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1028 DWC3_DEPCMD_CLEARSTALL, &params);
1029 if (ret)
1030 dev_err(dwc->dev, "failed to %s STALL on %s\n",
1031 value ? "set" : "clear",
1032 dep->name);
1033 else
1034 dep->flags &= ~DWC3_EP_STALL;
1035 }
5275455a 1036
72246da4
FB		 1037 return ret;
1038}
1039
1040static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1041{
1042 struct dwc3_ep *dep = to_dwc3_ep(ep);
1043 struct dwc3 *dwc = dep->dwc;
1044
1045 unsigned long flags;
1046
1047 int ret;
1048
1049 spin_lock_irqsave(&dwc->lock, flags);
1050
1051 if (usb_endpoint_xfer_isoc(dep->desc)) {
1052 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1053 ret = -EINVAL;
1054 goto out;
1055 }
1056
1057 ret = __dwc3_gadget_ep_set_halt(dep, value);
1058out:
1059 spin_unlock_irqrestore(&dwc->lock, flags);
1060
1061 return ret;
1062}
1063
1064static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1065{
1066 struct dwc3_ep *dep = to_dwc3_ep(ep);
1067
1068 dep->flags |= DWC3_EP_WEDGE;
1069
5275455a 1070 return dwc3_gadget_ep_set_halt(ep, 1);
72246da4
FB		 1071}
1072
1073/* -------------------------------------------------------------------------- */
1074
1075static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1076 .bLength = USB_DT_ENDPOINT_SIZE,
1077 .bDescriptorType = USB_DT_ENDPOINT,
1078 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1079};
1080
1081static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1082 .enable = dwc3_gadget_ep0_enable,
1083 .disable = dwc3_gadget_ep0_disable,
1084 .alloc_request = dwc3_gadget_ep_alloc_request,
1085 .free_request = dwc3_gadget_ep_free_request,
1086 .queue = dwc3_gadget_ep0_queue,
1087 .dequeue = dwc3_gadget_ep_dequeue,
1088 .set_halt = dwc3_gadget_ep_set_halt,
1089 .set_wedge = dwc3_gadget_ep_set_wedge,
1090};
1091
1092static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1093 .enable = dwc3_gadget_ep_enable,
1094 .disable = dwc3_gadget_ep_disable,
1095 .alloc_request = dwc3_gadget_ep_alloc_request,
1096 .free_request = dwc3_gadget_ep_free_request,
1097 .queue = dwc3_gadget_ep_queue,
1098 .dequeue = dwc3_gadget_ep_dequeue,
1099 .set_halt = dwc3_gadget_ep_set_halt,
1100 .set_wedge = dwc3_gadget_ep_set_wedge,
1101};
1102
1103/* -------------------------------------------------------------------------- */
1104
1105static int dwc3_gadget_get_frame(struct usb_gadget *g)
1106{
1107 struct dwc3 *dwc = gadget_to_dwc(g);
1108 u32 reg;
1109
1110 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1111 return DWC3_DSTS_SOFFN(reg);
1112}
1113
1114static int dwc3_gadget_wakeup(struct usb_gadget *g)
1115{
1116 struct dwc3 *dwc = gadget_to_dwc(g);
1117
1118 unsigned long timeout;
1119 unsigned long flags;
1120
1121 u32 reg;
1122
1123 int ret = 0;
1124
1125 u8 link_state;
1126 u8 speed;
1127
1128 spin_lock_irqsave(&dwc->lock, flags);
1129
1130 /*
1131 * According to the Databook Remote wakeup request should
1132 * be issued only when the device is in early suspend state.
1133 *
1134 * We can check that via USB Link State bits in DSTS register.
1135 */
1136 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1137
1138 speed = reg & DWC3_DSTS_CONNECTSPD;
1139 if (speed == DWC3_DSTS_SUPERSPEED) {
1140 dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n");
1141 ret = -EINVAL;
1142 goto out;
1143 }
1144
1145 link_state = DWC3_DSTS_USBLNKST(reg);
1146
1147 switch (link_state) {
1148 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1149 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1150 break;
1151 default:
1152 dev_dbg(dwc->dev, "can't wakeup from link state %d\n",
1153 link_state);
1154 ret = -EINVAL;
1155 goto out;
1156 }
1157
1158 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1159
1160 /*
1161 * Switch link state to Recovery. In HS/FS/LS this means
1162 * RemoteWakeup Request
1163 */
1164 reg |= DWC3_DCTL_ULSTCHNG_RECOVERY;
1165 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1166
1167 /* wait for at least 2000us */
1168 usleep_range(2000, 2500);
1169
1170 /* write zeroes to Link Change Request */
1171 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1172 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1173
1174 /* pool until Link State change to ON */
1175 timeout = jiffies + msecs_to_jiffies(100);
1176
1177 while (!(time_after(jiffies, timeout))) {
1178 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1179
1180 /* in HS, means ON */
1181 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1182 break;
1183 }
1184
1185 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1186 dev_err(dwc->dev, "failed to send remote wakeup\n");
1187 ret = -EINVAL;
1188 }
1189
1190out:
1191 spin_unlock_irqrestore(&dwc->lock, flags);
1192
1193 return ret;
1194}
1195
1196static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1197 int is_selfpowered)
1198{
1199 struct dwc3 *dwc = gadget_to_dwc(g);
1200
1201 dwc->is_selfpowered = !!is_selfpowered;
1202
1203 return 0;
1204}
1205
1206static void dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on)
1207{
1208 u32 reg;
61d58242 1209 u32 timeout = 500;
72246da4
FB		 1210
1211 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1212 if (is_on)
1213 reg |= DWC3_DCTL_RUN_STOP;
1214 else
1215 reg &= ~DWC3_DCTL_RUN_STOP;
1216
1217 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1218
1219 do {
1220 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1221 if (is_on) {
1222 if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1223 break;
1224 } else {
1225 if (reg & DWC3_DSTS_DEVCTRLHLT)
1226 break;
1227 }
72246da4
FB		 1228 timeout--;
1229 if (!timeout)
1230 break;
61d58242 1231 udelay(1);
72246da4
FB		 1232 } while (1);
1233
1234 dev_vdbg(dwc->dev, "gadget %s data soft-%s\n",
1235 dwc->gadget_driver
1236 ? dwc->gadget_driver->function : "no-function",
1237 is_on ? "connect" : "disconnect");
1238}
1239
1240static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1241{
1242 struct dwc3 *dwc = gadget_to_dwc(g);
1243 unsigned long flags;
1244
1245 is_on = !!is_on;
1246
1247 spin_lock_irqsave(&dwc->lock, flags);
1248 dwc3_gadget_run_stop(dwc, is_on);
1249 spin_unlock_irqrestore(&dwc->lock, flags);
1250
1251 return 0;
1252}
1253
1254static int dwc3_gadget_start(struct usb_gadget *g,
1255 struct usb_gadget_driver *driver)
1256{
1257 struct dwc3 *dwc = gadget_to_dwc(g);
1258 struct dwc3_ep *dep;
1259 unsigned long flags;
1260 int ret = 0;
1261 u32 reg;
1262
1263 spin_lock_irqsave(&dwc->lock, flags);
1264
1265 if (dwc->gadget_driver) {
1266 dev_err(dwc->dev, "%s is already bound to %s\n",
1267 dwc->gadget.name,
1268 dwc->gadget_driver->driver.name);
1269 ret = -EBUSY;
1270 goto err0;
1271 }
1272
1273 dwc->gadget_driver = driver;
1274 dwc->gadget.dev.driver = &driver->driver;
1275
72246da4
FB		 1276 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1277 reg &= ~(DWC3_DCFG_SPEED_MASK);
6c167fc9 1278 reg |= dwc->maximum_speed;
72246da4
FB		 1279 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1280
b23c8439
PZ		 1281 dwc->start_config_issued = false;
1282
72246da4
FB		 1283 /* Start with SuperSpeed Default */
1284 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1285
1286 dep = dwc->eps[0];
c90bfaec 1287 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL);
72246da4
FB		 1288 if (ret) {
1289 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1290 goto err0;
1291 }
1292
1293 dep = dwc->eps[1];
c90bfaec 1294 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL);
72246da4
FB		 1295 if (ret) {
1296 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1297 goto err1;
1298 }
1299
1300 /* begin to receive SETUP packets */
c7fcdeb2 1301 dwc->ep0state = EP0_SETUP_PHASE;
72246da4
FB		 1302 dwc3_ep0_out_start(dwc);
1303
1304 spin_unlock_irqrestore(&dwc->lock, flags);
1305
1306 return 0;
1307
1308err1:
1309 __dwc3_gadget_ep_disable(dwc->eps[0]);
1310
1311err0:
1312 spin_unlock_irqrestore(&dwc->lock, flags);
1313
1314 return ret;
1315}
1316
1317static int dwc3_gadget_stop(struct usb_gadget *g,
1318 struct usb_gadget_driver *driver)
1319{
1320 struct dwc3 *dwc = gadget_to_dwc(g);
1321 unsigned long flags;
1322
1323 spin_lock_irqsave(&dwc->lock, flags);
1324
1325 __dwc3_gadget_ep_disable(dwc->eps[0]);
1326 __dwc3_gadget_ep_disable(dwc->eps[1]);
1327
1328 dwc->gadget_driver = NULL;
1329 dwc->gadget.dev.driver = NULL;
1330
1331 spin_unlock_irqrestore(&dwc->lock, flags);
1332
1333 return 0;
1334}
1335static const struct usb_gadget_ops dwc3_gadget_ops = {
1336 .get_frame = dwc3_gadget_get_frame,
1337 .wakeup = dwc3_gadget_wakeup,
1338 .set_selfpowered = dwc3_gadget_set_selfpowered,
1339 .pullup = dwc3_gadget_pullup,
1340 .udc_start = dwc3_gadget_start,
1341 .udc_stop = dwc3_gadget_stop,
1342};
1343
1344/* -------------------------------------------------------------------------- */
1345
1346static int __devinit dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1347{
1348 struct dwc3_ep *dep;
1349 u8 epnum;
1350
1351 INIT_LIST_HEAD(&dwc->gadget.ep_list);
1352
1353 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1354 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1355 if (!dep) {
1356 dev_err(dwc->dev, "can't allocate endpoint %d\n",
1357 epnum);
1358 return -ENOMEM;
1359 }
1360
1361 dep->dwc = dwc;
1362 dep->number = epnum;
1363 dwc->eps[epnum] = dep;
1364
1365 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1366 (epnum & 1) ? "in" : "out");
1367 dep->endpoint.name = dep->name;
1368 dep->direction = (epnum & 1);
1369
1370 if (epnum == 0 || epnum == 1) {
1371 dep->endpoint.maxpacket = 512;
1372 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1373 if (!epnum)
1374 dwc->gadget.ep0 = &dep->endpoint;
1375 } else {
1376 int ret;
1377
1378 dep->endpoint.maxpacket = 1024;
12d36c16 1379 dep->endpoint.max_streams = 15;
72246da4
FB		 1380 dep->endpoint.ops = &dwc3_gadget_ep_ops;
1381 list_add_tail(&dep->endpoint.ep_list,
1382 &dwc->gadget.ep_list);
1383
1384 ret = dwc3_alloc_trb_pool(dep);
25b8ff68 1385 if (ret)
72246da4 1386 return ret;
72246da4 1387 }
25b8ff68 1388
72246da4
FB		 1389 INIT_LIST_HEAD(&dep->request_list);
1390 INIT_LIST_HEAD(&dep->req_queued);
1391 }
1392
1393 return 0;
1394}
1395
1396static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1397{
1398 struct dwc3_ep *dep;
1399 u8 epnum;
1400
1401 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1402 dep = dwc->eps[epnum];
1403 dwc3_free_trb_pool(dep);
1404
1405 if (epnum != 0 && epnum != 1)
1406 list_del(&dep->endpoint.ep_list);
1407
1408 kfree(dep);
1409 }
1410}
1411
1412static void dwc3_gadget_release(struct device *dev)
1413{
1414 dev_dbg(dev, "%s\n", __func__);
1415}
1416
1417/* -------------------------------------------------------------------------- */
1418static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1419 const struct dwc3_event_depevt *event, int status)
1420{
1421 struct dwc3_request *req;
1422 struct dwc3_trb trb;
1423 unsigned int count;
1424 unsigned int s_pkt = 0;
1425
1426 do {
1427 req = next_request(&dep->req_queued);
d39ee7be
SAS		 1428 if (!req) {
1429 WARN_ON_ONCE(1);
1430 return 1;
1431 }
72246da4
FB		 1432
1433 dwc3_trb_to_nat(req->trb, &trb);
1434
0d2f4758
SAS		 1435 if (trb.hwo && status != -ESHUTDOWN)
1436 /*
1437 * We continue despite the error. There is not much we
1438 * can do. If we don't clean in up we loop for ever. If
1439 * we skip the TRB than it gets overwritten reused after
1440 * a while since we use them in a ring buffer. a BUG()
1441 * would help. Lets hope that if this occures, someone
1442 * fixes the root cause instead of looking away :)
1443 */
72246da4
FB		 1444 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1445 dep->name, req->trb);
72246da4
FB		 1446 count = trb.length;
1447
1448 if (dep->direction) {
1449 if (count) {
1450 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1451 dep->name);
1452 status = -ECONNRESET;
1453 }
1454 } else {
1455 if (count && (event->status & DEPEVT_STATUS_SHORT))
1456 s_pkt = 1;
1457 }
1458
1459 /*
1460 * We assume here we will always receive the entire data block
1461 * which we should receive. Meaning, if we program RX to
1462 * receive 4K but we receive only 2K, we assume that's all we
1463 * should receive and we simply bounce the request back to the
1464 * gadget driver for further processing.
1465 */
1466 req->request.actual += req->request.length - count;
1467 dwc3_gadget_giveback(dep, req, status);
1468 if (s_pkt)
1469 break;
1470 if ((event->status & DEPEVT_STATUS_LST) && trb.lst)
1471 break;
1472 if ((event->status & DEPEVT_STATUS_IOC) && trb.ioc)
1473 break;
1474 } while (1);
1475
1476 if ((event->status & DEPEVT_STATUS_IOC) && trb.ioc)
1477 return 0;
1478 return 1;
1479}
1480
1481static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
1482 struct dwc3_ep *dep, const struct dwc3_event_depevt *event,
1483 int start_new)
1484{
1485 unsigned status = 0;
1486 int clean_busy;
1487
1488 if (event->status & DEPEVT_STATUS_BUSERR)
1489 status = -ECONNRESET;
1490
1491 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
a1ae9be5 1492 if (clean_busy) {
72246da4 1493 dep->flags &= ~DWC3_EP_BUSY;
a1ae9be5
SAS		 1494 dep->res_trans_idx = 0;
1495 }
fae2b904
FB		 1496
1497 /*
1498 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
1499 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
1500 */
1501 if (dwc->revision < DWC3_REVISION_183A) {
1502 u32 reg;
1503 int i;
1504
1505 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
1506 struct dwc3_ep *dep = dwc->eps[i];
1507
1508 if (!(dep->flags & DWC3_EP_ENABLED))
1509 continue;
1510
1511 if (!list_empty(&dep->req_queued))
1512 return;
1513 }
1514
1515 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1516 reg |= dwc->u1u2;
1517 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1518
1519 dwc->u1u2 = 0;
1520 }
72246da4
FB		 1521}
1522
1523static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1524 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1525{
1526 u32 uf;
1527
1528 if (list_empty(&dep->request_list)) {
1529 dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n",
1530 dep->name);
1531 return;
1532 }
1533
1534 if (event->parameters) {
1535 u32 mask;
1536
1537 mask = ~(dep->interval - 1);
1538 uf = event->parameters & mask;
1539 /* 4 micro frames in the future */
1540 uf += dep->interval * 4;
1541 } else {
1542 uf = 0;
1543 }
1544
1545 __dwc3_gadget_kick_transfer(dep, uf, 1);
1546}
1547
1548static void dwc3_process_ep_cmd_complete(struct dwc3_ep *dep,
1549 const struct dwc3_event_depevt *event)
1550{
1551 struct dwc3 *dwc = dep->dwc;
1552 struct dwc3_event_depevt mod_ev = *event;
1553
1554 /*
1555 * We were asked to remove one requests. It is possible that this
1556 * request and a few other were started together and have the same
1557 * transfer index. Since we stopped the complete endpoint we don't
1558 * know how many requests were already completed (and not yet)
1559 * reported and how could be done (later). We purge them all until
1560 * the end of the list.
1561 */
1562 mod_ev.status = DEPEVT_STATUS_LST;
1563 dwc3_cleanup_done_reqs(dwc, dep, &mod_ev, -ESHUTDOWN);
1564 dep->flags &= ~DWC3_EP_BUSY;
1565 /* pending requets are ignored and are queued on XferNotReady */
72246da4
FB		 1566}
1567
1568static void dwc3_ep_cmd_compl(struct dwc3_ep *dep,
1569 const struct dwc3_event_depevt *event)
1570{
1571 u32 param = event->parameters;
1572 u32 cmd_type = (param >> 8) & ((1 << 5) - 1);
1573
1574 switch (cmd_type) {
1575 case DWC3_DEPCMD_ENDTRANSFER:
1576 dwc3_process_ep_cmd_complete(dep, event);
1577 break;
1578 case DWC3_DEPCMD_STARTTRANSFER:
1579 dep->res_trans_idx = param & 0x7f;
1580 break;
1581 default:
1582 printk(KERN_ERR "%s() unknown /unexpected type: %d\n",
1583 __func__, cmd_type);
1584 break;
1585 };
1586}
1587
1588static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
1589 const struct dwc3_event_depevt *event)
1590{
1591 struct dwc3_ep *dep;
1592 u8 epnum = event->endpoint_number;
1593
1594 dep = dwc->eps[epnum];
1595
1596 dev_vdbg(dwc->dev, "%s: %s\n", dep->name,
1597 dwc3_ep_event_string(event->endpoint_event));
1598
1599 if (epnum == 0 || epnum == 1) {
1600 dwc3_ep0_interrupt(dwc, event);
1601 return;
1602 }
1603
1604 switch (event->endpoint_event) {
1605 case DWC3_DEPEVT_XFERCOMPLETE:
1606 if (usb_endpoint_xfer_isoc(dep->desc)) {
1607 dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n",
1608 dep->name);
1609 return;
1610 }
1611
1612 dwc3_endpoint_transfer_complete(dwc, dep, event, 1);
1613 break;
1614 case DWC3_DEPEVT_XFERINPROGRESS:
1615 if (!usb_endpoint_xfer_isoc(dep->desc)) {
1616 dev_dbg(dwc->dev, "%s is not an Isochronous endpoint\n",
1617 dep->name);
1618 return;
1619 }
1620
1621 dwc3_endpoint_transfer_complete(dwc, dep, event, 0);
1622 break;
1623 case DWC3_DEPEVT_XFERNOTREADY:
1624 if (usb_endpoint_xfer_isoc(dep->desc)) {
1625 dwc3_gadget_start_isoc(dwc, dep, event);
1626 } else {
1627 int ret;
1628
1629 dev_vdbg(dwc->dev, "%s: reason %s\n",
1630 dep->name, event->status
1631 ? "Transfer Active"
1632 : "Transfer Not Active");
1633
1634 ret = __dwc3_gadget_kick_transfer(dep, 0, 1);
1635 if (!ret || ret == -EBUSY)
1636 return;
1637
1638 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1639 dep->name);
1640 }
1641
879631aa
FB		 1642 break;
1643 case DWC3_DEPEVT_STREAMEVT:
1644 if (!usb_endpoint_xfer_bulk(dep->desc)) {
1645 dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
1646 dep->name);
1647 return;
1648 }
1649
1650 switch (event->status) {
1651 case DEPEVT_STREAMEVT_FOUND:
1652 dev_vdbg(dwc->dev, "Stream %d found and started\n",
1653 event->parameters);
1654
1655 break;
1656 case DEPEVT_STREAMEVT_NOTFOUND:
1657 /* FALLTHROUGH */
1658 default:
1659 dev_dbg(dwc->dev, "Couldn't find suitable stream\n");
1660 }
72246da4
FB		 1661 break;
1662 case DWC3_DEPEVT_RXTXFIFOEVT:
1663 dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name);
1664 break;
72246da4
FB		 1665 case DWC3_DEPEVT_EPCMDCMPLT:
1666 dwc3_ep_cmd_compl(dep, event);
1667 break;
1668 }
1669}
1670
1671static void dwc3_disconnect_gadget(struct dwc3 *dwc)
1672{
1673 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
1674 spin_unlock(&dwc->lock);
1675 dwc->gadget_driver->disconnect(&dwc->gadget);
1676 spin_lock(&dwc->lock);
1677 }
1678}
1679
1680static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum)
1681{
1682 struct dwc3_ep *dep;
1683 struct dwc3_gadget_ep_cmd_params params;
1684 u32 cmd;
1685 int ret;
1686
1687 dep = dwc->eps[epnum];
1688
624407f9 1689 WARN_ON(!dep->res_trans_idx);
72246da4
FB		 1690 if (dep->res_trans_idx) {
1691 cmd = DWC3_DEPCMD_ENDTRANSFER;
1692 cmd |= DWC3_DEPCMD_HIPRI_FORCERM | DWC3_DEPCMD_CMDIOC;
1693 cmd |= DWC3_DEPCMD_PARAM(dep->res_trans_idx);
1694 memset(&params, 0, sizeof(params));
1695 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
1696 WARN_ON_ONCE(ret);
a1ae9be5 1697 dep->res_trans_idx = 0;
72246da4
FB		 1698 }
1699}
1700
1701static void dwc3_stop_active_transfers(struct dwc3 *dwc)
1702{
1703 u32 epnum;
1704
1705 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1706 struct dwc3_ep *dep;
1707
1708 dep = dwc->eps[epnum];
1709 if (!(dep->flags & DWC3_EP_ENABLED))
1710 continue;
1711
624407f9 1712 dwc3_remove_requests(dwc, dep);
72246da4
FB		 1713 }
1714}
1715
1716static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
1717{
1718 u32 epnum;
1719
1720 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1721 struct dwc3_ep *dep;
1722 struct dwc3_gadget_ep_cmd_params params;
1723 int ret;
1724
1725 dep = dwc->eps[epnum];
1726
1727 if (!(dep->flags & DWC3_EP_STALL))
1728 continue;
1729
1730 dep->flags &= ~DWC3_EP_STALL;
1731
1732 memset(&params, 0, sizeof(params));
1733 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1734 DWC3_DEPCMD_CLEARSTALL, &params);
1735 WARN_ON_ONCE(ret);
1736 }
1737}
1738
1739static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
1740{
1741 dev_vdbg(dwc->dev, "%s\n", __func__);
1742#if 0
1743 XXX
1744 U1/U2 is powersave optimization. Skip it for now. Anyway we need to
1745 enable it before we can disable it.
1746
1747 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1748 reg &= ~DWC3_DCTL_INITU1ENA;
1749 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1750
1751 reg &= ~DWC3_DCTL_INITU2ENA;
1752 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1753#endif
1754
1755 dwc3_stop_active_transfers(dwc);
1756 dwc3_disconnect_gadget(dwc);
b23c8439 1757 dwc->start_config_issued = false;
72246da4
FB		 1758
1759 dwc->gadget.speed = USB_SPEED_UNKNOWN;
df62df56 1760 dwc->setup_packet_pending = false;
72246da4
FB		 1761}
1762
1763static void dwc3_gadget_usb3_phy_power(struct dwc3 *dwc, int on)
1764{
1765 u32 reg;
1766
1767 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
1768
1769 if (on)
1770 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
1771 else
1772 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
1773
1774 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
1775}
1776
1777static void dwc3_gadget_usb2_phy_power(struct dwc3 *dwc, int on)
1778{
1779 u32 reg;
1780
1781 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1782
1783 if (on)
1784 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
1785 else
1786 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
1787
1788 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1789}
1790
1791static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
1792{
1793 u32 reg;
1794
1795 dev_vdbg(dwc->dev, "%s\n", __func__);
1796
df62df56
FB		 1797 /*
1798 * WORKAROUND: DWC3 revisions <1.88a have an issue which
1799 * would cause a missing Disconnect Event if there's a
1800 * pending Setup Packet in the FIFO.
1801 *
1802 * There's no suggested workaround on the official Bug
1803 * report, which states that "unless the driver/application
1804 * is doing any special handling of a disconnect event,
1805 * there is no functional issue".
1806 *
1807 * Unfortunately, it turns out that we _do_ some special
1808 * handling of a disconnect event, namely complete all
1809 * pending transfers, notify gadget driver of the
1810 * disconnection, and so on.
1811 *
1812 * Our suggested workaround is to follow the Disconnect
1813 * Event steps here, instead, based on a setup_packet_pending
1814 * flag. Such flag gets set whenever we have a XferNotReady
1815 * event on EP0 and gets cleared on XferComplete for the
1816 * same endpoint.
1817 *
1818 * Refers to:
1819 *
1820 * STAR#9000466709: RTL: Device : Disconnect event not
1821 * generated if setup packet pending in FIFO
1822 */
1823 if (dwc->revision < DWC3_REVISION_188A) {
1824 if (dwc->setup_packet_pending)
1825 dwc3_gadget_disconnect_interrupt(dwc);
1826 }
1827
961906ed
FB		 1828 /* after reset -> Default State */
1829 dwc->dev_state = DWC3_DEFAULT_STATE;
1830
72246da4
FB		 1831 /* Enable PHYs */
1832 dwc3_gadget_usb2_phy_power(dwc, true);
1833 dwc3_gadget_usb3_phy_power(dwc, true);
1834
1835 if (dwc->gadget.speed != USB_SPEED_UNKNOWN)
1836 dwc3_disconnect_gadget(dwc);
1837
1838 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1839 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
1840 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1841
1842 dwc3_stop_active_transfers(dwc);
1843 dwc3_clear_stall_all_ep(dwc);
b23c8439 1844 dwc->start_config_issued = false;
72246da4
FB		 1845
1846 /* Reset device address to zero */
1847 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1848 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
1849 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
72246da4
FB		 1850}
1851
1852static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
1853{
1854 u32 reg;
1855 u32 usb30_clock = DWC3_GCTL_CLK_BUS;
1856
1857 /*
1858 * We change the clock only at SS but I dunno why I would want to do
1859 * this. Maybe it becomes part of the power saving plan.
1860 */
1861
1862 if (speed != DWC3_DSTS_SUPERSPEED)
1863 return;
1864
1865 /*
1866 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
1867 * each time on Connect Done.
1868 */
1869 if (!usb30_clock)
1870 return;
1871
1872 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
1873 reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
1874 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
1875}
1876
1877static void dwc3_gadget_disable_phy(struct dwc3 *dwc, u8 speed)
1878{
1879 switch (speed) {
1880 case USB_SPEED_SUPER:
1881 dwc3_gadget_usb2_phy_power(dwc, false);
1882 break;
1883 case USB_SPEED_HIGH:
1884 case USB_SPEED_FULL:
1885 case USB_SPEED_LOW:
1886 dwc3_gadget_usb3_phy_power(dwc, false);
1887 break;
1888 }
1889}
1890
1891static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
1892{
1893 struct dwc3_gadget_ep_cmd_params params;
1894 struct dwc3_ep *dep;
1895 int ret;
1896 u32 reg;
1897 u8 speed;
1898
1899 dev_vdbg(dwc->dev, "%s\n", __func__);
1900
1901 memset(&params, 0x00, sizeof(params));
1902
72246da4
FB		 1903 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1904 speed = reg & DWC3_DSTS_CONNECTSPD;
1905 dwc->speed = speed;
1906
1907 dwc3_update_ram_clk_sel(dwc, speed);
1908
1909 switch (speed) {
1910 case DWC3_DCFG_SUPERSPEED:
05870c5b
FB		 1911 /*
1912 * WORKAROUND: DWC3 revisions <1.90a have an issue which
1913 * would cause a missing USB3 Reset event.
1914 *
1915 * In such situations, we should force a USB3 Reset
1916 * event by calling our dwc3_gadget_reset_interrupt()
1917 * routine.
1918 *
1919 * Refers to:
1920 *
1921 * STAR#9000483510: RTL: SS : USB3 reset event may
1922 * not be generated always when the link enters poll
1923 */
1924 if (dwc->revision < DWC3_REVISION_190A)
1925 dwc3_gadget_reset_interrupt(dwc);
1926
72246da4
FB		 1927 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1928 dwc->gadget.ep0->maxpacket = 512;
1929 dwc->gadget.speed = USB_SPEED_SUPER;
1930 break;
1931 case DWC3_DCFG_HIGHSPEED:
1932 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
1933 dwc->gadget.ep0->maxpacket = 64;
1934 dwc->gadget.speed = USB_SPEED_HIGH;
1935 break;
1936 case DWC3_DCFG_FULLSPEED2:
1937 case DWC3_DCFG_FULLSPEED1:
1938 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
1939 dwc->gadget.ep0->maxpacket = 64;
1940 dwc->gadget.speed = USB_SPEED_FULL;
1941 break;
1942 case DWC3_DCFG_LOWSPEED:
1943 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
1944 dwc->gadget.ep0->maxpacket = 8;
1945 dwc->gadget.speed = USB_SPEED_LOW;
1946 break;
1947 }
1948
1949 /* Disable unneded PHY */
1950 dwc3_gadget_disable_phy(dwc, dwc->gadget.speed);
1951
1952 dep = dwc->eps[0];
c90bfaec 1953 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL);
72246da4
FB		 1954 if (ret) {
1955 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1956 return;
1957 }
1958
1959 dep = dwc->eps[1];
c90bfaec 1960 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL);
72246da4
FB		 1961 if (ret) {
1962 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1963 return;
1964 }
1965
1966 /*
1967 * Configure PHY via GUSB3PIPECTLn if required.
1968 *
1969 * Update GTXFIFOSIZn
1970 *
1971 * In both cases reset values should be sufficient.
1972 */
1973}
1974
1975static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
1976{
1977 dev_vdbg(dwc->dev, "%s\n", __func__);
1978
1979 /*
1980 * TODO take core out of low power mode when that's
1981 * implemented.
1982 */
1983
1984 dwc->gadget_driver->resume(&dwc->gadget);
1985}
1986
1987static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
1988 unsigned int evtinfo)
1989{
fae2b904
FB		 1990 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
1991
1992 /*
1993 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
1994 * on the link partner, the USB session might do multiple entry/exit
1995 * of low power states before a transfer takes place.
1996 *
1997 * Due to this problem, we might experience lower throughput. The
1998 * suggested workaround is to disable DCTL[12:9] bits if we're
1999 * transitioning from U1/U2 to U0 and enable those bits again
2000 * after a transfer completes and there are no pending transfers
2001 * on any of the enabled endpoints.
2002 *
2003 * This is the first half of that workaround.
2004 *
2005 * Refers to:
2006 *
2007 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2008 * core send LGO_Ux entering U0
2009 */
2010 if (dwc->revision < DWC3_REVISION_183A) {
2011 if (next == DWC3_LINK_STATE_U0) {
2012 u32 u1u2;
2013 u32 reg;
2014
2015 switch (dwc->link_state) {
2016 case DWC3_LINK_STATE_U1:
2017 case DWC3_LINK_STATE_U2:
2018 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2019 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2020 | DWC3_DCTL_ACCEPTU2ENA
2021 | DWC3_DCTL_INITU1ENA
2022 | DWC3_DCTL_ACCEPTU1ENA);
2023
2024 if (!dwc->u1u2)
2025 dwc->u1u2 = reg & u1u2;
2026
2027 reg &= ~u1u2;
2028
2029 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2030 break;
2031 default:
2032 /* do nothing */
2033 break;
2034 }
2035 }
2036 }
2037
2038 dwc->link_state = next;
019ac832
FB		 2039
2040 dev_vdbg(dwc->dev, "%s link %d\n", __func__, dwc->link_state);
72246da4
FB		 2041}
2042
2043static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2044 const struct dwc3_event_devt *event)
2045{
2046 switch (event->type) {
2047 case DWC3_DEVICE_EVENT_DISCONNECT:
2048 dwc3_gadget_disconnect_interrupt(dwc);
2049 break;
2050 case DWC3_DEVICE_EVENT_RESET:
2051 dwc3_gadget_reset_interrupt(dwc);
2052 break;
2053 case DWC3_DEVICE_EVENT_CONNECT_DONE:
2054 dwc3_gadget_conndone_interrupt(dwc);
2055 break;
2056 case DWC3_DEVICE_EVENT_WAKEUP:
2057 dwc3_gadget_wakeup_interrupt(dwc);
2058 break;
2059 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2060 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2061 break;
2062 case DWC3_DEVICE_EVENT_EOPF:
2063 dev_vdbg(dwc->dev, "End of Periodic Frame\n");
2064 break;
2065 case DWC3_DEVICE_EVENT_SOF:
2066 dev_vdbg(dwc->dev, "Start of Periodic Frame\n");
2067 break;
2068 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2069 dev_vdbg(dwc->dev, "Erratic Error\n");
2070 break;
2071 case DWC3_DEVICE_EVENT_CMD_CMPL:
2072 dev_vdbg(dwc->dev, "Command Complete\n");
2073 break;
2074 case DWC3_DEVICE_EVENT_OVERFLOW:
2075 dev_vdbg(dwc->dev, "Overflow\n");
2076 break;
2077 default:
2078 dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2079 }
2080}
2081
2082static void dwc3_process_event_entry(struct dwc3 *dwc,
2083 const union dwc3_event *event)
2084{
2085 /* Endpoint IRQ, handle it and return early */
2086 if (event->type.is_devspec == 0) {
2087 /* depevt */
2088 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2089 }
2090
2091 switch (event->type.type) {
2092 case DWC3_EVENT_TYPE_DEV:
2093 dwc3_gadget_interrupt(dwc, &event->devt);
2094 break;
2095 /* REVISIT what to do with Carkit and I2C events ? */
2096 default:
2097 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2098 }
2099}
2100
2101static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
2102{
2103 struct dwc3_event_buffer *evt;
2104 int left;
2105 u32 count;
2106
2107 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf));
2108 count &= DWC3_GEVNTCOUNT_MASK;
2109 if (!count)
2110 return IRQ_NONE;
2111
2112 evt = dwc->ev_buffs[buf];
2113 left = count;
2114
2115 while (left > 0) {
2116 union dwc3_event event;
2117
2118 memcpy(&event.raw, (evt->buf + evt->lpos), sizeof(event.raw));
2119 dwc3_process_event_entry(dwc, &event);
2120 /*
2121 * XXX we wrap around correctly to the next entry as almost all
2122 * entries are 4 bytes in size. There is one entry which has 12
2123 * bytes which is a regular entry followed by 8 bytes data. ATM
2124 * I don't know how things are organized if were get next to the
2125 * a boundary so I worry about that once we try to handle that.
2126 */
2127 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2128 left -= 4;
2129
2130 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4);
2131 }
2132
2133 return IRQ_HANDLED;
2134}
2135
2136static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
2137{
2138 struct dwc3 *dwc = _dwc;
2139 int i;
2140 irqreturn_t ret = IRQ_NONE;
2141
2142 spin_lock(&dwc->lock);
2143
9f622b2a 2144 for (i = 0; i < dwc->num_event_buffers; i++) {
72246da4
FB		 2145 irqreturn_t status;
2146
2147 status = dwc3_process_event_buf(dwc, i);
2148 if (status == IRQ_HANDLED)
2149 ret = status;
2150 }
2151
2152 spin_unlock(&dwc->lock);
2153
2154 return ret;
2155}
2156
2157/**
2158 * dwc3_gadget_init - Initializes gadget related registers
2159 * @dwc: Pointer to out controller context structure
2160 *
2161 * Returns 0 on success otherwise negative errno.
2162 */
2163int __devinit dwc3_gadget_init(struct dwc3 *dwc)
2164{
2165 u32 reg;
2166 int ret;
2167 int irq;
2168
2169 dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2170 &dwc->ctrl_req_addr, GFP_KERNEL);
2171 if (!dwc->ctrl_req) {
2172 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2173 ret = -ENOMEM;
2174 goto err0;
2175 }
2176
2177 dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2178 &dwc->ep0_trb_addr, GFP_KERNEL);
2179 if (!dwc->ep0_trb) {
2180 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2181 ret = -ENOMEM;
2182 goto err1;
2183 }
2184
2185 dwc->setup_buf = dma_alloc_coherent(dwc->dev,
2186 sizeof(*dwc->setup_buf) * 2,
2187 &dwc->setup_buf_addr, GFP_KERNEL);
2188 if (!dwc->setup_buf) {
2189 dev_err(dwc->dev, "failed to allocate setup buffer\n");
2190 ret = -ENOMEM;
2191 goto err2;
2192 }
2193
5812b1c2
FB		 2194 dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
2195 512, &dwc->ep0_bounce_addr, GFP_KERNEL);
2196 if (!dwc->ep0_bounce) {
2197 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2198 ret = -ENOMEM;
2199 goto err3;
2200 }
2201
72246da4
FB		 2202 dev_set_name(&dwc->gadget.dev, "gadget");
2203
2204 dwc->gadget.ops = &dwc3_gadget_ops;
d327ab5b 2205 dwc->gadget.max_speed = USB_SPEED_SUPER;
72246da4
FB		 2206 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2207 dwc->gadget.dev.parent = dwc->dev;
eeb720fb 2208 dwc->gadget.sg_supported = true;
72246da4
FB		 2209
2210 dma_set_coherent_mask(&dwc->gadget.dev, dwc->dev->coherent_dma_mask);
2211
2212 dwc->gadget.dev.dma_parms = dwc->dev->dma_parms;
2213 dwc->gadget.dev.dma_mask = dwc->dev->dma_mask;
2214 dwc->gadget.dev.release = dwc3_gadget_release;
2215 dwc->gadget.name = "dwc3-gadget";
2216
2217 /*
2218 * REVISIT: Here we should clear all pending IRQs to be
2219 * sure we're starting from a well known location.
2220 */
2221
2222 ret = dwc3_gadget_init_endpoints(dwc);
2223 if (ret)
5812b1c2 2224 goto err4;
72246da4
FB		 2225
2226 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
2227
2228 ret = request_irq(irq, dwc3_interrupt, IRQF_SHARED,
2229 "dwc3", dwc);
2230 if (ret) {
2231 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
2232 irq, ret);
5812b1c2 2233 goto err5;
72246da4
FB		 2234 }
2235
2236 /* Enable all but Start and End of Frame IRQs */
2237 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
2238 DWC3_DEVTEN_EVNTOVERFLOWEN |
2239 DWC3_DEVTEN_CMDCMPLTEN |
2240 DWC3_DEVTEN_ERRTICERREN |
2241 DWC3_DEVTEN_WKUPEVTEN |
2242 DWC3_DEVTEN_ULSTCNGEN |
2243 DWC3_DEVTEN_CONNECTDONEEN |
2244 DWC3_DEVTEN_USBRSTEN |
2245 DWC3_DEVTEN_DISCONNEVTEN);
2246 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
2247
2248 ret = device_register(&dwc->gadget.dev);
2249 if (ret) {
2250 dev_err(dwc->dev, "failed to register gadget device\n");
2251 put_device(&dwc->gadget.dev);
5812b1c2 2252 goto err6;
72246da4
FB		 2253 }
2254
2255 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2256 if (ret) {
2257 dev_err(dwc->dev, "failed to register udc\n");
5812b1c2 2258 goto err7;
72246da4
FB		 2259 }
2260
2261 return 0;
2262
5812b1c2 2263err7:
72246da4
FB		 2264 device_unregister(&dwc->gadget.dev);
2265
5812b1c2 2266err6:
72246da4
FB		 2267 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
2268 free_irq(irq, dwc);
2269
5812b1c2 2270err5:
72246da4
FB		 2271 dwc3_gadget_free_endpoints(dwc);
2272
5812b1c2
FB		 2273err4:
2274 dma_free_coherent(dwc->dev, 512, dwc->ep0_bounce,
2275 dwc->ep0_bounce_addr);
2276
72246da4
FB		 2277err3:
2278 dma_free_coherent(dwc->dev, sizeof(*dwc->setup_buf) * 2,
2279 dwc->setup_buf, dwc->setup_buf_addr);
2280
2281err2:
2282 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2283 dwc->ep0_trb, dwc->ep0_trb_addr);
2284
2285err1:
2286 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2287 dwc->ctrl_req, dwc->ctrl_req_addr);
2288
2289err0:
2290 return ret;
2291}
2292
2293void dwc3_gadget_exit(struct dwc3 *dwc)
2294{
2295 int irq;
72246da4
FB		 2296
2297 usb_del_gadget_udc(&dwc->gadget);
2298 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
2299
2300 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
2301 free_irq(irq, dwc);
2302
72246da4
FB		 2303 dwc3_gadget_free_endpoints(dwc);
2304
5812b1c2
FB		 2305 dma_free_coherent(dwc->dev, 512, dwc->ep0_bounce,
2306 dwc->ep0_bounce_addr);
2307
72246da4
FB		 2308 dma_free_coherent(dwc->dev, sizeof(*dwc->setup_buf) * 2,
2309 dwc->setup_buf, dwc->setup_buf_addr);
2310
2311 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2312 dwc->ep0_trb, dwc->ep0_trb_addr);
2313
2314 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2315 dwc->ctrl_req, dwc->ctrl_req_addr);
2316
2317 device_unregister(&dwc->gadget.dev);
2318}
kernel source for telekom puls (alcatel/mediatek)