projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
usb: dwc3: gadget: allow Link state changes via debugfs
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / usb / dwc3 / gadget.c
CommitLineData
72246da4
FB		 1/**
2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
72246da4
FB		 5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer,
14 * without modification.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. The names of the above-listed copyright holders may not be used
19 * to endorse or promote products derived from this software without
20 * specific prior written permission.
21 *
22 * ALTERNATIVELY, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2, as published by the Free
24 * Software Foundation.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 */
38
39#include <linux/kernel.h>
40#include <linux/delay.h>
41#include <linux/slab.h>
42#include <linux/spinlock.h>
43#include <linux/platform_device.h>
44#include <linux/pm_runtime.h>
45#include <linux/interrupt.h>
46#include <linux/io.h>
47#include <linux/list.h>
48#include <linux/dma-mapping.h>
49
50#include <linux/usb/ch9.h>
51#include <linux/usb/gadget.h>
52
53#include "core.h"
54#include "gadget.h"
55#include "io.h"
56
57#define DMA_ADDR_INVALID (~(dma_addr_t)0)
58
04a9bfcd
FB		 59/**
60 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
61 * @dwc: pointer to our context structure
62 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
63 *
64 * Caller should take care of locking. This function will
65 * return 0 on success or -EINVAL if wrong Test Selector
66 * is passed
67 */
68int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
69{
70 u32 reg;
71
72 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
73 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
74
75 switch (mode) {
76 case TEST_J:
77 case TEST_K:
78 case TEST_SE0_NAK:
79 case TEST_PACKET:
80 case TEST_FORCE_EN:
81 reg |= mode << 1;
82 break;
83 default:
84 return -EINVAL;
85 }
86
87 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
88
89 return 0;
90}
91
8598bde7
FB		 92/**
93 * dwc3_gadget_set_link_state - Sets USB Link to a particular State
94 * @dwc: pointer to our context structure
95 * @state: the state to put link into
96 *
97 * Caller should take care of locking. This function will
98 * return 0 on success or -EINVAL.
99 */
100int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
101{
102 int retries = 100;
103 u32 reg;
104
105 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
106 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
107
108 /* set requested state */
109 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
110 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
111
112 /* wait for a change in DSTS */
113 while (--retries) {
114 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
115
116 /* in HS, means ON */
117 if (DWC3_DSTS_USBLNKST(reg) == state)
118 return 0;
119
138801aa 120 udelay(500);
8598bde7
FB		 121 }
122
123 dev_vdbg(dwc->dev, "link state change request timed out\n");
124
125 return -ETIMEDOUT;
126}
127
72246da4
FB		 128void dwc3_map_buffer_to_dma(struct dwc3_request *req)
129{
130 struct dwc3 *dwc = req->dep->dwc;
131
78c58a53
SAS		 132 if (req->request.length == 0) {
133 /* req->request.dma = dwc->setup_buf_addr; */
134 return;
135 }
136
eeb720fb
FB		 137 if (req->request.num_sgs) {
138 int mapped;
139
140 mapped = dma_map_sg(dwc->dev, req->request.sg,
141 req->request.num_sgs,
142 req->direction ? DMA_TO_DEVICE
143 : DMA_FROM_DEVICE);
144 if (mapped < 0) {
145 dev_err(dwc->dev, "failed to map SGs\n");
146 return;
147 }
148
149 req->request.num_mapped_sgs = mapped;
150 return;
151 }
152
72246da4
FB		 153 if (req->request.dma == DMA_ADDR_INVALID) {
154 req->request.dma = dma_map_single(dwc->dev, req->request.buf,
155 req->request.length, req->direction
156 ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
157 req->mapped = true;
72246da4
FB		 158 }
159}
160
161void dwc3_unmap_buffer_from_dma(struct dwc3_request *req)
162{
163 struct dwc3 *dwc = req->dep->dwc;
164
78c58a53
SAS		 165 if (req->request.length == 0) {
166 req->request.dma = DMA_ADDR_INVALID;
167 return;
168 }
169
eeb720fb
FB		 170 if (req->request.num_mapped_sgs) {
171 req->request.dma = DMA_ADDR_INVALID;
172 dma_unmap_sg(dwc->dev, req->request.sg,
c09d6b51 173 req->request.num_mapped_sgs,
eeb720fb
FB		 174 req->direction ? DMA_TO_DEVICE
175 : DMA_FROM_DEVICE);
176
177 req->request.num_mapped_sgs = 0;
178 return;
179 }
180
72246da4
FB		 181 if (req->mapped) {
182 dma_unmap_single(dwc->dev, req->request.dma,
183 req->request.length, req->direction
184 ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
185 req->mapped = 0;
f198ead2 186 req->request.dma = DMA_ADDR_INVALID;
72246da4
FB		 187 }
188}
189
190void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
191 int status)
192{
193 struct dwc3 *dwc = dep->dwc;
194
195 if (req->queued) {
eeb720fb
FB		 196 if (req->request.num_mapped_sgs)
197 dep->busy_slot += req->request.num_mapped_sgs;
198 else
199 dep->busy_slot++;
200
72246da4
FB		 201 /*
202 * Skip LINK TRB. We can't use req->trb and check for
203 * DWC3_TRBCTL_LINK_TRB because it points the TRB we just
204 * completed (not the LINK TRB).
205 */
206 if (((dep->busy_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
207 usb_endpoint_xfer_isoc(dep->desc))
208 dep->busy_slot++;
209 }
210 list_del(&req->list);
eeb720fb 211 req->trb = NULL;
72246da4
FB		 212
213 if (req->request.status == -EINPROGRESS)
214 req->request.status = status;
215
216 dwc3_unmap_buffer_from_dma(req);
217
218 dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n",
219 req, dep->name, req->request.actual,
220 req->request.length, status);
221
222 spin_unlock(&dwc->lock);
223 req->request.complete(&req->dep->endpoint, &req->request);
224 spin_lock(&dwc->lock);
225}
226
227static const char *dwc3_gadget_ep_cmd_string(u8 cmd)
228{
229 switch (cmd) {
230 case DWC3_DEPCMD_DEPSTARTCFG:
231 return "Start New Configuration";
232 case DWC3_DEPCMD_ENDTRANSFER:
233 return "End Transfer";
234 case DWC3_DEPCMD_UPDATETRANSFER:
235 return "Update Transfer";
236 case DWC3_DEPCMD_STARTTRANSFER:
237 return "Start Transfer";
238 case DWC3_DEPCMD_CLEARSTALL:
239 return "Clear Stall";
240 case DWC3_DEPCMD_SETSTALL:
241 return "Set Stall";
242 case DWC3_DEPCMD_GETSEQNUMBER:
243 return "Get Data Sequence Number";
244 case DWC3_DEPCMD_SETTRANSFRESOURCE:
245 return "Set Endpoint Transfer Resource";
246 case DWC3_DEPCMD_SETEPCONFIG:
247 return "Set Endpoint Configuration";
248 default:
249 return "UNKNOWN command";
250 }
251}
252
253int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
254 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
255{
256 struct dwc3_ep *dep = dwc->eps[ep];
61d58242 257 u32 timeout = 500;
72246da4
FB		 258 u32 reg;
259
260 dev_vdbg(dwc->dev, "%s: cmd '%s' params %08x %08x %08x\n",
261 dep->name,
dc1c70a7
FB		 262 dwc3_gadget_ep_cmd_string(cmd), params->param0,
263 params->param1, params->param2);
72246da4 264
dc1c70a7
FB		 265 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
266 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
267 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
72246da4
FB		 268
269 dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
270 do {
271 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
272 if (!(reg & DWC3_DEPCMD_CMDACT)) {
164f6e14
FB		 273 dev_vdbg(dwc->dev, "Command Complete --> %d\n",
274 DWC3_DEPCMD_STATUS(reg));
72246da4
FB		 275 return 0;
276 }
277
278 /*
72246da4
FB		 279 * We can't sleep here, because it is also called from
280 * interrupt context.
281 */
282 timeout--;
283 if (!timeout)
284 return -ETIMEDOUT;
285
61d58242 286 udelay(1);
72246da4
FB		 287 } while (1);
288}
289
290static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
291 struct dwc3_trb_hw *trb)
292{
c439ef87 293 u32 offset = (char *) trb - (char *) dep->trb_pool;
72246da4
FB		 294
295 return dep->trb_pool_dma + offset;
296}
297
298static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
299{
300 struct dwc3 *dwc = dep->dwc;
301
302 if (dep->trb_pool)
303 return 0;
304
305 if (dep->number == 0 || dep->number == 1)
306 return 0;
307
308 dep->trb_pool = dma_alloc_coherent(dwc->dev,
309 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
310 &dep->trb_pool_dma, GFP_KERNEL);
311 if (!dep->trb_pool) {
312 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
313 dep->name);
314 return -ENOMEM;
315 }
316
317 return 0;
318}
319
320static void dwc3_free_trb_pool(struct dwc3_ep *dep)
321{
322 struct dwc3 *dwc = dep->dwc;
323
324 dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
325 dep->trb_pool, dep->trb_pool_dma);
326
327 dep->trb_pool = NULL;
328 dep->trb_pool_dma = 0;
329}
330
331static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
332{
333 struct dwc3_gadget_ep_cmd_params params;
334 u32 cmd;
335
336 memset(&params, 0x00, sizeof(params));
337
338 if (dep->number != 1) {
339 cmd = DWC3_DEPCMD_DEPSTARTCFG;
340 /* XferRscIdx == 0 for ep0 and 2 for the remaining */
b23c8439
PZ		 341 if (dep->number > 1) {
342 if (dwc->start_config_issued)
343 return 0;
344 dwc->start_config_issued = true;
72246da4 345 cmd |= DWC3_DEPCMD_PARAM(2);
b23c8439 346 }
72246da4
FB		 347
348 return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, &params);
349 }
350
351 return 0;
352}
353
354static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
c90bfaec
FB		 355 const struct usb_endpoint_descriptor *desc,
356 const struct usb_ss_ep_comp_descriptor *comp_desc)
72246da4
FB		 357{
358 struct dwc3_gadget_ep_cmd_params params;
359
360 memset(&params, 0x00, sizeof(params));
361
dc1c70a7
FB		 362 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
363 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc))
364 | DWC3_DEPCFG_BURST_SIZE(dep->endpoint.maxburst);
72246da4 365
dc1c70a7
FB		 366 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
367 | DWC3_DEPCFG_XFER_NOT_READY_EN;
72246da4 368
18b7ede5 369 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
dc1c70a7
FB		 370 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
371 | DWC3_DEPCFG_STREAM_EVENT_EN;
879631aa
FB		 372 dep->stream_capable = true;
373 }
374
72246da4 375 if (usb_endpoint_xfer_isoc(desc))
dc1c70a7 376 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
72246da4
FB		 377
378 /*
379 * We are doing 1:1 mapping for endpoints, meaning
380 * Physical Endpoints 2 maps to Logical Endpoint 2 and
381 * so on. We consider the direction bit as part of the physical
382 * endpoint number. So USB endpoint 0x81 is 0x03.
383 */
dc1c70a7 384 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
72246da4
FB		 385
386 /*
387 * We must use the lower 16 TX FIFOs even though
388 * HW might have more
389 */
390 if (dep->direction)
dc1c70a7 391 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
72246da4
FB		 392
393 if (desc->bInterval) {
dc1c70a7 394 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
72246da4
FB		 395 dep->interval = 1 << (desc->bInterval - 1);
396 }
397
398 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
399 DWC3_DEPCMD_SETEPCONFIG, &params);
400}
401
402static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
403{
404 struct dwc3_gadget_ep_cmd_params params;
405
406 memset(&params, 0x00, sizeof(params));
407
dc1c70a7 408 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
72246da4
FB		 409
410 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
411 DWC3_DEPCMD_SETTRANSFRESOURCE, &params);
412}
413
414/**
415 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
416 * @dep: endpoint to be initialized
417 * @desc: USB Endpoint Descriptor
418 *
419 * Caller should take care of locking
420 */
421static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
c90bfaec
FB		 422 const struct usb_endpoint_descriptor *desc,
423 const struct usb_ss_ep_comp_descriptor *comp_desc)
72246da4
FB		 424{
425 struct dwc3 *dwc = dep->dwc;
426 u32 reg;
427 int ret = -ENOMEM;
428
429 if (!(dep->flags & DWC3_EP_ENABLED)) {
430 ret = dwc3_gadget_start_config(dwc, dep);
431 if (ret)
432 return ret;
433 }
434
c90bfaec 435 ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc);
72246da4
FB		 436 if (ret)
437 return ret;
438
439 if (!(dep->flags & DWC3_EP_ENABLED)) {
440 struct dwc3_trb_hw *trb_st_hw;
441 struct dwc3_trb_hw *trb_link_hw;
442 struct dwc3_trb trb_link;
443
444 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
445 if (ret)
446 return ret;
447
448 dep->desc = desc;
c90bfaec 449 dep->comp_desc = comp_desc;
72246da4
FB		 450 dep->type = usb_endpoint_type(desc);
451 dep->flags |= DWC3_EP_ENABLED;
452
453 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
454 reg |= DWC3_DALEPENA_EP(dep->number);
455 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
456
457 if (!usb_endpoint_xfer_isoc(desc))
458 return 0;
459
460 memset(&trb_link, 0, sizeof(trb_link));
461
462 /* Link TRB for ISOC. The HWO but is never reset */
463 trb_st_hw = &dep->trb_pool[0];
464
465 trb_link.bplh = dwc3_trb_dma_offset(dep, trb_st_hw);
466 trb_link.trbctl = DWC3_TRBCTL_LINK_TRB;
467 trb_link.hwo = true;
468
469 trb_link_hw = &dep->trb_pool[DWC3_TRB_NUM - 1];
470 dwc3_trb_to_hw(&trb_link, trb_link_hw);
471 }
472
473 return 0;
474}
475
624407f9
SAS		 476static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum);
477static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
72246da4
FB		 478{
479 struct dwc3_request *req;
480
624407f9
SAS		 481 if (!list_empty(&dep->req_queued))
482 dwc3_stop_active_transfer(dwc, dep->number);
483
72246da4
FB		 484 while (!list_empty(&dep->request_list)) {
485 req = next_request(&dep->request_list);
486
624407f9 487 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
72246da4 488 }
72246da4
FB		 489}
490
491/**
492 * __dwc3_gadget_ep_disable - Disables a HW endpoint
493 * @dep: the endpoint to disable
494 *
624407f9
SAS		 495 * This function also removes requests which are currently processed ny the
496 * hardware and those which are not yet scheduled.
497 * Caller should take care of locking.
72246da4 498 */
72246da4
FB		 499static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
500{
501 struct dwc3 *dwc = dep->dwc;
502 u32 reg;
503
624407f9 504 dwc3_remove_requests(dwc, dep);
72246da4
FB		 505
506 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
507 reg &= ~DWC3_DALEPENA_EP(dep->number);
508 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
509
879631aa 510 dep->stream_capable = false;
72246da4 511 dep->desc = NULL;
c90bfaec 512 dep->comp_desc = NULL;
72246da4 513 dep->type = 0;
879631aa 514 dep->flags = 0;
72246da4
FB		 515
516 return 0;
517}
518
519/* -------------------------------------------------------------------------- */
520
521static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
522 const struct usb_endpoint_descriptor *desc)
523{
524 return -EINVAL;
525}
526
527static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
528{
529 return -EINVAL;
530}
531
532/* -------------------------------------------------------------------------- */
533
534static int dwc3_gadget_ep_enable(struct usb_ep *ep,
535 const struct usb_endpoint_descriptor *desc)
536{
537 struct dwc3_ep *dep;
538 struct dwc3 *dwc;
539 unsigned long flags;
540 int ret;
541
542 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
543 pr_debug("dwc3: invalid parameters\n");
544 return -EINVAL;
545 }
546
547 if (!desc->wMaxPacketSize) {
548 pr_debug("dwc3: missing wMaxPacketSize\n");
549 return -EINVAL;
550 }
551
552 dep = to_dwc3_ep(ep);
553 dwc = dep->dwc;
554
555 switch (usb_endpoint_type(desc)) {
556 case USB_ENDPOINT_XFER_CONTROL:
557 strncat(dep->name, "-control", sizeof(dep->name));
558 break;
559 case USB_ENDPOINT_XFER_ISOC:
560 strncat(dep->name, "-isoc", sizeof(dep->name));
561 break;
562 case USB_ENDPOINT_XFER_BULK:
563 strncat(dep->name, "-bulk", sizeof(dep->name));
564 break;
565 case USB_ENDPOINT_XFER_INT:
566 strncat(dep->name, "-int", sizeof(dep->name));
567 break;
568 default:
569 dev_err(dwc->dev, "invalid endpoint transfer type\n");
570 }
571
572 if (dep->flags & DWC3_EP_ENABLED) {
573 dev_WARN_ONCE(dwc->dev, true, "%s is already enabled\n",
574 dep->name);
575 return 0;
576 }
577
578 dev_vdbg(dwc->dev, "Enabling %s\n", dep->name);
579
580 spin_lock_irqsave(&dwc->lock, flags);
c90bfaec 581 ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc);
72246da4
FB		 582 spin_unlock_irqrestore(&dwc->lock, flags);
583
584 return ret;
585}
586
587static int dwc3_gadget_ep_disable(struct usb_ep *ep)
588{
589 struct dwc3_ep *dep;
590 struct dwc3 *dwc;
591 unsigned long flags;
592 int ret;
593
594 if (!ep) {
595 pr_debug("dwc3: invalid parameters\n");
596 return -EINVAL;
597 }
598
599 dep = to_dwc3_ep(ep);
600 dwc = dep->dwc;
601
602 if (!(dep->flags & DWC3_EP_ENABLED)) {
603 dev_WARN_ONCE(dwc->dev, true, "%s is already disabled\n",
604 dep->name);
605 return 0;
606 }
607
608 snprintf(dep->name, sizeof(dep->name), "ep%d%s",
609 dep->number >> 1,
610 (dep->number & 1) ? "in" : "out");
611
612 spin_lock_irqsave(&dwc->lock, flags);
613 ret = __dwc3_gadget_ep_disable(dep);
614 spin_unlock_irqrestore(&dwc->lock, flags);
615
616 return ret;
617}
618
619static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
620 gfp_t gfp_flags)
621{
622 struct dwc3_request *req;
623 struct dwc3_ep *dep = to_dwc3_ep(ep);
624 struct dwc3 *dwc = dep->dwc;
625
626 req = kzalloc(sizeof(*req), gfp_flags);
627 if (!req) {
628 dev_err(dwc->dev, "not enough memory\n");
629 return NULL;
630 }
631
632 req->epnum = dep->number;
633 req->dep = dep;
634 req->request.dma = DMA_ADDR_INVALID;
635
636 return &req->request;
637}
638
639static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
640 struct usb_request *request)
641{
642 struct dwc3_request *req = to_dwc3_request(request);
643
644 kfree(req);
645}
646
c71fc37c
FB		 647/**
648 * dwc3_prepare_one_trb - setup one TRB from one request
649 * @dep: endpoint for which this request is prepared
650 * @req: dwc3_request pointer
651 */
68e823e2 652static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
eeb720fb
FB		 653 struct dwc3_request *req, dma_addr_t dma,
654 unsigned length, unsigned last, unsigned chain)
c71fc37c 655{
eeb720fb 656 struct dwc3 *dwc = dep->dwc;
c71fc37c
FB		 657 struct dwc3_trb_hw *trb_hw;
658 struct dwc3_trb trb;
659
660 unsigned int cur_slot;
661
eeb720fb
FB		 662 dev_vdbg(dwc->dev, "%s: req %p dma %08llx length %d%s%s\n",
663 dep->name, req, (unsigned long long) dma,
664 length, last ? " last" : "",
665 chain ? " chain" : "");
666
c71fc37c
FB		 667 trb_hw = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
668 cur_slot = dep->free_slot;
669 dep->free_slot++;
670
671 /* Skip the LINK-TRB on ISOC */
672 if (((cur_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
673 usb_endpoint_xfer_isoc(dep->desc))
68e823e2 674 return;
c71fc37c 675
c71fc37c 676 memset(&trb, 0, sizeof(trb));
eeb720fb
FB		 677 if (!req->trb) {
678 dwc3_gadget_move_request_queued(req);
679 req->trb = trb_hw;
680 req->trb_dma = dwc3_trb_dma_offset(dep, trb_hw);
681 }
c71fc37c
FB		 682
683 if (usb_endpoint_xfer_isoc(dep->desc)) {
684 trb.isp_imi = true;
685 trb.csp = true;
686 } else {
eeb720fb 687 trb.chn = chain;
c71fc37c
FB		 688 trb.lst = last;
689 }
690
691 if (usb_endpoint_xfer_bulk(dep->desc) && dep->stream_capable)
692 trb.sid_sofn = req->request.stream_id;
693
694 switch (usb_endpoint_type(dep->desc)) {
695 case USB_ENDPOINT_XFER_CONTROL:
696 trb.trbctl = DWC3_TRBCTL_CONTROL_SETUP;
697 break;
698
699 case USB_ENDPOINT_XFER_ISOC:
700 trb.trbctl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
701
702 /* IOC every DWC3_TRB_NUM / 4 so we can refill */
703 if (!(cur_slot % (DWC3_TRB_NUM / 4)))
704 trb.ioc = last;
705 break;
706
707 case USB_ENDPOINT_XFER_BULK:
708 case USB_ENDPOINT_XFER_INT:
709 trb.trbctl = DWC3_TRBCTL_NORMAL;
710 break;
711 default:
712 /*
713 * This is only possible with faulty memory because we
714 * checked it already :)
715 */
716 BUG();
717 }
718
eeb720fb
FB		 719 trb.length = length;
720 trb.bplh = dma;
c71fc37c
FB		 721 trb.hwo = true;
722
723 dwc3_trb_to_hw(&trb, trb_hw);
c71fc37c
FB		 724}
725
72246da4
FB		 726/*
727 * dwc3_prepare_trbs - setup TRBs from requests
728 * @dep: endpoint for which requests are being prepared
729 * @starting: true if the endpoint is idle and no requests are queued.
730 *
731 * The functions goes through the requests list and setups TRBs for the
732 * transfers. The functions returns once there are not more TRBs available or
733 * it run out of requests.
734 */
68e823e2 735static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
72246da4 736{
68e823e2 737 struct dwc3_request *req, *n;
72246da4 738 u32 trbs_left;
c71fc37c 739 unsigned int last_one = 0;
72246da4
FB		 740
741 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
742
743 /* the first request must not be queued */
744 trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
c71fc37c 745
72246da4
FB		 746 /*
747 * if busy & slot are equal than it is either full or empty. If we are
748 * starting to proceed requests then we are empty. Otherwise we ar
749 * full and don't do anything
750 */
751 if (!trbs_left) {
752 if (!starting)
68e823e2 753 return;
72246da4
FB		 754 trbs_left = DWC3_TRB_NUM;
755 /*
756 * In case we start from scratch, we queue the ISOC requests
757 * starting from slot 1. This is done because we use ring
758 * buffer and have no LST bit to stop us. Instead, we place
759 * IOC bit TRB_NUM/4. We try to avoid to having an interrupt
760 * after the first request so we start at slot 1 and have
761 * 7 requests proceed before we hit the first IOC.
762 * Other transfer types don't use the ring buffer and are
763 * processed from the first TRB until the last one. Since we
764 * don't wrap around we have to start at the beginning.
765 */
766 if (usb_endpoint_xfer_isoc(dep->desc)) {
767 dep->busy_slot = 1;
768 dep->free_slot = 1;
769 } else {
770 dep->busy_slot = 0;
771 dep->free_slot = 0;
772 }
773 }
774
775 /* The last TRB is a link TRB, not used for xfer */
776 if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->desc))
68e823e2 777 return;
72246da4
FB		 778
779 list_for_each_entry_safe(req, n, &dep->request_list, list) {
eeb720fb
FB		 780 unsigned length;
781 dma_addr_t dma;
72246da4 782
eeb720fb
FB		 783 if (req->request.num_mapped_sgs > 0) {
784 struct usb_request *request = &req->request;
785 struct scatterlist *sg = request->sg;
786 struct scatterlist *s;
787 int i;
72246da4 788
eeb720fb
FB		 789 for_each_sg(sg, s, request->num_mapped_sgs, i) {
790 unsigned chain = true;
72246da4 791
eeb720fb
FB		 792 length = sg_dma_len(s);
793 dma = sg_dma_address(s);
72246da4 794
eeb720fb
FB		 795 if (i == (request->num_mapped_sgs - 1)
796 || sg_is_last(s)) {
797 last_one = true;
798 chain = false;
799 }
72246da4 800
eeb720fb
FB		 801 trbs_left--;
802 if (!trbs_left)
803 last_one = true;
72246da4 804
eeb720fb
FB		 805 if (last_one)
806 chain = false;
72246da4 807
eeb720fb
FB		 808 dwc3_prepare_one_trb(dep, req, dma, length,
809 last_one, chain);
72246da4 810
eeb720fb
FB		 811 if (last_one)
812 break;
813 }
72246da4 814 } else {
eeb720fb
FB		 815 dma = req->request.dma;
816 length = req->request.length;
817 trbs_left--;
72246da4 818
eeb720fb
FB		 819 if (!trbs_left)
820 last_one = 1;
879631aa 821
eeb720fb
FB		 822 /* Is this the last request? */
823 if (list_is_last(&req->list, &dep->request_list))
824 last_one = 1;
72246da4 825
eeb720fb
FB		 826 dwc3_prepare_one_trb(dep, req, dma, length,
827 last_one, false);
72246da4 828
eeb720fb
FB		 829 if (last_one)
830 break;
72246da4 831 }
72246da4 832 }
72246da4
FB		 833}
834
835static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
836 int start_new)
837{
838 struct dwc3_gadget_ep_cmd_params params;
839 struct dwc3_request *req;
840 struct dwc3 *dwc = dep->dwc;
841 int ret;
842 u32 cmd;
843
844 if (start_new && (dep->flags & DWC3_EP_BUSY)) {
845 dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name);
846 return -EBUSY;
847 }
848 dep->flags &= ~DWC3_EP_PENDING_REQUEST;
849
850 /*
851 * If we are getting here after a short-out-packet we don't enqueue any
852 * new requests as we try to set the IOC bit only on the last request.
853 */
854 if (start_new) {
855 if (list_empty(&dep->req_queued))
856 dwc3_prepare_trbs(dep, start_new);
857
858 /* req points to the first request which will be sent */
859 req = next_request(&dep->req_queued);
860 } else {
68e823e2
FB		 861 dwc3_prepare_trbs(dep, start_new);
862
72246da4
FB		 863 /*
864 * req points to the first request where HWO changed
865 * from 0 to 1
866 */
68e823e2 867 req = next_request(&dep->req_queued);
72246da4
FB		 868 }
869 if (!req) {
870 dep->flags |= DWC3_EP_PENDING_REQUEST;
871 return 0;
872 }
873
874 memset(&params, 0, sizeof(params));
dc1c70a7
FB		 875 params.param0 = upper_32_bits(req->trb_dma);
876 params.param1 = lower_32_bits(req->trb_dma);
72246da4
FB		 877
878 if (start_new)
879 cmd = DWC3_DEPCMD_STARTTRANSFER;
880 else
881 cmd = DWC3_DEPCMD_UPDATETRANSFER;
882
883 cmd |= DWC3_DEPCMD_PARAM(cmd_param);
884 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
885 if (ret < 0) {
886 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
887
888 /*
889 * FIXME we need to iterate over the list of requests
890 * here and stop, unmap, free and del each of the linked
891 * requests instead of we do now.
892 */
893 dwc3_unmap_buffer_from_dma(req);
894 list_del(&req->list);
895 return ret;
896 }
897
898 dep->flags |= DWC3_EP_BUSY;
899 dep->res_trans_idx = dwc3_gadget_ep_get_transfer_index(dwc,
900 dep->number);
25b8ff68
FB		 901
902 WARN_ON_ONCE(!dep->res_trans_idx);
903
72246da4
FB		 904 return 0;
905}
906
907static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
908{
909 req->request.actual = 0;
910 req->request.status = -EINPROGRESS;
911 req->direction = dep->direction;
912 req->epnum = dep->number;
913
914 /*
915 * We only add to our list of requests now and
916 * start consuming the list once we get XferNotReady
917 * IRQ.
918 *
919 * That way, we avoid doing anything that we don't need
920 * to do now and defer it until the point we receive a
921 * particular token from the Host side.
922 *
923 * This will also avoid Host cancelling URBs due to too
924 * many NACKs.
925 */
926 dwc3_map_buffer_to_dma(req);
927 list_add_tail(&req->list, &dep->request_list);
928
929 /*
930 * There is one special case: XferNotReady with
931 * empty list of requests. We need to kick the
932 * transfer here in that situation, otherwise
933 * we will be NAKing forever.
934 *
935 * If we get XferNotReady before gadget driver
936 * has a chance to queue a request, we will ACK
937 * the IRQ but won't be able to receive the data
938 * until the next request is queued. The following
939 * code is handling exactly that.
940 */
941 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
942 int ret;
943 int start_trans;
944
945 start_trans = 1;
946 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
947 dep->flags & DWC3_EP_BUSY)
948 start_trans = 0;
949
950 ret = __dwc3_gadget_kick_transfer(dep, 0, start_trans);
951 if (ret && ret != -EBUSY) {
952 struct dwc3 *dwc = dep->dwc;
953
954 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
955 dep->name);
956 }
957 };
958
959 return 0;
960}
961
962static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
963 gfp_t gfp_flags)
964{
965 struct dwc3_request *req = to_dwc3_request(request);
966 struct dwc3_ep *dep = to_dwc3_ep(ep);
967 struct dwc3 *dwc = dep->dwc;
968
969 unsigned long flags;
970
971 int ret;
972
973 if (!dep->desc) {
974 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
975 request, ep->name);
976 return -ESHUTDOWN;
977 }
978
979 dev_vdbg(dwc->dev, "queing request %p to %s length %d\n",
980 request, ep->name, request->length);
981
982 spin_lock_irqsave(&dwc->lock, flags);
983 ret = __dwc3_gadget_ep_queue(dep, req);
984 spin_unlock_irqrestore(&dwc->lock, flags);
985
986 return ret;
987}
988
989static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
990 struct usb_request *request)
991{
992 struct dwc3_request *req = to_dwc3_request(request);
993 struct dwc3_request *r = NULL;
994
995 struct dwc3_ep *dep = to_dwc3_ep(ep);
996 struct dwc3 *dwc = dep->dwc;
997
998 unsigned long flags;
999 int ret = 0;
1000
1001 spin_lock_irqsave(&dwc->lock, flags);
1002
1003 list_for_each_entry(r, &dep->request_list, list) {
1004 if (r == req)
1005 break;
1006 }
1007
1008 if (r != req) {
1009 list_for_each_entry(r, &dep->req_queued, list) {
1010 if (r == req)
1011 break;
1012 }
1013 if (r == req) {
1014 /* wait until it is processed */
1015 dwc3_stop_active_transfer(dwc, dep->number);
1016 goto out0;
1017 }
1018 dev_err(dwc->dev, "request %p was not queued to %s\n",
1019 request, ep->name);
1020 ret = -EINVAL;
1021 goto out0;
1022 }
1023
1024 /* giveback the request */
1025 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1026
1027out0:
1028 spin_unlock_irqrestore(&dwc->lock, flags);
1029
1030 return ret;
1031}
1032
1033int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value)
1034{
1035 struct dwc3_gadget_ep_cmd_params params;
1036 struct dwc3 *dwc = dep->dwc;
1037 int ret;
1038
1039 memset(&params, 0x00, sizeof(params));
1040
1041 if (value) {
0b7836a9
FB		 1042 if (dep->number == 0 || dep->number == 1) {
1043 /*
1044 * Whenever EP0 is stalled, we will restart
1045 * the state machine, thus moving back to
1046 * Setup Phase
1047 */
1048 dwc->ep0state = EP0_SETUP_PHASE;
1049 }
72246da4
FB		 1050
1051 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1052 DWC3_DEPCMD_SETSTALL, &params);
1053 if (ret)
1054 dev_err(dwc->dev, "failed to %s STALL on %s\n",
1055 value ? "set" : "clear",
1056 dep->name);
1057 else
1058 dep->flags |= DWC3_EP_STALL;
1059 } else {
5275455a
PZ		 1060 if (dep->flags & DWC3_EP_WEDGE)
1061 return 0;
1062
72246da4
FB		 1063 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1064 DWC3_DEPCMD_CLEARSTALL, &params);
1065 if (ret)
1066 dev_err(dwc->dev, "failed to %s STALL on %s\n",
1067 value ? "set" : "clear",
1068 dep->name);
1069 else
1070 dep->flags &= ~DWC3_EP_STALL;
1071 }
5275455a 1072
72246da4
FB		 1073 return ret;
1074}
1075
1076static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1077{
1078 struct dwc3_ep *dep = to_dwc3_ep(ep);
1079 struct dwc3 *dwc = dep->dwc;
1080
1081 unsigned long flags;
1082
1083 int ret;
1084
1085 spin_lock_irqsave(&dwc->lock, flags);
1086
1087 if (usb_endpoint_xfer_isoc(dep->desc)) {
1088 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1089 ret = -EINVAL;
1090 goto out;
1091 }
1092
1093 ret = __dwc3_gadget_ep_set_halt(dep, value);
1094out:
1095 spin_unlock_irqrestore(&dwc->lock, flags);
1096
1097 return ret;
1098}
1099
1100static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1101{
1102 struct dwc3_ep *dep = to_dwc3_ep(ep);
1103
1104 dep->flags |= DWC3_EP_WEDGE;
1105
5275455a 1106 return dwc3_gadget_ep_set_halt(ep, 1);
72246da4
FB		 1107}
1108
1109/* -------------------------------------------------------------------------- */
1110
1111static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1112 .bLength = USB_DT_ENDPOINT_SIZE,
1113 .bDescriptorType = USB_DT_ENDPOINT,
1114 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1115};
1116
1117static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1118 .enable = dwc3_gadget_ep0_enable,
1119 .disable = dwc3_gadget_ep0_disable,
1120 .alloc_request = dwc3_gadget_ep_alloc_request,
1121 .free_request = dwc3_gadget_ep_free_request,
1122 .queue = dwc3_gadget_ep0_queue,
1123 .dequeue = dwc3_gadget_ep_dequeue,
1124 .set_halt = dwc3_gadget_ep_set_halt,
1125 .set_wedge = dwc3_gadget_ep_set_wedge,
1126};
1127
1128static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1129 .enable = dwc3_gadget_ep_enable,
1130 .disable = dwc3_gadget_ep_disable,
1131 .alloc_request = dwc3_gadget_ep_alloc_request,
1132 .free_request = dwc3_gadget_ep_free_request,
1133 .queue = dwc3_gadget_ep_queue,
1134 .dequeue = dwc3_gadget_ep_dequeue,
1135 .set_halt = dwc3_gadget_ep_set_halt,
1136 .set_wedge = dwc3_gadget_ep_set_wedge,
1137};
1138
1139/* -------------------------------------------------------------------------- */
1140
1141static int dwc3_gadget_get_frame(struct usb_gadget *g)
1142{
1143 struct dwc3 *dwc = gadget_to_dwc(g);
1144 u32 reg;
1145
1146 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1147 return DWC3_DSTS_SOFFN(reg);
1148}
1149
1150static int dwc3_gadget_wakeup(struct usb_gadget *g)
1151{
1152 struct dwc3 *dwc = gadget_to_dwc(g);
1153
1154 unsigned long timeout;
1155 unsigned long flags;
1156
1157 u32 reg;
1158
1159 int ret = 0;
1160
1161 u8 link_state;
1162 u8 speed;
1163
1164 spin_lock_irqsave(&dwc->lock, flags);
1165
1166 /*
1167 * According to the Databook Remote wakeup request should
1168 * be issued only when the device is in early suspend state.
1169 *
1170 * We can check that via USB Link State bits in DSTS register.
1171 */
1172 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1173
1174 speed = reg & DWC3_DSTS_CONNECTSPD;
1175 if (speed == DWC3_DSTS_SUPERSPEED) {
1176 dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n");
1177 ret = -EINVAL;
1178 goto out;
1179 }
1180
1181 link_state = DWC3_DSTS_USBLNKST(reg);
1182
1183 switch (link_state) {
1184 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1185 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1186 break;
1187 default:
1188 dev_dbg(dwc->dev, "can't wakeup from link state %d\n",
1189 link_state);
1190 ret = -EINVAL;
1191 goto out;
1192 }
1193
8598bde7
FB		 1194 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1195 if (ret < 0) {
1196 dev_err(dwc->dev, "failed to put link in Recovery\n");
1197 goto out;
1198 }
72246da4
FB		 1199
1200 /* write zeroes to Link Change Request */
1201 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1202 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1203
1204 /* pool until Link State change to ON */
1205 timeout = jiffies + msecs_to_jiffies(100);
1206
1207 while (!(time_after(jiffies, timeout))) {
1208 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1209
1210 /* in HS, means ON */
1211 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1212 break;
1213 }
1214
1215 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1216 dev_err(dwc->dev, "failed to send remote wakeup\n");
1217 ret = -EINVAL;
1218 }
1219
1220out:
1221 spin_unlock_irqrestore(&dwc->lock, flags);
1222
1223 return ret;
1224}
1225
1226static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1227 int is_selfpowered)
1228{
1229 struct dwc3 *dwc = gadget_to_dwc(g);
1230
1231 dwc->is_selfpowered = !!is_selfpowered;
1232
1233 return 0;
1234}
1235
1236static void dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on)
1237{
1238 u32 reg;
61d58242 1239 u32 timeout = 500;
72246da4
FB		 1240
1241 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1242 if (is_on)
1243 reg |= DWC3_DCTL_RUN_STOP;
1244 else
1245 reg &= ~DWC3_DCTL_RUN_STOP;
1246
1247 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1248
1249 do {
1250 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1251 if (is_on) {
1252 if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1253 break;
1254 } else {
1255 if (reg & DWC3_DSTS_DEVCTRLHLT)
1256 break;
1257 }
72246da4
FB		 1258 timeout--;
1259 if (!timeout)
1260 break;
61d58242 1261 udelay(1);
72246da4
FB		 1262 } while (1);
1263
1264 dev_vdbg(dwc->dev, "gadget %s data soft-%s\n",
1265 dwc->gadget_driver
1266 ? dwc->gadget_driver->function : "no-function",
1267 is_on ? "connect" : "disconnect");
1268}
1269
1270static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1271{
1272 struct dwc3 *dwc = gadget_to_dwc(g);
1273 unsigned long flags;
1274
1275 is_on = !!is_on;
1276
1277 spin_lock_irqsave(&dwc->lock, flags);
1278 dwc3_gadget_run_stop(dwc, is_on);
1279 spin_unlock_irqrestore(&dwc->lock, flags);
1280
1281 return 0;
1282}
1283
1284static int dwc3_gadget_start(struct usb_gadget *g,
1285 struct usb_gadget_driver *driver)
1286{
1287 struct dwc3 *dwc = gadget_to_dwc(g);
1288 struct dwc3_ep *dep;
1289 unsigned long flags;
1290 int ret = 0;
1291 u32 reg;
1292
1293 spin_lock_irqsave(&dwc->lock, flags);
1294
1295 if (dwc->gadget_driver) {
1296 dev_err(dwc->dev, "%s is already bound to %s\n",
1297 dwc->gadget.name,
1298 dwc->gadget_driver->driver.name);
1299 ret = -EBUSY;
1300 goto err0;
1301 }
1302
1303 dwc->gadget_driver = driver;
1304 dwc->gadget.dev.driver = &driver->driver;
1305
72246da4
FB		 1306 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1307 reg &= ~(DWC3_DCFG_SPEED_MASK);
6c167fc9 1308 reg |= dwc->maximum_speed;
72246da4
FB		 1309 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1310
b23c8439
PZ		 1311 dwc->start_config_issued = false;
1312
72246da4
FB		 1313 /* Start with SuperSpeed Default */
1314 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1315
1316 dep = dwc->eps[0];
c90bfaec 1317 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL);
72246da4
FB		 1318 if (ret) {
1319 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1320 goto err0;
1321 }
1322
1323 dep = dwc->eps[1];
c90bfaec 1324 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL);
72246da4
FB		 1325 if (ret) {
1326 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1327 goto err1;
1328 }
1329
1330 /* begin to receive SETUP packets */
c7fcdeb2 1331 dwc->ep0state = EP0_SETUP_PHASE;
72246da4
FB		 1332 dwc3_ep0_out_start(dwc);
1333
1334 spin_unlock_irqrestore(&dwc->lock, flags);
1335
1336 return 0;
1337
1338err1:
1339 __dwc3_gadget_ep_disable(dwc->eps[0]);
1340
1341err0:
1342 spin_unlock_irqrestore(&dwc->lock, flags);
1343
1344 return ret;
1345}
1346
1347static int dwc3_gadget_stop(struct usb_gadget *g,
1348 struct usb_gadget_driver *driver)
1349{
1350 struct dwc3 *dwc = gadget_to_dwc(g);
1351 unsigned long flags;
1352
1353 spin_lock_irqsave(&dwc->lock, flags);
1354
1355 __dwc3_gadget_ep_disable(dwc->eps[0]);
1356 __dwc3_gadget_ep_disable(dwc->eps[1]);
1357
1358 dwc->gadget_driver = NULL;
1359 dwc->gadget.dev.driver = NULL;
1360
1361 spin_unlock_irqrestore(&dwc->lock, flags);
1362
1363 return 0;
1364}
1365static const struct usb_gadget_ops dwc3_gadget_ops = {
1366 .get_frame = dwc3_gadget_get_frame,
1367 .wakeup = dwc3_gadget_wakeup,
1368 .set_selfpowered = dwc3_gadget_set_selfpowered,
1369 .pullup = dwc3_gadget_pullup,
1370 .udc_start = dwc3_gadget_start,
1371 .udc_stop = dwc3_gadget_stop,
1372};
1373
1374/* -------------------------------------------------------------------------- */
1375
1376static int __devinit dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1377{
1378 struct dwc3_ep *dep;
1379 u8 epnum;
1380
1381 INIT_LIST_HEAD(&dwc->gadget.ep_list);
1382
1383 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1384 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1385 if (!dep) {
1386 dev_err(dwc->dev, "can't allocate endpoint %d\n",
1387 epnum);
1388 return -ENOMEM;
1389 }
1390
1391 dep->dwc = dwc;
1392 dep->number = epnum;
1393 dwc->eps[epnum] = dep;
1394
1395 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1396 (epnum & 1) ? "in" : "out");
1397 dep->endpoint.name = dep->name;
1398 dep->direction = (epnum & 1);
1399
1400 if (epnum == 0 || epnum == 1) {
1401 dep->endpoint.maxpacket = 512;
1402 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1403 if (!epnum)
1404 dwc->gadget.ep0 = &dep->endpoint;
1405 } else {
1406 int ret;
1407
1408 dep->endpoint.maxpacket = 1024;
12d36c16 1409 dep->endpoint.max_streams = 15;
72246da4
FB		 1410 dep->endpoint.ops = &dwc3_gadget_ep_ops;
1411 list_add_tail(&dep->endpoint.ep_list,
1412 &dwc->gadget.ep_list);
1413
1414 ret = dwc3_alloc_trb_pool(dep);
25b8ff68 1415 if (ret)
72246da4 1416 return ret;
72246da4 1417 }
25b8ff68 1418
72246da4
FB		 1419 INIT_LIST_HEAD(&dep->request_list);
1420 INIT_LIST_HEAD(&dep->req_queued);
1421 }
1422
1423 return 0;
1424}
1425
1426static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1427{
1428 struct dwc3_ep *dep;
1429 u8 epnum;
1430
1431 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1432 dep = dwc->eps[epnum];
1433 dwc3_free_trb_pool(dep);
1434
1435 if (epnum != 0 && epnum != 1)
1436 list_del(&dep->endpoint.ep_list);
1437
1438 kfree(dep);
1439 }
1440}
1441
1442static void dwc3_gadget_release(struct device *dev)
1443{
1444 dev_dbg(dev, "%s\n", __func__);
1445}
1446
1447/* -------------------------------------------------------------------------- */
1448static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1449 const struct dwc3_event_depevt *event, int status)
1450{
1451 struct dwc3_request *req;
1452 struct dwc3_trb trb;
1453 unsigned int count;
1454 unsigned int s_pkt = 0;
1455
1456 do {
1457 req = next_request(&dep->req_queued);
d39ee7be
SAS		 1458 if (!req) {
1459 WARN_ON_ONCE(1);
1460 return 1;
1461 }
72246da4
FB		 1462
1463 dwc3_trb_to_nat(req->trb, &trb);
1464
0d2f4758
SAS		 1465 if (trb.hwo && status != -ESHUTDOWN)
1466 /*
1467 * We continue despite the error. There is not much we
1468 * can do. If we don't clean in up we loop for ever. If
1469 * we skip the TRB than it gets overwritten reused after
1470 * a while since we use them in a ring buffer. a BUG()
1471 * would help. Lets hope that if this occures, someone
1472 * fixes the root cause instead of looking away :)
1473 */
72246da4
FB		 1474 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1475 dep->name, req->trb);
72246da4
FB		 1476 count = trb.length;
1477
1478 if (dep->direction) {
1479 if (count) {
1480 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1481 dep->name);
1482 status = -ECONNRESET;
1483 }
1484 } else {
1485 if (count && (event->status & DEPEVT_STATUS_SHORT))
1486 s_pkt = 1;
1487 }
1488
1489 /*
1490 * We assume here we will always receive the entire data block
1491 * which we should receive. Meaning, if we program RX to
1492 * receive 4K but we receive only 2K, we assume that's all we
1493 * should receive and we simply bounce the request back to the
1494 * gadget driver for further processing.
1495 */
1496 req->request.actual += req->request.length - count;
1497 dwc3_gadget_giveback(dep, req, status);
1498 if (s_pkt)
1499 break;
1500 if ((event->status & DEPEVT_STATUS_LST) && trb.lst)
1501 break;
1502 if ((event->status & DEPEVT_STATUS_IOC) && trb.ioc)
1503 break;
1504 } while (1);
1505
1506 if ((event->status & DEPEVT_STATUS_IOC) && trb.ioc)
1507 return 0;
1508 return 1;
1509}
1510
1511static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
1512 struct dwc3_ep *dep, const struct dwc3_event_depevt *event,
1513 int start_new)
1514{
1515 unsigned status = 0;
1516 int clean_busy;
1517
1518 if (event->status & DEPEVT_STATUS_BUSERR)
1519 status = -ECONNRESET;
1520
1521 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
a1ae9be5 1522 if (clean_busy) {
72246da4 1523 dep->flags &= ~DWC3_EP_BUSY;
a1ae9be5
SAS		 1524 dep->res_trans_idx = 0;
1525 }
fae2b904
FB		 1526
1527 /*
1528 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
1529 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
1530 */
1531 if (dwc->revision < DWC3_REVISION_183A) {
1532 u32 reg;
1533 int i;
1534
1535 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
1536 struct dwc3_ep *dep = dwc->eps[i];
1537
1538 if (!(dep->flags & DWC3_EP_ENABLED))
1539 continue;
1540
1541 if (!list_empty(&dep->req_queued))
1542 return;
1543 }
1544
1545 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1546 reg |= dwc->u1u2;
1547 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1548
1549 dwc->u1u2 = 0;
1550 }
72246da4
FB		 1551}
1552
1553static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1554 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1555{
1556 u32 uf;
1557
1558 if (list_empty(&dep->request_list)) {
1559 dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n",
1560 dep->name);
1561 return;
1562 }
1563
1564 if (event->parameters) {
1565 u32 mask;
1566
1567 mask = ~(dep->interval - 1);
1568 uf = event->parameters & mask;
1569 /* 4 micro frames in the future */
1570 uf += dep->interval * 4;
1571 } else {
1572 uf = 0;
1573 }
1574
1575 __dwc3_gadget_kick_transfer(dep, uf, 1);
1576}
1577
1578static void dwc3_process_ep_cmd_complete(struct dwc3_ep *dep,
1579 const struct dwc3_event_depevt *event)
1580{
1581 struct dwc3 *dwc = dep->dwc;
1582 struct dwc3_event_depevt mod_ev = *event;
1583
1584 /*
1585 * We were asked to remove one requests. It is possible that this
1586 * request and a few other were started together and have the same
1587 * transfer index. Since we stopped the complete endpoint we don't
1588 * know how many requests were already completed (and not yet)
1589 * reported and how could be done (later). We purge them all until
1590 * the end of the list.
1591 */
1592 mod_ev.status = DEPEVT_STATUS_LST;
1593 dwc3_cleanup_done_reqs(dwc, dep, &mod_ev, -ESHUTDOWN);
1594 dep->flags &= ~DWC3_EP_BUSY;
1595 /* pending requets are ignored and are queued on XferNotReady */
72246da4
FB		 1596}
1597
1598static void dwc3_ep_cmd_compl(struct dwc3_ep *dep,
1599 const struct dwc3_event_depevt *event)
1600{
1601 u32 param = event->parameters;
1602 u32 cmd_type = (param >> 8) & ((1 << 5) - 1);
1603
1604 switch (cmd_type) {
1605 case DWC3_DEPCMD_ENDTRANSFER:
1606 dwc3_process_ep_cmd_complete(dep, event);
1607 break;
1608 case DWC3_DEPCMD_STARTTRANSFER:
1609 dep->res_trans_idx = param & 0x7f;
1610 break;
1611 default:
1612 printk(KERN_ERR "%s() unknown /unexpected type: %d\n",
1613 __func__, cmd_type);
1614 break;
1615 };
1616}
1617
1618static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
1619 const struct dwc3_event_depevt *event)
1620{
1621 struct dwc3_ep *dep;
1622 u8 epnum = event->endpoint_number;
1623
1624 dep = dwc->eps[epnum];
1625
1626 dev_vdbg(dwc->dev, "%s: %s\n", dep->name,
1627 dwc3_ep_event_string(event->endpoint_event));
1628
1629 if (epnum == 0 || epnum == 1) {
1630 dwc3_ep0_interrupt(dwc, event);
1631 return;
1632 }
1633
1634 switch (event->endpoint_event) {
1635 case DWC3_DEPEVT_XFERCOMPLETE:
1636 if (usb_endpoint_xfer_isoc(dep->desc)) {
1637 dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n",
1638 dep->name);
1639 return;
1640 }
1641
1642 dwc3_endpoint_transfer_complete(dwc, dep, event, 1);
1643 break;
1644 case DWC3_DEPEVT_XFERINPROGRESS:
1645 if (!usb_endpoint_xfer_isoc(dep->desc)) {
1646 dev_dbg(dwc->dev, "%s is not an Isochronous endpoint\n",
1647 dep->name);
1648 return;
1649 }
1650
1651 dwc3_endpoint_transfer_complete(dwc, dep, event, 0);
1652 break;
1653 case DWC3_DEPEVT_XFERNOTREADY:
1654 if (usb_endpoint_xfer_isoc(dep->desc)) {
1655 dwc3_gadget_start_isoc(dwc, dep, event);
1656 } else {
1657 int ret;
1658
1659 dev_vdbg(dwc->dev, "%s: reason %s\n",
1660 dep->name, event->status
1661 ? "Transfer Active"
1662 : "Transfer Not Active");
1663
1664 ret = __dwc3_gadget_kick_transfer(dep, 0, 1);
1665 if (!ret || ret == -EBUSY)
1666 return;
1667
1668 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1669 dep->name);
1670 }
1671
879631aa
FB		 1672 break;
1673 case DWC3_DEPEVT_STREAMEVT:
1674 if (!usb_endpoint_xfer_bulk(dep->desc)) {
1675 dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
1676 dep->name);
1677 return;
1678 }
1679
1680 switch (event->status) {
1681 case DEPEVT_STREAMEVT_FOUND:
1682 dev_vdbg(dwc->dev, "Stream %d found and started\n",
1683 event->parameters);
1684
1685 break;
1686 case DEPEVT_STREAMEVT_NOTFOUND:
1687 /* FALLTHROUGH */
1688 default:
1689 dev_dbg(dwc->dev, "Couldn't find suitable stream\n");
1690 }
72246da4
FB		 1691 break;
1692 case DWC3_DEPEVT_RXTXFIFOEVT:
1693 dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name);
1694 break;
72246da4
FB		 1695 case DWC3_DEPEVT_EPCMDCMPLT:
1696 dwc3_ep_cmd_compl(dep, event);
1697 break;
1698 }
1699}
1700
1701static void dwc3_disconnect_gadget(struct dwc3 *dwc)
1702{
1703 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
1704 spin_unlock(&dwc->lock);
1705 dwc->gadget_driver->disconnect(&dwc->gadget);
1706 spin_lock(&dwc->lock);
1707 }
1708}
1709
1710static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum)
1711{
1712 struct dwc3_ep *dep;
1713 struct dwc3_gadget_ep_cmd_params params;
1714 u32 cmd;
1715 int ret;
1716
1717 dep = dwc->eps[epnum];
1718
624407f9 1719 WARN_ON(!dep->res_trans_idx);
72246da4
FB		 1720 if (dep->res_trans_idx) {
1721 cmd = DWC3_DEPCMD_ENDTRANSFER;
1722 cmd |= DWC3_DEPCMD_HIPRI_FORCERM | DWC3_DEPCMD_CMDIOC;
1723 cmd |= DWC3_DEPCMD_PARAM(dep->res_trans_idx);
1724 memset(&params, 0, sizeof(params));
1725 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
1726 WARN_ON_ONCE(ret);
a1ae9be5 1727 dep->res_trans_idx = 0;
72246da4
FB		 1728 }
1729}
1730
1731static void dwc3_stop_active_transfers(struct dwc3 *dwc)
1732{
1733 u32 epnum;
1734
1735 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1736 struct dwc3_ep *dep;
1737
1738 dep = dwc->eps[epnum];
1739 if (!(dep->flags & DWC3_EP_ENABLED))
1740 continue;
1741
624407f9 1742 dwc3_remove_requests(dwc, dep);
72246da4
FB		 1743 }
1744}
1745
1746static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
1747{
1748 u32 epnum;
1749
1750 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1751 struct dwc3_ep *dep;
1752 struct dwc3_gadget_ep_cmd_params params;
1753 int ret;
1754
1755 dep = dwc->eps[epnum];
1756
1757 if (!(dep->flags & DWC3_EP_STALL))
1758 continue;
1759
1760 dep->flags &= ~DWC3_EP_STALL;
1761
1762 memset(&params, 0, sizeof(params));
1763 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1764 DWC3_DEPCMD_CLEARSTALL, &params);
1765 WARN_ON_ONCE(ret);
1766 }
1767}
1768
1769static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
1770{
1771 dev_vdbg(dwc->dev, "%s\n", __func__);
1772#if 0
1773 XXX
1774 U1/U2 is powersave optimization. Skip it for now. Anyway we need to
1775 enable it before we can disable it.
1776
1777 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1778 reg &= ~DWC3_DCTL_INITU1ENA;
1779 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1780
1781 reg &= ~DWC3_DCTL_INITU2ENA;
1782 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1783#endif
1784
1785 dwc3_stop_active_transfers(dwc);
1786 dwc3_disconnect_gadget(dwc);
b23c8439 1787 dwc->start_config_issued = false;
72246da4
FB		 1788
1789 dwc->gadget.speed = USB_SPEED_UNKNOWN;
df62df56 1790 dwc->setup_packet_pending = false;
72246da4
FB		 1791}
1792
1793static void dwc3_gadget_usb3_phy_power(struct dwc3 *dwc, int on)
1794{
1795 u32 reg;
1796
1797 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
1798
1799 if (on)
1800 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
1801 else
1802 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
1803
1804 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
1805}
1806
1807static void dwc3_gadget_usb2_phy_power(struct dwc3 *dwc, int on)
1808{
1809 u32 reg;
1810
1811 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1812
1813 if (on)
1814 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
1815 else
1816 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
1817
1818 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1819}
1820
1821static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
1822{
1823 u32 reg;
1824
1825 dev_vdbg(dwc->dev, "%s\n", __func__);
1826
df62df56
FB		 1827 /*
1828 * WORKAROUND: DWC3 revisions <1.88a have an issue which
1829 * would cause a missing Disconnect Event if there's a
1830 * pending Setup Packet in the FIFO.
1831 *
1832 * There's no suggested workaround on the official Bug
1833 * report, which states that "unless the driver/application
1834 * is doing any special handling of a disconnect event,
1835 * there is no functional issue".
1836 *
1837 * Unfortunately, it turns out that we _do_ some special
1838 * handling of a disconnect event, namely complete all
1839 * pending transfers, notify gadget driver of the
1840 * disconnection, and so on.
1841 *
1842 * Our suggested workaround is to follow the Disconnect
1843 * Event steps here, instead, based on a setup_packet_pending
1844 * flag. Such flag gets set whenever we have a XferNotReady
1845 * event on EP0 and gets cleared on XferComplete for the
1846 * same endpoint.
1847 *
1848 * Refers to:
1849 *
1850 * STAR#9000466709: RTL: Device : Disconnect event not
1851 * generated if setup packet pending in FIFO
1852 */
1853 if (dwc->revision < DWC3_REVISION_188A) {
1854 if (dwc->setup_packet_pending)
1855 dwc3_gadget_disconnect_interrupt(dwc);
1856 }
1857
961906ed
FB		 1858 /* after reset -> Default State */
1859 dwc->dev_state = DWC3_DEFAULT_STATE;
1860
72246da4
FB		 1861 /* Enable PHYs */
1862 dwc3_gadget_usb2_phy_power(dwc, true);
1863 dwc3_gadget_usb3_phy_power(dwc, true);
1864
1865 if (dwc->gadget.speed != USB_SPEED_UNKNOWN)
1866 dwc3_disconnect_gadget(dwc);
1867
1868 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1869 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
1870 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1871
1872 dwc3_stop_active_transfers(dwc);
1873 dwc3_clear_stall_all_ep(dwc);
b23c8439 1874 dwc->start_config_issued = false;
72246da4
FB		 1875
1876 /* Reset device address to zero */
1877 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1878 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
1879 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
72246da4
FB		 1880}
1881
1882static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
1883{
1884 u32 reg;
1885 u32 usb30_clock = DWC3_GCTL_CLK_BUS;
1886
1887 /*
1888 * We change the clock only at SS but I dunno why I would want to do
1889 * this. Maybe it becomes part of the power saving plan.
1890 */
1891
1892 if (speed != DWC3_DSTS_SUPERSPEED)
1893 return;
1894
1895 /*
1896 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
1897 * each time on Connect Done.
1898 */
1899 if (!usb30_clock)
1900 return;
1901
1902 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
1903 reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
1904 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
1905}
1906
1907static void dwc3_gadget_disable_phy(struct dwc3 *dwc, u8 speed)
1908{
1909 switch (speed) {
1910 case USB_SPEED_SUPER:
1911 dwc3_gadget_usb2_phy_power(dwc, false);
1912 break;
1913 case USB_SPEED_HIGH:
1914 case USB_SPEED_FULL:
1915 case USB_SPEED_LOW:
1916 dwc3_gadget_usb3_phy_power(dwc, false);
1917 break;
1918 }
1919}
1920
1921static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
1922{
1923 struct dwc3_gadget_ep_cmd_params params;
1924 struct dwc3_ep *dep;
1925 int ret;
1926 u32 reg;
1927 u8 speed;
1928
1929 dev_vdbg(dwc->dev, "%s\n", __func__);
1930
1931 memset(&params, 0x00, sizeof(params));
1932
72246da4
FB		 1933 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1934 speed = reg & DWC3_DSTS_CONNECTSPD;
1935 dwc->speed = speed;
1936
1937 dwc3_update_ram_clk_sel(dwc, speed);
1938
1939 switch (speed) {
1940 case DWC3_DCFG_SUPERSPEED:
05870c5b
FB		 1941 /*
1942 * WORKAROUND: DWC3 revisions <1.90a have an issue which
1943 * would cause a missing USB3 Reset event.
1944 *
1945 * In such situations, we should force a USB3 Reset
1946 * event by calling our dwc3_gadget_reset_interrupt()
1947 * routine.
1948 *
1949 * Refers to:
1950 *
1951 * STAR#9000483510: RTL: SS : USB3 reset event may
1952 * not be generated always when the link enters poll
1953 */
1954 if (dwc->revision < DWC3_REVISION_190A)
1955 dwc3_gadget_reset_interrupt(dwc);
1956
72246da4
FB		 1957 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1958 dwc->gadget.ep0->maxpacket = 512;
1959 dwc->gadget.speed = USB_SPEED_SUPER;
1960 break;
1961 case DWC3_DCFG_HIGHSPEED:
1962 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
1963 dwc->gadget.ep0->maxpacket = 64;
1964 dwc->gadget.speed = USB_SPEED_HIGH;
1965 break;
1966 case DWC3_DCFG_FULLSPEED2:
1967 case DWC3_DCFG_FULLSPEED1:
1968 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
1969 dwc->gadget.ep0->maxpacket = 64;
1970 dwc->gadget.speed = USB_SPEED_FULL;
1971 break;
1972 case DWC3_DCFG_LOWSPEED:
1973 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
1974 dwc->gadget.ep0->maxpacket = 8;
1975 dwc->gadget.speed = USB_SPEED_LOW;
1976 break;
1977 }
1978
1979 /* Disable unneded PHY */
1980 dwc3_gadget_disable_phy(dwc, dwc->gadget.speed);
1981
1982 dep = dwc->eps[0];
c90bfaec 1983 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL);
72246da4
FB		 1984 if (ret) {
1985 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1986 return;
1987 }
1988
1989 dep = dwc->eps[1];
c90bfaec 1990 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL);
72246da4
FB		 1991 if (ret) {
1992 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1993 return;
1994 }
1995
1996 /*
1997 * Configure PHY via GUSB3PIPECTLn if required.
1998 *
1999 * Update GTXFIFOSIZn
2000 *
2001 * In both cases reset values should be sufficient.
2002 */
2003}
2004
2005static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2006{
2007 dev_vdbg(dwc->dev, "%s\n", __func__);
2008
2009 /*
2010 * TODO take core out of low power mode when that's
2011 * implemented.
2012 */
2013
2014 dwc->gadget_driver->resume(&dwc->gadget);
2015}
2016
2017static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2018 unsigned int evtinfo)
2019{
fae2b904
FB		 2020 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2021
2022 /*
2023 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2024 * on the link partner, the USB session might do multiple entry/exit
2025 * of low power states before a transfer takes place.
2026 *
2027 * Due to this problem, we might experience lower throughput. The
2028 * suggested workaround is to disable DCTL[12:9] bits if we're
2029 * transitioning from U1/U2 to U0 and enable those bits again
2030 * after a transfer completes and there are no pending transfers
2031 * on any of the enabled endpoints.
2032 *
2033 * This is the first half of that workaround.
2034 *
2035 * Refers to:
2036 *
2037 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2038 * core send LGO_Ux entering U0
2039 */
2040 if (dwc->revision < DWC3_REVISION_183A) {
2041 if (next == DWC3_LINK_STATE_U0) {
2042 u32 u1u2;
2043 u32 reg;
2044
2045 switch (dwc->link_state) {
2046 case DWC3_LINK_STATE_U1:
2047 case DWC3_LINK_STATE_U2:
2048 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2049 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2050 | DWC3_DCTL_ACCEPTU2ENA
2051 | DWC3_DCTL_INITU1ENA
2052 | DWC3_DCTL_ACCEPTU1ENA);
2053
2054 if (!dwc->u1u2)
2055 dwc->u1u2 = reg & u1u2;
2056
2057 reg &= ~u1u2;
2058
2059 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2060 break;
2061 default:
2062 /* do nothing */
2063 break;
2064 }
2065 }
2066 }
2067
2068 dwc->link_state = next;
019ac832
FB		 2069
2070 dev_vdbg(dwc->dev, "%s link %d\n", __func__, dwc->link_state);
72246da4
FB		 2071}
2072
2073static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2074 const struct dwc3_event_devt *event)
2075{
2076 switch (event->type) {
2077 case DWC3_DEVICE_EVENT_DISCONNECT:
2078 dwc3_gadget_disconnect_interrupt(dwc);
2079 break;
2080 case DWC3_DEVICE_EVENT_RESET:
2081 dwc3_gadget_reset_interrupt(dwc);
2082 break;
2083 case DWC3_DEVICE_EVENT_CONNECT_DONE:
2084 dwc3_gadget_conndone_interrupt(dwc);
2085 break;
2086 case DWC3_DEVICE_EVENT_WAKEUP:
2087 dwc3_gadget_wakeup_interrupt(dwc);
2088 break;
2089 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2090 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2091 break;
2092 case DWC3_DEVICE_EVENT_EOPF:
2093 dev_vdbg(dwc->dev, "End of Periodic Frame\n");
2094 break;
2095 case DWC3_DEVICE_EVENT_SOF:
2096 dev_vdbg(dwc->dev, "Start of Periodic Frame\n");
2097 break;
2098 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2099 dev_vdbg(dwc->dev, "Erratic Error\n");
2100 break;
2101 case DWC3_DEVICE_EVENT_CMD_CMPL:
2102 dev_vdbg(dwc->dev, "Command Complete\n");
2103 break;
2104 case DWC3_DEVICE_EVENT_OVERFLOW:
2105 dev_vdbg(dwc->dev, "Overflow\n");
2106 break;
2107 default:
2108 dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2109 }
2110}
2111
2112static void dwc3_process_event_entry(struct dwc3 *dwc,
2113 const union dwc3_event *event)
2114{
2115 /* Endpoint IRQ, handle it and return early */
2116 if (event->type.is_devspec == 0) {
2117 /* depevt */
2118 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2119 }
2120
2121 switch (event->type.type) {
2122 case DWC3_EVENT_TYPE_DEV:
2123 dwc3_gadget_interrupt(dwc, &event->devt);
2124 break;
2125 /* REVISIT what to do with Carkit and I2C events ? */
2126 default:
2127 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2128 }
2129}
2130
2131static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
2132{
2133 struct dwc3_event_buffer *evt;
2134 int left;
2135 u32 count;
2136
2137 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf));
2138 count &= DWC3_GEVNTCOUNT_MASK;
2139 if (!count)
2140 return IRQ_NONE;
2141
2142 evt = dwc->ev_buffs[buf];
2143 left = count;
2144
2145 while (left > 0) {
2146 union dwc3_event event;
2147
2148 memcpy(&event.raw, (evt->buf + evt->lpos), sizeof(event.raw));
2149 dwc3_process_event_entry(dwc, &event);
2150 /*
2151 * XXX we wrap around correctly to the next entry as almost all
2152 * entries are 4 bytes in size. There is one entry which has 12
2153 * bytes which is a regular entry followed by 8 bytes data. ATM
2154 * I don't know how things are organized if were get next to the
2155 * a boundary so I worry about that once we try to handle that.
2156 */
2157 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2158 left -= 4;
2159
2160 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4);
2161 }
2162
2163 return IRQ_HANDLED;
2164}
2165
2166static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
2167{
2168 struct dwc3 *dwc = _dwc;
2169 int i;
2170 irqreturn_t ret = IRQ_NONE;
2171
2172 spin_lock(&dwc->lock);
2173
9f622b2a 2174 for (i = 0; i < dwc->num_event_buffers; i++) {
72246da4
FB		 2175 irqreturn_t status;
2176
2177 status = dwc3_process_event_buf(dwc, i);
2178 if (status == IRQ_HANDLED)
2179 ret = status;
2180 }
2181
2182 spin_unlock(&dwc->lock);
2183
2184 return ret;
2185}
2186
2187/**
2188 * dwc3_gadget_init - Initializes gadget related registers
2189 * @dwc: Pointer to out controller context structure
2190 *
2191 * Returns 0 on success otherwise negative errno.
2192 */
2193int __devinit dwc3_gadget_init(struct dwc3 *dwc)
2194{
2195 u32 reg;
2196 int ret;
2197 int irq;
2198
2199 dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2200 &dwc->ctrl_req_addr, GFP_KERNEL);
2201 if (!dwc->ctrl_req) {
2202 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2203 ret = -ENOMEM;
2204 goto err0;
2205 }
2206
2207 dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2208 &dwc->ep0_trb_addr, GFP_KERNEL);
2209 if (!dwc->ep0_trb) {
2210 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2211 ret = -ENOMEM;
2212 goto err1;
2213 }
2214
2215 dwc->setup_buf = dma_alloc_coherent(dwc->dev,
2216 sizeof(*dwc->setup_buf) * 2,
2217 &dwc->setup_buf_addr, GFP_KERNEL);
2218 if (!dwc->setup_buf) {
2219 dev_err(dwc->dev, "failed to allocate setup buffer\n");
2220 ret = -ENOMEM;
2221 goto err2;
2222 }
2223
5812b1c2
FB		 2224 dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
2225 512, &dwc->ep0_bounce_addr, GFP_KERNEL);
2226 if (!dwc->ep0_bounce) {
2227 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2228 ret = -ENOMEM;
2229 goto err3;
2230 }
2231
72246da4
FB		 2232 dev_set_name(&dwc->gadget.dev, "gadget");
2233
2234 dwc->gadget.ops = &dwc3_gadget_ops;
d327ab5b 2235 dwc->gadget.max_speed = USB_SPEED_SUPER;
72246da4
FB		 2236 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2237 dwc->gadget.dev.parent = dwc->dev;
eeb720fb 2238 dwc->gadget.sg_supported = true;
72246da4
FB		 2239
2240 dma_set_coherent_mask(&dwc->gadget.dev, dwc->dev->coherent_dma_mask);
2241
2242 dwc->gadget.dev.dma_parms = dwc->dev->dma_parms;
2243 dwc->gadget.dev.dma_mask = dwc->dev->dma_mask;
2244 dwc->gadget.dev.release = dwc3_gadget_release;
2245 dwc->gadget.name = "dwc3-gadget";
2246
2247 /*
2248 * REVISIT: Here we should clear all pending IRQs to be
2249 * sure we're starting from a well known location.
2250 */
2251
2252 ret = dwc3_gadget_init_endpoints(dwc);
2253 if (ret)
5812b1c2 2254 goto err4;
72246da4
FB		 2255
2256 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
2257
2258 ret = request_irq(irq, dwc3_interrupt, IRQF_SHARED,
2259 "dwc3", dwc);
2260 if (ret) {
2261 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
2262 irq, ret);
5812b1c2 2263 goto err5;
72246da4
FB		 2264 }
2265
2266 /* Enable all but Start and End of Frame IRQs */
2267 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
2268 DWC3_DEVTEN_EVNTOVERFLOWEN |
2269 DWC3_DEVTEN_CMDCMPLTEN |
2270 DWC3_DEVTEN_ERRTICERREN |
2271 DWC3_DEVTEN_WKUPEVTEN |
2272 DWC3_DEVTEN_ULSTCNGEN |
2273 DWC3_DEVTEN_CONNECTDONEEN |
2274 DWC3_DEVTEN_USBRSTEN |
2275 DWC3_DEVTEN_DISCONNEVTEN);
2276 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
2277
2278 ret = device_register(&dwc->gadget.dev);
2279 if (ret) {
2280 dev_err(dwc->dev, "failed to register gadget device\n");
2281 put_device(&dwc->gadget.dev);
5812b1c2 2282 goto err6;
72246da4
FB		 2283 }
2284
2285 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2286 if (ret) {
2287 dev_err(dwc->dev, "failed to register udc\n");
5812b1c2 2288 goto err7;
72246da4
FB		 2289 }
2290
2291 return 0;
2292
5812b1c2 2293err7:
72246da4
FB		 2294 device_unregister(&dwc->gadget.dev);
2295
5812b1c2 2296err6:
72246da4
FB		 2297 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
2298 free_irq(irq, dwc);
2299
5812b1c2 2300err5:
72246da4
FB		 2301 dwc3_gadget_free_endpoints(dwc);
2302
5812b1c2
FB		 2303err4:
2304 dma_free_coherent(dwc->dev, 512, dwc->ep0_bounce,
2305 dwc->ep0_bounce_addr);
2306
72246da4
FB		 2307err3:
2308 dma_free_coherent(dwc->dev, sizeof(*dwc->setup_buf) * 2,
2309 dwc->setup_buf, dwc->setup_buf_addr);
2310
2311err2:
2312 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2313 dwc->ep0_trb, dwc->ep0_trb_addr);
2314
2315err1:
2316 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2317 dwc->ctrl_req, dwc->ctrl_req_addr);
2318
2319err0:
2320 return ret;
2321}
2322
2323void dwc3_gadget_exit(struct dwc3 *dwc)
2324{
2325 int irq;
72246da4
FB		 2326
2327 usb_del_gadget_udc(&dwc->gadget);
2328 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
2329
2330 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
2331 free_irq(irq, dwc);
2332
72246da4
FB		 2333 dwc3_gadget_free_endpoints(dwc);
2334
5812b1c2
FB		 2335 dma_free_coherent(dwc->dev, 512, dwc->ep0_bounce,
2336 dwc->ep0_bounce_addr);
2337
72246da4
FB		 2338 dma_free_coherent(dwc->dev, sizeof(*dwc->setup_buf) * 2,
2339 dwc->setup_buf, dwc->setup_buf_addr);
2340
2341 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2342 dwc->ep0_trb, dwc->ep0_trb_addr);
2343
2344 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2345 dwc->ctrl_req, dwc->ctrl_req_addr);
2346
2347 device_unregister(&dwc->gadget.dev);
2348}
kernel source for telekom puls (alcatel/mediatek)