2 * ALSA driver for RME Digi96, Digi96/8 and Digi96/8 PRO/PAD/PST audio
5 * Copyright (c) 2000, 2001 Anders Torger <torger@ludd.luth.se>
7 * Thanks to Henk Hesselink <henk@anda.nl> for the analog volume control
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
26 #include <linux/delay.h>
27 #include <linux/init.h>
28 #include <linux/interrupt.h>
29 #include <linux/pci.h>
30 #include <linux/module.h>
32 #include <sound/core.h>
33 #include <sound/info.h>
34 #include <sound/control.h>
35 #include <sound/pcm.h>
36 #include <sound/pcm_params.h>
37 #include <sound/asoundef.h>
38 #include <sound/initval.h>
42 /* note, two last pcis should be equal, it is not a bug */
44 MODULE_AUTHOR("Anders Torger <torger@ludd.luth.se>");
45 MODULE_DESCRIPTION("RME Digi96, Digi96/8, Digi96/8 PRO, Digi96/8 PST, "
47 MODULE_LICENSE("GPL");
48 MODULE_SUPPORTED_DEVICE("{{RME,Digi96},"
52 "{RME,Digi96/8 PAD}}");
54 static int index
[SNDRV_CARDS
] = SNDRV_DEFAULT_IDX
; /* Index 0-MAX */
55 static char *id
[SNDRV_CARDS
] = SNDRV_DEFAULT_STR
; /* ID for this card */
56 static bool enable
[SNDRV_CARDS
] = SNDRV_DEFAULT_ENABLE_PNP
; /* Enable this card */
58 module_param_array(index
, int, NULL
, 0444);
59 MODULE_PARM_DESC(index
, "Index value for RME Digi96 soundcard.");
60 module_param_array(id
, charp
, NULL
, 0444);
61 MODULE_PARM_DESC(id
, "ID string for RME Digi96 soundcard.");
62 module_param_array(enable
, bool, NULL
, 0444);
63 MODULE_PARM_DESC(enable
, "Enable RME Digi96 soundcard.");
66 * Defines for RME Digi96 series, from internal RME reference documents
70 #define RME96_SPDIF_NCHANNELS 2
72 /* Playback and capture buffer size */
73 #define RME96_BUFFER_SIZE 0x10000
76 #define RME96_IO_SIZE 0x60000
79 #define RME96_IO_PLAY_BUFFER 0x0
80 #define RME96_IO_REC_BUFFER 0x10000
81 #define RME96_IO_CONTROL_REGISTER 0x20000
82 #define RME96_IO_ADDITIONAL_REG 0x20004
83 #define RME96_IO_CONFIRM_PLAY_IRQ 0x20008
84 #define RME96_IO_CONFIRM_REC_IRQ 0x2000C
85 #define RME96_IO_SET_PLAY_POS 0x40000
86 #define RME96_IO_RESET_PLAY_POS 0x4FFFC
87 #define RME96_IO_SET_REC_POS 0x50000
88 #define RME96_IO_RESET_REC_POS 0x5FFFC
89 #define RME96_IO_GET_PLAY_POS 0x20000
90 #define RME96_IO_GET_REC_POS 0x30000
92 /* Write control register bits */
93 #define RME96_WCR_START (1 << 0)
94 #define RME96_WCR_START_2 (1 << 1)
95 #define RME96_WCR_GAIN_0 (1 << 2)
96 #define RME96_WCR_GAIN_1 (1 << 3)
97 #define RME96_WCR_MODE24 (1 << 4)
98 #define RME96_WCR_MODE24_2 (1 << 5)
99 #define RME96_WCR_BM (1 << 6)
100 #define RME96_WCR_BM_2 (1 << 7)
101 #define RME96_WCR_ADAT (1 << 8)
102 #define RME96_WCR_FREQ_0 (1 << 9)
103 #define RME96_WCR_FREQ_1 (1 << 10)
104 #define RME96_WCR_DS (1 << 11)
105 #define RME96_WCR_PRO (1 << 12)
106 #define RME96_WCR_EMP (1 << 13)
107 #define RME96_WCR_SEL (1 << 14)
108 #define RME96_WCR_MASTER (1 << 15)
109 #define RME96_WCR_PD (1 << 16)
110 #define RME96_WCR_INP_0 (1 << 17)
111 #define RME96_WCR_INP_1 (1 << 18)
112 #define RME96_WCR_THRU_0 (1 << 19)
113 #define RME96_WCR_THRU_1 (1 << 20)
114 #define RME96_WCR_THRU_2 (1 << 21)
115 #define RME96_WCR_THRU_3 (1 << 22)
116 #define RME96_WCR_THRU_4 (1 << 23)
117 #define RME96_WCR_THRU_5 (1 << 24)
118 #define RME96_WCR_THRU_6 (1 << 25)
119 #define RME96_WCR_THRU_7 (1 << 26)
120 #define RME96_WCR_DOLBY (1 << 27)
121 #define RME96_WCR_MONITOR_0 (1 << 28)
122 #define RME96_WCR_MONITOR_1 (1 << 29)
123 #define RME96_WCR_ISEL (1 << 30)
124 #define RME96_WCR_IDIS (1 << 31)
126 #define RME96_WCR_BITPOS_GAIN_0 2
127 #define RME96_WCR_BITPOS_GAIN_1 3
128 #define RME96_WCR_BITPOS_FREQ_0 9
129 #define RME96_WCR_BITPOS_FREQ_1 10
130 #define RME96_WCR_BITPOS_INP_0 17
131 #define RME96_WCR_BITPOS_INP_1 18
132 #define RME96_WCR_BITPOS_MONITOR_0 28
133 #define RME96_WCR_BITPOS_MONITOR_1 29
135 /* Read control register bits */
136 #define RME96_RCR_AUDIO_ADDR_MASK 0xFFFF
137 #define RME96_RCR_IRQ_2 (1 << 16)
138 #define RME96_RCR_T_OUT (1 << 17)
139 #define RME96_RCR_DEV_ID_0 (1 << 21)
140 #define RME96_RCR_DEV_ID_1 (1 << 22)
141 #define RME96_RCR_LOCK (1 << 23)
142 #define RME96_RCR_VERF (1 << 26)
143 #define RME96_RCR_F0 (1 << 27)
144 #define RME96_RCR_F1 (1 << 28)
145 #define RME96_RCR_F2 (1 << 29)
146 #define RME96_RCR_AUTOSYNC (1 << 30)
147 #define RME96_RCR_IRQ (1 << 31)
149 #define RME96_RCR_BITPOS_F0 27
150 #define RME96_RCR_BITPOS_F1 28
151 #define RME96_RCR_BITPOS_F2 29
153 /* Additional register bits */
154 #define RME96_AR_WSEL (1 << 0)
155 #define RME96_AR_ANALOG (1 << 1)
156 #define RME96_AR_FREQPAD_0 (1 << 2)
157 #define RME96_AR_FREQPAD_1 (1 << 3)
158 #define RME96_AR_FREQPAD_2 (1 << 4)
159 #define RME96_AR_PD2 (1 << 5)
160 #define RME96_AR_DAC_EN (1 << 6)
161 #define RME96_AR_CLATCH (1 << 7)
162 #define RME96_AR_CCLK (1 << 8)
163 #define RME96_AR_CDATA (1 << 9)
165 #define RME96_AR_BITPOS_F0 2
166 #define RME96_AR_BITPOS_F1 3
167 #define RME96_AR_BITPOS_F2 4
170 #define RME96_MONITOR_TRACKS_1_2 0
171 #define RME96_MONITOR_TRACKS_3_4 1
172 #define RME96_MONITOR_TRACKS_5_6 2
173 #define RME96_MONITOR_TRACKS_7_8 3
176 #define RME96_ATTENUATION_0 0
177 #define RME96_ATTENUATION_6 1
178 #define RME96_ATTENUATION_12 2
179 #define RME96_ATTENUATION_18 3
182 #define RME96_INPUT_OPTICAL 0
183 #define RME96_INPUT_COAXIAL 1
184 #define RME96_INPUT_INTERNAL 2
185 #define RME96_INPUT_XLR 3
186 #define RME96_INPUT_ANALOG 4
189 #define RME96_CLOCKMODE_SLAVE 0
190 #define RME96_CLOCKMODE_MASTER 1
191 #define RME96_CLOCKMODE_WORDCLOCK 2
193 /* Block sizes in bytes */
194 #define RME96_SMALL_BLOCK_SIZE 2048
195 #define RME96_LARGE_BLOCK_SIZE 8192
198 #define RME96_AD1852_VOL_BITS 14
199 #define RME96_AD1855_VOL_BITS 10
206 void __iomem
*iobase
;
208 u32 wcreg
; /* cached write control register value */
209 u32 wcreg_spdif
; /* S/PDIF setup */
210 u32 wcreg_spdif_stream
; /* S/PDIF setup (temporary) */
211 u32 rcreg
; /* cached read control register value */
212 u32 areg
; /* cached additional register value */
213 u16 vol
[2]; /* cached volume of analog output */
215 u8 rev
; /* card revision number */
217 struct snd_pcm_substream
*playback_substream
;
218 struct snd_pcm_substream
*capture_substream
;
220 int playback_frlog
; /* log2 of framesize */
223 size_t playback_periodsize
; /* in bytes, zero if not used */
224 size_t capture_periodsize
; /* in bytes, zero if not used */
226 struct snd_card
*card
;
227 struct snd_pcm
*spdif_pcm
;
228 struct snd_pcm
*adat_pcm
;
230 struct snd_kcontrol
*spdif_ctl
;
233 static DEFINE_PCI_DEVICE_TABLE(snd_rme96_ids
) = {
234 { PCI_VDEVICE(XILINX
, PCI_DEVICE_ID_RME_DIGI96
), 0, },
235 { PCI_VDEVICE(XILINX
, PCI_DEVICE_ID_RME_DIGI96_8
), 0, },
236 { PCI_VDEVICE(XILINX
, PCI_DEVICE_ID_RME_DIGI96_8_PRO
), 0, },
237 { PCI_VDEVICE(XILINX
, PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST
), 0, },
241 MODULE_DEVICE_TABLE(pci
, snd_rme96_ids
);
243 #define RME96_ISPLAYING(rme96) ((rme96)->wcreg & RME96_WCR_START)
244 #define RME96_ISRECORDING(rme96) ((rme96)->wcreg & RME96_WCR_START_2)
245 #define RME96_HAS_ANALOG_IN(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST)
246 #define RME96_HAS_ANALOG_OUT(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PRO || \
247 (rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST)
248 #define RME96_DAC_IS_1852(rme96) (RME96_HAS_ANALOG_OUT(rme96) && (rme96)->rev >= 4)
249 #define RME96_DAC_IS_1855(rme96) (((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && (rme96)->rev < 4) || \
250 ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PRO && (rme96)->rev == 2))
251 #define RME96_185X_MAX_OUT(rme96) ((1 << (RME96_DAC_IS_1852(rme96) ? RME96_AD1852_VOL_BITS : RME96_AD1855_VOL_BITS)) - 1)
254 snd_rme96_playback_prepare(struct snd_pcm_substream
*substream
);
257 snd_rme96_capture_prepare(struct snd_pcm_substream
*substream
);
260 snd_rme96_playback_trigger(struct snd_pcm_substream
*substream
,
264 snd_rme96_capture_trigger(struct snd_pcm_substream
*substream
,
267 static snd_pcm_uframes_t
268 snd_rme96_playback_pointer(struct snd_pcm_substream
*substream
);
270 static snd_pcm_uframes_t
271 snd_rme96_capture_pointer(struct snd_pcm_substream
*substream
);
273 static void snd_rme96_proc_init(struct rme96
*rme96
);
276 snd_rme96_create_switches(struct snd_card
*card
,
277 struct rme96
*rme96
);
280 snd_rme96_getinputtype(struct rme96
*rme96
);
282 static inline unsigned int
283 snd_rme96_playback_ptr(struct rme96
*rme96
)
285 return (readl(rme96
->iobase
+ RME96_IO_GET_PLAY_POS
)
286 & RME96_RCR_AUDIO_ADDR_MASK
) >> rme96
->playback_frlog
;
289 static inline unsigned int
290 snd_rme96_capture_ptr(struct rme96
*rme96
)
292 return (readl(rme96
->iobase
+ RME96_IO_GET_REC_POS
)
293 & RME96_RCR_AUDIO_ADDR_MASK
) >> rme96
->capture_frlog
;
297 snd_rme96_playback_silence(struct snd_pcm_substream
*substream
,
298 int channel
, /* not used (interleaved data) */
299 snd_pcm_uframes_t pos
,
300 snd_pcm_uframes_t count
)
302 struct rme96
*rme96
= snd_pcm_substream_chip(substream
);
303 count
<<= rme96
->playback_frlog
;
304 pos
<<= rme96
->playback_frlog
;
305 memset_io(rme96
->iobase
+ RME96_IO_PLAY_BUFFER
+ pos
,
311 snd_rme96_playback_copy(struct snd_pcm_substream
*substream
,
312 int channel
, /* not used (interleaved data) */
313 snd_pcm_uframes_t pos
,
315 snd_pcm_uframes_t count
)
317 struct rme96
*rme96
= snd_pcm_substream_chip(substream
);
318 count
<<= rme96
->playback_frlog
;
319 pos
<<= rme96
->playback_frlog
;
320 copy_from_user_toio(rme96
->iobase
+ RME96_IO_PLAY_BUFFER
+ pos
, src
,
326 snd_rme96_capture_copy(struct snd_pcm_substream
*substream
,
327 int channel
, /* not used (interleaved data) */
328 snd_pcm_uframes_t pos
,
330 snd_pcm_uframes_t count
)
332 struct rme96
*rme96
= snd_pcm_substream_chip(substream
);
333 count
<<= rme96
->capture_frlog
;
334 pos
<<= rme96
->capture_frlog
;
335 copy_to_user_fromio(dst
, rme96
->iobase
+ RME96_IO_REC_BUFFER
+ pos
,
341 * Digital output capabilities (S/PDIF)
343 static struct snd_pcm_hardware snd_rme96_playback_spdif_info
=
345 .info
= (SNDRV_PCM_INFO_MMAP_IOMEM
|
346 SNDRV_PCM_INFO_MMAP_VALID
|
347 SNDRV_PCM_INFO_INTERLEAVED
|
348 SNDRV_PCM_INFO_PAUSE
),
349 .formats
= (SNDRV_PCM_FMTBIT_S16_LE
|
350 SNDRV_PCM_FMTBIT_S32_LE
),
351 .rates
= (SNDRV_PCM_RATE_32000
|
352 SNDRV_PCM_RATE_44100
|
353 SNDRV_PCM_RATE_48000
|
354 SNDRV_PCM_RATE_64000
|
355 SNDRV_PCM_RATE_88200
|
356 SNDRV_PCM_RATE_96000
),
361 .buffer_bytes_max
= RME96_BUFFER_SIZE
,
362 .period_bytes_min
= RME96_SMALL_BLOCK_SIZE
,
363 .period_bytes_max
= RME96_LARGE_BLOCK_SIZE
,
364 .periods_min
= RME96_BUFFER_SIZE
/ RME96_LARGE_BLOCK_SIZE
,
365 .periods_max
= RME96_BUFFER_SIZE
/ RME96_SMALL_BLOCK_SIZE
,
370 * Digital input capabilities (S/PDIF)
372 static struct snd_pcm_hardware snd_rme96_capture_spdif_info
=
374 .info
= (SNDRV_PCM_INFO_MMAP_IOMEM
|
375 SNDRV_PCM_INFO_MMAP_VALID
|
376 SNDRV_PCM_INFO_INTERLEAVED
|
377 SNDRV_PCM_INFO_PAUSE
),
378 .formats
= (SNDRV_PCM_FMTBIT_S16_LE
|
379 SNDRV_PCM_FMTBIT_S32_LE
),
380 .rates
= (SNDRV_PCM_RATE_32000
|
381 SNDRV_PCM_RATE_44100
|
382 SNDRV_PCM_RATE_48000
|
383 SNDRV_PCM_RATE_64000
|
384 SNDRV_PCM_RATE_88200
|
385 SNDRV_PCM_RATE_96000
),
390 .buffer_bytes_max
= RME96_BUFFER_SIZE
,
391 .period_bytes_min
= RME96_SMALL_BLOCK_SIZE
,
392 .period_bytes_max
= RME96_LARGE_BLOCK_SIZE
,
393 .periods_min
= RME96_BUFFER_SIZE
/ RME96_LARGE_BLOCK_SIZE
,
394 .periods_max
= RME96_BUFFER_SIZE
/ RME96_SMALL_BLOCK_SIZE
,
399 * Digital output capabilities (ADAT)
401 static struct snd_pcm_hardware snd_rme96_playback_adat_info
=
403 .info
= (SNDRV_PCM_INFO_MMAP_IOMEM
|
404 SNDRV_PCM_INFO_MMAP_VALID
|
405 SNDRV_PCM_INFO_INTERLEAVED
|
406 SNDRV_PCM_INFO_PAUSE
),
407 .formats
= (SNDRV_PCM_FMTBIT_S16_LE
|
408 SNDRV_PCM_FMTBIT_S32_LE
),
409 .rates
= (SNDRV_PCM_RATE_44100
|
410 SNDRV_PCM_RATE_48000
),
415 .buffer_bytes_max
= RME96_BUFFER_SIZE
,
416 .period_bytes_min
= RME96_SMALL_BLOCK_SIZE
,
417 .period_bytes_max
= RME96_LARGE_BLOCK_SIZE
,
418 .periods_min
= RME96_BUFFER_SIZE
/ RME96_LARGE_BLOCK_SIZE
,
419 .periods_max
= RME96_BUFFER_SIZE
/ RME96_SMALL_BLOCK_SIZE
,
424 * Digital input capabilities (ADAT)
426 static struct snd_pcm_hardware snd_rme96_capture_adat_info
=
428 .info
= (SNDRV_PCM_INFO_MMAP_IOMEM
|
429 SNDRV_PCM_INFO_MMAP_VALID
|
430 SNDRV_PCM_INFO_INTERLEAVED
|
431 SNDRV_PCM_INFO_PAUSE
),
432 .formats
= (SNDRV_PCM_FMTBIT_S16_LE
|
433 SNDRV_PCM_FMTBIT_S32_LE
),
434 .rates
= (SNDRV_PCM_RATE_44100
|
435 SNDRV_PCM_RATE_48000
),
440 .buffer_bytes_max
= RME96_BUFFER_SIZE
,
441 .period_bytes_min
= RME96_SMALL_BLOCK_SIZE
,
442 .period_bytes_max
= RME96_LARGE_BLOCK_SIZE
,
443 .periods_min
= RME96_BUFFER_SIZE
/ RME96_LARGE_BLOCK_SIZE
,
444 .periods_max
= RME96_BUFFER_SIZE
/ RME96_SMALL_BLOCK_SIZE
,
449 * The CDATA, CCLK and CLATCH bits can be used to write to the SPI interface
450 * of the AD1852 or AD1852 D/A converter on the board. CDATA must be set up
451 * on the falling edge of CCLK and be stable on the rising edge. The rising
452 * edge of CLATCH after the last data bit clocks in the whole data word.
453 * A fast processor could probably drive the SPI interface faster than the
454 * DAC can handle (3MHz for the 1855, unknown for the 1852). The udelay(1)
455 * limits the data rate to 500KHz and only causes a delay of 33 microsecs.
457 * NOTE: increased delay from 1 to 10, since there where problems setting
461 snd_rme96_write_SPI(struct rme96
*rme96
, u16 val
)
465 for (i
= 0; i
< 16; i
++) {
467 rme96
->areg
|= RME96_AR_CDATA
;
469 rme96
->areg
&= ~RME96_AR_CDATA
;
471 rme96
->areg
&= ~(RME96_AR_CCLK
| RME96_AR_CLATCH
);
472 writel(rme96
->areg
, rme96
->iobase
+ RME96_IO_ADDITIONAL_REG
);
474 rme96
->areg
|= RME96_AR_CCLK
;
475 writel(rme96
->areg
, rme96
->iobase
+ RME96_IO_ADDITIONAL_REG
);
479 rme96
->areg
&= ~(RME96_AR_CCLK
| RME96_AR_CDATA
);
480 rme96
->areg
|= RME96_AR_CLATCH
;
481 writel(rme96
->areg
, rme96
->iobase
+ RME96_IO_ADDITIONAL_REG
);
483 rme96
->areg
&= ~RME96_AR_CLATCH
;
484 writel(rme96
->areg
, rme96
->iobase
+ RME96_IO_ADDITIONAL_REG
);
488 snd_rme96_apply_dac_volume(struct rme96
*rme96
)
490 if (RME96_DAC_IS_1852(rme96
)) {
491 snd_rme96_write_SPI(rme96
, (rme96
->vol
[0] << 2) | 0x0);
492 snd_rme96_write_SPI(rme96
, (rme96
->vol
[1] << 2) | 0x2);
493 } else if (RME96_DAC_IS_1855(rme96
)) {
494 snd_rme96_write_SPI(rme96
, (rme96
->vol
[0] & 0x3FF) | 0x000);
495 snd_rme96_write_SPI(rme96
, (rme96
->vol
[1] & 0x3FF) | 0x400);
500 snd_rme96_reset_dac(struct rme96
*rme96
)
502 writel(rme96
->wcreg
| RME96_WCR_PD
,
503 rme96
->iobase
+ RME96_IO_CONTROL_REGISTER
);
504 writel(rme96
->wcreg
, rme96
->iobase
+ RME96_IO_CONTROL_REGISTER
);
508 snd_rme96_getmontracks(struct rme96
*rme96
)
510 return ((rme96
->wcreg
>> RME96_WCR_BITPOS_MONITOR_0
) & 1) +
511 (((rme96
->wcreg
>> RME96_WCR_BITPOS_MONITOR_1
) & 1) << 1);
515 snd_rme96_setmontracks(struct rme96
*rme96
,
519 rme96
->wcreg
|= RME96_WCR_MONITOR_0
;
521 rme96
->wcreg
&= ~RME96_WCR_MONITOR_0
;
524 rme96
->wcreg
|= RME96_WCR_MONITOR_1
;
526 rme96
->wcreg
&= ~RME96_WCR_MONITOR_1
;
528 writel(rme96
->wcreg
, rme96
->iobase
+ RME96_IO_CONTROL_REGISTER
);
533 snd_rme96_getattenuation(struct rme96
*rme96
)
535 return ((rme96
->wcreg
>> RME96_WCR_BITPOS_GAIN_0
) & 1) +
536 (((rme96
->wcreg
>> RME96_WCR_BITPOS_GAIN_1
) & 1) << 1);
540 snd_rme96_setattenuation(struct rme96
*rme96
,
543 switch (attenuation
) {
545 rme96
->wcreg
= (rme96
->wcreg
& ~RME96_WCR_GAIN_0
) &
549 rme96
->wcreg
= (rme96
->wcreg
| RME96_WCR_GAIN_0
) &
553 rme96
->wcreg
= (rme96
->wcreg
& ~RME96_WCR_GAIN_0
) |
557 rme96
->wcreg
= (rme96
->wcreg
| RME96_WCR_GAIN_0
) |
563 writel(rme96
->wcreg
, rme96
->iobase
+ RME96_IO_CONTROL_REGISTER
);
568 snd_rme96_capture_getrate(struct rme96
*rme96
,
574 if (rme96
->areg
& RME96_AR_ANALOG
) {
575 /* Analog input, overrides S/PDIF setting */
576 n
= ((rme96
->areg
>> RME96_AR_BITPOS_F0
) & 1) +
577 (((rme96
->areg
>> RME96_AR_BITPOS_F1
) & 1) << 1);
591 return (rme96
->areg
& RME96_AR_BITPOS_F2
) ? rate
<< 1 : rate
;
594 rme96
->rcreg
= readl(rme96
->iobase
+ RME96_IO_CONTROL_REGISTER
);
595 if (rme96
->rcreg
& RME96_RCR_LOCK
) {
598 if (rme96
->rcreg
& RME96_RCR_T_OUT
) {
604 if (rme96
->rcreg
& RME96_RCR_VERF
) {
609 n
= ((rme96
->rcreg
>> RME96_RCR_BITPOS_F0
) & 1) +
610 (((rme96
->rcreg
>> RME96_RCR_BITPOS_F1
) & 1) << 1) +
611 (((rme96
->rcreg
>> RME96_RCR_BITPOS_F2
) & 1) << 2);
615 if (rme96
->rcreg
& RME96_RCR_T_OUT
) {
619 case 3: return 96000;
620 case 4: return 88200;
621 case 5: return 48000;
622 case 6: return 44100;
623 case 7: return 32000;
631 snd_rme96_playback_getrate(struct rme96
*rme96
)
635 if (!(rme96
->wcreg
& RME96_WCR_MASTER
) &&
636 snd_rme96_getinputtype(rme96
) != RME96_INPUT_ANALOG
&&
637 (rate
= snd_rme96_capture_getrate(rme96
, &dummy
)) > 0)
642 rate
= ((rme96
->wcreg
>> RME96_WCR_BITPOS_FREQ_0
) & 1) +
643 (((rme96
->wcreg
>> RME96_WCR_BITPOS_FREQ_1
) & 1) << 1);
657 return (rme96
->wcreg
& RME96_WCR_DS
) ? rate
<< 1 : rate
;
661 snd_rme96_playback_setrate(struct rme96
*rme96
,
666 ds
= rme96
->wcreg
& RME96_WCR_DS
;
669 rme96
->wcreg
&= ~RME96_WCR_DS
;
670 rme96
->wcreg
= (rme96
->wcreg
| RME96_WCR_FREQ_0
) &
674 rme96
->wcreg
&= ~RME96_WCR_DS
;
675 rme96
->wcreg
= (rme96
->wcreg
| RME96_WCR_FREQ_1
) &
679 rme96
->wcreg
&= ~RME96_WCR_DS
;
680 rme96
->wcreg
= (rme96
->wcreg
| RME96_WCR_FREQ_0
) |
684 rme96
->wcreg
|= RME96_WCR_DS
;
685 rme96
->wcreg
= (rme96
->wcreg
| RME96_WCR_FREQ_0
) &
689 rme96
->wcreg
|= RME96_WCR_DS
;
690 rme96
->wcreg
= (rme96
->wcreg
| RME96_WCR_FREQ_1
) &
694 rme96
->wcreg
|= RME96_WCR_DS
;
695 rme96
->wcreg
= (rme96
->wcreg
| RME96_WCR_FREQ_0
) |
701 if ((!ds
&& rme96
->wcreg
& RME96_WCR_DS
) ||
702 (ds
&& !(rme96
->wcreg
& RME96_WCR_DS
)))
704 /* change to/from double-speed: reset the DAC (if available) */
705 snd_rme96_reset_dac(rme96
);
706 return 1; /* need to restore volume */
708 writel(rme96
->wcreg
, rme96
->iobase
+ RME96_IO_CONTROL_REGISTER
);
714 snd_rme96_capture_analog_setrate(struct rme96
*rme96
,
719 rme96
->areg
= ((rme96
->areg
| RME96_AR_FREQPAD_0
) &
720 ~RME96_AR_FREQPAD_1
) & ~RME96_AR_FREQPAD_2
;
723 rme96
->areg
= ((rme96
->areg
& ~RME96_AR_FREQPAD_0
) |
724 RME96_AR_FREQPAD_1
) & ~RME96_AR_FREQPAD_2
;
727 rme96
->areg
= ((rme96
->areg
| RME96_AR_FREQPAD_0
) |
728 RME96_AR_FREQPAD_1
) & ~RME96_AR_FREQPAD_2
;
731 if (rme96
->rev
< 4) {
734 rme96
->areg
= ((rme96
->areg
| RME96_AR_FREQPAD_0
) &
735 ~RME96_AR_FREQPAD_1
) | RME96_AR_FREQPAD_2
;
738 if (rme96
->rev
< 4) {
741 rme96
->areg
= ((rme96
->areg
& ~RME96_AR_FREQPAD_0
) |
742 RME96_AR_FREQPAD_1
) | RME96_AR_FREQPAD_2
;
745 rme96
->areg
= ((rme96
->areg
| RME96_AR_FREQPAD_0
) |
746 RME96_AR_FREQPAD_1
) | RME96_AR_FREQPAD_2
;
751 writel(rme96
->areg
, rme96
->iobase
+ RME96_IO_ADDITIONAL_REG
);
756 snd_rme96_setclockmode(struct rme96
*rme96
,
760 case RME96_CLOCKMODE_SLAVE
:
762 rme96
->wcreg
&= ~RME96_WCR_MASTER
;
763 rme96
->areg
&= ~RME96_AR_WSEL
;
765 case RME96_CLOCKMODE_MASTER
:
767 rme96
->wcreg
|= RME96_WCR_MASTER
;
768 rme96
->areg
&= ~RME96_AR_WSEL
;
770 case RME96_CLOCKMODE_WORDCLOCK
:
771 /* Word clock is a master mode */
772 rme96
->wcreg
|= RME96_WCR_MASTER
;
773 rme96
->areg
|= RME96_AR_WSEL
;
778 writel(rme96
->wcreg
, rme96
->iobase
+ RME96_IO_CONTROL_REGISTER
);
779 writel(rme96
->areg
, rme96
->iobase
+ RME96_IO_ADDITIONAL_REG
);
784 snd_rme96_getclockmode(struct rme96
*rme96
)
786 if (rme96
->areg
& RME96_AR_WSEL
) {
787 return RME96_CLOCKMODE_WORDCLOCK
;
789 return (rme96
->wcreg
& RME96_WCR_MASTER
) ? RME96_CLOCKMODE_MASTER
:
790 RME96_CLOCKMODE_SLAVE
;
794 snd_rme96_setinputtype(struct rme96
*rme96
,
800 case RME96_INPUT_OPTICAL
:
801 rme96
->wcreg
= (rme96
->wcreg
& ~RME96_WCR_INP_0
) &
804 case RME96_INPUT_COAXIAL
:
805 rme96
->wcreg
= (rme96
->wcreg
| RME96_WCR_INP_0
) &
808 case RME96_INPUT_INTERNAL
:
809 rme96
->wcreg
= (rme96
->wcreg
& ~RME96_WCR_INP_0
) |
812 case RME96_INPUT_XLR
:
813 if ((rme96
->pci
->device
!= PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST
&&
814 rme96
->pci
->device
!= PCI_DEVICE_ID_RME_DIGI96_8_PRO
) ||
815 (rme96
->pci
->device
== PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST
&&
818 /* Only Digi96/8 PRO and Digi96/8 PAD supports XLR */
821 rme96
->wcreg
= (rme96
->wcreg
| RME96_WCR_INP_0
) |
824 case RME96_INPUT_ANALOG
:
825 if (!RME96_HAS_ANALOG_IN(rme96
)) {
828 rme96
->areg
|= RME96_AR_ANALOG
;
829 writel(rme96
->areg
, rme96
->iobase
+ RME96_IO_ADDITIONAL_REG
);
830 if (rme96
->rev
< 4) {
832 * Revision less than 004 does not support 64 and
835 if (snd_rme96_capture_getrate(rme96
, &n
) == 88200) {
836 snd_rme96_capture_analog_setrate(rme96
, 44100);
838 if (snd_rme96_capture_getrate(rme96
, &n
) == 64000) {
839 snd_rme96_capture_analog_setrate(rme96
, 32000);
846 if (type
!= RME96_INPUT_ANALOG
&& RME96_HAS_ANALOG_IN(rme96
)) {
847 rme96
->areg
&= ~RME96_AR_ANALOG
;
848 writel(rme96
->areg
, rme96
->iobase
+ RME96_IO_ADDITIONAL_REG
);
850 writel(rme96
->wcreg
, rme96
->iobase
+ RME96_IO_CONTROL_REGISTER
);
855 snd_rme96_getinputtype(struct rme96
*rme96
)
857 if (rme96
->areg
& RME96_AR_ANALOG
) {
858 return RME96_INPUT_ANALOG
;
860 return ((rme96
->wcreg
>> RME96_WCR_BITPOS_INP_0
) & 1) +
861 (((rme96
->wcreg
>> RME96_WCR_BITPOS_INP_1
) & 1) << 1);
865 snd_rme96_setframelog(struct rme96
*rme96
,
871 if (n_channels
== 2) {
874 /* assume 8 channels */
878 frlog
+= (rme96
->wcreg
& RME96_WCR_MODE24
) ? 2 : 1;
879 rme96
->playback_frlog
= frlog
;
881 frlog
+= (rme96
->wcreg
& RME96_WCR_MODE24_2
) ? 2 : 1;
882 rme96
->capture_frlog
= frlog
;
887 snd_rme96_playback_setformat(struct rme96
*rme96
,
891 case SNDRV_PCM_FORMAT_S16_LE
:
892 rme96
->wcreg
&= ~RME96_WCR_MODE24
;
894 case SNDRV_PCM_FORMAT_S32_LE
:
895 rme96
->wcreg
|= RME96_WCR_MODE24
;
900 writel(rme96
->wcreg
, rme96
->iobase
+ RME96_IO_CONTROL_REGISTER
);
905 snd_rme96_capture_setformat(struct rme96
*rme96
,
909 case SNDRV_PCM_FORMAT_S16_LE
:
910 rme96
->wcreg
&= ~RME96_WCR_MODE24_2
;
912 case SNDRV_PCM_FORMAT_S32_LE
:
913 rme96
->wcreg
|= RME96_WCR_MODE24_2
;
918 writel(rme96
->wcreg
, rme96
->iobase
+ RME96_IO_CONTROL_REGISTER
);
923 snd_rme96_set_period_properties(struct rme96
*rme96
,
926 switch (period_bytes
) {
927 case RME96_LARGE_BLOCK_SIZE
:
928 rme96
->wcreg
&= ~RME96_WCR_ISEL
;
930 case RME96_SMALL_BLOCK_SIZE
:
931 rme96
->wcreg
|= RME96_WCR_ISEL
;
937 rme96
->wcreg
&= ~RME96_WCR_IDIS
;
938 writel(rme96
->wcreg
, rme96
->iobase
+ RME96_IO_CONTROL_REGISTER
);
942 snd_rme96_playback_hw_params(struct snd_pcm_substream
*substream
,
943 struct snd_pcm_hw_params
*params
)
945 struct rme96
*rme96
= snd_pcm_substream_chip(substream
);
946 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
947 int err
, rate
, dummy
;
948 bool apply_dac_volume
= false;
950 runtime
->dma_area
= (void __force
*)(rme96
->iobase
+
951 RME96_IO_PLAY_BUFFER
);
952 runtime
->dma_addr
= rme96
->port
+ RME96_IO_PLAY_BUFFER
;
953 runtime
->dma_bytes
= RME96_BUFFER_SIZE
;
955 spin_lock_irq(&rme96
->lock
);
956 if (!(rme96
->wcreg
& RME96_WCR_MASTER
) &&
957 snd_rme96_getinputtype(rme96
) != RME96_INPUT_ANALOG
&&
958 (rate
= snd_rme96_capture_getrate(rme96
, &dummy
)) > 0)
961 if ((int)params_rate(params
) != rate
) {
966 err
= snd_rme96_playback_setrate(rme96
, params_rate(params
));
969 apply_dac_volume
= err
> 0; /* need to restore volume later? */
972 err
= snd_rme96_playback_setformat(rme96
, params_format(params
));
975 snd_rme96_setframelog(rme96
, params_channels(params
), 1);
976 if (rme96
->capture_periodsize
!= 0) {
977 if (params_period_size(params
) << rme96
->playback_frlog
!=
978 rme96
->capture_periodsize
)
984 rme96
->playback_periodsize
=
985 params_period_size(params
) << rme96
->playback_frlog
;
986 snd_rme96_set_period_properties(rme96
, rme96
->playback_periodsize
);
988 if ((rme96
->wcreg
& RME96_WCR_ADAT
) == 0) {
989 rme96
->wcreg
&= ~(RME96_WCR_PRO
| RME96_WCR_DOLBY
| RME96_WCR_EMP
);
990 writel(rme96
->wcreg
|= rme96
->wcreg_spdif_stream
, rme96
->iobase
+ RME96_IO_CONTROL_REGISTER
);
995 spin_unlock_irq(&rme96
->lock
);
996 if (apply_dac_volume
) {
997 usleep_range(3000, 10000);
998 snd_rme96_apply_dac_volume(rme96
);
1005 snd_rme96_capture_hw_params(struct snd_pcm_substream
*substream
,
1006 struct snd_pcm_hw_params
*params
)
1008 struct rme96
*rme96
= snd_pcm_substream_chip(substream
);
1009 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1010 int err
, isadat
, rate
;
1012 runtime
->dma_area
= (void __force
*)(rme96
->iobase
+
1013 RME96_IO_REC_BUFFER
);
1014 runtime
->dma_addr
= rme96
->port
+ RME96_IO_REC_BUFFER
;
1015 runtime
->dma_bytes
= RME96_BUFFER_SIZE
;
1017 spin_lock_irq(&rme96
->lock
);
1018 if ((err
= snd_rme96_capture_setformat(rme96
, params_format(params
))) < 0) {
1019 spin_unlock_irq(&rme96
->lock
);
1022 if (snd_rme96_getinputtype(rme96
) == RME96_INPUT_ANALOG
) {
1023 if ((err
= snd_rme96_capture_analog_setrate(rme96
,
1024 params_rate(params
))) < 0)
1026 spin_unlock_irq(&rme96
->lock
);
1029 } else if ((rate
= snd_rme96_capture_getrate(rme96
, &isadat
)) > 0) {
1030 if ((int)params_rate(params
) != rate
) {
1031 spin_unlock_irq(&rme96
->lock
);
1034 if ((isadat
&& runtime
->hw
.channels_min
== 2) ||
1035 (!isadat
&& runtime
->hw
.channels_min
== 8))
1037 spin_unlock_irq(&rme96
->lock
);
1041 snd_rme96_setframelog(rme96
, params_channels(params
), 0);
1042 if (rme96
->playback_periodsize
!= 0) {
1043 if (params_period_size(params
) << rme96
->capture_frlog
!=
1044 rme96
->playback_periodsize
)
1046 spin_unlock_irq(&rme96
->lock
);
1050 rme96
->capture_periodsize
=
1051 params_period_size(params
) << rme96
->capture_frlog
;
1052 snd_rme96_set_period_properties(rme96
, rme96
->capture_periodsize
);
1053 spin_unlock_irq(&rme96
->lock
);
1059 snd_rme96_playback_start(struct rme96
*rme96
,
1063 writel(0, rme96
->iobase
+ RME96_IO_RESET_PLAY_POS
);
1066 rme96
->wcreg
|= RME96_WCR_START
;
1067 writel(rme96
->wcreg
, rme96
->iobase
+ RME96_IO_CONTROL_REGISTER
);
1071 snd_rme96_capture_start(struct rme96
*rme96
,
1075 writel(0, rme96
->iobase
+ RME96_IO_RESET_REC_POS
);
1078 rme96
->wcreg
|= RME96_WCR_START_2
;
1079 writel(rme96
->wcreg
, rme96
->iobase
+ RME96_IO_CONTROL_REGISTER
);
1083 snd_rme96_playback_stop(struct rme96
*rme96
)
1086 * Check if there is an unconfirmed IRQ, if so confirm it, or else
1087 * the hardware will not stop generating interrupts
1089 rme96
->rcreg
= readl(rme96
->iobase
+ RME96_IO_CONTROL_REGISTER
);
1090 if (rme96
->rcreg
& RME96_RCR_IRQ
) {
1091 writel(0, rme96
->iobase
+ RME96_IO_CONFIRM_PLAY_IRQ
);
1093 rme96
->wcreg
&= ~RME96_WCR_START
;
1094 writel(rme96
->wcreg
, rme96
->iobase
+ RME96_IO_CONTROL_REGISTER
);
1098 snd_rme96_capture_stop(struct rme96
*rme96
)
1100 rme96
->rcreg
= readl(rme96
->iobase
+ RME96_IO_CONTROL_REGISTER
);
1101 if (rme96
->rcreg
& RME96_RCR_IRQ_2
) {
1102 writel(0, rme96
->iobase
+ RME96_IO_CONFIRM_REC_IRQ
);
1104 rme96
->wcreg
&= ~RME96_WCR_START_2
;
1105 writel(rme96
->wcreg
, rme96
->iobase
+ RME96_IO_CONTROL_REGISTER
);
1109 snd_rme96_interrupt(int irq
,
1112 struct rme96
*rme96
= (struct rme96
*)dev_id
;
1114 rme96
->rcreg
= readl(rme96
->iobase
+ RME96_IO_CONTROL_REGISTER
);
1115 /* fastpath out, to ease interrupt sharing */
1116 if (!((rme96
->rcreg
& RME96_RCR_IRQ
) ||
1117 (rme96
->rcreg
& RME96_RCR_IRQ_2
)))
1122 if (rme96
->rcreg
& RME96_RCR_IRQ
) {
1124 snd_pcm_period_elapsed(rme96
->playback_substream
);
1125 writel(0, rme96
->iobase
+ RME96_IO_CONFIRM_PLAY_IRQ
);
1127 if (rme96
->rcreg
& RME96_RCR_IRQ_2
) {
1129 snd_pcm_period_elapsed(rme96
->capture_substream
);
1130 writel(0, rme96
->iobase
+ RME96_IO_CONFIRM_REC_IRQ
);
1135 static unsigned int period_bytes
[] = { RME96_SMALL_BLOCK_SIZE
, RME96_LARGE_BLOCK_SIZE
};
1137 static struct snd_pcm_hw_constraint_list hw_constraints_period_bytes
= {
1138 .count
= ARRAY_SIZE(period_bytes
),
1139 .list
= period_bytes
,
1144 rme96_set_buffer_size_constraint(struct rme96
*rme96
,
1145 struct snd_pcm_runtime
*runtime
)
1149 snd_pcm_hw_constraint_minmax(runtime
, SNDRV_PCM_HW_PARAM_BUFFER_BYTES
,
1150 RME96_BUFFER_SIZE
, RME96_BUFFER_SIZE
);
1151 if ((size
= rme96
->playback_periodsize
) != 0 ||
1152 (size
= rme96
->capture_periodsize
) != 0)
1153 snd_pcm_hw_constraint_minmax(runtime
,
1154 SNDRV_PCM_HW_PARAM_PERIOD_BYTES
,
1157 snd_pcm_hw_constraint_list(runtime
, 0,
1158 SNDRV_PCM_HW_PARAM_PERIOD_BYTES
,
1159 &hw_constraints_period_bytes
);
1163 snd_rme96_playback_spdif_open(struct snd_pcm_substream
*substream
)
1166 struct rme96
*rme96
= snd_pcm_substream_chip(substream
);
1167 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1169 spin_lock_irq(&rme96
->lock
);
1170 if (rme96
->playback_substream
!= NULL
) {
1171 spin_unlock_irq(&rme96
->lock
);
1174 rme96
->wcreg
&= ~RME96_WCR_ADAT
;
1175 writel(rme96
->wcreg
, rme96
->iobase
+ RME96_IO_CONTROL_REGISTER
);
1176 rme96
->playback_substream
= substream
;
1177 spin_unlock_irq(&rme96
->lock
);
1179 runtime
->hw
= snd_rme96_playback_spdif_info
;
1180 if (!(rme96
->wcreg
& RME96_WCR_MASTER
) &&
1181 snd_rme96_getinputtype(rme96
) != RME96_INPUT_ANALOG
&&
1182 (rate
= snd_rme96_capture_getrate(rme96
, &dummy
)) > 0)
1185 runtime
->hw
.rates
= snd_pcm_rate_to_rate_bit(rate
);
1186 runtime
->hw
.rate_min
= rate
;
1187 runtime
->hw
.rate_max
= rate
;
1189 rme96_set_buffer_size_constraint(rme96
, runtime
);
1191 rme96
->wcreg_spdif_stream
= rme96
->wcreg_spdif
;
1192 rme96
->spdif_ctl
->vd
[0].access
&= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE
;
1193 snd_ctl_notify(rme96
->card
, SNDRV_CTL_EVENT_MASK_VALUE
|
1194 SNDRV_CTL_EVENT_MASK_INFO
, &rme96
->spdif_ctl
->id
);
1199 snd_rme96_capture_spdif_open(struct snd_pcm_substream
*substream
)
1202 struct rme96
*rme96
= snd_pcm_substream_chip(substream
);
1203 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1205 runtime
->hw
= snd_rme96_capture_spdif_info
;
1206 if (snd_rme96_getinputtype(rme96
) != RME96_INPUT_ANALOG
&&
1207 (rate
= snd_rme96_capture_getrate(rme96
, &isadat
)) > 0)
1212 runtime
->hw
.rates
= snd_pcm_rate_to_rate_bit(rate
);
1213 runtime
->hw
.rate_min
= rate
;
1214 runtime
->hw
.rate_max
= rate
;
1217 spin_lock_irq(&rme96
->lock
);
1218 if (rme96
->capture_substream
!= NULL
) {
1219 spin_unlock_irq(&rme96
->lock
);
1222 rme96
->capture_substream
= substream
;
1223 spin_unlock_irq(&rme96
->lock
);
1225 rme96_set_buffer_size_constraint(rme96
, runtime
);
1230 snd_rme96_playback_adat_open(struct snd_pcm_substream
*substream
)
1233 struct rme96
*rme96
= snd_pcm_substream_chip(substream
);
1234 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1236 spin_lock_irq(&rme96
->lock
);
1237 if (rme96
->playback_substream
!= NULL
) {
1238 spin_unlock_irq(&rme96
->lock
);
1241 rme96
->wcreg
|= RME96_WCR_ADAT
;
1242 writel(rme96
->wcreg
, rme96
->iobase
+ RME96_IO_CONTROL_REGISTER
);
1243 rme96
->playback_substream
= substream
;
1244 spin_unlock_irq(&rme96
->lock
);
1246 runtime
->hw
= snd_rme96_playback_adat_info
;
1247 if (!(rme96
->wcreg
& RME96_WCR_MASTER
) &&
1248 snd_rme96_getinputtype(rme96
) != RME96_INPUT_ANALOG
&&
1249 (rate
= snd_rme96_capture_getrate(rme96
, &dummy
)) > 0)
1252 runtime
->hw
.rates
= snd_pcm_rate_to_rate_bit(rate
);
1253 runtime
->hw
.rate_min
= rate
;
1254 runtime
->hw
.rate_max
= rate
;
1256 rme96_set_buffer_size_constraint(rme96
, runtime
);
1261 snd_rme96_capture_adat_open(struct snd_pcm_substream
*substream
)
1264 struct rme96
*rme96
= snd_pcm_substream_chip(substream
);
1265 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1267 runtime
->hw
= snd_rme96_capture_adat_info
;
1268 if (snd_rme96_getinputtype(rme96
) == RME96_INPUT_ANALOG
) {
1269 /* makes no sense to use analog input. Note that analog
1270 expension cards AEB4/8-I are RME96_INPUT_INTERNAL */
1273 if ((rate
= snd_rme96_capture_getrate(rme96
, &isadat
)) > 0) {
1277 runtime
->hw
.rates
= snd_pcm_rate_to_rate_bit(rate
);
1278 runtime
->hw
.rate_min
= rate
;
1279 runtime
->hw
.rate_max
= rate
;
1282 spin_lock_irq(&rme96
->lock
);
1283 if (rme96
->capture_substream
!= NULL
) {
1284 spin_unlock_irq(&rme96
->lock
);
1287 rme96
->capture_substream
= substream
;
1288 spin_unlock_irq(&rme96
->lock
);
1290 rme96_set_buffer_size_constraint(rme96
, runtime
);
1295 snd_rme96_playback_close(struct snd_pcm_substream
*substream
)
1297 struct rme96
*rme96
= snd_pcm_substream_chip(substream
);
1300 spin_lock_irq(&rme96
->lock
);
1301 if (RME96_ISPLAYING(rme96
)) {
1302 snd_rme96_playback_stop(rme96
);
1304 rme96
->playback_substream
= NULL
;
1305 rme96
->playback_periodsize
= 0;
1306 spdif
= (rme96
->wcreg
& RME96_WCR_ADAT
) == 0;
1307 spin_unlock_irq(&rme96
->lock
);
1309 rme96
->spdif_ctl
->vd
[0].access
|= SNDRV_CTL_ELEM_ACCESS_INACTIVE
;
1310 snd_ctl_notify(rme96
->card
, SNDRV_CTL_EVENT_MASK_VALUE
|
1311 SNDRV_CTL_EVENT_MASK_INFO
, &rme96
->spdif_ctl
->id
);
1317 snd_rme96_capture_close(struct snd_pcm_substream
*substream
)
1319 struct rme96
*rme96
= snd_pcm_substream_chip(substream
);
1321 spin_lock_irq(&rme96
->lock
);
1322 if (RME96_ISRECORDING(rme96
)) {
1323 snd_rme96_capture_stop(rme96
);
1325 rme96
->capture_substream
= NULL
;
1326 rme96
->capture_periodsize
= 0;
1327 spin_unlock_irq(&rme96
->lock
);
1332 snd_rme96_playback_prepare(struct snd_pcm_substream
*substream
)
1334 struct rme96
*rme96
= snd_pcm_substream_chip(substream
);
1336 spin_lock_irq(&rme96
->lock
);
1337 if (RME96_ISPLAYING(rme96
)) {
1338 snd_rme96_playback_stop(rme96
);
1340 writel(0, rme96
->iobase
+ RME96_IO_RESET_PLAY_POS
);
1341 spin_unlock_irq(&rme96
->lock
);
1346 snd_rme96_capture_prepare(struct snd_pcm_substream
*substream
)
1348 struct rme96
*rme96
= snd_pcm_substream_chip(substream
);
1350 spin_lock_irq(&rme96
->lock
);
1351 if (RME96_ISRECORDING(rme96
)) {
1352 snd_rme96_capture_stop(rme96
);
1354 writel(0, rme96
->iobase
+ RME96_IO_RESET_REC_POS
);
1355 spin_unlock_irq(&rme96
->lock
);
1360 snd_rme96_playback_trigger(struct snd_pcm_substream
*substream
,
1363 struct rme96
*rme96
= snd_pcm_substream_chip(substream
);
1366 case SNDRV_PCM_TRIGGER_START
:
1367 if (!RME96_ISPLAYING(rme96
)) {
1368 if (substream
!= rme96
->playback_substream
) {
1371 snd_rme96_playback_start(rme96
, 0);
1375 case SNDRV_PCM_TRIGGER_STOP
:
1376 if (RME96_ISPLAYING(rme96
)) {
1377 if (substream
!= rme96
->playback_substream
) {
1380 snd_rme96_playback_stop(rme96
);
1384 case SNDRV_PCM_TRIGGER_PAUSE_PUSH
:
1385 if (RME96_ISPLAYING(rme96
)) {
1386 snd_rme96_playback_stop(rme96
);
1390 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE
:
1391 if (!RME96_ISPLAYING(rme96
)) {
1392 snd_rme96_playback_start(rme96
, 1);
1403 snd_rme96_capture_trigger(struct snd_pcm_substream
*substream
,
1406 struct rme96
*rme96
= snd_pcm_substream_chip(substream
);
1409 case SNDRV_PCM_TRIGGER_START
:
1410 if (!RME96_ISRECORDING(rme96
)) {
1411 if (substream
!= rme96
->capture_substream
) {
1414 snd_rme96_capture_start(rme96
, 0);
1418 case SNDRV_PCM_TRIGGER_STOP
:
1419 if (RME96_ISRECORDING(rme96
)) {
1420 if (substream
!= rme96
->capture_substream
) {
1423 snd_rme96_capture_stop(rme96
);
1427 case SNDRV_PCM_TRIGGER_PAUSE_PUSH
:
1428 if (RME96_ISRECORDING(rme96
)) {
1429 snd_rme96_capture_stop(rme96
);
1433 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE
:
1434 if (!RME96_ISRECORDING(rme96
)) {
1435 snd_rme96_capture_start(rme96
, 1);
1446 static snd_pcm_uframes_t
1447 snd_rme96_playback_pointer(struct snd_pcm_substream
*substream
)
1449 struct rme96
*rme96
= snd_pcm_substream_chip(substream
);
1450 return snd_rme96_playback_ptr(rme96
);
1453 static snd_pcm_uframes_t
1454 snd_rme96_capture_pointer(struct snd_pcm_substream
*substream
)
1456 struct rme96
*rme96
= snd_pcm_substream_chip(substream
);
1457 return snd_rme96_capture_ptr(rme96
);
1460 static struct snd_pcm_ops snd_rme96_playback_spdif_ops
= {
1461 .open
= snd_rme96_playback_spdif_open
,
1462 .close
= snd_rme96_playback_close
,
1463 .ioctl
= snd_pcm_lib_ioctl
,
1464 .hw_params
= snd_rme96_playback_hw_params
,
1465 .prepare
= snd_rme96_playback_prepare
,
1466 .trigger
= snd_rme96_playback_trigger
,
1467 .pointer
= snd_rme96_playback_pointer
,
1468 .copy
= snd_rme96_playback_copy
,
1469 .silence
= snd_rme96_playback_silence
,
1470 .mmap
= snd_pcm_lib_mmap_iomem
,
1473 static struct snd_pcm_ops snd_rme96_capture_spdif_ops
= {
1474 .open
= snd_rme96_capture_spdif_open
,
1475 .close
= snd_rme96_capture_close
,
1476 .ioctl
= snd_pcm_lib_ioctl
,
1477 .hw_params
= snd_rme96_capture_hw_params
,
1478 .prepare
= snd_rme96_capture_prepare
,
1479 .trigger
= snd_rme96_capture_trigger
,
1480 .pointer
= snd_rme96_capture_pointer
,
1481 .copy
= snd_rme96_capture_copy
,
1482 .mmap
= snd_pcm_lib_mmap_iomem
,
1485 static struct snd_pcm_ops snd_rme96_playback_adat_ops
= {
1486 .open
= snd_rme96_playback_adat_open
,
1487 .close
= snd_rme96_playback_close
,
1488 .ioctl
= snd_pcm_lib_ioctl
,
1489 .hw_params
= snd_rme96_playback_hw_params
,
1490 .prepare
= snd_rme96_playback_prepare
,
1491 .trigger
= snd_rme96_playback_trigger
,
1492 .pointer
= snd_rme96_playback_pointer
,
1493 .copy
= snd_rme96_playback_copy
,
1494 .silence
= snd_rme96_playback_silence
,
1495 .mmap
= snd_pcm_lib_mmap_iomem
,
1498 static struct snd_pcm_ops snd_rme96_capture_adat_ops
= {
1499 .open
= snd_rme96_capture_adat_open
,
1500 .close
= snd_rme96_capture_close
,
1501 .ioctl
= snd_pcm_lib_ioctl
,
1502 .hw_params
= snd_rme96_capture_hw_params
,
1503 .prepare
= snd_rme96_capture_prepare
,
1504 .trigger
= snd_rme96_capture_trigger
,
1505 .pointer
= snd_rme96_capture_pointer
,
1506 .copy
= snd_rme96_capture_copy
,
1507 .mmap
= snd_pcm_lib_mmap_iomem
,
1511 snd_rme96_free(void *private_data
)
1513 struct rme96
*rme96
= (struct rme96
*)private_data
;
1515 if (rme96
== NULL
) {
1518 if (rme96
->irq
>= 0) {
1519 snd_rme96_playback_stop(rme96
);
1520 snd_rme96_capture_stop(rme96
);
1521 rme96
->areg
&= ~RME96_AR_DAC_EN
;
1522 writel(rme96
->areg
, rme96
->iobase
+ RME96_IO_ADDITIONAL_REG
);
1523 free_irq(rme96
->irq
, (void *)rme96
);
1526 if (rme96
->iobase
) {
1527 iounmap(rme96
->iobase
);
1528 rme96
->iobase
= NULL
;
1531 pci_release_regions(rme96
->pci
);
1534 pci_disable_device(rme96
->pci
);
1538 snd_rme96_free_spdif_pcm(struct snd_pcm
*pcm
)
1540 struct rme96
*rme96
= pcm
->private_data
;
1541 rme96
->spdif_pcm
= NULL
;
1545 snd_rme96_free_adat_pcm(struct snd_pcm
*pcm
)
1547 struct rme96
*rme96
= pcm
->private_data
;
1548 rme96
->adat_pcm
= NULL
;
1552 snd_rme96_create(struct rme96
*rme96
)
1554 struct pci_dev
*pci
= rme96
->pci
;
1558 spin_lock_init(&rme96
->lock
);
1560 if ((err
= pci_enable_device(pci
)) < 0)
1563 if ((err
= pci_request_regions(pci
, "RME96")) < 0)
1565 rme96
->port
= pci_resource_start(rme96
->pci
, 0);
1567 rme96
->iobase
= ioremap_nocache(rme96
->port
, RME96_IO_SIZE
);
1568 if (!rme96
->iobase
) {
1569 snd_printk(KERN_ERR
"unable to remap memory region 0x%lx-0x%lx\n", rme96
->port
, rme96
->port
+ RME96_IO_SIZE
- 1);
1573 if (request_irq(pci
->irq
, snd_rme96_interrupt
, IRQF_SHARED
,
1574 KBUILD_MODNAME
, rme96
)) {
1575 snd_printk(KERN_ERR
"unable to grab IRQ %d\n", pci
->irq
);
1578 rme96
->irq
= pci
->irq
;
1580 /* read the card's revision number */
1581 pci_read_config_byte(pci
, 8, &rme96
->rev
);
1583 /* set up ALSA pcm device for S/PDIF */
1584 if ((err
= snd_pcm_new(rme96
->card
, "Digi96 IEC958", 0,
1585 1, 1, &rme96
->spdif_pcm
)) < 0)
1589 rme96
->spdif_pcm
->private_data
= rme96
;
1590 rme96
->spdif_pcm
->private_free
= snd_rme96_free_spdif_pcm
;
1591 strcpy(rme96
->spdif_pcm
->name
, "Digi96 IEC958");
1592 snd_pcm_set_ops(rme96
->spdif_pcm
, SNDRV_PCM_STREAM_PLAYBACK
, &snd_rme96_playback_spdif_ops
);
1593 snd_pcm_set_ops(rme96
->spdif_pcm
, SNDRV_PCM_STREAM_CAPTURE
, &snd_rme96_capture_spdif_ops
);
1595 rme96
->spdif_pcm
->info_flags
= 0;
1597 /* set up ALSA pcm device for ADAT */
1598 if (pci
->device
== PCI_DEVICE_ID_RME_DIGI96
) {
1599 /* ADAT is not available on the base model */
1600 rme96
->adat_pcm
= NULL
;
1602 if ((err
= snd_pcm_new(rme96
->card
, "Digi96 ADAT", 1,
1603 1, 1, &rme96
->adat_pcm
)) < 0)
1607 rme96
->adat_pcm
->private_data
= rme96
;
1608 rme96
->adat_pcm
->private_free
= snd_rme96_free_adat_pcm
;
1609 strcpy(rme96
->adat_pcm
->name
, "Digi96 ADAT");
1610 snd_pcm_set_ops(rme96
->adat_pcm
, SNDRV_PCM_STREAM_PLAYBACK
, &snd_rme96_playback_adat_ops
);
1611 snd_pcm_set_ops(rme96
->adat_pcm
, SNDRV_PCM_STREAM_CAPTURE
, &snd_rme96_capture_adat_ops
);
1613 rme96
->adat_pcm
->info_flags
= 0;
1616 rme96
->playback_periodsize
= 0;
1617 rme96
->capture_periodsize
= 0;
1619 /* make sure playback/capture is stopped, if by some reason active */
1620 snd_rme96_playback_stop(rme96
);
1621 snd_rme96_capture_stop(rme96
);
1623 /* set default values in registers */
1625 RME96_WCR_FREQ_1
| /* set 44.1 kHz playback */
1626 RME96_WCR_SEL
| /* normal playback */
1627 RME96_WCR_MASTER
| /* set to master clock mode */
1628 RME96_WCR_INP_0
; /* set coaxial input */
1630 rme96
->areg
= RME96_AR_FREQPAD_1
; /* set 44.1 kHz analog capture */
1632 writel(rme96
->wcreg
, rme96
->iobase
+ RME96_IO_CONTROL_REGISTER
);
1633 writel(rme96
->areg
, rme96
->iobase
+ RME96_IO_ADDITIONAL_REG
);
1636 writel(rme96
->areg
| RME96_AR_PD2
,
1637 rme96
->iobase
+ RME96_IO_ADDITIONAL_REG
);
1638 writel(rme96
->areg
, rme96
->iobase
+ RME96_IO_ADDITIONAL_REG
);
1640 /* reset and enable the DAC (order is important). */
1641 snd_rme96_reset_dac(rme96
);
1642 rme96
->areg
|= RME96_AR_DAC_EN
;
1643 writel(rme96
->areg
, rme96
->iobase
+ RME96_IO_ADDITIONAL_REG
);
1645 /* reset playback and record buffer pointers */
1646 writel(0, rme96
->iobase
+ RME96_IO_RESET_PLAY_POS
);
1647 writel(0, rme96
->iobase
+ RME96_IO_RESET_REC_POS
);
1650 rme96
->vol
[0] = rme96
->vol
[1] = 0;
1651 if (RME96_HAS_ANALOG_OUT(rme96
)) {
1652 snd_rme96_apply_dac_volume(rme96
);
1655 /* init switch interface */
1656 if ((err
= snd_rme96_create_switches(rme96
->card
, rme96
)) < 0) {
1660 /* init proc interface */
1661 snd_rme96_proc_init(rme96
);
1671 snd_rme96_proc_read(struct snd_info_entry
*entry
, struct snd_info_buffer
*buffer
)
1674 struct rme96
*rme96
= entry
->private_data
;
1676 rme96
->rcreg
= readl(rme96
->iobase
+ RME96_IO_CONTROL_REGISTER
);
1678 snd_iprintf(buffer
, rme96
->card
->longname
);
1679 snd_iprintf(buffer
, " (index #%d)\n", rme96
->card
->number
+ 1);
1681 snd_iprintf(buffer
, "\nGeneral settings\n");
1682 if (rme96
->wcreg
& RME96_WCR_IDIS
) {
1683 snd_iprintf(buffer
, " period size: N/A (interrupts "
1685 } else if (rme96
->wcreg
& RME96_WCR_ISEL
) {
1686 snd_iprintf(buffer
, " period size: 2048 bytes\n");
1688 snd_iprintf(buffer
, " period size: 8192 bytes\n");
1690 snd_iprintf(buffer
, "\nInput settings\n");
1691 switch (snd_rme96_getinputtype(rme96
)) {
1692 case RME96_INPUT_OPTICAL
:
1693 snd_iprintf(buffer
, " input: optical");
1695 case RME96_INPUT_COAXIAL
:
1696 snd_iprintf(buffer
, " input: coaxial");
1698 case RME96_INPUT_INTERNAL
:
1699 snd_iprintf(buffer
, " input: internal");
1701 case RME96_INPUT_XLR
:
1702 snd_iprintf(buffer
, " input: XLR");
1704 case RME96_INPUT_ANALOG
:
1705 snd_iprintf(buffer
, " input: analog");
1708 if (snd_rme96_capture_getrate(rme96
, &n
) < 0) {
1709 snd_iprintf(buffer
, "\n sample rate: no valid signal\n");
1712 snd_iprintf(buffer
, " (8 channels)\n");
1714 snd_iprintf(buffer
, " (2 channels)\n");
1716 snd_iprintf(buffer
, " sample rate: %d Hz\n",
1717 snd_rme96_capture_getrate(rme96
, &n
));
1719 if (rme96
->wcreg
& RME96_WCR_MODE24_2
) {
1720 snd_iprintf(buffer
, " sample format: 24 bit\n");
1722 snd_iprintf(buffer
, " sample format: 16 bit\n");
1725 snd_iprintf(buffer
, "\nOutput settings\n");
1726 if (rme96
->wcreg
& RME96_WCR_SEL
) {
1727 snd_iprintf(buffer
, " output signal: normal playback\n");
1729 snd_iprintf(buffer
, " output signal: same as input\n");
1731 snd_iprintf(buffer
, " sample rate: %d Hz\n",
1732 snd_rme96_playback_getrate(rme96
));
1733 if (rme96
->wcreg
& RME96_WCR_MODE24
) {
1734 snd_iprintf(buffer
, " sample format: 24 bit\n");
1736 snd_iprintf(buffer
, " sample format: 16 bit\n");
1738 if (rme96
->areg
& RME96_AR_WSEL
) {
1739 snd_iprintf(buffer
, " sample clock source: word clock\n");
1740 } else if (rme96
->wcreg
& RME96_WCR_MASTER
) {
1741 snd_iprintf(buffer
, " sample clock source: internal\n");
1742 } else if (snd_rme96_getinputtype(rme96
) == RME96_INPUT_ANALOG
) {
1743 snd_iprintf(buffer
, " sample clock source: autosync (internal anyway due to analog input setting)\n");
1744 } else if (snd_rme96_capture_getrate(rme96
, &n
) < 0) {
1745 snd_iprintf(buffer
, " sample clock source: autosync (internal anyway due to no valid signal)\n");
1747 snd_iprintf(buffer
, " sample clock source: autosync\n");
1749 if (rme96
->wcreg
& RME96_WCR_PRO
) {
1750 snd_iprintf(buffer
, " format: AES/EBU (professional)\n");
1752 snd_iprintf(buffer
, " format: IEC958 (consumer)\n");
1754 if (rme96
->wcreg
& RME96_WCR_EMP
) {
1755 snd_iprintf(buffer
, " emphasis: on\n");
1757 snd_iprintf(buffer
, " emphasis: off\n");
1759 if (rme96
->wcreg
& RME96_WCR_DOLBY
) {
1760 snd_iprintf(buffer
, " non-audio (dolby): on\n");
1762 snd_iprintf(buffer
, " non-audio (dolby): off\n");
1764 if (RME96_HAS_ANALOG_IN(rme96
)) {
1765 snd_iprintf(buffer
, "\nAnalog output settings\n");
1766 switch (snd_rme96_getmontracks(rme96
)) {
1767 case RME96_MONITOR_TRACKS_1_2
:
1768 snd_iprintf(buffer
, " monitored ADAT tracks: 1+2\n");
1770 case RME96_MONITOR_TRACKS_3_4
:
1771 snd_iprintf(buffer
, " monitored ADAT tracks: 3+4\n");
1773 case RME96_MONITOR_TRACKS_5_6
:
1774 snd_iprintf(buffer
, " monitored ADAT tracks: 5+6\n");
1776 case RME96_MONITOR_TRACKS_7_8
:
1777 snd_iprintf(buffer
, " monitored ADAT tracks: 7+8\n");
1780 switch (snd_rme96_getattenuation(rme96
)) {
1781 case RME96_ATTENUATION_0
:
1782 snd_iprintf(buffer
, " attenuation: 0 dB\n");
1784 case RME96_ATTENUATION_6
:
1785 snd_iprintf(buffer
, " attenuation: -6 dB\n");
1787 case RME96_ATTENUATION_12
:
1788 snd_iprintf(buffer
, " attenuation: -12 dB\n");
1790 case RME96_ATTENUATION_18
:
1791 snd_iprintf(buffer
, " attenuation: -18 dB\n");
1794 snd_iprintf(buffer
, " volume left: %u\n", rme96
->vol
[0]);
1795 snd_iprintf(buffer
, " volume right: %u\n", rme96
->vol
[1]);
1799 static void snd_rme96_proc_init(struct rme96
*rme96
)
1801 struct snd_info_entry
*entry
;
1803 if (! snd_card_proc_new(rme96
->card
, "rme96", &entry
))
1804 snd_info_set_text_ops(entry
, rme96
, snd_rme96_proc_read
);
1811 #define snd_rme96_info_loopback_control snd_ctl_boolean_mono_info
1814 snd_rme96_get_loopback_control(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
1816 struct rme96
*rme96
= snd_kcontrol_chip(kcontrol
);
1818 spin_lock_irq(&rme96
->lock
);
1819 ucontrol
->value
.integer
.value
[0] = rme96
->wcreg
& RME96_WCR_SEL
? 0 : 1;
1820 spin_unlock_irq(&rme96
->lock
);
1824 snd_rme96_put_loopback_control(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
1826 struct rme96
*rme96
= snd_kcontrol_chip(kcontrol
);
1830 val
= ucontrol
->value
.integer
.value
[0] ? 0 : RME96_WCR_SEL
;
1831 spin_lock_irq(&rme96
->lock
);
1832 val
= (rme96
->wcreg
& ~RME96_WCR_SEL
) | val
;
1833 change
= val
!= rme96
->wcreg
;
1835 writel(val
, rme96
->iobase
+ RME96_IO_CONTROL_REGISTER
);
1836 spin_unlock_irq(&rme96
->lock
);
1841 snd_rme96_info_inputtype_control(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_info
*uinfo
)
1843 static char *_texts
[5] = { "Optical", "Coaxial", "Internal", "XLR", "Analog" };
1844 struct rme96
*rme96
= snd_kcontrol_chip(kcontrol
);
1845 char *texts
[5] = { _texts
[0], _texts
[1], _texts
[2], _texts
[3], _texts
[4] };
1847 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_ENUMERATED
;
1849 switch (rme96
->pci
->device
) {
1850 case PCI_DEVICE_ID_RME_DIGI96
:
1851 case PCI_DEVICE_ID_RME_DIGI96_8
:
1852 uinfo
->value
.enumerated
.items
= 3;
1854 case PCI_DEVICE_ID_RME_DIGI96_8_PRO
:
1855 uinfo
->value
.enumerated
.items
= 4;
1857 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST
:
1858 if (rme96
->rev
> 4) {
1860 uinfo
->value
.enumerated
.items
= 4;
1861 texts
[3] = _texts
[4]; /* Analog instead of XLR */
1864 uinfo
->value
.enumerated
.items
= 5;
1871 if (uinfo
->value
.enumerated
.item
> uinfo
->value
.enumerated
.items
- 1) {
1872 uinfo
->value
.enumerated
.item
= uinfo
->value
.enumerated
.items
- 1;
1874 strcpy(uinfo
->value
.enumerated
.name
, texts
[uinfo
->value
.enumerated
.item
]);
1878 snd_rme96_get_inputtype_control(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
1880 struct rme96
*rme96
= snd_kcontrol_chip(kcontrol
);
1881 unsigned int items
= 3;
1883 spin_lock_irq(&rme96
->lock
);
1884 ucontrol
->value
.enumerated
.item
[0] = snd_rme96_getinputtype(rme96
);
1886 switch (rme96
->pci
->device
) {
1887 case PCI_DEVICE_ID_RME_DIGI96
:
1888 case PCI_DEVICE_ID_RME_DIGI96_8
:
1891 case PCI_DEVICE_ID_RME_DIGI96_8_PRO
:
1894 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST
:
1895 if (rme96
->rev
> 4) {
1896 /* for handling PST case, (INPUT_ANALOG is moved to INPUT_XLR */
1897 if (ucontrol
->value
.enumerated
.item
[0] == RME96_INPUT_ANALOG
) {
1898 ucontrol
->value
.enumerated
.item
[0] = RME96_INPUT_XLR
;
1909 if (ucontrol
->value
.enumerated
.item
[0] >= items
) {
1910 ucontrol
->value
.enumerated
.item
[0] = items
- 1;
1913 spin_unlock_irq(&rme96
->lock
);
1917 snd_rme96_put_inputtype_control(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
1919 struct rme96
*rme96
= snd_kcontrol_chip(kcontrol
);
1921 int change
, items
= 3;
1923 switch (rme96
->pci
->device
) {
1924 case PCI_DEVICE_ID_RME_DIGI96
:
1925 case PCI_DEVICE_ID_RME_DIGI96_8
:
1928 case PCI_DEVICE_ID_RME_DIGI96_8_PRO
:
1931 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST
:
1932 if (rme96
->rev
> 4) {
1942 val
= ucontrol
->value
.enumerated
.item
[0] % items
;
1944 /* special case for PST */
1945 if (rme96
->pci
->device
== PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST
&& rme96
->rev
> 4) {
1946 if (val
== RME96_INPUT_XLR
) {
1947 val
= RME96_INPUT_ANALOG
;
1951 spin_lock_irq(&rme96
->lock
);
1952 change
= (int)val
!= snd_rme96_getinputtype(rme96
);
1953 snd_rme96_setinputtype(rme96
, val
);
1954 spin_unlock_irq(&rme96
->lock
);
1959 snd_rme96_info_clockmode_control(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_info
*uinfo
)
1961 static char *texts
[3] = { "AutoSync", "Internal", "Word" };
1963 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_ENUMERATED
;
1965 uinfo
->value
.enumerated
.items
= 3;
1966 if (uinfo
->value
.enumerated
.item
> 2) {
1967 uinfo
->value
.enumerated
.item
= 2;
1969 strcpy(uinfo
->value
.enumerated
.name
, texts
[uinfo
->value
.enumerated
.item
]);
1973 snd_rme96_get_clockmode_control(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
1975 struct rme96
*rme96
= snd_kcontrol_chip(kcontrol
);
1977 spin_lock_irq(&rme96
->lock
);
1978 ucontrol
->value
.enumerated
.item
[0] = snd_rme96_getclockmode(rme96
);
1979 spin_unlock_irq(&rme96
->lock
);
1983 snd_rme96_put_clockmode_control(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
1985 struct rme96
*rme96
= snd_kcontrol_chip(kcontrol
);
1989 val
= ucontrol
->value
.enumerated
.item
[0] % 3;
1990 spin_lock_irq(&rme96
->lock
);
1991 change
= (int)val
!= snd_rme96_getclockmode(rme96
);
1992 snd_rme96_setclockmode(rme96
, val
);
1993 spin_unlock_irq(&rme96
->lock
);
1998 snd_rme96_info_attenuation_control(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_info
*uinfo
)
2000 static char *texts
[4] = { "0 dB", "-6 dB", "-12 dB", "-18 dB" };
2002 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_ENUMERATED
;
2004 uinfo
->value
.enumerated
.items
= 4;
2005 if (uinfo
->value
.enumerated
.item
> 3) {
2006 uinfo
->value
.enumerated
.item
= 3;
2008 strcpy(uinfo
->value
.enumerated
.name
, texts
[uinfo
->value
.enumerated
.item
]);
2012 snd_rme96_get_attenuation_control(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
2014 struct rme96
*rme96
= snd_kcontrol_chip(kcontrol
);
2016 spin_lock_irq(&rme96
->lock
);
2017 ucontrol
->value
.enumerated
.item
[0] = snd_rme96_getattenuation(rme96
);
2018 spin_unlock_irq(&rme96
->lock
);
2022 snd_rme96_put_attenuation_control(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
2024 struct rme96
*rme96
= snd_kcontrol_chip(kcontrol
);
2028 val
= ucontrol
->value
.enumerated
.item
[0] % 4;
2029 spin_lock_irq(&rme96
->lock
);
2031 change
= (int)val
!= snd_rme96_getattenuation(rme96
);
2032 snd_rme96_setattenuation(rme96
, val
);
2033 spin_unlock_irq(&rme96
->lock
);
2038 snd_rme96_info_montracks_control(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_info
*uinfo
)
2040 static char *texts
[4] = { "1+2", "3+4", "5+6", "7+8" };
2042 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_ENUMERATED
;
2044 uinfo
->value
.enumerated
.items
= 4;
2045 if (uinfo
->value
.enumerated
.item
> 3) {
2046 uinfo
->value
.enumerated
.item
= 3;
2048 strcpy(uinfo
->value
.enumerated
.name
, texts
[uinfo
->value
.enumerated
.item
]);
2052 snd_rme96_get_montracks_control(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
2054 struct rme96
*rme96
= snd_kcontrol_chip(kcontrol
);
2056 spin_lock_irq(&rme96
->lock
);
2057 ucontrol
->value
.enumerated
.item
[0] = snd_rme96_getmontracks(rme96
);
2058 spin_unlock_irq(&rme96
->lock
);
2062 snd_rme96_put_montracks_control(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
2064 struct rme96
*rme96
= snd_kcontrol_chip(kcontrol
);
2068 val
= ucontrol
->value
.enumerated
.item
[0] % 4;
2069 spin_lock_irq(&rme96
->lock
);
2070 change
= (int)val
!= snd_rme96_getmontracks(rme96
);
2071 snd_rme96_setmontracks(rme96
, val
);
2072 spin_unlock_irq(&rme96
->lock
);
2076 static u32
snd_rme96_convert_from_aes(struct snd_aes_iec958
*aes
)
2079 val
|= (aes
->status
[0] & IEC958_AES0_PROFESSIONAL
) ? RME96_WCR_PRO
: 0;
2080 val
|= (aes
->status
[0] & IEC958_AES0_NONAUDIO
) ? RME96_WCR_DOLBY
: 0;
2081 if (val
& RME96_WCR_PRO
)
2082 val
|= (aes
->status
[0] & IEC958_AES0_PRO_EMPHASIS_5015
) ? RME96_WCR_EMP
: 0;
2084 val
|= (aes
->status
[0] & IEC958_AES0_CON_EMPHASIS_5015
) ? RME96_WCR_EMP
: 0;
2088 static void snd_rme96_convert_to_aes(struct snd_aes_iec958
*aes
, u32 val
)
2090 aes
->status
[0] = ((val
& RME96_WCR_PRO
) ? IEC958_AES0_PROFESSIONAL
: 0) |
2091 ((val
& RME96_WCR_DOLBY
) ? IEC958_AES0_NONAUDIO
: 0);
2092 if (val
& RME96_WCR_PRO
)
2093 aes
->status
[0] |= (val
& RME96_WCR_EMP
) ? IEC958_AES0_PRO_EMPHASIS_5015
: 0;
2095 aes
->status
[0] |= (val
& RME96_WCR_EMP
) ? IEC958_AES0_CON_EMPHASIS_5015
: 0;
2098 static int snd_rme96_control_spdif_info(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_info
*uinfo
)
2100 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_IEC958
;
2105 static int snd_rme96_control_spdif_get(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
2107 struct rme96
*rme96
= snd_kcontrol_chip(kcontrol
);
2109 snd_rme96_convert_to_aes(&ucontrol
->value
.iec958
, rme96
->wcreg_spdif
);
2113 static int snd_rme96_control_spdif_put(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
2115 struct rme96
*rme96
= snd_kcontrol_chip(kcontrol
);
2119 val
= snd_rme96_convert_from_aes(&ucontrol
->value
.iec958
);
2120 spin_lock_irq(&rme96
->lock
);
2121 change
= val
!= rme96
->wcreg_spdif
;
2122 rme96
->wcreg_spdif
= val
;
2123 spin_unlock_irq(&rme96
->lock
);
2127 static int snd_rme96_control_spdif_stream_info(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_info
*uinfo
)
2129 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_IEC958
;
2134 static int snd_rme96_control_spdif_stream_get(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
2136 struct rme96
*rme96
= snd_kcontrol_chip(kcontrol
);
2138 snd_rme96_convert_to_aes(&ucontrol
->value
.iec958
, rme96
->wcreg_spdif_stream
);
2142 static int snd_rme96_control_spdif_stream_put(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
2144 struct rme96
*rme96
= snd_kcontrol_chip(kcontrol
);
2148 val
= snd_rme96_convert_from_aes(&ucontrol
->value
.iec958
);
2149 spin_lock_irq(&rme96
->lock
);
2150 change
= val
!= rme96
->wcreg_spdif_stream
;
2151 rme96
->wcreg_spdif_stream
= val
;
2152 rme96
->wcreg
&= ~(RME96_WCR_PRO
| RME96_WCR_DOLBY
| RME96_WCR_EMP
);
2153 rme96
->wcreg
|= val
;
2154 writel(rme96
->wcreg
, rme96
->iobase
+ RME96_IO_CONTROL_REGISTER
);
2155 spin_unlock_irq(&rme96
->lock
);
2159 static int snd_rme96_control_spdif_mask_info(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_info
*uinfo
)
2161 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_IEC958
;
2166 static int snd_rme96_control_spdif_mask_get(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*ucontrol
)
2168 ucontrol
->value
.iec958
.status
[0] = kcontrol
->private_value
;
2173 snd_rme96_dac_volume_info(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_info
*uinfo
)
2175 struct rme96
*rme96
= snd_kcontrol_chip(kcontrol
);
2177 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_INTEGER
;
2179 uinfo
->value
.integer
.min
= 0;
2180 uinfo
->value
.integer
.max
= RME96_185X_MAX_OUT(rme96
);
2185 snd_rme96_dac_volume_get(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*u
)
2187 struct rme96
*rme96
= snd_kcontrol_chip(kcontrol
);
2189 spin_lock_irq(&rme96
->lock
);
2190 u
->value
.integer
.value
[0] = rme96
->vol
[0];
2191 u
->value
.integer
.value
[1] = rme96
->vol
[1];
2192 spin_unlock_irq(&rme96
->lock
);
2198 snd_rme96_dac_volume_put(struct snd_kcontrol
*kcontrol
, struct snd_ctl_elem_value
*u
)
2200 struct rme96
*rme96
= snd_kcontrol_chip(kcontrol
);
2202 unsigned int vol
, maxvol
;
2205 if (!RME96_HAS_ANALOG_OUT(rme96
))
2207 maxvol
= RME96_185X_MAX_OUT(rme96
);
2208 spin_lock_irq(&rme96
->lock
);
2209 vol
= u
->value
.integer
.value
[0];
2210 if (vol
!= rme96
->vol
[0] && vol
<= maxvol
) {
2211 rme96
->vol
[0] = vol
;
2214 vol
= u
->value
.integer
.value
[1];
2215 if (vol
!= rme96
->vol
[1] && vol
<= maxvol
) {
2216 rme96
->vol
[1] = vol
;
2220 snd_rme96_apply_dac_volume(rme96
);
2221 spin_unlock_irq(&rme96
->lock
);
2226 static struct snd_kcontrol_new snd_rme96_controls
[] = {
2228 .iface
= SNDRV_CTL_ELEM_IFACE_PCM
,
2229 .name
= SNDRV_CTL_NAME_IEC958("",PLAYBACK
,DEFAULT
),
2230 .info
= snd_rme96_control_spdif_info
,
2231 .get
= snd_rme96_control_spdif_get
,
2232 .put
= snd_rme96_control_spdif_put
2235 .access
= SNDRV_CTL_ELEM_ACCESS_READWRITE
| SNDRV_CTL_ELEM_ACCESS_INACTIVE
,
2236 .iface
= SNDRV_CTL_ELEM_IFACE_PCM
,
2237 .name
= SNDRV_CTL_NAME_IEC958("",PLAYBACK
,PCM_STREAM
),
2238 .info
= snd_rme96_control_spdif_stream_info
,
2239 .get
= snd_rme96_control_spdif_stream_get
,
2240 .put
= snd_rme96_control_spdif_stream_put
2243 .access
= SNDRV_CTL_ELEM_ACCESS_READ
,
2244 .iface
= SNDRV_CTL_ELEM_IFACE_PCM
,
2245 .name
= SNDRV_CTL_NAME_IEC958("",PLAYBACK
,CON_MASK
),
2246 .info
= snd_rme96_control_spdif_mask_info
,
2247 .get
= snd_rme96_control_spdif_mask_get
,
2248 .private_value
= IEC958_AES0_NONAUDIO
|
2249 IEC958_AES0_PROFESSIONAL
|
2250 IEC958_AES0_CON_EMPHASIS
2253 .access
= SNDRV_CTL_ELEM_ACCESS_READ
,
2254 .iface
= SNDRV_CTL_ELEM_IFACE_PCM
,
2255 .name
= SNDRV_CTL_NAME_IEC958("",PLAYBACK
,PRO_MASK
),
2256 .info
= snd_rme96_control_spdif_mask_info
,
2257 .get
= snd_rme96_control_spdif_mask_get
,
2258 .private_value
= IEC958_AES0_NONAUDIO
|
2259 IEC958_AES0_PROFESSIONAL
|
2260 IEC958_AES0_PRO_EMPHASIS
2263 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
2264 .name
= "Input Connector",
2265 .info
= snd_rme96_info_inputtype_control
,
2266 .get
= snd_rme96_get_inputtype_control
,
2267 .put
= snd_rme96_put_inputtype_control
2270 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
2271 .name
= "Loopback Input",
2272 .info
= snd_rme96_info_loopback_control
,
2273 .get
= snd_rme96_get_loopback_control
,
2274 .put
= snd_rme96_put_loopback_control
2277 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
2278 .name
= "Sample Clock Source",
2279 .info
= snd_rme96_info_clockmode_control
,
2280 .get
= snd_rme96_get_clockmode_control
,
2281 .put
= snd_rme96_put_clockmode_control
2284 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
2285 .name
= "Monitor Tracks",
2286 .info
= snd_rme96_info_montracks_control
,
2287 .get
= snd_rme96_get_montracks_control
,
2288 .put
= snd_rme96_put_montracks_control
2291 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
2292 .name
= "Attenuation",
2293 .info
= snd_rme96_info_attenuation_control
,
2294 .get
= snd_rme96_get_attenuation_control
,
2295 .put
= snd_rme96_put_attenuation_control
2298 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
2299 .name
= "DAC Playback Volume",
2300 .info
= snd_rme96_dac_volume_info
,
2301 .get
= snd_rme96_dac_volume_get
,
2302 .put
= snd_rme96_dac_volume_put
2307 snd_rme96_create_switches(struct snd_card
*card
,
2308 struct rme96
*rme96
)
2311 struct snd_kcontrol
*kctl
;
2313 for (idx
= 0; idx
< 7; idx
++) {
2314 if ((err
= snd_ctl_add(card
, kctl
= snd_ctl_new1(&snd_rme96_controls
[idx
], rme96
))) < 0)
2316 if (idx
== 1) /* IEC958 (S/PDIF) Stream */
2317 rme96
->spdif_ctl
= kctl
;
2320 if (RME96_HAS_ANALOG_OUT(rme96
)) {
2321 for (idx
= 7; idx
< 10; idx
++)
2322 if ((err
= snd_ctl_add(card
, snd_ctl_new1(&snd_rme96_controls
[idx
], rme96
))) < 0)
2330 * Card initialisation
2333 static void snd_rme96_card_free(struct snd_card
*card
)
2335 snd_rme96_free(card
->private_data
);
2339 snd_rme96_probe(struct pci_dev
*pci
,
2340 const struct pci_device_id
*pci_id
)
2343 struct rme96
*rme96
;
2344 struct snd_card
*card
;
2348 if (dev
>= SNDRV_CARDS
) {
2355 err
= snd_card_create(index
[dev
], id
[dev
], THIS_MODULE
,
2356 sizeof(struct rme96
), &card
);
2359 card
->private_free
= snd_rme96_card_free
;
2360 rme96
= card
->private_data
;
2363 snd_card_set_dev(card
, &pci
->dev
);
2364 if ((err
= snd_rme96_create(rme96
)) < 0) {
2365 snd_card_free(card
);
2369 strcpy(card
->driver
, "Digi96");
2370 switch (rme96
->pci
->device
) {
2371 case PCI_DEVICE_ID_RME_DIGI96
:
2372 strcpy(card
->shortname
, "RME Digi96");
2374 case PCI_DEVICE_ID_RME_DIGI96_8
:
2375 strcpy(card
->shortname
, "RME Digi96/8");
2377 case PCI_DEVICE_ID_RME_DIGI96_8_PRO
:
2378 strcpy(card
->shortname
, "RME Digi96/8 PRO");
2380 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST
:
2381 pci_read_config_byte(rme96
->pci
, 8, &val
);
2383 strcpy(card
->shortname
, "RME Digi96/8 PAD");
2385 strcpy(card
->shortname
, "RME Digi96/8 PST");
2389 sprintf(card
->longname
, "%s at 0x%lx, irq %d", card
->shortname
,
2390 rme96
->port
, rme96
->irq
);
2392 if ((err
= snd_card_register(card
)) < 0) {
2393 snd_card_free(card
);
2396 pci_set_drvdata(pci
, card
);
2401 static void snd_rme96_remove(struct pci_dev
*pci
)
2403 snd_card_free(pci_get_drvdata(pci
));
2404 pci_set_drvdata(pci
, NULL
);
2407 static struct pci_driver rme96_driver
= {
2408 .name
= KBUILD_MODNAME
,
2409 .id_table
= snd_rme96_ids
,
2410 .probe
= snd_rme96_probe
,
2411 .remove
= snd_rme96_remove
,
2414 module_pci_driver(rme96_driver
);