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drivers: power: report battery voltage in AOSP compatible format
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / pci / rme96.c
CommitLineData
1da177e4
LT		 1/*
2 * ALSA driver for RME Digi96, Digi96/8 and Digi96/8 PRO/PAD/PST audio
3 * interfaces
4 *
5 * Copyright (c) 2000, 2001 Anders Torger <torger@ludd.luth.se>
6 *
7 * Thanks to Henk Hesselink <henk@anda.nl> for the analog volume control
8 * code.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 */
25
1da177e4
LT		 26#include <linux/delay.h>
27#include <linux/init.h>
28#include <linux/interrupt.h>
29#include <linux/pci.h>
65a77217 30#include <linux/module.h>
1da177e4
LT		 31
32#include <sound/core.h>
33#include <sound/info.h>
34#include <sound/control.h>
35#include <sound/pcm.h>
36#include <sound/pcm_params.h>
37#include <sound/asoundef.h>
38#include <sound/initval.h>
39
40#include <asm/io.h>
41
42/* note, two last pcis should be equal, it is not a bug */
43
44MODULE_AUTHOR("Anders Torger <torger@ludd.luth.se>");
45MODULE_DESCRIPTION("RME Digi96, Digi96/8, Digi96/8 PRO, Digi96/8 PST, "
46 "Digi96/8 PAD");
47MODULE_LICENSE("GPL");
48MODULE_SUPPORTED_DEVICE("{{RME,Digi96},"
49 "{RME,Digi96/8},"
50 "{RME,Digi96/8 PRO},"
51 "{RME,Digi96/8 PST},"
52 "{RME,Digi96/8 PAD}}");
53
54static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
55static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
a67ff6a5 56static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
1da177e4
LT		 57
58module_param_array(index, int, NULL, 0444);
59MODULE_PARM_DESC(index, "Index value for RME Digi96 soundcard.");
60module_param_array(id, charp, NULL, 0444);
61MODULE_PARM_DESC(id, "ID string for RME Digi96 soundcard.");
62module_param_array(enable, bool, NULL, 0444);
63MODULE_PARM_DESC(enable, "Enable RME Digi96 soundcard.");
64
65/*
66 * Defines for RME Digi96 series, from internal RME reference documents
67 * dated 12.01.00
68 */
69
70#define RME96_SPDIF_NCHANNELS 2
71
72/* Playback and capture buffer size */
73#define RME96_BUFFER_SIZE 0x10000
74
75/* IO area size */
76#define RME96_IO_SIZE 0x60000
77
78/* IO area offsets */
79#define RME96_IO_PLAY_BUFFER 0x0
80#define RME96_IO_REC_BUFFER 0x10000
81#define RME96_IO_CONTROL_REGISTER 0x20000
82#define RME96_IO_ADDITIONAL_REG 0x20004
83#define RME96_IO_CONFIRM_PLAY_IRQ 0x20008
84#define RME96_IO_CONFIRM_REC_IRQ 0x2000C
85#define RME96_IO_SET_PLAY_POS 0x40000
86#define RME96_IO_RESET_PLAY_POS 0x4FFFC
87#define RME96_IO_SET_REC_POS 0x50000
88#define RME96_IO_RESET_REC_POS 0x5FFFC
89#define RME96_IO_GET_PLAY_POS 0x20000
90#define RME96_IO_GET_REC_POS 0x30000
91
92/* Write control register bits */
93#define RME96_WCR_START (1 << 0)
94#define RME96_WCR_START_2 (1 << 1)
95#define RME96_WCR_GAIN_0 (1 << 2)
96#define RME96_WCR_GAIN_1 (1 << 3)
97#define RME96_WCR_MODE24 (1 << 4)
98#define RME96_WCR_MODE24_2 (1 << 5)
99#define RME96_WCR_BM (1 << 6)
100#define RME96_WCR_BM_2 (1 << 7)
101#define RME96_WCR_ADAT (1 << 8)
102#define RME96_WCR_FREQ_0 (1 << 9)
103#define RME96_WCR_FREQ_1 (1 << 10)
104#define RME96_WCR_DS (1 << 11)
105#define RME96_WCR_PRO (1 << 12)
106#define RME96_WCR_EMP (1 << 13)
107#define RME96_WCR_SEL (1 << 14)
108#define RME96_WCR_MASTER (1 << 15)
109#define RME96_WCR_PD (1 << 16)
110#define RME96_WCR_INP_0 (1 << 17)
111#define RME96_WCR_INP_1 (1 << 18)
112#define RME96_WCR_THRU_0 (1 << 19)
113#define RME96_WCR_THRU_1 (1 << 20)
114#define RME96_WCR_THRU_2 (1 << 21)
115#define RME96_WCR_THRU_3 (1 << 22)
116#define RME96_WCR_THRU_4 (1 << 23)
117#define RME96_WCR_THRU_5 (1 << 24)
118#define RME96_WCR_THRU_6 (1 << 25)
119#define RME96_WCR_THRU_7 (1 << 26)
120#define RME96_WCR_DOLBY (1 << 27)
121#define RME96_WCR_MONITOR_0 (1 << 28)
122#define RME96_WCR_MONITOR_1 (1 << 29)
123#define RME96_WCR_ISEL (1 << 30)
124#define RME96_WCR_IDIS (1 << 31)
125
126#define RME96_WCR_BITPOS_GAIN_0 2
127#define RME96_WCR_BITPOS_GAIN_1 3
128#define RME96_WCR_BITPOS_FREQ_0 9
129#define RME96_WCR_BITPOS_FREQ_1 10
130#define RME96_WCR_BITPOS_INP_0 17
131#define RME96_WCR_BITPOS_INP_1 18
132#define RME96_WCR_BITPOS_MONITOR_0 28
133#define RME96_WCR_BITPOS_MONITOR_1 29
134
135/* Read control register bits */
136#define RME96_RCR_AUDIO_ADDR_MASK 0xFFFF
137#define RME96_RCR_IRQ_2 (1 << 16)
138#define RME96_RCR_T_OUT (1 << 17)
139#define RME96_RCR_DEV_ID_0 (1 << 21)
140#define RME96_RCR_DEV_ID_1 (1 << 22)
141#define RME96_RCR_LOCK (1 << 23)
142#define RME96_RCR_VERF (1 << 26)
143#define RME96_RCR_F0 (1 << 27)
144#define RME96_RCR_F1 (1 << 28)
145#define RME96_RCR_F2 (1 << 29)
146#define RME96_RCR_AUTOSYNC (1 << 30)
147#define RME96_RCR_IRQ (1 << 31)
148
149#define RME96_RCR_BITPOS_F0 27
150#define RME96_RCR_BITPOS_F1 28
151#define RME96_RCR_BITPOS_F2 29
152
25985edc 153/* Additional register bits */
1da177e4
LT		 154#define RME96_AR_WSEL (1 << 0)
155#define RME96_AR_ANALOG (1 << 1)
156#define RME96_AR_FREQPAD_0 (1 << 2)
157#define RME96_AR_FREQPAD_1 (1 << 3)
158#define RME96_AR_FREQPAD_2 (1 << 4)
159#define RME96_AR_PD2 (1 << 5)
160#define RME96_AR_DAC_EN (1 << 6)
161#define RME96_AR_CLATCH (1 << 7)
162#define RME96_AR_CCLK (1 << 8)
163#define RME96_AR_CDATA (1 << 9)
164
165#define RME96_AR_BITPOS_F0 2
166#define RME96_AR_BITPOS_F1 3
167#define RME96_AR_BITPOS_F2 4
168
169/* Monitor tracks */
170#define RME96_MONITOR_TRACKS_1_2 0
171#define RME96_MONITOR_TRACKS_3_4 1
172#define RME96_MONITOR_TRACKS_5_6 2
173#define RME96_MONITOR_TRACKS_7_8 3
174
175/* Attenuation */
176#define RME96_ATTENUATION_0 0
177#define RME96_ATTENUATION_6 1
178#define RME96_ATTENUATION_12 2
179#define RME96_ATTENUATION_18 3
180
181/* Input types */
182#define RME96_INPUT_OPTICAL 0
183#define RME96_INPUT_COAXIAL 1
184#define RME96_INPUT_INTERNAL 2
185#define RME96_INPUT_XLR 3
186#define RME96_INPUT_ANALOG 4
187
188/* Clock modes */
189#define RME96_CLOCKMODE_SLAVE 0
190#define RME96_CLOCKMODE_MASTER 1
191#define RME96_CLOCKMODE_WORDCLOCK 2
192
193/* Block sizes in bytes */
194#define RME96_SMALL_BLOCK_SIZE 2048
195#define RME96_LARGE_BLOCK_SIZE 8192
196
197/* Volume control */
198#define RME96_AD1852_VOL_BITS 14
199#define RME96_AD1855_VOL_BITS 10
200
1da177e4 201
a3aefd88 202struct rme96 {
1da177e4
LT		 203 spinlock_t lock;
204 int irq;
205 unsigned long port;
206 void __iomem *iobase;
207
208 u32 wcreg; /* cached write control register value */
209 u32 wcreg_spdif; /* S/PDIF setup */
210 u32 wcreg_spdif_stream; /* S/PDIF setup (temporary) */
211 u32 rcreg; /* cached read control register value */
212 u32 areg; /* cached additional register value */
213 u16 vol[2]; /* cached volume of analog output */
214
215 u8 rev; /* card revision number */
216
a3aefd88
TI		 217 struct snd_pcm_substream *playback_substream;
218 struct snd_pcm_substream *capture_substream;
1da177e4
LT		 219
220 int playback_frlog; /* log2 of framesize */
221 int capture_frlog;
222
223 size_t playback_periodsize; /* in bytes, zero if not used */
224 size_t capture_periodsize; /* in bytes, zero if not used */
225
a3aefd88
TI		 226 struct snd_card *card;
227 struct snd_pcm *spdif_pcm;
228 struct snd_pcm *adat_pcm;
1da177e4 229 struct pci_dev *pci;
a3aefd88
TI		 230 struct snd_kcontrol *spdif_ctl;
231};
1da177e4 232
cebe41d4 233static DEFINE_PCI_DEVICE_TABLE(snd_rme96_ids) = {
28d27aae
JP		 234 { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96), 0, },
235 { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8), 0, },
236 { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8_PRO), 0, },
237 { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST), 0, },
1da177e4
LT		 238 { 0, }
239};
240
241MODULE_DEVICE_TABLE(pci, snd_rme96_ids);
242
243#define RME96_ISPLAYING(rme96) ((rme96)->wcreg & RME96_WCR_START)
244#define RME96_ISRECORDING(rme96) ((rme96)->wcreg & RME96_WCR_START_2)
8b7fc421
RD		 245#define RME96_HAS_ANALOG_IN(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST)
246#define RME96_HAS_ANALOG_OUT(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PRO || \
247 (rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST)
1da177e4 248#define RME96_DAC_IS_1852(rme96) (RME96_HAS_ANALOG_OUT(rme96) && (rme96)->rev >= 4)
8b7fc421
RD		 249#define RME96_DAC_IS_1855(rme96) (((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && (rme96)->rev < 4) || \
250 ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PRO && (rme96)->rev == 2))
1da177e4
LT		 251#define RME96_185X_MAX_OUT(rme96) ((1 << (RME96_DAC_IS_1852(rme96) ? RME96_AD1852_VOL_BITS : RME96_AD1855_VOL_BITS)) - 1)
252
253static int
a3aefd88 254snd_rme96_playback_prepare(struct snd_pcm_substream *substream);
1da177e4
LT		 255
256static int
a3aefd88 257snd_rme96_capture_prepare(struct snd_pcm_substream *substream);
1da177e4
LT		 258
259static int
a3aefd88 260snd_rme96_playback_trigger(struct snd_pcm_substream *substream,
1da177e4
LT		 261 int cmd);
262
263static int
a3aefd88 264snd_rme96_capture_trigger(struct snd_pcm_substream *substream,
1da177e4
LT		 265 int cmd);
266
267static snd_pcm_uframes_t
a3aefd88 268snd_rme96_playback_pointer(struct snd_pcm_substream *substream);
1da177e4
LT		 269
270static snd_pcm_uframes_t
a3aefd88 271snd_rme96_capture_pointer(struct snd_pcm_substream *substream);
1da177e4 272
e23e7a14 273static void snd_rme96_proc_init(struct rme96 *rme96);
1da177e4
LT		 274
275static int
a3aefd88
TI		 276snd_rme96_create_switches(struct snd_card *card,
277 struct rme96 *rme96);
1da177e4
LT		 278
279static int
a3aefd88 280snd_rme96_getinputtype(struct rme96 *rme96);
1da177e4
LT		 281
282static inline unsigned int
a3aefd88 283snd_rme96_playback_ptr(struct rme96 *rme96)
1da177e4
LT		 284{
285 return (readl(rme96->iobase + RME96_IO_GET_PLAY_POS)
286 & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->playback_frlog;
287}
288
289static inline unsigned int
a3aefd88 290snd_rme96_capture_ptr(struct rme96 *rme96)
1da177e4
LT		 291{
292 return (readl(rme96->iobase + RME96_IO_GET_REC_POS)
293 & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->capture_frlog;
294}
295
1da177e4 296static int
a3aefd88 297snd_rme96_playback_silence(struct snd_pcm_substream *substream,
1da177e4
LT		 298 int channel, /* not used (interleaved data) */
299 snd_pcm_uframes_t pos,
300 snd_pcm_uframes_t count)
301{
a3aefd88 302 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1da177e4
LT		 303 count <<= rme96->playback_frlog;
304 pos <<= rme96->playback_frlog;
305 memset_io(rme96->iobase + RME96_IO_PLAY_BUFFER + pos,
306 0, count);
307 return 0;
308}
309
310static int
a3aefd88 311snd_rme96_playback_copy(struct snd_pcm_substream *substream,
1da177e4
LT		 312 int channel, /* not used (interleaved data) */
313 snd_pcm_uframes_t pos,
314 void __user *src,
315 snd_pcm_uframes_t count)
316{
a3aefd88 317 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1da177e4
LT		 318 count <<= rme96->playback_frlog;
319 pos <<= rme96->playback_frlog;
320 copy_from_user_toio(rme96->iobase + RME96_IO_PLAY_BUFFER + pos, src,
321 count);
322 return 0;
323}
324
325static int
a3aefd88 326snd_rme96_capture_copy(struct snd_pcm_substream *substream,
1da177e4
LT		 327 int channel, /* not used (interleaved data) */
328 snd_pcm_uframes_t pos,
329 void __user *dst,
330 snd_pcm_uframes_t count)
331{
a3aefd88 332 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1da177e4
LT		 333 count <<= rme96->capture_frlog;
334 pos <<= rme96->capture_frlog;
335 copy_to_user_fromio(dst, rme96->iobase + RME96_IO_REC_BUFFER + pos,
336 count);
337 return 0;
338}
339
340/*
7f927fcc 341 * Digital output capabilities (S/PDIF)
1da177e4 342 */
a3aefd88 343static struct snd_pcm_hardware snd_rme96_playback_spdif_info =
1da177e4
LT		 344{
345 .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
346 SNDRV_PCM_INFO_MMAP_VALID |
347 SNDRV_PCM_INFO_INTERLEAVED |
348 SNDRV_PCM_INFO_PAUSE),
349 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
350 SNDRV_PCM_FMTBIT_S32_LE),
351 .rates = (SNDRV_PCM_RATE_32000 |
352 SNDRV_PCM_RATE_44100 |
353 SNDRV_PCM_RATE_48000 |
354 SNDRV_PCM_RATE_64000 |
355 SNDRV_PCM_RATE_88200 |
356 SNDRV_PCM_RATE_96000),
357 .rate_min = 32000,
358 .rate_max = 96000,
359 .channels_min = 2,
360 .channels_max = 2,
361 .buffer_bytes_max = RME96_BUFFER_SIZE,
362 .period_bytes_min = RME96_SMALL_BLOCK_SIZE,
363 .period_bytes_max = RME96_LARGE_BLOCK_SIZE,
364 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
365 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
366 .fifo_size = 0,
367};
368
369/*
7f927fcc 370 * Digital input capabilities (S/PDIF)
1da177e4 371 */
a3aefd88 372static struct snd_pcm_hardware snd_rme96_capture_spdif_info =
1da177e4
LT		 373{
374 .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
375 SNDRV_PCM_INFO_MMAP_VALID |
376 SNDRV_PCM_INFO_INTERLEAVED |
377 SNDRV_PCM_INFO_PAUSE),
378 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
379 SNDRV_PCM_FMTBIT_S32_LE),
380 .rates = (SNDRV_PCM_RATE_32000 |
381 SNDRV_PCM_RATE_44100 |
382 SNDRV_PCM_RATE_48000 |
383 SNDRV_PCM_RATE_64000 |
384 SNDRV_PCM_RATE_88200 |
385 SNDRV_PCM_RATE_96000),
386 .rate_min = 32000,
387 .rate_max = 96000,
388 .channels_min = 2,
389 .channels_max = 2,
390 .buffer_bytes_max = RME96_BUFFER_SIZE,
391 .period_bytes_min = RME96_SMALL_BLOCK_SIZE,
392 .period_bytes_max = RME96_LARGE_BLOCK_SIZE,
393 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
394 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
395 .fifo_size = 0,
396};
397
398/*
7f927fcc 399 * Digital output capabilities (ADAT)
1da177e4 400 */
a3aefd88 401static struct snd_pcm_hardware snd_rme96_playback_adat_info =
1da177e4
LT		 402{
403 .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
404 SNDRV_PCM_INFO_MMAP_VALID |
405 SNDRV_PCM_INFO_INTERLEAVED |
406 SNDRV_PCM_INFO_PAUSE),
407 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
408 SNDRV_PCM_FMTBIT_S32_LE),
409 .rates = (SNDRV_PCM_RATE_44100 |
410 SNDRV_PCM_RATE_48000),
411 .rate_min = 44100,
412 .rate_max = 48000,
413 .channels_min = 8,
414 .channels_max = 8,
415 .buffer_bytes_max = RME96_BUFFER_SIZE,
416 .period_bytes_min = RME96_SMALL_BLOCK_SIZE,
417 .period_bytes_max = RME96_LARGE_BLOCK_SIZE,
418 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
419 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
420 .fifo_size = 0,
421};
422
423/*
7f927fcc 424 * Digital input capabilities (ADAT)
1da177e4 425 */
a3aefd88 426static struct snd_pcm_hardware snd_rme96_capture_adat_info =
1da177e4
LT		 427{
428 .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
429 SNDRV_PCM_INFO_MMAP_VALID |
430 SNDRV_PCM_INFO_INTERLEAVED |
431 SNDRV_PCM_INFO_PAUSE),
432 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
433 SNDRV_PCM_FMTBIT_S32_LE),
434 .rates = (SNDRV_PCM_RATE_44100 |
435 SNDRV_PCM_RATE_48000),
436 .rate_min = 44100,
437 .rate_max = 48000,
438 .channels_min = 8,
439 .channels_max = 8,
440 .buffer_bytes_max = RME96_BUFFER_SIZE,
441 .period_bytes_min = RME96_SMALL_BLOCK_SIZE,
442 .period_bytes_max = RME96_LARGE_BLOCK_SIZE,
443 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
444 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
445 .fifo_size = 0,
446};
447
448/*
449 * The CDATA, CCLK and CLATCH bits can be used to write to the SPI interface
450 * of the AD1852 or AD1852 D/A converter on the board. CDATA must be set up
451 * on the falling edge of CCLK and be stable on the rising edge. The rising
452 * edge of CLATCH after the last data bit clocks in the whole data word.
453 * A fast processor could probably drive the SPI interface faster than the
454 * DAC can handle (3MHz for the 1855, unknown for the 1852). The udelay(1)
455 * limits the data rate to 500KHz and only causes a delay of 33 microsecs.
456 *
457 * NOTE: increased delay from 1 to 10, since there where problems setting
458 * the volume.
459 */
460static void
a3aefd88 461snd_rme96_write_SPI(struct rme96 *rme96, u16 val)
1da177e4
LT		 462{
463 int i;
464
465 for (i = 0; i < 16; i++) {
466 if (val & 0x8000) {
467 rme96->areg |= RME96_AR_CDATA;
468 } else {
469 rme96->areg &= ~RME96_AR_CDATA;
470 }
471 rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CLATCH);
472 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
473 udelay(10);
474 rme96->areg |= RME96_AR_CCLK;
475 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
476 udelay(10);
477 val <<= 1;
478 }
479 rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CDATA);
480 rme96->areg |= RME96_AR_CLATCH;
481 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
482 udelay(10);
483 rme96->areg &= ~RME96_AR_CLATCH;
484 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
485}
486
487static void
a3aefd88 488snd_rme96_apply_dac_volume(struct rme96 *rme96)
1da177e4
LT		 489{
490 if (RME96_DAC_IS_1852(rme96)) {
491 snd_rme96_write_SPI(rme96, (rme96->vol[0] << 2) | 0x0);
492 snd_rme96_write_SPI(rme96, (rme96->vol[1] << 2) | 0x2);
493 } else if (RME96_DAC_IS_1855(rme96)) {
494 snd_rme96_write_SPI(rme96, (rme96->vol[0] & 0x3FF) | 0x000);
495 snd_rme96_write_SPI(rme96, (rme96->vol[1] & 0x3FF) | 0x400);
496 }
497}
498
499static void
a3aefd88 500snd_rme96_reset_dac(struct rme96 *rme96)
1da177e4
LT		 501{
502 writel(rme96->wcreg | RME96_WCR_PD,
503 rme96->iobase + RME96_IO_CONTROL_REGISTER);
504 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
505}
506
507static int
a3aefd88 508snd_rme96_getmontracks(struct rme96 *rme96)
1da177e4
LT		 509{
510 return ((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_0) & 1) +
511 (((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_1) & 1) << 1);
512}
513
514static int
a3aefd88 515snd_rme96_setmontracks(struct rme96 *rme96,
1da177e4
LT		 516 int montracks)
517{
518 if (montracks & 1) {
519 rme96->wcreg |= RME96_WCR_MONITOR_0;
520 } else {
521 rme96->wcreg &= ~RME96_WCR_MONITOR_0;
522 }
523 if (montracks & 2) {
524 rme96->wcreg |= RME96_WCR_MONITOR_1;
525 } else {
526 rme96->wcreg &= ~RME96_WCR_MONITOR_1;
527 }
528 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
529 return 0;
530}
531
532static int
a3aefd88 533snd_rme96_getattenuation(struct rme96 *rme96)
1da177e4
LT		 534{
535 return ((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_0) & 1) +
536 (((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_1) & 1) << 1);
537}
538
539static int
a3aefd88 540snd_rme96_setattenuation(struct rme96 *rme96,
1da177e4
LT		 541 int attenuation)
542{
543 switch (attenuation) {
544 case 0:
545 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) &
546 ~RME96_WCR_GAIN_1;
547 break;
548 case 1:
549 rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) &
550 ~RME96_WCR_GAIN_1;
551 break;
552 case 2:
553 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) |
554 RME96_WCR_GAIN_1;
555 break;
556 case 3:
557 rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) |
558 RME96_WCR_GAIN_1;
559 break;
560 default:
561 return -EINVAL;
562 }
563 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
564 return 0;
565}
566
567static int
a3aefd88 568snd_rme96_capture_getrate(struct rme96 *rme96,
1da177e4
LT		 569 int *is_adat)
570{
571 int n, rate;
572
573 *is_adat = 0;
574 if (rme96->areg & RME96_AR_ANALOG) {
575 /* Analog input, overrides S/PDIF setting */
576 n = ((rme96->areg >> RME96_AR_BITPOS_F0) & 1) +
577 (((rme96->areg >> RME96_AR_BITPOS_F1) & 1) << 1);
578 switch (n) {
579 case 1:
580 rate = 32000;
581 break;
582 case 2:
583 rate = 44100;
584 break;
585 case 3:
586 rate = 48000;
587 break;
588 default:
589 return -1;
590 }
591 return (rme96->areg & RME96_AR_BITPOS_F2) ? rate << 1 : rate;
592 }
593
594 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
595 if (rme96->rcreg & RME96_RCR_LOCK) {
596 /* ADAT rate */
597 *is_adat = 1;
598 if (rme96->rcreg & RME96_RCR_T_OUT) {
599 return 48000;
600 }
601 return 44100;
602 }
603
604 if (rme96->rcreg & RME96_RCR_VERF) {
605 return -1;
606 }
607
608 /* S/PDIF rate */
609 n = ((rme96->rcreg >> RME96_RCR_BITPOS_F0) & 1) +
610 (((rme96->rcreg >> RME96_RCR_BITPOS_F1) & 1) << 1) +
611 (((rme96->rcreg >> RME96_RCR_BITPOS_F2) & 1) << 2);
612
613 switch (n) {
614 case 0:
615 if (rme96->rcreg & RME96_RCR_T_OUT) {
616 return 64000;
617 }
618 return -1;
619 case 3: return 96000;
620 case 4: return 88200;
621 case 5: return 48000;
622 case 6: return 44100;
623 case 7: return 32000;
624 default:
625 break;
626 }
627 return -1;
628}
629
630static int
a3aefd88 631snd_rme96_playback_getrate(struct rme96 *rme96)
1da177e4
LT		 632{
633 int rate, dummy;
634
635 if (!(rme96->wcreg & RME96_WCR_MASTER) &&
636 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
637 (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
638 {
639 /* slave clock */
640 return rate;
641 }
642 rate = ((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_0) & 1) +
643 (((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_1) & 1) << 1);
644 switch (rate) {
645 case 1:
646 rate = 32000;
647 break;
648 case 2:
649 rate = 44100;
650 break;
651 case 3:
652 rate = 48000;
653 break;
654 default:
655 return -1;
656 }
657 return (rme96->wcreg & RME96_WCR_DS) ? rate << 1 : rate;
658}
659
660static int
a3aefd88 661snd_rme96_playback_setrate(struct rme96 *rme96,
1da177e4
LT		 662 int rate)
663{
664 int ds;
665
666 ds = rme96->wcreg & RME96_WCR_DS;
667 switch (rate) {
668 case 32000:
669 rme96->wcreg &= ~RME96_WCR_DS;
670 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &
671 ~RME96_WCR_FREQ_1;
672 break;
673 case 44100:
674 rme96->wcreg &= ~RME96_WCR_DS;
675 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &
676 ~RME96_WCR_FREQ_0;
677 break;
678 case 48000:
679 rme96->wcreg &= ~RME96_WCR_DS;
680 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |
681 RME96_WCR_FREQ_1;
682 break;
683 case 64000:
684 rme96->wcreg |= RME96_WCR_DS;
685 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &
686 ~RME96_WCR_FREQ_1;
687 break;
688 case 88200:
689 rme96->wcreg |= RME96_WCR_DS;
690 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &
691 ~RME96_WCR_FREQ_0;
692 break;
693 case 96000:
694 rme96->wcreg |= RME96_WCR_DS;
695 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |
696 RME96_WCR_FREQ_1;
697 break;
698 default:
699 return -EINVAL;
700 }
701 if ((!ds && rme96->wcreg & RME96_WCR_DS) ||
702 (ds && !(rme96->wcreg & RME96_WCR_DS)))
703 {
704 /* change to/from double-speed: reset the DAC (if available) */
705 snd_rme96_reset_dac(rme96);
43702b71 706 return 1; /* need to restore volume */
1da177e4
LT		 707 } else {
708 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
43702b71 709 return 0;
1da177e4 710 }
1da177e4
LT		 711}
712
713static int
a3aefd88 714snd_rme96_capture_analog_setrate(struct rme96 *rme96,
1da177e4
LT		 715 int rate)
716{
717 switch (rate) {
718 case 32000:
719 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) &
720 ~RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
721 break;
722 case 44100:
723 rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) |
724 RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
725 break;
726 case 48000:
727 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) |
728 RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
729 break;
730 case 64000:
731 if (rme96->rev < 4) {
732 return -EINVAL;
733 }
734 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) &
735 ~RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
736 break;
737 case 88200:
738 if (rme96->rev < 4) {
739 return -EINVAL;
740 }
741 rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) |
742 RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
743 break;
744 case 96000:
745 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) |
746 RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
747 break;
748 default:
749 return -EINVAL;
750 }
751 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
752 return 0;
753}
754
755static int
a3aefd88 756snd_rme96_setclockmode(struct rme96 *rme96,
1da177e4
LT		 757 int mode)
758{
759 switch (mode) {
760 case RME96_CLOCKMODE_SLAVE:
761 /* AutoSync */
762 rme96->wcreg &= ~RME96_WCR_MASTER;
763 rme96->areg &= ~RME96_AR_WSEL;
764 break;
765 case RME96_CLOCKMODE_MASTER:
766 /* Internal */
767 rme96->wcreg |= RME96_WCR_MASTER;
768 rme96->areg &= ~RME96_AR_WSEL;
769 break;
770 case RME96_CLOCKMODE_WORDCLOCK:
771 /* Word clock is a master mode */
772 rme96->wcreg |= RME96_WCR_MASTER;
773 rme96->areg |= RME96_AR_WSEL;
774 break;
775 default:
776 return -EINVAL;
777 }
778 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
779 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
780 return 0;
781}
782
783static int
a3aefd88 784snd_rme96_getclockmode(struct rme96 *rme96)
1da177e4
LT		 785{
786 if (rme96->areg & RME96_AR_WSEL) {
787 return RME96_CLOCKMODE_WORDCLOCK;
788 }
789 return (rme96->wcreg & RME96_WCR_MASTER) ? RME96_CLOCKMODE_MASTER :
790 RME96_CLOCKMODE_SLAVE;
791}
792
793static int
a3aefd88 794snd_rme96_setinputtype(struct rme96 *rme96,
1da177e4
LT		 795 int type)
796{
797 int n;
798
799 switch (type) {
800 case RME96_INPUT_OPTICAL:
801 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) &
802 ~RME96_WCR_INP_1;
803 break;
804 case RME96_INPUT_COAXIAL:
805 rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) &
806 ~RME96_WCR_INP_1;
807 break;
808 case RME96_INPUT_INTERNAL:
809 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) |
810 RME96_WCR_INP_1;
811 break;
812 case RME96_INPUT_XLR:
8b7fc421
RD		 813 if ((rme96->pci->device != PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST &&
814 rme96->pci->device != PCI_DEVICE_ID_RME_DIGI96_8_PRO) ||
815 (rme96->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST &&
1da177e4
LT		 816 rme96->rev > 4))
817 {
818 /* Only Digi96/8 PRO and Digi96/8 PAD supports XLR */
819 return -EINVAL;
820 }
821 rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) |
822 RME96_WCR_INP_1;
823 break;
824 case RME96_INPUT_ANALOG:
825 if (!RME96_HAS_ANALOG_IN(rme96)) {
826 return -EINVAL;
827 }
828 rme96->areg |= RME96_AR_ANALOG;
829 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
830 if (rme96->rev < 4) {
831 /*
832 * Revision less than 004 does not support 64 and
833 * 88.2 kHz
834 */
835 if (snd_rme96_capture_getrate(rme96, &n) == 88200) {
836 snd_rme96_capture_analog_setrate(rme96, 44100);
837 }
838 if (snd_rme96_capture_getrate(rme96, &n) == 64000) {
839 snd_rme96_capture_analog_setrate(rme96, 32000);
840 }
841 }
842 return 0;
843 default:
844 return -EINVAL;
845 }
846 if (type != RME96_INPUT_ANALOG && RME96_HAS_ANALOG_IN(rme96)) {
847 rme96->areg &= ~RME96_AR_ANALOG;
848 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
849 }
850 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
851 return 0;
852}
853
854static int
a3aefd88 855snd_rme96_getinputtype(struct rme96 *rme96)
1da177e4
LT		 856{
857 if (rme96->areg & RME96_AR_ANALOG) {
858 return RME96_INPUT_ANALOG;
859 }
860 return ((rme96->wcreg >> RME96_WCR_BITPOS_INP_0) & 1) +
861 (((rme96->wcreg >> RME96_WCR_BITPOS_INP_1) & 1) << 1);
862}
863
864static void
a3aefd88 865snd_rme96_setframelog(struct rme96 *rme96,
1da177e4
LT		 866 int n_channels,
867 int is_playback)
868{
869 int frlog;
870
871 if (n_channels == 2) {
872 frlog = 1;
873 } else {
874 /* assume 8 channels */
875 frlog = 3;
876 }
877 if (is_playback) {
878 frlog += (rme96->wcreg & RME96_WCR_MODE24) ? 2 : 1;
879 rme96->playback_frlog = frlog;
880 } else {
881 frlog += (rme96->wcreg & RME96_WCR_MODE24_2) ? 2 : 1;
882 rme96->capture_frlog = frlog;
883 }
884}
885
886static int
a3aefd88 887snd_rme96_playback_setformat(struct rme96 *rme96,
1da177e4
LT		 888 int format)
889{
890 switch (format) {
891 case SNDRV_PCM_FORMAT_S16_LE:
892 rme96->wcreg &= ~RME96_WCR_MODE24;
893 break;
894 case SNDRV_PCM_FORMAT_S32_LE:
895 rme96->wcreg |= RME96_WCR_MODE24;
896 break;
897 default:
898 return -EINVAL;
899 }
900 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
901 return 0;
902}
903
904static int
a3aefd88 905snd_rme96_capture_setformat(struct rme96 *rme96,
1da177e4
LT		 906 int format)
907{
908 switch (format) {
909 case SNDRV_PCM_FORMAT_S16_LE:
910 rme96->wcreg &= ~RME96_WCR_MODE24_2;
911 break;
912 case SNDRV_PCM_FORMAT_S32_LE:
913 rme96->wcreg |= RME96_WCR_MODE24_2;
914 break;
915 default:
916 return -EINVAL;
917 }
918 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
919 return 0;
920}
921
922static void
a3aefd88 923snd_rme96_set_period_properties(struct rme96 *rme96,
1da177e4
LT		 924 size_t period_bytes)
925{
926 switch (period_bytes) {
927 case RME96_LARGE_BLOCK_SIZE:
928 rme96->wcreg &= ~RME96_WCR_ISEL;
929 break;
930 case RME96_SMALL_BLOCK_SIZE:
931 rme96->wcreg |= RME96_WCR_ISEL;
932 break;
933 default:
934 snd_BUG();
935 break;
936 }
937 rme96->wcreg &= ~RME96_WCR_IDIS;
938 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
939}
940
941static int
a3aefd88
TI		 942snd_rme96_playback_hw_params(struct snd_pcm_substream *substream,
943 struct snd_pcm_hw_params *params)
1da177e4 944{
a3aefd88
TI		 945 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
946 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4 947 int err, rate, dummy;
43702b71 948 bool apply_dac_volume = false;
1da177e4 949
4d23359b
CL		 950 runtime->dma_area = (void __force *)(rme96->iobase +
951 RME96_IO_PLAY_BUFFER);
1da177e4
LT		 952 runtime->dma_addr = rme96->port + RME96_IO_PLAY_BUFFER;
953 runtime->dma_bytes = RME96_BUFFER_SIZE;
954
955 spin_lock_irq(&rme96->lock);
956 if (!(rme96->wcreg & RME96_WCR_MASTER) &&
957 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
958 (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
959 {
960 /* slave clock */
961 if ((int)params_rate(params) != rate) {
43702b71
TI		 962 err = -EIO;
963 goto error;
964 }
965 } else {
966 err = snd_rme96_playback_setrate(rme96, params_rate(params));
967 if (err < 0)
968 goto error;
969 apply_dac_volume = err > 0; /* need to restore volume later? */
1da177e4 970 }
43702b71
TI		 971
972 err = snd_rme96_playback_setformat(rme96, params_format(params));
973 if (err < 0)
974 goto error;
1da177e4
LT		 975 snd_rme96_setframelog(rme96, params_channels(params), 1);
976 if (rme96->capture_periodsize != 0) {
977 if (params_period_size(params) << rme96->playback_frlog !=
978 rme96->capture_periodsize)
979 {
43702b71
TI		 980 err = -EBUSY;
981 goto error;
1da177e4
LT		 982 }
983 }
984 rme96->playback_periodsize =
985 params_period_size(params) << rme96->playback_frlog;
986 snd_rme96_set_period_properties(rme96, rme96->playback_periodsize);
987 /* S/PDIF setup */
988 if ((rme96->wcreg & RME96_WCR_ADAT) == 0) {
989 rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);
990 writel(rme96->wcreg |= rme96->wcreg_spdif_stream, rme96->iobase + RME96_IO_CONTROL_REGISTER);
991 }
43702b71
TI		 992
993 err = 0;
994 error:
1da177e4 995 spin_unlock_irq(&rme96->lock);
43702b71
TI		 996 if (apply_dac_volume) {
997 usleep_range(3000, 10000);
998 snd_rme96_apply_dac_volume(rme96);
999 }
1000
1001 return err;
1da177e4
LT		 1002}
1003
1004static int
a3aefd88
TI		 1005snd_rme96_capture_hw_params(struct snd_pcm_substream *substream,
1006 struct snd_pcm_hw_params *params)
1da177e4 1007{
a3aefd88
TI		 1008 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1009 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4
LT		 1010 int err, isadat, rate;
1011
4d23359b
CL		 1012 runtime->dma_area = (void __force *)(rme96->iobase +
1013 RME96_IO_REC_BUFFER);
1da177e4
LT		 1014 runtime->dma_addr = rme96->port + RME96_IO_REC_BUFFER;
1015 runtime->dma_bytes = RME96_BUFFER_SIZE;
1016
1017 spin_lock_irq(&rme96->lock);
1018 if ((err = snd_rme96_capture_setformat(rme96, params_format(params))) < 0) {
1019 spin_unlock_irq(&rme96->lock);
1020 return err;
1021 }
1022 if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
1023 if ((err = snd_rme96_capture_analog_setrate(rme96,
1024 params_rate(params))) < 0)
1025 {
1026 spin_unlock_irq(&rme96->lock);
1027 return err;
1028 }
1029 } else if ((rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0) {
1030 if ((int)params_rate(params) != rate) {
1031 spin_unlock_irq(&rme96->lock);
1032 return -EIO;
1033 }
1034 if ((isadat && runtime->hw.channels_min == 2) ||
1035 (!isadat && runtime->hw.channels_min == 8))
1036 {
1037 spin_unlock_irq(&rme96->lock);
1038 return -EIO;
1039 }
1040 }
1041 snd_rme96_setframelog(rme96, params_channels(params), 0);
1042 if (rme96->playback_periodsize != 0) {
1043 if (params_period_size(params) << rme96->capture_frlog !=
1044 rme96->playback_periodsize)
1045 {
1046 spin_unlock_irq(&rme96->lock);
1047 return -EBUSY;
1048 }
1049 }
1050 rme96->capture_periodsize =
1051 params_period_size(params) << rme96->capture_frlog;
1052 snd_rme96_set_period_properties(rme96, rme96->capture_periodsize);
1053 spin_unlock_irq(&rme96->lock);
1054
1055 return 0;
1056}
1057
1058static void
a3aefd88 1059snd_rme96_playback_start(struct rme96 *rme96,
1da177e4
LT		 1060 int from_pause)
1061{
1062 if (!from_pause) {
1063 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1064 }
1065
1066 rme96->wcreg |= RME96_WCR_START;
1067 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1068}
1069
1070static void
a3aefd88 1071snd_rme96_capture_start(struct rme96 *rme96,
1da177e4
LT		 1072 int from_pause)
1073{
1074 if (!from_pause) {
1075 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1076 }
1077
1078 rme96->wcreg |= RME96_WCR_START_2;
1079 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1080}
1081
1082static void
a3aefd88 1083snd_rme96_playback_stop(struct rme96 *rme96)
1da177e4
LT		 1084{
1085 /*
1086 * Check if there is an unconfirmed IRQ, if so confirm it, or else
1087 * the hardware will not stop generating interrupts
1088 */
1089 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1090 if (rme96->rcreg & RME96_RCR_IRQ) {
1091 writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ);
1092 }
1093 rme96->wcreg &= ~RME96_WCR_START;
1094 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1095}
1096
1097static void
a3aefd88 1098snd_rme96_capture_stop(struct rme96 *rme96)
1da177e4
LT		 1099{
1100 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1101 if (rme96->rcreg & RME96_RCR_IRQ_2) {
1102 writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ);
1103 }
1104 rme96->wcreg &= ~RME96_WCR_START_2;
1105 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1106}
1107
1108static irqreturn_t
1109snd_rme96_interrupt(int irq,
7d12e780 1110 void *dev_id)
1da177e4 1111{
a3aefd88 1112 struct rme96 *rme96 = (struct rme96 *)dev_id;
1da177e4
LT		 1113
1114 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1115 /* fastpath out, to ease interrupt sharing */
1116 if (!((rme96->rcreg & RME96_RCR_IRQ) ||
1117 (rme96->rcreg & RME96_RCR_IRQ_2)))
1118 {
1119 return IRQ_NONE;
1120 }
1121
1122 if (rme96->rcreg & RME96_RCR_IRQ) {
1123 /* playback */
1124 snd_pcm_period_elapsed(rme96->playback_substream);
1125 writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ);
1126 }
1127 if (rme96->rcreg & RME96_RCR_IRQ_2) {
1128 /* capture */
1129 snd_pcm_period_elapsed(rme96->capture_substream);
1130 writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ);
1131 }
1132 return IRQ_HANDLED;
1133}
1134
1135static unsigned int period_bytes[] = { RME96_SMALL_BLOCK_SIZE, RME96_LARGE_BLOCK_SIZE };
1136
a3aefd88 1137static struct snd_pcm_hw_constraint_list hw_constraints_period_bytes = {
1da177e4
LT		 1138 .count = ARRAY_SIZE(period_bytes),
1139 .list = period_bytes,
1140 .mask = 0
1141};
1142
2ce7fb57
TI		 1143static void
1144rme96_set_buffer_size_constraint(struct rme96 *rme96,
1145 struct snd_pcm_runtime *runtime)
1146{
1147 unsigned int size;
1148
1149 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1150 RME96_BUFFER_SIZE, RME96_BUFFER_SIZE);
1151 if ((size = rme96->playback_periodsize) != 0 ||
1152 (size = rme96->capture_periodsize) != 0)
1153 snd_pcm_hw_constraint_minmax(runtime,
1154 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1155 size, size);
1156 else
1157 snd_pcm_hw_constraint_list(runtime, 0,
1158 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1159 &hw_constraints_period_bytes);
1160}
1161
1da177e4 1162static int
a3aefd88 1163snd_rme96_playback_spdif_open(struct snd_pcm_substream *substream)
1da177e4
LT		 1164{
1165 int rate, dummy;
a3aefd88
TI		 1166 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1167 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4 1168
1da177e4
LT		 1169 spin_lock_irq(&rme96->lock);
1170 if (rme96->playback_substream != NULL) {
1171 spin_unlock_irq(&rme96->lock);
1172 return -EBUSY;
1173 }
1174 rme96->wcreg &= ~RME96_WCR_ADAT;
1175 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1176 rme96->playback_substream = substream;
1177 spin_unlock_irq(&rme96->lock);
1178
1179 runtime->hw = snd_rme96_playback_spdif_info;
1180 if (!(rme96->wcreg & RME96_WCR_MASTER) &&
1181 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
1182 (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
1183 {
1184 /* slave clock */
918f3a0e 1185 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
1da177e4
LT		 1186 runtime->hw.rate_min = rate;
1187 runtime->hw.rate_max = rate;
1188 }
2ce7fb57 1189 rme96_set_buffer_size_constraint(rme96, runtime);
1da177e4
LT		 1190
1191 rme96->wcreg_spdif_stream = rme96->wcreg_spdif;
1192 rme96->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1193 snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE |
1194 SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id);
1195 return 0;
1196}
1197
1198static int
a3aefd88 1199snd_rme96_capture_spdif_open(struct snd_pcm_substream *substream)
1da177e4
LT		 1200{
1201 int isadat, rate;
a3aefd88
TI		 1202 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1203 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4 1204
1da177e4
LT		 1205 runtime->hw = snd_rme96_capture_spdif_info;
1206 if (snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
1207 (rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0)
1208 {
1209 if (isadat) {
1210 return -EIO;
1211 }
918f3a0e 1212 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
1da177e4
LT		 1213 runtime->hw.rate_min = rate;
1214 runtime->hw.rate_max = rate;
1215 }
1216
1217 spin_lock_irq(&rme96->lock);
1218 if (rme96->capture_substream != NULL) {
1219 spin_unlock_irq(&rme96->lock);
1220 return -EBUSY;
1221 }
1222 rme96->capture_substream = substream;
1223 spin_unlock_irq(&rme96->lock);
1224
2ce7fb57 1225 rme96_set_buffer_size_constraint(rme96, runtime);
1da177e4
LT		 1226 return 0;
1227}
1228
1229static int
a3aefd88 1230snd_rme96_playback_adat_open(struct snd_pcm_substream *substream)
1da177e4
LT		 1231{
1232 int rate, dummy;
a3aefd88
TI		 1233 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1234 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4 1235
1da177e4
LT		 1236 spin_lock_irq(&rme96->lock);
1237 if (rme96->playback_substream != NULL) {
1238 spin_unlock_irq(&rme96->lock);
1239 return -EBUSY;
1240 }
1241 rme96->wcreg |= RME96_WCR_ADAT;
1242 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1243 rme96->playback_substream = substream;
1244 spin_unlock_irq(&rme96->lock);
1245
1246 runtime->hw = snd_rme96_playback_adat_info;
1247 if (!(rme96->wcreg & RME96_WCR_MASTER) &&
1248 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
1249 (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
1250 {
1251 /* slave clock */
918f3a0e 1252 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
1da177e4
LT		 1253 runtime->hw.rate_min = rate;
1254 runtime->hw.rate_max = rate;
1255 }
2ce7fb57 1256 rme96_set_buffer_size_constraint(rme96, runtime);
1da177e4
LT		 1257 return 0;
1258}
1259
1260static int
a3aefd88 1261snd_rme96_capture_adat_open(struct snd_pcm_substream *substream)
1da177e4
LT		 1262{
1263 int isadat, rate;
a3aefd88
TI		 1264 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1265 struct snd_pcm_runtime *runtime = substream->runtime;
1da177e4 1266
1da177e4
LT		 1267 runtime->hw = snd_rme96_capture_adat_info;
1268 if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
1269 /* makes no sense to use analog input. Note that analog
1270 expension cards AEB4/8-I are RME96_INPUT_INTERNAL */
1271 return -EIO;
1272 }
1273 if ((rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0) {
1274 if (!isadat) {
1275 return -EIO;
1276 }
918f3a0e 1277 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
1da177e4
LT		 1278 runtime->hw.rate_min = rate;
1279 runtime->hw.rate_max = rate;
1280 }
1281
1282 spin_lock_irq(&rme96->lock);
1283 if (rme96->capture_substream != NULL) {
1284 spin_unlock_irq(&rme96->lock);
1285 return -EBUSY;
1286 }
1287 rme96->capture_substream = substream;
1288 spin_unlock_irq(&rme96->lock);
1289
2ce7fb57 1290 rme96_set_buffer_size_constraint(rme96, runtime);
1da177e4
LT		 1291 return 0;
1292}
1293
1294static int
a3aefd88 1295snd_rme96_playback_close(struct snd_pcm_substream *substream)
1da177e4 1296{
a3aefd88 1297 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1da177e4
LT		 1298 int spdif = 0;
1299
1300 spin_lock_irq(&rme96->lock);
1301 if (RME96_ISPLAYING(rme96)) {
1302 snd_rme96_playback_stop(rme96);
1303 }
1304 rme96->playback_substream = NULL;
1305 rme96->playback_periodsize = 0;
1306 spdif = (rme96->wcreg & RME96_WCR_ADAT) == 0;
1307 spin_unlock_irq(&rme96->lock);
1308 if (spdif) {
1309 rme96->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1310 snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE |
1311 SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id);
1312 }
1313 return 0;
1314}
1315
1316static int
a3aefd88 1317snd_rme96_capture_close(struct snd_pcm_substream *substream)
1da177e4 1318{
a3aefd88 1319 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1da177e4
LT		 1320
1321 spin_lock_irq(&rme96->lock);
1322 if (RME96_ISRECORDING(rme96)) {
1323 snd_rme96_capture_stop(rme96);
1324 }
1325 rme96->capture_substream = NULL;
1326 rme96->capture_periodsize = 0;
1327 spin_unlock_irq(&rme96->lock);
1328 return 0;
1329}
1330
1331static int
a3aefd88 1332snd_rme96_playback_prepare(struct snd_pcm_substream *substream)
1da177e4 1333{
a3aefd88 1334 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1da177e4
LT		 1335
1336 spin_lock_irq(&rme96->lock);
1337 if (RME96_ISPLAYING(rme96)) {
1338 snd_rme96_playback_stop(rme96);
1339 }
1340 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1341 spin_unlock_irq(&rme96->lock);
1342 return 0;
1343}
1344
1345static int
a3aefd88 1346snd_rme96_capture_prepare(struct snd_pcm_substream *substream)
1da177e4 1347{
a3aefd88 1348 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1da177e4
LT		 1349
1350 spin_lock_irq(&rme96->lock);
1351 if (RME96_ISRECORDING(rme96)) {
1352 snd_rme96_capture_stop(rme96);
1353 }
1354 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1355 spin_unlock_irq(&rme96->lock);
1356 return 0;
1357}
1358
1359static int
a3aefd88 1360snd_rme96_playback_trigger(struct snd_pcm_substream *substream,
1da177e4
LT		 1361 int cmd)
1362{
a3aefd88 1363 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1da177e4
LT		 1364
1365 switch (cmd) {
1366 case SNDRV_PCM_TRIGGER_START:
1367 if (!RME96_ISPLAYING(rme96)) {
1368 if (substream != rme96->playback_substream) {
1369 return -EBUSY;
1370 }
1371 snd_rme96_playback_start(rme96, 0);
1372 }
1373 break;
1374
1375 case SNDRV_PCM_TRIGGER_STOP:
1376 if (RME96_ISPLAYING(rme96)) {
1377 if (substream != rme96->playback_substream) {
1378 return -EBUSY;
1379 }
1380 snd_rme96_playback_stop(rme96);
1381 }
1382 break;
1383
1384 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1385 if (RME96_ISPLAYING(rme96)) {
1386 snd_rme96_playback_stop(rme96);
1387 }
1388 break;
1389
1390 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1391 if (!RME96_ISPLAYING(rme96)) {
1392 snd_rme96_playback_start(rme96, 1);
1393 }
1394 break;
1395
1396 default:
1397 return -EINVAL;
1398 }
1399 return 0;
1400}
1401
1402static int
a3aefd88 1403snd_rme96_capture_trigger(struct snd_pcm_substream *substream,
1da177e4
LT		 1404 int cmd)
1405{
a3aefd88 1406 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1da177e4
LT		 1407
1408 switch (cmd) {
1409 case SNDRV_PCM_TRIGGER_START:
1410 if (!RME96_ISRECORDING(rme96)) {
1411 if (substream != rme96->capture_substream) {
1412 return -EBUSY;
1413 }
1414 snd_rme96_capture_start(rme96, 0);
1415 }
1416 break;
1417
1418 case SNDRV_PCM_TRIGGER_STOP:
1419 if (RME96_ISRECORDING(rme96)) {
1420 if (substream != rme96->capture_substream) {
1421 return -EBUSY;
1422 }
1423 snd_rme96_capture_stop(rme96);
1424 }
1425 break;
1426
1427 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1428 if (RME96_ISRECORDING(rme96)) {
1429 snd_rme96_capture_stop(rme96);
1430 }
1431 break;
1432
1433 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1434 if (!RME96_ISRECORDING(rme96)) {
1435 snd_rme96_capture_start(rme96, 1);
1436 }
1437 break;
1438
1439 default:
1440 return -EINVAL;
1441 }
1442
1443 return 0;
1444}
1445
1446static snd_pcm_uframes_t
a3aefd88 1447snd_rme96_playback_pointer(struct snd_pcm_substream *substream)
1da177e4 1448{
a3aefd88 1449 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1da177e4
LT		 1450 return snd_rme96_playback_ptr(rme96);
1451}
1452
1453static snd_pcm_uframes_t
a3aefd88 1454snd_rme96_capture_pointer(struct snd_pcm_substream *substream)
1da177e4 1455{
a3aefd88 1456 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1da177e4
LT		 1457 return snd_rme96_capture_ptr(rme96);
1458}
1459
a3aefd88 1460static struct snd_pcm_ops snd_rme96_playback_spdif_ops = {
1da177e4
LT		 1461 .open = snd_rme96_playback_spdif_open,
1462 .close = snd_rme96_playback_close,
1463 .ioctl = snd_pcm_lib_ioctl,
1464 .hw_params = snd_rme96_playback_hw_params,
1465 .prepare = snd_rme96_playback_prepare,
1466 .trigger = snd_rme96_playback_trigger,
1467 .pointer = snd_rme96_playback_pointer,
1468 .copy = snd_rme96_playback_copy,
1469 .silence = snd_rme96_playback_silence,
1470 .mmap = snd_pcm_lib_mmap_iomem,
1471};
1472
a3aefd88 1473static struct snd_pcm_ops snd_rme96_capture_spdif_ops = {
1da177e4
LT		 1474 .open = snd_rme96_capture_spdif_open,
1475 .close = snd_rme96_capture_close,
1476 .ioctl = snd_pcm_lib_ioctl,
1477 .hw_params = snd_rme96_capture_hw_params,
1478 .prepare = snd_rme96_capture_prepare,
1479 .trigger = snd_rme96_capture_trigger,
1480 .pointer = snd_rme96_capture_pointer,
1481 .copy = snd_rme96_capture_copy,
1482 .mmap = snd_pcm_lib_mmap_iomem,
1483};
1484
a3aefd88 1485static struct snd_pcm_ops snd_rme96_playback_adat_ops = {
1da177e4
LT		 1486 .open = snd_rme96_playback_adat_open,
1487 .close = snd_rme96_playback_close,
1488 .ioctl = snd_pcm_lib_ioctl,
1489 .hw_params = snd_rme96_playback_hw_params,
1490 .prepare = snd_rme96_playback_prepare,
1491 .trigger = snd_rme96_playback_trigger,
1492 .pointer = snd_rme96_playback_pointer,
1493 .copy = snd_rme96_playback_copy,
1494 .silence = snd_rme96_playback_silence,
1495 .mmap = snd_pcm_lib_mmap_iomem,
1496};
1497
a3aefd88 1498static struct snd_pcm_ops snd_rme96_capture_adat_ops = {
1da177e4
LT		 1499 .open = snd_rme96_capture_adat_open,
1500 .close = snd_rme96_capture_close,
1501 .ioctl = snd_pcm_lib_ioctl,
1502 .hw_params = snd_rme96_capture_hw_params,
1503 .prepare = snd_rme96_capture_prepare,
1504 .trigger = snd_rme96_capture_trigger,
1505 .pointer = snd_rme96_capture_pointer,
1506 .copy = snd_rme96_capture_copy,
1507 .mmap = snd_pcm_lib_mmap_iomem,
1508};
1509
1510static void
1511snd_rme96_free(void *private_data)
1512{
a3aefd88 1513 struct rme96 *rme96 = (struct rme96 *)private_data;
1da177e4
LT		 1514
1515 if (rme96 == NULL) {
1516 return;
1517 }
1518 if (rme96->irq >= 0) {
1519 snd_rme96_playback_stop(rme96);
1520 snd_rme96_capture_stop(rme96);
1521 rme96->areg &= ~RME96_AR_DAC_EN;
1522 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1523 free_irq(rme96->irq, (void *)rme96);
1524 rme96->irq = -1;
1525 }
1526 if (rme96->iobase) {
1527 iounmap(rme96->iobase);
1528 rme96->iobase = NULL;
1529 }
1530 if (rme96->port) {
1531 pci_release_regions(rme96->pci);
1532 rme96->port = 0;
1533 }
1534 pci_disable_device(rme96->pci);
1535}
1536
1537static void
a3aefd88 1538snd_rme96_free_spdif_pcm(struct snd_pcm *pcm)
1da177e4 1539{
9fe856e4 1540 struct rme96 *rme96 = pcm->private_data;
1da177e4
LT		 1541 rme96->spdif_pcm = NULL;
1542}
1543
1544static void
a3aefd88 1545snd_rme96_free_adat_pcm(struct snd_pcm *pcm)
1da177e4 1546{
9fe856e4 1547 struct rme96 *rme96 = pcm->private_data;
1da177e4
LT		 1548 rme96->adat_pcm = NULL;
1549}
1550
e23e7a14 1551static int
a3aefd88 1552snd_rme96_create(struct rme96 *rme96)
1da177e4
LT		 1553{
1554 struct pci_dev *pci = rme96->pci;
1555 int err;
1556
1557 rme96->irq = -1;
1558 spin_lock_init(&rme96->lock);
1559
1560 if ((err = pci_enable_device(pci)) < 0)
1561 return err;
1562
1563 if ((err = pci_request_regions(pci, "RME96")) < 0)
1564 return err;
1565 rme96->port = pci_resource_start(rme96->pci, 0);
1566
44977b71
HH		 1567 rme96->iobase = ioremap_nocache(rme96->port, RME96_IO_SIZE);
1568 if (!rme96->iobase) {
688956f2
TI		 1569 snd_printk(KERN_ERR "unable to remap memory region 0x%lx-0x%lx\n", rme96->port, rme96->port + RME96_IO_SIZE - 1);
1570 return -ENOMEM;
1571 }
1572
437a5a46 1573 if (request_irq(pci->irq, snd_rme96_interrupt, IRQF_SHARED,
934c2b6d 1574 KBUILD_MODNAME, rme96)) {
99b359ba 1575 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
1da177e4
LT		 1576 return -EBUSY;
1577 }
1578 rme96->irq = pci->irq;
1579
1da177e4
LT		 1580 /* read the card's revision number */
1581 pci_read_config_byte(pci, 8, &rme96->rev);
1582
1583 /* set up ALSA pcm device for S/PDIF */
1584 if ((err = snd_pcm_new(rme96->card, "Digi96 IEC958", 0,
1585 1, 1, &rme96->spdif_pcm)) < 0)
1586 {
1587 return err;
1588 }
1589 rme96->spdif_pcm->private_data = rme96;
1590 rme96->spdif_pcm->private_free = snd_rme96_free_spdif_pcm;
1591 strcpy(rme96->spdif_pcm->name, "Digi96 IEC958");
1592 snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_spdif_ops);
1593 snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_spdif_ops);
1594
1595 rme96->spdif_pcm->info_flags = 0;
1596
1597 /* set up ALSA pcm device for ADAT */
8b7fc421 1598 if (pci->device == PCI_DEVICE_ID_RME_DIGI96) {
1da177e4
LT		 1599 /* ADAT is not available on the base model */
1600 rme96->adat_pcm = NULL;
1601 } else {
1602 if ((err = snd_pcm_new(rme96->card, "Digi96 ADAT", 1,
1603 1, 1, &rme96->adat_pcm)) < 0)
1604 {
1605 return err;
1606 }
1607 rme96->adat_pcm->private_data = rme96;
1608 rme96->adat_pcm->private_free = snd_rme96_free_adat_pcm;
1609 strcpy(rme96->adat_pcm->name, "Digi96 ADAT");
1610 snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_adat_ops);
1611 snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_adat_ops);
1612
1613 rme96->adat_pcm->info_flags = 0;
1614 }
1615
1616 rme96->playback_periodsize = 0;
1617 rme96->capture_periodsize = 0;
1618
1619 /* make sure playback/capture is stopped, if by some reason active */
1620 snd_rme96_playback_stop(rme96);
1621 snd_rme96_capture_stop(rme96);
1622
1623 /* set default values in registers */
1624 rme96->wcreg =
1625 RME96_WCR_FREQ_1 | /* set 44.1 kHz playback */
1626 RME96_WCR_SEL | /* normal playback */
1627 RME96_WCR_MASTER | /* set to master clock mode */
1628 RME96_WCR_INP_0; /* set coaxial input */
1629
1630 rme96->areg = RME96_AR_FREQPAD_1; /* set 44.1 kHz analog capture */
1631
1632 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1633 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1634
1635 /* reset the ADC */
1636 writel(rme96->areg | RME96_AR_PD2,
1637 rme96->iobase + RME96_IO_ADDITIONAL_REG);
1638 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1639
1640 /* reset and enable the DAC (order is important). */
1641 snd_rme96_reset_dac(rme96);
1642 rme96->areg |= RME96_AR_DAC_EN;
1643 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1644
1645 /* reset playback and record buffer pointers */
1646 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1647 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1648
1649 /* reset volume */
1650 rme96->vol[0] = rme96->vol[1] = 0;
1651 if (RME96_HAS_ANALOG_OUT(rme96)) {
1652 snd_rme96_apply_dac_volume(rme96);
1653 }
1654
1655 /* init switch interface */
1656 if ((err = snd_rme96_create_switches(rme96->card, rme96)) < 0) {
1657 return err;
1658 }
1659
1660 /* init proc interface */
1661 snd_rme96_proc_init(rme96);
1662
1663 return 0;
1664}
1665
1666/*
1667 * proc interface
1668 */
1669
1670static void
a3aefd88 1671snd_rme96_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
1da177e4
LT		 1672{
1673 int n;
9fe856e4 1674 struct rme96 *rme96 = entry->private_data;
1da177e4
LT		 1675
1676 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1677
1678 snd_iprintf(buffer, rme96->card->longname);
1679 snd_iprintf(buffer, " (index #%d)\n", rme96->card->number + 1);
1680
1681 snd_iprintf(buffer, "\nGeneral settings\n");
1682 if (rme96->wcreg & RME96_WCR_IDIS) {
1683 snd_iprintf(buffer, " period size: N/A (interrupts "
1684 "disabled)\n");
1685 } else if (rme96->wcreg & RME96_WCR_ISEL) {
1686 snd_iprintf(buffer, " period size: 2048 bytes\n");
1687 } else {
1688 snd_iprintf(buffer, " period size: 8192 bytes\n");
1689 }
1690 snd_iprintf(buffer, "\nInput settings\n");
1691 switch (snd_rme96_getinputtype(rme96)) {
1692 case RME96_INPUT_OPTICAL:
1693 snd_iprintf(buffer, " input: optical");
1694 break;
1695 case RME96_INPUT_COAXIAL:
1696 snd_iprintf(buffer, " input: coaxial");
1697 break;
1698 case RME96_INPUT_INTERNAL:
1699 snd_iprintf(buffer, " input: internal");
1700 break;
1701 case RME96_INPUT_XLR:
1702 snd_iprintf(buffer, " input: XLR");
1703 break;
1704 case RME96_INPUT_ANALOG:
1705 snd_iprintf(buffer, " input: analog");
1706 break;
1707 }
1708 if (snd_rme96_capture_getrate(rme96, &n) < 0) {
1709 snd_iprintf(buffer, "\n sample rate: no valid signal\n");
1710 } else {
1711 if (n) {
1712 snd_iprintf(buffer, " (8 channels)\n");
1713 } else {
1714 snd_iprintf(buffer, " (2 channels)\n");
1715 }
1716 snd_iprintf(buffer, " sample rate: %d Hz\n",
1717 snd_rme96_capture_getrate(rme96, &n));
1718 }
1719 if (rme96->wcreg & RME96_WCR_MODE24_2) {
1720 snd_iprintf(buffer, " sample format: 24 bit\n");
1721 } else {
1722 snd_iprintf(buffer, " sample format: 16 bit\n");
1723 }
1724
1725 snd_iprintf(buffer, "\nOutput settings\n");
1726 if (rme96->wcreg & RME96_WCR_SEL) {
1727 snd_iprintf(buffer, " output signal: normal playback\n");
1728 } else {
1729 snd_iprintf(buffer, " output signal: same as input\n");
1730 }
1731 snd_iprintf(buffer, " sample rate: %d Hz\n",
1732 snd_rme96_playback_getrate(rme96));
1733 if (rme96->wcreg & RME96_WCR_MODE24) {
1734 snd_iprintf(buffer, " sample format: 24 bit\n");
1735 } else {
1736 snd_iprintf(buffer, " sample format: 16 bit\n");
1737 }
1738 if (rme96->areg & RME96_AR_WSEL) {
1739 snd_iprintf(buffer, " sample clock source: word clock\n");
1740 } else if (rme96->wcreg & RME96_WCR_MASTER) {
1741 snd_iprintf(buffer, " sample clock source: internal\n");
1742 } else if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
1743 snd_iprintf(buffer, " sample clock source: autosync (internal anyway due to analog input setting)\n");
1744 } else if (snd_rme96_capture_getrate(rme96, &n) < 0) {
1745 snd_iprintf(buffer, " sample clock source: autosync (internal anyway due to no valid signal)\n");
1746 } else {
1747 snd_iprintf(buffer, " sample clock source: autosync\n");
1748 }
1749 if (rme96->wcreg & RME96_WCR_PRO) {
1750 snd_iprintf(buffer, " format: AES/EBU (professional)\n");
1751 } else {
1752 snd_iprintf(buffer, " format: IEC958 (consumer)\n");
1753 }
1754 if (rme96->wcreg & RME96_WCR_EMP) {
1755 snd_iprintf(buffer, " emphasis: on\n");
1756 } else {
1757 snd_iprintf(buffer, " emphasis: off\n");
1758 }
1759 if (rme96->wcreg & RME96_WCR_DOLBY) {
1760 snd_iprintf(buffer, " non-audio (dolby): on\n");
1761 } else {
1762 snd_iprintf(buffer, " non-audio (dolby): off\n");
1763 }
1764 if (RME96_HAS_ANALOG_IN(rme96)) {
1765 snd_iprintf(buffer, "\nAnalog output settings\n");
1766 switch (snd_rme96_getmontracks(rme96)) {
1767 case RME96_MONITOR_TRACKS_1_2:
1768 snd_iprintf(buffer, " monitored ADAT tracks: 1+2\n");
1769 break;
1770 case RME96_MONITOR_TRACKS_3_4:
1771 snd_iprintf(buffer, " monitored ADAT tracks: 3+4\n");
1772 break;
1773 case RME96_MONITOR_TRACKS_5_6:
1774 snd_iprintf(buffer, " monitored ADAT tracks: 5+6\n");
1775 break;
1776 case RME96_MONITOR_TRACKS_7_8:
1777 snd_iprintf(buffer, " monitored ADAT tracks: 7+8\n");
1778 break;
1779 }
1780 switch (snd_rme96_getattenuation(rme96)) {
1781 case RME96_ATTENUATION_0:
1782 snd_iprintf(buffer, " attenuation: 0 dB\n");
1783 break;
1784 case RME96_ATTENUATION_6:
1785 snd_iprintf(buffer, " attenuation: -6 dB\n");
1786 break;
1787 case RME96_ATTENUATION_12:
1788 snd_iprintf(buffer, " attenuation: -12 dB\n");
1789 break;
1790 case RME96_ATTENUATION_18:
1791 snd_iprintf(buffer, " attenuation: -18 dB\n");
1792 break;
1793 }
1794 snd_iprintf(buffer, " volume left: %u\n", rme96->vol[0]);
1795 snd_iprintf(buffer, " volume right: %u\n", rme96->vol[1]);
1796 }
1797}
1798
e23e7a14 1799static void snd_rme96_proc_init(struct rme96 *rme96)
1da177e4 1800{
a3aefd88 1801 struct snd_info_entry *entry;
1da177e4
LT		 1802
1803 if (! snd_card_proc_new(rme96->card, "rme96", &entry))
bf850204 1804 snd_info_set_text_ops(entry, rme96, snd_rme96_proc_read);
1da177e4
LT		 1805}
1806
1807/*
1808 * control interface
1809 */
1810
a5ce8890
TI		 1811#define snd_rme96_info_loopback_control snd_ctl_boolean_mono_info
1812
1da177e4 1813static int
a3aefd88 1814snd_rme96_get_loopback_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1815{
a3aefd88 1816 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1817
1818 spin_lock_irq(&rme96->lock);
1819 ucontrol->value.integer.value[0] = rme96->wcreg & RME96_WCR_SEL ? 0 : 1;
1820 spin_unlock_irq(&rme96->lock);
1821 return 0;
1822}
1823static int
a3aefd88 1824snd_rme96_put_loopback_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1825{
a3aefd88 1826 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1827 unsigned int val;
1828 int change;
1829
1830 val = ucontrol->value.integer.value[0] ? 0 : RME96_WCR_SEL;
1831 spin_lock_irq(&rme96->lock);
1832 val = (rme96->wcreg & ~RME96_WCR_SEL) | val;
1833 change = val != rme96->wcreg;
1834 rme96->wcreg = val;
1835 writel(val, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1836 spin_unlock_irq(&rme96->lock);
1837 return change;
1838}
1839
1840static int
a3aefd88 1841snd_rme96_info_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 1842{
1843 static char *_texts[5] = { "Optical", "Coaxial", "Internal", "XLR", "Analog" };
a3aefd88 1844 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1845 char *texts[5] = { _texts[0], _texts[1], _texts[2], _texts[3], _texts[4] };
1846
1847 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1848 uinfo->count = 1;
1849 switch (rme96->pci->device) {
8b7fc421
RD		 1850 case PCI_DEVICE_ID_RME_DIGI96:
1851 case PCI_DEVICE_ID_RME_DIGI96_8:
1da177e4
LT		 1852 uinfo->value.enumerated.items = 3;
1853 break;
8b7fc421 1854 case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
1da177e4
LT		 1855 uinfo->value.enumerated.items = 4;
1856 break;
8b7fc421 1857 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
1da177e4
LT		 1858 if (rme96->rev > 4) {
1859 /* PST */
1860 uinfo->value.enumerated.items = 4;
1861 texts[3] = _texts[4]; /* Analog instead of XLR */
1862 } else {
1863 /* PAD */
1864 uinfo->value.enumerated.items = 5;
1865 }
1866 break;
1867 default:
1868 snd_BUG();
1869 break;
1870 }
1871 if (uinfo->value.enumerated.item > uinfo->value.enumerated.items - 1) {
1872 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1873 }
1874 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1875 return 0;
1876}
1877static int
a3aefd88 1878snd_rme96_get_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1879{
a3aefd88 1880 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1881 unsigned int items = 3;
1882
1883 spin_lock_irq(&rme96->lock);
1884 ucontrol->value.enumerated.item[0] = snd_rme96_getinputtype(rme96);
1885
1886 switch (rme96->pci->device) {
8b7fc421
RD		 1887 case PCI_DEVICE_ID_RME_DIGI96:
1888 case PCI_DEVICE_ID_RME_DIGI96_8:
1da177e4
LT		 1889 items = 3;
1890 break;
8b7fc421 1891 case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
1da177e4
LT		 1892 items = 4;
1893 break;
8b7fc421 1894 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
1da177e4
LT		 1895 if (rme96->rev > 4) {
1896 /* for handling PST case, (INPUT_ANALOG is moved to INPUT_XLR */
1897 if (ucontrol->value.enumerated.item[0] == RME96_INPUT_ANALOG) {
1898 ucontrol->value.enumerated.item[0] = RME96_INPUT_XLR;
1899 }
1900 items = 4;
1901 } else {
1902 items = 5;
1903 }
1904 break;
1905 default:
1906 snd_BUG();
1907 break;
1908 }
1909 if (ucontrol->value.enumerated.item[0] >= items) {
1910 ucontrol->value.enumerated.item[0] = items - 1;
1911 }
1912
1913 spin_unlock_irq(&rme96->lock);
1914 return 0;
1915}
1916static int
a3aefd88 1917snd_rme96_put_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1918{
a3aefd88 1919 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1920 unsigned int val;
1921 int change, items = 3;
1922
1923 switch (rme96->pci->device) {
8b7fc421
RD		 1924 case PCI_DEVICE_ID_RME_DIGI96:
1925 case PCI_DEVICE_ID_RME_DIGI96_8:
1da177e4
LT		 1926 items = 3;
1927 break;
8b7fc421 1928 case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
1da177e4
LT		 1929 items = 4;
1930 break;
8b7fc421 1931 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
1da177e4
LT		 1932 if (rme96->rev > 4) {
1933 items = 4;
1934 } else {
1935 items = 5;
1936 }
1937 break;
1938 default:
1939 snd_BUG();
1940 break;
1941 }
1942 val = ucontrol->value.enumerated.item[0] % items;
1943
1944 /* special case for PST */
8b7fc421 1945 if (rme96->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && rme96->rev > 4) {
1da177e4
LT		 1946 if (val == RME96_INPUT_XLR) {
1947 val = RME96_INPUT_ANALOG;
1948 }
1949 }
1950
1951 spin_lock_irq(&rme96->lock);
1952 change = (int)val != snd_rme96_getinputtype(rme96);
1953 snd_rme96_setinputtype(rme96, val);
1954 spin_unlock_irq(&rme96->lock);
1955 return change;
1956}
1957
1958static int
a3aefd88 1959snd_rme96_info_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 1960{
1961 static char *texts[3] = { "AutoSync", "Internal", "Word" };
1962
1963 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1964 uinfo->count = 1;
1965 uinfo->value.enumerated.items = 3;
1966 if (uinfo->value.enumerated.item > 2) {
1967 uinfo->value.enumerated.item = 2;
1968 }
1969 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1970 return 0;
1971}
1972static int
a3aefd88 1973snd_rme96_get_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1974{
a3aefd88 1975 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1976
1977 spin_lock_irq(&rme96->lock);
1978 ucontrol->value.enumerated.item[0] = snd_rme96_getclockmode(rme96);
1979 spin_unlock_irq(&rme96->lock);
1980 return 0;
1981}
1982static int
a3aefd88 1983snd_rme96_put_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 1984{
a3aefd88 1985 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 1986 unsigned int val;
1987 int change;
1988
1989 val = ucontrol->value.enumerated.item[0] % 3;
1990 spin_lock_irq(&rme96->lock);
1991 change = (int)val != snd_rme96_getclockmode(rme96);
1992 snd_rme96_setclockmode(rme96, val);
1993 spin_unlock_irq(&rme96->lock);
1994 return change;
1995}
1996
1997static int
a3aefd88 1998snd_rme96_info_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 1999{
2000 static char *texts[4] = { "0 dB", "-6 dB", "-12 dB", "-18 dB" };
2001
2002 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2003 uinfo->count = 1;
2004 uinfo->value.enumerated.items = 4;
2005 if (uinfo->value.enumerated.item > 3) {
2006 uinfo->value.enumerated.item = 3;
2007 }
2008 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2009 return 0;
2010}
2011static int
a3aefd88 2012snd_rme96_get_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2013{
a3aefd88 2014 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2015
2016 spin_lock_irq(&rme96->lock);
2017 ucontrol->value.enumerated.item[0] = snd_rme96_getattenuation(rme96);
2018 spin_unlock_irq(&rme96->lock);
2019 return 0;
2020}
2021static int
a3aefd88 2022snd_rme96_put_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2023{
a3aefd88 2024 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2025 unsigned int val;
2026 int change;
2027
2028 val = ucontrol->value.enumerated.item[0] % 4;
2029 spin_lock_irq(&rme96->lock);
2030
2031 change = (int)val != snd_rme96_getattenuation(rme96);
2032 snd_rme96_setattenuation(rme96, val);
2033 spin_unlock_irq(&rme96->lock);
2034 return change;
2035}
2036
2037static int
a3aefd88 2038snd_rme96_info_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 2039{
2040 static char *texts[4] = { "1+2", "3+4", "5+6", "7+8" };
2041
2042 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2043 uinfo->count = 1;
2044 uinfo->value.enumerated.items = 4;
2045 if (uinfo->value.enumerated.item > 3) {
2046 uinfo->value.enumerated.item = 3;
2047 }
2048 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2049 return 0;
2050}
2051static int
a3aefd88 2052snd_rme96_get_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2053{
a3aefd88 2054 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2055
2056 spin_lock_irq(&rme96->lock);
2057 ucontrol->value.enumerated.item[0] = snd_rme96_getmontracks(rme96);
2058 spin_unlock_irq(&rme96->lock);
2059 return 0;
2060}
2061static int
a3aefd88 2062snd_rme96_put_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2063{
a3aefd88 2064 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2065 unsigned int val;
2066 int change;
2067
2068 val = ucontrol->value.enumerated.item[0] % 4;
2069 spin_lock_irq(&rme96->lock);
2070 change = (int)val != snd_rme96_getmontracks(rme96);
2071 snd_rme96_setmontracks(rme96, val);
2072 spin_unlock_irq(&rme96->lock);
2073 return change;
2074}
2075
a3aefd88 2076static u32 snd_rme96_convert_from_aes(struct snd_aes_iec958 *aes)
1da177e4
LT		 2077{
2078 u32 val = 0;
2079 val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME96_WCR_PRO : 0;
2080 val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? RME96_WCR_DOLBY : 0;
2081 if (val & RME96_WCR_PRO)
2082 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME96_WCR_EMP : 0;
2083 else
2084 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME96_WCR_EMP : 0;
2085 return val;
2086}
2087
a3aefd88 2088static void snd_rme96_convert_to_aes(struct snd_aes_iec958 *aes, u32 val)
1da177e4
LT		 2089{
2090 aes->status[0] = ((val & RME96_WCR_PRO) ? IEC958_AES0_PROFESSIONAL : 0) |
2091 ((val & RME96_WCR_DOLBY) ? IEC958_AES0_NONAUDIO : 0);
2092 if (val & RME96_WCR_PRO)
2093 aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
2094 else
2095 aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
2096}
2097
a3aefd88 2098static int snd_rme96_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 2099{
2100 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2101 uinfo->count = 1;
2102 return 0;
2103}
2104
a3aefd88 2105static int snd_rme96_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2106{
a3aefd88 2107 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2108
2109 snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif);
2110 return 0;
2111}
2112
a3aefd88 2113static int snd_rme96_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2114{
a3aefd88 2115 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2116 int change;
2117 u32 val;
2118
2119 val = snd_rme96_convert_from_aes(&ucontrol->value.iec958);
2120 spin_lock_irq(&rme96->lock);
2121 change = val != rme96->wcreg_spdif;
2122 rme96->wcreg_spdif = val;
2123 spin_unlock_irq(&rme96->lock);
2124 return change;
2125}
2126
a3aefd88 2127static int snd_rme96_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 2128{
2129 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2130 uinfo->count = 1;
2131 return 0;
2132}
2133
a3aefd88 2134static int snd_rme96_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2135{
a3aefd88 2136 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2137
2138 snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif_stream);
2139 return 0;
2140}
2141
a3aefd88 2142static int snd_rme96_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4 2143{
a3aefd88 2144 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2145 int change;
2146 u32 val;
2147
2148 val = snd_rme96_convert_from_aes(&ucontrol->value.iec958);
2149 spin_lock_irq(&rme96->lock);
2150 change = val != rme96->wcreg_spdif_stream;
2151 rme96->wcreg_spdif_stream = val;
2152 rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);
2153 rme96->wcreg |= val;
2154 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
2155 spin_unlock_irq(&rme96->lock);
2156 return change;
2157}
2158
a3aefd88 2159static int snd_rme96_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4
LT		 2160{
2161 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2162 uinfo->count = 1;
2163 return 0;
2164}
2165
a3aefd88 2166static int snd_rme96_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1da177e4
LT		 2167{
2168 ucontrol->value.iec958.status[0] = kcontrol->private_value;
2169 return 0;
2170}
2171
2172static int
a3aefd88 2173snd_rme96_dac_volume_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1da177e4 2174{
a3aefd88 2175 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2176
2177 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2178 uinfo->count = 2;
2179 uinfo->value.integer.min = 0;
2180 uinfo->value.integer.max = RME96_185X_MAX_OUT(rme96);
2181 return 0;
2182}
2183
2184static int
a3aefd88 2185snd_rme96_dac_volume_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *u)
1da177e4 2186{
a3aefd88 2187 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4
LT		 2188
2189 spin_lock_irq(&rme96->lock);
2190 u->value.integer.value[0] = rme96->vol[0];
2191 u->value.integer.value[1] = rme96->vol[1];
2192 spin_unlock_irq(&rme96->lock);
2193
2194 return 0;
2195}
2196
2197static int
a3aefd88 2198snd_rme96_dac_volume_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *u)
1da177e4 2199{
a3aefd88 2200 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1da177e4 2201 int change = 0;
4e98d6a7 2202 unsigned int vol, maxvol;
1da177e4 2203
4e98d6a7
TI		 2204
2205 if (!RME96_HAS_ANALOG_OUT(rme96))
1da177e4 2206 return -EINVAL;
4e98d6a7 2207 maxvol = RME96_185X_MAX_OUT(rme96);
1da177e4 2208 spin_lock_irq(&rme96->lock);
4e98d6a7
TI		 2209 vol = u->value.integer.value[0];
2210 if (vol != rme96->vol[0] && vol <= maxvol) {
2211 rme96->vol[0] = vol;
2212 change = 1;
2213 }
2214 vol = u->value.integer.value[1];
2215 if (vol != rme96->vol[1] && vol <= maxvol) {
2216 rme96->vol[1] = vol;
2217 change = 1;
1da177e4 2218 }
4e98d6a7
TI		 2219 if (change)
2220 snd_rme96_apply_dac_volume(rme96);
1da177e4
LT		 2221 spin_unlock_irq(&rme96->lock);
2222
2223 return change;
2224}
2225
a3aefd88 2226static struct snd_kcontrol_new snd_rme96_controls[] = {
1da177e4
LT		 2227{
2228 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2229 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2230 .info = snd_rme96_control_spdif_info,
2231 .get = snd_rme96_control_spdif_get,
2232 .put = snd_rme96_control_spdif_put
2233},
2234{
2235 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
2236 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2237 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2238 .info = snd_rme96_control_spdif_stream_info,
2239 .get = snd_rme96_control_spdif_stream_get,
2240 .put = snd_rme96_control_spdif_stream_put
2241},
2242{
2243 .access = SNDRV_CTL_ELEM_ACCESS_READ,
67ed4161 2244 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1da177e4
LT		 2245 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
2246 .info = snd_rme96_control_spdif_mask_info,
2247 .get = snd_rme96_control_spdif_mask_get,
2248 .private_value = IEC958_AES0_NONAUDIO |
2249 IEC958_AES0_PROFESSIONAL |
2250 IEC958_AES0_CON_EMPHASIS
2251},
2252{
2253 .access = SNDRV_CTL_ELEM_ACCESS_READ,
67ed4161 2254 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1da177e4
LT		 2255 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
2256 .info = snd_rme96_control_spdif_mask_info,
2257 .get = snd_rme96_control_spdif_mask_get,
2258 .private_value = IEC958_AES0_NONAUDIO |
2259 IEC958_AES0_PROFESSIONAL |
2260 IEC958_AES0_PRO_EMPHASIS
2261},
2262{
2263 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2264 .name = "Input Connector",
2265 .info = snd_rme96_info_inputtype_control,
2266 .get = snd_rme96_get_inputtype_control,
2267 .put = snd_rme96_put_inputtype_control
2268},
2269{
2270 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2271 .name = "Loopback Input",
2272 .info = snd_rme96_info_loopback_control,
2273 .get = snd_rme96_get_loopback_control,
2274 .put = snd_rme96_put_loopback_control
2275},
2276{
2277 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2278 .name = "Sample Clock Source",
2279 .info = snd_rme96_info_clockmode_control,
2280 .get = snd_rme96_get_clockmode_control,
2281 .put = snd_rme96_put_clockmode_control
2282},
2283{
2284 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2285 .name = "Monitor Tracks",
2286 .info = snd_rme96_info_montracks_control,
2287 .get = snd_rme96_get_montracks_control,
2288 .put = snd_rme96_put_montracks_control
2289},
2290{
2291 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2292 .name = "Attenuation",
2293 .info = snd_rme96_info_attenuation_control,
2294 .get = snd_rme96_get_attenuation_control,
2295 .put = snd_rme96_put_attenuation_control
2296},
2297{
2298 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2299 .name = "DAC Playback Volume",
2300 .info = snd_rme96_dac_volume_info,
2301 .get = snd_rme96_dac_volume_get,
2302 .put = snd_rme96_dac_volume_put
2303}
2304};
2305
2306static int
a3aefd88
TI		 2307snd_rme96_create_switches(struct snd_card *card,
2308 struct rme96 *rme96)
1da177e4
LT		 2309{
2310 int idx, err;
a3aefd88 2311 struct snd_kcontrol *kctl;
1da177e4
LT		 2312
2313 for (idx = 0; idx < 7; idx++) {
2314 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_rme96_controls[idx], rme96))) < 0)
2315 return err;
2316 if (idx == 1) /* IEC958 (S/PDIF) Stream */
2317 rme96->spdif_ctl = kctl;
2318 }
2319
2320 if (RME96_HAS_ANALOG_OUT(rme96)) {
2321 for (idx = 7; idx < 10; idx++)
2322 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_rme96_controls[idx], rme96))) < 0)
2323 return err;
2324 }
2325
2326 return 0;
2327}
2328
2329/*
2330 * Card initialisation
2331 */
2332
a3aefd88 2333static void snd_rme96_card_free(struct snd_card *card)
1da177e4
LT		 2334{
2335 snd_rme96_free(card->private_data);
2336}
2337
e23e7a14 2338static int
1da177e4
LT		 2339snd_rme96_probe(struct pci_dev *pci,
2340 const struct pci_device_id *pci_id)
2341{
2342 static int dev;
a3aefd88
TI		 2343 struct rme96 *rme96;
2344 struct snd_card *card;
1da177e4
LT		 2345 int err;
2346 u8 val;
2347
2348 if (dev >= SNDRV_CARDS) {
2349 return -ENODEV;
2350 }
2351 if (!enable[dev]) {
2352 dev++;
2353 return -ENOENT;
2354 }
e58de7ba
TI		 2355 err = snd_card_create(index[dev], id[dev], THIS_MODULE,
2356 sizeof(struct rme96), &card);
2357 if (err < 0)
2358 return err;
1da177e4 2359 card->private_free = snd_rme96_card_free;
9fe856e4 2360 rme96 = card->private_data;
1da177e4
LT		 2361 rme96->card = card;
2362 rme96->pci = pci;
2363 snd_card_set_dev(card, &pci->dev);
2364 if ((err = snd_rme96_create(rme96)) < 0) {
2365 snd_card_free(card);
2366 return err;
2367 }
2368
2369 strcpy(card->driver, "Digi96");
2370 switch (rme96->pci->device) {
8b7fc421 2371 case PCI_DEVICE_ID_RME_DIGI96:
1da177e4
LT		 2372 strcpy(card->shortname, "RME Digi96");
2373 break;
8b7fc421 2374 case PCI_DEVICE_ID_RME_DIGI96_8:
1da177e4
LT		 2375 strcpy(card->shortname, "RME Digi96/8");
2376 break;
8b7fc421 2377 case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
1da177e4
LT		 2378 strcpy(card->shortname, "RME Digi96/8 PRO");
2379 break;
8b7fc421 2380 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
1da177e4
LT		 2381 pci_read_config_byte(rme96->pci, 8, &val);
2382 if (val < 5) {
2383 strcpy(card->shortname, "RME Digi96/8 PAD");
2384 } else {
2385 strcpy(card->shortname, "RME Digi96/8 PST");
2386 }
2387 break;
2388 }
2389 sprintf(card->longname, "%s at 0x%lx, irq %d", card->shortname,
2390 rme96->port, rme96->irq);
2391
2392 if ((err = snd_card_register(card)) < 0) {
2393 snd_card_free(card);
2394 return err;
2395 }
2396 pci_set_drvdata(pci, card);
2397 dev++;
2398 return 0;
2399}
2400
e23e7a14 2401static void snd_rme96_remove(struct pci_dev *pci)
1da177e4
LT		 2402{
2403 snd_card_free(pci_get_drvdata(pci));
2404 pci_set_drvdata(pci, NULL);
2405}
2406
e9f66d9b 2407static struct pci_driver rme96_driver = {
3733e424 2408 .name = KBUILD_MODNAME,
1da177e4
LT		 2409 .id_table = snd_rme96_ids,
2410 .probe = snd_rme96_probe,
e23e7a14 2411 .remove = snd_rme96_remove,
1da177e4
LT		 2412};
2413
e9f66d9b 2414module_pci_driver(rme96_driver);
kernel source for telekom puls (alcatel/mediatek)