include/linux/dw_dmac.h

   1 /*
   2  * Driver for the Synopsys DesignWare DMA Controller (aka DMACA on
   3  * AVR32 systems.)
   4  *
   5  * Copyright (C) 2007 Atmel Corporation
   6  * Copyright (C) 2010-2011 ST Microelectronics
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12 #ifndef DW_DMAC_H
  13 #define DW_DMAC_H
  14
  15 #include <linux/dmaengine.h>
  16
  17 /**
  18  * struct dw_dma_slave - Controller-specific information about a slave
  19  *
  20  * @dma_dev: required DMA master device. Depricated.
  21  * @bus_id: name of this device channel, not just a device name since
  22  *          devices may have more than one channel e.g. "foo_tx"
  23  * @cfg_hi: Platform-specific initializer for the CFG_HI register
  24  * @cfg_lo: Platform-specific initializer for the CFG_LO register
  25  * @src_master: src master for transfers on allocated channel.
  26  * @dst_master: dest master for transfers on allocated channel.
  27  */
  28 struct dw_dma_slave {
  29         struct device           *dma_dev;
  30         u32                     cfg_hi;
  31         u32                     cfg_lo;
  32         u8                      src_master;
  33         u8                      dst_master;
  34 };
  35
  36 /**
  37  * struct dw_dma_platform_data - Controller configuration parameters
  38  * @nr_channels: Number of channels supported by hardware (max 8)
  39  * @is_private: The device channels should be marked as private and not for
  40  *      by the general purpose DMA channel allocator.
  41  * @chan_allocation_order: Allocate channels starting from 0 or 7
  42  * @chan_priority: Set channel priority increasing from 0 to 7 or 7 to 0.
  43  * @block_size: Maximum block size supported by the controller
  44  * @nr_masters: Number of AHB masters supported by the controller
  45  * @data_width: Maximum data width supported by hardware per AHB master
  46  *              (0 - 8bits, 1 - 16bits, ..., 5 - 256bits)
  47  * @sd: slave specific data. Used for configuring channels
  48  * @sd_count: count of slave data structures passed.
  49  */
  50 struct dw_dma_platform_data {
  51         unsigned int    nr_channels;
  52         bool            is_private;
  53 #define CHAN_ALLOCATION_ASCENDING       0       /* zero to seven */
  54 #define CHAN_ALLOCATION_DESCENDING      1       /* seven to zero */
  55         unsigned char   chan_allocation_order;
  56 #define CHAN_PRIORITY_ASCENDING         0       /* chan0 highest */
  57 #define CHAN_PRIORITY_DESCENDING        1       /* chan7 highest */
  58         unsigned char   chan_priority;
  59         unsigned short  block_size;
  60         unsigned char   nr_masters;
  61         unsigned char   data_width[4];
  62 };
  63
  64 /* bursts size */
  65 enum dw_dma_msize {
  66         DW_DMA_MSIZE_1,
  67         DW_DMA_MSIZE_4,
  68         DW_DMA_MSIZE_8,
  69         DW_DMA_MSIZE_16,
  70         DW_DMA_MSIZE_32,
  71         DW_DMA_MSIZE_64,
  72         DW_DMA_MSIZE_128,
  73         DW_DMA_MSIZE_256,
  74 };
  75
  76 /* Platform-configurable bits in CFG_HI */
  77 #define DWC_CFGH_FCMODE         (1 << 0)
  78 #define DWC_CFGH_FIFO_MODE      (1 << 1)
  79 #define DWC_CFGH_PROTCTL(x)     ((x) << 2)
  80 #define DWC_CFGH_SRC_PER(x)     ((x) << 7)
  81 #define DWC_CFGH_DST_PER(x)     ((x) << 11)
  82
  83 /* Platform-configurable bits in CFG_LO */
  84 #define DWC_CFGL_LOCK_CH_XFER   (0 << 12)       /* scope of LOCK_CH */
  85 #define DWC_CFGL_LOCK_CH_BLOCK  (1 << 12)
  86 #define DWC_CFGL_LOCK_CH_XACT   (2 << 12)
  87 #define DWC_CFGL_LOCK_BUS_XFER  (0 << 14)       /* scope of LOCK_BUS */
  88 #define DWC_CFGL_LOCK_BUS_BLOCK (1 << 14)
  89 #define DWC_CFGL_LOCK_BUS_XACT  (2 << 14)
  90 #define DWC_CFGL_LOCK_CH        (1 << 15)       /* channel lockout */
  91 #define DWC_CFGL_LOCK_BUS       (1 << 16)       /* busmaster lockout */
  92 #define DWC_CFGL_HS_DST_POL     (1 << 18)       /* dst handshake active low */
  93 #define DWC_CFGL_HS_SRC_POL     (1 << 19)       /* src handshake active low */
  94
  95 /* DMA API extensions */
  96 struct dw_cyclic_desc {
  97         struct dw_desc  **desc;
  98         unsigned long   periods;
  99         void            (*period_callback)(void *param);
 100         void            *period_callback_param;
 101 };
 102
 103 struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
 104                 dma_addr_t buf_addr, size_t buf_len, size_t period_len,
 105                 enum dma_transfer_direction direction);
 106 void dw_dma_cyclic_free(struct dma_chan *chan);
 107 int dw_dma_cyclic_start(struct dma_chan *chan);
 108 void dw_dma_cyclic_stop(struct dma_chan *chan);
 109
 110 dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan);
 111
 112 dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan);
 113
 114 #endif /* DW_DMAC_H */